ARMCodeEmitter.cpp revision 5cdede43e92a370130fddde2ff071c74ea463448 
1//===-- ARM/ARMCodeEmitter.cpp - Convert ARM code to machine code ---------===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file contains the pass that transforms the ARM machine instructions into
11// relocatable machine code.
12//
13//===----------------------------------------------------------------------===//
14
15#define DEBUG_TYPE "jit"
16#include "ARM.h"
17#include "ARMAddressingModes.h"
18#include "ARMConstantPoolValue.h"
19#include "ARMInstrInfo.h"
20#include "ARMRelocations.h"
21#include "ARMSubtarget.h"
22#include "ARMTargetMachine.h"
23#include "llvm/Constants.h"
24#include "llvm/DerivedTypes.h"
25#include "llvm/Function.h"
26#include "llvm/PassManager.h"
27#include "llvm/CodeGen/JITCodeEmitter.h"
28#include "llvm/CodeGen/MachineConstantPool.h"
29#include "llvm/CodeGen/MachineFunctionPass.h"
30#include "llvm/CodeGen/MachineInstr.h"
31#include "llvm/CodeGen/MachineJumpTableInfo.h"
32#include "llvm/CodeGen/MachineModuleInfo.h"
33#include "llvm/CodeGen/Passes.h"
34#include "llvm/ADT/Statistic.h"
35#include "llvm/Support/Debug.h"
36#include "llvm/Support/ErrorHandling.h"
37#include "llvm/Support/raw_ostream.h"
38#ifndef NDEBUG
39#include <iomanip>
40#endif
41using namespace llvm;
42
43STATISTIC(NumEmitted, "Number of machine instructions emitted");
44
45namespace {
46
47  class ARMCodeEmitter : public MachineFunctionPass {
48    ARMJITInfo                *JTI;
49    const ARMInstrInfo        *II;
50    const TargetData          *TD;
51    const ARMSubtarget        *Subtarget;
52    TargetMachine             &TM;
53    JITCodeEmitter            &MCE;
54    MachineModuleInfo *MMI;
55    const std::vector<MachineConstantPoolEntry> *MCPEs;
56    const std::vector<MachineJumpTableEntry> *MJTEs;
57    bool IsPIC;
58    bool IsThumb;
59
60    void getAnalysisUsage(AnalysisUsage &AU) const {
61      AU.addRequired<MachineModuleInfo>();
62      MachineFunctionPass::getAnalysisUsage(AU);
63    }
64
65    static char ID;
66  public:
67    ARMCodeEmitter(TargetMachine &tm, JITCodeEmitter &mce)
68      : MachineFunctionPass(&ID), JTI(0),
69        II((const ARMInstrInfo *)tm.getInstrInfo()),
70        TD(tm.getTargetData()), TM(tm),
71        MCE(mce), MCPEs(0), MJTEs(0),
72        IsPIC(TM.getRelocationModel() == Reloc::PIC_), IsThumb(false) {}
73
74    /// getBinaryCodeForInstr - This function, generated by the
75    /// CodeEmitterGenerator using TableGen, produces the binary encoding for
76    /// machine instructions.
77    unsigned getBinaryCodeForInstr(const MachineInstr &MI);
78
79    bool runOnMachineFunction(MachineFunction &MF);
80
81    virtual const char *getPassName() const {
82      return "ARM Machine Code Emitter";
83    }
84
85    void emitInstruction(const MachineInstr &MI);
86
87  private:
88
89    void emitWordLE(unsigned Binary);
90    void emitDWordLE(uint64_t Binary);
91    void emitConstPoolInstruction(const MachineInstr &MI);
92    void emitMOVi32immInstruction(const MachineInstr &MI);
93    void emitMOVi2piecesInstruction(const MachineInstr &MI);
94    void emitLEApcrelJTInstruction(const MachineInstr &MI);
95    void emitPseudoMoveInstruction(const MachineInstr &MI);
96    void addPCLabel(unsigned LabelID);
97    void emitPseudoInstruction(const MachineInstr &MI);
98    unsigned getMachineSoRegOpValue(const MachineInstr &MI,
99                                    const TargetInstrDesc &TID,
100                                    const MachineOperand &MO,
101                                    unsigned OpIdx);
102
103    unsigned getMachineSoImmOpValue(unsigned SoImm);
104
105    unsigned getAddrModeSBit(const MachineInstr &MI,
106                             const TargetInstrDesc &TID) const;
107
108    void emitDataProcessingInstruction(const MachineInstr &MI,
109                                       unsigned ImplicitRd = 0,
110                                       unsigned ImplicitRn = 0);
111
112    void emitLoadStoreInstruction(const MachineInstr &MI,
113                                  unsigned ImplicitRd = 0,
114                                  unsigned ImplicitRn = 0);
115
116    void emitMiscLoadStoreInstruction(const MachineInstr &MI,
117                                      unsigned ImplicitRn = 0);
118
119    void emitLoadStoreMultipleInstruction(const MachineInstr &MI);
120
121    void emitMulFrmInstruction(const MachineInstr &MI);
122
123    void emitExtendInstruction(const MachineInstr &MI);
124
125    void emitMiscArithInstruction(const MachineInstr &MI);
126
127    void emitBranchInstruction(const MachineInstr &MI);
128
129    void emitInlineJumpTable(unsigned JTIndex);
130
131    void emitMiscBranchInstruction(const MachineInstr &MI);
132
133    void emitVFPArithInstruction(const MachineInstr &MI);
134
135    void emitVFPConversionInstruction(const MachineInstr &MI);
136
137    void emitVFPLoadStoreInstruction(const MachineInstr &MI);
138
139    void emitVFPLoadStoreMultipleInstruction(const MachineInstr &MI);
140
141    void emitMiscInstruction(const MachineInstr &MI);
142
143    void emitNEONGetLaneInstruction(const MachineInstr &MI);
144    void emitNEON1RegModImmInstruction(const MachineInstr &MI);
145    void emitNEON2RegInstruction(const MachineInstr &MI);
146    void emitNEON3RegInstruction(const MachineInstr &MI);
147
148    /// getMachineOpValue - Return binary encoding of operand. If the machine
149    /// operand requires relocation, record the relocation and return zero.
150    unsigned getMachineOpValue(const MachineInstr &MI,const MachineOperand &MO);
151    unsigned getMachineOpValue(const MachineInstr &MI, unsigned OpIdx) {
152      return getMachineOpValue(MI, MI.getOperand(OpIdx));
153    }
154
155    /// getMovi32Value - Return binary encoding of operand for movw/movt. If the
156    /// machine operand requires relocation, record the relocation and return
157    /// zero.
158    unsigned getMovi32Value(const MachineInstr &MI,const MachineOperand &MO,
159                            unsigned Reloc);
160    unsigned getMovi32Value(const MachineInstr &MI, unsigned OpIdx,
161                            unsigned Reloc) {
162      return getMovi32Value(MI, MI.getOperand(OpIdx), Reloc);
163    }
164
165    /// getShiftOp - Return the shift opcode (bit[6:5]) of the immediate value.
166    ///
167    unsigned getShiftOp(unsigned Imm) const ;
168
169    /// Routines that handle operands which add machine relocations which are
170    /// fixed up by the relocation stage.
171    void emitGlobalAddress(const GlobalValue *GV, unsigned Reloc,
172                           bool MayNeedFarStub,  bool Indirect,
173                           intptr_t ACPV = 0);
174    void emitExternalSymbolAddress(const char *ES, unsigned Reloc);
175    void emitConstPoolAddress(unsigned CPI, unsigned Reloc);
176    void emitJumpTableAddress(unsigned JTIndex, unsigned Reloc);
177    void emitMachineBasicBlock(MachineBasicBlock *BB, unsigned Reloc,
178                               intptr_t JTBase = 0);
179  };
180}
181
182char ARMCodeEmitter::ID = 0;
183
184/// createARMJITCodeEmitterPass - Return a pass that emits the collected ARM
185/// code to the specified MCE object.
186FunctionPass *llvm::createARMJITCodeEmitterPass(ARMBaseTargetMachine &TM,
187                                                JITCodeEmitter &JCE) {
188  return new ARMCodeEmitter(TM, JCE);
189}
190
191bool ARMCodeEmitter::runOnMachineFunction(MachineFunction &MF) {
192  assert((MF.getTarget().getRelocationModel() != Reloc::Default ||
193          MF.getTarget().getRelocationModel() != Reloc::Static) &&
194         "JIT relocation model must be set to static or default!");
195  JTI = ((ARMTargetMachine &)MF.getTarget()).getJITInfo();
196  II = ((const ARMTargetMachine &)MF.getTarget()).getInstrInfo();
197  TD = ((const ARMTargetMachine &)MF.getTarget()).getTargetData();
198  Subtarget = &TM.getSubtarget<ARMSubtarget>();
199  MCPEs = &MF.getConstantPool()->getConstants();
200  MJTEs = 0;
201  if (MF.getJumpTableInfo()) MJTEs = &MF.getJumpTableInfo()->getJumpTables();
202  IsPIC = TM.getRelocationModel() == Reloc::PIC_;
203  IsThumb = MF.getInfo<ARMFunctionInfo>()->isThumbFunction();
204  JTI->Initialize(MF, IsPIC);
205  MMI = &getAnalysis<MachineModuleInfo>();
206  MCE.setModuleInfo(MMI);
207
208  do {
209    DEBUG(errs() << "JITTing function '"
210          << MF.getFunction()->getName() << "'\n");
211    MCE.startFunction(MF);
212    for (MachineFunction::iterator MBB = MF.begin(), E = MF.end();
213         MBB != E; ++MBB) {
214      MCE.StartMachineBasicBlock(MBB);
215      for (MachineBasicBlock::const_iterator I = MBB->begin(), E = MBB->end();
216           I != E; ++I)
217        emitInstruction(*I);
218    }
219  } while (MCE.finishFunction(MF));
220
221  return false;
222}
223
224/// getShiftOp - Return the shift opcode (bit[6:5]) of the immediate value.
225///
226unsigned ARMCodeEmitter::getShiftOp(unsigned Imm) const {
227  switch (ARM_AM::getAM2ShiftOpc(Imm)) {
228  default: llvm_unreachable("Unknown shift opc!");
229  case ARM_AM::asr: return 2;
230  case ARM_AM::lsl: return 0;
231  case ARM_AM::lsr: return 1;
232  case ARM_AM::ror:
233  case ARM_AM::rrx: return 3;
234  }
235  return 0;
236}
237
238/// getMovi32Value - Return binary encoding of operand for movw/movt. If the
239/// machine operand requires relocation, record the relocation and return zero.
240unsigned ARMCodeEmitter::getMovi32Value(const MachineInstr &MI,
241                                        const MachineOperand &MO,
242                                        unsigned Reloc) {
243  assert(((Reloc == ARM::reloc_arm_movt) || (Reloc == ARM::reloc_arm_movw))
244      && "Relocation to this function should be for movt or movw");
245
246  if (MO.isImm())
247    return static_cast<unsigned>(MO.getImm());
248  else if (MO.isGlobal())
249    emitGlobalAddress(MO.getGlobal(), Reloc, true, false);
250  else if (MO.isSymbol())
251    emitExternalSymbolAddress(MO.getSymbolName(), Reloc);
252  else if (MO.isMBB())
253    emitMachineBasicBlock(MO.getMBB(), Reloc);
254  else {
255#ifndef NDEBUG
256    errs() << MO;
257#endif
258    llvm_unreachable("Unsupported operand type for movw/movt");
259  }
260  return 0;
261}
262
263/// getMachineOpValue - Return binary encoding of operand. If the machine
264/// operand requires relocation, record the relocation and return zero.
265unsigned ARMCodeEmitter::getMachineOpValue(const MachineInstr &MI,
266                                           const MachineOperand &MO) {
267  if (MO.isReg())
268    return ARMRegisterInfo::getRegisterNumbering(MO.getReg());
269  else if (MO.isImm())
270    return static_cast<unsigned>(MO.getImm());
271  else if (MO.isGlobal())
272    emitGlobalAddress(MO.getGlobal(), ARM::reloc_arm_branch, true, false);
273  else if (MO.isSymbol())
274    emitExternalSymbolAddress(MO.getSymbolName(), ARM::reloc_arm_branch);
275  else if (MO.isCPI()) {
276    const TargetInstrDesc &TID = MI.getDesc();
277    // For VFP load, the immediate offset is multiplied by 4.
278    unsigned Reloc =  ((TID.TSFlags & ARMII::FormMask) == ARMII::VFPLdStFrm)
279      ? ARM::reloc_arm_vfp_cp_entry : ARM::reloc_arm_cp_entry;
280    emitConstPoolAddress(MO.getIndex(), Reloc);
281  } else if (MO.isJTI())
282    emitJumpTableAddress(MO.getIndex(), ARM::reloc_arm_relative);
283  else if (MO.isMBB())
284    emitMachineBasicBlock(MO.getMBB(), ARM::reloc_arm_branch);
285  else {
286#ifndef NDEBUG
287    errs() << MO;
288#endif
289    llvm_unreachable(0);
290  }
291  return 0;
292}
293
294/// emitGlobalAddress - Emit the specified address to the code stream.
295///
296void ARMCodeEmitter::emitGlobalAddress(const GlobalValue *GV, unsigned Reloc,
297                                       bool MayNeedFarStub, bool Indirect,
298                                       intptr_t ACPV) {
299  MachineRelocation MR = Indirect
300    ? MachineRelocation::getIndirectSymbol(MCE.getCurrentPCOffset(), Reloc,
301                                           const_cast<GlobalValue *>(GV),
302                                           ACPV, MayNeedFarStub)
303    : MachineRelocation::getGV(MCE.getCurrentPCOffset(), Reloc,
304                               const_cast<GlobalValue *>(GV), ACPV,
305                               MayNeedFarStub);
306  MCE.addRelocation(MR);
307}
308
309/// emitExternalSymbolAddress - Arrange for the address of an external symbol to
310/// be emitted to the current location in the function, and allow it to be PC
311/// relative.
312void ARMCodeEmitter::emitExternalSymbolAddress(const char *ES, unsigned Reloc) {
313  MCE.addRelocation(MachineRelocation::getExtSym(MCE.getCurrentPCOffset(),
314                                                 Reloc, ES));
315}
316
317/// emitConstPoolAddress - Arrange for the address of an constant pool
318/// to be emitted to the current location in the function, and allow it to be PC
319/// relative.
320void ARMCodeEmitter::emitConstPoolAddress(unsigned CPI, unsigned Reloc) {
321  // Tell JIT emitter we'll resolve the address.
322  MCE.addRelocation(MachineRelocation::getConstPool(MCE.getCurrentPCOffset(),
323                                                    Reloc, CPI, 0, true));
324}
325
326/// emitJumpTableAddress - Arrange for the address of a jump table to
327/// be emitted to the current location in the function, and allow it to be PC
328/// relative.
329void ARMCodeEmitter::emitJumpTableAddress(unsigned JTIndex, unsigned Reloc) {
330  MCE.addRelocation(MachineRelocation::getJumpTable(MCE.getCurrentPCOffset(),
331                                                    Reloc, JTIndex, 0, true));
332}
333
334/// emitMachineBasicBlock - Emit the specified address basic block.
335void ARMCodeEmitter::emitMachineBasicBlock(MachineBasicBlock *BB,
336                                           unsigned Reloc, intptr_t JTBase) {
337  MCE.addRelocation(MachineRelocation::getBB(MCE.getCurrentPCOffset(),
338                                             Reloc, BB, JTBase));
339}
340
341void ARMCodeEmitter::emitWordLE(unsigned Binary) {
342  DEBUG(errs() << "  0x";
343        errs().write_hex(Binary) << "\n");
344  MCE.emitWordLE(Binary);
345}
346
347void ARMCodeEmitter::emitDWordLE(uint64_t Binary) {
348  DEBUG(errs() << "  0x";
349        errs().write_hex(Binary) << "\n");
350  MCE.emitDWordLE(Binary);
351}
352
353void ARMCodeEmitter::emitInstruction(const MachineInstr &MI) {
354  DEBUG(errs() << "JIT: " << (void*)MCE.getCurrentPCValue() << ":\t" << MI);
355
356  MCE.processDebugLoc(MI.getDebugLoc(), true);
357
358  ++NumEmitted;  // Keep track of the # of mi's emitted
359  switch (MI.getDesc().TSFlags & ARMII::FormMask) {
360  default: {
361    llvm_unreachable("Unhandled instruction encoding format!");
362    break;
363  }
364  case ARMII::Pseudo:
365    emitPseudoInstruction(MI);
366    break;
367  case ARMII::DPFrm:
368  case ARMII::DPSoRegFrm:
369    emitDataProcessingInstruction(MI);
370    break;
371  case ARMII::LdFrm:
372  case ARMII::StFrm:
373    emitLoadStoreInstruction(MI);
374    break;
375  case ARMII::LdMiscFrm:
376  case ARMII::StMiscFrm:
377    emitMiscLoadStoreInstruction(MI);
378    break;
379  case ARMII::LdStMulFrm:
380    emitLoadStoreMultipleInstruction(MI);
381    break;
382  case ARMII::MulFrm:
383    emitMulFrmInstruction(MI);
384    break;
385  case ARMII::ExtFrm:
386    emitExtendInstruction(MI);
387    break;
388  case ARMII::ArithMiscFrm:
389    emitMiscArithInstruction(MI);
390    break;
391  case ARMII::BrFrm:
392    emitBranchInstruction(MI);
393    break;
394  case ARMII::BrMiscFrm:
395    emitMiscBranchInstruction(MI);
396    break;
397  // VFP instructions.
398  case ARMII::VFPUnaryFrm:
399  case ARMII::VFPBinaryFrm:
400    emitVFPArithInstruction(MI);
401    break;
402  case ARMII::VFPConv1Frm:
403  case ARMII::VFPConv2Frm:
404  case ARMII::VFPConv3Frm:
405  case ARMII::VFPConv4Frm:
406  case ARMII::VFPConv5Frm:
407    emitVFPConversionInstruction(MI);
408    break;
409  case ARMII::VFPLdStFrm:
410    emitVFPLoadStoreInstruction(MI);
411    break;
412  case ARMII::VFPLdStMulFrm:
413    emitVFPLoadStoreMultipleInstruction(MI);
414    break;
415  case ARMII::VFPMiscFrm:
416    emitMiscInstruction(MI);
417    break;
418  // NEON instructions.
419  case ARMII::NGetLnFrm:
420    emitNEONGetLaneInstruction(MI);
421    break;
422  case ARMII::N1RegModImmFrm:
423    emitNEON1RegModImmInstruction(MI);
424    break;
425  case ARMII::N2RegFrm:
426    emitNEON2RegInstruction(MI);
427    break;
428  case ARMII::N3RegFrm:
429    emitNEON3RegInstruction(MI);
430    break;
431  }
432  MCE.processDebugLoc(MI.getDebugLoc(), false);
433}
434
435void ARMCodeEmitter::emitConstPoolInstruction(const MachineInstr &MI) {
436  unsigned CPI = MI.getOperand(0).getImm();       // CP instruction index.
437  unsigned CPIndex = MI.getOperand(1).getIndex(); // Actual cp entry index.
438  const MachineConstantPoolEntry &MCPE = (*MCPEs)[CPIndex];
439
440  // Remember the CONSTPOOL_ENTRY address for later relocation.
441  JTI->addConstantPoolEntryAddr(CPI, MCE.getCurrentPCValue());
442
443  // Emit constpool island entry. In most cases, the actual values will be
444  // resolved and relocated after code emission.
445  if (MCPE.isMachineConstantPoolEntry()) {
446    ARMConstantPoolValue *ACPV =
447      static_cast<ARMConstantPoolValue*>(MCPE.Val.MachineCPVal);
448
449    DEBUG(errs() << "  ** ARM constant pool #" << CPI << " @ "
450          << (void*)MCE.getCurrentPCValue() << " " << *ACPV << '\n');
451
452    assert(ACPV->isGlobalValue() && "unsupported constant pool value");
453    const GlobalValue *GV = ACPV->getGV();
454    if (GV) {
455      Reloc::Model RelocM = TM.getRelocationModel();
456      emitGlobalAddress(GV, ARM::reloc_arm_machine_cp_entry,
457                        isa<Function>(GV),
458                        Subtarget->GVIsIndirectSymbol(GV, RelocM),
459                        (intptr_t)ACPV);
460     } else  {
461      emitExternalSymbolAddress(ACPV->getSymbol(), ARM::reloc_arm_absolute);
462    }
463    emitWordLE(0);
464  } else {
465    const Constant *CV = MCPE.Val.ConstVal;
466
467    DEBUG({
468        errs() << "  ** Constant pool #" << CPI << " @ "
469               << (void*)MCE.getCurrentPCValue() << " ";
470        if (const Function *F = dyn_cast<Function>(CV))
471          errs() << F->getName();
472        else
473          errs() << *CV;
474        errs() << '\n';
475      });
476
477    if (const GlobalValue *GV = dyn_cast<GlobalValue>(CV)) {
478      emitGlobalAddress(GV, ARM::reloc_arm_absolute, isa<Function>(GV), false);
479      emitWordLE(0);
480    } else if (const ConstantInt *CI = dyn_cast<ConstantInt>(CV)) {
481      uint32_t Val = *(uint32_t*)CI->getValue().getRawData();
482      emitWordLE(Val);
483    } else if (const ConstantFP *CFP = dyn_cast<ConstantFP>(CV)) {
484      if (CFP->getType()->isFloatTy())
485        emitWordLE(CFP->getValueAPF().bitcastToAPInt().getZExtValue());
486      else if (CFP->getType()->isDoubleTy())
487        emitDWordLE(CFP->getValueAPF().bitcastToAPInt().getZExtValue());
488      else {
489        llvm_unreachable("Unable to handle this constantpool entry!");
490      }
491    } else {
492      llvm_unreachable("Unable to handle this constantpool entry!");
493    }
494  }
495}
496
497void ARMCodeEmitter::emitMOVi32immInstruction(const MachineInstr &MI) {
498  const MachineOperand &MO0 = MI.getOperand(0);
499  const MachineOperand &MO1 = MI.getOperand(1);
500
501  // Emit the 'movw' instruction.
502  unsigned Binary = 0x30 << 20;  // mov: Insts{27-20} = 0b00110000
503
504  unsigned Lo16 = getMovi32Value(MI, MO1, ARM::reloc_arm_movw) & 0xFFFF;
505
506  // Set the conditional execution predicate.
507  Binary |= II->getPredicate(&MI) << ARMII::CondShift;
508
509  // Encode Rd.
510  Binary |= getMachineOpValue(MI, MO0) << ARMII::RegRdShift;
511
512  // Encode imm16 as imm4:imm12
513  Binary |= Lo16 & 0xFFF; // Insts{11-0} = imm12
514  Binary |= ((Lo16 >> 12) & 0xF) << 16; // Insts{19-16} = imm4
515  emitWordLE(Binary);
516
517  unsigned Hi16 = getMovi32Value(MI, MO1, ARM::reloc_arm_movt) >> 16;
518  // Emit the 'movt' instruction.
519  Binary = 0x34 << 20; // movt: Insts{27-20} = 0b00110100
520
521  // Set the conditional execution predicate.
522  Binary |= II->getPredicate(&MI) << ARMII::CondShift;
523
524  // Encode Rd.
525  Binary |= getMachineOpValue(MI, MO0) << ARMII::RegRdShift;
526
527  // Encode imm16 as imm4:imm1, same as movw above.
528  Binary |= Hi16 & 0xFFF;
529  Binary |= ((Hi16 >> 12) & 0xF) << 16;
530  emitWordLE(Binary);
531}
532
533void ARMCodeEmitter::emitMOVi2piecesInstruction(const MachineInstr &MI) {
534  const MachineOperand &MO0 = MI.getOperand(0);
535  const MachineOperand &MO1 = MI.getOperand(1);
536  assert(MO1.isImm() && ARM_AM::isSOImmTwoPartVal(MO1.getImm()) &&
537                                                  "Not a valid so_imm value!");
538  unsigned V1 = ARM_AM::getSOImmTwoPartFirst(MO1.getImm());
539  unsigned V2 = ARM_AM::getSOImmTwoPartSecond(MO1.getImm());
540
541  // Emit the 'mov' instruction.
542  unsigned Binary = 0xd << 21;  // mov: Insts{24-21} = 0b1101
543
544  // Set the conditional execution predicate.
545  Binary |= II->getPredicate(&MI) << ARMII::CondShift;
546
547  // Encode Rd.
548  Binary |= getMachineOpValue(MI, MO0) << ARMII::RegRdShift;
549
550  // Encode so_imm.
551  // Set bit I(25) to identify this is the immediate form of <shifter_op>
552  Binary |= 1 << ARMII::I_BitShift;
553  Binary |= getMachineSoImmOpValue(V1);
554  emitWordLE(Binary);
555
556  // Now the 'orr' instruction.
557  Binary = 0xc << 21;  // orr: Insts{24-21} = 0b1100
558
559  // Set the conditional execution predicate.
560  Binary |= II->getPredicate(&MI) << ARMII::CondShift;
561
562  // Encode Rd.
563  Binary |= getMachineOpValue(MI, MO0) << ARMII::RegRdShift;
564
565  // Encode Rn.
566  Binary |= getMachineOpValue(MI, MO0) << ARMII::RegRnShift;
567
568  // Encode so_imm.
569  // Set bit I(25) to identify this is the immediate form of <shifter_op>
570  Binary |= 1 << ARMII::I_BitShift;
571  Binary |= getMachineSoImmOpValue(V2);
572  emitWordLE(Binary);
573}
574
575void ARMCodeEmitter::emitLEApcrelJTInstruction(const MachineInstr &MI) {
576  // It's basically add r, pc, (LJTI - $+8)
577
578  const TargetInstrDesc &TID = MI.getDesc();
579
580  // Emit the 'add' instruction.
581  unsigned Binary = 0x4 << 21;  // add: Insts{24-31} = 0b0100
582
583  // Set the conditional execution predicate
584  Binary |= II->getPredicate(&MI) << ARMII::CondShift;
585
586  // Encode S bit if MI modifies CPSR.
587  Binary |= getAddrModeSBit(MI, TID);
588
589  // Encode Rd.
590  Binary |= getMachineOpValue(MI, 0) << ARMII::RegRdShift;
591
592  // Encode Rn which is PC.
593  Binary |= ARMRegisterInfo::getRegisterNumbering(ARM::PC) << ARMII::RegRnShift;
594
595  // Encode the displacement.
596  Binary |= 1 << ARMII::I_BitShift;
597  emitJumpTableAddress(MI.getOperand(1).getIndex(), ARM::reloc_arm_jt_base);
598
599  emitWordLE(Binary);
600}
601
602void ARMCodeEmitter::emitPseudoMoveInstruction(const MachineInstr &MI) {
603  unsigned Opcode = MI.getDesc().Opcode;
604
605  // Part of binary is determined by TableGn.
606  unsigned Binary = getBinaryCodeForInstr(MI);
607
608  // Set the conditional execution predicate
609  Binary |= II->getPredicate(&MI) << ARMII::CondShift;
610
611  // Encode S bit if MI modifies CPSR.
612  if (Opcode == ARM::MOVsrl_flag || Opcode == ARM::MOVsra_flag)
613    Binary |= 1 << ARMII::S_BitShift;
614
615  // Encode register def if there is one.
616  Binary |= getMachineOpValue(MI, 0) << ARMII::RegRdShift;
617
618  // Encode the shift operation.
619  switch (Opcode) {
620  default: break;
621  case ARM::MOVrx:
622    // rrx
623    Binary |= 0x6 << 4;
624    break;
625  case ARM::MOVsrl_flag:
626    // lsr #1
627    Binary |= (0x2 << 4) | (1 << 7);
628    break;
629  case ARM::MOVsra_flag:
630    // asr #1
631    Binary |= (0x4 << 4) | (1 << 7);
632    break;
633  }
634
635  // Encode register Rm.
636  Binary |= getMachineOpValue(MI, 1);
637
638  emitWordLE(Binary);
639}
640
641void ARMCodeEmitter::addPCLabel(unsigned LabelID) {
642  DEBUG(errs() << "  ** LPC" << LabelID << " @ "
643        << (void*)MCE.getCurrentPCValue() << '\n');
644  JTI->addPCLabelAddr(LabelID, MCE.getCurrentPCValue());
645}
646
647void ARMCodeEmitter::emitPseudoInstruction(const MachineInstr &MI) {
648  unsigned Opcode = MI.getDesc().Opcode;
649  switch (Opcode) {
650  default:
651    llvm_unreachable("ARMCodeEmitter::emitPseudoInstruction");
652  case TargetOpcode::INLINEASM: {
653    // We allow inline assembler nodes with empty bodies - they can
654    // implicitly define registers, which is ok for JIT.
655    if (MI.getOperand(0).getSymbolName()[0]) {
656      report_fatal_error("JIT does not support inline asm!");
657    }
658    break;
659  }
660  case TargetOpcode::DBG_LABEL:
661  case TargetOpcode::EH_LABEL:
662    MCE.emitLabel(MI.getOperand(0).getMCSymbol());
663    break;
664  case TargetOpcode::IMPLICIT_DEF:
665  case TargetOpcode::KILL:
666    // Do nothing.
667    break;
668  case ARM::CONSTPOOL_ENTRY:
669    emitConstPoolInstruction(MI);
670    break;
671  case ARM::PICADD: {
672    // Remember of the address of the PC label for relocation later.
673    addPCLabel(MI.getOperand(2).getImm());
674    // PICADD is just an add instruction that implicitly read pc.
675    emitDataProcessingInstruction(MI, 0, ARM::PC);
676    break;
677  }
678  case ARM::PICLDR:
679  case ARM::PICLDRB:
680  case ARM::PICSTR:
681  case ARM::PICSTRB: {
682    // Remember of the address of the PC label for relocation later.
683    addPCLabel(MI.getOperand(2).getImm());
684    // These are just load / store instructions that implicitly read pc.
685    emitLoadStoreInstruction(MI, 0, ARM::PC);
686    break;
687  }
688  case ARM::PICLDRH:
689  case ARM::PICLDRSH:
690  case ARM::PICLDRSB:
691  case ARM::PICSTRH: {
692    // Remember of the address of the PC label for relocation later.
693    addPCLabel(MI.getOperand(2).getImm());
694    // These are just load / store instructions that implicitly read pc.
695    emitMiscLoadStoreInstruction(MI, ARM::PC);
696    break;
697  }
698
699  case ARM::MOVi32imm:
700    emitMOVi32immInstruction(MI);
701    break;
702
703  case ARM::MOVi2pieces:
704    // Two instructions to materialize a constant.
705    emitMOVi2piecesInstruction(MI);
706    break;
707  case ARM::LEApcrelJT:
708    // Materialize jumptable address.
709    emitLEApcrelJTInstruction(MI);
710    break;
711  case ARM::MOVrx:
712  case ARM::MOVsrl_flag:
713  case ARM::MOVsra_flag:
714    emitPseudoMoveInstruction(MI);
715    break;
716  }
717}
718
719unsigned ARMCodeEmitter::getMachineSoRegOpValue(const MachineInstr &MI,
720                                                const TargetInstrDesc &TID,
721                                                const MachineOperand &MO,
722                                                unsigned OpIdx) {
723  unsigned Binary = getMachineOpValue(MI, MO);
724
725  const MachineOperand &MO1 = MI.getOperand(OpIdx + 1);
726  const MachineOperand &MO2 = MI.getOperand(OpIdx + 2);
727  ARM_AM::ShiftOpc SOpc = ARM_AM::getSORegShOp(MO2.getImm());
728
729  // Encode the shift opcode.
730  unsigned SBits = 0;
731  unsigned Rs = MO1.getReg();
732  if (Rs) {
733    // Set shift operand (bit[7:4]).
734    // LSL - 0001
735    // LSR - 0011
736    // ASR - 0101
737    // ROR - 0111
738    // RRX - 0110 and bit[11:8] clear.
739    switch (SOpc) {
740    default: llvm_unreachable("Unknown shift opc!");
741    case ARM_AM::lsl: SBits = 0x1; break;
742    case ARM_AM::lsr: SBits = 0x3; break;
743    case ARM_AM::asr: SBits = 0x5; break;
744    case ARM_AM::ror: SBits = 0x7; break;
745    case ARM_AM::rrx: SBits = 0x6; break;
746    }
747  } else {
748    // Set shift operand (bit[6:4]).
749    // LSL - 000
750    // LSR - 010
751    // ASR - 100
752    // ROR - 110
753    switch (SOpc) {
754    default: llvm_unreachable("Unknown shift opc!");
755    case ARM_AM::lsl: SBits = 0x0; break;
756    case ARM_AM::lsr: SBits = 0x2; break;
757    case ARM_AM::asr: SBits = 0x4; break;
758    case ARM_AM::ror: SBits = 0x6; break;
759    }
760  }
761  Binary |= SBits << 4;
762  if (SOpc == ARM_AM::rrx)
763    return Binary;
764
765  // Encode the shift operation Rs or shift_imm (except rrx).
766  if (Rs) {
767    // Encode Rs bit[11:8].
768    assert(ARM_AM::getSORegOffset(MO2.getImm()) == 0);
769    return Binary |
770      (ARMRegisterInfo::getRegisterNumbering(Rs) << ARMII::RegRsShift);
771  }
772
773  // Encode shift_imm bit[11:7].
774  return Binary | ARM_AM::getSORegOffset(MO2.getImm()) << 7;
775}
776
777unsigned ARMCodeEmitter::getMachineSoImmOpValue(unsigned SoImm) {
778  int SoImmVal = ARM_AM::getSOImmVal(SoImm);
779  assert(SoImmVal != -1 && "Not a valid so_imm value!");
780
781  // Encode rotate_imm.
782  unsigned Binary = (ARM_AM::getSOImmValRot((unsigned)SoImmVal) >> 1)
783    << ARMII::SoRotImmShift;
784
785  // Encode immed_8.
786  Binary |= ARM_AM::getSOImmValImm((unsigned)SoImmVal);
787  return Binary;
788}
789
790unsigned ARMCodeEmitter::getAddrModeSBit(const MachineInstr &MI,
791                                         const TargetInstrDesc &TID) const {
792  for (unsigned i = MI.getNumOperands(), e = TID.getNumOperands(); i != e; --i){
793    const MachineOperand &MO = MI.getOperand(i-1);
794    if (MO.isReg() && MO.isDef() && MO.getReg() == ARM::CPSR)
795      return 1 << ARMII::S_BitShift;
796  }
797  return 0;
798}
799
800void ARMCodeEmitter::emitDataProcessingInstruction(const MachineInstr &MI,
801                                                   unsigned ImplicitRd,
802                                                   unsigned ImplicitRn) {
803  const TargetInstrDesc &TID = MI.getDesc();
804
805  // Part of binary is determined by TableGn.
806  unsigned Binary = getBinaryCodeForInstr(MI);
807
808  // Set the conditional execution predicate
809  Binary |= II->getPredicate(&MI) << ARMII::CondShift;
810
811  // Encode S bit if MI modifies CPSR.
812  Binary |= getAddrModeSBit(MI, TID);
813
814  // Encode register def if there is one.
815  unsigned NumDefs = TID.getNumDefs();
816  unsigned OpIdx = 0;
817  if (NumDefs)
818    Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRdShift;
819  else if (ImplicitRd)
820    // Special handling for implicit use (e.g. PC).
821    Binary |= (ARMRegisterInfo::getRegisterNumbering(ImplicitRd)
822               << ARMII::RegRdShift);
823
824  if (TID.Opcode == ARM::MOVi16) {
825      // Get immediate from MI.
826      unsigned Lo16 = getMovi32Value(MI, MI.getOperand(OpIdx),
827                      ARM::reloc_arm_movw);
828      // Encode imm which is the same as in emitMOVi32immInstruction().
829      Binary |= Lo16 & 0xFFF;
830      Binary |= ((Lo16 >> 12) & 0xF) << 16;
831      emitWordLE(Binary);
832      return;
833  } else if(TID.Opcode == ARM::MOVTi16) {
834      unsigned Hi16 = (getMovi32Value(MI, MI.getOperand(OpIdx),
835                       ARM::reloc_arm_movt) >> 16);
836      Binary |= Hi16 & 0xFFF;
837      Binary |= ((Hi16 >> 12) & 0xF) << 16;
838      emitWordLE(Binary);
839      return;
840  } else if ((TID.Opcode == ARM::BFC) || (TID.Opcode == ARM::BFI)) {
841      uint32_t v = ~MI.getOperand(2).getImm();
842      int32_t lsb = CountTrailingZeros_32(v);
843      int32_t msb = (32 - CountLeadingZeros_32(v)) - 1;
844      // Instr{20-16} = msb, Instr{11-7} = lsb
845      Binary |= (msb & 0x1F) << 16;
846      Binary |= (lsb & 0x1F) << 7;
847      emitWordLE(Binary);
848      return;
849  } else if ((TID.Opcode == ARM::UBFX) || (TID.Opcode == ARM::SBFX)) {
850      // Encode Rn in Instr{0-3}
851      Binary |= getMachineOpValue(MI, OpIdx++);
852
853      uint32_t lsb = MI.getOperand(OpIdx++).getImm();
854      uint32_t widthm1 = MI.getOperand(OpIdx++).getImm() - 1;
855
856      // Instr{20-16} = widthm1, Instr{11-7} = lsb
857      Binary |= (widthm1 & 0x1F) << 16;
858      Binary |= (lsb & 0x1F) << 7;
859      emitWordLE(Binary);
860      return;
861  }
862
863  // If this is a two-address operand, skip it. e.g. MOVCCr operand 1.
864  if (TID.getOperandConstraint(OpIdx, TOI::TIED_TO) != -1)
865    ++OpIdx;
866
867  // Encode first non-shifter register operand if there is one.
868  bool isUnary = TID.TSFlags & ARMII::UnaryDP;
869  if (!isUnary) {
870    if (ImplicitRn)
871      // Special handling for implicit use (e.g. PC).
872      Binary |= (ARMRegisterInfo::getRegisterNumbering(ImplicitRn)
873                 << ARMII::RegRnShift);
874    else {
875      Binary |= getMachineOpValue(MI, OpIdx) << ARMII::RegRnShift;
876      ++OpIdx;
877    }
878  }
879
880  // Encode shifter operand.
881  const MachineOperand &MO = MI.getOperand(OpIdx);
882  if ((TID.TSFlags & ARMII::FormMask) == ARMII::DPSoRegFrm) {
883    // Encode SoReg.
884    emitWordLE(Binary | getMachineSoRegOpValue(MI, TID, MO, OpIdx));
885    return;
886  }
887
888  if (MO.isReg()) {
889    // Encode register Rm.
890    emitWordLE(Binary | ARMRegisterInfo::getRegisterNumbering(MO.getReg()));
891    return;
892  }
893
894  // Encode so_imm.
895  Binary |= getMachineSoImmOpValue((unsigned)MO.getImm());
896
897  emitWordLE(Binary);
898}
899
900void ARMCodeEmitter::emitLoadStoreInstruction(const MachineInstr &MI,
901                                              unsigned ImplicitRd,
902                                              unsigned ImplicitRn) {
903  const TargetInstrDesc &TID = MI.getDesc();
904  unsigned Form = TID.TSFlags & ARMII::FormMask;
905  bool IsPrePost = (TID.TSFlags & ARMII::IndexModeMask) != 0;
906
907  // Part of binary is determined by TableGn.
908  unsigned Binary = getBinaryCodeForInstr(MI);
909
910  // Set the conditional execution predicate
911  Binary |= II->getPredicate(&MI) << ARMII::CondShift;
912
913  unsigned OpIdx = 0;
914
915  // Operand 0 of a pre- and post-indexed store is the address base
916  // writeback. Skip it.
917  bool Skipped = false;
918  if (IsPrePost && Form == ARMII::StFrm) {
919    ++OpIdx;
920    Skipped = true;
921  }
922
923  // Set first operand
924  if (ImplicitRd)
925    // Special handling for implicit use (e.g. PC).
926    Binary |= (ARMRegisterInfo::getRegisterNumbering(ImplicitRd)
927               << ARMII::RegRdShift);
928  else
929    Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRdShift;
930
931  // Set second operand
932  if (ImplicitRn)
933    // Special handling for implicit use (e.g. PC).
934    Binary |= (ARMRegisterInfo::getRegisterNumbering(ImplicitRn)
935               << ARMII::RegRnShift);
936  else
937    Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRnShift;
938
939  // If this is a two-address operand, skip it. e.g. LDR_PRE.
940  if (!Skipped && TID.getOperandConstraint(OpIdx, TOI::TIED_TO) != -1)
941    ++OpIdx;
942
943  const MachineOperand &MO2 = MI.getOperand(OpIdx);
944  unsigned AM2Opc = (ImplicitRn == ARM::PC)
945    ? 0 : MI.getOperand(OpIdx+1).getImm();
946
947  // Set bit U(23) according to sign of immed value (positive or negative).
948  Binary |= ((ARM_AM::getAM2Op(AM2Opc) == ARM_AM::add ? 1 : 0) <<
949             ARMII::U_BitShift);
950  if (!MO2.getReg()) { // is immediate
951    if (ARM_AM::getAM2Offset(AM2Opc))
952      // Set the value of offset_12 field
953      Binary |= ARM_AM::getAM2Offset(AM2Opc);
954    emitWordLE(Binary);
955    return;
956  }
957
958  // Set bit I(25), because this is not in immediate enconding.
959  Binary |= 1 << ARMII::I_BitShift;
960  assert(TargetRegisterInfo::isPhysicalRegister(MO2.getReg()));
961  // Set bit[3:0] to the corresponding Rm register
962  Binary |= ARMRegisterInfo::getRegisterNumbering(MO2.getReg());
963
964  // If this instr is in scaled register offset/index instruction, set
965  // shift_immed(bit[11:7]) and shift(bit[6:5]) fields.
966  if (unsigned ShImm = ARM_AM::getAM2Offset(AM2Opc)) {
967    Binary |= getShiftOp(AM2Opc) << ARMII::ShiftImmShift;  // shift
968    Binary |= ShImm              << ARMII::ShiftShift;     // shift_immed
969  }
970
971  emitWordLE(Binary);
972}
973
974void ARMCodeEmitter::emitMiscLoadStoreInstruction(const MachineInstr &MI,
975                                                  unsigned ImplicitRn) {
976  const TargetInstrDesc &TID = MI.getDesc();
977  unsigned Form = TID.TSFlags & ARMII::FormMask;
978  bool IsPrePost = (TID.TSFlags & ARMII::IndexModeMask) != 0;
979
980  // Part of binary is determined by TableGn.
981  unsigned Binary = getBinaryCodeForInstr(MI);
982
983  // Set the conditional execution predicate
984  Binary |= II->getPredicate(&MI) << ARMII::CondShift;
985
986  unsigned OpIdx = 0;
987
988  // Operand 0 of a pre- and post-indexed store is the address base
989  // writeback. Skip it.
990  bool Skipped = false;
991  if (IsPrePost && Form == ARMII::StMiscFrm) {
992    ++OpIdx;
993    Skipped = true;
994  }
995
996  // Set first operand
997  Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRdShift;
998
999  // Skip LDRD and STRD's second operand.
1000  if (TID.Opcode == ARM::LDRD || TID.Opcode == ARM::STRD)
1001    ++OpIdx;
1002
1003  // Set second operand
1004  if (ImplicitRn)
1005    // Special handling for implicit use (e.g. PC).
1006    Binary |= (ARMRegisterInfo::getRegisterNumbering(ImplicitRn)
1007               << ARMII::RegRnShift);
1008  else
1009    Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRnShift;
1010
1011  // If this is a two-address operand, skip it. e.g. LDRH_POST.
1012  if (!Skipped && TID.getOperandConstraint(OpIdx, TOI::TIED_TO) != -1)
1013    ++OpIdx;
1014
1015  const MachineOperand &MO2 = MI.getOperand(OpIdx);
1016  unsigned AM3Opc = (ImplicitRn == ARM::PC)
1017    ? 0 : MI.getOperand(OpIdx+1).getImm();
1018
1019  // Set bit U(23) according to sign of immed value (positive or negative)
1020  Binary |= ((ARM_AM::getAM3Op(AM3Opc) == ARM_AM::add ? 1 : 0) <<
1021             ARMII::U_BitShift);
1022
1023  // If this instr is in register offset/index encoding, set bit[3:0]
1024  // to the corresponding Rm register.
1025  if (MO2.getReg()) {
1026    Binary |= ARMRegisterInfo::getRegisterNumbering(MO2.getReg());
1027    emitWordLE(Binary);
1028    return;
1029  }
1030
1031  // This instr is in immediate offset/index encoding, set bit 22 to 1.
1032  Binary |= 1 << ARMII::AM3_I_BitShift;
1033  if (unsigned ImmOffs = ARM_AM::getAM3Offset(AM3Opc)) {
1034    // Set operands
1035    Binary |= (ImmOffs >> 4) << ARMII::ImmHiShift;  // immedH
1036    Binary |= (ImmOffs & 0xF);                      // immedL
1037  }
1038
1039  emitWordLE(Binary);
1040}
1041
1042static unsigned getAddrModeUPBits(unsigned Mode) {
1043  unsigned Binary = 0;
1044
1045  // Set addressing mode by modifying bits U(23) and P(24)
1046  // IA - Increment after  - bit U = 1 and bit P = 0
1047  // IB - Increment before - bit U = 1 and bit P = 1
1048  // DA - Decrement after  - bit U = 0 and bit P = 0
1049  // DB - Decrement before - bit U = 0 and bit P = 1
1050  switch (Mode) {
1051  default: llvm_unreachable("Unknown addressing sub-mode!");
1052  case ARM_AM::da:                                     break;
1053  case ARM_AM::db: Binary |= 0x1 << ARMII::P_BitShift; break;
1054  case ARM_AM::ia: Binary |= 0x1 << ARMII::U_BitShift; break;
1055  case ARM_AM::ib: Binary |= 0x3 << ARMII::U_BitShift; break;
1056  }
1057
1058  return Binary;
1059}
1060
1061void ARMCodeEmitter::emitLoadStoreMultipleInstruction(const MachineInstr &MI) {
1062  const TargetInstrDesc &TID = MI.getDesc();
1063  bool IsUpdating = (TID.TSFlags & ARMII::IndexModeMask) != 0;
1064
1065  // Part of binary is determined by TableGn.
1066  unsigned Binary = getBinaryCodeForInstr(MI);
1067
1068  // Set the conditional execution predicate
1069  Binary |= II->getPredicate(&MI) << ARMII::CondShift;
1070
1071  // Skip operand 0 of an instruction with base register update.
1072  unsigned OpIdx = 0;
1073  if (IsUpdating)
1074    ++OpIdx;
1075
1076  // Set base address operand
1077  Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRnShift;
1078
1079  // Set addressing mode by modifying bits U(23) and P(24)
1080  const MachineOperand &MO = MI.getOperand(OpIdx++);
1081  Binary |= getAddrModeUPBits(ARM_AM::getAM4SubMode(MO.getImm()));
1082
1083  // Set bit W(21)
1084  if (IsUpdating)
1085    Binary |= 0x1 << ARMII::W_BitShift;
1086
1087  // Set registers
1088  for (unsigned i = OpIdx+2, e = MI.getNumOperands(); i != e; ++i) {
1089    const MachineOperand &MO = MI.getOperand(i);
1090    if (!MO.isReg() || MO.isImplicit())
1091      break;
1092    unsigned RegNum = ARMRegisterInfo::getRegisterNumbering(MO.getReg());
1093    assert(TargetRegisterInfo::isPhysicalRegister(MO.getReg()) &&
1094           RegNum < 16);
1095    Binary |= 0x1 << RegNum;
1096  }
1097
1098  emitWordLE(Binary);
1099}
1100
1101void ARMCodeEmitter::emitMulFrmInstruction(const MachineInstr &MI) {
1102  const TargetInstrDesc &TID = MI.getDesc();
1103
1104  // Part of binary is determined by TableGn.
1105  unsigned Binary = getBinaryCodeForInstr(MI);
1106
1107  // Set the conditional execution predicate
1108  Binary |= II->getPredicate(&MI) << ARMII::CondShift;
1109
1110  // Encode S bit if MI modifies CPSR.
1111  Binary |= getAddrModeSBit(MI, TID);
1112
1113  // 32x32->64bit operations have two destination registers. The number
1114  // of register definitions will tell us if that's what we're dealing with.
1115  unsigned OpIdx = 0;
1116  if (TID.getNumDefs() == 2)
1117    Binary |= getMachineOpValue (MI, OpIdx++) << ARMII::RegRdLoShift;
1118
1119  // Encode Rd
1120  Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRdHiShift;
1121
1122  // Encode Rm
1123  Binary |= getMachineOpValue(MI, OpIdx++);
1124
1125  // Encode Rs
1126  Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRsShift;
1127
1128  // Many multiple instructions (e.g. MLA) have three src operands. Encode
1129  // it as Rn (for multiply, that's in the same offset as RdLo.
1130  if (TID.getNumOperands() > OpIdx &&
1131      !TID.OpInfo[OpIdx].isPredicate() &&
1132      !TID.OpInfo[OpIdx].isOptionalDef())
1133    Binary |= getMachineOpValue(MI, OpIdx) << ARMII::RegRdLoShift;
1134
1135  emitWordLE(Binary);
1136}
1137
1138void ARMCodeEmitter::emitExtendInstruction(const MachineInstr &MI) {
1139  const TargetInstrDesc &TID = MI.getDesc();
1140
1141  // Part of binary is determined by TableGn.
1142  unsigned Binary = getBinaryCodeForInstr(MI);
1143
1144  // Set the conditional execution predicate
1145  Binary |= II->getPredicate(&MI) << ARMII::CondShift;
1146
1147  unsigned OpIdx = 0;
1148
1149  // Encode Rd
1150  Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRdShift;
1151
1152  const MachineOperand &MO1 = MI.getOperand(OpIdx++);
1153  const MachineOperand &MO2 = MI.getOperand(OpIdx);
1154  if (MO2.isReg()) {
1155    // Two register operand form.
1156    // Encode Rn.
1157    Binary |= getMachineOpValue(MI, MO1) << ARMII::RegRnShift;
1158
1159    // Encode Rm.
1160    Binary |= getMachineOpValue(MI, MO2);
1161    ++OpIdx;
1162  } else {
1163    Binary |= getMachineOpValue(MI, MO1);
1164  }
1165
1166  // Encode rot imm (0, 8, 16, or 24) if it has a rotate immediate operand.
1167  if (MI.getOperand(OpIdx).isImm() &&
1168      !TID.OpInfo[OpIdx].isPredicate() &&
1169      !TID.OpInfo[OpIdx].isOptionalDef())
1170    Binary |= (getMachineOpValue(MI, OpIdx) / 8) << ARMII::ExtRotImmShift;
1171
1172  emitWordLE(Binary);
1173}
1174
1175void ARMCodeEmitter::emitMiscArithInstruction(const MachineInstr &MI) {
1176  const TargetInstrDesc &TID = MI.getDesc();
1177
1178  // Part of binary is determined by TableGn.
1179  unsigned Binary = getBinaryCodeForInstr(MI);
1180
1181  // Set the conditional execution predicate
1182  Binary |= II->getPredicate(&MI) << ARMII::CondShift;
1183
1184  unsigned OpIdx = 0;
1185
1186  // Encode Rd
1187  Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRdShift;
1188
1189  const MachineOperand &MO = MI.getOperand(OpIdx++);
1190  if (OpIdx == TID.getNumOperands() ||
1191      TID.OpInfo[OpIdx].isPredicate() ||
1192      TID.OpInfo[OpIdx].isOptionalDef()) {
1193    // Encode Rm and it's done.
1194    Binary |= getMachineOpValue(MI, MO);
1195    emitWordLE(Binary);
1196    return;
1197  }
1198
1199  // Encode Rn.
1200  Binary |= getMachineOpValue(MI, MO) << ARMII::RegRnShift;
1201
1202  // Encode Rm.
1203  Binary |= getMachineOpValue(MI, OpIdx++);
1204
1205  // Encode shift_imm.
1206  unsigned ShiftAmt = MI.getOperand(OpIdx).getImm();
1207  assert(ShiftAmt < 32 && "shift_imm range is 0 to 31!");
1208  Binary |= ShiftAmt << ARMII::ShiftShift;
1209
1210  emitWordLE(Binary);
1211}
1212
1213void ARMCodeEmitter::emitBranchInstruction(const MachineInstr &MI) {
1214  const TargetInstrDesc &TID = MI.getDesc();
1215
1216  if (TID.Opcode == ARM::TPsoft) {
1217    llvm_unreachable("ARM::TPsoft FIXME"); // FIXME
1218  }
1219
1220  // Part of binary is determined by TableGn.
1221  unsigned Binary = getBinaryCodeForInstr(MI);
1222
1223  // Set the conditional execution predicate
1224  Binary |= II->getPredicate(&MI) << ARMII::CondShift;
1225
1226  // Set signed_immed_24 field
1227  Binary |= getMachineOpValue(MI, 0);
1228
1229  emitWordLE(Binary);
1230}
1231
1232void ARMCodeEmitter::emitInlineJumpTable(unsigned JTIndex) {
1233  // Remember the base address of the inline jump table.
1234  uintptr_t JTBase = MCE.getCurrentPCValue();
1235  JTI->addJumpTableBaseAddr(JTIndex, JTBase);
1236  DEBUG(errs() << "  ** Jump Table #" << JTIndex << " @ " << (void*)JTBase
1237               << '\n');
1238
1239  // Now emit the jump table entries.
1240  const std::vector<MachineBasicBlock*> &MBBs = (*MJTEs)[JTIndex].MBBs;
1241  for (unsigned i = 0, e = MBBs.size(); i != e; ++i) {
1242    if (IsPIC)
1243      // DestBB address - JT base.
1244      emitMachineBasicBlock(MBBs[i], ARM::reloc_arm_pic_jt, JTBase);
1245    else
1246      // Absolute DestBB address.
1247      emitMachineBasicBlock(MBBs[i], ARM::reloc_arm_absolute);
1248    emitWordLE(0);
1249  }
1250}
1251
1252void ARMCodeEmitter::emitMiscBranchInstruction(const MachineInstr &MI) {
1253  const TargetInstrDesc &TID = MI.getDesc();
1254
1255  // Handle jump tables.
1256  if (TID.Opcode == ARM::BR_JTr || TID.Opcode == ARM::BR_JTadd) {
1257    // First emit a ldr pc, [] instruction.
1258    emitDataProcessingInstruction(MI, ARM::PC);
1259
1260    // Then emit the inline jump table.
1261    unsigned JTIndex =
1262      (TID.Opcode == ARM::BR_JTr)
1263      ? MI.getOperand(1).getIndex() : MI.getOperand(2).getIndex();
1264    emitInlineJumpTable(JTIndex);
1265    return;
1266  } else if (TID.Opcode == ARM::BR_JTm) {
1267    // First emit a ldr pc, [] instruction.
1268    emitLoadStoreInstruction(MI, ARM::PC);
1269
1270    // Then emit the inline jump table.
1271    emitInlineJumpTable(MI.getOperand(3).getIndex());
1272    return;
1273  }
1274
1275  // Part of binary is determined by TableGn.
1276  unsigned Binary = getBinaryCodeForInstr(MI);
1277
1278  // Set the conditional execution predicate
1279  Binary |= II->getPredicate(&MI) << ARMII::CondShift;
1280
1281  if (TID.Opcode == ARM::BX_RET || TID.Opcode == ARM::MOVPCLR)
1282    // The return register is LR.
1283    Binary |= ARMRegisterInfo::getRegisterNumbering(ARM::LR);
1284  else
1285    // otherwise, set the return register
1286    Binary |= getMachineOpValue(MI, 0);
1287
1288  emitWordLE(Binary);
1289}
1290
1291static unsigned encodeVFPRd(const MachineInstr &MI, unsigned OpIdx) {
1292  unsigned RegD = MI.getOperand(OpIdx).getReg();
1293  unsigned Binary = 0;
1294  bool isSPVFP = false;
1295  RegD = ARMRegisterInfo::getRegisterNumbering(RegD, &isSPVFP);
1296  if (!isSPVFP)
1297    Binary |=   RegD               << ARMII::RegRdShift;
1298  else {
1299    Binary |= ((RegD & 0x1E) >> 1) << ARMII::RegRdShift;
1300    Binary |=  (RegD & 0x01)       << ARMII::D_BitShift;
1301  }
1302  return Binary;
1303}
1304
1305static unsigned encodeVFPRn(const MachineInstr &MI, unsigned OpIdx) {
1306  unsigned RegN = MI.getOperand(OpIdx).getReg();
1307  unsigned Binary = 0;
1308  bool isSPVFP = false;
1309  RegN = ARMRegisterInfo::getRegisterNumbering(RegN, &isSPVFP);
1310  if (!isSPVFP)
1311    Binary |=   RegN               << ARMII::RegRnShift;
1312  else {
1313    Binary |= ((RegN & 0x1E) >> 1) << ARMII::RegRnShift;
1314    Binary |=  (RegN & 0x01)       << ARMII::N_BitShift;
1315  }
1316  return Binary;
1317}
1318
1319static unsigned encodeVFPRm(const MachineInstr &MI, unsigned OpIdx) {
1320  unsigned RegM = MI.getOperand(OpIdx).getReg();
1321  unsigned Binary = 0;
1322  bool isSPVFP = false;
1323  RegM = ARMRegisterInfo::getRegisterNumbering(RegM, &isSPVFP);
1324  if (!isSPVFP)
1325    Binary |=   RegM;
1326  else {
1327    Binary |= ((RegM & 0x1E) >> 1);
1328    Binary |=  (RegM & 0x01)       << ARMII::M_BitShift;
1329  }
1330  return Binary;
1331}
1332
1333void ARMCodeEmitter::emitVFPArithInstruction(const MachineInstr &MI) {
1334  const TargetInstrDesc &TID = MI.getDesc();
1335
1336  // Part of binary is determined by TableGn.
1337  unsigned Binary = getBinaryCodeForInstr(MI);
1338
1339  // Set the conditional execution predicate
1340  Binary |= II->getPredicate(&MI) << ARMII::CondShift;
1341
1342  unsigned OpIdx = 0;
1343  assert((Binary & ARMII::D_BitShift) == 0 &&
1344         (Binary & ARMII::N_BitShift) == 0 &&
1345         (Binary & ARMII::M_BitShift) == 0 && "VFP encoding bug!");
1346
1347  // Encode Dd / Sd.
1348  Binary |= encodeVFPRd(MI, OpIdx++);
1349
1350  // If this is a two-address operand, skip it, e.g. FMACD.
1351  if (TID.getOperandConstraint(OpIdx, TOI::TIED_TO) != -1)
1352    ++OpIdx;
1353
1354  // Encode Dn / Sn.
1355  if ((TID.TSFlags & ARMII::FormMask) == ARMII::VFPBinaryFrm)
1356    Binary |= encodeVFPRn(MI, OpIdx++);
1357
1358  if (OpIdx == TID.getNumOperands() ||
1359      TID.OpInfo[OpIdx].isPredicate() ||
1360      TID.OpInfo[OpIdx].isOptionalDef()) {
1361    // FCMPEZD etc. has only one operand.
1362    emitWordLE(Binary);
1363    return;
1364  }
1365
1366  // Encode Dm / Sm.
1367  Binary |= encodeVFPRm(MI, OpIdx);
1368
1369  emitWordLE(Binary);
1370}
1371
1372void ARMCodeEmitter::emitVFPConversionInstruction(const MachineInstr &MI) {
1373  const TargetInstrDesc &TID = MI.getDesc();
1374  unsigned Form = TID.TSFlags & ARMII::FormMask;
1375
1376  // Part of binary is determined by TableGn.
1377  unsigned Binary = getBinaryCodeForInstr(MI);
1378
1379  // Set the conditional execution predicate
1380  Binary |= II->getPredicate(&MI) << ARMII::CondShift;
1381
1382  switch (Form) {
1383  default: break;
1384  case ARMII::VFPConv1Frm:
1385  case ARMII::VFPConv2Frm:
1386  case ARMII::VFPConv3Frm:
1387    // Encode Dd / Sd.
1388    Binary |= encodeVFPRd(MI, 0);
1389    break;
1390  case ARMII::VFPConv4Frm:
1391    // Encode Dn / Sn.
1392    Binary |= encodeVFPRn(MI, 0);
1393    break;
1394  case ARMII::VFPConv5Frm:
1395    // Encode Dm / Sm.
1396    Binary |= encodeVFPRm(MI, 0);
1397    break;
1398  }
1399
1400  switch (Form) {
1401  default: break;
1402  case ARMII::VFPConv1Frm:
1403    // Encode Dm / Sm.
1404    Binary |= encodeVFPRm(MI, 1);
1405    break;
1406  case ARMII::VFPConv2Frm:
1407  case ARMII::VFPConv3Frm:
1408    // Encode Dn / Sn.
1409    Binary |= encodeVFPRn(MI, 1);
1410    break;
1411  case ARMII::VFPConv4Frm:
1412  case ARMII::VFPConv5Frm:
1413    // Encode Dd / Sd.
1414    Binary |= encodeVFPRd(MI, 1);
1415    break;
1416  }
1417
1418  if (Form == ARMII::VFPConv5Frm)
1419    // Encode Dn / Sn.
1420    Binary |= encodeVFPRn(MI, 2);
1421  else if (Form == ARMII::VFPConv3Frm)
1422    // Encode Dm / Sm.
1423    Binary |= encodeVFPRm(MI, 2);
1424
1425  emitWordLE(Binary);
1426}
1427
1428void ARMCodeEmitter::emitVFPLoadStoreInstruction(const MachineInstr &MI) {
1429  // Part of binary is determined by TableGn.
1430  unsigned Binary = getBinaryCodeForInstr(MI);
1431
1432  // Set the conditional execution predicate
1433  Binary |= II->getPredicate(&MI) << ARMII::CondShift;
1434
1435  unsigned OpIdx = 0;
1436
1437  // Encode Dd / Sd.
1438  Binary |= encodeVFPRd(MI, OpIdx++);
1439
1440  // Encode address base.
1441  const MachineOperand &Base = MI.getOperand(OpIdx++);
1442  Binary |= getMachineOpValue(MI, Base) << ARMII::RegRnShift;
1443
1444  // If there is a non-zero immediate offset, encode it.
1445  if (Base.isReg()) {
1446    const MachineOperand &Offset = MI.getOperand(OpIdx);
1447    if (unsigned ImmOffs = ARM_AM::getAM5Offset(Offset.getImm())) {
1448      if (ARM_AM::getAM5Op(Offset.getImm()) == ARM_AM::add)
1449        Binary |= 1 << ARMII::U_BitShift;
1450      Binary |= ImmOffs;
1451      emitWordLE(Binary);
1452      return;
1453    }
1454  }
1455
1456  // If immediate offset is omitted, default to +0.
1457  Binary |= 1 << ARMII::U_BitShift;
1458
1459  emitWordLE(Binary);
1460}
1461
1462void
1463ARMCodeEmitter::emitVFPLoadStoreMultipleInstruction(const MachineInstr &MI) {
1464  const TargetInstrDesc &TID = MI.getDesc();
1465  bool IsUpdating = (TID.TSFlags & ARMII::IndexModeMask) != 0;
1466
1467  // Part of binary is determined by TableGn.
1468  unsigned Binary = getBinaryCodeForInstr(MI);
1469
1470  // Set the conditional execution predicate
1471  Binary |= II->getPredicate(&MI) << ARMII::CondShift;
1472
1473  // Skip operand 0 of an instruction with base register update.
1474  unsigned OpIdx = 0;
1475  if (IsUpdating)
1476    ++OpIdx;
1477
1478  // Set base address operand
1479  Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRnShift;
1480
1481  // Set addressing mode by modifying bits U(23) and P(24)
1482  const MachineOperand &MO = MI.getOperand(OpIdx++);
1483  Binary |= getAddrModeUPBits(ARM_AM::getAM5SubMode(MO.getImm()));
1484
1485  // Set bit W(21)
1486  if (IsUpdating)
1487    Binary |= 0x1 << ARMII::W_BitShift;
1488
1489  // First register is encoded in Dd.
1490  Binary |= encodeVFPRd(MI, OpIdx+2);
1491
1492  // Number of registers are encoded in offset field.
1493  unsigned NumRegs = 1;
1494  for (unsigned i = OpIdx+3, e = MI.getNumOperands(); i != e; ++i) {
1495    const MachineOperand &MO = MI.getOperand(i);
1496    if (!MO.isReg() || MO.isImplicit())
1497      break;
1498    ++NumRegs;
1499  }
1500  // Bit 8 will be set if <list> is consecutive 64-bit registers (e.g., D0)
1501  // Otherwise, it will be 0, in the case of 32-bit registers.
1502  if(Binary & 0x100)
1503    Binary |= NumRegs * 2;
1504  else
1505    Binary |= NumRegs;
1506
1507  emitWordLE(Binary);
1508}
1509
1510void ARMCodeEmitter::emitMiscInstruction(const MachineInstr &MI) {
1511  unsigned Opcode = MI.getDesc().Opcode;
1512  // Part of binary is determined by TableGn.
1513  unsigned Binary = getBinaryCodeForInstr(MI);
1514
1515  // Set the conditional execution predicate
1516  Binary |= II->getPredicate(&MI) << ARMII::CondShift;
1517
1518  switch(Opcode) {
1519  default:
1520    llvm_unreachable("ARMCodeEmitter::emitMiscInstruction");
1521
1522  case ARM::FMSTAT:
1523    // No further encoding needed.
1524    break;
1525
1526  case ARM::VMRS:
1527  case ARM::VMSR: {
1528    const MachineOperand &MO0 = MI.getOperand(0);
1529    // Encode Rt.
1530    Binary |= ARMRegisterInfo::getRegisterNumbering(MO0.getReg())
1531                << ARMII::RegRdShift;
1532    break;
1533  }
1534
1535  case ARM::FCONSTD:
1536  case ARM::FCONSTS: {
1537    // Encode Dd / Sd.
1538    Binary |= encodeVFPRd(MI, 0);
1539
1540    // Encode imm., Table A7-18 VFP modified immediate constants
1541    const MachineOperand &MO1 = MI.getOperand(1);
1542    unsigned Imm = static_cast<unsigned>(MO1.getFPImm()->getValueAPF()
1543                      .bitcastToAPInt().getHiBits(32).getLimitedValue());
1544    unsigned ModifiedImm;
1545
1546    if(Opcode == ARM::FCONSTS)
1547      ModifiedImm = (Imm & 0x80000000) >> 24 | // a
1548                    (Imm & 0x03F80000) >> 19;  // bcdefgh
1549    else // Opcode == ARM::FCONSTD
1550      ModifiedImm = (Imm & 0x80000000) >> 24 | // a
1551                    (Imm & 0x007F0000) >> 16;  // bcdefgh
1552
1553    // Insts{19-16} = abcd, Insts{3-0} = efgh
1554    Binary |= ((ModifiedImm & 0xF0) >> 4) << 16;
1555    Binary |= (ModifiedImm & 0xF);
1556    break;
1557  }
1558  }
1559
1560  emitWordLE(Binary);
1561}
1562
1563static unsigned encodeNEONRd(const MachineInstr &MI, unsigned OpIdx) {
1564  unsigned RegD = MI.getOperand(OpIdx).getReg();
1565  unsigned Binary = 0;
1566  RegD = ARMRegisterInfo::getRegisterNumbering(RegD);
1567  Binary |= (RegD & 0xf) << ARMII::RegRdShift;
1568  Binary |= ((RegD >> 4) & 1) << ARMII::D_BitShift;
1569  return Binary;
1570}
1571
1572static unsigned encodeNEONRn(const MachineInstr &MI, unsigned OpIdx) {
1573  unsigned RegN = MI.getOperand(OpIdx).getReg();
1574  unsigned Binary = 0;
1575  RegN = ARMRegisterInfo::getRegisterNumbering(RegN);
1576  Binary |= (RegN & 0xf) << ARMII::RegRnShift;
1577  Binary |= ((RegN >> 4) & 1) << ARMII::N_BitShift;
1578  return Binary;
1579}
1580
1581static unsigned encodeNEONRm(const MachineInstr &MI, unsigned OpIdx) {
1582  unsigned RegM = MI.getOperand(OpIdx).getReg();
1583  unsigned Binary = 0;
1584  RegM = ARMRegisterInfo::getRegisterNumbering(RegM);
1585  Binary |= (RegM & 0xf);
1586  Binary |= ((RegM >> 4) & 1) << ARMII::M_BitShift;
1587  return Binary;
1588}
1589
1590/// convertNEONDataProcToThumb - Convert the ARM mode encoding for a NEON
1591/// data-processing instruction to the corresponding Thumb encoding.
1592static unsigned convertNEONDataProcToThumb(unsigned Binary) {
1593  assert((Binary & 0xfe000000) == 0xf2000000 &&
1594         "not an ARM NEON data-processing instruction");
1595  unsigned UBit = (Binary >> 24) & 1;
1596  return 0xef000000 | (UBit << 28) | (Binary & 0xffffff);
1597}
1598
1599void ARMCodeEmitter::emitNEONGetLaneInstruction(const MachineInstr &MI) {
1600  unsigned Binary = getBinaryCodeForInstr(MI);
1601
1602  // Set the conditional execution predicate
1603  Binary |= (IsThumb ? ARMCC::AL : II->getPredicate(&MI)) << ARMII::CondShift;
1604
1605  unsigned RegT = MI.getOperand(0).getReg();
1606  RegT = ARMRegisterInfo::getRegisterNumbering(RegT);
1607  Binary |= (RegT << ARMII::RegRdShift);
1608  Binary |= encodeNEONRn(MI, 1);
1609
1610  unsigned LaneShift;
1611  if ((Binary & (1 << 22)) != 0)
1612    LaneShift = 0; // 8-bit elements
1613  else if ((Binary & (1 << 5)) != 0)
1614    LaneShift = 1; // 16-bit elements
1615  else
1616    LaneShift = 2; // 32-bit elements
1617
1618  unsigned Lane = MI.getOperand(2).getImm() << LaneShift;
1619  unsigned Opc1 = Lane >> 2;
1620  unsigned Opc2 = Lane & 3;
1621  assert((Opc1 & 3) == 0 && "out-of-range lane number operand");
1622  Binary |= (Opc1 << 21);
1623  Binary |= (Opc2 << 5);
1624
1625  emitWordLE(Binary);
1626}
1627
1628void ARMCodeEmitter::emitNEON1RegModImmInstruction(const MachineInstr &MI) {
1629  unsigned Binary = getBinaryCodeForInstr(MI);
1630  // Destination register is encoded in Dd.
1631  Binary |= encodeNEONRd(MI, 0);
1632  // Immediate fields: Op, Cmode, I, Imm3, Imm4
1633  unsigned Imm = MI.getOperand(1).getImm();
1634  unsigned Op = (Imm >> 12) & 1;
1635  unsigned Cmode = (Imm >> 8) & 0xf;
1636  unsigned I = (Imm >> 7) & 1;
1637  unsigned Imm3 = (Imm >> 4) & 0x7;
1638  unsigned Imm4 = Imm & 0xf;
1639  Binary |= (I << 24) | (Imm3 << 16) | (Cmode << 8) | (Op << 5) | Imm4;
1640  if (IsThumb)
1641    Binary = convertNEONDataProcToThumb(Binary);
1642  emitWordLE(Binary);
1643}
1644
1645void ARMCodeEmitter::emitNEON2RegInstruction(const MachineInstr &MI) {
1646  const TargetInstrDesc &TID = MI.getDesc();
1647  unsigned Binary = getBinaryCodeForInstr(MI);
1648  // Destination register is encoded in Dd; source register in Dm.
1649  unsigned OpIdx = 0;
1650  Binary |= encodeNEONRd(MI, OpIdx++);
1651  if (TID.getOperandConstraint(OpIdx, TOI::TIED_TO) != -1)
1652    ++OpIdx;
1653  Binary |= encodeNEONRm(MI, OpIdx);
1654  if (IsThumb)
1655    Binary = convertNEONDataProcToThumb(Binary);
1656  // FIXME: This does not handle VDUPfdf or VDUPfqf.
1657  emitWordLE(Binary);
1658}
1659
1660void ARMCodeEmitter::emitNEON3RegInstruction(const MachineInstr &MI) {
1661  const TargetInstrDesc &TID = MI.getDesc();
1662  unsigned Binary = getBinaryCodeForInstr(MI);
1663  // Destination register is encoded in Dd; source registers in Dn and Dm.
1664  unsigned OpIdx = 0;
1665  Binary |= encodeNEONRd(MI, OpIdx++);
1666  if (TID.getOperandConstraint(OpIdx, TOI::TIED_TO) != -1)
1667    ++OpIdx;
1668  Binary |= encodeNEONRn(MI, OpIdx++);
1669  if (TID.getOperandConstraint(OpIdx, TOI::TIED_TO) != -1)
1670    ++OpIdx;
1671  Binary |= encodeNEONRm(MI, OpIdx);
1672  if (IsThumb)
1673    Binary = convertNEONDataProcToThumb(Binary);
1674  // FIXME: This does not handle VMOVDneon or VMOVQ.
1675  emitWordLE(Binary);
1676}
1677
1678#include "ARMGenCodeEmitter.inc"
1679