ARMCodeEmitter.cpp revision 705e07f578e2b3af47ddab610feb4e7f2d3063a5
1//===-- ARM/ARMCodeEmitter.cpp - Convert ARM code to machine code ---------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file contains the pass that transforms the ARM machine instructions into 11// relocatable machine code. 12// 13//===----------------------------------------------------------------------===// 14 15#define DEBUG_TYPE "jit" 16#include "ARM.h" 17#include "ARMAddressingModes.h" 18#include "ARMConstantPoolValue.h" 19#include "ARMInstrInfo.h" 20#include "ARMRelocations.h" 21#include "ARMSubtarget.h" 22#include "ARMTargetMachine.h" 23#include "llvm/Constants.h" 24#include "llvm/DerivedTypes.h" 25#include "llvm/Function.h" 26#include "llvm/PassManager.h" 27#include "llvm/CodeGen/MachineCodeEmitter.h" 28#include "llvm/CodeGen/JITCodeEmitter.h" 29#include "llvm/CodeGen/ObjectCodeEmitter.h" 30#include "llvm/CodeGen/MachineConstantPool.h" 31#include "llvm/CodeGen/MachineFunctionPass.h" 32#include "llvm/CodeGen/MachineInstr.h" 33#include "llvm/CodeGen/MachineJumpTableInfo.h" 34#include "llvm/CodeGen/Passes.h" 35#include "llvm/ADT/Statistic.h" 36#include "llvm/Support/Compiler.h" 37#include "llvm/Support/Debug.h" 38#include "llvm/Support/ErrorHandling.h" 39#include "llvm/Support/raw_ostream.h" 40#ifndef NDEBUG 41#include <iomanip> 42#endif 43using namespace llvm; 44 45STATISTIC(NumEmitted, "Number of machine instructions emitted"); 46 47namespace { 48 49 class ARMCodeEmitter { 50 public: 51 /// getBinaryCodeForInstr - This function, generated by the 52 /// CodeEmitterGenerator using TableGen, produces the binary encoding for 53 /// machine instructions. 54 unsigned getBinaryCodeForInstr(const MachineInstr &MI); 55 }; 56 57 template<class CodeEmitter> 58 class VISIBILITY_HIDDEN Emitter : public MachineFunctionPass, 59 public ARMCodeEmitter { 60 ARMJITInfo *JTI; 61 const ARMInstrInfo *II; 62 const TargetData *TD; 63 TargetMachine &TM; 64 CodeEmitter &MCE; 65 const std::vector<MachineConstantPoolEntry> *MCPEs; 66 const std::vector<MachineJumpTableEntry> *MJTEs; 67 bool IsPIC; 68 69 public: 70 static char ID; 71 explicit Emitter(TargetMachine &tm, CodeEmitter &mce) 72 : MachineFunctionPass(&ID), JTI(0), II(0), TD(0), TM(tm), 73 MCE(mce), MCPEs(0), MJTEs(0), 74 IsPIC(TM.getRelocationModel() == Reloc::PIC_) {} 75 Emitter(TargetMachine &tm, CodeEmitter &mce, 76 const ARMInstrInfo &ii, const TargetData &td) 77 : MachineFunctionPass(&ID), JTI(0), II(&ii), TD(&td), TM(tm), 78 MCE(mce), MCPEs(0), MJTEs(0), 79 IsPIC(TM.getRelocationModel() == Reloc::PIC_) {} 80 81 bool runOnMachineFunction(MachineFunction &MF); 82 83 virtual const char *getPassName() const { 84 return "ARM Machine Code Emitter"; 85 } 86 87 void emitInstruction(const MachineInstr &MI); 88 89 private: 90 91 void emitWordLE(unsigned Binary); 92 93 void emitDWordLE(uint64_t Binary); 94 95 void emitConstPoolInstruction(const MachineInstr &MI); 96 97 void emitMOVi2piecesInstruction(const MachineInstr &MI); 98 99 void emitLEApcrelJTInstruction(const MachineInstr &MI); 100 101 void emitPseudoMoveInstruction(const MachineInstr &MI); 102 103 void addPCLabel(unsigned LabelID); 104 105 void emitPseudoInstruction(const MachineInstr &MI); 106 107 unsigned getMachineSoRegOpValue(const MachineInstr &MI, 108 const TargetInstrDesc &TID, 109 const MachineOperand &MO, 110 unsigned OpIdx); 111 112 unsigned getMachineSoImmOpValue(unsigned SoImm); 113 114 unsigned getAddrModeSBit(const MachineInstr &MI, 115 const TargetInstrDesc &TID) const; 116 117 void emitDataProcessingInstruction(const MachineInstr &MI, 118 unsigned ImplicitRd = 0, 119 unsigned ImplicitRn = 0); 120 121 void emitLoadStoreInstruction(const MachineInstr &MI, 122 unsigned ImplicitRd = 0, 123 unsigned ImplicitRn = 0); 124 125 void emitMiscLoadStoreInstruction(const MachineInstr &MI, 126 unsigned ImplicitRn = 0); 127 128 void emitLoadStoreMultipleInstruction(const MachineInstr &MI); 129 130 void emitMulFrmInstruction(const MachineInstr &MI); 131 132 void emitExtendInstruction(const MachineInstr &MI); 133 134 void emitMiscArithInstruction(const MachineInstr &MI); 135 136 void emitBranchInstruction(const MachineInstr &MI); 137 138 void emitInlineJumpTable(unsigned JTIndex); 139 140 void emitMiscBranchInstruction(const MachineInstr &MI); 141 142 void emitVFPArithInstruction(const MachineInstr &MI); 143 144 void emitVFPConversionInstruction(const MachineInstr &MI); 145 146 void emitVFPLoadStoreInstruction(const MachineInstr &MI); 147 148 void emitVFPLoadStoreMultipleInstruction(const MachineInstr &MI); 149 150 void emitMiscInstruction(const MachineInstr &MI); 151 152 /// getMachineOpValue - Return binary encoding of operand. If the machine 153 /// operand requires relocation, record the relocation and return zero. 154 unsigned getMachineOpValue(const MachineInstr &MI,const MachineOperand &MO); 155 unsigned getMachineOpValue(const MachineInstr &MI, unsigned OpIdx) { 156 return getMachineOpValue(MI, MI.getOperand(OpIdx)); 157 } 158 159 /// getShiftOp - Return the shift opcode (bit[6:5]) of the immediate value. 160 /// 161 unsigned getShiftOp(unsigned Imm) const ; 162 163 /// Routines that handle operands which add machine relocations which are 164 /// fixed up by the relocation stage. 165 void emitGlobalAddress(GlobalValue *GV, unsigned Reloc, 166 bool NeedStub, intptr_t ACPV = 0); 167 void emitExternalSymbolAddress(const char *ES, unsigned Reloc); 168 void emitConstPoolAddress(unsigned CPI, unsigned Reloc); 169 void emitJumpTableAddress(unsigned JTIndex, unsigned Reloc); 170 void emitMachineBasicBlock(MachineBasicBlock *BB, unsigned Reloc, 171 intptr_t JTBase = 0); 172 }; 173 template <class CodeEmitter> 174 char Emitter<CodeEmitter>::ID = 0; 175} 176 177/// createARMCodeEmitterPass - Return a pass that emits the collected ARM code 178/// to the specified MCE object. 179 180FunctionPass *llvm::createARMCodeEmitterPass(ARMBaseTargetMachine &TM, 181 MachineCodeEmitter &MCE) { 182 return new Emitter<MachineCodeEmitter>(TM, MCE); 183} 184FunctionPass *llvm::createARMJITCodeEmitterPass(ARMBaseTargetMachine &TM, 185 JITCodeEmitter &JCE) { 186 return new Emitter<JITCodeEmitter>(TM, JCE); 187} 188FunctionPass *llvm::createARMObjectCodeEmitterPass(ARMBaseTargetMachine &TM, 189 ObjectCodeEmitter &OCE) { 190 return new Emitter<ObjectCodeEmitter>(TM, OCE); 191} 192 193template<class CodeEmitter> 194bool Emitter<CodeEmitter>::runOnMachineFunction(MachineFunction &MF) { 195 assert((MF.getTarget().getRelocationModel() != Reloc::Default || 196 MF.getTarget().getRelocationModel() != Reloc::Static) && 197 "JIT relocation model must be set to static or default!"); 198 II = ((ARMTargetMachine&)MF.getTarget()).getInstrInfo(); 199 TD = ((ARMTargetMachine&)MF.getTarget()).getTargetData(); 200 JTI = ((ARMTargetMachine&)MF.getTarget()).getJITInfo(); 201 MCPEs = &MF.getConstantPool()->getConstants(); 202 MJTEs = &MF.getJumpTableInfo()->getJumpTables(); 203 IsPIC = TM.getRelocationModel() == Reloc::PIC_; 204 JTI->Initialize(MF, IsPIC); 205 206 do { 207 DEBUG(errs() << "JITTing function '" 208 << MF.getFunction()->getName() << "'\n"); 209 MCE.startFunction(MF); 210 for (MachineFunction::iterator MBB = MF.begin(), E = MF.end(); 211 MBB != E; ++MBB) { 212 MCE.StartMachineBasicBlock(MBB); 213 for (MachineBasicBlock::const_iterator I = MBB->begin(), E = MBB->end(); 214 I != E; ++I) 215 emitInstruction(*I); 216 } 217 } while (MCE.finishFunction(MF)); 218 219 return false; 220} 221 222/// getShiftOp - Return the shift opcode (bit[6:5]) of the immediate value. 223/// 224template<class CodeEmitter> 225unsigned Emitter<CodeEmitter>::getShiftOp(unsigned Imm) const { 226 switch (ARM_AM::getAM2ShiftOpc(Imm)) { 227 default: llvm_unreachable("Unknown shift opc!"); 228 case ARM_AM::asr: return 2; 229 case ARM_AM::lsl: return 0; 230 case ARM_AM::lsr: return 1; 231 case ARM_AM::ror: 232 case ARM_AM::rrx: return 3; 233 } 234 return 0; 235} 236 237/// getMachineOpValue - Return binary encoding of operand. If the machine 238/// operand requires relocation, record the relocation and return zero. 239template<class CodeEmitter> 240unsigned Emitter<CodeEmitter>::getMachineOpValue(const MachineInstr &MI, 241 const MachineOperand &MO) { 242 if (MO.isReg()) 243 return ARMRegisterInfo::getRegisterNumbering(MO.getReg()); 244 else if (MO.isImm()) 245 return static_cast<unsigned>(MO.getImm()); 246 else if (MO.isGlobal()) 247 emitGlobalAddress(MO.getGlobal(), ARM::reloc_arm_branch, true); 248 else if (MO.isSymbol()) 249 emitExternalSymbolAddress(MO.getSymbolName(), ARM::reloc_arm_branch); 250 else if (MO.isCPI()) { 251 const TargetInstrDesc &TID = MI.getDesc(); 252 // For VFP load, the immediate offset is multiplied by 4. 253 unsigned Reloc = ((TID.TSFlags & ARMII::FormMask) == ARMII::VFPLdStFrm) 254 ? ARM::reloc_arm_vfp_cp_entry : ARM::reloc_arm_cp_entry; 255 emitConstPoolAddress(MO.getIndex(), Reloc); 256 } else if (MO.isJTI()) 257 emitJumpTableAddress(MO.getIndex(), ARM::reloc_arm_relative); 258 else if (MO.isMBB()) 259 emitMachineBasicBlock(MO.getMBB(), ARM::reloc_arm_branch); 260 else { 261#ifndef NDEBUG 262 errs() << MO; 263#endif 264 llvm_unreachable(0); 265 } 266 return 0; 267} 268 269/// emitGlobalAddress - Emit the specified address to the code stream. 270/// 271template<class CodeEmitter> 272void Emitter<CodeEmitter>::emitGlobalAddress(GlobalValue *GV, unsigned Reloc, 273 bool NeedStub, intptr_t ACPV) { 274 MCE.addRelocation(MachineRelocation::getGV(MCE.getCurrentPCOffset(), Reloc, 275 GV, ACPV, NeedStub)); 276} 277 278/// emitExternalSymbolAddress - Arrange for the address of an external symbol to 279/// be emitted to the current location in the function, and allow it to be PC 280/// relative. 281template<class CodeEmitter> 282void Emitter<CodeEmitter>::emitExternalSymbolAddress(const char *ES, 283 unsigned Reloc) { 284 MCE.addRelocation(MachineRelocation::getExtSym(MCE.getCurrentPCOffset(), 285 Reloc, ES)); 286} 287 288/// emitConstPoolAddress - Arrange for the address of an constant pool 289/// to be emitted to the current location in the function, and allow it to be PC 290/// relative. 291template<class CodeEmitter> 292void Emitter<CodeEmitter>::emitConstPoolAddress(unsigned CPI, 293 unsigned Reloc) { 294 // Tell JIT emitter we'll resolve the address. 295 MCE.addRelocation(MachineRelocation::getConstPool(MCE.getCurrentPCOffset(), 296 Reloc, CPI, 0, true)); 297} 298 299/// emitJumpTableAddress - Arrange for the address of a jump table to 300/// be emitted to the current location in the function, and allow it to be PC 301/// relative. 302template<class CodeEmitter> 303void Emitter<CodeEmitter>::emitJumpTableAddress(unsigned JTIndex, 304 unsigned Reloc) { 305 MCE.addRelocation(MachineRelocation::getJumpTable(MCE.getCurrentPCOffset(), 306 Reloc, JTIndex, 0, true)); 307} 308 309/// emitMachineBasicBlock - Emit the specified address basic block. 310template<class CodeEmitter> 311void Emitter<CodeEmitter>::emitMachineBasicBlock(MachineBasicBlock *BB, 312 unsigned Reloc, intptr_t JTBase) { 313 MCE.addRelocation(MachineRelocation::getBB(MCE.getCurrentPCOffset(), 314 Reloc, BB, JTBase)); 315} 316 317template<class CodeEmitter> 318void Emitter<CodeEmitter>::emitWordLE(unsigned Binary) { 319#ifndef NDEBUG 320 DOUT << " 0x" << std::hex << std::setw(8) << std::setfill('0') 321 << Binary << std::dec << "\n"; 322#endif 323 MCE.emitWordLE(Binary); 324} 325 326template<class CodeEmitter> 327void Emitter<CodeEmitter>::emitDWordLE(uint64_t Binary) { 328#ifndef NDEBUG 329 DOUT << " 0x" << std::hex << std::setw(8) << std::setfill('0') 330 << (unsigned)Binary << std::dec << "\n"; 331 DOUT << " 0x" << std::hex << std::setw(8) << std::setfill('0') 332 << (unsigned)(Binary >> 32) << std::dec << "\n"; 333#endif 334 MCE.emitDWordLE(Binary); 335} 336 337template<class CodeEmitter> 338void Emitter<CodeEmitter>::emitInstruction(const MachineInstr &MI) { 339 DEBUG(errs() << "JIT: " << (void*)MCE.getCurrentPCValue() << ":\t" << MI); 340 341 MCE.processDebugLoc(MI.getDebugLoc()); 342 343 NumEmitted++; // Keep track of the # of mi's emitted 344 switch (MI.getDesc().TSFlags & ARMII::FormMask) { 345 default: { 346 llvm_unreachable("Unhandled instruction encoding format!"); 347 break; 348 } 349 case ARMII::Pseudo: 350 emitPseudoInstruction(MI); 351 break; 352 case ARMII::DPFrm: 353 case ARMII::DPSoRegFrm: 354 emitDataProcessingInstruction(MI); 355 break; 356 case ARMII::LdFrm: 357 case ARMII::StFrm: 358 emitLoadStoreInstruction(MI); 359 break; 360 case ARMII::LdMiscFrm: 361 case ARMII::StMiscFrm: 362 emitMiscLoadStoreInstruction(MI); 363 break; 364 case ARMII::LdStMulFrm: 365 emitLoadStoreMultipleInstruction(MI); 366 break; 367 case ARMII::MulFrm: 368 emitMulFrmInstruction(MI); 369 break; 370 case ARMII::ExtFrm: 371 emitExtendInstruction(MI); 372 break; 373 case ARMII::ArithMiscFrm: 374 emitMiscArithInstruction(MI); 375 break; 376 case ARMII::BrFrm: 377 emitBranchInstruction(MI); 378 break; 379 case ARMII::BrMiscFrm: 380 emitMiscBranchInstruction(MI); 381 break; 382 // VFP instructions. 383 case ARMII::VFPUnaryFrm: 384 case ARMII::VFPBinaryFrm: 385 emitVFPArithInstruction(MI); 386 break; 387 case ARMII::VFPConv1Frm: 388 case ARMII::VFPConv2Frm: 389 case ARMII::VFPConv3Frm: 390 case ARMII::VFPConv4Frm: 391 case ARMII::VFPConv5Frm: 392 emitVFPConversionInstruction(MI); 393 break; 394 case ARMII::VFPLdStFrm: 395 emitVFPLoadStoreInstruction(MI); 396 break; 397 case ARMII::VFPLdStMulFrm: 398 emitVFPLoadStoreMultipleInstruction(MI); 399 break; 400 case ARMII::VFPMiscFrm: 401 emitMiscInstruction(MI); 402 break; 403 } 404} 405 406template<class CodeEmitter> 407void Emitter<CodeEmitter>::emitConstPoolInstruction(const MachineInstr &MI) { 408 unsigned CPI = MI.getOperand(0).getImm(); // CP instruction index. 409 unsigned CPIndex = MI.getOperand(1).getIndex(); // Actual cp entry index. 410 const MachineConstantPoolEntry &MCPE = (*MCPEs)[CPIndex]; 411 412 // Remember the CONSTPOOL_ENTRY address for later relocation. 413 JTI->addConstantPoolEntryAddr(CPI, MCE.getCurrentPCValue()); 414 415 // Emit constpool island entry. In most cases, the actual values will be 416 // resolved and relocated after code emission. 417 if (MCPE.isMachineConstantPoolEntry()) { 418 ARMConstantPoolValue *ACPV = 419 static_cast<ARMConstantPoolValue*>(MCPE.Val.MachineCPVal); 420 421 DEBUG(errs() << " ** ARM constant pool #" << CPI << " @ " 422 << (void*)MCE.getCurrentPCValue() << " " << *ACPV << '\n'); 423 424 GlobalValue *GV = ACPV->getGV(); 425 if (GV) { 426 assert(!ACPV->isStub() && "Don't know how to deal this yet!"); 427 if (ACPV->isNonLazyPointer()) 428 MCE.addRelocation(MachineRelocation::getIndirectSymbol( 429 MCE.getCurrentPCOffset(), ARM::reloc_arm_machine_cp_entry, GV, 430 (intptr_t)ACPV, false)); 431 else 432 emitGlobalAddress(GV, ARM::reloc_arm_machine_cp_entry, 433 ACPV->isStub() || isa<Function>(GV), (intptr_t)ACPV); 434 } else { 435 assert(!ACPV->isNonLazyPointer() && "Don't know how to deal this yet!"); 436 emitExternalSymbolAddress(ACPV->getSymbol(), ARM::reloc_arm_absolute); 437 } 438 emitWordLE(0); 439 } else { 440 Constant *CV = MCPE.Val.ConstVal; 441 442 DEBUG({ 443 errs() << " ** Constant pool #" << CPI << " @ " 444 << (void*)MCE.getCurrentPCValue() << " "; 445 if (const Function *F = dyn_cast<Function>(CV)) 446 errs() << F->getName(); 447 else 448 errs() << *CV; 449 errs() << '\n'; 450 }); 451 452 if (GlobalValue *GV = dyn_cast<GlobalValue>(CV)) { 453 emitGlobalAddress(GV, ARM::reloc_arm_absolute, isa<Function>(GV)); 454 emitWordLE(0); 455 } else if (const ConstantInt *CI = dyn_cast<ConstantInt>(CV)) { 456 uint32_t Val = *(uint32_t*)CI->getValue().getRawData(); 457 emitWordLE(Val); 458 } else if (const ConstantFP *CFP = dyn_cast<ConstantFP>(CV)) { 459 if (CFP->getType() == Type::getFloatTy(CFP->getContext())) 460 emitWordLE(CFP->getValueAPF().bitcastToAPInt().getZExtValue()); 461 else if (CFP->getType() == Type::getDoubleTy(CFP->getContext())) 462 emitDWordLE(CFP->getValueAPF().bitcastToAPInt().getZExtValue()); 463 else { 464 llvm_unreachable("Unable to handle this constantpool entry!"); 465 } 466 } else { 467 llvm_unreachable("Unable to handle this constantpool entry!"); 468 } 469 } 470} 471 472template<class CodeEmitter> 473void Emitter<CodeEmitter>::emitMOVi2piecesInstruction(const MachineInstr &MI) { 474 const MachineOperand &MO0 = MI.getOperand(0); 475 const MachineOperand &MO1 = MI.getOperand(1); 476 assert(MO1.isImm() && ARM_AM::getSOImmVal(MO1.isImm()) != -1 && 477 "Not a valid so_imm value!"); 478 unsigned V1 = ARM_AM::getSOImmTwoPartFirst(MO1.getImm()); 479 unsigned V2 = ARM_AM::getSOImmTwoPartSecond(MO1.getImm()); 480 481 // Emit the 'mov' instruction. 482 unsigned Binary = 0xd << 21; // mov: Insts{24-21} = 0b1101 483 484 // Set the conditional execution predicate. 485 Binary |= II->getPredicate(&MI) << ARMII::CondShift; 486 487 // Encode Rd. 488 Binary |= getMachineOpValue(MI, MO0) << ARMII::RegRdShift; 489 490 // Encode so_imm. 491 // Set bit I(25) to identify this is the immediate form of <shifter_op> 492 Binary |= 1 << ARMII::I_BitShift; 493 Binary |= getMachineSoImmOpValue(V1); 494 emitWordLE(Binary); 495 496 // Now the 'orr' instruction. 497 Binary = 0xc << 21; // orr: Insts{24-21} = 0b1100 498 499 // Set the conditional execution predicate. 500 Binary |= II->getPredicate(&MI) << ARMII::CondShift; 501 502 // Encode Rd. 503 Binary |= getMachineOpValue(MI, MO0) << ARMII::RegRdShift; 504 505 // Encode Rn. 506 Binary |= getMachineOpValue(MI, MO0) << ARMII::RegRnShift; 507 508 // Encode so_imm. 509 // Set bit I(25) to identify this is the immediate form of <shifter_op> 510 Binary |= 1 << ARMII::I_BitShift; 511 Binary |= getMachineSoImmOpValue(V2); 512 emitWordLE(Binary); 513} 514 515template<class CodeEmitter> 516void Emitter<CodeEmitter>::emitLEApcrelJTInstruction(const MachineInstr &MI) { 517 // It's basically add r, pc, (LJTI - $+8) 518 519 const TargetInstrDesc &TID = MI.getDesc(); 520 521 // Emit the 'add' instruction. 522 unsigned Binary = 0x4 << 21; // add: Insts{24-31} = 0b0100 523 524 // Set the conditional execution predicate 525 Binary |= II->getPredicate(&MI) << ARMII::CondShift; 526 527 // Encode S bit if MI modifies CPSR. 528 Binary |= getAddrModeSBit(MI, TID); 529 530 // Encode Rd. 531 Binary |= getMachineOpValue(MI, 0) << ARMII::RegRdShift; 532 533 // Encode Rn which is PC. 534 Binary |= ARMRegisterInfo::getRegisterNumbering(ARM::PC) << ARMII::RegRnShift; 535 536 // Encode the displacement. 537 Binary |= 1 << ARMII::I_BitShift; 538 emitJumpTableAddress(MI.getOperand(1).getIndex(), ARM::reloc_arm_jt_base); 539 540 emitWordLE(Binary); 541} 542 543template<class CodeEmitter> 544void Emitter<CodeEmitter>::emitPseudoMoveInstruction(const MachineInstr &MI) { 545 unsigned Opcode = MI.getDesc().Opcode; 546 547 // Part of binary is determined by TableGn. 548 unsigned Binary = getBinaryCodeForInstr(MI); 549 550 // Set the conditional execution predicate 551 Binary |= II->getPredicate(&MI) << ARMII::CondShift; 552 553 // Encode S bit if MI modifies CPSR. 554 if (Opcode == ARM::MOVsrl_flag || Opcode == ARM::MOVsra_flag) 555 Binary |= 1 << ARMII::S_BitShift; 556 557 // Encode register def if there is one. 558 Binary |= getMachineOpValue(MI, 0) << ARMII::RegRdShift; 559 560 // Encode the shift operation. 561 switch (Opcode) { 562 default: break; 563 case ARM::MOVrx: 564 // rrx 565 Binary |= 0x6 << 4; 566 break; 567 case ARM::MOVsrl_flag: 568 // lsr #1 569 Binary |= (0x2 << 4) | (1 << 7); 570 break; 571 case ARM::MOVsra_flag: 572 // asr #1 573 Binary |= (0x4 << 4) | (1 << 7); 574 break; 575 } 576 577 // Encode register Rm. 578 Binary |= getMachineOpValue(MI, 1); 579 580 emitWordLE(Binary); 581} 582 583template<class CodeEmitter> 584void Emitter<CodeEmitter>::addPCLabel(unsigned LabelID) { 585 DOUT << " ** LPC" << LabelID << " @ " 586 << (void*)MCE.getCurrentPCValue() << '\n'; 587 JTI->addPCLabelAddr(LabelID, MCE.getCurrentPCValue()); 588} 589 590template<class CodeEmitter> 591void Emitter<CodeEmitter>::emitPseudoInstruction(const MachineInstr &MI) { 592 unsigned Opcode = MI.getDesc().Opcode; 593 switch (Opcode) { 594 default: 595 llvm_unreachable("ARMCodeEmitter::emitPseudoInstruction");//FIXME: 596 case TargetInstrInfo::INLINEASM: { 597 // We allow inline assembler nodes with empty bodies - they can 598 // implicitly define registers, which is ok for JIT. 599 if (MI.getOperand(0).getSymbolName()[0]) { 600 llvm_report_error("JIT does not support inline asm!"); 601 } 602 break; 603 } 604 case TargetInstrInfo::DBG_LABEL: 605 case TargetInstrInfo::EH_LABEL: 606 MCE.emitLabel(MI.getOperand(0).getImm()); 607 break; 608 case TargetInstrInfo::IMPLICIT_DEF: 609 case ARM::DWARF_LOC: 610 // Do nothing. 611 break; 612 case ARM::CONSTPOOL_ENTRY: 613 emitConstPoolInstruction(MI); 614 break; 615 case ARM::PICADD: { 616 // Remember of the address of the PC label for relocation later. 617 addPCLabel(MI.getOperand(2).getImm()); 618 // PICADD is just an add instruction that implicitly read pc. 619 emitDataProcessingInstruction(MI, 0, ARM::PC); 620 break; 621 } 622 case ARM::PICLDR: 623 case ARM::PICLDRB: 624 case ARM::PICSTR: 625 case ARM::PICSTRB: { 626 // Remember of the address of the PC label for relocation later. 627 addPCLabel(MI.getOperand(2).getImm()); 628 // These are just load / store instructions that implicitly read pc. 629 emitLoadStoreInstruction(MI, 0, ARM::PC); 630 break; 631 } 632 case ARM::PICLDRH: 633 case ARM::PICLDRSH: 634 case ARM::PICLDRSB: 635 case ARM::PICSTRH: { 636 // Remember of the address of the PC label for relocation later. 637 addPCLabel(MI.getOperand(2).getImm()); 638 // These are just load / store instructions that implicitly read pc. 639 emitMiscLoadStoreInstruction(MI, ARM::PC); 640 break; 641 } 642 case ARM::MOVi2pieces: 643 // Two instructions to materialize a constant. 644 emitMOVi2piecesInstruction(MI); 645 break; 646 case ARM::LEApcrelJT: 647 // Materialize jumptable address. 648 emitLEApcrelJTInstruction(MI); 649 break; 650 case ARM::MOVrx: 651 case ARM::MOVsrl_flag: 652 case ARM::MOVsra_flag: 653 emitPseudoMoveInstruction(MI); 654 break; 655 } 656} 657 658template<class CodeEmitter> 659unsigned Emitter<CodeEmitter>::getMachineSoRegOpValue( 660 const MachineInstr &MI, 661 const TargetInstrDesc &TID, 662 const MachineOperand &MO, 663 unsigned OpIdx) { 664 unsigned Binary = getMachineOpValue(MI, MO); 665 666 const MachineOperand &MO1 = MI.getOperand(OpIdx + 1); 667 const MachineOperand &MO2 = MI.getOperand(OpIdx + 2); 668 ARM_AM::ShiftOpc SOpc = ARM_AM::getSORegShOp(MO2.getImm()); 669 670 // Encode the shift opcode. 671 unsigned SBits = 0; 672 unsigned Rs = MO1.getReg(); 673 if (Rs) { 674 // Set shift operand (bit[7:4]). 675 // LSL - 0001 676 // LSR - 0011 677 // ASR - 0101 678 // ROR - 0111 679 // RRX - 0110 and bit[11:8] clear. 680 switch (SOpc) { 681 default: llvm_unreachable("Unknown shift opc!"); 682 case ARM_AM::lsl: SBits = 0x1; break; 683 case ARM_AM::lsr: SBits = 0x3; break; 684 case ARM_AM::asr: SBits = 0x5; break; 685 case ARM_AM::ror: SBits = 0x7; break; 686 case ARM_AM::rrx: SBits = 0x6; break; 687 } 688 } else { 689 // Set shift operand (bit[6:4]). 690 // LSL - 000 691 // LSR - 010 692 // ASR - 100 693 // ROR - 110 694 switch (SOpc) { 695 default: llvm_unreachable("Unknown shift opc!"); 696 case ARM_AM::lsl: SBits = 0x0; break; 697 case ARM_AM::lsr: SBits = 0x2; break; 698 case ARM_AM::asr: SBits = 0x4; break; 699 case ARM_AM::ror: SBits = 0x6; break; 700 } 701 } 702 Binary |= SBits << 4; 703 if (SOpc == ARM_AM::rrx) 704 return Binary; 705 706 // Encode the shift operation Rs or shift_imm (except rrx). 707 if (Rs) { 708 // Encode Rs bit[11:8]. 709 assert(ARM_AM::getSORegOffset(MO2.getImm()) == 0); 710 return Binary | 711 (ARMRegisterInfo::getRegisterNumbering(Rs) << ARMII::RegRsShift); 712 } 713 714 // Encode shift_imm bit[11:7]. 715 return Binary | ARM_AM::getSORegOffset(MO2.getImm()) << 7; 716} 717 718template<class CodeEmitter> 719unsigned Emitter<CodeEmitter>::getMachineSoImmOpValue(unsigned SoImm) { 720 int SoImmVal = ARM_AM::getSOImmVal(SoImm); 721 assert(SoImmVal != -1 && "Not a valid so_imm value!"); 722 723 // Encode rotate_imm. 724 unsigned Binary = (ARM_AM::getSOImmValRot((unsigned)SoImmVal) >> 1) 725 << ARMII::SoRotImmShift; 726 727 // Encode immed_8. 728 Binary |= ARM_AM::getSOImmValImm((unsigned)SoImmVal); 729 return Binary; 730} 731 732template<class CodeEmitter> 733unsigned Emitter<CodeEmitter>::getAddrModeSBit(const MachineInstr &MI, 734 const TargetInstrDesc &TID) const { 735 for (unsigned i = MI.getNumOperands(), e = TID.getNumOperands(); i != e; --i){ 736 const MachineOperand &MO = MI.getOperand(i-1); 737 if (MO.isReg() && MO.isDef() && MO.getReg() == ARM::CPSR) 738 return 1 << ARMII::S_BitShift; 739 } 740 return 0; 741} 742 743template<class CodeEmitter> 744void Emitter<CodeEmitter>::emitDataProcessingInstruction( 745 const MachineInstr &MI, 746 unsigned ImplicitRd, 747 unsigned ImplicitRn) { 748 const TargetInstrDesc &TID = MI.getDesc(); 749 750 if (TID.Opcode == ARM::BFC) { 751 llvm_report_error("ARMv6t2 JIT is not yet supported."); 752 } 753 754 // Part of binary is determined by TableGn. 755 unsigned Binary = getBinaryCodeForInstr(MI); 756 757 // Set the conditional execution predicate 758 Binary |= II->getPredicate(&MI) << ARMII::CondShift; 759 760 // Encode S bit if MI modifies CPSR. 761 Binary |= getAddrModeSBit(MI, TID); 762 763 // Encode register def if there is one. 764 unsigned NumDefs = TID.getNumDefs(); 765 unsigned OpIdx = 0; 766 if (NumDefs) 767 Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRdShift; 768 else if (ImplicitRd) 769 // Special handling for implicit use (e.g. PC). 770 Binary |= (ARMRegisterInfo::getRegisterNumbering(ImplicitRd) 771 << ARMII::RegRdShift); 772 773 // If this is a two-address operand, skip it. e.g. MOVCCr operand 1. 774 if (TID.getOperandConstraint(OpIdx, TOI::TIED_TO) != -1) 775 ++OpIdx; 776 777 // Encode first non-shifter register operand if there is one. 778 bool isUnary = TID.TSFlags & ARMII::UnaryDP; 779 if (!isUnary) { 780 if (ImplicitRn) 781 // Special handling for implicit use (e.g. PC). 782 Binary |= (ARMRegisterInfo::getRegisterNumbering(ImplicitRn) 783 << ARMII::RegRnShift); 784 else { 785 Binary |= getMachineOpValue(MI, OpIdx) << ARMII::RegRnShift; 786 ++OpIdx; 787 } 788 } 789 790 // Encode shifter operand. 791 const MachineOperand &MO = MI.getOperand(OpIdx); 792 if ((TID.TSFlags & ARMII::FormMask) == ARMII::DPSoRegFrm) { 793 // Encode SoReg. 794 emitWordLE(Binary | getMachineSoRegOpValue(MI, TID, MO, OpIdx)); 795 return; 796 } 797 798 if (MO.isReg()) { 799 // Encode register Rm. 800 emitWordLE(Binary | ARMRegisterInfo::getRegisterNumbering(MO.getReg())); 801 return; 802 } 803 804 // Encode so_imm. 805 Binary |= getMachineSoImmOpValue((unsigned)MO.getImm()); 806 807 emitWordLE(Binary); 808} 809 810template<class CodeEmitter> 811void Emitter<CodeEmitter>::emitLoadStoreInstruction( 812 const MachineInstr &MI, 813 unsigned ImplicitRd, 814 unsigned ImplicitRn) { 815 const TargetInstrDesc &TID = MI.getDesc(); 816 unsigned Form = TID.TSFlags & ARMII::FormMask; 817 bool IsPrePost = (TID.TSFlags & ARMII::IndexModeMask) != 0; 818 819 // Part of binary is determined by TableGn. 820 unsigned Binary = getBinaryCodeForInstr(MI); 821 822 // Set the conditional execution predicate 823 Binary |= II->getPredicate(&MI) << ARMII::CondShift; 824 825 unsigned OpIdx = 0; 826 827 // Operand 0 of a pre- and post-indexed store is the address base 828 // writeback. Skip it. 829 bool Skipped = false; 830 if (IsPrePost && Form == ARMII::StFrm) { 831 ++OpIdx; 832 Skipped = true; 833 } 834 835 // Set first operand 836 if (ImplicitRd) 837 // Special handling for implicit use (e.g. PC). 838 Binary |= (ARMRegisterInfo::getRegisterNumbering(ImplicitRd) 839 << ARMII::RegRdShift); 840 else 841 Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRdShift; 842 843 // Set second operand 844 if (ImplicitRn) 845 // Special handling for implicit use (e.g. PC). 846 Binary |= (ARMRegisterInfo::getRegisterNumbering(ImplicitRn) 847 << ARMII::RegRnShift); 848 else 849 Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRnShift; 850 851 // If this is a two-address operand, skip it. e.g. LDR_PRE. 852 if (!Skipped && TID.getOperandConstraint(OpIdx, TOI::TIED_TO) != -1) 853 ++OpIdx; 854 855 const MachineOperand &MO2 = MI.getOperand(OpIdx); 856 unsigned AM2Opc = (ImplicitRn == ARM::PC) 857 ? 0 : MI.getOperand(OpIdx+1).getImm(); 858 859 // Set bit U(23) according to sign of immed value (positive or negative). 860 Binary |= ((ARM_AM::getAM2Op(AM2Opc) == ARM_AM::add ? 1 : 0) << 861 ARMII::U_BitShift); 862 if (!MO2.getReg()) { // is immediate 863 if (ARM_AM::getAM2Offset(AM2Opc)) 864 // Set the value of offset_12 field 865 Binary |= ARM_AM::getAM2Offset(AM2Opc); 866 emitWordLE(Binary); 867 return; 868 } 869 870 // Set bit I(25), because this is not in immediate enconding. 871 Binary |= 1 << ARMII::I_BitShift; 872 assert(TargetRegisterInfo::isPhysicalRegister(MO2.getReg())); 873 // Set bit[3:0] to the corresponding Rm register 874 Binary |= ARMRegisterInfo::getRegisterNumbering(MO2.getReg()); 875 876 // If this instr is in scaled register offset/index instruction, set 877 // shift_immed(bit[11:7]) and shift(bit[6:5]) fields. 878 if (unsigned ShImm = ARM_AM::getAM2Offset(AM2Opc)) { 879 Binary |= getShiftOp(AM2Opc) << ARMII::ShiftImmShift; // shift 880 Binary |= ShImm << ARMII::ShiftShift; // shift_immed 881 } 882 883 emitWordLE(Binary); 884} 885 886template<class CodeEmitter> 887void Emitter<CodeEmitter>::emitMiscLoadStoreInstruction(const MachineInstr &MI, 888 unsigned ImplicitRn) { 889 const TargetInstrDesc &TID = MI.getDesc(); 890 unsigned Form = TID.TSFlags & ARMII::FormMask; 891 bool IsPrePost = (TID.TSFlags & ARMII::IndexModeMask) != 0; 892 893 // Part of binary is determined by TableGn. 894 unsigned Binary = getBinaryCodeForInstr(MI); 895 896 // Set the conditional execution predicate 897 Binary |= II->getPredicate(&MI) << ARMII::CondShift; 898 899 unsigned OpIdx = 0; 900 901 // Operand 0 of a pre- and post-indexed store is the address base 902 // writeback. Skip it. 903 bool Skipped = false; 904 if (IsPrePost && Form == ARMII::StMiscFrm) { 905 ++OpIdx; 906 Skipped = true; 907 } 908 909 // Set first operand 910 Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRdShift; 911 912 // Skip LDRD and STRD's second operand. 913 if (TID.Opcode == ARM::LDRD || TID.Opcode == ARM::STRD) 914 ++OpIdx; 915 916 // Set second operand 917 if (ImplicitRn) 918 // Special handling for implicit use (e.g. PC). 919 Binary |= (ARMRegisterInfo::getRegisterNumbering(ImplicitRn) 920 << ARMII::RegRnShift); 921 else 922 Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRnShift; 923 924 // If this is a two-address operand, skip it. e.g. LDRH_POST. 925 if (!Skipped && TID.getOperandConstraint(OpIdx, TOI::TIED_TO) != -1) 926 ++OpIdx; 927 928 const MachineOperand &MO2 = MI.getOperand(OpIdx); 929 unsigned AM3Opc = (ImplicitRn == ARM::PC) 930 ? 0 : MI.getOperand(OpIdx+1).getImm(); 931 932 // Set bit U(23) according to sign of immed value (positive or negative) 933 Binary |= ((ARM_AM::getAM3Op(AM3Opc) == ARM_AM::add ? 1 : 0) << 934 ARMII::U_BitShift); 935 936 // If this instr is in register offset/index encoding, set bit[3:0] 937 // to the corresponding Rm register. 938 if (MO2.getReg()) { 939 Binary |= ARMRegisterInfo::getRegisterNumbering(MO2.getReg()); 940 emitWordLE(Binary); 941 return; 942 } 943 944 // This instr is in immediate offset/index encoding, set bit 22 to 1. 945 Binary |= 1 << ARMII::AM3_I_BitShift; 946 if (unsigned ImmOffs = ARM_AM::getAM3Offset(AM3Opc)) { 947 // Set operands 948 Binary |= (ImmOffs >> 4) << ARMII::ImmHiShift; // immedH 949 Binary |= (ImmOffs & 0xF); // immedL 950 } 951 952 emitWordLE(Binary); 953} 954 955static unsigned getAddrModeUPBits(unsigned Mode) { 956 unsigned Binary = 0; 957 958 // Set addressing mode by modifying bits U(23) and P(24) 959 // IA - Increment after - bit U = 1 and bit P = 0 960 // IB - Increment before - bit U = 1 and bit P = 1 961 // DA - Decrement after - bit U = 0 and bit P = 0 962 // DB - Decrement before - bit U = 0 and bit P = 1 963 switch (Mode) { 964 default: llvm_unreachable("Unknown addressing sub-mode!"); 965 case ARM_AM::da: break; 966 case ARM_AM::db: Binary |= 0x1 << ARMII::P_BitShift; break; 967 case ARM_AM::ia: Binary |= 0x1 << ARMII::U_BitShift; break; 968 case ARM_AM::ib: Binary |= 0x3 << ARMII::U_BitShift; break; 969 } 970 971 return Binary; 972} 973 974template<class CodeEmitter> 975void Emitter<CodeEmitter>::emitLoadStoreMultipleInstruction( 976 const MachineInstr &MI) { 977 // Part of binary is determined by TableGn. 978 unsigned Binary = getBinaryCodeForInstr(MI); 979 980 // Set the conditional execution predicate 981 Binary |= II->getPredicate(&MI) << ARMII::CondShift; 982 983 // Set base address operand 984 Binary |= getMachineOpValue(MI, 0) << ARMII::RegRnShift; 985 986 // Set addressing mode by modifying bits U(23) and P(24) 987 const MachineOperand &MO = MI.getOperand(1); 988 Binary |= getAddrModeUPBits(ARM_AM::getAM4SubMode(MO.getImm())); 989 990 // Set bit W(21) 991 if (ARM_AM::getAM4WBFlag(MO.getImm())) 992 Binary |= 0x1 << ARMII::W_BitShift; 993 994 // Set registers 995 for (unsigned i = 4, e = MI.getNumOperands(); i != e; ++i) { 996 const MachineOperand &MO = MI.getOperand(i); 997 if (!MO.isReg() || MO.isImplicit()) 998 break; 999 unsigned RegNum = ARMRegisterInfo::getRegisterNumbering(MO.getReg()); 1000 assert(TargetRegisterInfo::isPhysicalRegister(MO.getReg()) && 1001 RegNum < 16); 1002 Binary |= 0x1 << RegNum; 1003 } 1004 1005 emitWordLE(Binary); 1006} 1007 1008template<class CodeEmitter> 1009void Emitter<CodeEmitter>::emitMulFrmInstruction(const MachineInstr &MI) { 1010 const TargetInstrDesc &TID = MI.getDesc(); 1011 1012 // Part of binary is determined by TableGn. 1013 unsigned Binary = getBinaryCodeForInstr(MI); 1014 1015 // Set the conditional execution predicate 1016 Binary |= II->getPredicate(&MI) << ARMII::CondShift; 1017 1018 // Encode S bit if MI modifies CPSR. 1019 Binary |= getAddrModeSBit(MI, TID); 1020 1021 // 32x32->64bit operations have two destination registers. The number 1022 // of register definitions will tell us if that's what we're dealing with. 1023 unsigned OpIdx = 0; 1024 if (TID.getNumDefs() == 2) 1025 Binary |= getMachineOpValue (MI, OpIdx++) << ARMII::RegRdLoShift; 1026 1027 // Encode Rd 1028 Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRdHiShift; 1029 1030 // Encode Rm 1031 Binary |= getMachineOpValue(MI, OpIdx++); 1032 1033 // Encode Rs 1034 Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRsShift; 1035 1036 // Many multiple instructions (e.g. MLA) have three src operands. Encode 1037 // it as Rn (for multiply, that's in the same offset as RdLo. 1038 if (TID.getNumOperands() > OpIdx && 1039 !TID.OpInfo[OpIdx].isPredicate() && 1040 !TID.OpInfo[OpIdx].isOptionalDef()) 1041 Binary |= getMachineOpValue(MI, OpIdx) << ARMII::RegRdLoShift; 1042 1043 emitWordLE(Binary); 1044} 1045 1046template<class CodeEmitter> 1047void Emitter<CodeEmitter>::emitExtendInstruction(const MachineInstr &MI) { 1048 const TargetInstrDesc &TID = MI.getDesc(); 1049 1050 // Part of binary is determined by TableGn. 1051 unsigned Binary = getBinaryCodeForInstr(MI); 1052 1053 // Set the conditional execution predicate 1054 Binary |= II->getPredicate(&MI) << ARMII::CondShift; 1055 1056 unsigned OpIdx = 0; 1057 1058 // Encode Rd 1059 Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRdShift; 1060 1061 const MachineOperand &MO1 = MI.getOperand(OpIdx++); 1062 const MachineOperand &MO2 = MI.getOperand(OpIdx); 1063 if (MO2.isReg()) { 1064 // Two register operand form. 1065 // Encode Rn. 1066 Binary |= getMachineOpValue(MI, MO1) << ARMII::RegRnShift; 1067 1068 // Encode Rm. 1069 Binary |= getMachineOpValue(MI, MO2); 1070 ++OpIdx; 1071 } else { 1072 Binary |= getMachineOpValue(MI, MO1); 1073 } 1074 1075 // Encode rot imm (0, 8, 16, or 24) if it has a rotate immediate operand. 1076 if (MI.getOperand(OpIdx).isImm() && 1077 !TID.OpInfo[OpIdx].isPredicate() && 1078 !TID.OpInfo[OpIdx].isOptionalDef()) 1079 Binary |= (getMachineOpValue(MI, OpIdx) / 8) << ARMII::ExtRotImmShift; 1080 1081 emitWordLE(Binary); 1082} 1083 1084template<class CodeEmitter> 1085void Emitter<CodeEmitter>::emitMiscArithInstruction(const MachineInstr &MI) { 1086 const TargetInstrDesc &TID = MI.getDesc(); 1087 1088 // Part of binary is determined by TableGn. 1089 unsigned Binary = getBinaryCodeForInstr(MI); 1090 1091 // Set the conditional execution predicate 1092 Binary |= II->getPredicate(&MI) << ARMII::CondShift; 1093 1094 unsigned OpIdx = 0; 1095 1096 // Encode Rd 1097 Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRdShift; 1098 1099 const MachineOperand &MO = MI.getOperand(OpIdx++); 1100 if (OpIdx == TID.getNumOperands() || 1101 TID.OpInfo[OpIdx].isPredicate() || 1102 TID.OpInfo[OpIdx].isOptionalDef()) { 1103 // Encode Rm and it's done. 1104 Binary |= getMachineOpValue(MI, MO); 1105 emitWordLE(Binary); 1106 return; 1107 } 1108 1109 // Encode Rn. 1110 Binary |= getMachineOpValue(MI, MO) << ARMII::RegRnShift; 1111 1112 // Encode Rm. 1113 Binary |= getMachineOpValue(MI, OpIdx++); 1114 1115 // Encode shift_imm. 1116 unsigned ShiftAmt = MI.getOperand(OpIdx).getImm(); 1117 assert(ShiftAmt < 32 && "shift_imm range is 0 to 31!"); 1118 Binary |= ShiftAmt << ARMII::ShiftShift; 1119 1120 emitWordLE(Binary); 1121} 1122 1123template<class CodeEmitter> 1124void Emitter<CodeEmitter>::emitBranchInstruction(const MachineInstr &MI) { 1125 const TargetInstrDesc &TID = MI.getDesc(); 1126 1127 if (TID.Opcode == ARM::TPsoft) { 1128 llvm_unreachable("ARM::TPsoft FIXME"); // FIXME 1129 } 1130 1131 // Part of binary is determined by TableGn. 1132 unsigned Binary = getBinaryCodeForInstr(MI); 1133 1134 // Set the conditional execution predicate 1135 Binary |= II->getPredicate(&MI) << ARMII::CondShift; 1136 1137 // Set signed_immed_24 field 1138 Binary |= getMachineOpValue(MI, 0); 1139 1140 emitWordLE(Binary); 1141} 1142 1143template<class CodeEmitter> 1144void Emitter<CodeEmitter>::emitInlineJumpTable(unsigned JTIndex) { 1145 // Remember the base address of the inline jump table. 1146 uintptr_t JTBase = MCE.getCurrentPCValue(); 1147 JTI->addJumpTableBaseAddr(JTIndex, JTBase); 1148 DOUT << " ** Jump Table #" << JTIndex << " @ " << (void*)JTBase << '\n'; 1149 1150 // Now emit the jump table entries. 1151 const std::vector<MachineBasicBlock*> &MBBs = (*MJTEs)[JTIndex].MBBs; 1152 for (unsigned i = 0, e = MBBs.size(); i != e; ++i) { 1153 if (IsPIC) 1154 // DestBB address - JT base. 1155 emitMachineBasicBlock(MBBs[i], ARM::reloc_arm_pic_jt, JTBase); 1156 else 1157 // Absolute DestBB address. 1158 emitMachineBasicBlock(MBBs[i], ARM::reloc_arm_absolute); 1159 emitWordLE(0); 1160 } 1161} 1162 1163template<class CodeEmitter> 1164void Emitter<CodeEmitter>::emitMiscBranchInstruction(const MachineInstr &MI) { 1165 const TargetInstrDesc &TID = MI.getDesc(); 1166 1167 // Handle jump tables. 1168 if (TID.Opcode == ARM::BR_JTr || TID.Opcode == ARM::BR_JTadd) { 1169 // First emit a ldr pc, [] instruction. 1170 emitDataProcessingInstruction(MI, ARM::PC); 1171 1172 // Then emit the inline jump table. 1173 unsigned JTIndex = 1174 (TID.Opcode == ARM::BR_JTr) 1175 ? MI.getOperand(1).getIndex() : MI.getOperand(2).getIndex(); 1176 emitInlineJumpTable(JTIndex); 1177 return; 1178 } else if (TID.Opcode == ARM::BR_JTm) { 1179 // First emit a ldr pc, [] instruction. 1180 emitLoadStoreInstruction(MI, ARM::PC); 1181 1182 // Then emit the inline jump table. 1183 emitInlineJumpTable(MI.getOperand(3).getIndex()); 1184 return; 1185 } 1186 1187 // Part of binary is determined by TableGn. 1188 unsigned Binary = getBinaryCodeForInstr(MI); 1189 1190 // Set the conditional execution predicate 1191 Binary |= II->getPredicate(&MI) << ARMII::CondShift; 1192 1193 if (TID.Opcode == ARM::BX_RET) 1194 // The return register is LR. 1195 Binary |= ARMRegisterInfo::getRegisterNumbering(ARM::LR); 1196 else 1197 // otherwise, set the return register 1198 Binary |= getMachineOpValue(MI, 0); 1199 1200 emitWordLE(Binary); 1201} 1202 1203static unsigned encodeVFPRd(const MachineInstr &MI, unsigned OpIdx) { 1204 unsigned RegD = MI.getOperand(OpIdx).getReg(); 1205 unsigned Binary = 0; 1206 bool isSPVFP = false; 1207 RegD = ARMRegisterInfo::getRegisterNumbering(RegD, &isSPVFP); 1208 if (!isSPVFP) 1209 Binary |= RegD << ARMII::RegRdShift; 1210 else { 1211 Binary |= ((RegD & 0x1E) >> 1) << ARMII::RegRdShift; 1212 Binary |= (RegD & 0x01) << ARMII::D_BitShift; 1213 } 1214 return Binary; 1215} 1216 1217static unsigned encodeVFPRn(const MachineInstr &MI, unsigned OpIdx) { 1218 unsigned RegN = MI.getOperand(OpIdx).getReg(); 1219 unsigned Binary = 0; 1220 bool isSPVFP = false; 1221 RegN = ARMRegisterInfo::getRegisterNumbering(RegN, &isSPVFP); 1222 if (!isSPVFP) 1223 Binary |= RegN << ARMII::RegRnShift; 1224 else { 1225 Binary |= ((RegN & 0x1E) >> 1) << ARMII::RegRnShift; 1226 Binary |= (RegN & 0x01) << ARMII::N_BitShift; 1227 } 1228 return Binary; 1229} 1230 1231static unsigned encodeVFPRm(const MachineInstr &MI, unsigned OpIdx) { 1232 unsigned RegM = MI.getOperand(OpIdx).getReg(); 1233 unsigned Binary = 0; 1234 bool isSPVFP = false; 1235 RegM = ARMRegisterInfo::getRegisterNumbering(RegM, &isSPVFP); 1236 if (!isSPVFP) 1237 Binary |= RegM; 1238 else { 1239 Binary |= ((RegM & 0x1E) >> 1); 1240 Binary |= (RegM & 0x01) << ARMII::M_BitShift; 1241 } 1242 return Binary; 1243} 1244 1245template<class CodeEmitter> 1246void Emitter<CodeEmitter>::emitVFPArithInstruction(const MachineInstr &MI) { 1247 const TargetInstrDesc &TID = MI.getDesc(); 1248 1249 // Part of binary is determined by TableGn. 1250 unsigned Binary = getBinaryCodeForInstr(MI); 1251 1252 // Set the conditional execution predicate 1253 Binary |= II->getPredicate(&MI) << ARMII::CondShift; 1254 1255 unsigned OpIdx = 0; 1256 assert((Binary & ARMII::D_BitShift) == 0 && 1257 (Binary & ARMII::N_BitShift) == 0 && 1258 (Binary & ARMII::M_BitShift) == 0 && "VFP encoding bug!"); 1259 1260 // Encode Dd / Sd. 1261 Binary |= encodeVFPRd(MI, OpIdx++); 1262 1263 // If this is a two-address operand, skip it, e.g. FMACD. 1264 if (TID.getOperandConstraint(OpIdx, TOI::TIED_TO) != -1) 1265 ++OpIdx; 1266 1267 // Encode Dn / Sn. 1268 if ((TID.TSFlags & ARMII::FormMask) == ARMII::VFPBinaryFrm) 1269 Binary |= encodeVFPRn(MI, OpIdx++); 1270 1271 if (OpIdx == TID.getNumOperands() || 1272 TID.OpInfo[OpIdx].isPredicate() || 1273 TID.OpInfo[OpIdx].isOptionalDef()) { 1274 // FCMPEZD etc. has only one operand. 1275 emitWordLE(Binary); 1276 return; 1277 } 1278 1279 // Encode Dm / Sm. 1280 Binary |= encodeVFPRm(MI, OpIdx); 1281 1282 emitWordLE(Binary); 1283} 1284 1285template<class CodeEmitter> 1286void Emitter<CodeEmitter>::emitVFPConversionInstruction( 1287 const MachineInstr &MI) { 1288 const TargetInstrDesc &TID = MI.getDesc(); 1289 unsigned Form = TID.TSFlags & ARMII::FormMask; 1290 1291 // Part of binary is determined by TableGn. 1292 unsigned Binary = getBinaryCodeForInstr(MI); 1293 1294 // Set the conditional execution predicate 1295 Binary |= II->getPredicate(&MI) << ARMII::CondShift; 1296 1297 switch (Form) { 1298 default: break; 1299 case ARMII::VFPConv1Frm: 1300 case ARMII::VFPConv2Frm: 1301 case ARMII::VFPConv3Frm: 1302 // Encode Dd / Sd. 1303 Binary |= encodeVFPRd(MI, 0); 1304 break; 1305 case ARMII::VFPConv4Frm: 1306 // Encode Dn / Sn. 1307 Binary |= encodeVFPRn(MI, 0); 1308 break; 1309 case ARMII::VFPConv5Frm: 1310 // Encode Dm / Sm. 1311 Binary |= encodeVFPRm(MI, 0); 1312 break; 1313 } 1314 1315 switch (Form) { 1316 default: break; 1317 case ARMII::VFPConv1Frm: 1318 // Encode Dm / Sm. 1319 Binary |= encodeVFPRm(MI, 1); 1320 break; 1321 case ARMII::VFPConv2Frm: 1322 case ARMII::VFPConv3Frm: 1323 // Encode Dn / Sn. 1324 Binary |= encodeVFPRn(MI, 1); 1325 break; 1326 case ARMII::VFPConv4Frm: 1327 case ARMII::VFPConv5Frm: 1328 // Encode Dd / Sd. 1329 Binary |= encodeVFPRd(MI, 1); 1330 break; 1331 } 1332 1333 if (Form == ARMII::VFPConv5Frm) 1334 // Encode Dn / Sn. 1335 Binary |= encodeVFPRn(MI, 2); 1336 else if (Form == ARMII::VFPConv3Frm) 1337 // Encode Dm / Sm. 1338 Binary |= encodeVFPRm(MI, 2); 1339 1340 emitWordLE(Binary); 1341} 1342 1343template<class CodeEmitter> 1344void Emitter<CodeEmitter>::emitVFPLoadStoreInstruction(const MachineInstr &MI) { 1345 // Part of binary is determined by TableGn. 1346 unsigned Binary = getBinaryCodeForInstr(MI); 1347 1348 // Set the conditional execution predicate 1349 Binary |= II->getPredicate(&MI) << ARMII::CondShift; 1350 1351 unsigned OpIdx = 0; 1352 1353 // Encode Dd / Sd. 1354 Binary |= encodeVFPRd(MI, OpIdx++); 1355 1356 // Encode address base. 1357 const MachineOperand &Base = MI.getOperand(OpIdx++); 1358 Binary |= getMachineOpValue(MI, Base) << ARMII::RegRnShift; 1359 1360 // If there is a non-zero immediate offset, encode it. 1361 if (Base.isReg()) { 1362 const MachineOperand &Offset = MI.getOperand(OpIdx); 1363 if (unsigned ImmOffs = ARM_AM::getAM5Offset(Offset.getImm())) { 1364 if (ARM_AM::getAM5Op(Offset.getImm()) == ARM_AM::add) 1365 Binary |= 1 << ARMII::U_BitShift; 1366 Binary |= ImmOffs; 1367 emitWordLE(Binary); 1368 return; 1369 } 1370 } 1371 1372 // If immediate offset is omitted, default to +0. 1373 Binary |= 1 << ARMII::U_BitShift; 1374 1375 emitWordLE(Binary); 1376} 1377 1378template<class CodeEmitter> 1379void Emitter<CodeEmitter>::emitVFPLoadStoreMultipleInstruction( 1380 const MachineInstr &MI) { 1381 // Part of binary is determined by TableGn. 1382 unsigned Binary = getBinaryCodeForInstr(MI); 1383 1384 // Set the conditional execution predicate 1385 Binary |= II->getPredicate(&MI) << ARMII::CondShift; 1386 1387 // Set base address operand 1388 Binary |= getMachineOpValue(MI, 0) << ARMII::RegRnShift; 1389 1390 // Set addressing mode by modifying bits U(23) and P(24) 1391 const MachineOperand &MO = MI.getOperand(1); 1392 Binary |= getAddrModeUPBits(ARM_AM::getAM5SubMode(MO.getImm())); 1393 1394 // Set bit W(21) 1395 if (ARM_AM::getAM5WBFlag(MO.getImm())) 1396 Binary |= 0x1 << ARMII::W_BitShift; 1397 1398 // First register is encoded in Dd. 1399 Binary |= encodeVFPRd(MI, 4); 1400 1401 // Number of registers are encoded in offset field. 1402 unsigned NumRegs = 1; 1403 for (unsigned i = 5, e = MI.getNumOperands(); i != e; ++i) { 1404 const MachineOperand &MO = MI.getOperand(i); 1405 if (!MO.isReg() || MO.isImplicit()) 1406 break; 1407 ++NumRegs; 1408 } 1409 Binary |= NumRegs * 2; 1410 1411 emitWordLE(Binary); 1412} 1413 1414template<class CodeEmitter> 1415void Emitter<CodeEmitter>::emitMiscInstruction(const MachineInstr &MI) { 1416 // Part of binary is determined by TableGn. 1417 unsigned Binary = getBinaryCodeForInstr(MI); 1418 1419 // Set the conditional execution predicate 1420 Binary |= II->getPredicate(&MI) << ARMII::CondShift; 1421 1422 emitWordLE(Binary); 1423} 1424 1425#include "ARMGenCodeEmitter.inc" 1426