ARMCodeEmitter.cpp revision 70939ee1415722d7f39f13faf9b3644b96007996 
1//===-- ARM/ARMCodeEmitter.cpp - Convert ARM code to machine code ---------===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file contains the pass that transforms the ARM machine instructions into
11// relocatable machine code.
12//
13//===----------------------------------------------------------------------===//
14
15#define DEBUG_TYPE "jit"
16#include "ARM.h"
17#include "ARMConstantPoolValue.h"
18#include "ARMInstrInfo.h"
19#include "ARMRelocations.h"
20#include "ARMSubtarget.h"
21#include "ARMTargetMachine.h"
22#include "MCTargetDesc/ARMAddressingModes.h"
23#include "llvm/Constants.h"
24#include "llvm/DerivedTypes.h"
25#include "llvm/Function.h"
26#include "llvm/PassManager.h"
27#include "llvm/CodeGen/JITCodeEmitter.h"
28#include "llvm/CodeGen/MachineConstantPool.h"
29#include "llvm/CodeGen/MachineFunctionPass.h"
30#include "llvm/CodeGen/MachineInstr.h"
31#include "llvm/CodeGen/MachineJumpTableInfo.h"
32#include "llvm/CodeGen/MachineModuleInfo.h"
33#include "llvm/CodeGen/Passes.h"
34#include "llvm/ADT/Statistic.h"
35#include "llvm/Support/Debug.h"
36#include "llvm/Support/ErrorHandling.h"
37#include "llvm/Support/raw_ostream.h"
38#ifndef NDEBUG
39#include <iomanip>
40#endif
41using namespace llvm;
42
43STATISTIC(NumEmitted, "Number of machine instructions emitted");
44
45namespace {
46
47  class ARMCodeEmitter : public MachineFunctionPass {
48    ARMJITInfo                *JTI;
49    const ARMInstrInfo        *II;
50    const TargetData          *TD;
51    const ARMSubtarget        *Subtarget;
52    TargetMachine             &TM;
53    JITCodeEmitter            &MCE;
54    MachineModuleInfo *MMI;
55    const std::vector<MachineConstantPoolEntry> *MCPEs;
56    const std::vector<MachineJumpTableEntry> *MJTEs;
57    bool IsPIC;
58    bool IsThumb;
59
60    void getAnalysisUsage(AnalysisUsage &AU) const {
61      AU.addRequired<MachineModuleInfo>();
62      MachineFunctionPass::getAnalysisUsage(AU);
63    }
64
65    static char ID;
66  public:
67    ARMCodeEmitter(TargetMachine &tm, JITCodeEmitter &mce)
68      : MachineFunctionPass(ID), JTI(0),
69        II((const ARMInstrInfo *)tm.getInstrInfo()),
70        TD(tm.getTargetData()), TM(tm),
71        MCE(mce), MCPEs(0), MJTEs(0),
72        IsPIC(TM.getRelocationModel() == Reloc::PIC_), IsThumb(false) {}
73
74    /// getBinaryCodeForInstr - This function, generated by the
75    /// CodeEmitterGenerator using TableGen, produces the binary encoding for
76    /// machine instructions.
77    unsigned getBinaryCodeForInstr(const MachineInstr &MI) const;
78
79    bool runOnMachineFunction(MachineFunction &MF);
80
81    virtual const char *getPassName() const {
82      return "ARM Machine Code Emitter";
83    }
84
85    void emitInstruction(const MachineInstr &MI);
86
87  private:
88
89    void emitWordLE(unsigned Binary);
90    void emitDWordLE(uint64_t Binary);
91    void emitConstPoolInstruction(const MachineInstr &MI);
92    void emitMOVi32immInstruction(const MachineInstr &MI);
93    void emitMOVi2piecesInstruction(const MachineInstr &MI);
94    void emitLEApcrelJTInstruction(const MachineInstr &MI);
95    void emitPseudoMoveInstruction(const MachineInstr &MI);
96    void addPCLabel(unsigned LabelID);
97    void emitPseudoInstruction(const MachineInstr &MI);
98    unsigned getMachineSoRegOpValue(const MachineInstr &MI,
99                                    const MCInstrDesc &MCID,
100                                    const MachineOperand &MO,
101                                    unsigned OpIdx);
102
103    unsigned getMachineSoImmOpValue(unsigned SoImm);
104    unsigned getAddrModeSBit(const MachineInstr &MI,
105                             const MCInstrDesc &MCID) const;
106
107    void emitDataProcessingInstruction(const MachineInstr &MI,
108                                       unsigned ImplicitRd = 0,
109                                       unsigned ImplicitRn = 0);
110
111    void emitLoadStoreInstruction(const MachineInstr &MI,
112                                  unsigned ImplicitRd = 0,
113                                  unsigned ImplicitRn = 0);
114
115    void emitMiscLoadStoreInstruction(const MachineInstr &MI,
116                                      unsigned ImplicitRn = 0);
117
118    void emitLoadStoreMultipleInstruction(const MachineInstr &MI);
119
120    void emitMulFrmInstruction(const MachineInstr &MI);
121
122    void emitExtendInstruction(const MachineInstr &MI);
123
124    void emitMiscArithInstruction(const MachineInstr &MI);
125
126    void emitSaturateInstruction(const MachineInstr &MI);
127
128    void emitBranchInstruction(const MachineInstr &MI);
129
130    void emitInlineJumpTable(unsigned JTIndex);
131
132    void emitMiscBranchInstruction(const MachineInstr &MI);
133
134    void emitVFPArithInstruction(const MachineInstr &MI);
135
136    void emitVFPConversionInstruction(const MachineInstr &MI);
137
138    void emitVFPLoadStoreInstruction(const MachineInstr &MI);
139
140    void emitVFPLoadStoreMultipleInstruction(const MachineInstr &MI);
141
142    void emitNEONLaneInstruction(const MachineInstr &MI);
143    void emitNEONDupInstruction(const MachineInstr &MI);
144    void emitNEON1RegModImmInstruction(const MachineInstr &MI);
145    void emitNEON2RegInstruction(const MachineInstr &MI);
146    void emitNEON3RegInstruction(const MachineInstr &MI);
147
148    /// getMachineOpValue - Return binary encoding of operand. If the machine
149    /// operand requires relocation, record the relocation and return zero.
150    unsigned getMachineOpValue(const MachineInstr &MI,
151                               const MachineOperand &MO) const;
152    unsigned getMachineOpValue(const MachineInstr &MI, unsigned OpIdx) const {
153      return getMachineOpValue(MI, MI.getOperand(OpIdx));
154    }
155
156    // FIXME: The legacy JIT ARMCodeEmitter doesn't rely on the the
157    //  TableGen'erated getBinaryCodeForInstr() function to encode any
158    //  operand values, instead querying getMachineOpValue() directly for
159    //  each operand it needs to encode. Thus, any of the new encoder
160    //  helper functions can simply return 0 as the values the return
161    //  are already handled elsewhere. They are placeholders to allow this
162    //  encoder to continue to function until the MC encoder is sufficiently
163    //  far along that this one can be eliminated entirely.
164    unsigned NEONThumb2DataIPostEncoder(const MachineInstr &MI, unsigned Val)
165      const { return 0; }
166    unsigned NEONThumb2LoadStorePostEncoder(const MachineInstr &MI,unsigned Val)
167      const { return 0; }
168    unsigned NEONThumb2DupPostEncoder(const MachineInstr &MI,unsigned Val)
169      const { return 0; }
170    unsigned VFPThumb2PostEncoder(const MachineInstr&MI, unsigned Val)
171      const { return 0; }
172    unsigned getAdrLabelOpValue(const MachineInstr &MI, unsigned Op)
173      const { return 0; }
174    unsigned getThumbAdrLabelOpValue(const MachineInstr &MI, unsigned Op)
175      const { return 0; }
176    unsigned getThumbBLTargetOpValue(const MachineInstr &MI, unsigned Op)
177      const { return 0; }
178    unsigned getThumbBLXTargetOpValue(const MachineInstr &MI, unsigned Op)
179      const { return 0; }
180    unsigned getThumbBRTargetOpValue(const MachineInstr &MI, unsigned Op)
181      const { return 0; }
182    unsigned getThumbBCCTargetOpValue(const MachineInstr &MI, unsigned Op)
183      const { return 0; }
184    unsigned getThumbCBTargetOpValue(const MachineInstr &MI, unsigned Op)
185      const { return 0; }
186    unsigned getBranchTargetOpValue(const MachineInstr &MI, unsigned Op)
187      const { return 0; }
188    unsigned getUnconditionalBranchTargetOpValue(const MachineInstr &MI,
189      unsigned Op) const { return 0; }
190    unsigned getARMBranchTargetOpValue(const MachineInstr &MI, unsigned Op)
191      const { return 0; }
192    unsigned getCCOutOpValue(const MachineInstr &MI, unsigned Op)
193      const { return 0; }
194    unsigned getSOImmOpValue(const MachineInstr &MI, unsigned Op)
195      const { return 0; }
196    unsigned getT2SOImmOpValue(const MachineInstr &MI, unsigned Op)
197      const { return 0; }
198    unsigned getSORegRegOpValue(const MachineInstr &MI, unsigned Op)
199      const { return 0; }
200    unsigned getSORegImmOpValue(const MachineInstr &MI, unsigned Op)
201      const { return 0; }
202    unsigned getThumbAddrModeRegRegOpValue(const MachineInstr &MI, unsigned Op)
203      const { return 0; }
204    unsigned getT2AddrModeImm12OpValue(const MachineInstr &MI, unsigned Op)
205      const { return 0; }
206    unsigned getT2AddrModeImm8OpValue(const MachineInstr &MI, unsigned Op)
207      const { return 0; }
208    unsigned getT2AddrModeImm8s4OpValue(const MachineInstr &MI, unsigned Op)
209      const { return 0; }
210    unsigned getT2AddrModeImm8OffsetOpValue(const MachineInstr &MI, unsigned Op)
211      const { return 0; }
212    unsigned getT2AddrModeImm12OffsetOpValue(const MachineInstr &MI,unsigned Op)
213      const { return 0; }
214    unsigned getT2AddrModeSORegOpValue(const MachineInstr &MI, unsigned Op)
215      const { return 0; }
216    unsigned getT2SORegOpValue(const MachineInstr &MI, unsigned Op)
217      const { return 0; }
218    unsigned getT2AdrLabelOpValue(const MachineInstr &MI, unsigned Op)
219      const { return 0; }
220    unsigned getAddrMode6AddressOpValue(const MachineInstr &MI, unsigned Op)
221      const { return 0; }
222    unsigned getAddrMode6OneLane32AddressOpValue(const MachineInstr &MI,
223                                                 unsigned Op)
224      const { return 0; }
225    unsigned getAddrMode6DupAddressOpValue(const MachineInstr &MI, unsigned Op)
226      const { return 0; }
227    unsigned getAddrMode6OffsetOpValue(const MachineInstr &MI, unsigned Op)
228      const { return 0; }
229    unsigned getBitfieldInvertedMaskOpValue(const MachineInstr &MI,
230                                            unsigned Op) const { return 0; }
231    unsigned getMsbOpValue(const MachineInstr &MI,
232                           unsigned Op) const { return 0; }
233    unsigned getSsatBitPosValue(const MachineInstr &MI,
234                                unsigned Op) const { return 0; }
235    uint32_t getLdStmModeOpValue(const MachineInstr &MI, unsigned OpIdx)
236      const {return 0; }
237    uint32_t getLdStSORegOpValue(const MachineInstr &MI, unsigned OpIdx)
238      const { return 0; }
239
240    unsigned getAddrModeImm12OpValue(const MachineInstr &MI, unsigned Op)
241      const {
242      // {17-13} = reg
243      // {12}    = (U)nsigned (add == '1', sub == '0')
244      // {11-0}  = imm12
245      const MachineOperand &MO  = MI.getOperand(Op);
246      const MachineOperand &MO1 = MI.getOperand(Op + 1);
247      if (!MO.isReg()) {
248        emitConstPoolAddress(MO.getIndex(), ARM::reloc_arm_cp_entry);
249        return 0;
250      }
251      unsigned Reg = getARMRegisterNumbering(MO.getReg());
252      int32_t Imm12 = MO1.getImm();
253      uint32_t Binary;
254      Binary = Imm12 & 0xfff;
255      if (Imm12 >= 0)
256        Binary |= (1 << 12);
257      Binary |= (Reg << 13);
258      return Binary;
259    }
260
261    unsigned getHiLo16ImmOpValue(const MachineInstr &MI, unsigned Op) const {
262      return 0;
263    }
264
265    uint32_t getAddrMode2OpValue(const MachineInstr &MI, unsigned OpIdx)
266      const { return 0;}
267    uint32_t getAddrMode2OffsetOpValue(const MachineInstr &MI, unsigned OpIdx)
268      const { return 0;}
269    uint32_t getPostIdxRegOpValue(const MachineInstr &MI, unsigned OpIdx)
270      const { return 0;}
271    uint32_t getAddrMode3OffsetOpValue(const MachineInstr &MI, unsigned OpIdx)
272      const { return 0;}
273    uint32_t getAddrMode3OpValue(const MachineInstr &MI, unsigned Op)
274      const { return 0; }
275    uint32_t getAddrModeThumbSPOpValue(const MachineInstr &MI, unsigned Op)
276      const { return 0; }
277    uint32_t getAddrModeSOpValue(const MachineInstr &MI, unsigned Op)
278      const { return 0; }
279    uint32_t getAddrModeISOpValue(const MachineInstr &MI, unsigned Op)
280      const { return 0; }
281    uint32_t getAddrModePCOpValue(const MachineInstr &MI, unsigned Op)
282      const { return 0; }
283    uint32_t getAddrMode5OpValue(const MachineInstr &MI, unsigned Op) const {
284      // {17-13} = reg
285      // {12}    = (U)nsigned (add == '1', sub == '0')
286      // {11-0}  = imm12
287      const MachineOperand &MO  = MI.getOperand(Op);
288      const MachineOperand &MO1 = MI.getOperand(Op + 1);
289      if (!MO.isReg()) {
290        emitConstPoolAddress(MO.getIndex(), ARM::reloc_arm_cp_entry);
291        return 0;
292      }
293      unsigned Reg = getARMRegisterNumbering(MO.getReg());
294      int32_t Imm12 = MO1.getImm();
295
296      // Special value for #-0
297      if (Imm12 == INT32_MIN)
298        Imm12 = 0;
299
300      // Immediate is always encoded as positive. The 'U' bit controls add vs
301      // sub.
302      bool isAdd = true;
303      if (Imm12 < 0) {
304        Imm12 = -Imm12;
305        isAdd = false;
306      }
307
308      uint32_t Binary = Imm12 & 0xfff;
309      if (isAdd)
310        Binary |= (1 << 12);
311      Binary |= (Reg << 13);
312      return Binary;
313    }
314    unsigned getNEONVcvtImm32OpValue(const MachineInstr &MI, unsigned Op)
315      const { return 0; }
316
317    unsigned getRegisterListOpValue(const MachineInstr &MI, unsigned Op)
318      const { return 0; }
319
320    unsigned getShiftRight8Imm(const MachineInstr &MI, unsigned Op)
321      const { return 0; }
322    unsigned getShiftRight16Imm(const MachineInstr &MI, unsigned Op)
323      const { return 0; }
324    unsigned getShiftRight32Imm(const MachineInstr &MI, unsigned Op)
325      const { return 0; }
326    unsigned getShiftRight64Imm(const MachineInstr &MI, unsigned Op)
327      const { return 0; }
328
329    /// getMovi32Value - Return binary encoding of operand for movw/movt. If the
330    /// machine operand requires relocation, record the relocation and return
331    /// zero.
332    unsigned getMovi32Value(const MachineInstr &MI,const MachineOperand &MO,
333                            unsigned Reloc);
334
335    /// getShiftOp - Return the shift opcode (bit[6:5]) of the immediate value.
336    ///
337    unsigned getShiftOp(unsigned Imm) const ;
338
339    /// Routines that handle operands which add machine relocations which are
340    /// fixed up by the relocation stage.
341    void emitGlobalAddress(const GlobalValue *GV, unsigned Reloc,
342                           bool MayNeedFarStub,  bool Indirect,
343                           intptr_t ACPV = 0) const;
344    void emitExternalSymbolAddress(const char *ES, unsigned Reloc) const;
345    void emitConstPoolAddress(unsigned CPI, unsigned Reloc) const;
346    void emitJumpTableAddress(unsigned JTIndex, unsigned Reloc) const;
347    void emitMachineBasicBlock(MachineBasicBlock *BB, unsigned Reloc,
348                               intptr_t JTBase = 0) const;
349  };
350}
351
352char ARMCodeEmitter::ID = 0;
353
354/// createARMJITCodeEmitterPass - Return a pass that emits the collected ARM
355/// code to the specified MCE object.
356FunctionPass *llvm::createARMJITCodeEmitterPass(ARMBaseTargetMachine &TM,
357                                                JITCodeEmitter &JCE) {
358  return new ARMCodeEmitter(TM, JCE);
359}
360
361bool ARMCodeEmitter::runOnMachineFunction(MachineFunction &MF) {
362  assert((MF.getTarget().getRelocationModel() != Reloc::Default ||
363          MF.getTarget().getRelocationModel() != Reloc::Static) &&
364         "JIT relocation model must be set to static or default!");
365  JTI = ((ARMTargetMachine &)MF.getTarget()).getJITInfo();
366  II = ((const ARMTargetMachine &)MF.getTarget()).getInstrInfo();
367  TD = ((const ARMTargetMachine &)MF.getTarget()).getTargetData();
368  Subtarget = &TM.getSubtarget<ARMSubtarget>();
369  MCPEs = &MF.getConstantPool()->getConstants();
370  MJTEs = 0;
371  if (MF.getJumpTableInfo()) MJTEs = &MF.getJumpTableInfo()->getJumpTables();
372  IsPIC = TM.getRelocationModel() == Reloc::PIC_;
373  IsThumb = MF.getInfo<ARMFunctionInfo>()->isThumbFunction();
374  JTI->Initialize(MF, IsPIC);
375  MMI = &getAnalysis<MachineModuleInfo>();
376  MCE.setModuleInfo(MMI);
377
378  do {
379    DEBUG(errs() << "JITTing function '"
380          << MF.getFunction()->getName() << "'\n");
381    MCE.startFunction(MF);
382    for (MachineFunction::iterator MBB = MF.begin(), E = MF.end();
383         MBB != E; ++MBB) {
384      MCE.StartMachineBasicBlock(MBB);
385      for (MachineBasicBlock::const_iterator I = MBB->begin(), E = MBB->end();
386           I != E; ++I)
387        emitInstruction(*I);
388    }
389  } while (MCE.finishFunction(MF));
390
391  return false;
392}
393
394/// getShiftOp - Return the shift opcode (bit[6:5]) of the immediate value.
395///
396unsigned ARMCodeEmitter::getShiftOp(unsigned Imm) const {
397  switch (ARM_AM::getAM2ShiftOpc(Imm)) {
398  default: llvm_unreachable("Unknown shift opc!");
399  case ARM_AM::asr: return 2;
400  case ARM_AM::lsl: return 0;
401  case ARM_AM::lsr: return 1;
402  case ARM_AM::ror:
403  case ARM_AM::rrx: return 3;
404  }
405  return 0;
406}
407
408/// getMovi32Value - Return binary encoding of operand for movw/movt. If the
409/// machine operand requires relocation, record the relocation and return zero.
410unsigned ARMCodeEmitter::getMovi32Value(const MachineInstr &MI,
411                                        const MachineOperand &MO,
412                                        unsigned Reloc) {
413  assert(((Reloc == ARM::reloc_arm_movt) || (Reloc == ARM::reloc_arm_movw))
414      && "Relocation to this function should be for movt or movw");
415
416  if (MO.isImm())
417    return static_cast<unsigned>(MO.getImm());
418  else if (MO.isGlobal())
419    emitGlobalAddress(MO.getGlobal(), Reloc, true, false);
420  else if (MO.isSymbol())
421    emitExternalSymbolAddress(MO.getSymbolName(), Reloc);
422  else if (MO.isMBB())
423    emitMachineBasicBlock(MO.getMBB(), Reloc);
424  else {
425#ifndef NDEBUG
426    errs() << MO;
427#endif
428    llvm_unreachable("Unsupported operand type for movw/movt");
429  }
430  return 0;
431}
432
433/// getMachineOpValue - Return binary encoding of operand. If the machine
434/// operand requires relocation, record the relocation and return zero.
435unsigned ARMCodeEmitter::getMachineOpValue(const MachineInstr &MI,
436                                           const MachineOperand &MO) const {
437  if (MO.isReg())
438    return getARMRegisterNumbering(MO.getReg());
439  else if (MO.isImm())
440    return static_cast<unsigned>(MO.getImm());
441  else if (MO.isGlobal())
442    emitGlobalAddress(MO.getGlobal(), ARM::reloc_arm_branch, true, false);
443  else if (MO.isSymbol())
444    emitExternalSymbolAddress(MO.getSymbolName(), ARM::reloc_arm_branch);
445  else if (MO.isCPI()) {
446    const MCInstrDesc &MCID = MI.getDesc();
447    // For VFP load, the immediate offset is multiplied by 4.
448    unsigned Reloc =  ((MCID.TSFlags & ARMII::FormMask) == ARMII::VFPLdStFrm)
449      ? ARM::reloc_arm_vfp_cp_entry : ARM::reloc_arm_cp_entry;
450    emitConstPoolAddress(MO.getIndex(), Reloc);
451  } else if (MO.isJTI())
452    emitJumpTableAddress(MO.getIndex(), ARM::reloc_arm_relative);
453  else if (MO.isMBB())
454    emitMachineBasicBlock(MO.getMBB(), ARM::reloc_arm_branch);
455  else
456    llvm_unreachable("Unable to encode MachineOperand!");
457  return 0;
458}
459
460/// emitGlobalAddress - Emit the specified address to the code stream.
461///
462void ARMCodeEmitter::emitGlobalAddress(const GlobalValue *GV, unsigned Reloc,
463                                       bool MayNeedFarStub, bool Indirect,
464                                       intptr_t ACPV) const {
465  MachineRelocation MR = Indirect
466    ? MachineRelocation::getIndirectSymbol(MCE.getCurrentPCOffset(), Reloc,
467                                           const_cast<GlobalValue *>(GV),
468                                           ACPV, MayNeedFarStub)
469    : MachineRelocation::getGV(MCE.getCurrentPCOffset(), Reloc,
470                               const_cast<GlobalValue *>(GV), ACPV,
471                               MayNeedFarStub);
472  MCE.addRelocation(MR);
473}
474
475/// emitExternalSymbolAddress - Arrange for the address of an external symbol to
476/// be emitted to the current location in the function, and allow it to be PC
477/// relative.
478void ARMCodeEmitter::
479emitExternalSymbolAddress(const char *ES, unsigned Reloc) const {
480  MCE.addRelocation(MachineRelocation::getExtSym(MCE.getCurrentPCOffset(),
481                                                 Reloc, ES));
482}
483
484/// emitConstPoolAddress - Arrange for the address of an constant pool
485/// to be emitted to the current location in the function, and allow it to be PC
486/// relative.
487void ARMCodeEmitter::emitConstPoolAddress(unsigned CPI, unsigned Reloc) const {
488  // Tell JIT emitter we'll resolve the address.
489  MCE.addRelocation(MachineRelocation::getConstPool(MCE.getCurrentPCOffset(),
490                                                    Reloc, CPI, 0, true));
491}
492
493/// emitJumpTableAddress - Arrange for the address of a jump table to
494/// be emitted to the current location in the function, and allow it to be PC
495/// relative.
496void ARMCodeEmitter::
497emitJumpTableAddress(unsigned JTIndex, unsigned Reloc) const {
498  MCE.addRelocation(MachineRelocation::getJumpTable(MCE.getCurrentPCOffset(),
499                                                    Reloc, JTIndex, 0, true));
500}
501
502/// emitMachineBasicBlock - Emit the specified address basic block.
503void ARMCodeEmitter::emitMachineBasicBlock(MachineBasicBlock *BB,
504                                           unsigned Reloc,
505                                           intptr_t JTBase) const {
506  MCE.addRelocation(MachineRelocation::getBB(MCE.getCurrentPCOffset(),
507                                             Reloc, BB, JTBase));
508}
509
510void ARMCodeEmitter::emitWordLE(unsigned Binary) {
511  DEBUG(errs() << "  0x";
512        errs().write_hex(Binary) << "\n");
513  MCE.emitWordLE(Binary);
514}
515
516void ARMCodeEmitter::emitDWordLE(uint64_t Binary) {
517  DEBUG(errs() << "  0x";
518        errs().write_hex(Binary) << "\n");
519  MCE.emitDWordLE(Binary);
520}
521
522void ARMCodeEmitter::emitInstruction(const MachineInstr &MI) {
523  DEBUG(errs() << "JIT: " << (void*)MCE.getCurrentPCValue() << ":\t" << MI);
524
525  MCE.processDebugLoc(MI.getDebugLoc(), true);
526
527  ++NumEmitted;  // Keep track of the # of mi's emitted
528  switch (MI.getDesc().TSFlags & ARMII::FormMask) {
529  default: {
530    llvm_unreachable("Unhandled instruction encoding format!");
531    break;
532  }
533  case ARMII::MiscFrm:
534    if (MI.getOpcode() == ARM::LEApcrelJT) {
535      // Materialize jumptable address.
536      emitLEApcrelJTInstruction(MI);
537      break;
538    }
539    llvm_unreachable("Unhandled instruction encoding!");
540    break;
541  case ARMII::Pseudo:
542    emitPseudoInstruction(MI);
543    break;
544  case ARMII::DPFrm:
545  case ARMII::DPSoRegFrm:
546    emitDataProcessingInstruction(MI);
547    break;
548  case ARMII::LdFrm:
549  case ARMII::StFrm:
550    emitLoadStoreInstruction(MI);
551    break;
552  case ARMII::LdMiscFrm:
553  case ARMII::StMiscFrm:
554    emitMiscLoadStoreInstruction(MI);
555    break;
556  case ARMII::LdStMulFrm:
557    emitLoadStoreMultipleInstruction(MI);
558    break;
559  case ARMII::MulFrm:
560    emitMulFrmInstruction(MI);
561    break;
562  case ARMII::ExtFrm:
563    emitExtendInstruction(MI);
564    break;
565  case ARMII::ArithMiscFrm:
566    emitMiscArithInstruction(MI);
567    break;
568  case ARMII::SatFrm:
569    emitSaturateInstruction(MI);
570    break;
571  case ARMII::BrFrm:
572    emitBranchInstruction(MI);
573    break;
574  case ARMII::BrMiscFrm:
575    emitMiscBranchInstruction(MI);
576    break;
577  // VFP instructions.
578  case ARMII::VFPUnaryFrm:
579  case ARMII::VFPBinaryFrm:
580    emitVFPArithInstruction(MI);
581    break;
582  case ARMII::VFPConv1Frm:
583  case ARMII::VFPConv2Frm:
584  case ARMII::VFPConv3Frm:
585  case ARMII::VFPConv4Frm:
586  case ARMII::VFPConv5Frm:
587    emitVFPConversionInstruction(MI);
588    break;
589  case ARMII::VFPLdStFrm:
590    emitVFPLoadStoreInstruction(MI);
591    break;
592  case ARMII::VFPLdStMulFrm:
593    emitVFPLoadStoreMultipleInstruction(MI);
594    break;
595
596  // NEON instructions.
597  case ARMII::NGetLnFrm:
598  case ARMII::NSetLnFrm:
599    emitNEONLaneInstruction(MI);
600    break;
601  case ARMII::NDupFrm:
602    emitNEONDupInstruction(MI);
603    break;
604  case ARMII::N1RegModImmFrm:
605    emitNEON1RegModImmInstruction(MI);
606    break;
607  case ARMII::N2RegFrm:
608    emitNEON2RegInstruction(MI);
609    break;
610  case ARMII::N3RegFrm:
611    emitNEON3RegInstruction(MI);
612    break;
613  }
614  MCE.processDebugLoc(MI.getDebugLoc(), false);
615}
616
617void ARMCodeEmitter::emitConstPoolInstruction(const MachineInstr &MI) {
618  unsigned CPI = MI.getOperand(0).getImm();       // CP instruction index.
619  unsigned CPIndex = MI.getOperand(1).getIndex(); // Actual cp entry index.
620  const MachineConstantPoolEntry &MCPE = (*MCPEs)[CPIndex];
621
622  // Remember the CONSTPOOL_ENTRY address for later relocation.
623  JTI->addConstantPoolEntryAddr(CPI, MCE.getCurrentPCValue());
624
625  // Emit constpool island entry. In most cases, the actual values will be
626  // resolved and relocated after code emission.
627  if (MCPE.isMachineConstantPoolEntry()) {
628    ARMConstantPoolValue *ACPV =
629      static_cast<ARMConstantPoolValue*>(MCPE.Val.MachineCPVal);
630
631    DEBUG(errs() << "  ** ARM constant pool #" << CPI << " @ "
632          << (void*)MCE.getCurrentPCValue() << " " << *ACPV << '\n');
633
634    assert(ACPV->isGlobalValue() && "unsupported constant pool value");
635    const GlobalValue *GV = ACPV->getGV();
636    if (GV) {
637      Reloc::Model RelocM = TM.getRelocationModel();
638      emitGlobalAddress(GV, ARM::reloc_arm_machine_cp_entry,
639                        isa<Function>(GV),
640                        Subtarget->GVIsIndirectSymbol(GV, RelocM),
641                        (intptr_t)ACPV);
642     } else  {
643      emitExternalSymbolAddress(ACPV->getSymbol(), ARM::reloc_arm_absolute);
644    }
645    emitWordLE(0);
646  } else {
647    const Constant *CV = MCPE.Val.ConstVal;
648
649    DEBUG({
650        errs() << "  ** Constant pool #" << CPI << " @ "
651               << (void*)MCE.getCurrentPCValue() << " ";
652        if (const Function *F = dyn_cast<Function>(CV))
653          errs() << F->getName();
654        else
655          errs() << *CV;
656        errs() << '\n';
657      });
658
659    if (const GlobalValue *GV = dyn_cast<GlobalValue>(CV)) {
660      emitGlobalAddress(GV, ARM::reloc_arm_absolute, isa<Function>(GV), false);
661      emitWordLE(0);
662    } else if (const ConstantInt *CI = dyn_cast<ConstantInt>(CV)) {
663      uint32_t Val = uint32_t(*CI->getValue().getRawData());
664      emitWordLE(Val);
665    } else if (const ConstantFP *CFP = dyn_cast<ConstantFP>(CV)) {
666      if (CFP->getType()->isFloatTy())
667        emitWordLE(CFP->getValueAPF().bitcastToAPInt().getZExtValue());
668      else if (CFP->getType()->isDoubleTy())
669        emitDWordLE(CFP->getValueAPF().bitcastToAPInt().getZExtValue());
670      else {
671        llvm_unreachable("Unable to handle this constantpool entry!");
672      }
673    } else {
674      llvm_unreachable("Unable to handle this constantpool entry!");
675    }
676  }
677}
678
679void ARMCodeEmitter::emitMOVi32immInstruction(const MachineInstr &MI) {
680  const MachineOperand &MO0 = MI.getOperand(0);
681  const MachineOperand &MO1 = MI.getOperand(1);
682
683  // Emit the 'movw' instruction.
684  unsigned Binary = 0x30 << 20;  // mov: Insts{27-20} = 0b00110000
685
686  unsigned Lo16 = getMovi32Value(MI, MO1, ARM::reloc_arm_movw) & 0xFFFF;
687
688  // Set the conditional execution predicate.
689  Binary |= II->getPredicate(&MI) << ARMII::CondShift;
690
691  // Encode Rd.
692  Binary |= getMachineOpValue(MI, MO0) << ARMII::RegRdShift;
693
694  // Encode imm16 as imm4:imm12
695  Binary |= Lo16 & 0xFFF; // Insts{11-0} = imm12
696  Binary |= ((Lo16 >> 12) & 0xF) << 16; // Insts{19-16} = imm4
697  emitWordLE(Binary);
698
699  unsigned Hi16 = getMovi32Value(MI, MO1, ARM::reloc_arm_movt) >> 16;
700  // Emit the 'movt' instruction.
701  Binary = 0x34 << 20; // movt: Insts{27-20} = 0b00110100
702
703  // Set the conditional execution predicate.
704  Binary |= II->getPredicate(&MI) << ARMII::CondShift;
705
706  // Encode Rd.
707  Binary |= getMachineOpValue(MI, MO0) << ARMII::RegRdShift;
708
709  // Encode imm16 as imm4:imm1, same as movw above.
710  Binary |= Hi16 & 0xFFF;
711  Binary |= ((Hi16 >> 12) & 0xF) << 16;
712  emitWordLE(Binary);
713}
714
715void ARMCodeEmitter::emitMOVi2piecesInstruction(const MachineInstr &MI) {
716  const MachineOperand &MO0 = MI.getOperand(0);
717  const MachineOperand &MO1 = MI.getOperand(1);
718  assert(MO1.isImm() && ARM_AM::isSOImmTwoPartVal(MO1.getImm()) &&
719                                                  "Not a valid so_imm value!");
720  unsigned V1 = ARM_AM::getSOImmTwoPartFirst(MO1.getImm());
721  unsigned V2 = ARM_AM::getSOImmTwoPartSecond(MO1.getImm());
722
723  // Emit the 'mov' instruction.
724  unsigned Binary = 0xd << 21;  // mov: Insts{24-21} = 0b1101
725
726  // Set the conditional execution predicate.
727  Binary |= II->getPredicate(&MI) << ARMII::CondShift;
728
729  // Encode Rd.
730  Binary |= getMachineOpValue(MI, MO0) << ARMII::RegRdShift;
731
732  // Encode so_imm.
733  // Set bit I(25) to identify this is the immediate form of <shifter_op>
734  Binary |= 1 << ARMII::I_BitShift;
735  Binary |= getMachineSoImmOpValue(V1);
736  emitWordLE(Binary);
737
738  // Now the 'orr' instruction.
739  Binary = 0xc << 21;  // orr: Insts{24-21} = 0b1100
740
741  // Set the conditional execution predicate.
742  Binary |= II->getPredicate(&MI) << ARMII::CondShift;
743
744  // Encode Rd.
745  Binary |= getMachineOpValue(MI, MO0) << ARMII::RegRdShift;
746
747  // Encode Rn.
748  Binary |= getMachineOpValue(MI, MO0) << ARMII::RegRnShift;
749
750  // Encode so_imm.
751  // Set bit I(25) to identify this is the immediate form of <shifter_op>
752  Binary |= 1 << ARMII::I_BitShift;
753  Binary |= getMachineSoImmOpValue(V2);
754  emitWordLE(Binary);
755}
756
757void ARMCodeEmitter::emitLEApcrelJTInstruction(const MachineInstr &MI) {
758  // It's basically add r, pc, (LJTI - $+8)
759
760  const MCInstrDesc &MCID = MI.getDesc();
761
762  // Emit the 'add' instruction.
763  unsigned Binary = 0x4 << 21;  // add: Insts{24-21} = 0b0100
764
765  // Set the conditional execution predicate
766  Binary |= II->getPredicate(&MI) << ARMII::CondShift;
767
768  // Encode S bit if MI modifies CPSR.
769  Binary |= getAddrModeSBit(MI, MCID);
770
771  // Encode Rd.
772  Binary |= getMachineOpValue(MI, 0) << ARMII::RegRdShift;
773
774  // Encode Rn which is PC.
775  Binary |= getARMRegisterNumbering(ARM::PC) << ARMII::RegRnShift;
776
777  // Encode the displacement.
778  Binary |= 1 << ARMII::I_BitShift;
779  emitJumpTableAddress(MI.getOperand(1).getIndex(), ARM::reloc_arm_jt_base);
780
781  emitWordLE(Binary);
782}
783
784void ARMCodeEmitter::emitPseudoMoveInstruction(const MachineInstr &MI) {
785  unsigned Opcode = MI.getDesc().Opcode;
786
787  // Part of binary is determined by TableGn.
788  unsigned Binary = getBinaryCodeForInstr(MI);
789
790  // Set the conditional execution predicate
791  Binary |= II->getPredicate(&MI) << ARMII::CondShift;
792
793  // Encode S bit if MI modifies CPSR.
794  if (Opcode == ARM::MOVsrl_flag || Opcode == ARM::MOVsra_flag)
795    Binary |= 1 << ARMII::S_BitShift;
796
797  // Encode register def if there is one.
798  Binary |= getMachineOpValue(MI, 0) << ARMII::RegRdShift;
799
800  // Encode the shift operation.
801  switch (Opcode) {
802  default: break;
803  case ARM::RRX:
804    // rrx
805    Binary |= 0x6 << 4;
806    break;
807  case ARM::MOVsrl_flag:
808    // lsr #1
809    Binary |= (0x2 << 4) | (1 << 7);
810    break;
811  case ARM::MOVsra_flag:
812    // asr #1
813    Binary |= (0x4 << 4) | (1 << 7);
814    break;
815  }
816
817  // Encode register Rm.
818  Binary |= getMachineOpValue(MI, 1);
819
820  emitWordLE(Binary);
821}
822
823void ARMCodeEmitter::addPCLabel(unsigned LabelID) {
824  DEBUG(errs() << "  ** LPC" << LabelID << " @ "
825        << (void*)MCE.getCurrentPCValue() << '\n');
826  JTI->addPCLabelAddr(LabelID, MCE.getCurrentPCValue());
827}
828
829void ARMCodeEmitter::emitPseudoInstruction(const MachineInstr &MI) {
830  unsigned Opcode = MI.getDesc().Opcode;
831  switch (Opcode) {
832  default:
833    llvm_unreachable("ARMCodeEmitter::emitPseudoInstruction");
834  case ARM::BX_CALL:
835  case ARM::BMOVPCRX_CALL:
836  case ARM::BXr9_CALL:
837  case ARM::BMOVPCRXr9_CALL: {
838    // First emit mov lr, pc
839    unsigned Binary = 0x01a0e00f;
840    Binary |= II->getPredicate(&MI) << ARMII::CondShift;
841    emitWordLE(Binary);
842
843    // and then emit the branch.
844    emitMiscBranchInstruction(MI);
845    break;
846  }
847  case TargetOpcode::INLINEASM: {
848    // We allow inline assembler nodes with empty bodies - they can
849    // implicitly define registers, which is ok for JIT.
850    if (MI.getOperand(0).getSymbolName()[0]) {
851      report_fatal_error("JIT does not support inline asm!");
852    }
853    break;
854  }
855  case TargetOpcode::PROLOG_LABEL:
856  case TargetOpcode::EH_LABEL:
857    MCE.emitLabel(MI.getOperand(0).getMCSymbol());
858    break;
859  case TargetOpcode::IMPLICIT_DEF:
860  case TargetOpcode::KILL:
861    // Do nothing.
862    break;
863  case ARM::CONSTPOOL_ENTRY:
864    emitConstPoolInstruction(MI);
865    break;
866  case ARM::PICADD: {
867    // Remember of the address of the PC label for relocation later.
868    addPCLabel(MI.getOperand(2).getImm());
869    // PICADD is just an add instruction that implicitly read pc.
870    emitDataProcessingInstruction(MI, 0, ARM::PC);
871    break;
872  }
873  case ARM::PICLDR:
874  case ARM::PICLDRB:
875  case ARM::PICSTR:
876  case ARM::PICSTRB: {
877    // Remember of the address of the PC label for relocation later.
878    addPCLabel(MI.getOperand(2).getImm());
879    // These are just load / store instructions that implicitly read pc.
880    emitLoadStoreInstruction(MI, 0, ARM::PC);
881    break;
882  }
883  case ARM::PICLDRH:
884  case ARM::PICLDRSH:
885  case ARM::PICLDRSB:
886  case ARM::PICSTRH: {
887    // Remember of the address of the PC label for relocation later.
888    addPCLabel(MI.getOperand(2).getImm());
889    // These are just load / store instructions that implicitly read pc.
890    emitMiscLoadStoreInstruction(MI, ARM::PC);
891    break;
892  }
893
894  case ARM::MOVi32imm:
895    // Two instructions to materialize a constant.
896    if (Subtarget->hasV6T2Ops())
897      emitMOVi32immInstruction(MI);
898    else
899      emitMOVi2piecesInstruction(MI);
900    break;
901
902  case ARM::LEApcrelJT:
903    // Materialize jumptable address.
904    emitLEApcrelJTInstruction(MI);
905    break;
906  case ARM::RRX:
907  case ARM::MOVsrl_flag:
908  case ARM::MOVsra_flag:
909    emitPseudoMoveInstruction(MI);
910    break;
911  }
912}
913
914unsigned ARMCodeEmitter::getMachineSoRegOpValue(const MachineInstr &MI,
915                                                const MCInstrDesc &MCID,
916                                                const MachineOperand &MO,
917                                                unsigned OpIdx) {
918  unsigned Binary = getMachineOpValue(MI, MO);
919
920  const MachineOperand &MO1 = MI.getOperand(OpIdx + 1);
921  const MachineOperand &MO2 = MI.getOperand(OpIdx + 2);
922  ARM_AM::ShiftOpc SOpc = ARM_AM::getSORegShOp(MO2.getImm());
923
924  // Encode the shift opcode.
925  unsigned SBits = 0;
926  unsigned Rs = MO1.getReg();
927  if (Rs) {
928    // Set shift operand (bit[7:4]).
929    // LSL - 0001
930    // LSR - 0011
931    // ASR - 0101
932    // ROR - 0111
933    // RRX - 0110 and bit[11:8] clear.
934    switch (SOpc) {
935    default: llvm_unreachable("Unknown shift opc!");
936    case ARM_AM::lsl: SBits = 0x1; break;
937    case ARM_AM::lsr: SBits = 0x3; break;
938    case ARM_AM::asr: SBits = 0x5; break;
939    case ARM_AM::ror: SBits = 0x7; break;
940    case ARM_AM::rrx: SBits = 0x6; break;
941    }
942  } else {
943    // Set shift operand (bit[6:4]).
944    // LSL - 000
945    // LSR - 010
946    // ASR - 100
947    // ROR - 110
948    switch (SOpc) {
949    default: llvm_unreachable("Unknown shift opc!");
950    case ARM_AM::lsl: SBits = 0x0; break;
951    case ARM_AM::lsr: SBits = 0x2; break;
952    case ARM_AM::asr: SBits = 0x4; break;
953    case ARM_AM::ror: SBits = 0x6; break;
954    }
955  }
956  Binary |= SBits << 4;
957  if (SOpc == ARM_AM::rrx)
958    return Binary;
959
960  // Encode the shift operation Rs or shift_imm (except rrx).
961  if (Rs) {
962    // Encode Rs bit[11:8].
963    assert(ARM_AM::getSORegOffset(MO2.getImm()) == 0);
964    return Binary | (getARMRegisterNumbering(Rs) << ARMII::RegRsShift);
965  }
966
967  // Encode shift_imm bit[11:7].
968  return Binary | ARM_AM::getSORegOffset(MO2.getImm()) << 7;
969}
970
971unsigned ARMCodeEmitter::getMachineSoImmOpValue(unsigned SoImm) {
972  int SoImmVal = ARM_AM::getSOImmVal(SoImm);
973  assert(SoImmVal != -1 && "Not a valid so_imm value!");
974
975  // Encode rotate_imm.
976  unsigned Binary = (ARM_AM::getSOImmValRot((unsigned)SoImmVal) >> 1)
977    << ARMII::SoRotImmShift;
978
979  // Encode immed_8.
980  Binary |= ARM_AM::getSOImmValImm((unsigned)SoImmVal);
981  return Binary;
982}
983
984unsigned ARMCodeEmitter::getAddrModeSBit(const MachineInstr &MI,
985                                         const MCInstrDesc &MCID) const {
986  for (unsigned i = MI.getNumOperands(), e = MCID.getNumOperands(); i >= e; --i){
987    const MachineOperand &MO = MI.getOperand(i-1);
988    if (MO.isReg() && MO.isDef() && MO.getReg() == ARM::CPSR)
989      return 1 << ARMII::S_BitShift;
990  }
991  return 0;
992}
993
994void ARMCodeEmitter::emitDataProcessingInstruction(const MachineInstr &MI,
995                                                   unsigned ImplicitRd,
996                                                   unsigned ImplicitRn) {
997  const MCInstrDesc &MCID = MI.getDesc();
998
999  // Part of binary is determined by TableGn.
1000  unsigned Binary = getBinaryCodeForInstr(MI);
1001
1002  // Set the conditional execution predicate
1003  Binary |= II->getPredicate(&MI) << ARMII::CondShift;
1004
1005  // Encode S bit if MI modifies CPSR.
1006  Binary |= getAddrModeSBit(MI, MCID);
1007
1008  // Encode register def if there is one.
1009  unsigned NumDefs = MCID.getNumDefs();
1010  unsigned OpIdx = 0;
1011  if (NumDefs)
1012    Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRdShift;
1013  else if (ImplicitRd)
1014    // Special handling for implicit use (e.g. PC).
1015    Binary |= (getARMRegisterNumbering(ImplicitRd) << ARMII::RegRdShift);
1016
1017  if (MCID.Opcode == ARM::MOVi16) {
1018      // Get immediate from MI.
1019      unsigned Lo16 = getMovi32Value(MI, MI.getOperand(OpIdx),
1020                      ARM::reloc_arm_movw);
1021      // Encode imm which is the same as in emitMOVi32immInstruction().
1022      Binary |= Lo16 & 0xFFF;
1023      Binary |= ((Lo16 >> 12) & 0xF) << 16;
1024      emitWordLE(Binary);
1025      return;
1026  } else if(MCID.Opcode == ARM::MOVTi16) {
1027      unsigned Hi16 = (getMovi32Value(MI, MI.getOperand(OpIdx),
1028                       ARM::reloc_arm_movt) >> 16);
1029      Binary |= Hi16 & 0xFFF;
1030      Binary |= ((Hi16 >> 12) & 0xF) << 16;
1031      emitWordLE(Binary);
1032      return;
1033  } else if ((MCID.Opcode == ARM::BFC) || (MCID.Opcode == ARM::BFI)) {
1034      uint32_t v = ~MI.getOperand(2).getImm();
1035      int32_t lsb = CountTrailingZeros_32(v);
1036      int32_t msb = (32 - CountLeadingZeros_32(v)) - 1;
1037      // Instr{20-16} = msb, Instr{11-7} = lsb
1038      Binary |= (msb & 0x1F) << 16;
1039      Binary |= (lsb & 0x1F) << 7;
1040      emitWordLE(Binary);
1041      return;
1042  } else if ((MCID.Opcode == ARM::UBFX) || (MCID.Opcode == ARM::SBFX)) {
1043      // Encode Rn in Instr{0-3}
1044      Binary |= getMachineOpValue(MI, OpIdx++);
1045
1046      uint32_t lsb = MI.getOperand(OpIdx++).getImm();
1047      uint32_t widthm1 = MI.getOperand(OpIdx++).getImm() - 1;
1048
1049      // Instr{20-16} = widthm1, Instr{11-7} = lsb
1050      Binary |= (widthm1 & 0x1F) << 16;
1051      Binary |= (lsb & 0x1F) << 7;
1052      emitWordLE(Binary);
1053      return;
1054  }
1055
1056  // If this is a two-address operand, skip it. e.g. MOVCCr operand 1.
1057  if (MCID.getOperandConstraint(OpIdx, MCOI::TIED_TO) != -1)
1058    ++OpIdx;
1059
1060  // Encode first non-shifter register operand if there is one.
1061  bool isUnary = MCID.TSFlags & ARMII::UnaryDP;
1062  if (!isUnary) {
1063    if (ImplicitRn)
1064      // Special handling for implicit use (e.g. PC).
1065      Binary |= (getARMRegisterNumbering(ImplicitRn) << ARMII::RegRnShift);
1066    else {
1067      Binary |= getMachineOpValue(MI, OpIdx) << ARMII::RegRnShift;
1068      ++OpIdx;
1069    }
1070  }
1071
1072  // Encode shifter operand.
1073  const MachineOperand &MO = MI.getOperand(OpIdx);
1074  if ((MCID.TSFlags & ARMII::FormMask) == ARMII::DPSoRegFrm) {
1075    // Encode SoReg.
1076    emitWordLE(Binary | getMachineSoRegOpValue(MI, MCID, MO, OpIdx));
1077    return;
1078  }
1079
1080  if (MO.isReg()) {
1081    // Encode register Rm.
1082    emitWordLE(Binary | getARMRegisterNumbering(MO.getReg()));
1083    return;
1084  }
1085
1086  // Encode so_imm.
1087  Binary |= getMachineSoImmOpValue((unsigned)MO.getImm());
1088
1089  emitWordLE(Binary);
1090}
1091
1092void ARMCodeEmitter::emitLoadStoreInstruction(const MachineInstr &MI,
1093                                              unsigned ImplicitRd,
1094                                              unsigned ImplicitRn) {
1095  const MCInstrDesc &MCID = MI.getDesc();
1096  unsigned Form = MCID.TSFlags & ARMII::FormMask;
1097  bool IsPrePost = (MCID.TSFlags & ARMII::IndexModeMask) != 0;
1098
1099  // Part of binary is determined by TableGn.
1100  unsigned Binary = getBinaryCodeForInstr(MI);
1101
1102  // If this is an LDRi12, STRi12 or LDRcp, nothing more needs be done.
1103  if (MI.getOpcode() == ARM::LDRi12 || MI.getOpcode() == ARM::LDRcp ||
1104      MI.getOpcode() == ARM::STRi12) {
1105    emitWordLE(Binary);
1106    return;
1107  }
1108
1109  // Set the conditional execution predicate
1110  Binary |= II->getPredicate(&MI) << ARMII::CondShift;
1111
1112  unsigned OpIdx = 0;
1113
1114  // Operand 0 of a pre- and post-indexed store is the address base
1115  // writeback. Skip it.
1116  bool Skipped = false;
1117  if (IsPrePost && Form == ARMII::StFrm) {
1118    ++OpIdx;
1119    Skipped = true;
1120  }
1121
1122  // Set first operand
1123  if (ImplicitRd)
1124    // Special handling for implicit use (e.g. PC).
1125    Binary |= (getARMRegisterNumbering(ImplicitRd) << ARMII::RegRdShift);
1126  else
1127    Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRdShift;
1128
1129  // Set second operand
1130  if (ImplicitRn)
1131    // Special handling for implicit use (e.g. PC).
1132    Binary |= (getARMRegisterNumbering(ImplicitRn) << ARMII::RegRnShift);
1133  else
1134    Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRnShift;
1135
1136  // If this is a two-address operand, skip it. e.g. LDR_PRE.
1137  if (!Skipped && MCID.getOperandConstraint(OpIdx, MCOI::TIED_TO) != -1)
1138    ++OpIdx;
1139
1140  const MachineOperand &MO2 = MI.getOperand(OpIdx);
1141  unsigned AM2Opc = (ImplicitRn == ARM::PC)
1142    ? 0 : MI.getOperand(OpIdx+1).getImm();
1143
1144  // Set bit U(23) according to sign of immed value (positive or negative).
1145  Binary |= ((ARM_AM::getAM2Op(AM2Opc) == ARM_AM::add ? 1 : 0) <<
1146             ARMII::U_BitShift);
1147  if (!MO2.getReg()) { // is immediate
1148    if (ARM_AM::getAM2Offset(AM2Opc))
1149      // Set the value of offset_12 field
1150      Binary |= ARM_AM::getAM2Offset(AM2Opc);
1151    emitWordLE(Binary);
1152    return;
1153  }
1154
1155  // Set bit I(25), because this is not in immediate encoding.
1156  Binary |= 1 << ARMII::I_BitShift;
1157  assert(TargetRegisterInfo::isPhysicalRegister(MO2.getReg()));
1158  // Set bit[3:0] to the corresponding Rm register
1159  Binary |= getARMRegisterNumbering(MO2.getReg());
1160
1161  // If this instr is in scaled register offset/index instruction, set
1162  // shift_immed(bit[11:7]) and shift(bit[6:5]) fields.
1163  if (unsigned ShImm = ARM_AM::getAM2Offset(AM2Opc)) {
1164    Binary |= getShiftOp(AM2Opc) << ARMII::ShiftImmShift;  // shift
1165    Binary |= ShImm              << ARMII::ShiftShift;     // shift_immed
1166  }
1167
1168  emitWordLE(Binary);
1169}
1170
1171void ARMCodeEmitter::emitMiscLoadStoreInstruction(const MachineInstr &MI,
1172                                                  unsigned ImplicitRn) {
1173  const MCInstrDesc &MCID = MI.getDesc();
1174  unsigned Form = MCID.TSFlags & ARMII::FormMask;
1175  bool IsPrePost = (MCID.TSFlags & ARMII::IndexModeMask) != 0;
1176
1177  // Part of binary is determined by TableGn.
1178  unsigned Binary = getBinaryCodeForInstr(MI);
1179
1180  // Set the conditional execution predicate
1181  Binary |= II->getPredicate(&MI) << ARMII::CondShift;
1182
1183  unsigned OpIdx = 0;
1184
1185  // Operand 0 of a pre- and post-indexed store is the address base
1186  // writeback. Skip it.
1187  bool Skipped = false;
1188  if (IsPrePost && Form == ARMII::StMiscFrm) {
1189    ++OpIdx;
1190    Skipped = true;
1191  }
1192
1193  // Set first operand
1194  Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRdShift;
1195
1196  // Skip LDRD and STRD's second operand.
1197  if (MCID.Opcode == ARM::LDRD || MCID.Opcode == ARM::STRD)
1198    ++OpIdx;
1199
1200  // Set second operand
1201  if (ImplicitRn)
1202    // Special handling for implicit use (e.g. PC).
1203    Binary |= (getARMRegisterNumbering(ImplicitRn) << ARMII::RegRnShift);
1204  else
1205    Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRnShift;
1206
1207  // If this is a two-address operand, skip it. e.g. LDRH_POST.
1208  if (!Skipped && MCID.getOperandConstraint(OpIdx, MCOI::TIED_TO) != -1)
1209    ++OpIdx;
1210
1211  const MachineOperand &MO2 = MI.getOperand(OpIdx);
1212  unsigned AM3Opc = (ImplicitRn == ARM::PC)
1213    ? 0 : MI.getOperand(OpIdx+1).getImm();
1214
1215  // Set bit U(23) according to sign of immed value (positive or negative)
1216  Binary |= ((ARM_AM::getAM3Op(AM3Opc) == ARM_AM::add ? 1 : 0) <<
1217             ARMII::U_BitShift);
1218
1219  // If this instr is in register offset/index encoding, set bit[3:0]
1220  // to the corresponding Rm register.
1221  if (MO2.getReg()) {
1222    Binary |= getARMRegisterNumbering(MO2.getReg());
1223    emitWordLE(Binary);
1224    return;
1225  }
1226
1227  // This instr is in immediate offset/index encoding, set bit 22 to 1.
1228  Binary |= 1 << ARMII::AM3_I_BitShift;
1229  if (unsigned ImmOffs = ARM_AM::getAM3Offset(AM3Opc)) {
1230    // Set operands
1231    Binary |= (ImmOffs >> 4) << ARMII::ImmHiShift;  // immedH
1232    Binary |= (ImmOffs & 0xF);                      // immedL
1233  }
1234
1235  emitWordLE(Binary);
1236}
1237
1238static unsigned getAddrModeUPBits(unsigned Mode) {
1239  unsigned Binary = 0;
1240
1241  // Set addressing mode by modifying bits U(23) and P(24)
1242  // IA - Increment after  - bit U = 1 and bit P = 0
1243  // IB - Increment before - bit U = 1 and bit P = 1
1244  // DA - Decrement after  - bit U = 0 and bit P = 0
1245  // DB - Decrement before - bit U = 0 and bit P = 1
1246  switch (Mode) {
1247  default: llvm_unreachable("Unknown addressing sub-mode!");
1248  case ARM_AM::da:                                     break;
1249  case ARM_AM::db: Binary |= 0x1 << ARMII::P_BitShift; break;
1250  case ARM_AM::ia: Binary |= 0x1 << ARMII::U_BitShift; break;
1251  case ARM_AM::ib: Binary |= 0x3 << ARMII::U_BitShift; break;
1252  }
1253
1254  return Binary;
1255}
1256
1257void ARMCodeEmitter::emitLoadStoreMultipleInstruction(const MachineInstr &MI) {
1258  const MCInstrDesc &MCID = MI.getDesc();
1259  bool IsUpdating = (MCID.TSFlags & ARMII::IndexModeMask) != 0;
1260
1261  // Part of binary is determined by TableGn.
1262  unsigned Binary = getBinaryCodeForInstr(MI);
1263
1264  // Set the conditional execution predicate
1265  Binary |= II->getPredicate(&MI) << ARMII::CondShift;
1266
1267  // Skip operand 0 of an instruction with base register update.
1268  unsigned OpIdx = 0;
1269  if (IsUpdating)
1270    ++OpIdx;
1271
1272  // Set base address operand
1273  Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRnShift;
1274
1275  // Set addressing mode by modifying bits U(23) and P(24)
1276  ARM_AM::AMSubMode Mode = ARM_AM::getLoadStoreMultipleSubMode(MI.getOpcode());
1277  Binary |= getAddrModeUPBits(ARM_AM::getAM4SubMode(Mode));
1278
1279  // Set bit W(21)
1280  if (IsUpdating)
1281    Binary |= 0x1 << ARMII::W_BitShift;
1282
1283  // Set registers
1284  for (unsigned i = OpIdx+2, e = MI.getNumOperands(); i != e; ++i) {
1285    const MachineOperand &MO = MI.getOperand(i);
1286    if (!MO.isReg() || MO.isImplicit())
1287      break;
1288    unsigned RegNum = getARMRegisterNumbering(MO.getReg());
1289    assert(TargetRegisterInfo::isPhysicalRegister(MO.getReg()) &&
1290           RegNum < 16);
1291    Binary |= 0x1 << RegNum;
1292  }
1293
1294  emitWordLE(Binary);
1295}
1296
1297void ARMCodeEmitter::emitMulFrmInstruction(const MachineInstr &MI) {
1298  const MCInstrDesc &MCID = MI.getDesc();
1299
1300  // Part of binary is determined by TableGn.
1301  unsigned Binary = getBinaryCodeForInstr(MI);
1302
1303  // Set the conditional execution predicate
1304  Binary |= II->getPredicate(&MI) << ARMII::CondShift;
1305
1306  // Encode S bit if MI modifies CPSR.
1307  Binary |= getAddrModeSBit(MI, MCID);
1308
1309  // 32x32->64bit operations have two destination registers. The number
1310  // of register definitions will tell us if that's what we're dealing with.
1311  unsigned OpIdx = 0;
1312  if (MCID.getNumDefs() == 2)
1313    Binary |= getMachineOpValue (MI, OpIdx++) << ARMII::RegRdLoShift;
1314
1315  // Encode Rd
1316  Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRdHiShift;
1317
1318  // Encode Rm
1319  Binary |= getMachineOpValue(MI, OpIdx++);
1320
1321  // Encode Rs
1322  Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRsShift;
1323
1324  // Many multiple instructions (e.g. MLA) have three src operands. Encode
1325  // it as Rn (for multiply, that's in the same offset as RdLo.
1326  if (MCID.getNumOperands() > OpIdx &&
1327      !MCID.OpInfo[OpIdx].isPredicate() &&
1328      !MCID.OpInfo[OpIdx].isOptionalDef())
1329    Binary |= getMachineOpValue(MI, OpIdx) << ARMII::RegRdLoShift;
1330
1331  emitWordLE(Binary);
1332}
1333
1334void ARMCodeEmitter::emitExtendInstruction(const MachineInstr &MI) {
1335  const MCInstrDesc &MCID = MI.getDesc();
1336
1337  // Part of binary is determined by TableGn.
1338  unsigned Binary = getBinaryCodeForInstr(MI);
1339
1340  // Set the conditional execution predicate
1341  Binary |= II->getPredicate(&MI) << ARMII::CondShift;
1342
1343  unsigned OpIdx = 0;
1344
1345  // Encode Rd
1346  Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRdShift;
1347
1348  const MachineOperand &MO1 = MI.getOperand(OpIdx++);
1349  const MachineOperand &MO2 = MI.getOperand(OpIdx);
1350  if (MO2.isReg()) {
1351    // Two register operand form.
1352    // Encode Rn.
1353    Binary |= getMachineOpValue(MI, MO1) << ARMII::RegRnShift;
1354
1355    // Encode Rm.
1356    Binary |= getMachineOpValue(MI, MO2);
1357    ++OpIdx;
1358  } else {
1359    Binary |= getMachineOpValue(MI, MO1);
1360  }
1361
1362  // Encode rot imm (0, 8, 16, or 24) if it has a rotate immediate operand.
1363  if (MI.getOperand(OpIdx).isImm() &&
1364      !MCID.OpInfo[OpIdx].isPredicate() &&
1365      !MCID.OpInfo[OpIdx].isOptionalDef())
1366    Binary |= (getMachineOpValue(MI, OpIdx) / 8) << ARMII::ExtRotImmShift;
1367
1368  emitWordLE(Binary);
1369}
1370
1371void ARMCodeEmitter::emitMiscArithInstruction(const MachineInstr &MI) {
1372  const MCInstrDesc &MCID = MI.getDesc();
1373
1374  // Part of binary is determined by TableGn.
1375  unsigned Binary = getBinaryCodeForInstr(MI);
1376
1377  // Set the conditional execution predicate
1378  Binary |= II->getPredicate(&MI) << ARMII::CondShift;
1379
1380  // PKH instructions are finished at this point
1381  if (MCID.Opcode == ARM::PKHBT || MCID.Opcode == ARM::PKHTB) {
1382    emitWordLE(Binary);
1383    return;
1384  }
1385
1386  unsigned OpIdx = 0;
1387
1388  // Encode Rd
1389  Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRdShift;
1390
1391  const MachineOperand &MO = MI.getOperand(OpIdx++);
1392  if (OpIdx == MCID.getNumOperands() ||
1393      MCID.OpInfo[OpIdx].isPredicate() ||
1394      MCID.OpInfo[OpIdx].isOptionalDef()) {
1395    // Encode Rm and it's done.
1396    Binary |= getMachineOpValue(MI, MO);
1397    emitWordLE(Binary);
1398    return;
1399  }
1400
1401  // Encode Rn.
1402  Binary |= getMachineOpValue(MI, MO) << ARMII::RegRnShift;
1403
1404  // Encode Rm.
1405  Binary |= getMachineOpValue(MI, OpIdx++);
1406
1407  // Encode shift_imm.
1408  unsigned ShiftAmt = MI.getOperand(OpIdx).getImm();
1409  if (MCID.Opcode == ARM::PKHTB) {
1410    assert(ShiftAmt != 0 && "PKHTB shift_imm is 0!");
1411    if (ShiftAmt == 32)
1412      ShiftAmt = 0;
1413  }
1414  assert(ShiftAmt < 32 && "shift_imm range is 0 to 31!");
1415  Binary |= ShiftAmt << ARMII::ShiftShift;
1416
1417  emitWordLE(Binary);
1418}
1419
1420void ARMCodeEmitter::emitSaturateInstruction(const MachineInstr &MI) {
1421  const MCInstrDesc &MCID = MI.getDesc();
1422
1423  // Part of binary is determined by TableGen.
1424  unsigned Binary = getBinaryCodeForInstr(MI);
1425
1426  // Set the conditional execution predicate
1427  Binary |= II->getPredicate(&MI) << ARMII::CondShift;
1428
1429  // Encode Rd
1430  Binary |= getMachineOpValue(MI, 0) << ARMII::RegRdShift;
1431
1432  // Encode saturate bit position.
1433  unsigned Pos = MI.getOperand(1).getImm();
1434  if (MCID.Opcode == ARM::SSAT || MCID.Opcode == ARM::SSAT16)
1435    Pos -= 1;
1436  assert((Pos < 16 || (Pos < 32 &&
1437                       MCID.Opcode != ARM::SSAT16 &&
1438                       MCID.Opcode != ARM::USAT16)) &&
1439         "saturate bit position out of range");
1440  Binary |= Pos << 16;
1441
1442  // Encode Rm
1443  Binary |= getMachineOpValue(MI, 2);
1444
1445  // Encode shift_imm.
1446  if (MCID.getNumOperands() == 4) {
1447    unsigned ShiftOp = MI.getOperand(3).getImm();
1448    ARM_AM::ShiftOpc Opc = ARM_AM::getSORegShOp(ShiftOp);
1449    if (Opc == ARM_AM::asr)
1450      Binary |= (1 << 6);
1451    unsigned ShiftAmt = MI.getOperand(3).getImm();
1452    if (ShiftAmt == 32 && Opc == ARM_AM::asr)
1453      ShiftAmt = 0;
1454    assert(ShiftAmt < 32 && "shift_imm range is 0 to 31!");
1455    Binary |= ShiftAmt << ARMII::ShiftShift;
1456  }
1457
1458  emitWordLE(Binary);
1459}
1460
1461void ARMCodeEmitter::emitBranchInstruction(const MachineInstr &MI) {
1462  const MCInstrDesc &MCID = MI.getDesc();
1463
1464  if (MCID.Opcode == ARM::TPsoft) {
1465    llvm_unreachable("ARM::TPsoft FIXME"); // FIXME
1466  }
1467
1468  // Part of binary is determined by TableGn.
1469  unsigned Binary = getBinaryCodeForInstr(MI);
1470
1471  // Set the conditional execution predicate
1472  Binary |= II->getPredicate(&MI) << ARMII::CondShift;
1473
1474  // Set signed_immed_24 field
1475  Binary |= getMachineOpValue(MI, 0);
1476
1477  emitWordLE(Binary);
1478}
1479
1480void ARMCodeEmitter::emitInlineJumpTable(unsigned JTIndex) {
1481  // Remember the base address of the inline jump table.
1482  uintptr_t JTBase = MCE.getCurrentPCValue();
1483  JTI->addJumpTableBaseAddr(JTIndex, JTBase);
1484  DEBUG(errs() << "  ** Jump Table #" << JTIndex << " @ " << (void*)JTBase
1485               << '\n');
1486
1487  // Now emit the jump table entries.
1488  const std::vector<MachineBasicBlock*> &MBBs = (*MJTEs)[JTIndex].MBBs;
1489  for (unsigned i = 0, e = MBBs.size(); i != e; ++i) {
1490    if (IsPIC)
1491      // DestBB address - JT base.
1492      emitMachineBasicBlock(MBBs[i], ARM::reloc_arm_pic_jt, JTBase);
1493    else
1494      // Absolute DestBB address.
1495      emitMachineBasicBlock(MBBs[i], ARM::reloc_arm_absolute);
1496    emitWordLE(0);
1497  }
1498}
1499
1500void ARMCodeEmitter::emitMiscBranchInstruction(const MachineInstr &MI) {
1501  const MCInstrDesc &MCID = MI.getDesc();
1502
1503  // Handle jump tables.
1504  if (MCID.Opcode == ARM::BR_JTr || MCID.Opcode == ARM::BR_JTadd) {
1505    // First emit a ldr pc, [] instruction.
1506    emitDataProcessingInstruction(MI, ARM::PC);
1507
1508    // Then emit the inline jump table.
1509    unsigned JTIndex =
1510      (MCID.Opcode == ARM::BR_JTr)
1511      ? MI.getOperand(1).getIndex() : MI.getOperand(2).getIndex();
1512    emitInlineJumpTable(JTIndex);
1513    return;
1514  } else if (MCID.Opcode == ARM::BR_JTm) {
1515    // First emit a ldr pc, [] instruction.
1516    emitLoadStoreInstruction(MI, ARM::PC);
1517
1518    // Then emit the inline jump table.
1519    emitInlineJumpTable(MI.getOperand(3).getIndex());
1520    return;
1521  }
1522
1523  // Part of binary is determined by TableGn.
1524  unsigned Binary = getBinaryCodeForInstr(MI);
1525
1526  // Set the conditional execution predicate
1527  Binary |= II->getPredicate(&MI) << ARMII::CondShift;
1528
1529  if (MCID.Opcode == ARM::BX_RET || MCID.Opcode == ARM::MOVPCLR)
1530    // The return register is LR.
1531    Binary |= getARMRegisterNumbering(ARM::LR);
1532  else
1533    // otherwise, set the return register
1534    Binary |= getMachineOpValue(MI, 0);
1535
1536  emitWordLE(Binary);
1537}
1538
1539static unsigned encodeVFPRd(const MachineInstr &MI, unsigned OpIdx) {
1540  unsigned RegD = MI.getOperand(OpIdx).getReg();
1541  unsigned Binary = 0;
1542  bool isSPVFP = ARM::SPRRegisterClass->contains(RegD);
1543  RegD = getARMRegisterNumbering(RegD);
1544  if (!isSPVFP)
1545    Binary |=   RegD               << ARMII::RegRdShift;
1546  else {
1547    Binary |= ((RegD & 0x1E) >> 1) << ARMII::RegRdShift;
1548    Binary |=  (RegD & 0x01)       << ARMII::D_BitShift;
1549  }
1550  return Binary;
1551}
1552
1553static unsigned encodeVFPRn(const MachineInstr &MI, unsigned OpIdx) {
1554  unsigned RegN = MI.getOperand(OpIdx).getReg();
1555  unsigned Binary = 0;
1556  bool isSPVFP = ARM::SPRRegisterClass->contains(RegN);
1557  RegN = getARMRegisterNumbering(RegN);
1558  if (!isSPVFP)
1559    Binary |=   RegN               << ARMII::RegRnShift;
1560  else {
1561    Binary |= ((RegN & 0x1E) >> 1) << ARMII::RegRnShift;
1562    Binary |=  (RegN & 0x01)       << ARMII::N_BitShift;
1563  }
1564  return Binary;
1565}
1566
1567static unsigned encodeVFPRm(const MachineInstr &MI, unsigned OpIdx) {
1568  unsigned RegM = MI.getOperand(OpIdx).getReg();
1569  unsigned Binary = 0;
1570  bool isSPVFP = ARM::SPRRegisterClass->contains(RegM);
1571  RegM = getARMRegisterNumbering(RegM);
1572  if (!isSPVFP)
1573    Binary |=   RegM;
1574  else {
1575    Binary |= ((RegM & 0x1E) >> 1);
1576    Binary |=  (RegM & 0x01)       << ARMII::M_BitShift;
1577  }
1578  return Binary;
1579}
1580
1581void ARMCodeEmitter::emitVFPArithInstruction(const MachineInstr &MI) {
1582  const MCInstrDesc &MCID = MI.getDesc();
1583
1584  // Part of binary is determined by TableGn.
1585  unsigned Binary = getBinaryCodeForInstr(MI);
1586
1587  // Set the conditional execution predicate
1588  Binary |= II->getPredicate(&MI) << ARMII::CondShift;
1589
1590  unsigned OpIdx = 0;
1591  assert((Binary & ARMII::D_BitShift) == 0 &&
1592         (Binary & ARMII::N_BitShift) == 0 &&
1593         (Binary & ARMII::M_BitShift) == 0 && "VFP encoding bug!");
1594
1595  // Encode Dd / Sd.
1596  Binary |= encodeVFPRd(MI, OpIdx++);
1597
1598  // If this is a two-address operand, skip it, e.g. FMACD.
1599  if (MCID.getOperandConstraint(OpIdx, MCOI::TIED_TO) != -1)
1600    ++OpIdx;
1601
1602  // Encode Dn / Sn.
1603  if ((MCID.TSFlags & ARMII::FormMask) == ARMII::VFPBinaryFrm)
1604    Binary |= encodeVFPRn(MI, OpIdx++);
1605
1606  if (OpIdx == MCID.getNumOperands() ||
1607      MCID.OpInfo[OpIdx].isPredicate() ||
1608      MCID.OpInfo[OpIdx].isOptionalDef()) {
1609    // FCMPEZD etc. has only one operand.
1610    emitWordLE(Binary);
1611    return;
1612  }
1613
1614  // Encode Dm / Sm.
1615  Binary |= encodeVFPRm(MI, OpIdx);
1616
1617  emitWordLE(Binary);
1618}
1619
1620void ARMCodeEmitter::emitVFPConversionInstruction(const MachineInstr &MI) {
1621  const MCInstrDesc &MCID = MI.getDesc();
1622  unsigned Form = MCID.TSFlags & ARMII::FormMask;
1623
1624  // Part of binary is determined by TableGn.
1625  unsigned Binary = getBinaryCodeForInstr(MI);
1626
1627  // Set the conditional execution predicate
1628  Binary |= II->getPredicate(&MI) << ARMII::CondShift;
1629
1630  switch (Form) {
1631  default: break;
1632  case ARMII::VFPConv1Frm:
1633  case ARMII::VFPConv2Frm:
1634  case ARMII::VFPConv3Frm:
1635    // Encode Dd / Sd.
1636    Binary |= encodeVFPRd(MI, 0);
1637    break;
1638  case ARMII::VFPConv4Frm:
1639    // Encode Dn / Sn.
1640    Binary |= encodeVFPRn(MI, 0);
1641    break;
1642  case ARMII::VFPConv5Frm:
1643    // Encode Dm / Sm.
1644    Binary |= encodeVFPRm(MI, 0);
1645    break;
1646  }
1647
1648  switch (Form) {
1649  default: break;
1650  case ARMII::VFPConv1Frm:
1651    // Encode Dm / Sm.
1652    Binary |= encodeVFPRm(MI, 1);
1653    break;
1654  case ARMII::VFPConv2Frm:
1655  case ARMII::VFPConv3Frm:
1656    // Encode Dn / Sn.
1657    Binary |= encodeVFPRn(MI, 1);
1658    break;
1659  case ARMII::VFPConv4Frm:
1660  case ARMII::VFPConv5Frm:
1661    // Encode Dd / Sd.
1662    Binary |= encodeVFPRd(MI, 1);
1663    break;
1664  }
1665
1666  if (Form == ARMII::VFPConv5Frm)
1667    // Encode Dn / Sn.
1668    Binary |= encodeVFPRn(MI, 2);
1669  else if (Form == ARMII::VFPConv3Frm)
1670    // Encode Dm / Sm.
1671    Binary |= encodeVFPRm(MI, 2);
1672
1673  emitWordLE(Binary);
1674}
1675
1676void ARMCodeEmitter::emitVFPLoadStoreInstruction(const MachineInstr &MI) {
1677  // Part of binary is determined by TableGn.
1678  unsigned Binary = getBinaryCodeForInstr(MI);
1679
1680  // Set the conditional execution predicate
1681  Binary |= II->getPredicate(&MI) << ARMII::CondShift;
1682
1683  unsigned OpIdx = 0;
1684
1685  // Encode Dd / Sd.
1686  Binary |= encodeVFPRd(MI, OpIdx++);
1687
1688  // Encode address base.
1689  const MachineOperand &Base = MI.getOperand(OpIdx++);
1690  Binary |= getMachineOpValue(MI, Base) << ARMII::RegRnShift;
1691
1692  // If there is a non-zero immediate offset, encode it.
1693  if (Base.isReg()) {
1694    const MachineOperand &Offset = MI.getOperand(OpIdx);
1695    if (unsigned ImmOffs = ARM_AM::getAM5Offset(Offset.getImm())) {
1696      if (ARM_AM::getAM5Op(Offset.getImm()) == ARM_AM::add)
1697        Binary |= 1 << ARMII::U_BitShift;
1698      Binary |= ImmOffs;
1699      emitWordLE(Binary);
1700      return;
1701    }
1702  }
1703
1704  // If immediate offset is omitted, default to +0.
1705  Binary |= 1 << ARMII::U_BitShift;
1706
1707  emitWordLE(Binary);
1708}
1709
1710void
1711ARMCodeEmitter::emitVFPLoadStoreMultipleInstruction(const MachineInstr &MI) {
1712  const MCInstrDesc &MCID = MI.getDesc();
1713  bool IsUpdating = (MCID.TSFlags & ARMII::IndexModeMask) != 0;
1714
1715  // Part of binary is determined by TableGn.
1716  unsigned Binary = getBinaryCodeForInstr(MI);
1717
1718  // Set the conditional execution predicate
1719  Binary |= II->getPredicate(&MI) << ARMII::CondShift;
1720
1721  // Skip operand 0 of an instruction with base register update.
1722  unsigned OpIdx = 0;
1723  if (IsUpdating)
1724    ++OpIdx;
1725
1726  // Set base address operand
1727  Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRnShift;
1728
1729  // Set addressing mode by modifying bits U(23) and P(24)
1730  ARM_AM::AMSubMode Mode = ARM_AM::getLoadStoreMultipleSubMode(MI.getOpcode());
1731  Binary |= getAddrModeUPBits(ARM_AM::getAM4SubMode(Mode));
1732
1733  // Set bit W(21)
1734  if (IsUpdating)
1735    Binary |= 0x1 << ARMII::W_BitShift;
1736
1737  // First register is encoded in Dd.
1738  Binary |= encodeVFPRd(MI, OpIdx+2);
1739
1740  // Count the number of registers.
1741  unsigned NumRegs = 1;
1742  for (unsigned i = OpIdx+3, e = MI.getNumOperands(); i != e; ++i) {
1743    const MachineOperand &MO = MI.getOperand(i);
1744    if (!MO.isReg() || MO.isImplicit())
1745      break;
1746    ++NumRegs;
1747  }
1748  // Bit 8 will be set if <list> is consecutive 64-bit registers (e.g., D0)
1749  // Otherwise, it will be 0, in the case of 32-bit registers.
1750  if(Binary & 0x100)
1751    Binary |= NumRegs * 2;
1752  else
1753    Binary |= NumRegs;
1754
1755  emitWordLE(Binary);
1756}
1757
1758static unsigned encodeNEONRd(const MachineInstr &MI, unsigned OpIdx) {
1759  unsigned RegD = MI.getOperand(OpIdx).getReg();
1760  unsigned Binary = 0;
1761  RegD = getARMRegisterNumbering(RegD);
1762  Binary |= (RegD & 0xf) << ARMII::RegRdShift;
1763  Binary |= ((RegD >> 4) & 1) << ARMII::D_BitShift;
1764  return Binary;
1765}
1766
1767static unsigned encodeNEONRn(const MachineInstr &MI, unsigned OpIdx) {
1768  unsigned RegN = MI.getOperand(OpIdx).getReg();
1769  unsigned Binary = 0;
1770  RegN = getARMRegisterNumbering(RegN);
1771  Binary |= (RegN & 0xf) << ARMII::RegRnShift;
1772  Binary |= ((RegN >> 4) & 1) << ARMII::N_BitShift;
1773  return Binary;
1774}
1775
1776static unsigned encodeNEONRm(const MachineInstr &MI, unsigned OpIdx) {
1777  unsigned RegM = MI.getOperand(OpIdx).getReg();
1778  unsigned Binary = 0;
1779  RegM = getARMRegisterNumbering(RegM);
1780  Binary |= (RegM & 0xf);
1781  Binary |= ((RegM >> 4) & 1) << ARMII::M_BitShift;
1782  return Binary;
1783}
1784
1785/// convertNEONDataProcToThumb - Convert the ARM mode encoding for a NEON
1786/// data-processing instruction to the corresponding Thumb encoding.
1787static unsigned convertNEONDataProcToThumb(unsigned Binary) {
1788  assert((Binary & 0xfe000000) == 0xf2000000 &&
1789         "not an ARM NEON data-processing instruction");
1790  unsigned UBit = (Binary >> 24) & 1;
1791  return 0xef000000 | (UBit << 28) | (Binary & 0xffffff);
1792}
1793
1794void ARMCodeEmitter::emitNEONLaneInstruction(const MachineInstr &MI) {
1795  unsigned Binary = getBinaryCodeForInstr(MI);
1796
1797  unsigned RegTOpIdx, RegNOpIdx, LnOpIdx;
1798  const MCInstrDesc &MCID = MI.getDesc();
1799  if ((MCID.TSFlags & ARMII::FormMask) == ARMII::NGetLnFrm) {
1800    RegTOpIdx = 0;
1801    RegNOpIdx = 1;
1802    LnOpIdx = 2;
1803  } else { // ARMII::NSetLnFrm
1804    RegTOpIdx = 2;
1805    RegNOpIdx = 0;
1806    LnOpIdx = 3;
1807  }
1808
1809  // Set the conditional execution predicate
1810  Binary |= (IsThumb ? ARMCC::AL : II->getPredicate(&MI)) << ARMII::CondShift;
1811
1812  unsigned RegT = MI.getOperand(RegTOpIdx).getReg();
1813  RegT = getARMRegisterNumbering(RegT);
1814  Binary |= (RegT << ARMII::RegRdShift);
1815  Binary |= encodeNEONRn(MI, RegNOpIdx);
1816
1817  unsigned LaneShift;
1818  if ((Binary & (1 << 22)) != 0)
1819    LaneShift = 0; // 8-bit elements
1820  else if ((Binary & (1 << 5)) != 0)
1821    LaneShift = 1; // 16-bit elements
1822  else
1823    LaneShift = 2; // 32-bit elements
1824
1825  unsigned Lane = MI.getOperand(LnOpIdx).getImm() << LaneShift;
1826  unsigned Opc1 = Lane >> 2;
1827  unsigned Opc2 = Lane & 3;
1828  assert((Opc1 & 3) == 0 && "out-of-range lane number operand");
1829  Binary |= (Opc1 << 21);
1830  Binary |= (Opc2 << 5);
1831
1832  emitWordLE(Binary);
1833}
1834
1835void ARMCodeEmitter::emitNEONDupInstruction(const MachineInstr &MI) {
1836  unsigned Binary = getBinaryCodeForInstr(MI);
1837
1838  // Set the conditional execution predicate
1839  Binary |= (IsThumb ? ARMCC::AL : II->getPredicate(&MI)) << ARMII::CondShift;
1840
1841  unsigned RegT = MI.getOperand(1).getReg();
1842  RegT = getARMRegisterNumbering(RegT);
1843  Binary |= (RegT << ARMII::RegRdShift);
1844  Binary |= encodeNEONRn(MI, 0);
1845  emitWordLE(Binary);
1846}
1847
1848void ARMCodeEmitter::emitNEON1RegModImmInstruction(const MachineInstr &MI) {
1849  unsigned Binary = getBinaryCodeForInstr(MI);
1850  // Destination register is encoded in Dd.
1851  Binary |= encodeNEONRd(MI, 0);
1852  // Immediate fields: Op, Cmode, I, Imm3, Imm4
1853  unsigned Imm = MI.getOperand(1).getImm();
1854  unsigned Op = (Imm >> 12) & 1;
1855  unsigned Cmode = (Imm >> 8) & 0xf;
1856  unsigned I = (Imm >> 7) & 1;
1857  unsigned Imm3 = (Imm >> 4) & 0x7;
1858  unsigned Imm4 = Imm & 0xf;
1859  Binary |= (I << 24) | (Imm3 << 16) | (Cmode << 8) | (Op << 5) | Imm4;
1860  if (IsThumb)
1861    Binary = convertNEONDataProcToThumb(Binary);
1862  emitWordLE(Binary);
1863}
1864
1865void ARMCodeEmitter::emitNEON2RegInstruction(const MachineInstr &MI) {
1866  const MCInstrDesc &MCID = MI.getDesc();
1867  unsigned Binary = getBinaryCodeForInstr(MI);
1868  // Destination register is encoded in Dd; source register in Dm.
1869  unsigned OpIdx = 0;
1870  Binary |= encodeNEONRd(MI, OpIdx++);
1871  if (MCID.getOperandConstraint(OpIdx, MCOI::TIED_TO) != -1)
1872    ++OpIdx;
1873  Binary |= encodeNEONRm(MI, OpIdx);
1874  if (IsThumb)
1875    Binary = convertNEONDataProcToThumb(Binary);
1876  // FIXME: This does not handle VDUPfdf or VDUPfqf.
1877  emitWordLE(Binary);
1878}
1879
1880void ARMCodeEmitter::emitNEON3RegInstruction(const MachineInstr &MI) {
1881  const MCInstrDesc &MCID = MI.getDesc();
1882  unsigned Binary = getBinaryCodeForInstr(MI);
1883  // Destination register is encoded in Dd; source registers in Dn and Dm.
1884  unsigned OpIdx = 0;
1885  Binary |= encodeNEONRd(MI, OpIdx++);
1886  if (MCID.getOperandConstraint(OpIdx, MCOI::TIED_TO) != -1)
1887    ++OpIdx;
1888  Binary |= encodeNEONRn(MI, OpIdx++);
1889  if (MCID.getOperandConstraint(OpIdx, MCOI::TIED_TO) != -1)
1890    ++OpIdx;
1891  Binary |= encodeNEONRm(MI, OpIdx);
1892  if (IsThumb)
1893    Binary = convertNEONDataProcToThumb(Binary);
1894  // FIXME: This does not handle VMOVDneon or VMOVQ.
1895  emitWordLE(Binary);
1896}
1897
1898#include "ARMGenCodeEmitter.inc"
1899