ARMCodeEmitter.cpp revision 713ff84d1467c64ad625681baa355b49bcc44ca3 
1//===-- ARM/ARMCodeEmitter.cpp - Convert ARM code to machine code ---------===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file contains the pass that transforms the ARM machine instructions into
11// relocatable machine code.
12//
13//===----------------------------------------------------------------------===//
14
15#define DEBUG_TYPE "jit"
16#include "ARM.h"
17#include "ARMAddressingModes.h"
18#include "ARMConstantPoolValue.h"
19#include "ARMInstrInfo.h"
20#include "ARMRelocations.h"
21#include "ARMSubtarget.h"
22#include "ARMTargetMachine.h"
23#include "llvm/Constants.h"
24#include "llvm/DerivedTypes.h"
25#include "llvm/Function.h"
26#include "llvm/PassManager.h"
27#include "llvm/CodeGen/MachineCodeEmitter.h"
28#include "llvm/CodeGen/JITCodeEmitter.h"
29#include "llvm/CodeGen/ObjectCodeEmitter.h"
30#include "llvm/CodeGen/MachineConstantPool.h"
31#include "llvm/CodeGen/MachineFunctionPass.h"
32#include "llvm/CodeGen/MachineInstr.h"
33#include "llvm/CodeGen/MachineJumpTableInfo.h"
34#include "llvm/CodeGen/MachineModuleInfo.h"
35#include "llvm/CodeGen/Passes.h"
36#include "llvm/ADT/Statistic.h"
37#include "llvm/Support/Compiler.h"
38#include "llvm/Support/Debug.h"
39#include "llvm/Support/ErrorHandling.h"
40#include "llvm/Support/raw_ostream.h"
41#ifndef NDEBUG
42#include <iomanip>
43#endif
44using namespace llvm;
45
46STATISTIC(NumEmitted, "Number of machine instructions emitted");
47
48namespace {
49
50  class ARMCodeEmitter {
51  public:
52    /// getBinaryCodeForInstr - This function, generated by the
53    /// CodeEmitterGenerator using TableGen, produces the binary encoding for
54    /// machine instructions.
55    unsigned getBinaryCodeForInstr(const MachineInstr &MI);
56  };
57
58  template<class CodeEmitter>
59  class VISIBILITY_HIDDEN Emitter : public MachineFunctionPass,
60                                    public ARMCodeEmitter {
61    ARMJITInfo                *JTI;
62    const ARMInstrInfo        *II;
63    const TargetData          *TD;
64    const ARMSubtarget        *Subtarget;
65    TargetMachine             &TM;
66    CodeEmitter               &MCE;
67    const std::vector<MachineConstantPoolEntry> *MCPEs;
68    const std::vector<MachineJumpTableEntry> *MJTEs;
69    bool IsPIC;
70
71    void getAnalysisUsage(AnalysisUsage &AU) const {
72      AU.addRequired<MachineModuleInfo>();
73      MachineFunctionPass::getAnalysisUsage(AU);
74    }
75
76  public:
77    static char ID;
78    explicit Emitter(TargetMachine &tm, CodeEmitter &mce)
79      : MachineFunctionPass(&ID), JTI(0), II(0), TD(0), TM(tm),
80      MCE(mce), MCPEs(0), MJTEs(0),
81      IsPIC(TM.getRelocationModel() == Reloc::PIC_) {}
82    Emitter(TargetMachine &tm, CodeEmitter &mce,
83            const ARMInstrInfo &ii, const TargetData &td)
84      : MachineFunctionPass(&ID), JTI(0), II(&ii), TD(&td), TM(tm),
85      MCE(mce), MCPEs(0), MJTEs(0),
86      IsPIC(TM.getRelocationModel() == Reloc::PIC_) {}
87
88    bool runOnMachineFunction(MachineFunction &MF);
89
90    virtual const char *getPassName() const {
91      return "ARM Machine Code Emitter";
92    }
93
94    void emitInstruction(const MachineInstr &MI);
95
96  private:
97
98    void emitWordLE(unsigned Binary);
99
100    void emitDWordLE(uint64_t Binary);
101
102    void emitConstPoolInstruction(const MachineInstr &MI);
103
104    void emitMOVi2piecesInstruction(const MachineInstr &MI);
105
106    void emitLEApcrelJTInstruction(const MachineInstr &MI);
107
108    void emitPseudoMoveInstruction(const MachineInstr &MI);
109
110    void addPCLabel(unsigned LabelID);
111
112    void emitPseudoInstruction(const MachineInstr &MI);
113
114    unsigned getMachineSoRegOpValue(const MachineInstr &MI,
115                                    const TargetInstrDesc &TID,
116                                    const MachineOperand &MO,
117                                    unsigned OpIdx);
118
119    unsigned getMachineSoImmOpValue(unsigned SoImm);
120
121    unsigned getAddrModeSBit(const MachineInstr &MI,
122                             const TargetInstrDesc &TID) const;
123
124    void emitDataProcessingInstruction(const MachineInstr &MI,
125                                       unsigned ImplicitRd = 0,
126                                       unsigned ImplicitRn = 0);
127
128    void emitLoadStoreInstruction(const MachineInstr &MI,
129                                  unsigned ImplicitRd = 0,
130                                  unsigned ImplicitRn = 0);
131
132    void emitMiscLoadStoreInstruction(const MachineInstr &MI,
133                                      unsigned ImplicitRn = 0);
134
135    void emitLoadStoreMultipleInstruction(const MachineInstr &MI);
136
137    void emitMulFrmInstruction(const MachineInstr &MI);
138
139    void emitExtendInstruction(const MachineInstr &MI);
140
141    void emitMiscArithInstruction(const MachineInstr &MI);
142
143    void emitBranchInstruction(const MachineInstr &MI);
144
145    void emitInlineJumpTable(unsigned JTIndex);
146
147    void emitMiscBranchInstruction(const MachineInstr &MI);
148
149    void emitVFPArithInstruction(const MachineInstr &MI);
150
151    void emitVFPConversionInstruction(const MachineInstr &MI);
152
153    void emitVFPLoadStoreInstruction(const MachineInstr &MI);
154
155    void emitVFPLoadStoreMultipleInstruction(const MachineInstr &MI);
156
157    void emitMiscInstruction(const MachineInstr &MI);
158
159    /// getMachineOpValue - Return binary encoding of operand. If the machine
160    /// operand requires relocation, record the relocation and return zero.
161    unsigned getMachineOpValue(const MachineInstr &MI,const MachineOperand &MO);
162    unsigned getMachineOpValue(const MachineInstr &MI, unsigned OpIdx) {
163      return getMachineOpValue(MI, MI.getOperand(OpIdx));
164    }
165
166    /// getShiftOp - Return the shift opcode (bit[6:5]) of the immediate value.
167    ///
168    unsigned getShiftOp(unsigned Imm) const ;
169
170    /// Routines that handle operands which add machine relocations which are
171    /// fixed up by the relocation stage.
172    void emitGlobalAddress(GlobalValue *GV, unsigned Reloc,
173                           bool NeedStub,  bool Indirect, intptr_t ACPV = 0);
174    void emitExternalSymbolAddress(const char *ES, unsigned Reloc);
175    void emitConstPoolAddress(unsigned CPI, unsigned Reloc);
176    void emitJumpTableAddress(unsigned JTIndex, unsigned Reloc);
177    void emitMachineBasicBlock(MachineBasicBlock *BB, unsigned Reloc,
178                               intptr_t JTBase = 0);
179  };
180  template <class CodeEmitter>
181  char Emitter<CodeEmitter>::ID = 0;
182}
183
184/// createARMCodeEmitterPass - Return a pass that emits the collected ARM code
185/// to the specified MCE object.
186
187FunctionPass *llvm::createARMCodeEmitterPass(ARMBaseTargetMachine &TM,
188                                             MachineCodeEmitter &MCE) {
189  return new Emitter<MachineCodeEmitter>(TM, MCE);
190}
191FunctionPass *llvm::createARMJITCodeEmitterPass(ARMBaseTargetMachine &TM,
192                                                JITCodeEmitter &JCE) {
193  return new Emitter<JITCodeEmitter>(TM, JCE);
194}
195FunctionPass *llvm::createARMObjectCodeEmitterPass(ARMBaseTargetMachine &TM,
196                                                   ObjectCodeEmitter &OCE) {
197  return new Emitter<ObjectCodeEmitter>(TM, OCE);
198}
199
200template<class CodeEmitter>
201bool Emitter<CodeEmitter>::runOnMachineFunction(MachineFunction &MF) {
202  assert((MF.getTarget().getRelocationModel() != Reloc::Default ||
203          MF.getTarget().getRelocationModel() != Reloc::Static) &&
204         "JIT relocation model must be set to static or default!");
205  JTI = ((ARMTargetMachine&)MF.getTarget()).getJITInfo();
206  II = ((ARMTargetMachine&)MF.getTarget()).getInstrInfo();
207  TD = ((ARMTargetMachine&)MF.getTarget()).getTargetData();
208  Subtarget = &TM.getSubtarget<ARMSubtarget>();
209  MCPEs = &MF.getConstantPool()->getConstants();
210  MJTEs = &MF.getJumpTableInfo()->getJumpTables();
211  IsPIC = TM.getRelocationModel() == Reloc::PIC_;
212  JTI->Initialize(MF, IsPIC);
213  MCE.setModuleInfo(&getAnalysis<MachineModuleInfo>());
214
215  do {
216    DEBUG(errs() << "JITTing function '"
217          << MF.getFunction()->getName() << "'\n");
218    MCE.startFunction(MF);
219    for (MachineFunction::iterator MBB = MF.begin(), E = MF.end();
220         MBB != E; ++MBB) {
221      MCE.StartMachineBasicBlock(MBB);
222      for (MachineBasicBlock::const_iterator I = MBB->begin(), E = MBB->end();
223           I != E; ++I)
224        emitInstruction(*I);
225    }
226  } while (MCE.finishFunction(MF));
227
228  return false;
229}
230
231/// getShiftOp - Return the shift opcode (bit[6:5]) of the immediate value.
232///
233template<class CodeEmitter>
234unsigned Emitter<CodeEmitter>::getShiftOp(unsigned Imm) const {
235  switch (ARM_AM::getAM2ShiftOpc(Imm)) {
236  default: llvm_unreachable("Unknown shift opc!");
237  case ARM_AM::asr: return 2;
238  case ARM_AM::lsl: return 0;
239  case ARM_AM::lsr: return 1;
240  case ARM_AM::ror:
241  case ARM_AM::rrx: return 3;
242  }
243  return 0;
244}
245
246/// getMachineOpValue - Return binary encoding of operand. If the machine
247/// operand requires relocation, record the relocation and return zero.
248template<class CodeEmitter>
249unsigned Emitter<CodeEmitter>::getMachineOpValue(const MachineInstr &MI,
250                                                 const MachineOperand &MO) {
251  if (MO.isReg())
252    return ARMRegisterInfo::getRegisterNumbering(MO.getReg());
253  else if (MO.isImm())
254    return static_cast<unsigned>(MO.getImm());
255  else if (MO.isGlobal())
256    emitGlobalAddress(MO.getGlobal(), ARM::reloc_arm_branch, true, false);
257  else if (MO.isSymbol())
258    emitExternalSymbolAddress(MO.getSymbolName(), ARM::reloc_arm_branch);
259  else if (MO.isCPI()) {
260    const TargetInstrDesc &TID = MI.getDesc();
261    // For VFP load, the immediate offset is multiplied by 4.
262    unsigned Reloc =  ((TID.TSFlags & ARMII::FormMask) == ARMII::VFPLdStFrm)
263      ? ARM::reloc_arm_vfp_cp_entry : ARM::reloc_arm_cp_entry;
264    emitConstPoolAddress(MO.getIndex(), Reloc);
265  } else if (MO.isJTI())
266    emitJumpTableAddress(MO.getIndex(), ARM::reloc_arm_relative);
267  else if (MO.isMBB())
268    emitMachineBasicBlock(MO.getMBB(), ARM::reloc_arm_branch);
269  else {
270#ifndef NDEBUG
271    errs() << MO;
272#endif
273    llvm_unreachable(0);
274  }
275  return 0;
276}
277
278/// emitGlobalAddress - Emit the specified address to the code stream.
279///
280template<class CodeEmitter>
281void Emitter<CodeEmitter>::emitGlobalAddress(GlobalValue *GV, unsigned Reloc,
282                                             bool NeedStub, bool Indirect,
283                                             intptr_t ACPV) {
284  MachineRelocation MR = Indirect
285    ? MachineRelocation::getIndirectSymbol(MCE.getCurrentPCOffset(), Reloc,
286                                           GV, ACPV, NeedStub)
287    : MachineRelocation::getGV(MCE.getCurrentPCOffset(), Reloc,
288                               GV, ACPV, NeedStub);
289  MCE.addRelocation(MR);
290}
291
292/// emitExternalSymbolAddress - Arrange for the address of an external symbol to
293/// be emitted to the current location in the function, and allow it to be PC
294/// relative.
295template<class CodeEmitter>
296void Emitter<CodeEmitter>::emitExternalSymbolAddress(const char *ES,
297                                                     unsigned Reloc) {
298  MCE.addRelocation(MachineRelocation::getExtSym(MCE.getCurrentPCOffset(),
299                                                 Reloc, ES));
300}
301
302/// emitConstPoolAddress - Arrange for the address of an constant pool
303/// to be emitted to the current location in the function, and allow it to be PC
304/// relative.
305template<class CodeEmitter>
306void Emitter<CodeEmitter>::emitConstPoolAddress(unsigned CPI,
307                                                unsigned Reloc) {
308  // Tell JIT emitter we'll resolve the address.
309  MCE.addRelocation(MachineRelocation::getConstPool(MCE.getCurrentPCOffset(),
310                                                    Reloc, CPI, 0, true));
311}
312
313/// emitJumpTableAddress - Arrange for the address of a jump table to
314/// be emitted to the current location in the function, and allow it to be PC
315/// relative.
316template<class CodeEmitter>
317void Emitter<CodeEmitter>::emitJumpTableAddress(unsigned JTIndex,
318                                                unsigned Reloc) {
319  MCE.addRelocation(MachineRelocation::getJumpTable(MCE.getCurrentPCOffset(),
320                                                    Reloc, JTIndex, 0, true));
321}
322
323/// emitMachineBasicBlock - Emit the specified address basic block.
324template<class CodeEmitter>
325void Emitter<CodeEmitter>::emitMachineBasicBlock(MachineBasicBlock *BB,
326                                              unsigned Reloc, intptr_t JTBase) {
327  MCE.addRelocation(MachineRelocation::getBB(MCE.getCurrentPCOffset(),
328                                             Reloc, BB, JTBase));
329}
330
331template<class CodeEmitter>
332void Emitter<CodeEmitter>::emitWordLE(unsigned Binary) {
333  DEBUG(errs() << "  0x";
334        errs().write_hex(Binary) << "\n");
335  MCE.emitWordLE(Binary);
336}
337
338template<class CodeEmitter>
339void Emitter<CodeEmitter>::emitDWordLE(uint64_t Binary) {
340  DEBUG(errs() << "  0x";
341        errs().write_hex(Binary) << "\n");
342  MCE.emitDWordLE(Binary);
343}
344
345template<class CodeEmitter>
346void Emitter<CodeEmitter>::emitInstruction(const MachineInstr &MI) {
347  DEBUG(errs() << "JIT: " << (void*)MCE.getCurrentPCValue() << ":\t" << MI);
348
349  MCE.processDebugLoc(MI.getDebugLoc());
350
351  NumEmitted++;  // Keep track of the # of mi's emitted
352  switch (MI.getDesc().TSFlags & ARMII::FormMask) {
353  default: {
354    llvm_unreachable("Unhandled instruction encoding format!");
355    break;
356  }
357  case ARMII::Pseudo:
358    emitPseudoInstruction(MI);
359    break;
360  case ARMII::DPFrm:
361  case ARMII::DPSoRegFrm:
362    emitDataProcessingInstruction(MI);
363    break;
364  case ARMII::LdFrm:
365  case ARMII::StFrm:
366    emitLoadStoreInstruction(MI);
367    break;
368  case ARMII::LdMiscFrm:
369  case ARMII::StMiscFrm:
370    emitMiscLoadStoreInstruction(MI);
371    break;
372  case ARMII::LdStMulFrm:
373    emitLoadStoreMultipleInstruction(MI);
374    break;
375  case ARMII::MulFrm:
376    emitMulFrmInstruction(MI);
377    break;
378  case ARMII::ExtFrm:
379    emitExtendInstruction(MI);
380    break;
381  case ARMII::ArithMiscFrm:
382    emitMiscArithInstruction(MI);
383    break;
384  case ARMII::BrFrm:
385    emitBranchInstruction(MI);
386    break;
387  case ARMII::BrMiscFrm:
388    emitMiscBranchInstruction(MI);
389    break;
390  // VFP instructions.
391  case ARMII::VFPUnaryFrm:
392  case ARMII::VFPBinaryFrm:
393    emitVFPArithInstruction(MI);
394    break;
395  case ARMII::VFPConv1Frm:
396  case ARMII::VFPConv2Frm:
397  case ARMII::VFPConv3Frm:
398  case ARMII::VFPConv4Frm:
399  case ARMII::VFPConv5Frm:
400    emitVFPConversionInstruction(MI);
401    break;
402  case ARMII::VFPLdStFrm:
403    emitVFPLoadStoreInstruction(MI);
404    break;
405  case ARMII::VFPLdStMulFrm:
406    emitVFPLoadStoreMultipleInstruction(MI);
407    break;
408  case ARMII::VFPMiscFrm:
409    emitMiscInstruction(MI);
410    break;
411  }
412}
413
414template<class CodeEmitter>
415void Emitter<CodeEmitter>::emitConstPoolInstruction(const MachineInstr &MI) {
416  unsigned CPI = MI.getOperand(0).getImm();       // CP instruction index.
417  unsigned CPIndex = MI.getOperand(1).getIndex(); // Actual cp entry index.
418  const MachineConstantPoolEntry &MCPE = (*MCPEs)[CPIndex];
419
420  // Remember the CONSTPOOL_ENTRY address for later relocation.
421  JTI->addConstantPoolEntryAddr(CPI, MCE.getCurrentPCValue());
422
423  // Emit constpool island entry. In most cases, the actual values will be
424  // resolved and relocated after code emission.
425  if (MCPE.isMachineConstantPoolEntry()) {
426    ARMConstantPoolValue *ACPV =
427      static_cast<ARMConstantPoolValue*>(MCPE.Val.MachineCPVal);
428
429    DEBUG(errs() << "  ** ARM constant pool #" << CPI << " @ "
430          << (void*)MCE.getCurrentPCValue() << " " << *ACPV << '\n');
431
432    GlobalValue *GV = ACPV->getGV();
433    if (GV) {
434      Reloc::Model RelocM = TM.getRelocationModel();
435      emitGlobalAddress(GV, ARM::reloc_arm_machine_cp_entry,
436                        isa<Function>(GV),
437                        Subtarget->GVIsIndirectSymbol(GV, RelocM),
438                        (intptr_t)ACPV);
439     } else  {
440      emitExternalSymbolAddress(ACPV->getSymbol(), ARM::reloc_arm_absolute);
441    }
442    emitWordLE(0);
443  } else {
444    Constant *CV = MCPE.Val.ConstVal;
445
446    DEBUG({
447        errs() << "  ** Constant pool #" << CPI << " @ "
448               << (void*)MCE.getCurrentPCValue() << " ";
449        if (const Function *F = dyn_cast<Function>(CV))
450          errs() << F->getName();
451        else
452          errs() << *CV;
453        errs() << '\n';
454      });
455
456    if (GlobalValue *GV = dyn_cast<GlobalValue>(CV)) {
457      emitGlobalAddress(GV, ARM::reloc_arm_absolute, isa<Function>(GV), false);
458      emitWordLE(0);
459    } else if (const ConstantInt *CI = dyn_cast<ConstantInt>(CV)) {
460      uint32_t Val = *(uint32_t*)CI->getValue().getRawData();
461      emitWordLE(Val);
462    } else if (const ConstantFP *CFP = dyn_cast<ConstantFP>(CV)) {
463      if (CFP->getType() == Type::getFloatTy(CFP->getContext()))
464        emitWordLE(CFP->getValueAPF().bitcastToAPInt().getZExtValue());
465      else if (CFP->getType() == Type::getDoubleTy(CFP->getContext()))
466        emitDWordLE(CFP->getValueAPF().bitcastToAPInt().getZExtValue());
467      else {
468        llvm_unreachable("Unable to handle this constantpool entry!");
469      }
470    } else {
471      llvm_unreachable("Unable to handle this constantpool entry!");
472    }
473  }
474}
475
476template<class CodeEmitter>
477void Emitter<CodeEmitter>::emitMOVi2piecesInstruction(const MachineInstr &MI) {
478  const MachineOperand &MO0 = MI.getOperand(0);
479  const MachineOperand &MO1 = MI.getOperand(1);
480  assert(MO1.isImm() && ARM_AM::getSOImmVal(MO1.isImm()) != -1 &&
481                                            "Not a valid so_imm value!");
482  unsigned V1 = ARM_AM::getSOImmTwoPartFirst(MO1.getImm());
483  unsigned V2 = ARM_AM::getSOImmTwoPartSecond(MO1.getImm());
484
485  // Emit the 'mov' instruction.
486  unsigned Binary = 0xd << 21;  // mov: Insts{24-21} = 0b1101
487
488  // Set the conditional execution predicate.
489  Binary |= II->getPredicate(&MI) << ARMII::CondShift;
490
491  // Encode Rd.
492  Binary |= getMachineOpValue(MI, MO0) << ARMII::RegRdShift;
493
494  // Encode so_imm.
495  // Set bit I(25) to identify this is the immediate form of <shifter_op>
496  Binary |= 1 << ARMII::I_BitShift;
497  Binary |= getMachineSoImmOpValue(V1);
498  emitWordLE(Binary);
499
500  // Now the 'orr' instruction.
501  Binary = 0xc << 21;  // orr: Insts{24-21} = 0b1100
502
503  // Set the conditional execution predicate.
504  Binary |= II->getPredicate(&MI) << ARMII::CondShift;
505
506  // Encode Rd.
507  Binary |= getMachineOpValue(MI, MO0) << ARMII::RegRdShift;
508
509  // Encode Rn.
510  Binary |= getMachineOpValue(MI, MO0) << ARMII::RegRnShift;
511
512  // Encode so_imm.
513  // Set bit I(25) to identify this is the immediate form of <shifter_op>
514  Binary |= 1 << ARMII::I_BitShift;
515  Binary |= getMachineSoImmOpValue(V2);
516  emitWordLE(Binary);
517}
518
519template<class CodeEmitter>
520void Emitter<CodeEmitter>::emitLEApcrelJTInstruction(const MachineInstr &MI) {
521  // It's basically add r, pc, (LJTI - $+8)
522
523  const TargetInstrDesc &TID = MI.getDesc();
524
525  // Emit the 'add' instruction.
526  unsigned Binary = 0x4 << 21;  // add: Insts{24-31} = 0b0100
527
528  // Set the conditional execution predicate
529  Binary |= II->getPredicate(&MI) << ARMII::CondShift;
530
531  // Encode S bit if MI modifies CPSR.
532  Binary |= getAddrModeSBit(MI, TID);
533
534  // Encode Rd.
535  Binary |= getMachineOpValue(MI, 0) << ARMII::RegRdShift;
536
537  // Encode Rn which is PC.
538  Binary |= ARMRegisterInfo::getRegisterNumbering(ARM::PC) << ARMII::RegRnShift;
539
540  // Encode the displacement.
541  Binary |= 1 << ARMII::I_BitShift;
542  emitJumpTableAddress(MI.getOperand(1).getIndex(), ARM::reloc_arm_jt_base);
543
544  emitWordLE(Binary);
545}
546
547template<class CodeEmitter>
548void Emitter<CodeEmitter>::emitPseudoMoveInstruction(const MachineInstr &MI) {
549  unsigned Opcode = MI.getDesc().Opcode;
550
551  // Part of binary is determined by TableGn.
552  unsigned Binary = getBinaryCodeForInstr(MI);
553
554  // Set the conditional execution predicate
555  Binary |= II->getPredicate(&MI) << ARMII::CondShift;
556
557  // Encode S bit if MI modifies CPSR.
558  if (Opcode == ARM::MOVsrl_flag || Opcode == ARM::MOVsra_flag)
559    Binary |= 1 << ARMII::S_BitShift;
560
561  // Encode register def if there is one.
562  Binary |= getMachineOpValue(MI, 0) << ARMII::RegRdShift;
563
564  // Encode the shift operation.
565  switch (Opcode) {
566  default: break;
567  case ARM::MOVrx:
568    // rrx
569    Binary |= 0x6 << 4;
570    break;
571  case ARM::MOVsrl_flag:
572    // lsr #1
573    Binary |= (0x2 << 4) | (1 << 7);
574    break;
575  case ARM::MOVsra_flag:
576    // asr #1
577    Binary |= (0x4 << 4) | (1 << 7);
578    break;
579  }
580
581  // Encode register Rm.
582  Binary |= getMachineOpValue(MI, 1);
583
584  emitWordLE(Binary);
585}
586
587template<class CodeEmitter>
588void Emitter<CodeEmitter>::addPCLabel(unsigned LabelID) {
589  DEBUG(errs() << "  ** LPC" << LabelID << " @ "
590        << (void*)MCE.getCurrentPCValue() << '\n');
591  JTI->addPCLabelAddr(LabelID, MCE.getCurrentPCValue());
592}
593
594template<class CodeEmitter>
595void Emitter<CodeEmitter>::emitPseudoInstruction(const MachineInstr &MI) {
596  unsigned Opcode = MI.getDesc().Opcode;
597  switch (Opcode) {
598  default:
599    llvm_unreachable("ARMCodeEmitter::emitPseudoInstruction");
600  // FIXME: Add support for MOVimm32.
601  case TargetInstrInfo::INLINEASM: {
602    // We allow inline assembler nodes with empty bodies - they can
603    // implicitly define registers, which is ok for JIT.
604    if (MI.getOperand(0).getSymbolName()[0]) {
605      llvm_report_error("JIT does not support inline asm!");
606    }
607    break;
608  }
609  case TargetInstrInfo::DBG_LABEL:
610  case TargetInstrInfo::EH_LABEL:
611    MCE.emitLabel(MI.getOperand(0).getImm());
612    break;
613  case TargetInstrInfo::IMPLICIT_DEF:
614  case TargetInstrInfo::KILL:
615  case ARM::DWARF_LOC:
616    // Do nothing.
617    break;
618  case ARM::CONSTPOOL_ENTRY:
619    emitConstPoolInstruction(MI);
620    break;
621  case ARM::PICADD: {
622    // Remember of the address of the PC label for relocation later.
623    addPCLabel(MI.getOperand(2).getImm());
624    // PICADD is just an add instruction that implicitly read pc.
625    emitDataProcessingInstruction(MI, 0, ARM::PC);
626    break;
627  }
628  case ARM::PICLDR:
629  case ARM::PICLDRB:
630  case ARM::PICSTR:
631  case ARM::PICSTRB: {
632    // Remember of the address of the PC label for relocation later.
633    addPCLabel(MI.getOperand(2).getImm());
634    // These are just load / store instructions that implicitly read pc.
635    emitLoadStoreInstruction(MI, 0, ARM::PC);
636    break;
637  }
638  case ARM::PICLDRH:
639  case ARM::PICLDRSH:
640  case ARM::PICLDRSB:
641  case ARM::PICSTRH: {
642    // Remember of the address of the PC label for relocation later.
643    addPCLabel(MI.getOperand(2).getImm());
644    // These are just load / store instructions that implicitly read pc.
645    emitMiscLoadStoreInstruction(MI, ARM::PC);
646    break;
647  }
648  case ARM::MOVi2pieces:
649    // Two instructions to materialize a constant.
650    emitMOVi2piecesInstruction(MI);
651    break;
652  case ARM::LEApcrelJT:
653    // Materialize jumptable address.
654    emitLEApcrelJTInstruction(MI);
655    break;
656  case ARM::MOVrx:
657  case ARM::MOVsrl_flag:
658  case ARM::MOVsra_flag:
659    emitPseudoMoveInstruction(MI);
660    break;
661  }
662}
663
664template<class CodeEmitter>
665unsigned Emitter<CodeEmitter>::getMachineSoRegOpValue(
666                                                const MachineInstr &MI,
667                                                const TargetInstrDesc &TID,
668                                                const MachineOperand &MO,
669                                                unsigned OpIdx) {
670  unsigned Binary = getMachineOpValue(MI, MO);
671
672  const MachineOperand &MO1 = MI.getOperand(OpIdx + 1);
673  const MachineOperand &MO2 = MI.getOperand(OpIdx + 2);
674  ARM_AM::ShiftOpc SOpc = ARM_AM::getSORegShOp(MO2.getImm());
675
676  // Encode the shift opcode.
677  unsigned SBits = 0;
678  unsigned Rs = MO1.getReg();
679  if (Rs) {
680    // Set shift operand (bit[7:4]).
681    // LSL - 0001
682    // LSR - 0011
683    // ASR - 0101
684    // ROR - 0111
685    // RRX - 0110 and bit[11:8] clear.
686    switch (SOpc) {
687    default: llvm_unreachable("Unknown shift opc!");
688    case ARM_AM::lsl: SBits = 0x1; break;
689    case ARM_AM::lsr: SBits = 0x3; break;
690    case ARM_AM::asr: SBits = 0x5; break;
691    case ARM_AM::ror: SBits = 0x7; break;
692    case ARM_AM::rrx: SBits = 0x6; break;
693    }
694  } else {
695    // Set shift operand (bit[6:4]).
696    // LSL - 000
697    // LSR - 010
698    // ASR - 100
699    // ROR - 110
700    switch (SOpc) {
701    default: llvm_unreachable("Unknown shift opc!");
702    case ARM_AM::lsl: SBits = 0x0; break;
703    case ARM_AM::lsr: SBits = 0x2; break;
704    case ARM_AM::asr: SBits = 0x4; break;
705    case ARM_AM::ror: SBits = 0x6; break;
706    }
707  }
708  Binary |= SBits << 4;
709  if (SOpc == ARM_AM::rrx)
710    return Binary;
711
712  // Encode the shift operation Rs or shift_imm (except rrx).
713  if (Rs) {
714    // Encode Rs bit[11:8].
715    assert(ARM_AM::getSORegOffset(MO2.getImm()) == 0);
716    return Binary |
717      (ARMRegisterInfo::getRegisterNumbering(Rs) << ARMII::RegRsShift);
718  }
719
720  // Encode shift_imm bit[11:7].
721  return Binary | ARM_AM::getSORegOffset(MO2.getImm()) << 7;
722}
723
724template<class CodeEmitter>
725unsigned Emitter<CodeEmitter>::getMachineSoImmOpValue(unsigned SoImm) {
726  int SoImmVal = ARM_AM::getSOImmVal(SoImm);
727  assert(SoImmVal != -1 && "Not a valid so_imm value!");
728
729  // Encode rotate_imm.
730  unsigned Binary = (ARM_AM::getSOImmValRot((unsigned)SoImmVal) >> 1)
731    << ARMII::SoRotImmShift;
732
733  // Encode immed_8.
734  Binary |= ARM_AM::getSOImmValImm((unsigned)SoImmVal);
735  return Binary;
736}
737
738template<class CodeEmitter>
739unsigned Emitter<CodeEmitter>::getAddrModeSBit(const MachineInstr &MI,
740                                             const TargetInstrDesc &TID) const {
741  for (unsigned i = MI.getNumOperands(), e = TID.getNumOperands(); i != e; --i){
742    const MachineOperand &MO = MI.getOperand(i-1);
743    if (MO.isReg() && MO.isDef() && MO.getReg() == ARM::CPSR)
744      return 1 << ARMII::S_BitShift;
745  }
746  return 0;
747}
748
749template<class CodeEmitter>
750void Emitter<CodeEmitter>::emitDataProcessingInstruction(
751                                                   const MachineInstr &MI,
752                                                   unsigned ImplicitRd,
753                                                   unsigned ImplicitRn) {
754  const TargetInstrDesc &TID = MI.getDesc();
755
756  if (TID.Opcode == ARM::BFC) {
757    llvm_report_error("ARMv6t2 JIT is not yet supported.");
758  }
759
760  // Part of binary is determined by TableGn.
761  unsigned Binary = getBinaryCodeForInstr(MI);
762
763  // Set the conditional execution predicate
764  Binary |= II->getPredicate(&MI) << ARMII::CondShift;
765
766  // Encode S bit if MI modifies CPSR.
767  Binary |= getAddrModeSBit(MI, TID);
768
769  // Encode register def if there is one.
770  unsigned NumDefs = TID.getNumDefs();
771  unsigned OpIdx = 0;
772  if (NumDefs)
773    Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRdShift;
774  else if (ImplicitRd)
775    // Special handling for implicit use (e.g. PC).
776    Binary |= (ARMRegisterInfo::getRegisterNumbering(ImplicitRd)
777               << ARMII::RegRdShift);
778
779  // If this is a two-address operand, skip it. e.g. MOVCCr operand 1.
780  if (TID.getOperandConstraint(OpIdx, TOI::TIED_TO) != -1)
781    ++OpIdx;
782
783  // Encode first non-shifter register operand if there is one.
784  bool isUnary = TID.TSFlags & ARMII::UnaryDP;
785  if (!isUnary) {
786    if (ImplicitRn)
787      // Special handling for implicit use (e.g. PC).
788      Binary |= (ARMRegisterInfo::getRegisterNumbering(ImplicitRn)
789                 << ARMII::RegRnShift);
790    else {
791      Binary |= getMachineOpValue(MI, OpIdx) << ARMII::RegRnShift;
792      ++OpIdx;
793    }
794  }
795
796  // Encode shifter operand.
797  const MachineOperand &MO = MI.getOperand(OpIdx);
798  if ((TID.TSFlags & ARMII::FormMask) == ARMII::DPSoRegFrm) {
799    // Encode SoReg.
800    emitWordLE(Binary | getMachineSoRegOpValue(MI, TID, MO, OpIdx));
801    return;
802  }
803
804  if (MO.isReg()) {
805    // Encode register Rm.
806    emitWordLE(Binary | ARMRegisterInfo::getRegisterNumbering(MO.getReg()));
807    return;
808  }
809
810  // Encode so_imm.
811  Binary |= getMachineSoImmOpValue((unsigned)MO.getImm());
812
813  emitWordLE(Binary);
814}
815
816template<class CodeEmitter>
817void Emitter<CodeEmitter>::emitLoadStoreInstruction(
818                                              const MachineInstr &MI,
819                                              unsigned ImplicitRd,
820                                              unsigned ImplicitRn) {
821  const TargetInstrDesc &TID = MI.getDesc();
822  unsigned Form = TID.TSFlags & ARMII::FormMask;
823  bool IsPrePost = (TID.TSFlags & ARMII::IndexModeMask) != 0;
824
825  // Part of binary is determined by TableGn.
826  unsigned Binary = getBinaryCodeForInstr(MI);
827
828  // Set the conditional execution predicate
829  Binary |= II->getPredicate(&MI) << ARMII::CondShift;
830
831  unsigned OpIdx = 0;
832
833  // Operand 0 of a pre- and post-indexed store is the address base
834  // writeback. Skip it.
835  bool Skipped = false;
836  if (IsPrePost && Form == ARMII::StFrm) {
837    ++OpIdx;
838    Skipped = true;
839  }
840
841  // Set first operand
842  if (ImplicitRd)
843    // Special handling for implicit use (e.g. PC).
844    Binary |= (ARMRegisterInfo::getRegisterNumbering(ImplicitRd)
845               << ARMII::RegRdShift);
846  else
847    Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRdShift;
848
849  // Set second operand
850  if (ImplicitRn)
851    // Special handling for implicit use (e.g. PC).
852    Binary |= (ARMRegisterInfo::getRegisterNumbering(ImplicitRn)
853               << ARMII::RegRnShift);
854  else
855    Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRnShift;
856
857  // If this is a two-address operand, skip it. e.g. LDR_PRE.
858  if (!Skipped && TID.getOperandConstraint(OpIdx, TOI::TIED_TO) != -1)
859    ++OpIdx;
860
861  const MachineOperand &MO2 = MI.getOperand(OpIdx);
862  unsigned AM2Opc = (ImplicitRn == ARM::PC)
863    ? 0 : MI.getOperand(OpIdx+1).getImm();
864
865  // Set bit U(23) according to sign of immed value (positive or negative).
866  Binary |= ((ARM_AM::getAM2Op(AM2Opc) == ARM_AM::add ? 1 : 0) <<
867             ARMII::U_BitShift);
868  if (!MO2.getReg()) { // is immediate
869    if (ARM_AM::getAM2Offset(AM2Opc))
870      // Set the value of offset_12 field
871      Binary |= ARM_AM::getAM2Offset(AM2Opc);
872    emitWordLE(Binary);
873    return;
874  }
875
876  // Set bit I(25), because this is not in immediate enconding.
877  Binary |= 1 << ARMII::I_BitShift;
878  assert(TargetRegisterInfo::isPhysicalRegister(MO2.getReg()));
879  // Set bit[3:0] to the corresponding Rm register
880  Binary |= ARMRegisterInfo::getRegisterNumbering(MO2.getReg());
881
882  // If this instr is in scaled register offset/index instruction, set
883  // shift_immed(bit[11:7]) and shift(bit[6:5]) fields.
884  if (unsigned ShImm = ARM_AM::getAM2Offset(AM2Opc)) {
885    Binary |= getShiftOp(AM2Opc) << ARMII::ShiftImmShift;  // shift
886    Binary |= ShImm              << ARMII::ShiftShift;     // shift_immed
887  }
888
889  emitWordLE(Binary);
890}
891
892template<class CodeEmitter>
893void Emitter<CodeEmitter>::emitMiscLoadStoreInstruction(const MachineInstr &MI,
894                                                        unsigned ImplicitRn) {
895  const TargetInstrDesc &TID = MI.getDesc();
896  unsigned Form = TID.TSFlags & ARMII::FormMask;
897  bool IsPrePost = (TID.TSFlags & ARMII::IndexModeMask) != 0;
898
899  // Part of binary is determined by TableGn.
900  unsigned Binary = getBinaryCodeForInstr(MI);
901
902  // Set the conditional execution predicate
903  Binary |= II->getPredicate(&MI) << ARMII::CondShift;
904
905  unsigned OpIdx = 0;
906
907  // Operand 0 of a pre- and post-indexed store is the address base
908  // writeback. Skip it.
909  bool Skipped = false;
910  if (IsPrePost && Form == ARMII::StMiscFrm) {
911    ++OpIdx;
912    Skipped = true;
913  }
914
915  // Set first operand
916  Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRdShift;
917
918  // Skip LDRD and STRD's second operand.
919  if (TID.Opcode == ARM::LDRD || TID.Opcode == ARM::STRD)
920    ++OpIdx;
921
922  // Set second operand
923  if (ImplicitRn)
924    // Special handling for implicit use (e.g. PC).
925    Binary |= (ARMRegisterInfo::getRegisterNumbering(ImplicitRn)
926               << ARMII::RegRnShift);
927  else
928    Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRnShift;
929
930  // If this is a two-address operand, skip it. e.g. LDRH_POST.
931  if (!Skipped && TID.getOperandConstraint(OpIdx, TOI::TIED_TO) != -1)
932    ++OpIdx;
933
934  const MachineOperand &MO2 = MI.getOperand(OpIdx);
935  unsigned AM3Opc = (ImplicitRn == ARM::PC)
936    ? 0 : MI.getOperand(OpIdx+1).getImm();
937
938  // Set bit U(23) according to sign of immed value (positive or negative)
939  Binary |= ((ARM_AM::getAM3Op(AM3Opc) == ARM_AM::add ? 1 : 0) <<
940             ARMII::U_BitShift);
941
942  // If this instr is in register offset/index encoding, set bit[3:0]
943  // to the corresponding Rm register.
944  if (MO2.getReg()) {
945    Binary |= ARMRegisterInfo::getRegisterNumbering(MO2.getReg());
946    emitWordLE(Binary);
947    return;
948  }
949
950  // This instr is in immediate offset/index encoding, set bit 22 to 1.
951  Binary |= 1 << ARMII::AM3_I_BitShift;
952  if (unsigned ImmOffs = ARM_AM::getAM3Offset(AM3Opc)) {
953    // Set operands
954    Binary |= (ImmOffs >> 4) << ARMII::ImmHiShift;  // immedH
955    Binary |= (ImmOffs & 0xF);                      // immedL
956  }
957
958  emitWordLE(Binary);
959}
960
961static unsigned getAddrModeUPBits(unsigned Mode) {
962  unsigned Binary = 0;
963
964  // Set addressing mode by modifying bits U(23) and P(24)
965  // IA - Increment after  - bit U = 1 and bit P = 0
966  // IB - Increment before - bit U = 1 and bit P = 1
967  // DA - Decrement after  - bit U = 0 and bit P = 0
968  // DB - Decrement before - bit U = 0 and bit P = 1
969  switch (Mode) {
970  default: llvm_unreachable("Unknown addressing sub-mode!");
971  case ARM_AM::da:                                     break;
972  case ARM_AM::db: Binary |= 0x1 << ARMII::P_BitShift; break;
973  case ARM_AM::ia: Binary |= 0x1 << ARMII::U_BitShift; break;
974  case ARM_AM::ib: Binary |= 0x3 << ARMII::U_BitShift; break;
975  }
976
977  return Binary;
978}
979
980template<class CodeEmitter>
981void Emitter<CodeEmitter>::emitLoadStoreMultipleInstruction(
982                                                       const MachineInstr &MI) {
983  // Part of binary is determined by TableGn.
984  unsigned Binary = getBinaryCodeForInstr(MI);
985
986  // Set the conditional execution predicate
987  Binary |= II->getPredicate(&MI) << ARMII::CondShift;
988
989  // Set base address operand
990  Binary |= getMachineOpValue(MI, 0) << ARMII::RegRnShift;
991
992  // Set addressing mode by modifying bits U(23) and P(24)
993  const MachineOperand &MO = MI.getOperand(1);
994  Binary |= getAddrModeUPBits(ARM_AM::getAM4SubMode(MO.getImm()));
995
996  // Set bit W(21)
997  if (ARM_AM::getAM4WBFlag(MO.getImm()))
998    Binary |= 0x1 << ARMII::W_BitShift;
999
1000  // Set registers
1001  for (unsigned i = 5, e = MI.getNumOperands(); i != e; ++i) {
1002    const MachineOperand &MO = MI.getOperand(i);
1003    if (!MO.isReg() || MO.isImplicit())
1004      break;
1005    unsigned RegNum = ARMRegisterInfo::getRegisterNumbering(MO.getReg());
1006    assert(TargetRegisterInfo::isPhysicalRegister(MO.getReg()) &&
1007           RegNum < 16);
1008    Binary |= 0x1 << RegNum;
1009  }
1010
1011  emitWordLE(Binary);
1012}
1013
1014template<class CodeEmitter>
1015void Emitter<CodeEmitter>::emitMulFrmInstruction(const MachineInstr &MI) {
1016  const TargetInstrDesc &TID = MI.getDesc();
1017
1018  // Part of binary is determined by TableGn.
1019  unsigned Binary = getBinaryCodeForInstr(MI);
1020
1021  // Set the conditional execution predicate
1022  Binary |= II->getPredicate(&MI) << ARMII::CondShift;
1023
1024  // Encode S bit if MI modifies CPSR.
1025  Binary |= getAddrModeSBit(MI, TID);
1026
1027  // 32x32->64bit operations have two destination registers. The number
1028  // of register definitions will tell us if that's what we're dealing with.
1029  unsigned OpIdx = 0;
1030  if (TID.getNumDefs() == 2)
1031    Binary |= getMachineOpValue (MI, OpIdx++) << ARMII::RegRdLoShift;
1032
1033  // Encode Rd
1034  Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRdHiShift;
1035
1036  // Encode Rm
1037  Binary |= getMachineOpValue(MI, OpIdx++);
1038
1039  // Encode Rs
1040  Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRsShift;
1041
1042  // Many multiple instructions (e.g. MLA) have three src operands. Encode
1043  // it as Rn (for multiply, that's in the same offset as RdLo.
1044  if (TID.getNumOperands() > OpIdx &&
1045      !TID.OpInfo[OpIdx].isPredicate() &&
1046      !TID.OpInfo[OpIdx].isOptionalDef())
1047    Binary |= getMachineOpValue(MI, OpIdx) << ARMII::RegRdLoShift;
1048
1049  emitWordLE(Binary);
1050}
1051
1052template<class CodeEmitter>
1053void Emitter<CodeEmitter>::emitExtendInstruction(const MachineInstr &MI) {
1054  const TargetInstrDesc &TID = MI.getDesc();
1055
1056  // Part of binary is determined by TableGn.
1057  unsigned Binary = getBinaryCodeForInstr(MI);
1058
1059  // Set the conditional execution predicate
1060  Binary |= II->getPredicate(&MI) << ARMII::CondShift;
1061
1062  unsigned OpIdx = 0;
1063
1064  // Encode Rd
1065  Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRdShift;
1066
1067  const MachineOperand &MO1 = MI.getOperand(OpIdx++);
1068  const MachineOperand &MO2 = MI.getOperand(OpIdx);
1069  if (MO2.isReg()) {
1070    // Two register operand form.
1071    // Encode Rn.
1072    Binary |= getMachineOpValue(MI, MO1) << ARMII::RegRnShift;
1073
1074    // Encode Rm.
1075    Binary |= getMachineOpValue(MI, MO2);
1076    ++OpIdx;
1077  } else {
1078    Binary |= getMachineOpValue(MI, MO1);
1079  }
1080
1081  // Encode rot imm (0, 8, 16, or 24) if it has a rotate immediate operand.
1082  if (MI.getOperand(OpIdx).isImm() &&
1083      !TID.OpInfo[OpIdx].isPredicate() &&
1084      !TID.OpInfo[OpIdx].isOptionalDef())
1085    Binary |= (getMachineOpValue(MI, OpIdx) / 8) << ARMII::ExtRotImmShift;
1086
1087  emitWordLE(Binary);
1088}
1089
1090template<class CodeEmitter>
1091void Emitter<CodeEmitter>::emitMiscArithInstruction(const MachineInstr &MI) {
1092  const TargetInstrDesc &TID = MI.getDesc();
1093
1094  // Part of binary is determined by TableGn.
1095  unsigned Binary = getBinaryCodeForInstr(MI);
1096
1097  // Set the conditional execution predicate
1098  Binary |= II->getPredicate(&MI) << ARMII::CondShift;
1099
1100  unsigned OpIdx = 0;
1101
1102  // Encode Rd
1103  Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRdShift;
1104
1105  const MachineOperand &MO = MI.getOperand(OpIdx++);
1106  if (OpIdx == TID.getNumOperands() ||
1107      TID.OpInfo[OpIdx].isPredicate() ||
1108      TID.OpInfo[OpIdx].isOptionalDef()) {
1109    // Encode Rm and it's done.
1110    Binary |= getMachineOpValue(MI, MO);
1111    emitWordLE(Binary);
1112    return;
1113  }
1114
1115  // Encode Rn.
1116  Binary |= getMachineOpValue(MI, MO) << ARMII::RegRnShift;
1117
1118  // Encode Rm.
1119  Binary |= getMachineOpValue(MI, OpIdx++);
1120
1121  // Encode shift_imm.
1122  unsigned ShiftAmt = MI.getOperand(OpIdx).getImm();
1123  assert(ShiftAmt < 32 && "shift_imm range is 0 to 31!");
1124  Binary |= ShiftAmt << ARMII::ShiftShift;
1125
1126  emitWordLE(Binary);
1127}
1128
1129template<class CodeEmitter>
1130void Emitter<CodeEmitter>::emitBranchInstruction(const MachineInstr &MI) {
1131  const TargetInstrDesc &TID = MI.getDesc();
1132
1133  if (TID.Opcode == ARM::TPsoft) {
1134    llvm_unreachable("ARM::TPsoft FIXME"); // FIXME
1135  }
1136
1137  // Part of binary is determined by TableGn.
1138  unsigned Binary = getBinaryCodeForInstr(MI);
1139
1140  // Set the conditional execution predicate
1141  Binary |= II->getPredicate(&MI) << ARMII::CondShift;
1142
1143  // Set signed_immed_24 field
1144  Binary |= getMachineOpValue(MI, 0);
1145
1146  emitWordLE(Binary);
1147}
1148
1149template<class CodeEmitter>
1150void Emitter<CodeEmitter>::emitInlineJumpTable(unsigned JTIndex) {
1151  // Remember the base address of the inline jump table.
1152  uintptr_t JTBase = MCE.getCurrentPCValue();
1153  JTI->addJumpTableBaseAddr(JTIndex, JTBase);
1154  DEBUG(errs() << "  ** Jump Table #" << JTIndex << " @ " << (void*)JTBase
1155               << '\n');
1156
1157  // Now emit the jump table entries.
1158  const std::vector<MachineBasicBlock*> &MBBs = (*MJTEs)[JTIndex].MBBs;
1159  for (unsigned i = 0, e = MBBs.size(); i != e; ++i) {
1160    if (IsPIC)
1161      // DestBB address - JT base.
1162      emitMachineBasicBlock(MBBs[i], ARM::reloc_arm_pic_jt, JTBase);
1163    else
1164      // Absolute DestBB address.
1165      emitMachineBasicBlock(MBBs[i], ARM::reloc_arm_absolute);
1166    emitWordLE(0);
1167  }
1168}
1169
1170template<class CodeEmitter>
1171void Emitter<CodeEmitter>::emitMiscBranchInstruction(const MachineInstr &MI) {
1172  const TargetInstrDesc &TID = MI.getDesc();
1173
1174  // Handle jump tables.
1175  if (TID.Opcode == ARM::BR_JTr || TID.Opcode == ARM::BR_JTadd) {
1176    // First emit a ldr pc, [] instruction.
1177    emitDataProcessingInstruction(MI, ARM::PC);
1178
1179    // Then emit the inline jump table.
1180    unsigned JTIndex =
1181      (TID.Opcode == ARM::BR_JTr)
1182      ? MI.getOperand(1).getIndex() : MI.getOperand(2).getIndex();
1183    emitInlineJumpTable(JTIndex);
1184    return;
1185  } else if (TID.Opcode == ARM::BR_JTm) {
1186    // First emit a ldr pc, [] instruction.
1187    emitLoadStoreInstruction(MI, ARM::PC);
1188
1189    // Then emit the inline jump table.
1190    emitInlineJumpTable(MI.getOperand(3).getIndex());
1191    return;
1192  }
1193
1194  // Part of binary is determined by TableGn.
1195  unsigned Binary = getBinaryCodeForInstr(MI);
1196
1197  // Set the conditional execution predicate
1198  Binary |= II->getPredicate(&MI) << ARMII::CondShift;
1199
1200  if (TID.Opcode == ARM::BX_RET)
1201    // The return register is LR.
1202    Binary |= ARMRegisterInfo::getRegisterNumbering(ARM::LR);
1203  else
1204    // otherwise, set the return register
1205    Binary |= getMachineOpValue(MI, 0);
1206
1207  emitWordLE(Binary);
1208}
1209
1210static unsigned encodeVFPRd(const MachineInstr &MI, unsigned OpIdx) {
1211  unsigned RegD = MI.getOperand(OpIdx).getReg();
1212  unsigned Binary = 0;
1213  bool isSPVFP = false;
1214  RegD = ARMRegisterInfo::getRegisterNumbering(RegD, &isSPVFP);
1215  if (!isSPVFP)
1216    Binary |=   RegD               << ARMII::RegRdShift;
1217  else {
1218    Binary |= ((RegD & 0x1E) >> 1) << ARMII::RegRdShift;
1219    Binary |=  (RegD & 0x01)       << ARMII::D_BitShift;
1220  }
1221  return Binary;
1222}
1223
1224static unsigned encodeVFPRn(const MachineInstr &MI, unsigned OpIdx) {
1225  unsigned RegN = MI.getOperand(OpIdx).getReg();
1226  unsigned Binary = 0;
1227  bool isSPVFP = false;
1228  RegN = ARMRegisterInfo::getRegisterNumbering(RegN, &isSPVFP);
1229  if (!isSPVFP)
1230    Binary |=   RegN               << ARMII::RegRnShift;
1231  else {
1232    Binary |= ((RegN & 0x1E) >> 1) << ARMII::RegRnShift;
1233    Binary |=  (RegN & 0x01)       << ARMII::N_BitShift;
1234  }
1235  return Binary;
1236}
1237
1238static unsigned encodeVFPRm(const MachineInstr &MI, unsigned OpIdx) {
1239  unsigned RegM = MI.getOperand(OpIdx).getReg();
1240  unsigned Binary = 0;
1241  bool isSPVFP = false;
1242  RegM = ARMRegisterInfo::getRegisterNumbering(RegM, &isSPVFP);
1243  if (!isSPVFP)
1244    Binary |=   RegM;
1245  else {
1246    Binary |= ((RegM & 0x1E) >> 1);
1247    Binary |=  (RegM & 0x01)       << ARMII::M_BitShift;
1248  }
1249  return Binary;
1250}
1251
1252template<class CodeEmitter>
1253void Emitter<CodeEmitter>::emitVFPArithInstruction(const MachineInstr &MI) {
1254  const TargetInstrDesc &TID = MI.getDesc();
1255
1256  // Part of binary is determined by TableGn.
1257  unsigned Binary = getBinaryCodeForInstr(MI);
1258
1259  // Set the conditional execution predicate
1260  Binary |= II->getPredicate(&MI) << ARMII::CondShift;
1261
1262  unsigned OpIdx = 0;
1263  assert((Binary & ARMII::D_BitShift) == 0 &&
1264         (Binary & ARMII::N_BitShift) == 0 &&
1265         (Binary & ARMII::M_BitShift) == 0 && "VFP encoding bug!");
1266
1267  // Encode Dd / Sd.
1268  Binary |= encodeVFPRd(MI, OpIdx++);
1269
1270  // If this is a two-address operand, skip it, e.g. FMACD.
1271  if (TID.getOperandConstraint(OpIdx, TOI::TIED_TO) != -1)
1272    ++OpIdx;
1273
1274  // Encode Dn / Sn.
1275  if ((TID.TSFlags & ARMII::FormMask) == ARMII::VFPBinaryFrm)
1276    Binary |= encodeVFPRn(MI, OpIdx++);
1277
1278  if (OpIdx == TID.getNumOperands() ||
1279      TID.OpInfo[OpIdx].isPredicate() ||
1280      TID.OpInfo[OpIdx].isOptionalDef()) {
1281    // FCMPEZD etc. has only one operand.
1282    emitWordLE(Binary);
1283    return;
1284  }
1285
1286  // Encode Dm / Sm.
1287  Binary |= encodeVFPRm(MI, OpIdx);
1288
1289  emitWordLE(Binary);
1290}
1291
1292template<class CodeEmitter>
1293void Emitter<CodeEmitter>::emitVFPConversionInstruction(
1294      const MachineInstr &MI) {
1295  const TargetInstrDesc &TID = MI.getDesc();
1296  unsigned Form = TID.TSFlags & ARMII::FormMask;
1297
1298  // Part of binary is determined by TableGn.
1299  unsigned Binary = getBinaryCodeForInstr(MI);
1300
1301  // Set the conditional execution predicate
1302  Binary |= II->getPredicate(&MI) << ARMII::CondShift;
1303
1304  switch (Form) {
1305  default: break;
1306  case ARMII::VFPConv1Frm:
1307  case ARMII::VFPConv2Frm:
1308  case ARMII::VFPConv3Frm:
1309    // Encode Dd / Sd.
1310    Binary |= encodeVFPRd(MI, 0);
1311    break;
1312  case ARMII::VFPConv4Frm:
1313    // Encode Dn / Sn.
1314    Binary |= encodeVFPRn(MI, 0);
1315    break;
1316  case ARMII::VFPConv5Frm:
1317    // Encode Dm / Sm.
1318    Binary |= encodeVFPRm(MI, 0);
1319    break;
1320  }
1321
1322  switch (Form) {
1323  default: break;
1324  case ARMII::VFPConv1Frm:
1325    // Encode Dm / Sm.
1326    Binary |= encodeVFPRm(MI, 1);
1327    break;
1328  case ARMII::VFPConv2Frm:
1329  case ARMII::VFPConv3Frm:
1330    // Encode Dn / Sn.
1331    Binary |= encodeVFPRn(MI, 1);
1332    break;
1333  case ARMII::VFPConv4Frm:
1334  case ARMII::VFPConv5Frm:
1335    // Encode Dd / Sd.
1336    Binary |= encodeVFPRd(MI, 1);
1337    break;
1338  }
1339
1340  if (Form == ARMII::VFPConv5Frm)
1341    // Encode Dn / Sn.
1342    Binary |= encodeVFPRn(MI, 2);
1343  else if (Form == ARMII::VFPConv3Frm)
1344    // Encode Dm / Sm.
1345    Binary |= encodeVFPRm(MI, 2);
1346
1347  emitWordLE(Binary);
1348}
1349
1350template<class CodeEmitter>
1351void Emitter<CodeEmitter>::emitVFPLoadStoreInstruction(const MachineInstr &MI) {
1352  // Part of binary is determined by TableGn.
1353  unsigned Binary = getBinaryCodeForInstr(MI);
1354
1355  // Set the conditional execution predicate
1356  Binary |= II->getPredicate(&MI) << ARMII::CondShift;
1357
1358  unsigned OpIdx = 0;
1359
1360  // Encode Dd / Sd.
1361  Binary |= encodeVFPRd(MI, OpIdx++);
1362
1363  // Encode address base.
1364  const MachineOperand &Base = MI.getOperand(OpIdx++);
1365  Binary |= getMachineOpValue(MI, Base) << ARMII::RegRnShift;
1366
1367  // If there is a non-zero immediate offset, encode it.
1368  if (Base.isReg()) {
1369    const MachineOperand &Offset = MI.getOperand(OpIdx);
1370    if (unsigned ImmOffs = ARM_AM::getAM5Offset(Offset.getImm())) {
1371      if (ARM_AM::getAM5Op(Offset.getImm()) == ARM_AM::add)
1372        Binary |= 1 << ARMII::U_BitShift;
1373      Binary |= ImmOffs;
1374      emitWordLE(Binary);
1375      return;
1376    }
1377  }
1378
1379  // If immediate offset is omitted, default to +0.
1380  Binary |= 1 << ARMII::U_BitShift;
1381
1382  emitWordLE(Binary);
1383}
1384
1385template<class CodeEmitter>
1386void Emitter<CodeEmitter>::emitVFPLoadStoreMultipleInstruction(
1387                                                       const MachineInstr &MI) {
1388  // Part of binary is determined by TableGn.
1389  unsigned Binary = getBinaryCodeForInstr(MI);
1390
1391  // Set the conditional execution predicate
1392  Binary |= II->getPredicate(&MI) << ARMII::CondShift;
1393
1394  // Set base address operand
1395  Binary |= getMachineOpValue(MI, 0) << ARMII::RegRnShift;
1396
1397  // Set addressing mode by modifying bits U(23) and P(24)
1398  const MachineOperand &MO = MI.getOperand(1);
1399  Binary |= getAddrModeUPBits(ARM_AM::getAM5SubMode(MO.getImm()));
1400
1401  // Set bit W(21)
1402  if (ARM_AM::getAM5WBFlag(MO.getImm()))
1403    Binary |= 0x1 << ARMII::W_BitShift;
1404
1405  // First register is encoded in Dd.
1406  Binary |= encodeVFPRd(MI, 5);
1407
1408  // Number of registers are encoded in offset field.
1409  unsigned NumRegs = 1;
1410  for (unsigned i = 6, e = MI.getNumOperands(); i != e; ++i) {
1411    const MachineOperand &MO = MI.getOperand(i);
1412    if (!MO.isReg() || MO.isImplicit())
1413      break;
1414    ++NumRegs;
1415  }
1416  Binary |= NumRegs * 2;
1417
1418  emitWordLE(Binary);
1419}
1420
1421template<class CodeEmitter>
1422void Emitter<CodeEmitter>::emitMiscInstruction(const MachineInstr &MI) {
1423  // Part of binary is determined by TableGn.
1424  unsigned Binary = getBinaryCodeForInstr(MI);
1425
1426  // Set the conditional execution predicate
1427  Binary |= II->getPredicate(&MI) << ARMII::CondShift;
1428
1429  emitWordLE(Binary);
1430}
1431
1432#include "ARMGenCodeEmitter.inc"
1433