ARMCodeEmitter.cpp revision 75579f739fbc99a92a15f3ce75bbd7628ba00f8c 
1//===-- ARM/ARMCodeEmitter.cpp - Convert ARM code to machine code ---------===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file contains the pass that transforms the ARM machine instructions into
11// relocatable machine code.
12//
13//===----------------------------------------------------------------------===//
14
15#define DEBUG_TYPE "jit"
16#include "ARM.h"
17#include "ARMAddressingModes.h"
18#include "ARMConstantPoolValue.h"
19#include "ARMInstrInfo.h"
20#include "ARMRelocations.h"
21#include "ARMSubtarget.h"
22#include "ARMTargetMachine.h"
23#include "llvm/Constants.h"
24#include "llvm/DerivedTypes.h"
25#include "llvm/Function.h"
26#include "llvm/PassManager.h"
27#include "llvm/CodeGen/JITCodeEmitter.h"
28#include "llvm/CodeGen/MachineConstantPool.h"
29#include "llvm/CodeGen/MachineFunctionPass.h"
30#include "llvm/CodeGen/MachineInstr.h"
31#include "llvm/CodeGen/MachineJumpTableInfo.h"
32#include "llvm/CodeGen/MachineModuleInfo.h"
33#include "llvm/CodeGen/Passes.h"
34#include "llvm/ADT/Statistic.h"
35#include "llvm/Support/Debug.h"
36#include "llvm/Support/ErrorHandling.h"
37#include "llvm/Support/raw_ostream.h"
38#ifndef NDEBUG
39#include <iomanip>
40#endif
41using namespace llvm;
42
43STATISTIC(NumEmitted, "Number of machine instructions emitted");
44
45namespace {
46
47  class ARMCodeEmitter : public MachineFunctionPass {
48    ARMJITInfo                *JTI;
49    const ARMInstrInfo        *II;
50    const TargetData          *TD;
51    const ARMSubtarget        *Subtarget;
52    TargetMachine             &TM;
53    JITCodeEmitter            &MCE;
54    MachineModuleInfo *MMI;
55    const std::vector<MachineConstantPoolEntry> *MCPEs;
56    const std::vector<MachineJumpTableEntry> *MJTEs;
57    bool IsPIC;
58    bool IsThumb;
59
60    void getAnalysisUsage(AnalysisUsage &AU) const {
61      AU.addRequired<MachineModuleInfo>();
62      MachineFunctionPass::getAnalysisUsage(AU);
63    }
64
65    static char ID;
66  public:
67    ARMCodeEmitter(TargetMachine &tm, JITCodeEmitter &mce)
68      : MachineFunctionPass(ID), JTI(0),
69        II((const ARMInstrInfo *)tm.getInstrInfo()),
70        TD(tm.getTargetData()), TM(tm),
71        MCE(mce), MCPEs(0), MJTEs(0),
72        IsPIC(TM.getRelocationModel() == Reloc::PIC_), IsThumb(false) {}
73
74    /// getBinaryCodeForInstr - This function, generated by the
75    /// CodeEmitterGenerator using TableGen, produces the binary encoding for
76    /// machine instructions.
77    unsigned getBinaryCodeForInstr(const MachineInstr &MI) const;
78
79    bool runOnMachineFunction(MachineFunction &MF);
80
81    virtual const char *getPassName() const {
82      return "ARM Machine Code Emitter";
83    }
84
85    void emitInstruction(const MachineInstr &MI);
86
87  private:
88
89    void emitWordLE(unsigned Binary);
90    void emitDWordLE(uint64_t Binary);
91    void emitConstPoolInstruction(const MachineInstr &MI);
92    void emitMOVi32immInstruction(const MachineInstr &MI);
93    void emitMOVi2piecesInstruction(const MachineInstr &MI);
94    void emitLEApcrelJTInstruction(const MachineInstr &MI);
95    void emitPseudoMoveInstruction(const MachineInstr &MI);
96    void addPCLabel(unsigned LabelID);
97    void emitPseudoInstruction(const MachineInstr &MI);
98    unsigned getMachineSoRegOpValue(const MachineInstr &MI,
99                                    const TargetInstrDesc &TID,
100                                    const MachineOperand &MO,
101                                    unsigned OpIdx);
102
103    unsigned getMachineSoImmOpValue(unsigned SoImm);
104    unsigned getAddrModeSBit(const MachineInstr &MI,
105                             const TargetInstrDesc &TID) const;
106
107    void emitDataProcessingInstruction(const MachineInstr &MI,
108                                       unsigned ImplicitRd = 0,
109                                       unsigned ImplicitRn = 0);
110
111    void emitLoadStoreInstruction(const MachineInstr &MI,
112                                  unsigned ImplicitRd = 0,
113                                  unsigned ImplicitRn = 0);
114
115    void emitMiscLoadStoreInstruction(const MachineInstr &MI,
116                                      unsigned ImplicitRn = 0);
117
118    void emitLoadStoreMultipleInstruction(const MachineInstr &MI);
119
120    void emitMulFrmInstruction(const MachineInstr &MI);
121
122    void emitExtendInstruction(const MachineInstr &MI);
123
124    void emitMiscArithInstruction(const MachineInstr &MI);
125
126    void emitSaturateInstruction(const MachineInstr &MI);
127
128    void emitBranchInstruction(const MachineInstr &MI);
129
130    void emitInlineJumpTable(unsigned JTIndex);
131
132    void emitMiscBranchInstruction(const MachineInstr &MI);
133
134    void emitVFPArithInstruction(const MachineInstr &MI);
135
136    void emitVFPConversionInstruction(const MachineInstr &MI);
137
138    void emitVFPLoadStoreInstruction(const MachineInstr &MI);
139
140    void emitVFPLoadStoreMultipleInstruction(const MachineInstr &MI);
141
142    void emitNEONLaneInstruction(const MachineInstr &MI);
143    void emitNEONDupInstruction(const MachineInstr &MI);
144    void emitNEON1RegModImmInstruction(const MachineInstr &MI);
145    void emitNEON2RegInstruction(const MachineInstr &MI);
146    void emitNEON3RegInstruction(const MachineInstr &MI);
147
148    /// getMachineOpValue - Return binary encoding of operand. If the machine
149    /// operand requires relocation, record the relocation and return zero.
150    unsigned getMachineOpValue(const MachineInstr &MI,
151                               const MachineOperand &MO) const;
152    unsigned getMachineOpValue(const MachineInstr &MI, unsigned OpIdx) const {
153      return getMachineOpValue(MI, MI.getOperand(OpIdx));
154    }
155
156    // FIXME: The legacy JIT ARMCodeEmitter doesn't rely on the the
157    //  TableGen'erated getBinaryCodeForInstr() function to encode any
158    //  operand values, instead querying getMachineOpValue() directly for
159    //  each operand it needs to encode. Thus, any of the new encoder
160    //  helper functions can simply return 0 as the values the return
161    //  are already handled elsewhere. They are placeholders to allow this
162    //  encoder to continue to function until the MC encoder is sufficiently
163    //  far along that this one can be eliminated entirely.
164    unsigned NEONThumb2DataIPostEncoder(const MachineInstr &MI, unsigned Val)
165      const { return 0; }
166    unsigned NEONThumb2LoadStorePostEncoder(const MachineInstr &MI,unsigned Val)
167      const { return 0; }
168    unsigned NEONThumb2DupPostEncoder(const MachineInstr &MI,unsigned Val)
169      const { return 0; }
170    unsigned getBranchTargetOpValue(const MachineInstr &MI, unsigned Op)
171      const { return 0; }
172    unsigned getCCOutOpValue(const MachineInstr &MI, unsigned Op)
173      const { return 0; }
174    unsigned getSOImmOpValue(const MachineInstr &MI, unsigned Op)
175      const { return 0; }
176    unsigned getT2SOImmOpValue(const MachineInstr &MI, unsigned Op)
177      const { return 0; }
178    unsigned getSORegOpValue(const MachineInstr &MI, unsigned Op)
179      const { return 0; }
180    unsigned getT2AddrModeImm12OpValue(const MachineInstr &MI, unsigned Op)
181      const { return 0; }
182    unsigned getT2AddrModeImm8OpValue(const MachineInstr &MI, unsigned Op)
183      const { return 0; }
184    unsigned getT2AddrModeSORegOpValue(const MachineInstr &MI, unsigned Op)
185      const { return 0; }
186    unsigned getT2SORegOpValue(const MachineInstr &MI, unsigned Op)
187      const { return 0; }
188    unsigned getRotImmOpValue(const MachineInstr &MI, unsigned Op)
189      const { return 0; }
190    unsigned getImmMinusOneOpValue(const MachineInstr &MI, unsigned Op)
191      const { return 0; }
192    unsigned getAddrMode6AddressOpValue(const MachineInstr &MI, unsigned Op)
193      const { return 0; }
194    unsigned getAddrMode6OffsetOpValue(const MachineInstr &MI, unsigned Op)
195      const { return 0; }
196    unsigned getBitfieldInvertedMaskOpValue(const MachineInstr &MI,
197                                            unsigned Op) const { return 0; }
198    uint32_t getLdStmModeOpValue(const MachineInstr &MI, unsigned OpIdx)
199      const {return 0; }
200    uint32_t getLdStSORegOpValue(const MachineInstr &MI, unsigned OpIdx)
201      const { return 0; }
202
203    unsigned getAddrModeImm12OpValue(const MachineInstr &MI, unsigned Op)
204      const {
205      // {17-13} = reg
206      // {12}    = (U)nsigned (add == '1', sub == '0')
207      // {11-0}  = imm12
208      const MachineOperand &MO  = MI.getOperand(Op);
209      const MachineOperand &MO1 = MI.getOperand(Op + 1);
210      if (!MO.isReg()) {
211        emitConstPoolAddress(MO.getIndex(), ARM::reloc_arm_cp_entry);
212        return 0;
213      }
214      unsigned Reg = getARMRegisterNumbering(MO.getReg());
215      int32_t Imm12 = MO1.getImm();
216      uint32_t Binary;
217      Binary = Imm12 & 0xfff;
218      if (Imm12 >= 0)
219        Binary |= (1 << 12);
220      Binary |= (Reg << 13);
221      return Binary;
222    }
223
224    unsigned getMovtImmOpValue(const MachineInstr &MI, unsigned Op) const {
225      return 0;
226    }
227
228    uint32_t getAddrMode2OpValue(const MachineInstr &MI, unsigned OpIdx)
229      const { return 0;}
230    uint32_t getAddrMode2OffsetOpValue(const MachineInstr &MI, unsigned OpIdx)
231      const { return 0;}
232    uint32_t getAddrMode3OffsetOpValue(const MachineInstr &MI, unsigned OpIdx)
233      const { return 0;}
234    uint32_t getAddrMode3OpValue(const MachineInstr &MI, unsigned Op) const
235      { return 0; }
236    uint32_t getAddrMode5OpValue(const MachineInstr &MI, unsigned Op) const {
237      // {17-13} = reg
238      // {12}    = (U)nsigned (add == '1', sub == '0')
239      // {11-0}  = imm12
240      const MachineOperand &MO  = MI.getOperand(Op);
241      const MachineOperand &MO1 = MI.getOperand(Op + 1);
242      if (!MO.isReg()) {
243        emitConstPoolAddress(MO.getIndex(), ARM::reloc_arm_cp_entry);
244        return 0;
245      }
246      unsigned Reg = getARMRegisterNumbering(MO.getReg());
247      int32_t Imm12 = MO1.getImm();
248
249      // Special value for #-0
250      if (Imm12 == INT32_MIN)
251        Imm12 = 0;
252
253      // Immediate is always encoded as positive. The 'U' bit controls add vs
254      // sub.
255      bool isAdd = true;
256      if (Imm12 < 0) {
257        Imm12 = -Imm12;
258        isAdd = false;
259      }
260
261      uint32_t Binary = Imm12 & 0xfff;
262      if (isAdd)
263        Binary |= (1 << 12);
264      Binary |= (Reg << 13);
265      return Binary;
266    }
267    unsigned getNEONVcvtImm32OpValue(const MachineInstr &MI, unsigned Op)
268      const { return 0; }
269
270    unsigned getRegisterListOpValue(const MachineInstr &MI, unsigned Op)
271      const { return 0; }
272
273    /// getMovi32Value - Return binary encoding of operand for movw/movt. If the
274    /// machine operand requires relocation, record the relocation and return
275    /// zero.
276    unsigned getMovi32Value(const MachineInstr &MI,const MachineOperand &MO,
277                            unsigned Reloc);
278
279    /// getShiftOp - Return the shift opcode (bit[6:5]) of the immediate value.
280    ///
281    unsigned getShiftOp(unsigned Imm) const ;
282
283    /// Routines that handle operands which add machine relocations which are
284    /// fixed up by the relocation stage.
285    void emitGlobalAddress(const GlobalValue *GV, unsigned Reloc,
286                           bool MayNeedFarStub,  bool Indirect,
287                           intptr_t ACPV = 0) const;
288    void emitExternalSymbolAddress(const char *ES, unsigned Reloc) const;
289    void emitConstPoolAddress(unsigned CPI, unsigned Reloc) const;
290    void emitJumpTableAddress(unsigned JTIndex, unsigned Reloc) const;
291    void emitMachineBasicBlock(MachineBasicBlock *BB, unsigned Reloc,
292                               intptr_t JTBase = 0) const;
293  };
294}
295
296char ARMCodeEmitter::ID = 0;
297
298/// createARMJITCodeEmitterPass - Return a pass that emits the collected ARM
299/// code to the specified MCE object.
300FunctionPass *llvm::createARMJITCodeEmitterPass(ARMBaseTargetMachine &TM,
301                                                JITCodeEmitter &JCE) {
302  return new ARMCodeEmitter(TM, JCE);
303}
304
305bool ARMCodeEmitter::runOnMachineFunction(MachineFunction &MF) {
306  assert((MF.getTarget().getRelocationModel() != Reloc::Default ||
307          MF.getTarget().getRelocationModel() != Reloc::Static) &&
308         "JIT relocation model must be set to static or default!");
309  JTI = ((ARMTargetMachine &)MF.getTarget()).getJITInfo();
310  II = ((const ARMTargetMachine &)MF.getTarget()).getInstrInfo();
311  TD = ((const ARMTargetMachine &)MF.getTarget()).getTargetData();
312  Subtarget = &TM.getSubtarget<ARMSubtarget>();
313  MCPEs = &MF.getConstantPool()->getConstants();
314  MJTEs = 0;
315  if (MF.getJumpTableInfo()) MJTEs = &MF.getJumpTableInfo()->getJumpTables();
316  IsPIC = TM.getRelocationModel() == Reloc::PIC_;
317  IsThumb = MF.getInfo<ARMFunctionInfo>()->isThumbFunction();
318  JTI->Initialize(MF, IsPIC);
319  MMI = &getAnalysis<MachineModuleInfo>();
320  MCE.setModuleInfo(MMI);
321
322  do {
323    DEBUG(errs() << "JITTing function '"
324          << MF.getFunction()->getName() << "'\n");
325    MCE.startFunction(MF);
326    for (MachineFunction::iterator MBB = MF.begin(), E = MF.end();
327         MBB != E; ++MBB) {
328      MCE.StartMachineBasicBlock(MBB);
329      for (MachineBasicBlock::const_iterator I = MBB->begin(), E = MBB->end();
330           I != E; ++I)
331        emitInstruction(*I);
332    }
333  } while (MCE.finishFunction(MF));
334
335  return false;
336}
337
338/// getShiftOp - Return the shift opcode (bit[6:5]) of the immediate value.
339///
340unsigned ARMCodeEmitter::getShiftOp(unsigned Imm) const {
341  switch (ARM_AM::getAM2ShiftOpc(Imm)) {
342  default: llvm_unreachable("Unknown shift opc!");
343  case ARM_AM::asr: return 2;
344  case ARM_AM::lsl: return 0;
345  case ARM_AM::lsr: return 1;
346  case ARM_AM::ror:
347  case ARM_AM::rrx: return 3;
348  }
349  return 0;
350}
351
352/// getMovi32Value - Return binary encoding of operand for movw/movt. If the
353/// machine operand requires relocation, record the relocation and return zero.
354unsigned ARMCodeEmitter::getMovi32Value(const MachineInstr &MI,
355                                        const MachineOperand &MO,
356                                        unsigned Reloc) {
357  assert(((Reloc == ARM::reloc_arm_movt) || (Reloc == ARM::reloc_arm_movw))
358      && "Relocation to this function should be for movt or movw");
359
360  if (MO.isImm())
361    return static_cast<unsigned>(MO.getImm());
362  else if (MO.isGlobal())
363    emitGlobalAddress(MO.getGlobal(), Reloc, true, false);
364  else if (MO.isSymbol())
365    emitExternalSymbolAddress(MO.getSymbolName(), Reloc);
366  else if (MO.isMBB())
367    emitMachineBasicBlock(MO.getMBB(), Reloc);
368  else {
369#ifndef NDEBUG
370    errs() << MO;
371#endif
372    llvm_unreachable("Unsupported operand type for movw/movt");
373  }
374  return 0;
375}
376
377/// getMachineOpValue - Return binary encoding of operand. If the machine
378/// operand requires relocation, record the relocation and return zero.
379unsigned ARMCodeEmitter::getMachineOpValue(const MachineInstr &MI,
380                                           const MachineOperand &MO) const {
381  if (MO.isReg())
382    return getARMRegisterNumbering(MO.getReg());
383  else if (MO.isImm())
384    return static_cast<unsigned>(MO.getImm());
385  else if (MO.isGlobal())
386    emitGlobalAddress(MO.getGlobal(), ARM::reloc_arm_branch, true, false);
387  else if (MO.isSymbol())
388    emitExternalSymbolAddress(MO.getSymbolName(), ARM::reloc_arm_branch);
389  else if (MO.isCPI()) {
390    const TargetInstrDesc &TID = MI.getDesc();
391    // For VFP load, the immediate offset is multiplied by 4.
392    unsigned Reloc =  ((TID.TSFlags & ARMII::FormMask) == ARMII::VFPLdStFrm)
393      ? ARM::reloc_arm_vfp_cp_entry : ARM::reloc_arm_cp_entry;
394    emitConstPoolAddress(MO.getIndex(), Reloc);
395  } else if (MO.isJTI())
396    emitJumpTableAddress(MO.getIndex(), ARM::reloc_arm_relative);
397  else if (MO.isMBB())
398    emitMachineBasicBlock(MO.getMBB(), ARM::reloc_arm_branch);
399  else
400    llvm_unreachable("Unable to encode MachineOperand!");
401  return 0;
402}
403
404/// emitGlobalAddress - Emit the specified address to the code stream.
405///
406void ARMCodeEmitter::emitGlobalAddress(const GlobalValue *GV, unsigned Reloc,
407                                       bool MayNeedFarStub, bool Indirect,
408                                       intptr_t ACPV) const {
409  MachineRelocation MR = Indirect
410    ? MachineRelocation::getIndirectSymbol(MCE.getCurrentPCOffset(), Reloc,
411                                           const_cast<GlobalValue *>(GV),
412                                           ACPV, MayNeedFarStub)
413    : MachineRelocation::getGV(MCE.getCurrentPCOffset(), Reloc,
414                               const_cast<GlobalValue *>(GV), ACPV,
415                               MayNeedFarStub);
416  MCE.addRelocation(MR);
417}
418
419/// emitExternalSymbolAddress - Arrange for the address of an external symbol to
420/// be emitted to the current location in the function, and allow it to be PC
421/// relative.
422void ARMCodeEmitter::
423emitExternalSymbolAddress(const char *ES, unsigned Reloc) const {
424  MCE.addRelocation(MachineRelocation::getExtSym(MCE.getCurrentPCOffset(),
425                                                 Reloc, ES));
426}
427
428/// emitConstPoolAddress - Arrange for the address of an constant pool
429/// to be emitted to the current location in the function, and allow it to be PC
430/// relative.
431void ARMCodeEmitter::emitConstPoolAddress(unsigned CPI, unsigned Reloc) const {
432  // Tell JIT emitter we'll resolve the address.
433  MCE.addRelocation(MachineRelocation::getConstPool(MCE.getCurrentPCOffset(),
434                                                    Reloc, CPI, 0, true));
435}
436
437/// emitJumpTableAddress - Arrange for the address of a jump table to
438/// be emitted to the current location in the function, and allow it to be PC
439/// relative.
440void ARMCodeEmitter::
441emitJumpTableAddress(unsigned JTIndex, unsigned Reloc) const {
442  MCE.addRelocation(MachineRelocation::getJumpTable(MCE.getCurrentPCOffset(),
443                                                    Reloc, JTIndex, 0, true));
444}
445
446/// emitMachineBasicBlock - Emit the specified address basic block.
447void ARMCodeEmitter::emitMachineBasicBlock(MachineBasicBlock *BB,
448                                           unsigned Reloc,
449                                           intptr_t JTBase) const {
450  MCE.addRelocation(MachineRelocation::getBB(MCE.getCurrentPCOffset(),
451                                             Reloc, BB, JTBase));
452}
453
454void ARMCodeEmitter::emitWordLE(unsigned Binary) {
455  DEBUG(errs() << "  0x";
456        errs().write_hex(Binary) << "\n");
457  MCE.emitWordLE(Binary);
458}
459
460void ARMCodeEmitter::emitDWordLE(uint64_t Binary) {
461  DEBUG(errs() << "  0x";
462        errs().write_hex(Binary) << "\n");
463  MCE.emitDWordLE(Binary);
464}
465
466void ARMCodeEmitter::emitInstruction(const MachineInstr &MI) {
467  DEBUG(errs() << "JIT: " << (void*)MCE.getCurrentPCValue() << ":\t" << MI);
468
469  MCE.processDebugLoc(MI.getDebugLoc(), true);
470
471  ++NumEmitted;  // Keep track of the # of mi's emitted
472  switch (MI.getDesc().TSFlags & ARMII::FormMask) {
473  default: {
474    llvm_unreachable("Unhandled instruction encoding format!");
475    break;
476  }
477  case ARMII::MiscFrm:
478    if (MI.getOpcode() == ARM::LEApcrelJT) {
479      // Materialize jumptable address.
480      emitLEApcrelJTInstruction(MI);
481      break;
482    }
483    llvm_unreachable("Unhandled instruction encoding!");
484    break;
485  case ARMII::Pseudo:
486    emitPseudoInstruction(MI);
487    break;
488  case ARMII::DPFrm:
489  case ARMII::DPSoRegFrm:
490    emitDataProcessingInstruction(MI);
491    break;
492  case ARMII::LdFrm:
493  case ARMII::StFrm:
494    emitLoadStoreInstruction(MI);
495    break;
496  case ARMII::LdMiscFrm:
497  case ARMII::StMiscFrm:
498    emitMiscLoadStoreInstruction(MI);
499    break;
500  case ARMII::LdStMulFrm:
501    emitLoadStoreMultipleInstruction(MI);
502    break;
503  case ARMII::MulFrm:
504    emitMulFrmInstruction(MI);
505    break;
506  case ARMII::ExtFrm:
507    emitExtendInstruction(MI);
508    break;
509  case ARMII::ArithMiscFrm:
510    emitMiscArithInstruction(MI);
511    break;
512  case ARMII::SatFrm:
513    emitSaturateInstruction(MI);
514    break;
515  case ARMII::BrFrm:
516    emitBranchInstruction(MI);
517    break;
518  case ARMII::BrMiscFrm:
519    emitMiscBranchInstruction(MI);
520    break;
521  // VFP instructions.
522  case ARMII::VFPUnaryFrm:
523  case ARMII::VFPBinaryFrm:
524    emitVFPArithInstruction(MI);
525    break;
526  case ARMII::VFPConv1Frm:
527  case ARMII::VFPConv2Frm:
528  case ARMII::VFPConv3Frm:
529  case ARMII::VFPConv4Frm:
530  case ARMII::VFPConv5Frm:
531    emitVFPConversionInstruction(MI);
532    break;
533  case ARMII::VFPLdStFrm:
534    emitVFPLoadStoreInstruction(MI);
535    break;
536  case ARMII::VFPLdStMulFrm:
537    emitVFPLoadStoreMultipleInstruction(MI);
538    break;
539
540  // NEON instructions.
541  case ARMII::NGetLnFrm:
542  case ARMII::NSetLnFrm:
543    emitNEONLaneInstruction(MI);
544    break;
545  case ARMII::NDupFrm:
546    emitNEONDupInstruction(MI);
547    break;
548  case ARMII::N1RegModImmFrm:
549    emitNEON1RegModImmInstruction(MI);
550    break;
551  case ARMII::N2RegFrm:
552    emitNEON2RegInstruction(MI);
553    break;
554  case ARMII::N3RegFrm:
555    emitNEON3RegInstruction(MI);
556    break;
557  }
558  MCE.processDebugLoc(MI.getDebugLoc(), false);
559}
560
561void ARMCodeEmitter::emitConstPoolInstruction(const MachineInstr &MI) {
562  unsigned CPI = MI.getOperand(0).getImm();       // CP instruction index.
563  unsigned CPIndex = MI.getOperand(1).getIndex(); // Actual cp entry index.
564  const MachineConstantPoolEntry &MCPE = (*MCPEs)[CPIndex];
565
566  // Remember the CONSTPOOL_ENTRY address for later relocation.
567  JTI->addConstantPoolEntryAddr(CPI, MCE.getCurrentPCValue());
568
569  // Emit constpool island entry. In most cases, the actual values will be
570  // resolved and relocated after code emission.
571  if (MCPE.isMachineConstantPoolEntry()) {
572    ARMConstantPoolValue *ACPV =
573      static_cast<ARMConstantPoolValue*>(MCPE.Val.MachineCPVal);
574
575    DEBUG(errs() << "  ** ARM constant pool #" << CPI << " @ "
576          << (void*)MCE.getCurrentPCValue() << " " << *ACPV << '\n');
577
578    assert(ACPV->isGlobalValue() && "unsupported constant pool value");
579    const GlobalValue *GV = ACPV->getGV();
580    if (GV) {
581      Reloc::Model RelocM = TM.getRelocationModel();
582      emitGlobalAddress(GV, ARM::reloc_arm_machine_cp_entry,
583                        isa<Function>(GV),
584                        Subtarget->GVIsIndirectSymbol(GV, RelocM),
585                        (intptr_t)ACPV);
586     } else  {
587      emitExternalSymbolAddress(ACPV->getSymbol(), ARM::reloc_arm_absolute);
588    }
589    emitWordLE(0);
590  } else {
591    const Constant *CV = MCPE.Val.ConstVal;
592
593    DEBUG({
594        errs() << "  ** Constant pool #" << CPI << " @ "
595               << (void*)MCE.getCurrentPCValue() << " ";
596        if (const Function *F = dyn_cast<Function>(CV))
597          errs() << F->getName();
598        else
599          errs() << *CV;
600        errs() << '\n';
601      });
602
603    if (const GlobalValue *GV = dyn_cast<GlobalValue>(CV)) {
604      emitGlobalAddress(GV, ARM::reloc_arm_absolute, isa<Function>(GV), false);
605      emitWordLE(0);
606    } else if (const ConstantInt *CI = dyn_cast<ConstantInt>(CV)) {
607      uint32_t Val = uint32_t(*CI->getValue().getRawData());
608      emitWordLE(Val);
609    } else if (const ConstantFP *CFP = dyn_cast<ConstantFP>(CV)) {
610      if (CFP->getType()->isFloatTy())
611        emitWordLE(CFP->getValueAPF().bitcastToAPInt().getZExtValue());
612      else if (CFP->getType()->isDoubleTy())
613        emitDWordLE(CFP->getValueAPF().bitcastToAPInt().getZExtValue());
614      else {
615        llvm_unreachable("Unable to handle this constantpool entry!");
616      }
617    } else {
618      llvm_unreachable("Unable to handle this constantpool entry!");
619    }
620  }
621}
622
623void ARMCodeEmitter::emitMOVi32immInstruction(const MachineInstr &MI) {
624  const MachineOperand &MO0 = MI.getOperand(0);
625  const MachineOperand &MO1 = MI.getOperand(1);
626
627  // Emit the 'movw' instruction.
628  unsigned Binary = 0x30 << 20;  // mov: Insts{27-20} = 0b00110000
629
630  unsigned Lo16 = getMovi32Value(MI, MO1, ARM::reloc_arm_movw) & 0xFFFF;
631
632  // Set the conditional execution predicate.
633  Binary |= II->getPredicate(&MI) << ARMII::CondShift;
634
635  // Encode Rd.
636  Binary |= getMachineOpValue(MI, MO0) << ARMII::RegRdShift;
637
638  // Encode imm16 as imm4:imm12
639  Binary |= Lo16 & 0xFFF; // Insts{11-0} = imm12
640  Binary |= ((Lo16 >> 12) & 0xF) << 16; // Insts{19-16} = imm4
641  emitWordLE(Binary);
642
643  unsigned Hi16 = getMovi32Value(MI, MO1, ARM::reloc_arm_movt) >> 16;
644  // Emit the 'movt' instruction.
645  Binary = 0x34 << 20; // movt: Insts{27-20} = 0b00110100
646
647  // Set the conditional execution predicate.
648  Binary |= II->getPredicate(&MI) << ARMII::CondShift;
649
650  // Encode Rd.
651  Binary |= getMachineOpValue(MI, MO0) << ARMII::RegRdShift;
652
653  // Encode imm16 as imm4:imm1, same as movw above.
654  Binary |= Hi16 & 0xFFF;
655  Binary |= ((Hi16 >> 12) & 0xF) << 16;
656  emitWordLE(Binary);
657}
658
659void ARMCodeEmitter::emitMOVi2piecesInstruction(const MachineInstr &MI) {
660  const MachineOperand &MO0 = MI.getOperand(0);
661  const MachineOperand &MO1 = MI.getOperand(1);
662  assert(MO1.isImm() && ARM_AM::isSOImmTwoPartVal(MO1.getImm()) &&
663                                                  "Not a valid so_imm value!");
664  unsigned V1 = ARM_AM::getSOImmTwoPartFirst(MO1.getImm());
665  unsigned V2 = ARM_AM::getSOImmTwoPartSecond(MO1.getImm());
666
667  // Emit the 'mov' instruction.
668  unsigned Binary = 0xd << 21;  // mov: Insts{24-21} = 0b1101
669
670  // Set the conditional execution predicate.
671  Binary |= II->getPredicate(&MI) << ARMII::CondShift;
672
673  // Encode Rd.
674  Binary |= getMachineOpValue(MI, MO0) << ARMII::RegRdShift;
675
676  // Encode so_imm.
677  // Set bit I(25) to identify this is the immediate form of <shifter_op>
678  Binary |= 1 << ARMII::I_BitShift;
679  Binary |= getMachineSoImmOpValue(V1);
680  emitWordLE(Binary);
681
682  // Now the 'orr' instruction.
683  Binary = 0xc << 21;  // orr: Insts{24-21} = 0b1100
684
685  // Set the conditional execution predicate.
686  Binary |= II->getPredicate(&MI) << ARMII::CondShift;
687
688  // Encode Rd.
689  Binary |= getMachineOpValue(MI, MO0) << ARMII::RegRdShift;
690
691  // Encode Rn.
692  Binary |= getMachineOpValue(MI, MO0) << ARMII::RegRnShift;
693
694  // Encode so_imm.
695  // Set bit I(25) to identify this is the immediate form of <shifter_op>
696  Binary |= 1 << ARMII::I_BitShift;
697  Binary |= getMachineSoImmOpValue(V2);
698  emitWordLE(Binary);
699}
700
701void ARMCodeEmitter::emitLEApcrelJTInstruction(const MachineInstr &MI) {
702  // It's basically add r, pc, (LJTI - $+8)
703
704  const TargetInstrDesc &TID = MI.getDesc();
705
706  // Emit the 'add' instruction.
707  unsigned Binary = 0x4 << 21;  // add: Insts{24-21} = 0b0100
708
709  // Set the conditional execution predicate
710  Binary |= II->getPredicate(&MI) << ARMII::CondShift;
711
712  // Encode S bit if MI modifies CPSR.
713  Binary |= getAddrModeSBit(MI, TID);
714
715  // Encode Rd.
716  Binary |= getMachineOpValue(MI, 0) << ARMII::RegRdShift;
717
718  // Encode Rn which is PC.
719  Binary |= getARMRegisterNumbering(ARM::PC) << ARMII::RegRnShift;
720
721  // Encode the displacement.
722  Binary |= 1 << ARMII::I_BitShift;
723  emitJumpTableAddress(MI.getOperand(1).getIndex(), ARM::reloc_arm_jt_base);
724
725  emitWordLE(Binary);
726}
727
728void ARMCodeEmitter::emitPseudoMoveInstruction(const MachineInstr &MI) {
729  unsigned Opcode = MI.getDesc().Opcode;
730
731  // Part of binary is determined by TableGn.
732  unsigned Binary = getBinaryCodeForInstr(MI);
733
734  // Set the conditional execution predicate
735  Binary |= II->getPredicate(&MI) << ARMII::CondShift;
736
737  // Encode S bit if MI modifies CPSR.
738  if (Opcode == ARM::MOVsrl_flag || Opcode == ARM::MOVsra_flag)
739    Binary |= 1 << ARMII::S_BitShift;
740
741  // Encode register def if there is one.
742  Binary |= getMachineOpValue(MI, 0) << ARMII::RegRdShift;
743
744  // Encode the shift operation.
745  switch (Opcode) {
746  default: break;
747  case ARM::RRX:
748    // rrx
749    Binary |= 0x6 << 4;
750    break;
751  case ARM::MOVsrl_flag:
752    // lsr #1
753    Binary |= (0x2 << 4) | (1 << 7);
754    break;
755  case ARM::MOVsra_flag:
756    // asr #1
757    Binary |= (0x4 << 4) | (1 << 7);
758    break;
759  }
760
761  // Encode register Rm.
762  Binary |= getMachineOpValue(MI, 1);
763
764  emitWordLE(Binary);
765}
766
767void ARMCodeEmitter::addPCLabel(unsigned LabelID) {
768  DEBUG(errs() << "  ** LPC" << LabelID << " @ "
769        << (void*)MCE.getCurrentPCValue() << '\n');
770  JTI->addPCLabelAddr(LabelID, MCE.getCurrentPCValue());
771}
772
773void ARMCodeEmitter::emitPseudoInstruction(const MachineInstr &MI) {
774  unsigned Opcode = MI.getDesc().Opcode;
775  switch (Opcode) {
776  default:
777    llvm_unreachable("ARMCodeEmitter::emitPseudoInstruction");
778  case ARM::BX:
779  case ARM::BMOVPCRX:
780  case ARM::BXr9:
781  case ARM::BMOVPCRXr9: {
782    // First emit mov lr, pc
783    unsigned Binary = 0x01a0e00f;
784    Binary |= II->getPredicate(&MI) << ARMII::CondShift;
785    emitWordLE(Binary);
786
787    // and then emit the branch.
788    emitMiscBranchInstruction(MI);
789    break;
790  }
791  case TargetOpcode::INLINEASM: {
792    // We allow inline assembler nodes with empty bodies - they can
793    // implicitly define registers, which is ok for JIT.
794    if (MI.getOperand(0).getSymbolName()[0]) {
795      report_fatal_error("JIT does not support inline asm!");
796    }
797    break;
798  }
799  case TargetOpcode::PROLOG_LABEL:
800  case TargetOpcode::EH_LABEL:
801    MCE.emitLabel(MI.getOperand(0).getMCSymbol());
802    break;
803  case TargetOpcode::IMPLICIT_DEF:
804  case TargetOpcode::KILL:
805    // Do nothing.
806    break;
807  case ARM::CONSTPOOL_ENTRY:
808    emitConstPoolInstruction(MI);
809    break;
810  case ARM::PICADD: {
811    // Remember of the address of the PC label for relocation later.
812    addPCLabel(MI.getOperand(2).getImm());
813    // PICADD is just an add instruction that implicitly read pc.
814    emitDataProcessingInstruction(MI, 0, ARM::PC);
815    break;
816  }
817  case ARM::PICLDR:
818  case ARM::PICLDRB:
819  case ARM::PICSTR:
820  case ARM::PICSTRB: {
821    // Remember of the address of the PC label for relocation later.
822    addPCLabel(MI.getOperand(2).getImm());
823    // These are just load / store instructions that implicitly read pc.
824    emitLoadStoreInstruction(MI, 0, ARM::PC);
825    break;
826  }
827  case ARM::PICLDRH:
828  case ARM::PICLDRSH:
829  case ARM::PICLDRSB:
830  case ARM::PICSTRH: {
831    // Remember of the address of the PC label for relocation later.
832    addPCLabel(MI.getOperand(2).getImm());
833    // These are just load / store instructions that implicitly read pc.
834    emitMiscLoadStoreInstruction(MI, ARM::PC);
835    break;
836  }
837
838  case ARM::MOVi32imm:
839    // Two instructions to materialize a constant.
840    if (Subtarget->hasV6T2Ops())
841      emitMOVi32immInstruction(MI);
842    else
843      emitMOVi2piecesInstruction(MI);
844    break;
845
846  case ARM::LEApcrelJT:
847    // Materialize jumptable address.
848    emitLEApcrelJTInstruction(MI);
849    break;
850  case ARM::RRX:
851  case ARM::MOVsrl_flag:
852  case ARM::MOVsra_flag:
853    emitPseudoMoveInstruction(MI);
854    break;
855  }
856}
857
858unsigned ARMCodeEmitter::getMachineSoRegOpValue(const MachineInstr &MI,
859                                                const TargetInstrDesc &TID,
860                                                const MachineOperand &MO,
861                                                unsigned OpIdx) {
862  unsigned Binary = getMachineOpValue(MI, MO);
863
864  const MachineOperand &MO1 = MI.getOperand(OpIdx + 1);
865  const MachineOperand &MO2 = MI.getOperand(OpIdx + 2);
866  ARM_AM::ShiftOpc SOpc = ARM_AM::getSORegShOp(MO2.getImm());
867
868  // Encode the shift opcode.
869  unsigned SBits = 0;
870  unsigned Rs = MO1.getReg();
871  if (Rs) {
872    // Set shift operand (bit[7:4]).
873    // LSL - 0001
874    // LSR - 0011
875    // ASR - 0101
876    // ROR - 0111
877    // RRX - 0110 and bit[11:8] clear.
878    switch (SOpc) {
879    default: llvm_unreachable("Unknown shift opc!");
880    case ARM_AM::lsl: SBits = 0x1; break;
881    case ARM_AM::lsr: SBits = 0x3; break;
882    case ARM_AM::asr: SBits = 0x5; break;
883    case ARM_AM::ror: SBits = 0x7; break;
884    case ARM_AM::rrx: SBits = 0x6; break;
885    }
886  } else {
887    // Set shift operand (bit[6:4]).
888    // LSL - 000
889    // LSR - 010
890    // ASR - 100
891    // ROR - 110
892    switch (SOpc) {
893    default: llvm_unreachable("Unknown shift opc!");
894    case ARM_AM::lsl: SBits = 0x0; break;
895    case ARM_AM::lsr: SBits = 0x2; break;
896    case ARM_AM::asr: SBits = 0x4; break;
897    case ARM_AM::ror: SBits = 0x6; break;
898    }
899  }
900  Binary |= SBits << 4;
901  if (SOpc == ARM_AM::rrx)
902    return Binary;
903
904  // Encode the shift operation Rs or shift_imm (except rrx).
905  if (Rs) {
906    // Encode Rs bit[11:8].
907    assert(ARM_AM::getSORegOffset(MO2.getImm()) == 0);
908    return Binary | (getARMRegisterNumbering(Rs) << ARMII::RegRsShift);
909  }
910
911  // Encode shift_imm bit[11:7].
912  return Binary | ARM_AM::getSORegOffset(MO2.getImm()) << 7;
913}
914
915unsigned ARMCodeEmitter::getMachineSoImmOpValue(unsigned SoImm) {
916  int SoImmVal = ARM_AM::getSOImmVal(SoImm);
917  assert(SoImmVal != -1 && "Not a valid so_imm value!");
918
919  // Encode rotate_imm.
920  unsigned Binary = (ARM_AM::getSOImmValRot((unsigned)SoImmVal) >> 1)
921    << ARMII::SoRotImmShift;
922
923  // Encode immed_8.
924  Binary |= ARM_AM::getSOImmValImm((unsigned)SoImmVal);
925  return Binary;
926}
927
928unsigned ARMCodeEmitter::getAddrModeSBit(const MachineInstr &MI,
929                                         const TargetInstrDesc &TID) const {
930  for (unsigned i = MI.getNumOperands(), e = TID.getNumOperands(); i != e; --i){
931    const MachineOperand &MO = MI.getOperand(i-1);
932    if (MO.isReg() && MO.isDef() && MO.getReg() == ARM::CPSR)
933      return 1 << ARMII::S_BitShift;
934  }
935  return 0;
936}
937
938void ARMCodeEmitter::emitDataProcessingInstruction(const MachineInstr &MI,
939                                                   unsigned ImplicitRd,
940                                                   unsigned ImplicitRn) {
941  const TargetInstrDesc &TID = MI.getDesc();
942
943  // Part of binary is determined by TableGn.
944  unsigned Binary = getBinaryCodeForInstr(MI);
945
946  // Set the conditional execution predicate
947  Binary |= II->getPredicate(&MI) << ARMII::CondShift;
948
949  // Encode S bit if MI modifies CPSR.
950  Binary |= getAddrModeSBit(MI, TID);
951
952  // Encode register def if there is one.
953  unsigned NumDefs = TID.getNumDefs();
954  unsigned OpIdx = 0;
955  if (NumDefs)
956    Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRdShift;
957  else if (ImplicitRd)
958    // Special handling for implicit use (e.g. PC).
959    Binary |= (getARMRegisterNumbering(ImplicitRd) << ARMII::RegRdShift);
960
961  if (TID.Opcode == ARM::MOVi16) {
962      // Get immediate from MI.
963      unsigned Lo16 = getMovi32Value(MI, MI.getOperand(OpIdx),
964                      ARM::reloc_arm_movw);
965      // Encode imm which is the same as in emitMOVi32immInstruction().
966      Binary |= Lo16 & 0xFFF;
967      Binary |= ((Lo16 >> 12) & 0xF) << 16;
968      emitWordLE(Binary);
969      return;
970  } else if(TID.Opcode == ARM::MOVTi16) {
971      unsigned Hi16 = (getMovi32Value(MI, MI.getOperand(OpIdx),
972                       ARM::reloc_arm_movt) >> 16);
973      Binary |= Hi16 & 0xFFF;
974      Binary |= ((Hi16 >> 12) & 0xF) << 16;
975      emitWordLE(Binary);
976      return;
977  } else if ((TID.Opcode == ARM::BFC) || (TID.Opcode == ARM::BFI)) {
978      uint32_t v = ~MI.getOperand(2).getImm();
979      int32_t lsb = CountTrailingZeros_32(v);
980      int32_t msb = (32 - CountLeadingZeros_32(v)) - 1;
981      // Instr{20-16} = msb, Instr{11-7} = lsb
982      Binary |= (msb & 0x1F) << 16;
983      Binary |= (lsb & 0x1F) << 7;
984      emitWordLE(Binary);
985      return;
986  } else if ((TID.Opcode == ARM::UBFX) || (TID.Opcode == ARM::SBFX)) {
987      // Encode Rn in Instr{0-3}
988      Binary |= getMachineOpValue(MI, OpIdx++);
989
990      uint32_t lsb = MI.getOperand(OpIdx++).getImm();
991      uint32_t widthm1 = MI.getOperand(OpIdx++).getImm() - 1;
992
993      // Instr{20-16} = widthm1, Instr{11-7} = lsb
994      Binary |= (widthm1 & 0x1F) << 16;
995      Binary |= (lsb & 0x1F) << 7;
996      emitWordLE(Binary);
997      return;
998  }
999
1000  // If this is a two-address operand, skip it. e.g. MOVCCr operand 1.
1001  if (TID.getOperandConstraint(OpIdx, TOI::TIED_TO) != -1)
1002    ++OpIdx;
1003
1004  // Encode first non-shifter register operand if there is one.
1005  bool isUnary = TID.TSFlags & ARMII::UnaryDP;
1006  if (!isUnary) {
1007    if (ImplicitRn)
1008      // Special handling for implicit use (e.g. PC).
1009      Binary |= (getARMRegisterNumbering(ImplicitRn) << ARMII::RegRnShift);
1010    else {
1011      Binary |= getMachineOpValue(MI, OpIdx) << ARMII::RegRnShift;
1012      ++OpIdx;
1013    }
1014  }
1015
1016  // Encode shifter operand.
1017  const MachineOperand &MO = MI.getOperand(OpIdx);
1018  if ((TID.TSFlags & ARMII::FormMask) == ARMII::DPSoRegFrm) {
1019    // Encode SoReg.
1020    emitWordLE(Binary | getMachineSoRegOpValue(MI, TID, MO, OpIdx));
1021    return;
1022  }
1023
1024  if (MO.isReg()) {
1025    // Encode register Rm.
1026    emitWordLE(Binary | getARMRegisterNumbering(MO.getReg()));
1027    return;
1028  }
1029
1030  // Encode so_imm.
1031  Binary |= getMachineSoImmOpValue((unsigned)MO.getImm());
1032
1033  emitWordLE(Binary);
1034}
1035
1036void ARMCodeEmitter::emitLoadStoreInstruction(const MachineInstr &MI,
1037                                              unsigned ImplicitRd,
1038                                              unsigned ImplicitRn) {
1039  const TargetInstrDesc &TID = MI.getDesc();
1040  unsigned Form = TID.TSFlags & ARMII::FormMask;
1041  bool IsPrePost = (TID.TSFlags & ARMII::IndexModeMask) != 0;
1042
1043  // Part of binary is determined by TableGn.
1044  unsigned Binary = getBinaryCodeForInstr(MI);
1045
1046  // If this is an LDRi12, STRi12 or LDRcp, nothing more needs be done.
1047  if (MI.getOpcode() == ARM::LDRi12 || MI.getOpcode() == ARM::LDRcp ||
1048      MI.getOpcode() == ARM::STRi12) {
1049    emitWordLE(Binary);
1050    return;
1051  }
1052
1053  // Set the conditional execution predicate
1054  Binary |= II->getPredicate(&MI) << ARMII::CondShift;
1055
1056  unsigned OpIdx = 0;
1057
1058  // Operand 0 of a pre- and post-indexed store is the address base
1059  // writeback. Skip it.
1060  bool Skipped = false;
1061  if (IsPrePost && Form == ARMII::StFrm) {
1062    ++OpIdx;
1063    Skipped = true;
1064  }
1065
1066  // Set first operand
1067  if (ImplicitRd)
1068    // Special handling for implicit use (e.g. PC).
1069    Binary |= (getARMRegisterNumbering(ImplicitRd) << ARMII::RegRdShift);
1070  else
1071    Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRdShift;
1072
1073  // Set second operand
1074  if (ImplicitRn)
1075    // Special handling for implicit use (e.g. PC).
1076    Binary |= (getARMRegisterNumbering(ImplicitRn) << ARMII::RegRnShift);
1077  else
1078    Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRnShift;
1079
1080  // If this is a two-address operand, skip it. e.g. LDR_PRE.
1081  if (!Skipped && TID.getOperandConstraint(OpIdx, TOI::TIED_TO) != -1)
1082    ++OpIdx;
1083
1084  const MachineOperand &MO2 = MI.getOperand(OpIdx);
1085  unsigned AM2Opc = (ImplicitRn == ARM::PC)
1086    ? 0 : MI.getOperand(OpIdx+1).getImm();
1087
1088  // Set bit U(23) according to sign of immed value (positive or negative).
1089  Binary |= ((ARM_AM::getAM2Op(AM2Opc) == ARM_AM::add ? 1 : 0) <<
1090             ARMII::U_BitShift);
1091  if (!MO2.getReg()) { // is immediate
1092    if (ARM_AM::getAM2Offset(AM2Opc))
1093      // Set the value of offset_12 field
1094      Binary |= ARM_AM::getAM2Offset(AM2Opc);
1095    emitWordLE(Binary);
1096    return;
1097  }
1098
1099  // Set bit I(25), because this is not in immediate encoding.
1100  Binary |= 1 << ARMII::I_BitShift;
1101  assert(TargetRegisterInfo::isPhysicalRegister(MO2.getReg()));
1102  // Set bit[3:0] to the corresponding Rm register
1103  Binary |= getARMRegisterNumbering(MO2.getReg());
1104
1105  // If this instr is in scaled register offset/index instruction, set
1106  // shift_immed(bit[11:7]) and shift(bit[6:5]) fields.
1107  if (unsigned ShImm = ARM_AM::getAM2Offset(AM2Opc)) {
1108    Binary |= getShiftOp(AM2Opc) << ARMII::ShiftImmShift;  // shift
1109    Binary |= ShImm              << ARMII::ShiftShift;     // shift_immed
1110  }
1111
1112  emitWordLE(Binary);
1113}
1114
1115void ARMCodeEmitter::emitMiscLoadStoreInstruction(const MachineInstr &MI,
1116                                                  unsigned ImplicitRn) {
1117  const TargetInstrDesc &TID = MI.getDesc();
1118  unsigned Form = TID.TSFlags & ARMII::FormMask;
1119  bool IsPrePost = (TID.TSFlags & ARMII::IndexModeMask) != 0;
1120
1121  // Part of binary is determined by TableGn.
1122  unsigned Binary = getBinaryCodeForInstr(MI);
1123
1124  // Set the conditional execution predicate
1125  Binary |= II->getPredicate(&MI) << ARMII::CondShift;
1126
1127  unsigned OpIdx = 0;
1128
1129  // Operand 0 of a pre- and post-indexed store is the address base
1130  // writeback. Skip it.
1131  bool Skipped = false;
1132  if (IsPrePost && Form == ARMII::StMiscFrm) {
1133    ++OpIdx;
1134    Skipped = true;
1135  }
1136
1137  // Set first operand
1138  Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRdShift;
1139
1140  // Skip LDRD and STRD's second operand.
1141  if (TID.Opcode == ARM::LDRD || TID.Opcode == ARM::STRD)
1142    ++OpIdx;
1143
1144  // Set second operand
1145  if (ImplicitRn)
1146    // Special handling for implicit use (e.g. PC).
1147    Binary |= (getARMRegisterNumbering(ImplicitRn) << ARMII::RegRnShift);
1148  else
1149    Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRnShift;
1150
1151  // If this is a two-address operand, skip it. e.g. LDRH_POST.
1152  if (!Skipped && TID.getOperandConstraint(OpIdx, TOI::TIED_TO) != -1)
1153    ++OpIdx;
1154
1155  const MachineOperand &MO2 = MI.getOperand(OpIdx);
1156  unsigned AM3Opc = (ImplicitRn == ARM::PC)
1157    ? 0 : MI.getOperand(OpIdx+1).getImm();
1158
1159  // Set bit U(23) according to sign of immed value (positive or negative)
1160  Binary |= ((ARM_AM::getAM3Op(AM3Opc) == ARM_AM::add ? 1 : 0) <<
1161             ARMII::U_BitShift);
1162
1163  // If this instr is in register offset/index encoding, set bit[3:0]
1164  // to the corresponding Rm register.
1165  if (MO2.getReg()) {
1166    Binary |= getARMRegisterNumbering(MO2.getReg());
1167    emitWordLE(Binary);
1168    return;
1169  }
1170
1171  // This instr is in immediate offset/index encoding, set bit 22 to 1.
1172  Binary |= 1 << ARMII::AM3_I_BitShift;
1173  if (unsigned ImmOffs = ARM_AM::getAM3Offset(AM3Opc)) {
1174    // Set operands
1175    Binary |= (ImmOffs >> 4) << ARMII::ImmHiShift;  // immedH
1176    Binary |= (ImmOffs & 0xF);                      // immedL
1177  }
1178
1179  emitWordLE(Binary);
1180}
1181
1182static unsigned getAddrModeUPBits(unsigned Mode) {
1183  unsigned Binary = 0;
1184
1185  // Set addressing mode by modifying bits U(23) and P(24)
1186  // IA - Increment after  - bit U = 1 and bit P = 0
1187  // IB - Increment before - bit U = 1 and bit P = 1
1188  // DA - Decrement after  - bit U = 0 and bit P = 0
1189  // DB - Decrement before - bit U = 0 and bit P = 1
1190  switch (Mode) {
1191  default: llvm_unreachable("Unknown addressing sub-mode!");
1192  case ARM_AM::da:                                     break;
1193  case ARM_AM::db: Binary |= 0x1 << ARMII::P_BitShift; break;
1194  case ARM_AM::ia: Binary |= 0x1 << ARMII::U_BitShift; break;
1195  case ARM_AM::ib: Binary |= 0x3 << ARMII::U_BitShift; break;
1196  }
1197
1198  return Binary;
1199}
1200
1201void ARMCodeEmitter::emitLoadStoreMultipleInstruction(const MachineInstr &MI) {
1202  const TargetInstrDesc &TID = MI.getDesc();
1203  bool IsUpdating = (TID.TSFlags & ARMII::IndexModeMask) != 0;
1204
1205  // Part of binary is determined by TableGn.
1206  unsigned Binary = getBinaryCodeForInstr(MI);
1207
1208  // Set the conditional execution predicate
1209  Binary |= II->getPredicate(&MI) << ARMII::CondShift;
1210
1211  // Skip operand 0 of an instruction with base register update.
1212  unsigned OpIdx = 0;
1213  if (IsUpdating)
1214    ++OpIdx;
1215
1216  // Set base address operand
1217  Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRnShift;
1218
1219  // Set addressing mode by modifying bits U(23) and P(24)
1220  ARM_AM::AMSubMode Mode = ARM_AM::getLoadStoreMultipleSubMode(MI.getOpcode());
1221  Binary |= getAddrModeUPBits(ARM_AM::getAM4SubMode(Mode));
1222
1223  // Set bit W(21)
1224  if (IsUpdating)
1225    Binary |= 0x1 << ARMII::W_BitShift;
1226
1227  // Set registers
1228  for (unsigned i = OpIdx+2, e = MI.getNumOperands(); i != e; ++i) {
1229    const MachineOperand &MO = MI.getOperand(i);
1230    if (!MO.isReg() || MO.isImplicit())
1231      break;
1232    unsigned RegNum = getARMRegisterNumbering(MO.getReg());
1233    assert(TargetRegisterInfo::isPhysicalRegister(MO.getReg()) &&
1234           RegNum < 16);
1235    Binary |= 0x1 << RegNum;
1236  }
1237
1238  emitWordLE(Binary);
1239}
1240
1241void ARMCodeEmitter::emitMulFrmInstruction(const MachineInstr &MI) {
1242  const TargetInstrDesc &TID = MI.getDesc();
1243
1244  // Part of binary is determined by TableGn.
1245  unsigned Binary = getBinaryCodeForInstr(MI);
1246
1247  // Set the conditional execution predicate
1248  Binary |= II->getPredicate(&MI) << ARMII::CondShift;
1249
1250  // Encode S bit if MI modifies CPSR.
1251  Binary |= getAddrModeSBit(MI, TID);
1252
1253  // 32x32->64bit operations have two destination registers. The number
1254  // of register definitions will tell us if that's what we're dealing with.
1255  unsigned OpIdx = 0;
1256  if (TID.getNumDefs() == 2)
1257    Binary |= getMachineOpValue (MI, OpIdx++) << ARMII::RegRdLoShift;
1258
1259  // Encode Rd
1260  Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRdHiShift;
1261
1262  // Encode Rm
1263  Binary |= getMachineOpValue(MI, OpIdx++);
1264
1265  // Encode Rs
1266  Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRsShift;
1267
1268  // Many multiple instructions (e.g. MLA) have three src operands. Encode
1269  // it as Rn (for multiply, that's in the same offset as RdLo.
1270  if (TID.getNumOperands() > OpIdx &&
1271      !TID.OpInfo[OpIdx].isPredicate() &&
1272      !TID.OpInfo[OpIdx].isOptionalDef())
1273    Binary |= getMachineOpValue(MI, OpIdx) << ARMII::RegRdLoShift;
1274
1275  emitWordLE(Binary);
1276}
1277
1278void ARMCodeEmitter::emitExtendInstruction(const MachineInstr &MI) {
1279  const TargetInstrDesc &TID = MI.getDesc();
1280
1281  // Part of binary is determined by TableGn.
1282  unsigned Binary = getBinaryCodeForInstr(MI);
1283
1284  // Set the conditional execution predicate
1285  Binary |= II->getPredicate(&MI) << ARMII::CondShift;
1286
1287  unsigned OpIdx = 0;
1288
1289  // Encode Rd
1290  Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRdShift;
1291
1292  const MachineOperand &MO1 = MI.getOperand(OpIdx++);
1293  const MachineOperand &MO2 = MI.getOperand(OpIdx);
1294  if (MO2.isReg()) {
1295    // Two register operand form.
1296    // Encode Rn.
1297    Binary |= getMachineOpValue(MI, MO1) << ARMII::RegRnShift;
1298
1299    // Encode Rm.
1300    Binary |= getMachineOpValue(MI, MO2);
1301    ++OpIdx;
1302  } else {
1303    Binary |= getMachineOpValue(MI, MO1);
1304  }
1305
1306  // Encode rot imm (0, 8, 16, or 24) if it has a rotate immediate operand.
1307  if (MI.getOperand(OpIdx).isImm() &&
1308      !TID.OpInfo[OpIdx].isPredicate() &&
1309      !TID.OpInfo[OpIdx].isOptionalDef())
1310    Binary |= (getMachineOpValue(MI, OpIdx) / 8) << ARMII::ExtRotImmShift;
1311
1312  emitWordLE(Binary);
1313}
1314
1315void ARMCodeEmitter::emitMiscArithInstruction(const MachineInstr &MI) {
1316  const TargetInstrDesc &TID = MI.getDesc();
1317
1318  // Part of binary is determined by TableGn.
1319  unsigned Binary = getBinaryCodeForInstr(MI);
1320
1321  // Set the conditional execution predicate
1322  Binary |= II->getPredicate(&MI) << ARMII::CondShift;
1323
1324  unsigned OpIdx = 0;
1325
1326  // Encode Rd
1327  Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRdShift;
1328
1329  const MachineOperand &MO = MI.getOperand(OpIdx++);
1330  if (OpIdx == TID.getNumOperands() ||
1331      TID.OpInfo[OpIdx].isPredicate() ||
1332      TID.OpInfo[OpIdx].isOptionalDef()) {
1333    // Encode Rm and it's done.
1334    Binary |= getMachineOpValue(MI, MO);
1335    emitWordLE(Binary);
1336    return;
1337  }
1338
1339  // Encode Rn.
1340  Binary |= getMachineOpValue(MI, MO) << ARMII::RegRnShift;
1341
1342  // Encode Rm.
1343  Binary |= getMachineOpValue(MI, OpIdx++);
1344
1345  // Encode shift_imm.
1346  unsigned ShiftAmt = MI.getOperand(OpIdx).getImm();
1347  if (TID.Opcode == ARM::PKHTB) {
1348    assert(ShiftAmt != 0 && "PKHTB shift_imm is 0!");
1349    if (ShiftAmt == 32)
1350      ShiftAmt = 0;
1351  }
1352  assert(ShiftAmt < 32 && "shift_imm range is 0 to 31!");
1353  Binary |= ShiftAmt << ARMII::ShiftShift;
1354
1355  emitWordLE(Binary);
1356}
1357
1358void ARMCodeEmitter::emitSaturateInstruction(const MachineInstr &MI) {
1359  const TargetInstrDesc &TID = MI.getDesc();
1360
1361  // Part of binary is determined by TableGen.
1362  unsigned Binary = getBinaryCodeForInstr(MI);
1363
1364  // Set the conditional execution predicate
1365  Binary |= II->getPredicate(&MI) << ARMII::CondShift;
1366
1367  // Encode Rd
1368  Binary |= getMachineOpValue(MI, 0) << ARMII::RegRdShift;
1369
1370  // Encode saturate bit position.
1371  unsigned Pos = MI.getOperand(1).getImm();
1372  if (TID.Opcode == ARM::SSAT || TID.Opcode == ARM::SSAT16)
1373    Pos -= 1;
1374  assert((Pos < 16 || (Pos < 32 &&
1375                       TID.Opcode != ARM::SSAT16 &&
1376                       TID.Opcode != ARM::USAT16)) &&
1377         "saturate bit position out of range");
1378  Binary |= Pos << 16;
1379
1380  // Encode Rm
1381  Binary |= getMachineOpValue(MI, 2);
1382
1383  // Encode shift_imm.
1384  if (TID.getNumOperands() == 4) {
1385    unsigned ShiftOp = MI.getOperand(3).getImm();
1386    ARM_AM::ShiftOpc Opc = ARM_AM::getSORegShOp(ShiftOp);
1387    if (Opc == ARM_AM::asr)
1388      Binary |= (1 << 6);
1389    unsigned ShiftAmt = MI.getOperand(3).getImm();
1390    if (ShiftAmt == 32 && Opc == ARM_AM::asr)
1391      ShiftAmt = 0;
1392    assert(ShiftAmt < 32 && "shift_imm range is 0 to 31!");
1393    Binary |= ShiftAmt << ARMII::ShiftShift;
1394  }
1395
1396  emitWordLE(Binary);
1397}
1398
1399void ARMCodeEmitter::emitBranchInstruction(const MachineInstr &MI) {
1400  const TargetInstrDesc &TID = MI.getDesc();
1401
1402  if (TID.Opcode == ARM::TPsoft) {
1403    llvm_unreachable("ARM::TPsoft FIXME"); // FIXME
1404  }
1405
1406  // Part of binary is determined by TableGn.
1407  unsigned Binary = getBinaryCodeForInstr(MI);
1408
1409  // Set the conditional execution predicate
1410  Binary |= II->getPredicate(&MI) << ARMII::CondShift;
1411
1412  // Set signed_immed_24 field
1413  Binary |= getMachineOpValue(MI, 0);
1414
1415  emitWordLE(Binary);
1416}
1417
1418void ARMCodeEmitter::emitInlineJumpTable(unsigned JTIndex) {
1419  // Remember the base address of the inline jump table.
1420  uintptr_t JTBase = MCE.getCurrentPCValue();
1421  JTI->addJumpTableBaseAddr(JTIndex, JTBase);
1422  DEBUG(errs() << "  ** Jump Table #" << JTIndex << " @ " << (void*)JTBase
1423               << '\n');
1424
1425  // Now emit the jump table entries.
1426  const std::vector<MachineBasicBlock*> &MBBs = (*MJTEs)[JTIndex].MBBs;
1427  for (unsigned i = 0, e = MBBs.size(); i != e; ++i) {
1428    if (IsPIC)
1429      // DestBB address - JT base.
1430      emitMachineBasicBlock(MBBs[i], ARM::reloc_arm_pic_jt, JTBase);
1431    else
1432      // Absolute DestBB address.
1433      emitMachineBasicBlock(MBBs[i], ARM::reloc_arm_absolute);
1434    emitWordLE(0);
1435  }
1436}
1437
1438void ARMCodeEmitter::emitMiscBranchInstruction(const MachineInstr &MI) {
1439  const TargetInstrDesc &TID = MI.getDesc();
1440
1441  // Handle jump tables.
1442  if (TID.Opcode == ARM::BR_JTr || TID.Opcode == ARM::BR_JTadd) {
1443    // First emit a ldr pc, [] instruction.
1444    emitDataProcessingInstruction(MI, ARM::PC);
1445
1446    // Then emit the inline jump table.
1447    unsigned JTIndex =
1448      (TID.Opcode == ARM::BR_JTr)
1449      ? MI.getOperand(1).getIndex() : MI.getOperand(2).getIndex();
1450    emitInlineJumpTable(JTIndex);
1451    return;
1452  } else if (TID.Opcode == ARM::BR_JTm) {
1453    // First emit a ldr pc, [] instruction.
1454    emitLoadStoreInstruction(MI, ARM::PC);
1455
1456    // Then emit the inline jump table.
1457    emitInlineJumpTable(MI.getOperand(3).getIndex());
1458    return;
1459  }
1460
1461  // Part of binary is determined by TableGn.
1462  unsigned Binary = getBinaryCodeForInstr(MI);
1463
1464  // Set the conditional execution predicate
1465  Binary |= II->getPredicate(&MI) << ARMII::CondShift;
1466
1467  if (TID.Opcode == ARM::BX_RET || TID.Opcode == ARM::MOVPCLR)
1468    // The return register is LR.
1469    Binary |= getARMRegisterNumbering(ARM::LR);
1470  else
1471    // otherwise, set the return register
1472    Binary |= getMachineOpValue(MI, 0);
1473
1474  emitWordLE(Binary);
1475}
1476
1477static unsigned encodeVFPRd(const MachineInstr &MI, unsigned OpIdx) {
1478  unsigned RegD = MI.getOperand(OpIdx).getReg();
1479  unsigned Binary = 0;
1480  bool isSPVFP = ARM::SPRRegisterClass->contains(RegD);
1481  RegD = getARMRegisterNumbering(RegD);
1482  if (!isSPVFP)
1483    Binary |=   RegD               << ARMII::RegRdShift;
1484  else {
1485    Binary |= ((RegD & 0x1E) >> 1) << ARMII::RegRdShift;
1486    Binary |=  (RegD & 0x01)       << ARMII::D_BitShift;
1487  }
1488  return Binary;
1489}
1490
1491static unsigned encodeVFPRn(const MachineInstr &MI, unsigned OpIdx) {
1492  unsigned RegN = MI.getOperand(OpIdx).getReg();
1493  unsigned Binary = 0;
1494  bool isSPVFP = ARM::SPRRegisterClass->contains(RegN);
1495  RegN = getARMRegisterNumbering(RegN);
1496  if (!isSPVFP)
1497    Binary |=   RegN               << ARMII::RegRnShift;
1498  else {
1499    Binary |= ((RegN & 0x1E) >> 1) << ARMII::RegRnShift;
1500    Binary |=  (RegN & 0x01)       << ARMII::N_BitShift;
1501  }
1502  return Binary;
1503}
1504
1505static unsigned encodeVFPRm(const MachineInstr &MI, unsigned OpIdx) {
1506  unsigned RegM = MI.getOperand(OpIdx).getReg();
1507  unsigned Binary = 0;
1508  bool isSPVFP = ARM::SPRRegisterClass->contains(RegM);
1509  RegM = getARMRegisterNumbering(RegM);
1510  if (!isSPVFP)
1511    Binary |=   RegM;
1512  else {
1513    Binary |= ((RegM & 0x1E) >> 1);
1514    Binary |=  (RegM & 0x01)       << ARMII::M_BitShift;
1515  }
1516  return Binary;
1517}
1518
1519void ARMCodeEmitter::emitVFPArithInstruction(const MachineInstr &MI) {
1520  const TargetInstrDesc &TID = MI.getDesc();
1521
1522  // Part of binary is determined by TableGn.
1523  unsigned Binary = getBinaryCodeForInstr(MI);
1524
1525  // Set the conditional execution predicate
1526  Binary |= II->getPredicate(&MI) << ARMII::CondShift;
1527
1528  unsigned OpIdx = 0;
1529  assert((Binary & ARMII::D_BitShift) == 0 &&
1530         (Binary & ARMII::N_BitShift) == 0 &&
1531         (Binary & ARMII::M_BitShift) == 0 && "VFP encoding bug!");
1532
1533  // Encode Dd / Sd.
1534  Binary |= encodeVFPRd(MI, OpIdx++);
1535
1536  // If this is a two-address operand, skip it, e.g. FMACD.
1537  if (TID.getOperandConstraint(OpIdx, TOI::TIED_TO) != -1)
1538    ++OpIdx;
1539
1540  // Encode Dn / Sn.
1541  if ((TID.TSFlags & ARMII::FormMask) == ARMII::VFPBinaryFrm)
1542    Binary |= encodeVFPRn(MI, OpIdx++);
1543
1544  if (OpIdx == TID.getNumOperands() ||
1545      TID.OpInfo[OpIdx].isPredicate() ||
1546      TID.OpInfo[OpIdx].isOptionalDef()) {
1547    // FCMPEZD etc. has only one operand.
1548    emitWordLE(Binary);
1549    return;
1550  }
1551
1552  // Encode Dm / Sm.
1553  Binary |= encodeVFPRm(MI, OpIdx);
1554
1555  emitWordLE(Binary);
1556}
1557
1558void ARMCodeEmitter::emitVFPConversionInstruction(const MachineInstr &MI) {
1559  const TargetInstrDesc &TID = MI.getDesc();
1560  unsigned Form = TID.TSFlags & ARMII::FormMask;
1561
1562  // Part of binary is determined by TableGn.
1563  unsigned Binary = getBinaryCodeForInstr(MI);
1564
1565  // Set the conditional execution predicate
1566  Binary |= II->getPredicate(&MI) << ARMII::CondShift;
1567
1568  switch (Form) {
1569  default: break;
1570  case ARMII::VFPConv1Frm:
1571  case ARMII::VFPConv2Frm:
1572  case ARMII::VFPConv3Frm:
1573    // Encode Dd / Sd.
1574    Binary |= encodeVFPRd(MI, 0);
1575    break;
1576  case ARMII::VFPConv4Frm:
1577    // Encode Dn / Sn.
1578    Binary |= encodeVFPRn(MI, 0);
1579    break;
1580  case ARMII::VFPConv5Frm:
1581    // Encode Dm / Sm.
1582    Binary |= encodeVFPRm(MI, 0);
1583    break;
1584  }
1585
1586  switch (Form) {
1587  default: break;
1588  case ARMII::VFPConv1Frm:
1589    // Encode Dm / Sm.
1590    Binary |= encodeVFPRm(MI, 1);
1591    break;
1592  case ARMII::VFPConv2Frm:
1593  case ARMII::VFPConv3Frm:
1594    // Encode Dn / Sn.
1595    Binary |= encodeVFPRn(MI, 1);
1596    break;
1597  case ARMII::VFPConv4Frm:
1598  case ARMII::VFPConv5Frm:
1599    // Encode Dd / Sd.
1600    Binary |= encodeVFPRd(MI, 1);
1601    break;
1602  }
1603
1604  if (Form == ARMII::VFPConv5Frm)
1605    // Encode Dn / Sn.
1606    Binary |= encodeVFPRn(MI, 2);
1607  else if (Form == ARMII::VFPConv3Frm)
1608    // Encode Dm / Sm.
1609    Binary |= encodeVFPRm(MI, 2);
1610
1611  emitWordLE(Binary);
1612}
1613
1614void ARMCodeEmitter::emitVFPLoadStoreInstruction(const MachineInstr &MI) {
1615  // Part of binary is determined by TableGn.
1616  unsigned Binary = getBinaryCodeForInstr(MI);
1617
1618  // Set the conditional execution predicate
1619  Binary |= II->getPredicate(&MI) << ARMII::CondShift;
1620
1621  unsigned OpIdx = 0;
1622
1623  // Encode Dd / Sd.
1624  Binary |= encodeVFPRd(MI, OpIdx++);
1625
1626  // Encode address base.
1627  const MachineOperand &Base = MI.getOperand(OpIdx++);
1628  Binary |= getMachineOpValue(MI, Base) << ARMII::RegRnShift;
1629
1630  // If there is a non-zero immediate offset, encode it.
1631  if (Base.isReg()) {
1632    const MachineOperand &Offset = MI.getOperand(OpIdx);
1633    if (unsigned ImmOffs = ARM_AM::getAM5Offset(Offset.getImm())) {
1634      if (ARM_AM::getAM5Op(Offset.getImm()) == ARM_AM::add)
1635        Binary |= 1 << ARMII::U_BitShift;
1636      Binary |= ImmOffs;
1637      emitWordLE(Binary);
1638      return;
1639    }
1640  }
1641
1642  // If immediate offset is omitted, default to +0.
1643  Binary |= 1 << ARMII::U_BitShift;
1644
1645  emitWordLE(Binary);
1646}
1647
1648void
1649ARMCodeEmitter::emitVFPLoadStoreMultipleInstruction(const MachineInstr &MI) {
1650  const TargetInstrDesc &TID = MI.getDesc();
1651  bool IsUpdating = (TID.TSFlags & ARMII::IndexModeMask) != 0;
1652
1653  // Part of binary is determined by TableGn.
1654  unsigned Binary = getBinaryCodeForInstr(MI);
1655
1656  // Set the conditional execution predicate
1657  Binary |= II->getPredicate(&MI) << ARMII::CondShift;
1658
1659  // Skip operand 0 of an instruction with base register update.
1660  unsigned OpIdx = 0;
1661  if (IsUpdating)
1662    ++OpIdx;
1663
1664  // Set base address operand
1665  Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRnShift;
1666
1667  // Set addressing mode by modifying bits U(23) and P(24)
1668  ARM_AM::AMSubMode Mode = ARM_AM::getLoadStoreMultipleSubMode(MI.getOpcode());
1669  Binary |= getAddrModeUPBits(ARM_AM::getAM4SubMode(Mode));
1670
1671  // Set bit W(21)
1672  if (IsUpdating)
1673    Binary |= 0x1 << ARMII::W_BitShift;
1674
1675  // First register is encoded in Dd.
1676  Binary |= encodeVFPRd(MI, OpIdx+2);
1677
1678  // Count the number of registers.
1679  unsigned NumRegs = 1;
1680  for (unsigned i = OpIdx+3, e = MI.getNumOperands(); i != e; ++i) {
1681    const MachineOperand &MO = MI.getOperand(i);
1682    if (!MO.isReg() || MO.isImplicit())
1683      break;
1684    ++NumRegs;
1685  }
1686  // Bit 8 will be set if <list> is consecutive 64-bit registers (e.g., D0)
1687  // Otherwise, it will be 0, in the case of 32-bit registers.
1688  if(Binary & 0x100)
1689    Binary |= NumRegs * 2;
1690  else
1691    Binary |= NumRegs;
1692
1693  emitWordLE(Binary);
1694}
1695
1696static unsigned encodeNEONRd(const MachineInstr &MI, unsigned OpIdx) {
1697  unsigned RegD = MI.getOperand(OpIdx).getReg();
1698  unsigned Binary = 0;
1699  RegD = getARMRegisterNumbering(RegD);
1700  Binary |= (RegD & 0xf) << ARMII::RegRdShift;
1701  Binary |= ((RegD >> 4) & 1) << ARMII::D_BitShift;
1702  return Binary;
1703}
1704
1705static unsigned encodeNEONRn(const MachineInstr &MI, unsigned OpIdx) {
1706  unsigned RegN = MI.getOperand(OpIdx).getReg();
1707  unsigned Binary = 0;
1708  RegN = getARMRegisterNumbering(RegN);
1709  Binary |= (RegN & 0xf) << ARMII::RegRnShift;
1710  Binary |= ((RegN >> 4) & 1) << ARMII::N_BitShift;
1711  return Binary;
1712}
1713
1714static unsigned encodeNEONRm(const MachineInstr &MI, unsigned OpIdx) {
1715  unsigned RegM = MI.getOperand(OpIdx).getReg();
1716  unsigned Binary = 0;
1717  RegM = getARMRegisterNumbering(RegM);
1718  Binary |= (RegM & 0xf);
1719  Binary |= ((RegM >> 4) & 1) << ARMII::M_BitShift;
1720  return Binary;
1721}
1722
1723/// convertNEONDataProcToThumb - Convert the ARM mode encoding for a NEON
1724/// data-processing instruction to the corresponding Thumb encoding.
1725static unsigned convertNEONDataProcToThumb(unsigned Binary) {
1726  assert((Binary & 0xfe000000) == 0xf2000000 &&
1727         "not an ARM NEON data-processing instruction");
1728  unsigned UBit = (Binary >> 24) & 1;
1729  return 0xef000000 | (UBit << 28) | (Binary & 0xffffff);
1730}
1731
1732void ARMCodeEmitter::emitNEONLaneInstruction(const MachineInstr &MI) {
1733  unsigned Binary = getBinaryCodeForInstr(MI);
1734
1735  unsigned RegTOpIdx, RegNOpIdx, LnOpIdx;
1736  const TargetInstrDesc &TID = MI.getDesc();
1737  if ((TID.TSFlags & ARMII::FormMask) == ARMII::NGetLnFrm) {
1738    RegTOpIdx = 0;
1739    RegNOpIdx = 1;
1740    LnOpIdx = 2;
1741  } else { // ARMII::NSetLnFrm
1742    RegTOpIdx = 2;
1743    RegNOpIdx = 0;
1744    LnOpIdx = 3;
1745  }
1746
1747  // Set the conditional execution predicate
1748  Binary |= (IsThumb ? ARMCC::AL : II->getPredicate(&MI)) << ARMII::CondShift;
1749
1750  unsigned RegT = MI.getOperand(RegTOpIdx).getReg();
1751  RegT = getARMRegisterNumbering(RegT);
1752  Binary |= (RegT << ARMII::RegRdShift);
1753  Binary |= encodeNEONRn(MI, RegNOpIdx);
1754
1755  unsigned LaneShift;
1756  if ((Binary & (1 << 22)) != 0)
1757    LaneShift = 0; // 8-bit elements
1758  else if ((Binary & (1 << 5)) != 0)
1759    LaneShift = 1; // 16-bit elements
1760  else
1761    LaneShift = 2; // 32-bit elements
1762
1763  unsigned Lane = MI.getOperand(LnOpIdx).getImm() << LaneShift;
1764  unsigned Opc1 = Lane >> 2;
1765  unsigned Opc2 = Lane & 3;
1766  assert((Opc1 & 3) == 0 && "out-of-range lane number operand");
1767  Binary |= (Opc1 << 21);
1768  Binary |= (Opc2 << 5);
1769
1770  emitWordLE(Binary);
1771}
1772
1773void ARMCodeEmitter::emitNEONDupInstruction(const MachineInstr &MI) {
1774  unsigned Binary = getBinaryCodeForInstr(MI);
1775
1776  // Set the conditional execution predicate
1777  Binary |= (IsThumb ? ARMCC::AL : II->getPredicate(&MI)) << ARMII::CondShift;
1778
1779  unsigned RegT = MI.getOperand(1).getReg();
1780  RegT = getARMRegisterNumbering(RegT);
1781  Binary |= (RegT << ARMII::RegRdShift);
1782  Binary |= encodeNEONRn(MI, 0);
1783  emitWordLE(Binary);
1784}
1785
1786void ARMCodeEmitter::emitNEON1RegModImmInstruction(const MachineInstr &MI) {
1787  unsigned Binary = getBinaryCodeForInstr(MI);
1788  // Destination register is encoded in Dd.
1789  Binary |= encodeNEONRd(MI, 0);
1790  // Immediate fields: Op, Cmode, I, Imm3, Imm4
1791  unsigned Imm = MI.getOperand(1).getImm();
1792  unsigned Op = (Imm >> 12) & 1;
1793  unsigned Cmode = (Imm >> 8) & 0xf;
1794  unsigned I = (Imm >> 7) & 1;
1795  unsigned Imm3 = (Imm >> 4) & 0x7;
1796  unsigned Imm4 = Imm & 0xf;
1797  Binary |= (I << 24) | (Imm3 << 16) | (Cmode << 8) | (Op << 5) | Imm4;
1798  if (IsThumb)
1799    Binary = convertNEONDataProcToThumb(Binary);
1800  emitWordLE(Binary);
1801}
1802
1803void ARMCodeEmitter::emitNEON2RegInstruction(const MachineInstr &MI) {
1804  const TargetInstrDesc &TID = MI.getDesc();
1805  unsigned Binary = getBinaryCodeForInstr(MI);
1806  // Destination register is encoded in Dd; source register in Dm.
1807  unsigned OpIdx = 0;
1808  Binary |= encodeNEONRd(MI, OpIdx++);
1809  if (TID.getOperandConstraint(OpIdx, TOI::TIED_TO) != -1)
1810    ++OpIdx;
1811  Binary |= encodeNEONRm(MI, OpIdx);
1812  if (IsThumb)
1813    Binary = convertNEONDataProcToThumb(Binary);
1814  // FIXME: This does not handle VDUPfdf or VDUPfqf.
1815  emitWordLE(Binary);
1816}
1817
1818void ARMCodeEmitter::emitNEON3RegInstruction(const MachineInstr &MI) {
1819  const TargetInstrDesc &TID = MI.getDesc();
1820  unsigned Binary = getBinaryCodeForInstr(MI);
1821  // Destination register is encoded in Dd; source registers in Dn and Dm.
1822  unsigned OpIdx = 0;
1823  Binary |= encodeNEONRd(MI, OpIdx++);
1824  if (TID.getOperandConstraint(OpIdx, TOI::TIED_TO) != -1)
1825    ++OpIdx;
1826  Binary |= encodeNEONRn(MI, OpIdx++);
1827  if (TID.getOperandConstraint(OpIdx, TOI::TIED_TO) != -1)
1828    ++OpIdx;
1829  Binary |= encodeNEONRm(MI, OpIdx);
1830  if (IsThumb)
1831    Binary = convertNEONDataProcToThumb(Binary);
1832  // FIXME: This does not handle VMOVDneon or VMOVQ.
1833  emitWordLE(Binary);
1834}
1835
1836#include "ARMGenCodeEmitter.inc"
1837