ARMCodeEmitter.cpp revision 7abe37e4aee38cc79d91dd069a37d7e91d5bef53 
1//===-- ARM/ARMCodeEmitter.cpp - Convert ARM code to machine code ---------===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file contains the pass that transforms the ARM machine instructions into
11// relocatable machine code.
12//
13//===----------------------------------------------------------------------===//
14
15#define DEBUG_TYPE "jit"
16#include "ARM.h"
17#include "ARMAddressingModes.h"
18#include "ARMConstantPoolValue.h"
19#include "ARMInstrInfo.h"
20#include "ARMRelocations.h"
21#include "ARMSubtarget.h"
22#include "ARMTargetMachine.h"
23#include "llvm/Constants.h"
24#include "llvm/DerivedTypes.h"
25#include "llvm/Function.h"
26#include "llvm/PassManager.h"
27#include "llvm/CodeGen/JITCodeEmitter.h"
28#include "llvm/CodeGen/MachineConstantPool.h"
29#include "llvm/CodeGen/MachineFunctionPass.h"
30#include "llvm/CodeGen/MachineInstr.h"
31#include "llvm/CodeGen/MachineJumpTableInfo.h"
32#include "llvm/CodeGen/MachineModuleInfo.h"
33#include "llvm/CodeGen/Passes.h"
34#include "llvm/ADT/Statistic.h"
35#include "llvm/Support/Debug.h"
36#include "llvm/Support/ErrorHandling.h"
37#include "llvm/Support/raw_ostream.h"
38#ifndef NDEBUG
39#include <iomanip>
40#endif
41using namespace llvm;
42
43STATISTIC(NumEmitted, "Number of machine instructions emitted");
44
45namespace {
46
47  class ARMCodeEmitter : public MachineFunctionPass {
48    ARMJITInfo                *JTI;
49    const ARMInstrInfo        *II;
50    const TargetData          *TD;
51    const ARMSubtarget        *Subtarget;
52    TargetMachine             &TM;
53    JITCodeEmitter            &MCE;
54    MachineModuleInfo *MMI;
55    const std::vector<MachineConstantPoolEntry> *MCPEs;
56    const std::vector<MachineJumpTableEntry> *MJTEs;
57    bool IsPIC;
58
59    void getAnalysisUsage(AnalysisUsage &AU) const {
60      AU.addRequired<MachineModuleInfo>();
61      MachineFunctionPass::getAnalysisUsage(AU);
62    }
63
64    static char ID;
65  public:
66    ARMCodeEmitter(TargetMachine &tm, JITCodeEmitter &mce)
67      : MachineFunctionPass(&ID), JTI(0),
68        II((const ARMInstrInfo *)tm.getInstrInfo()),
69        TD(tm.getTargetData()), TM(tm),
70    MCE(mce), MCPEs(0), MJTEs(0),
71    IsPIC(TM.getRelocationModel() == Reloc::PIC_) {}
72
73    /// getBinaryCodeForInstr - This function, generated by the
74    /// CodeEmitterGenerator using TableGen, produces the binary encoding for
75    /// machine instructions.
76    unsigned getBinaryCodeForInstr(const MachineInstr &MI);
77
78    bool runOnMachineFunction(MachineFunction &MF);
79
80    virtual const char *getPassName() const {
81      return "ARM Machine Code Emitter";
82    }
83
84    void emitInstruction(const MachineInstr &MI);
85
86  private:
87
88    void emitWordLE(unsigned Binary);
89    void emitDWordLE(uint64_t Binary);
90    void emitConstPoolInstruction(const MachineInstr &MI);
91    void emitMOVi32immInstruction(const MachineInstr &MI);
92    void emitMOVi2piecesInstruction(const MachineInstr &MI);
93    void emitLEApcrelJTInstruction(const MachineInstr &MI);
94    void emitPseudoMoveInstruction(const MachineInstr &MI);
95    void addPCLabel(unsigned LabelID);
96    void emitPseudoInstruction(const MachineInstr &MI);
97    unsigned getMachineSoRegOpValue(const MachineInstr &MI,
98                                    const TargetInstrDesc &TID,
99                                    const MachineOperand &MO,
100                                    unsigned OpIdx);
101
102    unsigned getMachineSoImmOpValue(unsigned SoImm);
103
104    unsigned getAddrModeSBit(const MachineInstr &MI,
105                             const TargetInstrDesc &TID) const;
106
107    void emitDataProcessingInstruction(const MachineInstr &MI,
108                                       unsigned ImplicitRd = 0,
109                                       unsigned ImplicitRn = 0);
110
111    void emitLoadStoreInstruction(const MachineInstr &MI,
112                                  unsigned ImplicitRd = 0,
113                                  unsigned ImplicitRn = 0);
114
115    void emitMiscLoadStoreInstruction(const MachineInstr &MI,
116                                      unsigned ImplicitRn = 0);
117
118    void emitLoadStoreMultipleInstruction(const MachineInstr &MI);
119
120    void emitMulFrmInstruction(const MachineInstr &MI);
121
122    void emitExtendInstruction(const MachineInstr &MI);
123
124    void emitMiscArithInstruction(const MachineInstr &MI);
125
126    void emitBranchInstruction(const MachineInstr &MI);
127
128    void emitInlineJumpTable(unsigned JTIndex);
129
130    void emitMiscBranchInstruction(const MachineInstr &MI);
131
132    void emitVFPArithInstruction(const MachineInstr &MI);
133
134    void emitVFPConversionInstruction(const MachineInstr &MI);
135
136    void emitVFPLoadStoreInstruction(const MachineInstr &MI);
137
138    void emitVFPLoadStoreMultipleInstruction(const MachineInstr &MI);
139
140    void emitMiscInstruction(const MachineInstr &MI);
141
142    /// getMachineOpValue - Return binary encoding of operand. If the machine
143    /// operand requires relocation, record the relocation and return zero.
144    unsigned getMachineOpValue(const MachineInstr &MI,const MachineOperand &MO);
145    unsigned getMachineOpValue(const MachineInstr &MI, unsigned OpIdx) {
146      return getMachineOpValue(MI, MI.getOperand(OpIdx));
147    }
148
149    /// getMovi32Value - Return binary encoding of operand for movw/movt. If the
150    /// machine operand requires relocation, record the relocation and return zero.
151    unsigned getMovi32Value(const MachineInstr &MI,const MachineOperand &MO,
152                            unsigned Reloc);
153    unsigned getMovi32Value(const MachineInstr &MI, unsigned OpIdx,
154                            unsigned Reloc) {
155      return getMovi32Value(MI, MI.getOperand(OpIdx), Reloc);
156    }
157
158    /// getShiftOp - Return the shift opcode (bit[6:5]) of the immediate value.
159    ///
160    unsigned getShiftOp(unsigned Imm) const ;
161
162    /// Routines that handle operands which add machine relocations which are
163    /// fixed up by the relocation stage.
164    void emitGlobalAddress(const GlobalValue *GV, unsigned Reloc,
165                           bool MayNeedFarStub,  bool Indirect,
166                           intptr_t ACPV = 0);
167    void emitExternalSymbolAddress(const char *ES, unsigned Reloc);
168    void emitConstPoolAddress(unsigned CPI, unsigned Reloc);
169    void emitJumpTableAddress(unsigned JTIndex, unsigned Reloc);
170    void emitMachineBasicBlock(MachineBasicBlock *BB, unsigned Reloc,
171                               intptr_t JTBase = 0);
172  };
173}
174
175char ARMCodeEmitter::ID = 0;
176
177/// createARMJITCodeEmitterPass - Return a pass that emits the collected ARM
178/// code to the specified MCE object.
179FunctionPass *llvm::createARMJITCodeEmitterPass(ARMBaseTargetMachine &TM,
180                                                JITCodeEmitter &JCE) {
181  return new ARMCodeEmitter(TM, JCE);
182}
183
184bool ARMCodeEmitter::runOnMachineFunction(MachineFunction &MF) {
185  assert((MF.getTarget().getRelocationModel() != Reloc::Default ||
186          MF.getTarget().getRelocationModel() != Reloc::Static) &&
187         "JIT relocation model must be set to static or default!");
188  JTI = ((ARMTargetMachine &)MF.getTarget()).getJITInfo();
189  II = ((const ARMTargetMachine &)MF.getTarget()).getInstrInfo();
190  TD = ((const ARMTargetMachine &)MF.getTarget()).getTargetData();
191  Subtarget = &TM.getSubtarget<ARMSubtarget>();
192  MCPEs = &MF.getConstantPool()->getConstants();
193  MJTEs = 0;
194  if (MF.getJumpTableInfo()) MJTEs = &MF.getJumpTableInfo()->getJumpTables();
195  IsPIC = TM.getRelocationModel() == Reloc::PIC_;
196  JTI->Initialize(MF, IsPIC);
197  MMI = &getAnalysis<MachineModuleInfo>();
198  MCE.setModuleInfo(MMI);
199
200  do {
201    DEBUG(errs() << "JITTing function '"
202          << MF.getFunction()->getName() << "'\n");
203    MCE.startFunction(MF);
204    for (MachineFunction::iterator MBB = MF.begin(), E = MF.end();
205         MBB != E; ++MBB) {
206      MCE.StartMachineBasicBlock(MBB);
207      for (MachineBasicBlock::const_iterator I = MBB->begin(), E = MBB->end();
208           I != E; ++I)
209        emitInstruction(*I);
210    }
211  } while (MCE.finishFunction(MF));
212
213  return false;
214}
215
216/// getShiftOp - Return the shift opcode (bit[6:5]) of the immediate value.
217///
218unsigned ARMCodeEmitter::getShiftOp(unsigned Imm) const {
219  switch (ARM_AM::getAM2ShiftOpc(Imm)) {
220  default: llvm_unreachable("Unknown shift opc!");
221  case ARM_AM::asr: return 2;
222  case ARM_AM::lsl: return 0;
223  case ARM_AM::lsr: return 1;
224  case ARM_AM::ror:
225  case ARM_AM::rrx: return 3;
226  }
227  return 0;
228}
229
230/// getMovi32Value - Return binary encoding of operand for movw/movt. If the
231/// machine operand requires relocation, record the relocation and return zero.
232unsigned ARMCodeEmitter::getMovi32Value(const MachineInstr &MI,
233                                        const MachineOperand &MO,
234                                        unsigned Reloc) {
235  assert(((Reloc == ARM::reloc_arm_movt) || (Reloc == ARM::reloc_arm_movw))
236      && "Relocation to this function should be for movt or movw");
237  switch(MO.getType()) {
238  case MachineOperand::MO_Register:
239    return ARMRegisterInfo::getRegisterNumbering(MO.getReg());
240    break;
241
242  case MachineOperand::MO_Immediate:
243    return static_cast<unsigned>(MO.getImm());
244    break;
245
246  case MachineOperand::MO_FPImmediate:
247    return static_cast<unsigned>(
248        MO.getFPImm()->getValueAPF().bitcastToAPInt().getLimitedValue());
249    break;
250
251  case MachineOperand::MO_MachineBasicBlock:
252    emitMachineBasicBlock(MO.getMBB(), Reloc);
253    break;
254
255  case MachineOperand::MO_ConstantPoolIndex:
256    emitConstPoolAddress(MO.getIndex(), Reloc);
257    break;
258
259  case MachineOperand::MO_JumpTableIndex:
260    emitJumpTableAddress(MO.getIndex(), Reloc);
261    break;
262
263  case MachineOperand::MO_ExternalSymbol:
264    emitExternalSymbolAddress(MO.getSymbolName(), Reloc);
265    break;
266
267  case MachineOperand::MO_GlobalAddress:
268    emitGlobalAddress(MO.getGlobal(), Reloc, true, false);
269    break;
270
271  default:
272    llvm_unreachable("Unsupported immediate operand type for movw/movt");
273    break;
274  }
275  return 0;
276}
277
278/// getMachineOpValue - Return binary encoding of operand. If the machine
279/// operand requires relocation, record the relocation and return zero.
280unsigned ARMCodeEmitter::getMachineOpValue(const MachineInstr &MI,
281                                           const MachineOperand &MO) {
282  if (MO.isReg())
283    return ARMRegisterInfo::getRegisterNumbering(MO.getReg());
284  else if (MO.isImm())
285    return static_cast<unsigned>(MO.getImm());
286  else if (MO.isGlobal())
287    emitGlobalAddress(MO.getGlobal(), ARM::reloc_arm_branch, true, false);
288  else if (MO.isSymbol())
289    emitExternalSymbolAddress(MO.getSymbolName(), ARM::reloc_arm_branch);
290  else if (MO.isCPI()) {
291    const TargetInstrDesc &TID = MI.getDesc();
292    // For VFP load, the immediate offset is multiplied by 4.
293    unsigned Reloc =  ((TID.TSFlags & ARMII::FormMask) == ARMII::VFPLdStFrm)
294      ? ARM::reloc_arm_vfp_cp_entry : ARM::reloc_arm_cp_entry;
295    emitConstPoolAddress(MO.getIndex(), Reloc);
296  } else if (MO.isJTI())
297    emitJumpTableAddress(MO.getIndex(), ARM::reloc_arm_relative);
298  else if (MO.isMBB())
299    emitMachineBasicBlock(MO.getMBB(), ARM::reloc_arm_branch);
300  else {
301#ifndef NDEBUG
302    errs() << MO;
303#endif
304    llvm_unreachable(0);
305  }
306  return 0;
307}
308
309/// emitGlobalAddress - Emit the specified address to the code stream.
310///
311void ARMCodeEmitter::emitGlobalAddress(const GlobalValue *GV, unsigned Reloc,
312                                       bool MayNeedFarStub, bool Indirect,
313                                       intptr_t ACPV) {
314  MachineRelocation MR = Indirect
315    ? MachineRelocation::getIndirectSymbol(MCE.getCurrentPCOffset(), Reloc,
316                                           const_cast<GlobalValue *>(GV),
317                                           ACPV, MayNeedFarStub)
318    : MachineRelocation::getGV(MCE.getCurrentPCOffset(), Reloc,
319                               const_cast<GlobalValue *>(GV), ACPV,
320                               MayNeedFarStub);
321  MCE.addRelocation(MR);
322}
323
324/// emitExternalSymbolAddress - Arrange for the address of an external symbol to
325/// be emitted to the current location in the function, and allow it to be PC
326/// relative.
327void ARMCodeEmitter::emitExternalSymbolAddress(const char *ES, unsigned Reloc) {
328  MCE.addRelocation(MachineRelocation::getExtSym(MCE.getCurrentPCOffset(),
329                                                 Reloc, ES));
330}
331
332/// emitConstPoolAddress - Arrange for the address of an constant pool
333/// to be emitted to the current location in the function, and allow it to be PC
334/// relative.
335void ARMCodeEmitter::emitConstPoolAddress(unsigned CPI, unsigned Reloc) {
336  // Tell JIT emitter we'll resolve the address.
337  MCE.addRelocation(MachineRelocation::getConstPool(MCE.getCurrentPCOffset(),
338                                                    Reloc, CPI, 0, true));
339}
340
341/// emitJumpTableAddress - Arrange for the address of a jump table to
342/// be emitted to the current location in the function, and allow it to be PC
343/// relative.
344void ARMCodeEmitter::emitJumpTableAddress(unsigned JTIndex, unsigned Reloc) {
345  MCE.addRelocation(MachineRelocation::getJumpTable(MCE.getCurrentPCOffset(),
346                                                    Reloc, JTIndex, 0, true));
347}
348
349/// emitMachineBasicBlock - Emit the specified address basic block.
350void ARMCodeEmitter::emitMachineBasicBlock(MachineBasicBlock *BB,
351                                           unsigned Reloc, intptr_t JTBase) {
352  MCE.addRelocation(MachineRelocation::getBB(MCE.getCurrentPCOffset(),
353                                             Reloc, BB, JTBase));
354}
355
356void ARMCodeEmitter::emitWordLE(unsigned Binary) {
357  DEBUG(errs() << "  0x";
358        errs().write_hex(Binary) << "\n");
359  MCE.emitWordLE(Binary);
360}
361
362void ARMCodeEmitter::emitDWordLE(uint64_t Binary) {
363  DEBUG(errs() << "  0x";
364        errs().write_hex(Binary) << "\n");
365  MCE.emitDWordLE(Binary);
366}
367
368void ARMCodeEmitter::emitInstruction(const MachineInstr &MI) {
369  DEBUG(errs() << "JIT: " << (void*)MCE.getCurrentPCValue() << ":\t" << MI);
370
371  MCE.processDebugLoc(MI.getDebugLoc(), true);
372
373  NumEmitted++;  // Keep track of the # of mi's emitted
374  switch (MI.getDesc().TSFlags & ARMII::FormMask) {
375  default: {
376    llvm_unreachable("Unhandled instruction encoding format!");
377    break;
378  }
379  case ARMII::Pseudo:
380    emitPseudoInstruction(MI);
381    break;
382  case ARMII::DPFrm:
383  case ARMII::DPSoRegFrm:
384    emitDataProcessingInstruction(MI);
385    break;
386  case ARMII::LdFrm:
387  case ARMII::StFrm:
388    emitLoadStoreInstruction(MI);
389    break;
390  case ARMII::LdMiscFrm:
391  case ARMII::StMiscFrm:
392    emitMiscLoadStoreInstruction(MI);
393    break;
394  case ARMII::LdStMulFrm:
395    emitLoadStoreMultipleInstruction(MI);
396    break;
397  case ARMII::MulFrm:
398    emitMulFrmInstruction(MI);
399    break;
400  case ARMII::ExtFrm:
401    emitExtendInstruction(MI);
402    break;
403  case ARMII::ArithMiscFrm:
404    emitMiscArithInstruction(MI);
405    break;
406  case ARMII::BrFrm:
407    emitBranchInstruction(MI);
408    break;
409  case ARMII::BrMiscFrm:
410    emitMiscBranchInstruction(MI);
411    break;
412  // VFP instructions.
413  case ARMII::VFPUnaryFrm:
414  case ARMII::VFPBinaryFrm:
415    emitVFPArithInstruction(MI);
416    break;
417  case ARMII::VFPConv1Frm:
418  case ARMII::VFPConv2Frm:
419  case ARMII::VFPConv3Frm:
420  case ARMII::VFPConv4Frm:
421  case ARMII::VFPConv5Frm:
422    emitVFPConversionInstruction(MI);
423    break;
424  case ARMII::VFPLdStFrm:
425    emitVFPLoadStoreInstruction(MI);
426    break;
427  case ARMII::VFPLdStMulFrm:
428    emitVFPLoadStoreMultipleInstruction(MI);
429    break;
430  case ARMII::VFPMiscFrm:
431    emitMiscInstruction(MI);
432    break;
433  }
434  MCE.processDebugLoc(MI.getDebugLoc(), false);
435}
436
437void ARMCodeEmitter::emitConstPoolInstruction(const MachineInstr &MI) {
438  unsigned CPI = MI.getOperand(0).getImm();       // CP instruction index.
439  unsigned CPIndex = MI.getOperand(1).getIndex(); // Actual cp entry index.
440  const MachineConstantPoolEntry &MCPE = (*MCPEs)[CPIndex];
441
442  // Remember the CONSTPOOL_ENTRY address for later relocation.
443  JTI->addConstantPoolEntryAddr(CPI, MCE.getCurrentPCValue());
444
445  // Emit constpool island entry. In most cases, the actual values will be
446  // resolved and relocated after code emission.
447  if (MCPE.isMachineConstantPoolEntry()) {
448    ARMConstantPoolValue *ACPV =
449      static_cast<ARMConstantPoolValue*>(MCPE.Val.MachineCPVal);
450
451    DEBUG(errs() << "  ** ARM constant pool #" << CPI << " @ "
452          << (void*)MCE.getCurrentPCValue() << " " << *ACPV << '\n');
453
454    assert(ACPV->isGlobalValue() && "unsupported constant pool value");
455    const GlobalValue *GV = ACPV->getGV();
456    if (GV) {
457      Reloc::Model RelocM = TM.getRelocationModel();
458      emitGlobalAddress(GV, ARM::reloc_arm_machine_cp_entry,
459                        isa<Function>(GV),
460                        Subtarget->GVIsIndirectSymbol(GV, RelocM),
461                        (intptr_t)ACPV);
462     } else  {
463      emitExternalSymbolAddress(ACPV->getSymbol(), ARM::reloc_arm_absolute);
464    }
465    emitWordLE(0);
466  } else {
467    const Constant *CV = MCPE.Val.ConstVal;
468
469    DEBUG({
470        errs() << "  ** Constant pool #" << CPI << " @ "
471               << (void*)MCE.getCurrentPCValue() << " ";
472        if (const Function *F = dyn_cast<Function>(CV))
473          errs() << F->getName();
474        else
475          errs() << *CV;
476        errs() << '\n';
477      });
478
479    if (const GlobalValue *GV = dyn_cast<GlobalValue>(CV)) {
480      emitGlobalAddress(GV, ARM::reloc_arm_absolute, isa<Function>(GV), false);
481      emitWordLE(0);
482    } else if (const ConstantInt *CI = dyn_cast<ConstantInt>(CV)) {
483      uint32_t Val = *(uint32_t*)CI->getValue().getRawData();
484      emitWordLE(Val);
485    } else if (const ConstantFP *CFP = dyn_cast<ConstantFP>(CV)) {
486      if (CFP->getType()->isFloatTy())
487        emitWordLE(CFP->getValueAPF().bitcastToAPInt().getZExtValue());
488      else if (CFP->getType()->isDoubleTy())
489        emitDWordLE(CFP->getValueAPF().bitcastToAPInt().getZExtValue());
490      else {
491        llvm_unreachable("Unable to handle this constantpool entry!");
492      }
493    } else {
494      llvm_unreachable("Unable to handle this constantpool entry!");
495    }
496  }
497}
498
499void ARMCodeEmitter::emitMOVi32immInstruction(const MachineInstr &MI) {
500  const MachineOperand &MO0 = MI.getOperand(0);
501  const MachineOperand &MO1 = MI.getOperand(1);
502
503  unsigned Lo16 = getMovi32Value(MI, MO1, ARM::reloc_arm_movw) & 0xFFFF;
504
505  // Emit the 'mov' instruction.
506  unsigned Binary = 0x30 << 20;  // mov: Insts{27-20} = 0b00110000
507
508  // Set the conditional execution predicate.
509  Binary |= II->getPredicate(&MI) << ARMII::CondShift;
510
511  // Encode Rd.
512  Binary |= getMachineOpValue(MI, MO0) << ARMII::RegRdShift;
513
514  // Encode imm.
515  Binary |= Lo16 & 0xFFF;
516  Binary |= ((Lo16 >> 12) & 0xF) << 16; // imm4:imm12, Insts[19-16] = imm4, Insts[11-0] = imm12
517  emitWordLE(Binary);
518
519  unsigned Hi16 = (getMovi32Value(MI, MO1, ARM::reloc_arm_movt) >> 16) & 0xFFFF;
520  // Emit the 'mov' instruction.
521  Binary = 0x34 << 20; // movt: Insts[27-20] = 0b00110100
522
523  // Set the conditional execution predicate.
524  Binary |= II->getPredicate(&MI) << ARMII::CondShift;
525
526  // Encode Rd.
527  Binary |= getMachineOpValue(MI, MO0) << ARMII::RegRdShift;
528
529  Binary |= Hi16 & 0xFFF;
530  Binary |= ((Hi16 >> 12) & 0xF) << 16;
531  emitWordLE(Binary);
532}
533
534void ARMCodeEmitter::emitMOVi2piecesInstruction(const MachineInstr &MI) {
535  const MachineOperand &MO0 = MI.getOperand(0);
536  const MachineOperand &MO1 = MI.getOperand(1);
537  assert(MO1.isImm() && ARM_AM::isSOImmTwoPartVal(MO1.getImm()) &&
538                                                  "Not a valid so_imm value!");
539  unsigned V1 = ARM_AM::getSOImmTwoPartFirst(MO1.getImm());
540  unsigned V2 = ARM_AM::getSOImmTwoPartSecond(MO1.getImm());
541
542  // Emit the 'mov' instruction.
543  unsigned Binary = 0xd << 21;  // mov: Insts{24-21} = 0b1101
544
545  // Set the conditional execution predicate.
546  Binary |= II->getPredicate(&MI) << ARMII::CondShift;
547
548  // Encode Rd.
549  Binary |= getMachineOpValue(MI, MO0) << ARMII::RegRdShift;
550
551  // Encode so_imm.
552  // Set bit I(25) to identify this is the immediate form of <shifter_op>
553  Binary |= 1 << ARMII::I_BitShift;
554  Binary |= getMachineSoImmOpValue(V1);
555  emitWordLE(Binary);
556
557  // Now the 'orr' instruction.
558  Binary = 0xc << 21;  // orr: Insts{24-21} = 0b1100
559
560  // Set the conditional execution predicate.
561  Binary |= II->getPredicate(&MI) << ARMII::CondShift;
562
563  // Encode Rd.
564  Binary |= getMachineOpValue(MI, MO0) << ARMII::RegRdShift;
565
566  // Encode Rn.
567  Binary |= getMachineOpValue(MI, MO0) << ARMII::RegRnShift;
568
569  // Encode so_imm.
570  // Set bit I(25) to identify this is the immediate form of <shifter_op>
571  Binary |= 1 << ARMII::I_BitShift;
572  Binary |= getMachineSoImmOpValue(V2);
573  emitWordLE(Binary);
574}
575
576void ARMCodeEmitter::emitLEApcrelJTInstruction(const MachineInstr &MI) {
577  // It's basically add r, pc, (LJTI - $+8)
578
579  const TargetInstrDesc &TID = MI.getDesc();
580
581  // Emit the 'add' instruction.
582  unsigned Binary = 0x4 << 21;  // add: Insts{24-31} = 0b0100
583
584  // Set the conditional execution predicate
585  Binary |= II->getPredicate(&MI) << ARMII::CondShift;
586
587  // Encode S bit if MI modifies CPSR.
588  Binary |= getAddrModeSBit(MI, TID);
589
590  // Encode Rd.
591  Binary |= getMachineOpValue(MI, 0) << ARMII::RegRdShift;
592
593  // Encode Rn which is PC.
594  Binary |= ARMRegisterInfo::getRegisterNumbering(ARM::PC) << ARMII::RegRnShift;
595
596  // Encode the displacement.
597  Binary |= 1 << ARMII::I_BitShift;
598  emitJumpTableAddress(MI.getOperand(1).getIndex(), ARM::reloc_arm_jt_base);
599
600  emitWordLE(Binary);
601}
602
603void ARMCodeEmitter::emitPseudoMoveInstruction(const MachineInstr &MI) {
604  unsigned Opcode = MI.getDesc().Opcode;
605
606  // Part of binary is determined by TableGn.
607  unsigned Binary = getBinaryCodeForInstr(MI);
608
609  // Set the conditional execution predicate
610  Binary |= II->getPredicate(&MI) << ARMII::CondShift;
611
612  // Encode S bit if MI modifies CPSR.
613  if (Opcode == ARM::MOVsrl_flag || Opcode == ARM::MOVsra_flag)
614    Binary |= 1 << ARMII::S_BitShift;
615
616  // Encode register def if there is one.
617  Binary |= getMachineOpValue(MI, 0) << ARMII::RegRdShift;
618
619  // Encode the shift operation.
620  switch (Opcode) {
621  default: break;
622  case ARM::MOVrx:
623    // rrx
624    Binary |= 0x6 << 4;
625    break;
626  case ARM::MOVsrl_flag:
627    // lsr #1
628    Binary |= (0x2 << 4) | (1 << 7);
629    break;
630  case ARM::MOVsra_flag:
631    // asr #1
632    Binary |= (0x4 << 4) | (1 << 7);
633    break;
634  }
635
636  // Encode register Rm.
637  Binary |= getMachineOpValue(MI, 1);
638
639  emitWordLE(Binary);
640}
641
642void ARMCodeEmitter::addPCLabel(unsigned LabelID) {
643  DEBUG(errs() << "  ** LPC" << LabelID << " @ "
644        << (void*)MCE.getCurrentPCValue() << '\n');
645  JTI->addPCLabelAddr(LabelID, MCE.getCurrentPCValue());
646}
647
648void ARMCodeEmitter::emitPseudoInstruction(const MachineInstr &MI) {
649  unsigned Opcode = MI.getDesc().Opcode;
650  switch (Opcode) {
651  default:
652    llvm_unreachable("ARMCodeEmitter::emitPseudoInstruction");
653  case TargetOpcode::INLINEASM: {
654    // We allow inline assembler nodes with empty bodies - they can
655    // implicitly define registers, which is ok for JIT.
656    if (MI.getOperand(0).getSymbolName()[0]) {
657      report_fatal_error("JIT does not support inline asm!");
658    }
659    break;
660  }
661  case TargetOpcode::DBG_LABEL:
662  case TargetOpcode::EH_LABEL:
663    MCE.emitLabel(MI.getOperand(0).getMCSymbol());
664    break;
665  case TargetOpcode::IMPLICIT_DEF:
666  case TargetOpcode::KILL:
667    // Do nothing.
668    break;
669  case ARM::CONSTPOOL_ENTRY:
670    emitConstPoolInstruction(MI);
671    break;
672  case ARM::PICADD: {
673    // Remember of the address of the PC label for relocation later.
674    addPCLabel(MI.getOperand(2).getImm());
675    // PICADD is just an add instruction that implicitly read pc.
676    emitDataProcessingInstruction(MI, 0, ARM::PC);
677    break;
678  }
679  case ARM::PICLDR:
680  case ARM::PICLDRB:
681  case ARM::PICSTR:
682  case ARM::PICSTRB: {
683    // Remember of the address of the PC label for relocation later.
684    addPCLabel(MI.getOperand(2).getImm());
685    // These are just load / store instructions that implicitly read pc.
686    emitLoadStoreInstruction(MI, 0, ARM::PC);
687    break;
688  }
689  case ARM::PICLDRH:
690  case ARM::PICLDRSH:
691  case ARM::PICLDRSB:
692  case ARM::PICSTRH: {
693    // Remember of the address of the PC label for relocation later.
694    addPCLabel(MI.getOperand(2).getImm());
695    // These are just load / store instructions that implicitly read pc.
696    emitMiscLoadStoreInstruction(MI, ARM::PC);
697    break;
698  }
699
700  case ARM::MOVi32imm:
701    emitMOVi32immInstruction(MI);
702    break;
703
704  case ARM::MOVi2pieces:
705    // Two instructions to materialize a constant.
706    emitMOVi2piecesInstruction(MI);
707    break;
708  case ARM::LEApcrelJT:
709    // Materialize jumptable address.
710    emitLEApcrelJTInstruction(MI);
711    break;
712  case ARM::MOVrx:
713  case ARM::MOVsrl_flag:
714  case ARM::MOVsra_flag:
715    emitPseudoMoveInstruction(MI);
716    break;
717  }
718}
719
720unsigned ARMCodeEmitter::getMachineSoRegOpValue(const MachineInstr &MI,
721                                                const TargetInstrDesc &TID,
722                                                const MachineOperand &MO,
723                                                unsigned OpIdx) {
724  unsigned Binary = getMachineOpValue(MI, MO);
725
726  const MachineOperand &MO1 = MI.getOperand(OpIdx + 1);
727  const MachineOperand &MO2 = MI.getOperand(OpIdx + 2);
728  ARM_AM::ShiftOpc SOpc = ARM_AM::getSORegShOp(MO2.getImm());
729
730  // Encode the shift opcode.
731  unsigned SBits = 0;
732  unsigned Rs = MO1.getReg();
733  if (Rs) {
734    // Set shift operand (bit[7:4]).
735    // LSL - 0001
736    // LSR - 0011
737    // ASR - 0101
738    // ROR - 0111
739    // RRX - 0110 and bit[11:8] clear.
740    switch (SOpc) {
741    default: llvm_unreachable("Unknown shift opc!");
742    case ARM_AM::lsl: SBits = 0x1; break;
743    case ARM_AM::lsr: SBits = 0x3; break;
744    case ARM_AM::asr: SBits = 0x5; break;
745    case ARM_AM::ror: SBits = 0x7; break;
746    case ARM_AM::rrx: SBits = 0x6; break;
747    }
748  } else {
749    // Set shift operand (bit[6:4]).
750    // LSL - 000
751    // LSR - 010
752    // ASR - 100
753    // ROR - 110
754    switch (SOpc) {
755    default: llvm_unreachable("Unknown shift opc!");
756    case ARM_AM::lsl: SBits = 0x0; break;
757    case ARM_AM::lsr: SBits = 0x2; break;
758    case ARM_AM::asr: SBits = 0x4; break;
759    case ARM_AM::ror: SBits = 0x6; break;
760    }
761  }
762  Binary |= SBits << 4;
763  if (SOpc == ARM_AM::rrx)
764    return Binary;
765
766  // Encode the shift operation Rs or shift_imm (except rrx).
767  if (Rs) {
768    // Encode Rs bit[11:8].
769    assert(ARM_AM::getSORegOffset(MO2.getImm()) == 0);
770    return Binary |
771      (ARMRegisterInfo::getRegisterNumbering(Rs) << ARMII::RegRsShift);
772  }
773
774  // Encode shift_imm bit[11:7].
775  return Binary | ARM_AM::getSORegOffset(MO2.getImm()) << 7;
776}
777
778unsigned ARMCodeEmitter::getMachineSoImmOpValue(unsigned SoImm) {
779  int SoImmVal = ARM_AM::getSOImmVal(SoImm);
780  assert(SoImmVal != -1 && "Not a valid so_imm value!");
781
782  // Encode rotate_imm.
783  unsigned Binary = (ARM_AM::getSOImmValRot((unsigned)SoImmVal) >> 1)
784    << ARMII::SoRotImmShift;
785
786  // Encode immed_8.
787  Binary |= ARM_AM::getSOImmValImm((unsigned)SoImmVal);
788  return Binary;
789}
790
791unsigned ARMCodeEmitter::getAddrModeSBit(const MachineInstr &MI,
792                                         const TargetInstrDesc &TID) const {
793  for (unsigned i = MI.getNumOperands(), e = TID.getNumOperands(); i != e; --i){
794    const MachineOperand &MO = MI.getOperand(i-1);
795    if (MO.isReg() && MO.isDef() && MO.getReg() == ARM::CPSR)
796      return 1 << ARMII::S_BitShift;
797  }
798  return 0;
799}
800
801void ARMCodeEmitter::emitDataProcessingInstruction(const MachineInstr &MI,
802                                                   unsigned ImplicitRd,
803                                                   unsigned ImplicitRn) {
804  const TargetInstrDesc &TID = MI.getDesc();
805
806  if (TID.Opcode == ARM::BFC) {
807    report_fatal_error("ARMv6t2 JIT is not yet supported.");
808  }
809
810  // Part of binary is determined by TableGn.
811  unsigned Binary = getBinaryCodeForInstr(MI);
812
813  // Set the conditional execution predicate
814  Binary |= II->getPredicate(&MI) << ARMII::CondShift;
815
816  // Encode S bit if MI modifies CPSR.
817  Binary |= getAddrModeSBit(MI, TID);
818
819  // Encode register def if there is one.
820  unsigned NumDefs = TID.getNumDefs();
821  unsigned OpIdx = 0;
822  if (NumDefs)
823    Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRdShift;
824  else if (ImplicitRd)
825    // Special handling for implicit use (e.g. PC).
826    Binary |= (ARMRegisterInfo::getRegisterNumbering(ImplicitRd)
827               << ARMII::RegRdShift);
828
829  // If this is a two-address operand, skip it. e.g. MOVCCr operand 1.
830  if (TID.getOperandConstraint(OpIdx, TOI::TIED_TO) != -1)
831    ++OpIdx;
832
833  // Encode first non-shifter register operand if there is one.
834  bool isUnary = TID.TSFlags & ARMII::UnaryDP;
835  if (!isUnary) {
836    if (ImplicitRn)
837      // Special handling for implicit use (e.g. PC).
838      Binary |= (ARMRegisterInfo::getRegisterNumbering(ImplicitRn)
839                 << ARMII::RegRnShift);
840    else {
841      Binary |= getMachineOpValue(MI, OpIdx) << ARMII::RegRnShift;
842      ++OpIdx;
843    }
844  }
845
846  // Encode shifter operand.
847  const MachineOperand &MO = MI.getOperand(OpIdx);
848  if ((TID.TSFlags & ARMII::FormMask) == ARMII::DPSoRegFrm) {
849    // Encode SoReg.
850    emitWordLE(Binary | getMachineSoRegOpValue(MI, TID, MO, OpIdx));
851    return;
852  }
853
854  if (MO.isReg()) {
855    // Encode register Rm.
856    emitWordLE(Binary | ARMRegisterInfo::getRegisterNumbering(MO.getReg()));
857    return;
858  }
859
860  // Encode so_imm.
861  Binary |= getMachineSoImmOpValue((unsigned)MO.getImm());
862
863  emitWordLE(Binary);
864}
865
866void ARMCodeEmitter::emitLoadStoreInstruction(const MachineInstr &MI,
867                                              unsigned ImplicitRd,
868                                              unsigned ImplicitRn) {
869  const TargetInstrDesc &TID = MI.getDesc();
870  unsigned Form = TID.TSFlags & ARMII::FormMask;
871  bool IsPrePost = (TID.TSFlags & ARMII::IndexModeMask) != 0;
872
873  // Part of binary is determined by TableGn.
874  unsigned Binary = getBinaryCodeForInstr(MI);
875
876  // Set the conditional execution predicate
877  Binary |= II->getPredicate(&MI) << ARMII::CondShift;
878
879  unsigned OpIdx = 0;
880
881  // Operand 0 of a pre- and post-indexed store is the address base
882  // writeback. Skip it.
883  bool Skipped = false;
884  if (IsPrePost && Form == ARMII::StFrm) {
885    ++OpIdx;
886    Skipped = true;
887  }
888
889  // Set first operand
890  if (ImplicitRd)
891    // Special handling for implicit use (e.g. PC).
892    Binary |= (ARMRegisterInfo::getRegisterNumbering(ImplicitRd)
893               << ARMII::RegRdShift);
894  else
895    Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRdShift;
896
897  // Set second operand
898  if (ImplicitRn)
899    // Special handling for implicit use (e.g. PC).
900    Binary |= (ARMRegisterInfo::getRegisterNumbering(ImplicitRn)
901               << ARMII::RegRnShift);
902  else
903    Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRnShift;
904
905  // If this is a two-address operand, skip it. e.g. LDR_PRE.
906  if (!Skipped && TID.getOperandConstraint(OpIdx, TOI::TIED_TO) != -1)
907    ++OpIdx;
908
909  const MachineOperand &MO2 = MI.getOperand(OpIdx);
910  unsigned AM2Opc = (ImplicitRn == ARM::PC)
911    ? 0 : MI.getOperand(OpIdx+1).getImm();
912
913  // Set bit U(23) according to sign of immed value (positive or negative).
914  Binary |= ((ARM_AM::getAM2Op(AM2Opc) == ARM_AM::add ? 1 : 0) <<
915             ARMII::U_BitShift);
916  if (!MO2.getReg()) { // is immediate
917    if (ARM_AM::getAM2Offset(AM2Opc))
918      // Set the value of offset_12 field
919      Binary |= ARM_AM::getAM2Offset(AM2Opc);
920    emitWordLE(Binary);
921    return;
922  }
923
924  // Set bit I(25), because this is not in immediate enconding.
925  Binary |= 1 << ARMII::I_BitShift;
926  assert(TargetRegisterInfo::isPhysicalRegister(MO2.getReg()));
927  // Set bit[3:0] to the corresponding Rm register
928  Binary |= ARMRegisterInfo::getRegisterNumbering(MO2.getReg());
929
930  // If this instr is in scaled register offset/index instruction, set
931  // shift_immed(bit[11:7]) and shift(bit[6:5]) fields.
932  if (unsigned ShImm = ARM_AM::getAM2Offset(AM2Opc)) {
933    Binary |= getShiftOp(AM2Opc) << ARMII::ShiftImmShift;  // shift
934    Binary |= ShImm              << ARMII::ShiftShift;     // shift_immed
935  }
936
937  emitWordLE(Binary);
938}
939
940void ARMCodeEmitter::emitMiscLoadStoreInstruction(const MachineInstr &MI,
941                                                  unsigned ImplicitRn) {
942  const TargetInstrDesc &TID = MI.getDesc();
943  unsigned Form = TID.TSFlags & ARMII::FormMask;
944  bool IsPrePost = (TID.TSFlags & ARMII::IndexModeMask) != 0;
945
946  // Part of binary is determined by TableGn.
947  unsigned Binary = getBinaryCodeForInstr(MI);
948
949  // Set the conditional execution predicate
950  Binary |= II->getPredicate(&MI) << ARMII::CondShift;
951
952  unsigned OpIdx = 0;
953
954  // Operand 0 of a pre- and post-indexed store is the address base
955  // writeback. Skip it.
956  bool Skipped = false;
957  if (IsPrePost && Form == ARMII::StMiscFrm) {
958    ++OpIdx;
959    Skipped = true;
960  }
961
962  // Set first operand
963  Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRdShift;
964
965  // Skip LDRD and STRD's second operand.
966  if (TID.Opcode == ARM::LDRD || TID.Opcode == ARM::STRD)
967    ++OpIdx;
968
969  // Set second operand
970  if (ImplicitRn)
971    // Special handling for implicit use (e.g. PC).
972    Binary |= (ARMRegisterInfo::getRegisterNumbering(ImplicitRn)
973               << ARMII::RegRnShift);
974  else
975    Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRnShift;
976
977  // If this is a two-address operand, skip it. e.g. LDRH_POST.
978  if (!Skipped && TID.getOperandConstraint(OpIdx, TOI::TIED_TO) != -1)
979    ++OpIdx;
980
981  const MachineOperand &MO2 = MI.getOperand(OpIdx);
982  unsigned AM3Opc = (ImplicitRn == ARM::PC)
983    ? 0 : MI.getOperand(OpIdx+1).getImm();
984
985  // Set bit U(23) according to sign of immed value (positive or negative)
986  Binary |= ((ARM_AM::getAM3Op(AM3Opc) == ARM_AM::add ? 1 : 0) <<
987             ARMII::U_BitShift);
988
989  // If this instr is in register offset/index encoding, set bit[3:0]
990  // to the corresponding Rm register.
991  if (MO2.getReg()) {
992    Binary |= ARMRegisterInfo::getRegisterNumbering(MO2.getReg());
993    emitWordLE(Binary);
994    return;
995  }
996
997  // This instr is in immediate offset/index encoding, set bit 22 to 1.
998  Binary |= 1 << ARMII::AM3_I_BitShift;
999  if (unsigned ImmOffs = ARM_AM::getAM3Offset(AM3Opc)) {
1000    // Set operands
1001    Binary |= (ImmOffs >> 4) << ARMII::ImmHiShift;  // immedH
1002    Binary |= (ImmOffs & 0xF);                      // immedL
1003  }
1004
1005  emitWordLE(Binary);
1006}
1007
1008static unsigned getAddrModeUPBits(unsigned Mode) {
1009  unsigned Binary = 0;
1010
1011  // Set addressing mode by modifying bits U(23) and P(24)
1012  // IA - Increment after  - bit U = 1 and bit P = 0
1013  // IB - Increment before - bit U = 1 and bit P = 1
1014  // DA - Decrement after  - bit U = 0 and bit P = 0
1015  // DB - Decrement before - bit U = 0 and bit P = 1
1016  switch (Mode) {
1017  default: llvm_unreachable("Unknown addressing sub-mode!");
1018  case ARM_AM::da:                                     break;
1019  case ARM_AM::db: Binary |= 0x1 << ARMII::P_BitShift; break;
1020  case ARM_AM::ia: Binary |= 0x1 << ARMII::U_BitShift; break;
1021  case ARM_AM::ib: Binary |= 0x3 << ARMII::U_BitShift; break;
1022  }
1023
1024  return Binary;
1025}
1026
1027void ARMCodeEmitter::emitLoadStoreMultipleInstruction(const MachineInstr &MI) {
1028  const TargetInstrDesc &TID = MI.getDesc();
1029  bool IsUpdating = (TID.TSFlags & ARMII::IndexModeMask) != 0;
1030
1031  // Part of binary is determined by TableGn.
1032  unsigned Binary = getBinaryCodeForInstr(MI);
1033
1034  // Set the conditional execution predicate
1035  Binary |= II->getPredicate(&MI) << ARMII::CondShift;
1036
1037  // Skip operand 0 of an instruction with base register update.
1038  unsigned OpIdx = 0;
1039  if (IsUpdating)
1040    ++OpIdx;
1041
1042  // Set base address operand
1043  Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRnShift;
1044
1045  // Set addressing mode by modifying bits U(23) and P(24)
1046  const MachineOperand &MO = MI.getOperand(OpIdx++);
1047  Binary |= getAddrModeUPBits(ARM_AM::getAM4SubMode(MO.getImm()));
1048
1049  // Set bit W(21)
1050  if (IsUpdating)
1051    Binary |= 0x1 << ARMII::W_BitShift;
1052
1053  // Set registers
1054  for (unsigned i = OpIdx+2, e = MI.getNumOperands(); i != e; ++i) {
1055    const MachineOperand &MO = MI.getOperand(i);
1056    if (!MO.isReg() || MO.isImplicit())
1057      break;
1058    unsigned RegNum = ARMRegisterInfo::getRegisterNumbering(MO.getReg());
1059    assert(TargetRegisterInfo::isPhysicalRegister(MO.getReg()) &&
1060           RegNum < 16);
1061    Binary |= 0x1 << RegNum;
1062  }
1063
1064  emitWordLE(Binary);
1065}
1066
1067void ARMCodeEmitter::emitMulFrmInstruction(const MachineInstr &MI) {
1068  const TargetInstrDesc &TID = MI.getDesc();
1069
1070  // Part of binary is determined by TableGn.
1071  unsigned Binary = getBinaryCodeForInstr(MI);
1072
1073  // Set the conditional execution predicate
1074  Binary |= II->getPredicate(&MI) << ARMII::CondShift;
1075
1076  // Encode S bit if MI modifies CPSR.
1077  Binary |= getAddrModeSBit(MI, TID);
1078
1079  // 32x32->64bit operations have two destination registers. The number
1080  // of register definitions will tell us if that's what we're dealing with.
1081  unsigned OpIdx = 0;
1082  if (TID.getNumDefs() == 2)
1083    Binary |= getMachineOpValue (MI, OpIdx++) << ARMII::RegRdLoShift;
1084
1085  // Encode Rd
1086  Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRdHiShift;
1087
1088  // Encode Rm
1089  Binary |= getMachineOpValue(MI, OpIdx++);
1090
1091  // Encode Rs
1092  Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRsShift;
1093
1094  // Many multiple instructions (e.g. MLA) have three src operands. Encode
1095  // it as Rn (for multiply, that's in the same offset as RdLo.
1096  if (TID.getNumOperands() > OpIdx &&
1097      !TID.OpInfo[OpIdx].isPredicate() &&
1098      !TID.OpInfo[OpIdx].isOptionalDef())
1099    Binary |= getMachineOpValue(MI, OpIdx) << ARMII::RegRdLoShift;
1100
1101  emitWordLE(Binary);
1102}
1103
1104void ARMCodeEmitter::emitExtendInstruction(const MachineInstr &MI) {
1105  const TargetInstrDesc &TID = MI.getDesc();
1106
1107  // Part of binary is determined by TableGn.
1108  unsigned Binary = getBinaryCodeForInstr(MI);
1109
1110  // Set the conditional execution predicate
1111  Binary |= II->getPredicate(&MI) << ARMII::CondShift;
1112
1113  unsigned OpIdx = 0;
1114
1115  // Encode Rd
1116  Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRdShift;
1117
1118  const MachineOperand &MO1 = MI.getOperand(OpIdx++);
1119  const MachineOperand &MO2 = MI.getOperand(OpIdx);
1120  if (MO2.isReg()) {
1121    // Two register operand form.
1122    // Encode Rn.
1123    Binary |= getMachineOpValue(MI, MO1) << ARMII::RegRnShift;
1124
1125    // Encode Rm.
1126    Binary |= getMachineOpValue(MI, MO2);
1127    ++OpIdx;
1128  } else {
1129    Binary |= getMachineOpValue(MI, MO1);
1130  }
1131
1132  // Encode rot imm (0, 8, 16, or 24) if it has a rotate immediate operand.
1133  if (MI.getOperand(OpIdx).isImm() &&
1134      !TID.OpInfo[OpIdx].isPredicate() &&
1135      !TID.OpInfo[OpIdx].isOptionalDef())
1136    Binary |= (getMachineOpValue(MI, OpIdx) / 8) << ARMII::ExtRotImmShift;
1137
1138  emitWordLE(Binary);
1139}
1140
1141void ARMCodeEmitter::emitMiscArithInstruction(const MachineInstr &MI) {
1142  const TargetInstrDesc &TID = MI.getDesc();
1143
1144  // Part of binary is determined by TableGn.
1145  unsigned Binary = getBinaryCodeForInstr(MI);
1146
1147  // Set the conditional execution predicate
1148  Binary |= II->getPredicate(&MI) << ARMII::CondShift;
1149
1150  unsigned OpIdx = 0;
1151
1152  // Encode Rd
1153  Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRdShift;
1154
1155  const MachineOperand &MO = MI.getOperand(OpIdx++);
1156  if (OpIdx == TID.getNumOperands() ||
1157      TID.OpInfo[OpIdx].isPredicate() ||
1158      TID.OpInfo[OpIdx].isOptionalDef()) {
1159    // Encode Rm and it's done.
1160    Binary |= getMachineOpValue(MI, MO);
1161    emitWordLE(Binary);
1162    return;
1163  }
1164
1165  // Encode Rn.
1166  Binary |= getMachineOpValue(MI, MO) << ARMII::RegRnShift;
1167
1168  // Encode Rm.
1169  Binary |= getMachineOpValue(MI, OpIdx++);
1170
1171  // Encode shift_imm.
1172  unsigned ShiftAmt = MI.getOperand(OpIdx).getImm();
1173  assert(ShiftAmt < 32 && "shift_imm range is 0 to 31!");
1174  Binary |= ShiftAmt << ARMII::ShiftShift;
1175
1176  emitWordLE(Binary);
1177}
1178
1179void ARMCodeEmitter::emitBranchInstruction(const MachineInstr &MI) {
1180  const TargetInstrDesc &TID = MI.getDesc();
1181
1182  if (TID.Opcode == ARM::TPsoft) {
1183    llvm_unreachable("ARM::TPsoft FIXME"); // FIXME
1184  }
1185
1186  // Part of binary is determined by TableGn.
1187  unsigned Binary = getBinaryCodeForInstr(MI);
1188
1189  // Set the conditional execution predicate
1190  Binary |= II->getPredicate(&MI) << ARMII::CondShift;
1191
1192  // Set signed_immed_24 field
1193  Binary |= getMachineOpValue(MI, 0);
1194
1195  emitWordLE(Binary);
1196}
1197
1198void ARMCodeEmitter::emitInlineJumpTable(unsigned JTIndex) {
1199  // Remember the base address of the inline jump table.
1200  uintptr_t JTBase = MCE.getCurrentPCValue();
1201  JTI->addJumpTableBaseAddr(JTIndex, JTBase);
1202  DEBUG(errs() << "  ** Jump Table #" << JTIndex << " @ " << (void*)JTBase
1203               << '\n');
1204
1205  // Now emit the jump table entries.
1206  const std::vector<MachineBasicBlock*> &MBBs = (*MJTEs)[JTIndex].MBBs;
1207  for (unsigned i = 0, e = MBBs.size(); i != e; ++i) {
1208    if (IsPIC)
1209      // DestBB address - JT base.
1210      emitMachineBasicBlock(MBBs[i], ARM::reloc_arm_pic_jt, JTBase);
1211    else
1212      // Absolute DestBB address.
1213      emitMachineBasicBlock(MBBs[i], ARM::reloc_arm_absolute);
1214    emitWordLE(0);
1215  }
1216}
1217
1218void ARMCodeEmitter::emitMiscBranchInstruction(const MachineInstr &MI) {
1219  const TargetInstrDesc &TID = MI.getDesc();
1220
1221  // Handle jump tables.
1222  if (TID.Opcode == ARM::BR_JTr || TID.Opcode == ARM::BR_JTadd) {
1223    // First emit a ldr pc, [] instruction.
1224    emitDataProcessingInstruction(MI, ARM::PC);
1225
1226    // Then emit the inline jump table.
1227    unsigned JTIndex =
1228      (TID.Opcode == ARM::BR_JTr)
1229      ? MI.getOperand(1).getIndex() : MI.getOperand(2).getIndex();
1230    emitInlineJumpTable(JTIndex);
1231    return;
1232  } else if (TID.Opcode == ARM::BR_JTm) {
1233    // First emit a ldr pc, [] instruction.
1234    emitLoadStoreInstruction(MI, ARM::PC);
1235
1236    // Then emit the inline jump table.
1237    emitInlineJumpTable(MI.getOperand(3).getIndex());
1238    return;
1239  }
1240
1241  // Part of binary is determined by TableGn.
1242  unsigned Binary = getBinaryCodeForInstr(MI);
1243
1244  // Set the conditional execution predicate
1245  Binary |= II->getPredicate(&MI) << ARMII::CondShift;
1246
1247  if (TID.Opcode == ARM::BX_RET || TID.Opcode == ARM::MOVPCLR)
1248    // The return register is LR.
1249    Binary |= ARMRegisterInfo::getRegisterNumbering(ARM::LR);
1250  else
1251    // otherwise, set the return register
1252    Binary |= getMachineOpValue(MI, 0);
1253
1254  emitWordLE(Binary);
1255}
1256
1257static unsigned encodeVFPRd(const MachineInstr &MI, unsigned OpIdx) {
1258  unsigned RegD = MI.getOperand(OpIdx).getReg();
1259  unsigned Binary = 0;
1260  bool isSPVFP = false;
1261  RegD = ARMRegisterInfo::getRegisterNumbering(RegD, &isSPVFP);
1262  if (!isSPVFP)
1263    Binary |=   RegD               << ARMII::RegRdShift;
1264  else {
1265    Binary |= ((RegD & 0x1E) >> 1) << ARMII::RegRdShift;
1266    Binary |=  (RegD & 0x01)       << ARMII::D_BitShift;
1267  }
1268  return Binary;
1269}
1270
1271static unsigned encodeVFPRn(const MachineInstr &MI, unsigned OpIdx) {
1272  unsigned RegN = MI.getOperand(OpIdx).getReg();
1273  unsigned Binary = 0;
1274  bool isSPVFP = false;
1275  RegN = ARMRegisterInfo::getRegisterNumbering(RegN, &isSPVFP);
1276  if (!isSPVFP)
1277    Binary |=   RegN               << ARMII::RegRnShift;
1278  else {
1279    Binary |= ((RegN & 0x1E) >> 1) << ARMII::RegRnShift;
1280    Binary |=  (RegN & 0x01)       << ARMII::N_BitShift;
1281  }
1282  return Binary;
1283}
1284
1285static unsigned encodeVFPRm(const MachineInstr &MI, unsigned OpIdx) {
1286  unsigned RegM = MI.getOperand(OpIdx).getReg();
1287  unsigned Binary = 0;
1288  bool isSPVFP = false;
1289  RegM = ARMRegisterInfo::getRegisterNumbering(RegM, &isSPVFP);
1290  if (!isSPVFP)
1291    Binary |=   RegM;
1292  else {
1293    Binary |= ((RegM & 0x1E) >> 1);
1294    Binary |=  (RegM & 0x01)       << ARMII::M_BitShift;
1295  }
1296  return Binary;
1297}
1298
1299void ARMCodeEmitter::emitVFPArithInstruction(const MachineInstr &MI) {
1300  const TargetInstrDesc &TID = MI.getDesc();
1301
1302  // Part of binary is determined by TableGn.
1303  unsigned Binary = getBinaryCodeForInstr(MI);
1304
1305  // Set the conditional execution predicate
1306  Binary |= II->getPredicate(&MI) << ARMII::CondShift;
1307
1308  unsigned OpIdx = 0;
1309  assert((Binary & ARMII::D_BitShift) == 0 &&
1310         (Binary & ARMII::N_BitShift) == 0 &&
1311         (Binary & ARMII::M_BitShift) == 0 && "VFP encoding bug!");
1312
1313  // Encode Dd / Sd.
1314  Binary |= encodeVFPRd(MI, OpIdx++);
1315
1316  // If this is a two-address operand, skip it, e.g. FMACD.
1317  if (TID.getOperandConstraint(OpIdx, TOI::TIED_TO) != -1)
1318    ++OpIdx;
1319
1320  // Encode Dn / Sn.
1321  if ((TID.TSFlags & ARMII::FormMask) == ARMII::VFPBinaryFrm)
1322    Binary |= encodeVFPRn(MI, OpIdx++);
1323
1324  if (OpIdx == TID.getNumOperands() ||
1325      TID.OpInfo[OpIdx].isPredicate() ||
1326      TID.OpInfo[OpIdx].isOptionalDef()) {
1327    // FCMPEZD etc. has only one operand.
1328    emitWordLE(Binary);
1329    return;
1330  }
1331
1332  // Encode Dm / Sm.
1333  Binary |= encodeVFPRm(MI, OpIdx);
1334
1335  emitWordLE(Binary);
1336}
1337
1338void ARMCodeEmitter::emitVFPConversionInstruction(const MachineInstr &MI) {
1339  const TargetInstrDesc &TID = MI.getDesc();
1340  unsigned Form = TID.TSFlags & ARMII::FormMask;
1341
1342  // Part of binary is determined by TableGn.
1343  unsigned Binary = getBinaryCodeForInstr(MI);
1344
1345  // Set the conditional execution predicate
1346  Binary |= II->getPredicate(&MI) << ARMII::CondShift;
1347
1348  switch (Form) {
1349  default: break;
1350  case ARMII::VFPConv1Frm:
1351  case ARMII::VFPConv2Frm:
1352  case ARMII::VFPConv3Frm:
1353    // Encode Dd / Sd.
1354    Binary |= encodeVFPRd(MI, 0);
1355    break;
1356  case ARMII::VFPConv4Frm:
1357    // Encode Dn / Sn.
1358    Binary |= encodeVFPRn(MI, 0);
1359    break;
1360  case ARMII::VFPConv5Frm:
1361    // Encode Dm / Sm.
1362    Binary |= encodeVFPRm(MI, 0);
1363    break;
1364  }
1365
1366  switch (Form) {
1367  default: break;
1368  case ARMII::VFPConv1Frm:
1369    // Encode Dm / Sm.
1370    Binary |= encodeVFPRm(MI, 1);
1371    break;
1372  case ARMII::VFPConv2Frm:
1373  case ARMII::VFPConv3Frm:
1374    // Encode Dn / Sn.
1375    Binary |= encodeVFPRn(MI, 1);
1376    break;
1377  case ARMII::VFPConv4Frm:
1378  case ARMII::VFPConv5Frm:
1379    // Encode Dd / Sd.
1380    Binary |= encodeVFPRd(MI, 1);
1381    break;
1382  }
1383
1384  if (Form == ARMII::VFPConv5Frm)
1385    // Encode Dn / Sn.
1386    Binary |= encodeVFPRn(MI, 2);
1387  else if (Form == ARMII::VFPConv3Frm)
1388    // Encode Dm / Sm.
1389    Binary |= encodeVFPRm(MI, 2);
1390
1391  emitWordLE(Binary);
1392}
1393
1394void ARMCodeEmitter::emitVFPLoadStoreInstruction(const MachineInstr &MI) {
1395  // Part of binary is determined by TableGn.
1396  unsigned Binary = getBinaryCodeForInstr(MI);
1397
1398  // Set the conditional execution predicate
1399  Binary |= II->getPredicate(&MI) << ARMII::CondShift;
1400
1401  unsigned OpIdx = 0;
1402
1403  // Encode Dd / Sd.
1404  Binary |= encodeVFPRd(MI, OpIdx++);
1405
1406  // Encode address base.
1407  const MachineOperand &Base = MI.getOperand(OpIdx++);
1408  Binary |= getMachineOpValue(MI, Base) << ARMII::RegRnShift;
1409
1410  // If there is a non-zero immediate offset, encode it.
1411  if (Base.isReg()) {
1412    const MachineOperand &Offset = MI.getOperand(OpIdx);
1413    if (unsigned ImmOffs = ARM_AM::getAM5Offset(Offset.getImm())) {
1414      if (ARM_AM::getAM5Op(Offset.getImm()) == ARM_AM::add)
1415        Binary |= 1 << ARMII::U_BitShift;
1416      Binary |= ImmOffs;
1417      emitWordLE(Binary);
1418      return;
1419    }
1420  }
1421
1422  // If immediate offset is omitted, default to +0.
1423  Binary |= 1 << ARMII::U_BitShift;
1424
1425  emitWordLE(Binary);
1426}
1427
1428void
1429ARMCodeEmitter::emitVFPLoadStoreMultipleInstruction(const MachineInstr &MI) {
1430  const TargetInstrDesc &TID = MI.getDesc();
1431  bool IsUpdating = (TID.TSFlags & ARMII::IndexModeMask) != 0;
1432
1433  // Part of binary is determined by TableGn.
1434  unsigned Binary = getBinaryCodeForInstr(MI);
1435
1436  // Set the conditional execution predicate
1437  Binary |= II->getPredicate(&MI) << ARMII::CondShift;
1438
1439  // Skip operand 0 of an instruction with base register update.
1440  unsigned OpIdx = 0;
1441  if (IsUpdating)
1442    ++OpIdx;
1443
1444  // Set base address operand
1445  Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRnShift;
1446
1447  // Set addressing mode by modifying bits U(23) and P(24)
1448  const MachineOperand &MO = MI.getOperand(OpIdx++);
1449  Binary |= getAddrModeUPBits(ARM_AM::getAM5SubMode(MO.getImm()));
1450
1451  // Set bit W(21)
1452  if (IsUpdating)
1453    Binary |= 0x1 << ARMII::W_BitShift;
1454
1455  // First register is encoded in Dd.
1456  Binary |= encodeVFPRd(MI, OpIdx+2);
1457
1458  // Number of registers are encoded in offset field.
1459  unsigned NumRegs = 1;
1460  for (unsigned i = OpIdx+3, e = MI.getNumOperands(); i != e; ++i) {
1461    const MachineOperand &MO = MI.getOperand(i);
1462    if (!MO.isReg() || MO.isImplicit())
1463      break;
1464    ++NumRegs;
1465  }
1466  Binary |= NumRegs * 2;
1467
1468  emitWordLE(Binary);
1469}
1470
1471void ARMCodeEmitter::emitMiscInstruction(const MachineInstr &MI) {
1472  // Part of binary is determined by TableGn.
1473  unsigned Binary = getBinaryCodeForInstr(MI);
1474
1475  // Set the conditional execution predicate
1476  Binary |= II->getPredicate(&MI) << ARMII::CondShift;
1477
1478  emitWordLE(Binary);
1479}
1480
1481#include "ARMGenCodeEmitter.inc"
1482