ARMCodeEmitter.cpp revision 81760863d144656b1d9753cbedb4d97927429b81
1//===-- ARM/ARMCodeEmitter.cpp - Convert ARM code to machine code ---------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file contains the pass that transforms the ARM machine instructions into 11// relocatable machine code. 12// 13//===----------------------------------------------------------------------===// 14 15#define DEBUG_TYPE "jit" 16#include "ARM.h" 17#include "ARMAddressingModes.h" 18#include "ARMConstantPoolValue.h" 19#include "ARMInstrInfo.h" 20#include "ARMRelocations.h" 21#include "ARMSubtarget.h" 22#include "ARMTargetMachine.h" 23#include "llvm/Constants.h" 24#include "llvm/DerivedTypes.h" 25#include "llvm/Function.h" 26#include "llvm/PassManager.h" 27#include "llvm/CodeGen/JITCodeEmitter.h" 28#include "llvm/CodeGen/MachineConstantPool.h" 29#include "llvm/CodeGen/MachineFunctionPass.h" 30#include "llvm/CodeGen/MachineInstr.h" 31#include "llvm/CodeGen/MachineJumpTableInfo.h" 32#include "llvm/CodeGen/MachineModuleInfo.h" 33#include "llvm/CodeGen/Passes.h" 34#include "llvm/ADT/Statistic.h" 35#include "llvm/Support/Debug.h" 36#include "llvm/Support/ErrorHandling.h" 37#include "llvm/Support/raw_ostream.h" 38#ifndef NDEBUG 39#include <iomanip> 40#endif 41using namespace llvm; 42 43STATISTIC(NumEmitted, "Number of machine instructions emitted"); 44 45namespace { 46 47 class ARMCodeEmitter : public MachineFunctionPass { 48 ARMJITInfo *JTI; 49 const ARMInstrInfo *II; 50 const TargetData *TD; 51 const ARMSubtarget *Subtarget; 52 TargetMachine &TM; 53 JITCodeEmitter &MCE; 54 MachineModuleInfo *MMI; 55 const std::vector<MachineConstantPoolEntry> *MCPEs; 56 const std::vector<MachineJumpTableEntry> *MJTEs; 57 bool IsPIC; 58 bool IsThumb; 59 60 void getAnalysisUsage(AnalysisUsage &AU) const { 61 AU.addRequired<MachineModuleInfo>(); 62 MachineFunctionPass::getAnalysisUsage(AU); 63 } 64 65 static char ID; 66 public: 67 ARMCodeEmitter(TargetMachine &tm, JITCodeEmitter &mce) 68 : MachineFunctionPass(ID), JTI(0), 69 II((const ARMInstrInfo *)tm.getInstrInfo()), 70 TD(tm.getTargetData()), TM(tm), 71 MCE(mce), MCPEs(0), MJTEs(0), 72 IsPIC(TM.getRelocationModel() == Reloc::PIC_), IsThumb(false) {} 73 74 /// getBinaryCodeForInstr - This function, generated by the 75 /// CodeEmitterGenerator using TableGen, produces the binary encoding for 76 /// machine instructions. 77 unsigned getBinaryCodeForInstr(const MachineInstr &MI); 78 79 bool runOnMachineFunction(MachineFunction &MF); 80 81 virtual const char *getPassName() const { 82 return "ARM Machine Code Emitter"; 83 } 84 85 void emitInstruction(const MachineInstr &MI); 86 87 private: 88 89 void emitWordLE(unsigned Binary); 90 void emitDWordLE(uint64_t Binary); 91 void emitConstPoolInstruction(const MachineInstr &MI); 92 void emitMOVi32immInstruction(const MachineInstr &MI); 93 void emitMOVi2piecesInstruction(const MachineInstr &MI); 94 void emitLEApcrelJTInstruction(const MachineInstr &MI); 95 void emitPseudoMoveInstruction(const MachineInstr &MI); 96 void addPCLabel(unsigned LabelID); 97 void emitPseudoInstruction(const MachineInstr &MI); 98 unsigned getMachineSoRegOpValue(const MachineInstr &MI, 99 const TargetInstrDesc &TID, 100 const MachineOperand &MO, 101 unsigned OpIdx); 102 103 unsigned getMachineSoImmOpValue(unsigned SoImm); 104 105 unsigned getAddrModeSBit(const MachineInstr &MI, 106 const TargetInstrDesc &TID) const; 107 108 void emitDataProcessingInstruction(const MachineInstr &MI, 109 unsigned ImplicitRd = 0, 110 unsigned ImplicitRn = 0); 111 112 void emitLoadStoreInstruction(const MachineInstr &MI, 113 unsigned ImplicitRd = 0, 114 unsigned ImplicitRn = 0); 115 116 void emitMiscLoadStoreInstruction(const MachineInstr &MI, 117 unsigned ImplicitRn = 0); 118 119 void emitLoadStoreMultipleInstruction(const MachineInstr &MI); 120 121 void emitMulFrmInstruction(const MachineInstr &MI); 122 123 void emitExtendInstruction(const MachineInstr &MI); 124 125 void emitMiscArithInstruction(const MachineInstr &MI); 126 127 void emitSaturateInstruction(const MachineInstr &MI); 128 129 void emitBranchInstruction(const MachineInstr &MI); 130 131 void emitInlineJumpTable(unsigned JTIndex); 132 133 void emitMiscBranchInstruction(const MachineInstr &MI); 134 135 void emitVFPArithInstruction(const MachineInstr &MI); 136 137 void emitVFPConversionInstruction(const MachineInstr &MI); 138 139 void emitVFPLoadStoreInstruction(const MachineInstr &MI); 140 141 void emitVFPLoadStoreMultipleInstruction(const MachineInstr &MI); 142 143 void emitMiscInstruction(const MachineInstr &MI); 144 145 void emitNEONLaneInstruction(const MachineInstr &MI); 146 void emitNEONDupInstruction(const MachineInstr &MI); 147 void emitNEON1RegModImmInstruction(const MachineInstr &MI); 148 void emitNEON2RegInstruction(const MachineInstr &MI); 149 void emitNEON3RegInstruction(const MachineInstr &MI); 150 151 /// getMachineOpValue - Return binary encoding of operand. If the machine 152 /// operand requires relocation, record the relocation and return zero. 153 unsigned getMachineOpValue(const MachineInstr &MI,const MachineOperand &MO); 154 unsigned getMachineOpValue(const MachineInstr &MI, unsigned OpIdx) { 155 return getMachineOpValue(MI, MI.getOperand(OpIdx)); 156 } 157 158 /// getMovi32Value - Return binary encoding of operand for movw/movt. If the 159 /// machine operand requires relocation, record the relocation and return 160 /// zero. 161 unsigned getMovi32Value(const MachineInstr &MI,const MachineOperand &MO, 162 unsigned Reloc); 163 164 /// getShiftOp - Return the shift opcode (bit[6:5]) of the immediate value. 165 /// 166 unsigned getShiftOp(unsigned Imm) const ; 167 168 /// Routines that handle operands which add machine relocations which are 169 /// fixed up by the relocation stage. 170 void emitGlobalAddress(const GlobalValue *GV, unsigned Reloc, 171 bool MayNeedFarStub, bool Indirect, 172 intptr_t ACPV = 0); 173 void emitExternalSymbolAddress(const char *ES, unsigned Reloc); 174 void emitConstPoolAddress(unsigned CPI, unsigned Reloc); 175 void emitJumpTableAddress(unsigned JTIndex, unsigned Reloc); 176 void emitMachineBasicBlock(MachineBasicBlock *BB, unsigned Reloc, 177 intptr_t JTBase = 0); 178 }; 179} 180 181char ARMCodeEmitter::ID = 0; 182 183/// createARMJITCodeEmitterPass - Return a pass that emits the collected ARM 184/// code to the specified MCE object. 185FunctionPass *llvm::createARMJITCodeEmitterPass(ARMBaseTargetMachine &TM, 186 JITCodeEmitter &JCE) { 187 return new ARMCodeEmitter(TM, JCE); 188} 189 190bool ARMCodeEmitter::runOnMachineFunction(MachineFunction &MF) { 191 assert((MF.getTarget().getRelocationModel() != Reloc::Default || 192 MF.getTarget().getRelocationModel() != Reloc::Static) && 193 "JIT relocation model must be set to static or default!"); 194 JTI = ((ARMTargetMachine &)MF.getTarget()).getJITInfo(); 195 II = ((const ARMTargetMachine &)MF.getTarget()).getInstrInfo(); 196 TD = ((const ARMTargetMachine &)MF.getTarget()).getTargetData(); 197 Subtarget = &TM.getSubtarget<ARMSubtarget>(); 198 MCPEs = &MF.getConstantPool()->getConstants(); 199 MJTEs = 0; 200 if (MF.getJumpTableInfo()) MJTEs = &MF.getJumpTableInfo()->getJumpTables(); 201 IsPIC = TM.getRelocationModel() == Reloc::PIC_; 202 IsThumb = MF.getInfo<ARMFunctionInfo>()->isThumbFunction(); 203 JTI->Initialize(MF, IsPIC); 204 MMI = &getAnalysis<MachineModuleInfo>(); 205 MCE.setModuleInfo(MMI); 206 207 do { 208 DEBUG(errs() << "JITTing function '" 209 << MF.getFunction()->getName() << "'\n"); 210 MCE.startFunction(MF); 211 for (MachineFunction::iterator MBB = MF.begin(), E = MF.end(); 212 MBB != E; ++MBB) { 213 MCE.StartMachineBasicBlock(MBB); 214 for (MachineBasicBlock::const_iterator I = MBB->begin(), E = MBB->end(); 215 I != E; ++I) 216 emitInstruction(*I); 217 } 218 } while (MCE.finishFunction(MF)); 219 220 return false; 221} 222 223/// getShiftOp - Return the shift opcode (bit[6:5]) of the immediate value. 224/// 225unsigned ARMCodeEmitter::getShiftOp(unsigned Imm) const { 226 switch (ARM_AM::getAM2ShiftOpc(Imm)) { 227 default: llvm_unreachable("Unknown shift opc!"); 228 case ARM_AM::asr: return 2; 229 case ARM_AM::lsl: return 0; 230 case ARM_AM::lsr: return 1; 231 case ARM_AM::ror: 232 case ARM_AM::rrx: return 3; 233 } 234 return 0; 235} 236 237/// getMovi32Value - Return binary encoding of operand for movw/movt. If the 238/// machine operand requires relocation, record the relocation and return zero. 239unsigned ARMCodeEmitter::getMovi32Value(const MachineInstr &MI, 240 const MachineOperand &MO, 241 unsigned Reloc) { 242 assert(((Reloc == ARM::reloc_arm_movt) || (Reloc == ARM::reloc_arm_movw)) 243 && "Relocation to this function should be for movt or movw"); 244 245 if (MO.isImm()) 246 return static_cast<unsigned>(MO.getImm()); 247 else if (MO.isGlobal()) 248 emitGlobalAddress(MO.getGlobal(), Reloc, true, false); 249 else if (MO.isSymbol()) 250 emitExternalSymbolAddress(MO.getSymbolName(), Reloc); 251 else if (MO.isMBB()) 252 emitMachineBasicBlock(MO.getMBB(), Reloc); 253 else { 254#ifndef NDEBUG 255 errs() << MO; 256#endif 257 llvm_unreachable("Unsupported operand type for movw/movt"); 258 } 259 return 0; 260} 261 262/// getMachineOpValue - Return binary encoding of operand. If the machine 263/// operand requires relocation, record the relocation and return zero. 264unsigned ARMCodeEmitter::getMachineOpValue(const MachineInstr &MI, 265 const MachineOperand &MO) { 266 if (MO.isReg()) 267 return ARMRegisterInfo::getRegisterNumbering(MO.getReg()); 268 else if (MO.isImm()) 269 return static_cast<unsigned>(MO.getImm()); 270 else if (MO.isGlobal()) 271 emitGlobalAddress(MO.getGlobal(), ARM::reloc_arm_branch, true, false); 272 else if (MO.isSymbol()) 273 emitExternalSymbolAddress(MO.getSymbolName(), ARM::reloc_arm_branch); 274 else if (MO.isCPI()) { 275 const TargetInstrDesc &TID = MI.getDesc(); 276 // For VFP load, the immediate offset is multiplied by 4. 277 unsigned Reloc = ((TID.TSFlags & ARMII::FormMask) == ARMII::VFPLdStFrm) 278 ? ARM::reloc_arm_vfp_cp_entry : ARM::reloc_arm_cp_entry; 279 emitConstPoolAddress(MO.getIndex(), Reloc); 280 } else if (MO.isJTI()) 281 emitJumpTableAddress(MO.getIndex(), ARM::reloc_arm_relative); 282 else if (MO.isMBB()) 283 emitMachineBasicBlock(MO.getMBB(), ARM::reloc_arm_branch); 284 else { 285#ifndef NDEBUG 286 errs() << MO; 287#endif 288 llvm_unreachable(0); 289 } 290 return 0; 291} 292 293/// emitGlobalAddress - Emit the specified address to the code stream. 294/// 295void ARMCodeEmitter::emitGlobalAddress(const GlobalValue *GV, unsigned Reloc, 296 bool MayNeedFarStub, bool Indirect, 297 intptr_t ACPV) { 298 MachineRelocation MR = Indirect 299 ? MachineRelocation::getIndirectSymbol(MCE.getCurrentPCOffset(), Reloc, 300 const_cast<GlobalValue *>(GV), 301 ACPV, MayNeedFarStub) 302 : MachineRelocation::getGV(MCE.getCurrentPCOffset(), Reloc, 303 const_cast<GlobalValue *>(GV), ACPV, 304 MayNeedFarStub); 305 MCE.addRelocation(MR); 306} 307 308/// emitExternalSymbolAddress - Arrange for the address of an external symbol to 309/// be emitted to the current location in the function, and allow it to be PC 310/// relative. 311void ARMCodeEmitter::emitExternalSymbolAddress(const char *ES, unsigned Reloc) { 312 MCE.addRelocation(MachineRelocation::getExtSym(MCE.getCurrentPCOffset(), 313 Reloc, ES)); 314} 315 316/// emitConstPoolAddress - Arrange for the address of an constant pool 317/// to be emitted to the current location in the function, and allow it to be PC 318/// relative. 319void ARMCodeEmitter::emitConstPoolAddress(unsigned CPI, unsigned Reloc) { 320 // Tell JIT emitter we'll resolve the address. 321 MCE.addRelocation(MachineRelocation::getConstPool(MCE.getCurrentPCOffset(), 322 Reloc, CPI, 0, true)); 323} 324 325/// emitJumpTableAddress - Arrange for the address of a jump table to 326/// be emitted to the current location in the function, and allow it to be PC 327/// relative. 328void ARMCodeEmitter::emitJumpTableAddress(unsigned JTIndex, unsigned Reloc) { 329 MCE.addRelocation(MachineRelocation::getJumpTable(MCE.getCurrentPCOffset(), 330 Reloc, JTIndex, 0, true)); 331} 332 333/// emitMachineBasicBlock - Emit the specified address basic block. 334void ARMCodeEmitter::emitMachineBasicBlock(MachineBasicBlock *BB, 335 unsigned Reloc, intptr_t JTBase) { 336 MCE.addRelocation(MachineRelocation::getBB(MCE.getCurrentPCOffset(), 337 Reloc, BB, JTBase)); 338} 339 340void ARMCodeEmitter::emitWordLE(unsigned Binary) { 341 DEBUG(errs() << " 0x"; 342 errs().write_hex(Binary) << "\n"); 343 MCE.emitWordLE(Binary); 344} 345 346void ARMCodeEmitter::emitDWordLE(uint64_t Binary) { 347 DEBUG(errs() << " 0x"; 348 errs().write_hex(Binary) << "\n"); 349 MCE.emitDWordLE(Binary); 350} 351 352void ARMCodeEmitter::emitInstruction(const MachineInstr &MI) { 353 DEBUG(errs() << "JIT: " << (void*)MCE.getCurrentPCValue() << ":\t" << MI); 354 355 MCE.processDebugLoc(MI.getDebugLoc(), true); 356 357 ++NumEmitted; // Keep track of the # of mi's emitted 358 switch (MI.getDesc().TSFlags & ARMII::FormMask) { 359 default: { 360 llvm_unreachable("Unhandled instruction encoding format!"); 361 break; 362 } 363 case ARMII::Pseudo: 364 emitPseudoInstruction(MI); 365 break; 366 case ARMII::DPFrm: 367 case ARMII::DPSoRegFrm: 368 emitDataProcessingInstruction(MI); 369 break; 370 case ARMII::LdFrm: 371 case ARMII::StFrm: 372 emitLoadStoreInstruction(MI); 373 break; 374 case ARMII::LdMiscFrm: 375 case ARMII::StMiscFrm: 376 emitMiscLoadStoreInstruction(MI); 377 break; 378 case ARMII::LdStMulFrm: 379 emitLoadStoreMultipleInstruction(MI); 380 break; 381 case ARMII::MulFrm: 382 emitMulFrmInstruction(MI); 383 break; 384 case ARMII::ExtFrm: 385 emitExtendInstruction(MI); 386 break; 387 case ARMII::ArithMiscFrm: 388 emitMiscArithInstruction(MI); 389 break; 390 case ARMII::SatFrm: 391 emitSaturateInstruction(MI); 392 break; 393 case ARMII::BrFrm: 394 emitBranchInstruction(MI); 395 break; 396 case ARMII::BrMiscFrm: 397 emitMiscBranchInstruction(MI); 398 break; 399 // VFP instructions. 400 case ARMII::VFPUnaryFrm: 401 case ARMII::VFPBinaryFrm: 402 emitVFPArithInstruction(MI); 403 break; 404 case ARMII::VFPConv1Frm: 405 case ARMII::VFPConv2Frm: 406 case ARMII::VFPConv3Frm: 407 case ARMII::VFPConv4Frm: 408 case ARMII::VFPConv5Frm: 409 emitVFPConversionInstruction(MI); 410 break; 411 case ARMII::VFPLdStFrm: 412 emitVFPLoadStoreInstruction(MI); 413 break; 414 case ARMII::VFPLdStMulFrm: 415 emitVFPLoadStoreMultipleInstruction(MI); 416 break; 417 case ARMII::VFPMiscFrm: 418 emitMiscInstruction(MI); 419 break; 420 // NEON instructions. 421 case ARMII::NGetLnFrm: 422 case ARMII::NSetLnFrm: 423 emitNEONLaneInstruction(MI); 424 break; 425 case ARMII::NDupFrm: 426 emitNEONDupInstruction(MI); 427 break; 428 case ARMII::N1RegModImmFrm: 429 emitNEON1RegModImmInstruction(MI); 430 break; 431 case ARMII::N2RegFrm: 432 emitNEON2RegInstruction(MI); 433 break; 434 case ARMII::N3RegFrm: 435 emitNEON3RegInstruction(MI); 436 break; 437 } 438 MCE.processDebugLoc(MI.getDebugLoc(), false); 439} 440 441void ARMCodeEmitter::emitConstPoolInstruction(const MachineInstr &MI) { 442 unsigned CPI = MI.getOperand(0).getImm(); // CP instruction index. 443 unsigned CPIndex = MI.getOperand(1).getIndex(); // Actual cp entry index. 444 const MachineConstantPoolEntry &MCPE = (*MCPEs)[CPIndex]; 445 446 // Remember the CONSTPOOL_ENTRY address for later relocation. 447 JTI->addConstantPoolEntryAddr(CPI, MCE.getCurrentPCValue()); 448 449 // Emit constpool island entry. In most cases, the actual values will be 450 // resolved and relocated after code emission. 451 if (MCPE.isMachineConstantPoolEntry()) { 452 ARMConstantPoolValue *ACPV = 453 static_cast<ARMConstantPoolValue*>(MCPE.Val.MachineCPVal); 454 455 DEBUG(errs() << " ** ARM constant pool #" << CPI << " @ " 456 << (void*)MCE.getCurrentPCValue() << " " << *ACPV << '\n'); 457 458 assert(ACPV->isGlobalValue() && "unsupported constant pool value"); 459 const GlobalValue *GV = ACPV->getGV(); 460 if (GV) { 461 Reloc::Model RelocM = TM.getRelocationModel(); 462 emitGlobalAddress(GV, ARM::reloc_arm_machine_cp_entry, 463 isa<Function>(GV), 464 Subtarget->GVIsIndirectSymbol(GV, RelocM), 465 (intptr_t)ACPV); 466 } else { 467 emitExternalSymbolAddress(ACPV->getSymbol(), ARM::reloc_arm_absolute); 468 } 469 emitWordLE(0); 470 } else { 471 const Constant *CV = MCPE.Val.ConstVal; 472 473 DEBUG({ 474 errs() << " ** Constant pool #" << CPI << " @ " 475 << (void*)MCE.getCurrentPCValue() << " "; 476 if (const Function *F = dyn_cast<Function>(CV)) 477 errs() << F->getName(); 478 else 479 errs() << *CV; 480 errs() << '\n'; 481 }); 482 483 if (const GlobalValue *GV = dyn_cast<GlobalValue>(CV)) { 484 emitGlobalAddress(GV, ARM::reloc_arm_absolute, isa<Function>(GV), false); 485 emitWordLE(0); 486 } else if (const ConstantInt *CI = dyn_cast<ConstantInt>(CV)) { 487 uint32_t Val = *(uint32_t*)CI->getValue().getRawData(); 488 emitWordLE(Val); 489 } else if (const ConstantFP *CFP = dyn_cast<ConstantFP>(CV)) { 490 if (CFP->getType()->isFloatTy()) 491 emitWordLE(CFP->getValueAPF().bitcastToAPInt().getZExtValue()); 492 else if (CFP->getType()->isDoubleTy()) 493 emitDWordLE(CFP->getValueAPF().bitcastToAPInt().getZExtValue()); 494 else { 495 llvm_unreachable("Unable to handle this constantpool entry!"); 496 } 497 } else { 498 llvm_unreachable("Unable to handle this constantpool entry!"); 499 } 500 } 501} 502 503void ARMCodeEmitter::emitMOVi32immInstruction(const MachineInstr &MI) { 504 const MachineOperand &MO0 = MI.getOperand(0); 505 const MachineOperand &MO1 = MI.getOperand(1); 506 507 // Emit the 'movw' instruction. 508 unsigned Binary = 0x30 << 20; // mov: Insts{27-20} = 0b00110000 509 510 unsigned Lo16 = getMovi32Value(MI, MO1, ARM::reloc_arm_movw) & 0xFFFF; 511 512 // Set the conditional execution predicate. 513 Binary |= II->getPredicate(&MI) << ARMII::CondShift; 514 515 // Encode Rd. 516 Binary |= getMachineOpValue(MI, MO0) << ARMII::RegRdShift; 517 518 // Encode imm16 as imm4:imm12 519 Binary |= Lo16 & 0xFFF; // Insts{11-0} = imm12 520 Binary |= ((Lo16 >> 12) & 0xF) << 16; // Insts{19-16} = imm4 521 emitWordLE(Binary); 522 523 unsigned Hi16 = getMovi32Value(MI, MO1, ARM::reloc_arm_movt) >> 16; 524 // Emit the 'movt' instruction. 525 Binary = 0x34 << 20; // movt: Insts{27-20} = 0b00110100 526 527 // Set the conditional execution predicate. 528 Binary |= II->getPredicate(&MI) << ARMII::CondShift; 529 530 // Encode Rd. 531 Binary |= getMachineOpValue(MI, MO0) << ARMII::RegRdShift; 532 533 // Encode imm16 as imm4:imm1, same as movw above. 534 Binary |= Hi16 & 0xFFF; 535 Binary |= ((Hi16 >> 12) & 0xF) << 16; 536 emitWordLE(Binary); 537} 538 539void ARMCodeEmitter::emitMOVi2piecesInstruction(const MachineInstr &MI) { 540 const MachineOperand &MO0 = MI.getOperand(0); 541 const MachineOperand &MO1 = MI.getOperand(1); 542 assert(MO1.isImm() && ARM_AM::isSOImmTwoPartVal(MO1.getImm()) && 543 "Not a valid so_imm value!"); 544 unsigned V1 = ARM_AM::getSOImmTwoPartFirst(MO1.getImm()); 545 unsigned V2 = ARM_AM::getSOImmTwoPartSecond(MO1.getImm()); 546 547 // Emit the 'mov' instruction. 548 unsigned Binary = 0xd << 21; // mov: Insts{24-21} = 0b1101 549 550 // Set the conditional execution predicate. 551 Binary |= II->getPredicate(&MI) << ARMII::CondShift; 552 553 // Encode Rd. 554 Binary |= getMachineOpValue(MI, MO0) << ARMII::RegRdShift; 555 556 // Encode so_imm. 557 // Set bit I(25) to identify this is the immediate form of <shifter_op> 558 Binary |= 1 << ARMII::I_BitShift; 559 Binary |= getMachineSoImmOpValue(V1); 560 emitWordLE(Binary); 561 562 // Now the 'orr' instruction. 563 Binary = 0xc << 21; // orr: Insts{24-21} = 0b1100 564 565 // Set the conditional execution predicate. 566 Binary |= II->getPredicate(&MI) << ARMII::CondShift; 567 568 // Encode Rd. 569 Binary |= getMachineOpValue(MI, MO0) << ARMII::RegRdShift; 570 571 // Encode Rn. 572 Binary |= getMachineOpValue(MI, MO0) << ARMII::RegRnShift; 573 574 // Encode so_imm. 575 // Set bit I(25) to identify this is the immediate form of <shifter_op> 576 Binary |= 1 << ARMII::I_BitShift; 577 Binary |= getMachineSoImmOpValue(V2); 578 emitWordLE(Binary); 579} 580 581void ARMCodeEmitter::emitLEApcrelJTInstruction(const MachineInstr &MI) { 582 // It's basically add r, pc, (LJTI - $+8) 583 584 const TargetInstrDesc &TID = MI.getDesc(); 585 586 // Emit the 'add' instruction. 587 unsigned Binary = 0x4 << 21; // add: Insts{24-31} = 0b0100 588 589 // Set the conditional execution predicate 590 Binary |= II->getPredicate(&MI) << ARMII::CondShift; 591 592 // Encode S bit if MI modifies CPSR. 593 Binary |= getAddrModeSBit(MI, TID); 594 595 // Encode Rd. 596 Binary |= getMachineOpValue(MI, 0) << ARMII::RegRdShift; 597 598 // Encode Rn which is PC. 599 Binary |= ARMRegisterInfo::getRegisterNumbering(ARM::PC) << ARMII::RegRnShift; 600 601 // Encode the displacement. 602 Binary |= 1 << ARMII::I_BitShift; 603 emitJumpTableAddress(MI.getOperand(1).getIndex(), ARM::reloc_arm_jt_base); 604 605 emitWordLE(Binary); 606} 607 608void ARMCodeEmitter::emitPseudoMoveInstruction(const MachineInstr &MI) { 609 unsigned Opcode = MI.getDesc().Opcode; 610 611 // Part of binary is determined by TableGn. 612 unsigned Binary = getBinaryCodeForInstr(MI); 613 614 // Set the conditional execution predicate 615 Binary |= II->getPredicate(&MI) << ARMII::CondShift; 616 617 // Encode S bit if MI modifies CPSR. 618 if (Opcode == ARM::MOVsrl_flag || Opcode == ARM::MOVsra_flag) 619 Binary |= 1 << ARMII::S_BitShift; 620 621 // Encode register def if there is one. 622 Binary |= getMachineOpValue(MI, 0) << ARMII::RegRdShift; 623 624 // Encode the shift operation. 625 switch (Opcode) { 626 default: break; 627 case ARM::MOVrx: 628 // rrx 629 Binary |= 0x6 << 4; 630 break; 631 case ARM::MOVsrl_flag: 632 // lsr #1 633 Binary |= (0x2 << 4) | (1 << 7); 634 break; 635 case ARM::MOVsra_flag: 636 // asr #1 637 Binary |= (0x4 << 4) | (1 << 7); 638 break; 639 } 640 641 // Encode register Rm. 642 Binary |= getMachineOpValue(MI, 1); 643 644 emitWordLE(Binary); 645} 646 647void ARMCodeEmitter::addPCLabel(unsigned LabelID) { 648 DEBUG(errs() << " ** LPC" << LabelID << " @ " 649 << (void*)MCE.getCurrentPCValue() << '\n'); 650 JTI->addPCLabelAddr(LabelID, MCE.getCurrentPCValue()); 651} 652 653void ARMCodeEmitter::emitPseudoInstruction(const MachineInstr &MI) { 654 unsigned Opcode = MI.getDesc().Opcode; 655 switch (Opcode) { 656 default: 657 llvm_unreachable("ARMCodeEmitter::emitPseudoInstruction"); 658 case ARM::BX: 659 case ARM::BMOVPCRX: 660 case ARM::BXr9: 661 case ARM::BMOVPCRXr9: { 662 // First emit mov lr, pc 663 unsigned Binary = 0x01a0e00f; 664 Binary |= II->getPredicate(&MI) << ARMII::CondShift; 665 emitWordLE(Binary); 666 667 // and then emit the branch. 668 emitMiscBranchInstruction(MI); 669 break; 670 } 671 case TargetOpcode::INLINEASM: { 672 // We allow inline assembler nodes with empty bodies - they can 673 // implicitly define registers, which is ok for JIT. 674 if (MI.getOperand(0).getSymbolName()[0]) { 675 report_fatal_error("JIT does not support inline asm!"); 676 } 677 break; 678 } 679 case TargetOpcode::PROLOG_LABEL: 680 case TargetOpcode::EH_LABEL: 681 MCE.emitLabel(MI.getOperand(0).getMCSymbol()); 682 break; 683 case TargetOpcode::IMPLICIT_DEF: 684 case TargetOpcode::KILL: 685 // Do nothing. 686 break; 687 case ARM::CONSTPOOL_ENTRY: 688 emitConstPoolInstruction(MI); 689 break; 690 case ARM::PICADD: { 691 // Remember of the address of the PC label for relocation later. 692 addPCLabel(MI.getOperand(2).getImm()); 693 // PICADD is just an add instruction that implicitly read pc. 694 emitDataProcessingInstruction(MI, 0, ARM::PC); 695 break; 696 } 697 case ARM::PICLDR: 698 case ARM::PICLDRB: 699 case ARM::PICSTR: 700 case ARM::PICSTRB: { 701 // Remember of the address of the PC label for relocation later. 702 addPCLabel(MI.getOperand(2).getImm()); 703 // These are just load / store instructions that implicitly read pc. 704 emitLoadStoreInstruction(MI, 0, ARM::PC); 705 break; 706 } 707 case ARM::PICLDRH: 708 case ARM::PICLDRSH: 709 case ARM::PICLDRSB: 710 case ARM::PICSTRH: { 711 // Remember of the address of the PC label for relocation later. 712 addPCLabel(MI.getOperand(2).getImm()); 713 // These are just load / store instructions that implicitly read pc. 714 emitMiscLoadStoreInstruction(MI, ARM::PC); 715 break; 716 } 717 718 case ARM::MOVi32imm: 719 emitMOVi32immInstruction(MI); 720 break; 721 722 case ARM::MOVi2pieces: 723 // Two instructions to materialize a constant. 724 emitMOVi2piecesInstruction(MI); 725 break; 726 case ARM::LEApcrelJT: 727 // Materialize jumptable address. 728 emitLEApcrelJTInstruction(MI); 729 break; 730 case ARM::MOVrx: 731 case ARM::MOVsrl_flag: 732 case ARM::MOVsra_flag: 733 emitPseudoMoveInstruction(MI); 734 break; 735 } 736} 737 738unsigned ARMCodeEmitter::getMachineSoRegOpValue(const MachineInstr &MI, 739 const TargetInstrDesc &TID, 740 const MachineOperand &MO, 741 unsigned OpIdx) { 742 unsigned Binary = getMachineOpValue(MI, MO); 743 744 const MachineOperand &MO1 = MI.getOperand(OpIdx + 1); 745 const MachineOperand &MO2 = MI.getOperand(OpIdx + 2); 746 ARM_AM::ShiftOpc SOpc = ARM_AM::getSORegShOp(MO2.getImm()); 747 748 // Encode the shift opcode. 749 unsigned SBits = 0; 750 unsigned Rs = MO1.getReg(); 751 if (Rs) { 752 // Set shift operand (bit[7:4]). 753 // LSL - 0001 754 // LSR - 0011 755 // ASR - 0101 756 // ROR - 0111 757 // RRX - 0110 and bit[11:8] clear. 758 switch (SOpc) { 759 default: llvm_unreachable("Unknown shift opc!"); 760 case ARM_AM::lsl: SBits = 0x1; break; 761 case ARM_AM::lsr: SBits = 0x3; break; 762 case ARM_AM::asr: SBits = 0x5; break; 763 case ARM_AM::ror: SBits = 0x7; break; 764 case ARM_AM::rrx: SBits = 0x6; break; 765 } 766 } else { 767 // Set shift operand (bit[6:4]). 768 // LSL - 000 769 // LSR - 010 770 // ASR - 100 771 // ROR - 110 772 switch (SOpc) { 773 default: llvm_unreachable("Unknown shift opc!"); 774 case ARM_AM::lsl: SBits = 0x0; break; 775 case ARM_AM::lsr: SBits = 0x2; break; 776 case ARM_AM::asr: SBits = 0x4; break; 777 case ARM_AM::ror: SBits = 0x6; break; 778 } 779 } 780 Binary |= SBits << 4; 781 if (SOpc == ARM_AM::rrx) 782 return Binary; 783 784 // Encode the shift operation Rs or shift_imm (except rrx). 785 if (Rs) { 786 // Encode Rs bit[11:8]. 787 assert(ARM_AM::getSORegOffset(MO2.getImm()) == 0); 788 return Binary | 789 (ARMRegisterInfo::getRegisterNumbering(Rs) << ARMII::RegRsShift); 790 } 791 792 // Encode shift_imm bit[11:7]. 793 return Binary | ARM_AM::getSORegOffset(MO2.getImm()) << 7; 794} 795 796unsigned ARMCodeEmitter::getMachineSoImmOpValue(unsigned SoImm) { 797 int SoImmVal = ARM_AM::getSOImmVal(SoImm); 798 assert(SoImmVal != -1 && "Not a valid so_imm value!"); 799 800 // Encode rotate_imm. 801 unsigned Binary = (ARM_AM::getSOImmValRot((unsigned)SoImmVal) >> 1) 802 << ARMII::SoRotImmShift; 803 804 // Encode immed_8. 805 Binary |= ARM_AM::getSOImmValImm((unsigned)SoImmVal); 806 return Binary; 807} 808 809unsigned ARMCodeEmitter::getAddrModeSBit(const MachineInstr &MI, 810 const TargetInstrDesc &TID) const { 811 for (unsigned i = MI.getNumOperands(), e = TID.getNumOperands(); i != e; --i){ 812 const MachineOperand &MO = MI.getOperand(i-1); 813 if (MO.isReg() && MO.isDef() && MO.getReg() == ARM::CPSR) 814 return 1 << ARMII::S_BitShift; 815 } 816 return 0; 817} 818 819void ARMCodeEmitter::emitDataProcessingInstruction(const MachineInstr &MI, 820 unsigned ImplicitRd, 821 unsigned ImplicitRn) { 822 const TargetInstrDesc &TID = MI.getDesc(); 823 824 // Part of binary is determined by TableGn. 825 unsigned Binary = getBinaryCodeForInstr(MI); 826 827 // Set the conditional execution predicate 828 Binary |= II->getPredicate(&MI) << ARMII::CondShift; 829 830 // Encode S bit if MI modifies CPSR. 831 Binary |= getAddrModeSBit(MI, TID); 832 833 // Encode register def if there is one. 834 unsigned NumDefs = TID.getNumDefs(); 835 unsigned OpIdx = 0; 836 if (NumDefs) 837 Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRdShift; 838 else if (ImplicitRd) 839 // Special handling for implicit use (e.g. PC). 840 Binary |= (ARMRegisterInfo::getRegisterNumbering(ImplicitRd) 841 << ARMII::RegRdShift); 842 843 if (TID.Opcode == ARM::MOVi16) { 844 // Get immediate from MI. 845 unsigned Lo16 = getMovi32Value(MI, MI.getOperand(OpIdx), 846 ARM::reloc_arm_movw); 847 // Encode imm which is the same as in emitMOVi32immInstruction(). 848 Binary |= Lo16 & 0xFFF; 849 Binary |= ((Lo16 >> 12) & 0xF) << 16; 850 emitWordLE(Binary); 851 return; 852 } else if(TID.Opcode == ARM::MOVTi16) { 853 unsigned Hi16 = (getMovi32Value(MI, MI.getOperand(OpIdx), 854 ARM::reloc_arm_movt) >> 16); 855 Binary |= Hi16 & 0xFFF; 856 Binary |= ((Hi16 >> 12) & 0xF) << 16; 857 emitWordLE(Binary); 858 return; 859 } else if ((TID.Opcode == ARM::BFC) || (TID.Opcode == ARM::BFI)) { 860 uint32_t v = ~MI.getOperand(2).getImm(); 861 int32_t lsb = CountTrailingZeros_32(v); 862 int32_t msb = (32 - CountLeadingZeros_32(v)) - 1; 863 // Instr{20-16} = msb, Instr{11-7} = lsb 864 Binary |= (msb & 0x1F) << 16; 865 Binary |= (lsb & 0x1F) << 7; 866 emitWordLE(Binary); 867 return; 868 } else if ((TID.Opcode == ARM::UBFX) || (TID.Opcode == ARM::SBFX)) { 869 // Encode Rn in Instr{0-3} 870 Binary |= getMachineOpValue(MI, OpIdx++); 871 872 uint32_t lsb = MI.getOperand(OpIdx++).getImm(); 873 uint32_t widthm1 = MI.getOperand(OpIdx++).getImm() - 1; 874 875 // Instr{20-16} = widthm1, Instr{11-7} = lsb 876 Binary |= (widthm1 & 0x1F) << 16; 877 Binary |= (lsb & 0x1F) << 7; 878 emitWordLE(Binary); 879 return; 880 } 881 882 // If this is a two-address operand, skip it. e.g. MOVCCr operand 1. 883 if (TID.getOperandConstraint(OpIdx, TOI::TIED_TO) != -1) 884 ++OpIdx; 885 886 // Encode first non-shifter register operand if there is one. 887 bool isUnary = TID.TSFlags & ARMII::UnaryDP; 888 if (!isUnary) { 889 if (ImplicitRn) 890 // Special handling for implicit use (e.g. PC). 891 Binary |= (ARMRegisterInfo::getRegisterNumbering(ImplicitRn) 892 << ARMII::RegRnShift); 893 else { 894 Binary |= getMachineOpValue(MI, OpIdx) << ARMII::RegRnShift; 895 ++OpIdx; 896 } 897 } 898 899 // Encode shifter operand. 900 const MachineOperand &MO = MI.getOperand(OpIdx); 901 if ((TID.TSFlags & ARMII::FormMask) == ARMII::DPSoRegFrm) { 902 // Encode SoReg. 903 emitWordLE(Binary | getMachineSoRegOpValue(MI, TID, MO, OpIdx)); 904 return; 905 } 906 907 if (MO.isReg()) { 908 // Encode register Rm. 909 emitWordLE(Binary | ARMRegisterInfo::getRegisterNumbering(MO.getReg())); 910 return; 911 } 912 913 // Encode so_imm. 914 Binary |= getMachineSoImmOpValue((unsigned)MO.getImm()); 915 916 emitWordLE(Binary); 917} 918 919void ARMCodeEmitter::emitLoadStoreInstruction(const MachineInstr &MI, 920 unsigned ImplicitRd, 921 unsigned ImplicitRn) { 922 const TargetInstrDesc &TID = MI.getDesc(); 923 unsigned Form = TID.TSFlags & ARMII::FormMask; 924 bool IsPrePost = (TID.TSFlags & ARMII::IndexModeMask) != 0; 925 926 // Part of binary is determined by TableGn. 927 unsigned Binary = getBinaryCodeForInstr(MI); 928 929 // Set the conditional execution predicate 930 Binary |= II->getPredicate(&MI) << ARMII::CondShift; 931 932 unsigned OpIdx = 0; 933 934 // Operand 0 of a pre- and post-indexed store is the address base 935 // writeback. Skip it. 936 bool Skipped = false; 937 if (IsPrePost && Form == ARMII::StFrm) { 938 ++OpIdx; 939 Skipped = true; 940 } 941 942 // Set first operand 943 if (ImplicitRd) 944 // Special handling for implicit use (e.g. PC). 945 Binary |= (ARMRegisterInfo::getRegisterNumbering(ImplicitRd) 946 << ARMII::RegRdShift); 947 else 948 Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRdShift; 949 950 // Set second operand 951 if (ImplicitRn) 952 // Special handling for implicit use (e.g. PC). 953 Binary |= (ARMRegisterInfo::getRegisterNumbering(ImplicitRn) 954 << ARMII::RegRnShift); 955 else 956 Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRnShift; 957 958 // If this is a two-address operand, skip it. e.g. LDR_PRE. 959 if (!Skipped && TID.getOperandConstraint(OpIdx, TOI::TIED_TO) != -1) 960 ++OpIdx; 961 962 const MachineOperand &MO2 = MI.getOperand(OpIdx); 963 unsigned AM2Opc = (ImplicitRn == ARM::PC) 964 ? 0 : MI.getOperand(OpIdx+1).getImm(); 965 966 // Set bit U(23) according to sign of immed value (positive or negative). 967 Binary |= ((ARM_AM::getAM2Op(AM2Opc) == ARM_AM::add ? 1 : 0) << 968 ARMII::U_BitShift); 969 if (!MO2.getReg()) { // is immediate 970 if (ARM_AM::getAM2Offset(AM2Opc)) 971 // Set the value of offset_12 field 972 Binary |= ARM_AM::getAM2Offset(AM2Opc); 973 emitWordLE(Binary); 974 return; 975 } 976 977 // Set bit I(25), because this is not in immediate enconding. 978 Binary |= 1 << ARMII::I_BitShift; 979 assert(TargetRegisterInfo::isPhysicalRegister(MO2.getReg())); 980 // Set bit[3:0] to the corresponding Rm register 981 Binary |= ARMRegisterInfo::getRegisterNumbering(MO2.getReg()); 982 983 // If this instr is in scaled register offset/index instruction, set 984 // shift_immed(bit[11:7]) and shift(bit[6:5]) fields. 985 if (unsigned ShImm = ARM_AM::getAM2Offset(AM2Opc)) { 986 Binary |= getShiftOp(AM2Opc) << ARMII::ShiftImmShift; // shift 987 Binary |= ShImm << ARMII::ShiftShift; // shift_immed 988 } 989 990 emitWordLE(Binary); 991} 992 993void ARMCodeEmitter::emitMiscLoadStoreInstruction(const MachineInstr &MI, 994 unsigned ImplicitRn) { 995 const TargetInstrDesc &TID = MI.getDesc(); 996 unsigned Form = TID.TSFlags & ARMII::FormMask; 997 bool IsPrePost = (TID.TSFlags & ARMII::IndexModeMask) != 0; 998 999 // Part of binary is determined by TableGn. 1000 unsigned Binary = getBinaryCodeForInstr(MI); 1001 1002 // Set the conditional execution predicate 1003 Binary |= II->getPredicate(&MI) << ARMII::CondShift; 1004 1005 unsigned OpIdx = 0; 1006 1007 // Operand 0 of a pre- and post-indexed store is the address base 1008 // writeback. Skip it. 1009 bool Skipped = false; 1010 if (IsPrePost && Form == ARMII::StMiscFrm) { 1011 ++OpIdx; 1012 Skipped = true; 1013 } 1014 1015 // Set first operand 1016 Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRdShift; 1017 1018 // Skip LDRD and STRD's second operand. 1019 if (TID.Opcode == ARM::LDRD || TID.Opcode == ARM::STRD) 1020 ++OpIdx; 1021 1022 // Set second operand 1023 if (ImplicitRn) 1024 // Special handling for implicit use (e.g. PC). 1025 Binary |= (ARMRegisterInfo::getRegisterNumbering(ImplicitRn) 1026 << ARMII::RegRnShift); 1027 else 1028 Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRnShift; 1029 1030 // If this is a two-address operand, skip it. e.g. LDRH_POST. 1031 if (!Skipped && TID.getOperandConstraint(OpIdx, TOI::TIED_TO) != -1) 1032 ++OpIdx; 1033 1034 const MachineOperand &MO2 = MI.getOperand(OpIdx); 1035 unsigned AM3Opc = (ImplicitRn == ARM::PC) 1036 ? 0 : MI.getOperand(OpIdx+1).getImm(); 1037 1038 // Set bit U(23) according to sign of immed value (positive or negative) 1039 Binary |= ((ARM_AM::getAM3Op(AM3Opc) == ARM_AM::add ? 1 : 0) << 1040 ARMII::U_BitShift); 1041 1042 // If this instr is in register offset/index encoding, set bit[3:0] 1043 // to the corresponding Rm register. 1044 if (MO2.getReg()) { 1045 Binary |= ARMRegisterInfo::getRegisterNumbering(MO2.getReg()); 1046 emitWordLE(Binary); 1047 return; 1048 } 1049 1050 // This instr is in immediate offset/index encoding, set bit 22 to 1. 1051 Binary |= 1 << ARMII::AM3_I_BitShift; 1052 if (unsigned ImmOffs = ARM_AM::getAM3Offset(AM3Opc)) { 1053 // Set operands 1054 Binary |= (ImmOffs >> 4) << ARMII::ImmHiShift; // immedH 1055 Binary |= (ImmOffs & 0xF); // immedL 1056 } 1057 1058 emitWordLE(Binary); 1059} 1060 1061static unsigned getAddrModeUPBits(unsigned Mode) { 1062 unsigned Binary = 0; 1063 1064 // Set addressing mode by modifying bits U(23) and P(24) 1065 // IA - Increment after - bit U = 1 and bit P = 0 1066 // IB - Increment before - bit U = 1 and bit P = 1 1067 // DA - Decrement after - bit U = 0 and bit P = 0 1068 // DB - Decrement before - bit U = 0 and bit P = 1 1069 switch (Mode) { 1070 default: llvm_unreachable("Unknown addressing sub-mode!"); 1071 case ARM_AM::da: break; 1072 case ARM_AM::db: Binary |= 0x1 << ARMII::P_BitShift; break; 1073 case ARM_AM::ia: Binary |= 0x1 << ARMII::U_BitShift; break; 1074 case ARM_AM::ib: Binary |= 0x3 << ARMII::U_BitShift; break; 1075 } 1076 1077 return Binary; 1078} 1079 1080void ARMCodeEmitter::emitLoadStoreMultipleInstruction(const MachineInstr &MI) { 1081 const TargetInstrDesc &TID = MI.getDesc(); 1082 bool IsUpdating = (TID.TSFlags & ARMII::IndexModeMask) != 0; 1083 1084 // Part of binary is determined by TableGn. 1085 unsigned Binary = getBinaryCodeForInstr(MI); 1086 1087 // Set the conditional execution predicate 1088 Binary |= II->getPredicate(&MI) << ARMII::CondShift; 1089 1090 // Skip operand 0 of an instruction with base register update. 1091 unsigned OpIdx = 0; 1092 if (IsUpdating) 1093 ++OpIdx; 1094 1095 // Set base address operand 1096 Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRnShift; 1097 1098 // Set addressing mode by modifying bits U(23) and P(24) 1099 const MachineOperand &MO = MI.getOperand(OpIdx++); 1100 Binary |= getAddrModeUPBits(ARM_AM::getAM4SubMode(MO.getImm())); 1101 1102 // Set bit W(21) 1103 if (IsUpdating) 1104 Binary |= 0x1 << ARMII::W_BitShift; 1105 1106 // Set registers 1107 for (unsigned i = OpIdx+2, e = MI.getNumOperands(); i != e; ++i) { 1108 const MachineOperand &MO = MI.getOperand(i); 1109 if (!MO.isReg() || MO.isImplicit()) 1110 break; 1111 unsigned RegNum = ARMRegisterInfo::getRegisterNumbering(MO.getReg()); 1112 assert(TargetRegisterInfo::isPhysicalRegister(MO.getReg()) && 1113 RegNum < 16); 1114 Binary |= 0x1 << RegNum; 1115 } 1116 1117 emitWordLE(Binary); 1118} 1119 1120void ARMCodeEmitter::emitMulFrmInstruction(const MachineInstr &MI) { 1121 const TargetInstrDesc &TID = MI.getDesc(); 1122 1123 // Part of binary is determined by TableGn. 1124 unsigned Binary = getBinaryCodeForInstr(MI); 1125 1126 // Set the conditional execution predicate 1127 Binary |= II->getPredicate(&MI) << ARMII::CondShift; 1128 1129 // Encode S bit if MI modifies CPSR. 1130 Binary |= getAddrModeSBit(MI, TID); 1131 1132 // 32x32->64bit operations have two destination registers. The number 1133 // of register definitions will tell us if that's what we're dealing with. 1134 unsigned OpIdx = 0; 1135 if (TID.getNumDefs() == 2) 1136 Binary |= getMachineOpValue (MI, OpIdx++) << ARMII::RegRdLoShift; 1137 1138 // Encode Rd 1139 Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRdHiShift; 1140 1141 // Encode Rm 1142 Binary |= getMachineOpValue(MI, OpIdx++); 1143 1144 // Encode Rs 1145 Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRsShift; 1146 1147 // Many multiple instructions (e.g. MLA) have three src operands. Encode 1148 // it as Rn (for multiply, that's in the same offset as RdLo. 1149 if (TID.getNumOperands() > OpIdx && 1150 !TID.OpInfo[OpIdx].isPredicate() && 1151 !TID.OpInfo[OpIdx].isOptionalDef()) 1152 Binary |= getMachineOpValue(MI, OpIdx) << ARMII::RegRdLoShift; 1153 1154 emitWordLE(Binary); 1155} 1156 1157void ARMCodeEmitter::emitExtendInstruction(const MachineInstr &MI) { 1158 const TargetInstrDesc &TID = MI.getDesc(); 1159 1160 // Part of binary is determined by TableGn. 1161 unsigned Binary = getBinaryCodeForInstr(MI); 1162 1163 // Set the conditional execution predicate 1164 Binary |= II->getPredicate(&MI) << ARMII::CondShift; 1165 1166 unsigned OpIdx = 0; 1167 1168 // Encode Rd 1169 Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRdShift; 1170 1171 const MachineOperand &MO1 = MI.getOperand(OpIdx++); 1172 const MachineOperand &MO2 = MI.getOperand(OpIdx); 1173 if (MO2.isReg()) { 1174 // Two register operand form. 1175 // Encode Rn. 1176 Binary |= getMachineOpValue(MI, MO1) << ARMII::RegRnShift; 1177 1178 // Encode Rm. 1179 Binary |= getMachineOpValue(MI, MO2); 1180 ++OpIdx; 1181 } else { 1182 Binary |= getMachineOpValue(MI, MO1); 1183 } 1184 1185 // Encode rot imm (0, 8, 16, or 24) if it has a rotate immediate operand. 1186 if (MI.getOperand(OpIdx).isImm() && 1187 !TID.OpInfo[OpIdx].isPredicate() && 1188 !TID.OpInfo[OpIdx].isOptionalDef()) 1189 Binary |= (getMachineOpValue(MI, OpIdx) / 8) << ARMII::ExtRotImmShift; 1190 1191 emitWordLE(Binary); 1192} 1193 1194void ARMCodeEmitter::emitMiscArithInstruction(const MachineInstr &MI) { 1195 const TargetInstrDesc &TID = MI.getDesc(); 1196 1197 // Part of binary is determined by TableGn. 1198 unsigned Binary = getBinaryCodeForInstr(MI); 1199 1200 // Set the conditional execution predicate 1201 Binary |= II->getPredicate(&MI) << ARMII::CondShift; 1202 1203 unsigned OpIdx = 0; 1204 1205 // Encode Rd 1206 Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRdShift; 1207 1208 const MachineOperand &MO = MI.getOperand(OpIdx++); 1209 if (OpIdx == TID.getNumOperands() || 1210 TID.OpInfo[OpIdx].isPredicate() || 1211 TID.OpInfo[OpIdx].isOptionalDef()) { 1212 // Encode Rm and it's done. 1213 Binary |= getMachineOpValue(MI, MO); 1214 emitWordLE(Binary); 1215 return; 1216 } 1217 1218 // Encode Rn. 1219 Binary |= getMachineOpValue(MI, MO) << ARMII::RegRnShift; 1220 1221 // Encode Rm. 1222 Binary |= getMachineOpValue(MI, OpIdx++); 1223 1224 // Encode shift_imm. 1225 unsigned ShiftAmt = MI.getOperand(OpIdx).getImm(); 1226 if (TID.Opcode == ARM::PKHTB) { 1227 assert(ShiftAmt != 0 && "PKHTB shift_imm is 0!"); 1228 if (ShiftAmt == 32) 1229 ShiftAmt = 0; 1230 } 1231 assert(ShiftAmt < 32 && "shift_imm range is 0 to 31!"); 1232 Binary |= ShiftAmt << ARMII::ShiftShift; 1233 1234 emitWordLE(Binary); 1235} 1236 1237void ARMCodeEmitter::emitSaturateInstruction(const MachineInstr &MI) { 1238 const TargetInstrDesc &TID = MI.getDesc(); 1239 1240 // Part of binary is determined by TableGen. 1241 unsigned Binary = getBinaryCodeForInstr(MI); 1242 1243 // Set the conditional execution predicate 1244 Binary |= II->getPredicate(&MI) << ARMII::CondShift; 1245 1246 // Encode Rd 1247 Binary |= getMachineOpValue(MI, 0) << ARMII::RegRdShift; 1248 1249 // Encode saturate bit position. 1250 unsigned Pos = MI.getOperand(1).getImm(); 1251 if (TID.Opcode == ARM::SSAT || TID.Opcode == ARM::SSAT16) 1252 Pos -= 1; 1253 assert((Pos < 16 || (Pos < 32 && 1254 TID.Opcode != ARM::SSAT16 && 1255 TID.Opcode != ARM::USAT16)) && 1256 "saturate bit position out of range"); 1257 Binary |= Pos << 16; 1258 1259 // Encode Rm 1260 Binary |= getMachineOpValue(MI, 2); 1261 1262 // Encode shift_imm. 1263 if (TID.getNumOperands() == 4) { 1264 unsigned ShiftOp = MI.getOperand(3).getImm(); 1265 ARM_AM::ShiftOpc Opc = ARM_AM::getSORegShOp(ShiftOp); 1266 if (Opc == ARM_AM::asr) 1267 Binary |= (1 << 6); 1268 unsigned ShiftAmt = MI.getOperand(3).getImm(); 1269 if (ShiftAmt == 32 && Opc == ARM_AM::asr) 1270 ShiftAmt = 0; 1271 assert(ShiftAmt < 32 && "shift_imm range is 0 to 31!"); 1272 Binary |= ShiftAmt << ARMII::ShiftShift; 1273 } 1274 1275 emitWordLE(Binary); 1276} 1277 1278void ARMCodeEmitter::emitBranchInstruction(const MachineInstr &MI) { 1279 const TargetInstrDesc &TID = MI.getDesc(); 1280 1281 if (TID.Opcode == ARM::TPsoft) { 1282 llvm_unreachable("ARM::TPsoft FIXME"); // FIXME 1283 } 1284 1285 // Part of binary is determined by TableGn. 1286 unsigned Binary = getBinaryCodeForInstr(MI); 1287 1288 // Set the conditional execution predicate 1289 Binary |= II->getPredicate(&MI) << ARMII::CondShift; 1290 1291 // Set signed_immed_24 field 1292 Binary |= getMachineOpValue(MI, 0); 1293 1294 emitWordLE(Binary); 1295} 1296 1297void ARMCodeEmitter::emitInlineJumpTable(unsigned JTIndex) { 1298 // Remember the base address of the inline jump table. 1299 uintptr_t JTBase = MCE.getCurrentPCValue(); 1300 JTI->addJumpTableBaseAddr(JTIndex, JTBase); 1301 DEBUG(errs() << " ** Jump Table #" << JTIndex << " @ " << (void*)JTBase 1302 << '\n'); 1303 1304 // Now emit the jump table entries. 1305 const std::vector<MachineBasicBlock*> &MBBs = (*MJTEs)[JTIndex].MBBs; 1306 for (unsigned i = 0, e = MBBs.size(); i != e; ++i) { 1307 if (IsPIC) 1308 // DestBB address - JT base. 1309 emitMachineBasicBlock(MBBs[i], ARM::reloc_arm_pic_jt, JTBase); 1310 else 1311 // Absolute DestBB address. 1312 emitMachineBasicBlock(MBBs[i], ARM::reloc_arm_absolute); 1313 emitWordLE(0); 1314 } 1315} 1316 1317void ARMCodeEmitter::emitMiscBranchInstruction(const MachineInstr &MI) { 1318 const TargetInstrDesc &TID = MI.getDesc(); 1319 1320 // Handle jump tables. 1321 if (TID.Opcode == ARM::BR_JTr || TID.Opcode == ARM::BR_JTadd) { 1322 // First emit a ldr pc, [] instruction. 1323 emitDataProcessingInstruction(MI, ARM::PC); 1324 1325 // Then emit the inline jump table. 1326 unsigned JTIndex = 1327 (TID.Opcode == ARM::BR_JTr) 1328 ? MI.getOperand(1).getIndex() : MI.getOperand(2).getIndex(); 1329 emitInlineJumpTable(JTIndex); 1330 return; 1331 } else if (TID.Opcode == ARM::BR_JTm) { 1332 // First emit a ldr pc, [] instruction. 1333 emitLoadStoreInstruction(MI, ARM::PC); 1334 1335 // Then emit the inline jump table. 1336 emitInlineJumpTable(MI.getOperand(3).getIndex()); 1337 return; 1338 } 1339 1340 // Part of binary is determined by TableGn. 1341 unsigned Binary = getBinaryCodeForInstr(MI); 1342 1343 // Set the conditional execution predicate 1344 Binary |= II->getPredicate(&MI) << ARMII::CondShift; 1345 1346 if (TID.Opcode == ARM::BX_RET || TID.Opcode == ARM::MOVPCLR) 1347 // The return register is LR. 1348 Binary |= ARMRegisterInfo::getRegisterNumbering(ARM::LR); 1349 else 1350 // otherwise, set the return register 1351 Binary |= getMachineOpValue(MI, 0); 1352 1353 emitWordLE(Binary); 1354} 1355 1356static unsigned encodeVFPRd(const MachineInstr &MI, unsigned OpIdx) { 1357 unsigned RegD = MI.getOperand(OpIdx).getReg(); 1358 unsigned Binary = 0; 1359 bool isSPVFP = false; 1360 RegD = ARMRegisterInfo::getRegisterNumbering(RegD, &isSPVFP); 1361 if (!isSPVFP) 1362 Binary |= RegD << ARMII::RegRdShift; 1363 else { 1364 Binary |= ((RegD & 0x1E) >> 1) << ARMII::RegRdShift; 1365 Binary |= (RegD & 0x01) << ARMII::D_BitShift; 1366 } 1367 return Binary; 1368} 1369 1370static unsigned encodeVFPRn(const MachineInstr &MI, unsigned OpIdx) { 1371 unsigned RegN = MI.getOperand(OpIdx).getReg(); 1372 unsigned Binary = 0; 1373 bool isSPVFP = false; 1374 RegN = ARMRegisterInfo::getRegisterNumbering(RegN, &isSPVFP); 1375 if (!isSPVFP) 1376 Binary |= RegN << ARMII::RegRnShift; 1377 else { 1378 Binary |= ((RegN & 0x1E) >> 1) << ARMII::RegRnShift; 1379 Binary |= (RegN & 0x01) << ARMII::N_BitShift; 1380 } 1381 return Binary; 1382} 1383 1384static unsigned encodeVFPRm(const MachineInstr &MI, unsigned OpIdx) { 1385 unsigned RegM = MI.getOperand(OpIdx).getReg(); 1386 unsigned Binary = 0; 1387 bool isSPVFP = false; 1388 RegM = ARMRegisterInfo::getRegisterNumbering(RegM, &isSPVFP); 1389 if (!isSPVFP) 1390 Binary |= RegM; 1391 else { 1392 Binary |= ((RegM & 0x1E) >> 1); 1393 Binary |= (RegM & 0x01) << ARMII::M_BitShift; 1394 } 1395 return Binary; 1396} 1397 1398void ARMCodeEmitter::emitVFPArithInstruction(const MachineInstr &MI) { 1399 const TargetInstrDesc &TID = MI.getDesc(); 1400 1401 // Part of binary is determined by TableGn. 1402 unsigned Binary = getBinaryCodeForInstr(MI); 1403 1404 // Set the conditional execution predicate 1405 Binary |= II->getPredicate(&MI) << ARMII::CondShift; 1406 1407 unsigned OpIdx = 0; 1408 assert((Binary & ARMII::D_BitShift) == 0 && 1409 (Binary & ARMII::N_BitShift) == 0 && 1410 (Binary & ARMII::M_BitShift) == 0 && "VFP encoding bug!"); 1411 1412 // Encode Dd / Sd. 1413 Binary |= encodeVFPRd(MI, OpIdx++); 1414 1415 // If this is a two-address operand, skip it, e.g. FMACD. 1416 if (TID.getOperandConstraint(OpIdx, TOI::TIED_TO) != -1) 1417 ++OpIdx; 1418 1419 // Encode Dn / Sn. 1420 if ((TID.TSFlags & ARMII::FormMask) == ARMII::VFPBinaryFrm) 1421 Binary |= encodeVFPRn(MI, OpIdx++); 1422 1423 if (OpIdx == TID.getNumOperands() || 1424 TID.OpInfo[OpIdx].isPredicate() || 1425 TID.OpInfo[OpIdx].isOptionalDef()) { 1426 // FCMPEZD etc. has only one operand. 1427 emitWordLE(Binary); 1428 return; 1429 } 1430 1431 // Encode Dm / Sm. 1432 Binary |= encodeVFPRm(MI, OpIdx); 1433 1434 emitWordLE(Binary); 1435} 1436 1437void ARMCodeEmitter::emitVFPConversionInstruction(const MachineInstr &MI) { 1438 const TargetInstrDesc &TID = MI.getDesc(); 1439 unsigned Form = TID.TSFlags & ARMII::FormMask; 1440 1441 // Part of binary is determined by TableGn. 1442 unsigned Binary = getBinaryCodeForInstr(MI); 1443 1444 // Set the conditional execution predicate 1445 Binary |= II->getPredicate(&MI) << ARMII::CondShift; 1446 1447 switch (Form) { 1448 default: break; 1449 case ARMII::VFPConv1Frm: 1450 case ARMII::VFPConv2Frm: 1451 case ARMII::VFPConv3Frm: 1452 // Encode Dd / Sd. 1453 Binary |= encodeVFPRd(MI, 0); 1454 break; 1455 case ARMII::VFPConv4Frm: 1456 // Encode Dn / Sn. 1457 Binary |= encodeVFPRn(MI, 0); 1458 break; 1459 case ARMII::VFPConv5Frm: 1460 // Encode Dm / Sm. 1461 Binary |= encodeVFPRm(MI, 0); 1462 break; 1463 } 1464 1465 switch (Form) { 1466 default: break; 1467 case ARMII::VFPConv1Frm: 1468 // Encode Dm / Sm. 1469 Binary |= encodeVFPRm(MI, 1); 1470 break; 1471 case ARMII::VFPConv2Frm: 1472 case ARMII::VFPConv3Frm: 1473 // Encode Dn / Sn. 1474 Binary |= encodeVFPRn(MI, 1); 1475 break; 1476 case ARMII::VFPConv4Frm: 1477 case ARMII::VFPConv5Frm: 1478 // Encode Dd / Sd. 1479 Binary |= encodeVFPRd(MI, 1); 1480 break; 1481 } 1482 1483 if (Form == ARMII::VFPConv5Frm) 1484 // Encode Dn / Sn. 1485 Binary |= encodeVFPRn(MI, 2); 1486 else if (Form == ARMII::VFPConv3Frm) 1487 // Encode Dm / Sm. 1488 Binary |= encodeVFPRm(MI, 2); 1489 1490 emitWordLE(Binary); 1491} 1492 1493void ARMCodeEmitter::emitVFPLoadStoreInstruction(const MachineInstr &MI) { 1494 // Part of binary is determined by TableGn. 1495 unsigned Binary = getBinaryCodeForInstr(MI); 1496 1497 // Set the conditional execution predicate 1498 Binary |= II->getPredicate(&MI) << ARMII::CondShift; 1499 1500 unsigned OpIdx = 0; 1501 1502 // Encode Dd / Sd. 1503 Binary |= encodeVFPRd(MI, OpIdx++); 1504 1505 // Encode address base. 1506 const MachineOperand &Base = MI.getOperand(OpIdx++); 1507 Binary |= getMachineOpValue(MI, Base) << ARMII::RegRnShift; 1508 1509 // If there is a non-zero immediate offset, encode it. 1510 if (Base.isReg()) { 1511 const MachineOperand &Offset = MI.getOperand(OpIdx); 1512 if (unsigned ImmOffs = ARM_AM::getAM5Offset(Offset.getImm())) { 1513 if (ARM_AM::getAM5Op(Offset.getImm()) == ARM_AM::add) 1514 Binary |= 1 << ARMII::U_BitShift; 1515 Binary |= ImmOffs; 1516 emitWordLE(Binary); 1517 return; 1518 } 1519 } 1520 1521 // If immediate offset is omitted, default to +0. 1522 Binary |= 1 << ARMII::U_BitShift; 1523 1524 emitWordLE(Binary); 1525} 1526 1527void 1528ARMCodeEmitter::emitVFPLoadStoreMultipleInstruction(const MachineInstr &MI) { 1529 const TargetInstrDesc &TID = MI.getDesc(); 1530 bool IsUpdating = (TID.TSFlags & ARMII::IndexModeMask) != 0; 1531 1532 // Part of binary is determined by TableGn. 1533 unsigned Binary = getBinaryCodeForInstr(MI); 1534 1535 // Set the conditional execution predicate 1536 Binary |= II->getPredicate(&MI) << ARMII::CondShift; 1537 1538 // Skip operand 0 of an instruction with base register update. 1539 unsigned OpIdx = 0; 1540 if (IsUpdating) 1541 ++OpIdx; 1542 1543 // Set base address operand 1544 Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRnShift; 1545 1546 // Set addressing mode by modifying bits U(23) and P(24) 1547 const MachineOperand &MO = MI.getOperand(OpIdx++); 1548 Binary |= getAddrModeUPBits(ARM_AM::getAM4SubMode(MO.getImm())); 1549 1550 // Set bit W(21) 1551 if (IsUpdating) 1552 Binary |= 0x1 << ARMII::W_BitShift; 1553 1554 // First register is encoded in Dd. 1555 Binary |= encodeVFPRd(MI, OpIdx+2); 1556 1557 // Count the number of registers. 1558 unsigned NumRegs = 1; 1559 for (unsigned i = OpIdx+3, e = MI.getNumOperands(); i != e; ++i) { 1560 const MachineOperand &MO = MI.getOperand(i); 1561 if (!MO.isReg() || MO.isImplicit()) 1562 break; 1563 ++NumRegs; 1564 } 1565 // Bit 8 will be set if <list> is consecutive 64-bit registers (e.g., D0) 1566 // Otherwise, it will be 0, in the case of 32-bit registers. 1567 if(Binary & 0x100) 1568 Binary |= NumRegs * 2; 1569 else 1570 Binary |= NumRegs; 1571 1572 emitWordLE(Binary); 1573} 1574 1575void ARMCodeEmitter::emitMiscInstruction(const MachineInstr &MI) { 1576 unsigned Opcode = MI.getDesc().Opcode; 1577 // Part of binary is determined by TableGn. 1578 unsigned Binary = getBinaryCodeForInstr(MI); 1579 1580 // Set the conditional execution predicate 1581 Binary |= II->getPredicate(&MI) << ARMII::CondShift; 1582 1583 switch(Opcode) { 1584 default: 1585 llvm_unreachable("ARMCodeEmitter::emitMiscInstruction"); 1586 1587 case ARM::FMSTAT: 1588 // No further encoding needed. 1589 break; 1590 1591 case ARM::VMRS: 1592 case ARM::VMSR: { 1593 const MachineOperand &MO0 = MI.getOperand(0); 1594 // Encode Rt. 1595 Binary |= ARMRegisterInfo::getRegisterNumbering(MO0.getReg()) 1596 << ARMII::RegRdShift; 1597 break; 1598 } 1599 1600 case ARM::FCONSTD: 1601 case ARM::FCONSTS: { 1602 // Encode Dd / Sd. 1603 Binary |= encodeVFPRd(MI, 0); 1604 1605 // Encode imm., Table A7-18 VFP modified immediate constants 1606 const MachineOperand &MO1 = MI.getOperand(1); 1607 unsigned Imm = static_cast<unsigned>(MO1.getFPImm()->getValueAPF() 1608 .bitcastToAPInt().getHiBits(32).getLimitedValue()); 1609 unsigned ModifiedImm; 1610 1611 if(Opcode == ARM::FCONSTS) 1612 ModifiedImm = (Imm & 0x80000000) >> 24 | // a 1613 (Imm & 0x03F80000) >> 19; // bcdefgh 1614 else // Opcode == ARM::FCONSTD 1615 ModifiedImm = (Imm & 0x80000000) >> 24 | // a 1616 (Imm & 0x007F0000) >> 16; // bcdefgh 1617 1618 // Insts{19-16} = abcd, Insts{3-0} = efgh 1619 Binary |= ((ModifiedImm & 0xF0) >> 4) << 16; 1620 Binary |= (ModifiedImm & 0xF); 1621 break; 1622 } 1623 } 1624 1625 emitWordLE(Binary); 1626} 1627 1628static unsigned encodeNEONRd(const MachineInstr &MI, unsigned OpIdx) { 1629 unsigned RegD = MI.getOperand(OpIdx).getReg(); 1630 unsigned Binary = 0; 1631 RegD = ARMRegisterInfo::getRegisterNumbering(RegD); 1632 Binary |= (RegD & 0xf) << ARMII::RegRdShift; 1633 Binary |= ((RegD >> 4) & 1) << ARMII::D_BitShift; 1634 return Binary; 1635} 1636 1637static unsigned encodeNEONRn(const MachineInstr &MI, unsigned OpIdx) { 1638 unsigned RegN = MI.getOperand(OpIdx).getReg(); 1639 unsigned Binary = 0; 1640 RegN = ARMRegisterInfo::getRegisterNumbering(RegN); 1641 Binary |= (RegN & 0xf) << ARMII::RegRnShift; 1642 Binary |= ((RegN >> 4) & 1) << ARMII::N_BitShift; 1643 return Binary; 1644} 1645 1646static unsigned encodeNEONRm(const MachineInstr &MI, unsigned OpIdx) { 1647 unsigned RegM = MI.getOperand(OpIdx).getReg(); 1648 unsigned Binary = 0; 1649 RegM = ARMRegisterInfo::getRegisterNumbering(RegM); 1650 Binary |= (RegM & 0xf); 1651 Binary |= ((RegM >> 4) & 1) << ARMII::M_BitShift; 1652 return Binary; 1653} 1654 1655/// convertNEONDataProcToThumb - Convert the ARM mode encoding for a NEON 1656/// data-processing instruction to the corresponding Thumb encoding. 1657static unsigned convertNEONDataProcToThumb(unsigned Binary) { 1658 assert((Binary & 0xfe000000) == 0xf2000000 && 1659 "not an ARM NEON data-processing instruction"); 1660 unsigned UBit = (Binary >> 24) & 1; 1661 return 0xef000000 | (UBit << 28) | (Binary & 0xffffff); 1662} 1663 1664void ARMCodeEmitter::emitNEONLaneInstruction(const MachineInstr &MI) { 1665 unsigned Binary = getBinaryCodeForInstr(MI); 1666 1667 unsigned RegTOpIdx, RegNOpIdx, LnOpIdx; 1668 const TargetInstrDesc &TID = MI.getDesc(); 1669 if ((TID.TSFlags & ARMII::FormMask) == ARMII::NGetLnFrm) { 1670 RegTOpIdx = 0; 1671 RegNOpIdx = 1; 1672 LnOpIdx = 2; 1673 } else { // ARMII::NSetLnFrm 1674 RegTOpIdx = 2; 1675 RegNOpIdx = 0; 1676 LnOpIdx = 3; 1677 } 1678 1679 // Set the conditional execution predicate 1680 Binary |= (IsThumb ? ARMCC::AL : II->getPredicate(&MI)) << ARMII::CondShift; 1681 1682 unsigned RegT = MI.getOperand(RegTOpIdx).getReg(); 1683 RegT = ARMRegisterInfo::getRegisterNumbering(RegT); 1684 Binary |= (RegT << ARMII::RegRdShift); 1685 Binary |= encodeNEONRn(MI, RegNOpIdx); 1686 1687 unsigned LaneShift; 1688 if ((Binary & (1 << 22)) != 0) 1689 LaneShift = 0; // 8-bit elements 1690 else if ((Binary & (1 << 5)) != 0) 1691 LaneShift = 1; // 16-bit elements 1692 else 1693 LaneShift = 2; // 32-bit elements 1694 1695 unsigned Lane = MI.getOperand(LnOpIdx).getImm() << LaneShift; 1696 unsigned Opc1 = Lane >> 2; 1697 unsigned Opc2 = Lane & 3; 1698 assert((Opc1 & 3) == 0 && "out-of-range lane number operand"); 1699 Binary |= (Opc1 << 21); 1700 Binary |= (Opc2 << 5); 1701 1702 emitWordLE(Binary); 1703} 1704 1705void ARMCodeEmitter::emitNEONDupInstruction(const MachineInstr &MI) { 1706 unsigned Binary = getBinaryCodeForInstr(MI); 1707 1708 // Set the conditional execution predicate 1709 Binary |= (IsThumb ? ARMCC::AL : II->getPredicate(&MI)) << ARMII::CondShift; 1710 1711 unsigned RegT = MI.getOperand(1).getReg(); 1712 RegT = ARMRegisterInfo::getRegisterNumbering(RegT); 1713 Binary |= (RegT << ARMII::RegRdShift); 1714 Binary |= encodeNEONRn(MI, 0); 1715 emitWordLE(Binary); 1716} 1717 1718void ARMCodeEmitter::emitNEON1RegModImmInstruction(const MachineInstr &MI) { 1719 unsigned Binary = getBinaryCodeForInstr(MI); 1720 // Destination register is encoded in Dd. 1721 Binary |= encodeNEONRd(MI, 0); 1722 // Immediate fields: Op, Cmode, I, Imm3, Imm4 1723 unsigned Imm = MI.getOperand(1).getImm(); 1724 unsigned Op = (Imm >> 12) & 1; 1725 unsigned Cmode = (Imm >> 8) & 0xf; 1726 unsigned I = (Imm >> 7) & 1; 1727 unsigned Imm3 = (Imm >> 4) & 0x7; 1728 unsigned Imm4 = Imm & 0xf; 1729 Binary |= (I << 24) | (Imm3 << 16) | (Cmode << 8) | (Op << 5) | Imm4; 1730 if (IsThumb) 1731 Binary = convertNEONDataProcToThumb(Binary); 1732 emitWordLE(Binary); 1733} 1734 1735void ARMCodeEmitter::emitNEON2RegInstruction(const MachineInstr &MI) { 1736 const TargetInstrDesc &TID = MI.getDesc(); 1737 unsigned Binary = getBinaryCodeForInstr(MI); 1738 // Destination register is encoded in Dd; source register in Dm. 1739 unsigned OpIdx = 0; 1740 Binary |= encodeNEONRd(MI, OpIdx++); 1741 if (TID.getOperandConstraint(OpIdx, TOI::TIED_TO) != -1) 1742 ++OpIdx; 1743 Binary |= encodeNEONRm(MI, OpIdx); 1744 if (IsThumb) 1745 Binary = convertNEONDataProcToThumb(Binary); 1746 // FIXME: This does not handle VDUPfdf or VDUPfqf. 1747 emitWordLE(Binary); 1748} 1749 1750void ARMCodeEmitter::emitNEON3RegInstruction(const MachineInstr &MI) { 1751 const TargetInstrDesc &TID = MI.getDesc(); 1752 unsigned Binary = getBinaryCodeForInstr(MI); 1753 // Destination register is encoded in Dd; source registers in Dn and Dm. 1754 unsigned OpIdx = 0; 1755 Binary |= encodeNEONRd(MI, OpIdx++); 1756 if (TID.getOperandConstraint(OpIdx, TOI::TIED_TO) != -1) 1757 ++OpIdx; 1758 Binary |= encodeNEONRn(MI, OpIdx++); 1759 if (TID.getOperandConstraint(OpIdx, TOI::TIED_TO) != -1) 1760 ++OpIdx; 1761 Binary |= encodeNEONRm(MI, OpIdx); 1762 if (IsThumb) 1763 Binary = convertNEONDataProcToThumb(Binary); 1764 // FIXME: This does not handle VMOVDneon or VMOVQ. 1765 emitWordLE(Binary); 1766} 1767 1768#include "ARMGenCodeEmitter.inc" 1769