ARMCodeEmitter.cpp revision 8600421afe774e20c147d9505e3ddc0c1fc04a99 
1//===-- ARM/ARMCodeEmitter.cpp - Convert ARM code to machine code ---------===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file contains the pass that transforms the ARM machine instructions into
11// relocatable machine code.
12//
13//===----------------------------------------------------------------------===//
14
15#define DEBUG_TYPE "jit"
16#include "ARM.h"
17#include "ARMAddressingModes.h"
18#include "ARMConstantPoolValue.h"
19#include "ARMInstrInfo.h"
20#include "ARMRelocations.h"
21#include "ARMSubtarget.h"
22#include "ARMTargetMachine.h"
23#include "llvm/Constants.h"
24#include "llvm/DerivedTypes.h"
25#include "llvm/Function.h"
26#include "llvm/PassManager.h"
27#include "llvm/CodeGen/MachineCodeEmitter.h"
28#include "llvm/CodeGen/MachineConstantPool.h"
29#include "llvm/CodeGen/MachineFunctionPass.h"
30#include "llvm/CodeGen/MachineInstr.h"
31#include "llvm/CodeGen/MachineJumpTableInfo.h"
32#include "llvm/CodeGen/Passes.h"
33#include "llvm/ADT/Statistic.h"
34#include "llvm/Support/Compiler.h"
35#include "llvm/Support/Debug.h"
36#ifndef NDEBUG
37#include <iomanip>
38#endif
39using namespace llvm;
40
41STATISTIC(NumEmitted, "Number of machine instructions emitted");
42
43namespace {
44  class VISIBILITY_HIDDEN ARMCodeEmitter : public MachineFunctionPass {
45    ARMJITInfo                *JTI;
46    const ARMInstrInfo        *II;
47    const TargetData          *TD;
48    TargetMachine             &TM;
49    MachineCodeEmitter        &MCE;
50    const std::vector<MachineConstantPoolEntry> *MCPEs;
51    const std::vector<MachineJumpTableEntry> *MJTEs;
52    bool IsPIC;
53
54  public:
55    static char ID;
56    explicit ARMCodeEmitter(TargetMachine &tm, MachineCodeEmitter &mce)
57      : MachineFunctionPass(&ID), JTI(0), II(0), TD(0), TM(tm),
58      MCE(mce), MCPEs(0), MJTEs(0),
59      IsPIC(TM.getRelocationModel() == Reloc::PIC_) {}
60    ARMCodeEmitter(TargetMachine &tm, MachineCodeEmitter &mce,
61            const ARMInstrInfo &ii, const TargetData &td)
62      : MachineFunctionPass(&ID), JTI(0), II(&ii), TD(&td), TM(tm),
63      MCE(mce), MCPEs(0), MJTEs(0),
64      IsPIC(TM.getRelocationModel() == Reloc::PIC_) {}
65
66    bool runOnMachineFunction(MachineFunction &MF);
67
68    virtual const char *getPassName() const {
69      return "ARM Machine Code Emitter";
70    }
71
72    void emitInstruction(const MachineInstr &MI);
73
74  private:
75
76    void emitWordLE(unsigned Binary);
77
78    void emitConstPoolInstruction(const MachineInstr &MI);
79
80    void emitMOVi2piecesInstruction(const MachineInstr &MI);
81
82    void emitLEApcrelJTInstruction(const MachineInstr &MI);
83
84    void addPCLabel(unsigned LabelID);
85
86    void emitPseudoInstruction(const MachineInstr &MI);
87
88    unsigned getMachineSoRegOpValue(const MachineInstr &MI,
89                                    const TargetInstrDesc &TID,
90                                    const MachineOperand &MO,
91                                    unsigned OpIdx);
92
93    unsigned getMachineSoImmOpValue(unsigned SoImm);
94
95    unsigned getAddrModeSBit(const MachineInstr &MI,
96                             const TargetInstrDesc &TID) const;
97
98    void emitDataProcessingInstruction(const MachineInstr &MI,
99                                       unsigned ImplicitRd = 0,
100                                       unsigned ImplicitRn = 0);
101
102    void emitLoadStoreInstruction(const MachineInstr &MI,
103                                  unsigned ImplicitRd = 0,
104                                  unsigned ImplicitRn = 0);
105
106    void emitMiscLoadStoreInstruction(const MachineInstr &MI,
107                                      unsigned ImplicitRn = 0);
108
109    void emitLoadStoreMultipleInstruction(const MachineInstr &MI);
110
111    void emitMulFrmInstruction(const MachineInstr &MI);
112
113    void emitExtendInstruction(const MachineInstr &MI);
114
115    void emitMiscArithInstruction(const MachineInstr &MI);
116
117    void emitBranchInstruction(const MachineInstr &MI);
118
119    void emitInlineJumpTable(unsigned JTIndex);
120
121    void emitMiscBranchInstruction(const MachineInstr &MI);
122
123    /// getBinaryCodeForInstr - This function, generated by the
124    /// CodeEmitterGenerator using TableGen, produces the binary encoding for
125    /// machine instructions.
126    ///
127    unsigned getBinaryCodeForInstr(const MachineInstr &MI);
128
129    /// getMachineOpValue - Return binary encoding of operand. If the machine
130    /// operand requires relocation, record the relocation and return zero.
131    unsigned getMachineOpValue(const MachineInstr &MI,const MachineOperand &MO);
132    unsigned getMachineOpValue(const MachineInstr &MI, unsigned OpIdx) {
133      return getMachineOpValue(MI, MI.getOperand(OpIdx));
134    }
135
136    /// getShiftOp - Return the shift opcode (bit[6:5]) of the immediate value.
137    ///
138    unsigned getShiftOp(unsigned Imm) const ;
139
140    /// Routines that handle operands which add machine relocations which are
141    /// fixed up by the relocation stage.
142    void emitGlobalAddress(GlobalValue *GV, unsigned Reloc,
143                           bool NeedStub, intptr_t ACPV = 0);
144    void emitExternalSymbolAddress(const char *ES, unsigned Reloc);
145    void emitConstPoolAddress(unsigned CPI, unsigned Reloc);
146    void emitJumpTableAddress(unsigned JTIndex, unsigned Reloc);
147    void emitMachineBasicBlock(MachineBasicBlock *BB, unsigned Reloc,
148                               intptr_t JTBase = 0);
149  };
150  char ARMCodeEmitter::ID = 0;
151}
152
153/// createARMCodeEmitterPass - Return a pass that emits the collected ARM code
154/// to the specified MCE object.
155FunctionPass *llvm::createARMCodeEmitterPass(ARMTargetMachine &TM,
156                                             MachineCodeEmitter &MCE) {
157  return new ARMCodeEmitter(TM, MCE);
158}
159
160bool ARMCodeEmitter::runOnMachineFunction(MachineFunction &MF) {
161  assert((MF.getTarget().getRelocationModel() != Reloc::Default ||
162          MF.getTarget().getRelocationModel() != Reloc::Static) &&
163         "JIT relocation model must be set to static or default!");
164  II = ((ARMTargetMachine&)MF.getTarget()).getInstrInfo();
165  TD = ((ARMTargetMachine&)MF.getTarget()).getTargetData();
166  JTI = ((ARMTargetMachine&)MF.getTarget()).getJITInfo();
167  MCPEs = &MF.getConstantPool()->getConstants();
168  MJTEs = &MF.getJumpTableInfo()->getJumpTables();
169  IsPIC = TM.getRelocationModel() == Reloc::PIC_;
170  JTI->Initialize(MF);
171
172  do {
173    DOUT << "JITTing function '" << MF.getFunction()->getName() << "'\n";
174    MCE.startFunction(MF);
175    for (MachineFunction::iterator MBB = MF.begin(), E = MF.end();
176         MBB != E; ++MBB) {
177      MCE.StartMachineBasicBlock(MBB);
178      for (MachineBasicBlock::const_iterator I = MBB->begin(), E = MBB->end();
179           I != E; ++I)
180        emitInstruction(*I);
181    }
182  } while (MCE.finishFunction(MF));
183
184  return false;
185}
186
187/// getShiftOp - Return the shift opcode (bit[6:5]) of the immediate value.
188///
189unsigned ARMCodeEmitter::getShiftOp(unsigned Imm) const {
190  switch (ARM_AM::getAM2ShiftOpc(Imm)) {
191  default: assert(0 && "Unknown shift opc!");
192  case ARM_AM::asr: return 2;
193  case ARM_AM::lsl: return 0;
194  case ARM_AM::lsr: return 1;
195  case ARM_AM::ror:
196  case ARM_AM::rrx: return 3;
197  }
198  return 0;
199}
200
201/// getMachineOpValue - Return binary encoding of operand. If the machine
202/// operand requires relocation, record the relocation and return zero.
203unsigned ARMCodeEmitter::getMachineOpValue(const MachineInstr &MI,
204                                           const MachineOperand &MO) {
205  if (MO.isReg())
206    return ARMRegisterInfo::getRegisterNumbering(MO.getReg());
207  else if (MO.isImm())
208    return static_cast<unsigned>(MO.getImm());
209  else if (MO.isGlobal())
210    emitGlobalAddress(MO.getGlobal(), ARM::reloc_arm_branch, true);
211  else if (MO.isSymbol())
212    emitExternalSymbolAddress(MO.getSymbolName(), ARM::reloc_arm_relative);
213  else if (MO.isCPI())
214    emitConstPoolAddress(MO.getIndex(), ARM::reloc_arm_cp_entry);
215  else if (MO.isJTI())
216    emitJumpTableAddress(MO.getIndex(), ARM::reloc_arm_relative);
217  else if (MO.isMBB())
218    emitMachineBasicBlock(MO.getMBB(), ARM::reloc_arm_branch);
219  else {
220    cerr << "ERROR: Unknown type of MachineOperand: " << MO << "\n";
221    abort();
222  }
223  return 0;
224}
225
226/// emitGlobalAddress - Emit the specified address to the code stream.
227///
228void ARMCodeEmitter::emitGlobalAddress(GlobalValue *GV, unsigned Reloc,
229                                       bool NeedStub, intptr_t ACPV) {
230  MCE.addRelocation(MachineRelocation::getGV(MCE.getCurrentPCOffset(),
231                                             Reloc, GV, ACPV, NeedStub));
232}
233
234/// emitExternalSymbolAddress - Arrange for the address of an external symbol to
235/// be emitted to the current location in the function, and allow it to be PC
236/// relative.
237void ARMCodeEmitter::emitExternalSymbolAddress(const char *ES, unsigned Reloc) {
238  MCE.addRelocation(MachineRelocation::getExtSym(MCE.getCurrentPCOffset(),
239                                                 Reloc, ES));
240}
241
242/// emitConstPoolAddress - Arrange for the address of an constant pool
243/// to be emitted to the current location in the function, and allow it to be PC
244/// relative.
245void ARMCodeEmitter::emitConstPoolAddress(unsigned CPI, unsigned Reloc) {
246  // Tell JIT emitter we'll resolve the address.
247  MCE.addRelocation(MachineRelocation::getConstPool(MCE.getCurrentPCOffset(),
248                                                    Reloc, CPI, 0, true));
249}
250
251/// emitJumpTableAddress - Arrange for the address of a jump table to
252/// be emitted to the current location in the function, and allow it to be PC
253/// relative.
254void ARMCodeEmitter::emitJumpTableAddress(unsigned JTIndex, unsigned Reloc) {
255  MCE.addRelocation(MachineRelocation::getJumpTable(MCE.getCurrentPCOffset(),
256                                                    Reloc, JTIndex, 0, true));
257}
258
259/// emitMachineBasicBlock - Emit the specified address basic block.
260void ARMCodeEmitter::emitMachineBasicBlock(MachineBasicBlock *BB,
261                                           unsigned Reloc, intptr_t JTBase) {
262  MCE.addRelocation(MachineRelocation::getBB(MCE.getCurrentPCOffset(),
263                                             Reloc, BB, JTBase));
264}
265
266void ARMCodeEmitter::emitWordLE(unsigned Binary) {
267#ifndef NDEBUG
268  DOUT << "  0x" << std::hex << std::setw(8) << std::setfill('0')
269       << Binary << std::dec << "\n";
270#endif
271  MCE.emitWordLE(Binary);
272}
273
274void ARMCodeEmitter::emitInstruction(const MachineInstr &MI) {
275  DOUT << "JIT: " << (void*)MCE.getCurrentPCValue() << ":\t" << MI;
276
277  NumEmitted++;  // Keep track of the # of mi's emitted
278  switch (MI.getDesc().TSFlags & ARMII::FormMask) {
279  default:
280    assert(0 && "Unhandled instruction encoding format!");
281    break;
282  case ARMII::Pseudo:
283    emitPseudoInstruction(MI);
284    break;
285  case ARMII::DPFrm:
286  case ARMII::DPSoRegFrm:
287    emitDataProcessingInstruction(MI);
288    break;
289  case ARMII::LdFrm:
290  case ARMII::StFrm:
291    emitLoadStoreInstruction(MI);
292    break;
293  case ARMII::LdMiscFrm:
294  case ARMII::StMiscFrm:
295    emitMiscLoadStoreInstruction(MI);
296    break;
297  case ARMII::LdMulFrm:
298  case ARMII::StMulFrm:
299    emitLoadStoreMultipleInstruction(MI);
300    break;
301  case ARMII::MulFrm:
302    emitMulFrmInstruction(MI);
303    break;
304  case ARMII::ExtFrm:
305    emitExtendInstruction(MI);
306    break;
307  case ARMII::ArithMiscFrm:
308    emitMiscArithInstruction(MI);
309    break;
310  case ARMII::BrFrm:
311    emitBranchInstruction(MI);
312    break;
313  case ARMII::BrMiscFrm:
314    emitMiscBranchInstruction(MI);
315    break;
316  }
317}
318
319void ARMCodeEmitter::emitConstPoolInstruction(const MachineInstr &MI) {
320  unsigned CPI = MI.getOperand(0).getImm();       // CP instruction index.
321  unsigned CPIndex = MI.getOperand(1).getIndex(); // Actual cp entry index.
322  const MachineConstantPoolEntry &MCPE = (*MCPEs)[CPIndex];
323
324  // Remember the CONSTPOOL_ENTRY address for later relocation.
325  JTI->addConstantPoolEntryAddr(CPI, MCE.getCurrentPCValue());
326
327  // Emit constpool island entry. In most cases, the actual values will be
328  // resolved and relocated after code emission.
329  if (MCPE.isMachineConstantPoolEntry()) {
330    ARMConstantPoolValue *ACPV =
331      static_cast<ARMConstantPoolValue*>(MCPE.Val.MachineCPVal);
332
333    DOUT << "  ** ARM constant pool #" << CPI << " @ "
334         << (void*)MCE.getCurrentPCValue() << " " << *ACPV << '\n';
335
336    GlobalValue *GV = ACPV->getGV();
337    if (GV) {
338      assert(!ACPV->isStub() && "Don't know how to deal this yet!");
339      emitGlobalAddress(GV, ARM::reloc_arm_machine_cp_entry, false,
340                        (intptr_t)ACPV);
341     } else  {
342      assert(!ACPV->isNonLazyPointer() && "Don't know how to deal this yet!");
343      emitExternalSymbolAddress(ACPV->getSymbol(), ARM::reloc_arm_absolute);
344    }
345    emitWordLE(0);
346  } else {
347    Constant *CV = MCPE.Val.ConstVal;
348
349    DOUT << "  ** Constant pool #" << CPI << " @ "
350         << (void*)MCE.getCurrentPCValue() << " " << *CV << '\n';
351
352    if (GlobalValue *GV = dyn_cast<GlobalValue>(CV)) {
353      emitGlobalAddress(GV, ARM::reloc_arm_absolute, false);
354      emitWordLE(0);
355    } else {
356      assert(CV->getType()->isInteger() &&
357             "Not expecting non-integer constpool entries yet!");
358      const ConstantInt *CI = dyn_cast<ConstantInt>(CV);
359      uint32_t Val = *(uint32_t*)CI->getValue().getRawData();
360      emitWordLE(Val);
361    }
362  }
363}
364
365void ARMCodeEmitter::emitMOVi2piecesInstruction(const MachineInstr &MI) {
366  const MachineOperand &MO0 = MI.getOperand(0);
367  const MachineOperand &MO1 = MI.getOperand(1);
368  assert(MO1.isImm() && "Not a valid so_imm value!");
369  unsigned V1 = ARM_AM::getSOImmTwoPartFirst(MO1.getImm());
370  unsigned V2 = ARM_AM::getSOImmTwoPartSecond(MO1.getImm());
371
372  // Emit the 'mov' instruction.
373  unsigned Binary = 0xd << 21;  // mov: Insts{24-21} = 0b1101
374
375  // Set the conditional execution predicate.
376  Binary |= II->getPredicate(&MI) << ARMII::CondShift;
377
378  // Encode Rd.
379  Binary |= getMachineOpValue(MI, MO0) << ARMII::RegRdShift;
380
381  // Encode so_imm.
382  // Set bit I(25) to identify this is the immediate form of <shifter_op>
383  Binary |= 1 << ARMII::I_BitShift;
384  Binary |= getMachineSoImmOpValue(ARM_AM::getSOImmVal(V1));
385  emitWordLE(Binary);
386
387  // Now the 'orr' instruction.
388  Binary = 0xc << 21;  // orr: Insts{24-21} = 0b1100
389
390  // Set the conditional execution predicate.
391  Binary |= II->getPredicate(&MI) << ARMII::CondShift;
392
393  // Encode Rd.
394  Binary |= getMachineOpValue(MI, MO0) << ARMII::RegRdShift;
395
396  // Encode Rn.
397  Binary |= getMachineOpValue(MI, MO0) << ARMII::RegRnShift;
398
399  // Encode so_imm.
400  // Set bit I(25) to identify this is the immediate form of <shifter_op>
401  Binary |= 1 << ARMII::I_BitShift;
402  Binary |= getMachineSoImmOpValue(ARM_AM::getSOImmVal(V2));
403  emitWordLE(Binary);
404}
405
406void ARMCodeEmitter::emitLEApcrelJTInstruction(const MachineInstr &MI) {
407  // It's basically add r, pc, (LJTI - $+8)
408
409  const TargetInstrDesc &TID = MI.getDesc();
410
411  // Emit the 'add' instruction.
412  unsigned Binary = 0x4 << 21;  // add: Insts{24-31} = 0b0100
413
414  // Set the conditional execution predicate
415  Binary |= II->getPredicate(&MI) << ARMII::CondShift;
416
417  // Encode S bit if MI modifies CPSR.
418  Binary |= getAddrModeSBit(MI, TID);
419
420  // Encode Rd.
421  Binary |= getMachineOpValue(MI, 0) << ARMII::RegRdShift;
422
423  // Encode Rn which is PC.
424  Binary |= ARMRegisterInfo::getRegisterNumbering(ARM::PC) << ARMII::RegRnShift;
425
426  // Encode the displacement.
427  // Set bit I(25) to identify this is the immediate form of <shifter_op>.
428  Binary |= 1 << ARMII::I_BitShift;
429  emitJumpTableAddress(MI.getOperand(1).getIndex(), ARM::reloc_arm_jt_base);
430
431  emitWordLE(Binary);
432}
433
434void ARMCodeEmitter::addPCLabel(unsigned LabelID) {
435  DOUT << "  ** LPC" << LabelID << " @ "
436       << (void*)MCE.getCurrentPCValue() << '\n';
437  JTI->addPCLabelAddr(LabelID, MCE.getCurrentPCValue());
438}
439
440void ARMCodeEmitter::emitPseudoInstruction(const MachineInstr &MI) {
441  unsigned Opcode = MI.getDesc().Opcode;
442  switch (Opcode) {
443  default:
444    abort(); // FIXME:
445  case ARM::CONSTPOOL_ENTRY:
446    emitConstPoolInstruction(MI);
447    break;
448  case ARM::PICADD: {
449    // Remember of the address of the PC label for relocation later.
450    addPCLabel(MI.getOperand(2).getImm());
451    // PICADD is just an add instruction that implicitly read pc.
452    emitDataProcessingInstruction(MI, 0, ARM::PC);
453    break;
454  }
455  case ARM::PICLDR:
456  case ARM::PICLDRB:
457  case ARM::PICSTR:
458  case ARM::PICSTRB: {
459    // Remember of the address of the PC label for relocation later.
460    addPCLabel(MI.getOperand(2).getImm());
461    // These are just load / store instructions that implicitly read pc.
462    emitLoadStoreInstruction(MI, 0, ARM::PC);
463    break;
464  }
465  case ARM::PICLDRH:
466  case ARM::PICLDRSH:
467  case ARM::PICLDRSB:
468  case ARM::PICSTRH: {
469    // Remember of the address of the PC label for relocation later.
470    addPCLabel(MI.getOperand(2).getImm());
471    // These are just load / store instructions that implicitly read pc.
472    emitMiscLoadStoreInstruction(MI, ARM::PC);
473    break;
474  }
475  case ARM::MOVi2pieces:
476    // Two instructions to materialize a constant.
477    emitMOVi2piecesInstruction(MI);
478    break;
479  case ARM::LEApcrelJT:
480    // Materialize jumptable address.
481    emitLEApcrelJTInstruction(MI);
482    break;
483  }
484}
485
486
487unsigned ARMCodeEmitter::getMachineSoRegOpValue(const MachineInstr &MI,
488                                                const TargetInstrDesc &TID,
489                                                const MachineOperand &MO,
490                                                unsigned OpIdx) {
491  unsigned Binary = getMachineOpValue(MI, MO);
492
493  const MachineOperand &MO1 = MI.getOperand(OpIdx + 1);
494  const MachineOperand &MO2 = MI.getOperand(OpIdx + 2);
495  ARM_AM::ShiftOpc SOpc = ARM_AM::getSORegShOp(MO2.getImm());
496
497  // Encode the shift opcode.
498  unsigned SBits = 0;
499  unsigned Rs = MO1.getReg();
500  if (Rs) {
501    // Set shift operand (bit[7:4]).
502    // LSL - 0001
503    // LSR - 0011
504    // ASR - 0101
505    // ROR - 0111
506    // RRX - 0110 and bit[11:8] clear.
507    switch (SOpc) {
508    default: assert(0 && "Unknown shift opc!");
509    case ARM_AM::lsl: SBits = 0x1; break;
510    case ARM_AM::lsr: SBits = 0x3; break;
511    case ARM_AM::asr: SBits = 0x5; break;
512    case ARM_AM::ror: SBits = 0x7; break;
513    case ARM_AM::rrx: SBits = 0x6; break;
514    }
515  } else {
516    // Set shift operand (bit[6:4]).
517    // LSL - 000
518    // LSR - 010
519    // ASR - 100
520    // ROR - 110
521    switch (SOpc) {
522    default: assert(0 && "Unknown shift opc!");
523    case ARM_AM::lsl: SBits = 0x0; break;
524    case ARM_AM::lsr: SBits = 0x2; break;
525    case ARM_AM::asr: SBits = 0x4; break;
526    case ARM_AM::ror: SBits = 0x6; break;
527    }
528  }
529  Binary |= SBits << 4;
530  if (SOpc == ARM_AM::rrx)
531    return Binary;
532
533  // Encode the shift operation Rs or shift_imm (except rrx).
534  if (Rs) {
535    // Encode Rs bit[11:8].
536    assert(ARM_AM::getSORegOffset(MO2.getImm()) == 0);
537    return Binary |
538      (ARMRegisterInfo::getRegisterNumbering(Rs) << ARMII::RegRsShift);
539  }
540
541  // Encode shift_imm bit[11:7].
542  return Binary | ARM_AM::getSORegOffset(MO2.getImm()) << 7;
543}
544
545unsigned ARMCodeEmitter::getMachineSoImmOpValue(unsigned SoImm) {
546  // Encode rotate_imm.
547  unsigned Binary = (ARM_AM::getSOImmValRot(SoImm) >> 1)
548    << ARMII::SoRotImmShift;
549
550  // Encode immed_8.
551  Binary |= ARM_AM::getSOImmValImm(SoImm);
552  return Binary;
553}
554
555unsigned ARMCodeEmitter::getAddrModeSBit(const MachineInstr &MI,
556                                         const TargetInstrDesc &TID) const {
557  for (unsigned i = MI.getNumOperands(), e = TID.getNumOperands(); i != e; --i){
558    const MachineOperand &MO = MI.getOperand(i-1);
559    if (MO.isReg() && MO.isDef() && MO.getReg() == ARM::CPSR)
560      return 1 << ARMII::S_BitShift;
561  }
562  return 0;
563}
564
565void ARMCodeEmitter::emitDataProcessingInstruction(const MachineInstr &MI,
566                                                   unsigned ImplicitRd,
567                                                   unsigned ImplicitRn) {
568  const TargetInstrDesc &TID = MI.getDesc();
569
570  // Part of binary is determined by TableGn.
571  unsigned Binary = getBinaryCodeForInstr(MI);
572
573  // Set the conditional execution predicate
574  Binary |= II->getPredicate(&MI) << ARMII::CondShift;
575
576  // Encode S bit if MI modifies CPSR.
577  Binary |= getAddrModeSBit(MI, TID);
578
579  // Encode register def if there is one.
580  unsigned NumDefs = TID.getNumDefs();
581  unsigned OpIdx = 0;
582  if (NumDefs)
583    Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRdShift;
584  else if (ImplicitRd)
585    // Special handling for implicit use (e.g. PC).
586    Binary |= (ARMRegisterInfo::getRegisterNumbering(ImplicitRd)
587               << ARMII::RegRdShift);
588
589  // If this is a two-address operand, skip it. e.g. MOVCCr operand 1.
590  if (TID.getOperandConstraint(OpIdx, TOI::TIED_TO) != -1)
591    ++OpIdx;
592
593  // Encode first non-shifter register operand if there is one.
594  bool isUnary = TID.TSFlags & ARMII::UnaryDP;
595  if (!isUnary) {
596    if (ImplicitRn)
597      // Special handling for implicit use (e.g. PC).
598      Binary |= (ARMRegisterInfo::getRegisterNumbering(ImplicitRn)
599                 << ARMII::RegRnShift);
600    else {
601      Binary |= getMachineOpValue(MI, OpIdx) << ARMII::RegRnShift;
602      ++OpIdx;
603    }
604  }
605
606  // Encode shifter operand.
607  const MachineOperand &MO = MI.getOperand(OpIdx);
608  if ((TID.TSFlags & ARMII::FormMask) == ARMII::DPSoRegFrm) {
609    // Encode SoReg.
610    emitWordLE(Binary | getMachineSoRegOpValue(MI, TID, MO, OpIdx));
611    return;
612  }
613
614  if (MO.isReg()) {
615    // Encode register Rm.
616    emitWordLE(Binary | ARMRegisterInfo::getRegisterNumbering(MO.getReg()));
617    return;
618  }
619
620  // Encode so_imm.
621  // Set bit I(25) to identify this is the immediate form of <shifter_op>.
622  Binary |= 1 << ARMII::I_BitShift;
623  Binary |= getMachineSoImmOpValue(MO.getImm());
624
625  emitWordLE(Binary);
626}
627
628void ARMCodeEmitter::emitLoadStoreInstruction(const MachineInstr &MI,
629                                              unsigned ImplicitRd,
630                                              unsigned ImplicitRn) {
631  // Part of binary is determined by TableGn.
632  unsigned Binary = getBinaryCodeForInstr(MI);
633
634  // Set the conditional execution predicate
635  Binary |= II->getPredicate(&MI) << ARMII::CondShift;
636
637  // Set first operand
638  unsigned OpIdx = 0;
639  if (ImplicitRd)
640    // Special handling for implicit use (e.g. PC).
641    Binary |= (ARMRegisterInfo::getRegisterNumbering(ImplicitRd)
642               << ARMII::RegRdShift);
643  else
644    Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRdShift;
645
646  // Set second operand
647  if (ImplicitRn)
648    // Special handling for implicit use (e.g. PC).
649    Binary |= (ARMRegisterInfo::getRegisterNumbering(ImplicitRn)
650               << ARMII::RegRnShift);
651  else
652    Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRnShift;
653
654  const MachineOperand &MO2 = MI.getOperand(OpIdx);
655  unsigned AM2Opc = (ImplicitRn == ARM::PC)
656    ? 0 : MI.getOperand(OpIdx+1).getImm();
657
658  // Set bit U(23) according to sign of immed value (positive or negative).
659  Binary |= ((ARM_AM::getAM2Op(AM2Opc) == ARM_AM::add ? 1 : 0) <<
660             ARMII::U_BitShift);
661  if (!MO2.getReg()) { // is immediate
662    if (ARM_AM::getAM2Offset(AM2Opc))
663      // Set the value of offset_12 field
664      Binary |= ARM_AM::getAM2Offset(AM2Opc);
665    emitWordLE(Binary);
666    return;
667  }
668
669  // Set bit I(25), because this is not in immediate enconding.
670  Binary |= 1 << ARMII::I_BitShift;
671  assert(TargetRegisterInfo::isPhysicalRegister(MO2.getReg()));
672  // Set bit[3:0] to the corresponding Rm register
673  Binary |= ARMRegisterInfo::getRegisterNumbering(MO2.getReg());
674
675  // if this instr is in scaled register offset/index instruction, set
676  // shift_immed(bit[11:7]) and shift(bit[6:5]) fields.
677  if (unsigned ShImm = ARM_AM::getAM2Offset(AM2Opc)) {
678    Binary |= getShiftOp(AM2Opc) << 5;  // shift
679    Binary |= ShImm              << 7;  // shift_immed
680  }
681
682  emitWordLE(Binary);
683}
684
685void ARMCodeEmitter::emitMiscLoadStoreInstruction(const MachineInstr &MI,
686                                                  unsigned ImplicitRn) {
687  // Part of binary is determined by TableGn.
688  unsigned Binary = getBinaryCodeForInstr(MI);
689
690  // Set the conditional execution predicate
691  Binary |= II->getPredicate(&MI) << ARMII::CondShift;
692
693  // Set first operand
694  Binary |= getMachineOpValue(MI, 0) << ARMII::RegRdShift;
695
696  // Set second operand
697  unsigned OpIdx = 1;
698  if (ImplicitRn)
699    // Special handling for implicit use (e.g. PC).
700    Binary |= (ARMRegisterInfo::getRegisterNumbering(ImplicitRn)
701               << ARMII::RegRnShift);
702  else
703    Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRnShift;
704
705  const MachineOperand &MO2 = MI.getOperand(OpIdx);
706  unsigned AM3Opc = (ImplicitRn == ARM::PC)
707    ? 0 : MI.getOperand(OpIdx+1).getImm();
708
709  // Set bit U(23) according to sign of immed value (positive or negative)
710  Binary |= ((ARM_AM::getAM3Op(AM3Opc) == ARM_AM::add ? 1 : 0) <<
711             ARMII::U_BitShift);
712
713  // If this instr is in register offset/index encoding, set bit[3:0]
714  // to the corresponding Rm register.
715  if (MO2.getReg()) {
716    Binary |= ARMRegisterInfo::getRegisterNumbering(MO2.getReg());
717    emitWordLE(Binary);
718    return;
719  }
720
721  // This instr is in immediate offset/index encoding, set bit 22 to 1.
722  Binary |= 1 << ARMII::AM3_I_BitShift;
723  if (unsigned ImmOffs = ARM_AM::getAM3Offset(AM3Opc)) {
724    // Set operands
725    Binary |= (ImmOffs >> 4) << 8;  // immedH
726    Binary |= (ImmOffs & ~0xF);     // immedL
727  }
728
729  emitWordLE(Binary);
730}
731
732void ARMCodeEmitter::emitLoadStoreMultipleInstruction(const MachineInstr &MI) {
733  // Part of binary is determined by TableGn.
734  unsigned Binary = getBinaryCodeForInstr(MI);
735
736  // Set the conditional execution predicate
737  Binary |= II->getPredicate(&MI) << ARMII::CondShift;
738
739  // Set first operand
740  Binary |= getMachineOpValue(MI, 0) << ARMII::RegRnShift;
741
742  // Set addressing mode by modifying bits U(23) and P(24)
743  // IA - Increment after  - bit U = 1 and bit P = 0
744  // IB - Increment before - bit U = 1 and bit P = 1
745  // DA - Decrement after  - bit U = 0 and bit P = 0
746  // DB - Decrement before - bit U = 0 and bit P = 1
747  const MachineOperand &MO = MI.getOperand(1);
748  ARM_AM::AMSubMode Mode = ARM_AM::getAM4SubMode(MO.getImm());
749  switch (Mode) {
750  default: assert(0 && "Unknown addressing sub-mode!");
751  case ARM_AM::da:                      break;
752  case ARM_AM::db: Binary |= 0x1 << ARMII::P_BitShift; break;
753  case ARM_AM::ia: Binary |= 0x1 << ARMII::U_BitShift; break;
754  case ARM_AM::ib: Binary |= 0x3 << ARMII::U_BitShift; break;
755  }
756
757  // Set bit W(21)
758  if (ARM_AM::getAM4WBFlag(MO.getImm()))
759    Binary |= 0x1 << ARMII::W_BitShift;
760
761  // Set registers
762  for (unsigned i = 4, e = MI.getNumOperands(); i != e; ++i) {
763    const MachineOperand &MO = MI.getOperand(i);
764    if (MO.isReg() && MO.isImplicit())
765      continue;
766    unsigned RegNum = ARMRegisterInfo::getRegisterNumbering(MO.getReg());
767    assert(TargetRegisterInfo::isPhysicalRegister(MO.getReg()) &&
768           RegNum < 16);
769    Binary |= 0x1 << RegNum;
770  }
771
772  emitWordLE(Binary);
773}
774
775void ARMCodeEmitter::emitMulFrmInstruction(const MachineInstr &MI) {
776  const TargetInstrDesc &TID = MI.getDesc();
777
778  // Part of binary is determined by TableGn.
779  unsigned Binary = getBinaryCodeForInstr(MI);
780
781  // Set the conditional execution predicate
782  Binary |= II->getPredicate(&MI) << ARMII::CondShift;
783
784  // Encode S bit if MI modifies CPSR.
785  Binary |= getAddrModeSBit(MI, TID);
786
787  // 32x32->64bit operations have two destination registers. The number
788  // of register definitions will tell us if that's what we're dealing with.
789  unsigned OpIdx = 0;
790  if (TID.getNumDefs() == 2)
791    Binary |= getMachineOpValue (MI, OpIdx++) << ARMII::RegRdLoShift;
792
793  // Encode Rd
794  Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRdHiShift;
795
796  // Encode Rm
797  Binary |= getMachineOpValue(MI, OpIdx++);
798
799  // Encode Rs
800  Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRsShift;
801
802  // Many multiple instructions (e.g. MLA) have three src operands. Encode
803  // it as Rn (for multiply, that's in the same offset as RdLo.
804  if (TID.getNumOperands() > OpIdx &&
805      !TID.OpInfo[OpIdx].isPredicate() &&
806      !TID.OpInfo[OpIdx].isOptionalDef())
807    Binary |= getMachineOpValue(MI, OpIdx) << ARMII::RegRdLoShift;
808
809  emitWordLE(Binary);
810}
811
812void ARMCodeEmitter::emitExtendInstruction(const MachineInstr &MI) {
813  const TargetInstrDesc &TID = MI.getDesc();
814
815  // Part of binary is determined by TableGn.
816  unsigned Binary = getBinaryCodeForInstr(MI);
817
818  // Set the conditional execution predicate
819  Binary |= II->getPredicate(&MI) << ARMII::CondShift;
820
821  unsigned OpIdx = 0;
822
823  // Encode Rd
824  Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRdShift;
825
826  const MachineOperand &MO1 = MI.getOperand(OpIdx++);
827  const MachineOperand &MO2 = MI.getOperand(OpIdx);
828  if (MO2.isReg()) {
829    // Two register operand form.
830    // Encode Rn.
831    Binary |= getMachineOpValue(MI, MO1) << ARMII::RegRnShift;
832
833    // Encode Rm.
834    Binary |= getMachineOpValue(MI, MO2);
835    ++OpIdx;
836  } else {
837    Binary |= getMachineOpValue(MI, MO1);
838  }
839
840  // Encode rot imm (0, 8, 16, or 24) if it has a rotate immediate operand.
841  if (MI.getOperand(OpIdx).isImm() &&
842      !TID.OpInfo[OpIdx].isPredicate() &&
843      !TID.OpInfo[OpIdx].isOptionalDef())
844    Binary |= (getMachineOpValue(MI, OpIdx) / 8) << ARMII::ExtRotImmShift;
845
846  emitWordLE(Binary);
847}
848
849void ARMCodeEmitter::emitMiscArithInstruction(const MachineInstr &MI) {
850  const TargetInstrDesc &TID = MI.getDesc();
851
852  // Part of binary is determined by TableGn.
853  unsigned Binary = getBinaryCodeForInstr(MI);
854
855  // Set the conditional execution predicate
856  Binary |= II->getPredicate(&MI) << ARMII::CondShift;
857
858  unsigned OpIdx = 0;
859
860  // Encode Rd
861  Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRdShift;
862
863  const MachineOperand &MO = MI.getOperand(OpIdx++);
864  if (OpIdx == TID.getNumOperands() ||
865      TID.OpInfo[OpIdx].isPredicate() ||
866      TID.OpInfo[OpIdx].isOptionalDef()) {
867    // Encode Rm and it's done.
868    Binary |= getMachineOpValue(MI, MO);
869    emitWordLE(Binary);
870    return;
871  }
872
873  // Encode Rn.
874  Binary |= getMachineOpValue(MI, MO) << ARMII::RegRnShift;
875
876  // Encode Rm.
877  Binary |= getMachineOpValue(MI, OpIdx++);
878
879  // Encode shift_imm.
880  unsigned ShiftAmt = MI.getOperand(OpIdx).getImm();
881  assert(ShiftAmt < 32 && "shift_imm range is 0 to 31!");
882  Binary |= ShiftAmt << ARMII::ShiftShift;
883
884  emitWordLE(Binary);
885}
886
887void ARMCodeEmitter::emitBranchInstruction(const MachineInstr &MI) {
888  const TargetInstrDesc &TID = MI.getDesc();
889
890  if (TID.Opcode == ARM::TPsoft)
891    abort(); // FIXME
892
893  // Part of binary is determined by TableGn.
894  unsigned Binary = getBinaryCodeForInstr(MI);
895
896  // Set the conditional execution predicate
897  Binary |= II->getPredicate(&MI) << ARMII::CondShift;
898
899  // Set signed_immed_24 field
900  Binary |= getMachineOpValue(MI, 0);
901
902  emitWordLE(Binary);
903}
904
905void ARMCodeEmitter::emitInlineJumpTable(unsigned JTIndex) {
906  // Remember the base address of the inline jump table.
907  intptr_t JTBase = MCE.getCurrentPCValue();
908  JTI->addJumpTableBaseAddr(JTIndex, JTBase);
909  DOUT << "  ** Jump Table #" << JTIndex << " @ " << (void*)JTBase << '\n';
910
911  // Now emit the jump table entries.
912  const std::vector<MachineBasicBlock*> &MBBs = (*MJTEs)[JTIndex].MBBs;
913  for (unsigned i = 0, e = MBBs.size(); i != e; ++i) {
914    if (IsPIC)
915      // DestBB address - JT base.
916      emitMachineBasicBlock(MBBs[i], ARM::reloc_arm_pic_jt, JTBase);
917    else
918      // Absolute DestBB address.
919      emitMachineBasicBlock(MBBs[i], ARM::reloc_arm_absolute);
920    emitWordLE(0);
921  }
922}
923
924void ARMCodeEmitter::emitMiscBranchInstruction(const MachineInstr &MI) {
925  const TargetInstrDesc &TID = MI.getDesc();
926
927  // Handle jump tables.
928  if (TID.Opcode == ARM::BR_JTr || TID.Opcode == ARM::BR_JTadd) {
929    // First emit a ldr pc, [] instruction.
930    emitDataProcessingInstruction(MI, ARM::PC);
931
932    // Then emit the inline jump table.
933    unsigned JTIndex = (TID.Opcode == ARM::BR_JTr)
934      ? MI.getOperand(1).getIndex() : MI.getOperand(2).getIndex();
935    emitInlineJumpTable(JTIndex);
936    return;
937  } else if (TID.Opcode == ARM::BR_JTm) {
938    // First emit a ldr pc, [] instruction.
939    emitLoadStoreInstruction(MI, ARM::PC);
940
941    // Then emit the inline jump table.
942    emitInlineJumpTable(MI.getOperand(3).getIndex());
943    return;
944  }
945
946  // Part of binary is determined by TableGn.
947  unsigned Binary = getBinaryCodeForInstr(MI);
948
949  // Set the conditional execution predicate
950  Binary |= II->getPredicate(&MI) << ARMII::CondShift;
951
952  if (TID.Opcode == ARM::BX_RET)
953    // The return register is LR.
954    Binary |= ARMRegisterInfo::getRegisterNumbering(ARM::LR);
955  else
956    // otherwise, set the return register
957    Binary |= getMachineOpValue(MI, 0);
958
959  emitWordLE(Binary);
960}
961
962#include "ARMGenCodeEmitter.inc"
963