ARMCodeEmitter.cpp revision 893e1c90a03a53cf13f73849324e83612688428a 
1//===-- ARM/ARMCodeEmitter.cpp - Convert ARM code to machine code ---------===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file contains the pass that transforms the ARM machine instructions into
11// relocatable machine code.
12//
13//===----------------------------------------------------------------------===//
14
15#define DEBUG_TYPE "jit"
16#include "ARM.h"
17#include "ARMAddressingModes.h"
18#include "ARMConstantPoolValue.h"
19#include "ARMInstrInfo.h"
20#include "ARMRelocations.h"
21#include "ARMSubtarget.h"
22#include "ARMTargetMachine.h"
23#include "llvm/Constants.h"
24#include "llvm/DerivedTypes.h"
25#include "llvm/Function.h"
26#include "llvm/PassManager.h"
27#include "llvm/CodeGen/MachineCodeEmitter.h"
28#include "llvm/CodeGen/JITCodeEmitter.h"
29#include "llvm/CodeGen/ObjectCodeEmitter.h"
30#include "llvm/CodeGen/MachineConstantPool.h"
31#include "llvm/CodeGen/MachineFunctionPass.h"
32#include "llvm/CodeGen/MachineInstr.h"
33#include "llvm/CodeGen/MachineJumpTableInfo.h"
34#include "llvm/CodeGen/Passes.h"
35#include "llvm/ADT/Statistic.h"
36#include "llvm/Support/Compiler.h"
37#include "llvm/Support/Debug.h"
38#include "llvm/Support/ErrorHandling.h"
39#include "llvm/Support/raw_ostream.h"
40#ifndef NDEBUG
41#include <iomanip>
42#endif
43using namespace llvm;
44
45STATISTIC(NumEmitted, "Number of machine instructions emitted");
46
47namespace {
48
49  class ARMCodeEmitter {
50  public:
51    /// getBinaryCodeForInstr - This function, generated by the
52    /// CodeEmitterGenerator using TableGen, produces the binary encoding for
53    /// machine instructions.
54    unsigned getBinaryCodeForInstr(const MachineInstr &MI);
55  };
56
57  template<class CodeEmitter>
58  class VISIBILITY_HIDDEN Emitter : public MachineFunctionPass,
59                                    public ARMCodeEmitter {
60    ARMJITInfo                *JTI;
61    const ARMInstrInfo        *II;
62    const TargetData          *TD;
63    TargetMachine             &TM;
64    CodeEmitter               &MCE;
65    const std::vector<MachineConstantPoolEntry> *MCPEs;
66    const std::vector<MachineJumpTableEntry> *MJTEs;
67    bool IsPIC;
68
69  public:
70    static char ID;
71    explicit Emitter(TargetMachine &tm, CodeEmitter &mce)
72      : MachineFunctionPass(&ID), JTI(0), II(0), TD(0), TM(tm),
73      MCE(mce), MCPEs(0), MJTEs(0),
74      IsPIC(TM.getRelocationModel() == Reloc::PIC_) {}
75    Emitter(TargetMachine &tm, CodeEmitter &mce,
76            const ARMInstrInfo &ii, const TargetData &td)
77      : MachineFunctionPass(&ID), JTI(0), II(&ii), TD(&td), TM(tm),
78      MCE(mce), MCPEs(0), MJTEs(0),
79      IsPIC(TM.getRelocationModel() == Reloc::PIC_) {}
80
81    bool runOnMachineFunction(MachineFunction &MF);
82
83    virtual const char *getPassName() const {
84      return "ARM Machine Code Emitter";
85    }
86
87    void emitInstruction(const MachineInstr &MI);
88
89  private:
90
91    void emitWordLE(unsigned Binary);
92
93    void emitDWordLE(uint64_t Binary);
94
95    void emitConstPoolInstruction(const MachineInstr &MI);
96
97    void emitMOVi2piecesInstruction(const MachineInstr &MI);
98
99    void emitLEApcrelJTInstruction(const MachineInstr &MI);
100
101    void emitPseudoMoveInstruction(const MachineInstr &MI);
102
103    void addPCLabel(unsigned LabelID);
104
105    void emitPseudoInstruction(const MachineInstr &MI);
106
107    unsigned getMachineSoRegOpValue(const MachineInstr &MI,
108                                    const TargetInstrDesc &TID,
109                                    const MachineOperand &MO,
110                                    unsigned OpIdx);
111
112    unsigned getMachineSoImmOpValue(unsigned SoImm);
113
114    unsigned getAddrModeSBit(const MachineInstr &MI,
115                             const TargetInstrDesc &TID) const;
116
117    void emitDataProcessingInstruction(const MachineInstr &MI,
118                                       unsigned ImplicitRd = 0,
119                                       unsigned ImplicitRn = 0);
120
121    void emitLoadStoreInstruction(const MachineInstr &MI,
122                                  unsigned ImplicitRd = 0,
123                                  unsigned ImplicitRn = 0);
124
125    void emitMiscLoadStoreInstruction(const MachineInstr &MI,
126                                      unsigned ImplicitRn = 0);
127
128    void emitLoadStoreMultipleInstruction(const MachineInstr &MI);
129
130    void emitMulFrmInstruction(const MachineInstr &MI);
131
132    void emitExtendInstruction(const MachineInstr &MI);
133
134    void emitMiscArithInstruction(const MachineInstr &MI);
135
136    void emitBranchInstruction(const MachineInstr &MI);
137
138    void emitInlineJumpTable(unsigned JTIndex);
139
140    void emitMiscBranchInstruction(const MachineInstr &MI);
141
142    void emitVFPArithInstruction(const MachineInstr &MI);
143
144    void emitVFPConversionInstruction(const MachineInstr &MI);
145
146    void emitVFPLoadStoreInstruction(const MachineInstr &MI);
147
148    void emitVFPLoadStoreMultipleInstruction(const MachineInstr &MI);
149
150    void emitMiscInstruction(const MachineInstr &MI);
151
152    /// getMachineOpValue - Return binary encoding of operand. If the machine
153    /// operand requires relocation, record the relocation and return zero.
154    unsigned getMachineOpValue(const MachineInstr &MI,const MachineOperand &MO);
155    unsigned getMachineOpValue(const MachineInstr &MI, unsigned OpIdx) {
156      return getMachineOpValue(MI, MI.getOperand(OpIdx));
157    }
158
159    /// getShiftOp - Return the shift opcode (bit[6:5]) of the immediate value.
160    ///
161    unsigned getShiftOp(unsigned Imm) const ;
162
163    /// Routines that handle operands which add machine relocations which are
164    /// fixed up by the relocation stage.
165    void emitGlobalAddress(GlobalValue *GV, unsigned Reloc,
166                           bool NeedStub, intptr_t ACPV = 0);
167    void emitExternalSymbolAddress(const char *ES, unsigned Reloc);
168    void emitConstPoolAddress(unsigned CPI, unsigned Reloc);
169    void emitJumpTableAddress(unsigned JTIndex, unsigned Reloc);
170    void emitMachineBasicBlock(MachineBasicBlock *BB, unsigned Reloc,
171                               intptr_t JTBase = 0);
172  };
173  template <class CodeEmitter>
174  char Emitter<CodeEmitter>::ID = 0;
175}
176
177/// createARMCodeEmitterPass - Return a pass that emits the collected ARM code
178/// to the specified MCE object.
179
180FunctionPass *llvm::createARMCodeEmitterPass(ARMBaseTargetMachine &TM,
181                                             MachineCodeEmitter &MCE) {
182  return new Emitter<MachineCodeEmitter>(TM, MCE);
183}
184FunctionPass *llvm::createARMJITCodeEmitterPass(ARMBaseTargetMachine &TM,
185                                                JITCodeEmitter &JCE) {
186  return new Emitter<JITCodeEmitter>(TM, JCE);
187}
188FunctionPass *llvm::createARMObjectCodeEmitterPass(ARMBaseTargetMachine &TM,
189                                                   ObjectCodeEmitter &OCE) {
190  return new Emitter<ObjectCodeEmitter>(TM, OCE);
191}
192
193template<class CodeEmitter>
194bool Emitter<CodeEmitter>::runOnMachineFunction(MachineFunction &MF) {
195  assert((MF.getTarget().getRelocationModel() != Reloc::Default ||
196          MF.getTarget().getRelocationModel() != Reloc::Static) &&
197         "JIT relocation model must be set to static or default!");
198  II = ((ARMTargetMachine&)MF.getTarget()).getInstrInfo();
199  TD = ((ARMTargetMachine&)MF.getTarget()).getTargetData();
200  JTI = ((ARMTargetMachine&)MF.getTarget()).getJITInfo();
201  MCPEs = &MF.getConstantPool()->getConstants();
202  MJTEs = &MF.getJumpTableInfo()->getJumpTables();
203  IsPIC = TM.getRelocationModel() == Reloc::PIC_;
204  JTI->Initialize(MF, IsPIC);
205
206  do {
207    DEBUG(errs() << "JITTing function '"
208          << MF.getFunction()->getName() << "'\n");
209    MCE.startFunction(MF);
210    for (MachineFunction::iterator MBB = MF.begin(), E = MF.end();
211         MBB != E; ++MBB) {
212      MCE.StartMachineBasicBlock(MBB);
213      for (MachineBasicBlock::const_iterator I = MBB->begin(), E = MBB->end();
214           I != E; ++I)
215        emitInstruction(*I);
216    }
217  } while (MCE.finishFunction(MF));
218
219  return false;
220}
221
222/// getShiftOp - Return the shift opcode (bit[6:5]) of the immediate value.
223///
224template<class CodeEmitter>
225unsigned Emitter<CodeEmitter>::getShiftOp(unsigned Imm) const {
226  switch (ARM_AM::getAM2ShiftOpc(Imm)) {
227  default: llvm_unreachable("Unknown shift opc!");
228  case ARM_AM::asr: return 2;
229  case ARM_AM::lsl: return 0;
230  case ARM_AM::lsr: return 1;
231  case ARM_AM::ror:
232  case ARM_AM::rrx: return 3;
233  }
234  return 0;
235}
236
237/// getMachineOpValue - Return binary encoding of operand. If the machine
238/// operand requires relocation, record the relocation and return zero.
239template<class CodeEmitter>
240unsigned Emitter<CodeEmitter>::getMachineOpValue(const MachineInstr &MI,
241                                                 const MachineOperand &MO) {
242  if (MO.isReg())
243    return ARMRegisterInfo::getRegisterNumbering(MO.getReg());
244  else if (MO.isImm())
245    return static_cast<unsigned>(MO.getImm());
246  else if (MO.isGlobal())
247    emitGlobalAddress(MO.getGlobal(), ARM::reloc_arm_branch, true);
248  else if (MO.isSymbol())
249    emitExternalSymbolAddress(MO.getSymbolName(), ARM::reloc_arm_branch);
250  else if (MO.isCPI()) {
251    const TargetInstrDesc &TID = MI.getDesc();
252    // For VFP load, the immediate offset is multiplied by 4.
253    unsigned Reloc =  ((TID.TSFlags & ARMII::FormMask) == ARMII::VFPLdStFrm)
254      ? ARM::reloc_arm_vfp_cp_entry : ARM::reloc_arm_cp_entry;
255    emitConstPoolAddress(MO.getIndex(), Reloc);
256  } else if (MO.isJTI())
257    emitJumpTableAddress(MO.getIndex(), ARM::reloc_arm_relative);
258  else if (MO.isMBB())
259    emitMachineBasicBlock(MO.getMBB(), ARM::reloc_arm_branch);
260  else {
261#ifndef NDEBUG
262    errs() << MO;
263#endif
264    llvm_unreachable(0);
265  }
266  return 0;
267}
268
269/// emitGlobalAddress - Emit the specified address to the code stream.
270///
271template<class CodeEmitter>
272void Emitter<CodeEmitter>::emitGlobalAddress(GlobalValue *GV, unsigned Reloc,
273                                             bool NeedStub, intptr_t ACPV) {
274  MCE.addRelocation(MachineRelocation::getGV(MCE.getCurrentPCOffset(), Reloc,
275                                             GV, ACPV, NeedStub));
276}
277
278/// emitExternalSymbolAddress - Arrange for the address of an external symbol to
279/// be emitted to the current location in the function, and allow it to be PC
280/// relative.
281template<class CodeEmitter>
282void Emitter<CodeEmitter>::emitExternalSymbolAddress(const char *ES,
283                                                     unsigned Reloc) {
284  MCE.addRelocation(MachineRelocation::getExtSym(MCE.getCurrentPCOffset(),
285                                                 Reloc, ES));
286}
287
288/// emitConstPoolAddress - Arrange for the address of an constant pool
289/// to be emitted to the current location in the function, and allow it to be PC
290/// relative.
291template<class CodeEmitter>
292void Emitter<CodeEmitter>::emitConstPoolAddress(unsigned CPI,
293                                                unsigned Reloc) {
294  // Tell JIT emitter we'll resolve the address.
295  MCE.addRelocation(MachineRelocation::getConstPool(MCE.getCurrentPCOffset(),
296                                                    Reloc, CPI, 0, true));
297}
298
299/// emitJumpTableAddress - Arrange for the address of a jump table to
300/// be emitted to the current location in the function, and allow it to be PC
301/// relative.
302template<class CodeEmitter>
303void Emitter<CodeEmitter>::emitJumpTableAddress(unsigned JTIndex,
304                                                unsigned Reloc) {
305  MCE.addRelocation(MachineRelocation::getJumpTable(MCE.getCurrentPCOffset(),
306                                                    Reloc, JTIndex, 0, true));
307}
308
309/// emitMachineBasicBlock - Emit the specified address basic block.
310template<class CodeEmitter>
311void Emitter<CodeEmitter>::emitMachineBasicBlock(MachineBasicBlock *BB,
312                                              unsigned Reloc, intptr_t JTBase) {
313  MCE.addRelocation(MachineRelocation::getBB(MCE.getCurrentPCOffset(),
314                                             Reloc, BB, JTBase));
315}
316
317template<class CodeEmitter>
318void Emitter<CodeEmitter>::emitWordLE(unsigned Binary) {
319  DEBUG(errs() << "  0x";
320        errs().write_hex(Binary) << "\n");
321  MCE.emitWordLE(Binary);
322}
323
324template<class CodeEmitter>
325void Emitter<CodeEmitter>::emitDWordLE(uint64_t Binary) {
326  DEBUG(errs() << "  0x";
327        errs().write_hex(Binary) << "\n");
328  MCE.emitDWordLE(Binary);
329}
330
331template<class CodeEmitter>
332void Emitter<CodeEmitter>::emitInstruction(const MachineInstr &MI) {
333  DEBUG(errs() << "JIT: " << (void*)MCE.getCurrentPCValue() << ":\t" << MI);
334
335  MCE.processDebugLoc(MI.getDebugLoc());
336
337  NumEmitted++;  // Keep track of the # of mi's emitted
338  switch (MI.getDesc().TSFlags & ARMII::FormMask) {
339  default: {
340    llvm_unreachable("Unhandled instruction encoding format!");
341    break;
342  }
343  case ARMII::Pseudo:
344    emitPseudoInstruction(MI);
345    break;
346  case ARMII::DPFrm:
347  case ARMII::DPSoRegFrm:
348    emitDataProcessingInstruction(MI);
349    break;
350  case ARMII::LdFrm:
351  case ARMII::StFrm:
352    emitLoadStoreInstruction(MI);
353    break;
354  case ARMII::LdMiscFrm:
355  case ARMII::StMiscFrm:
356    emitMiscLoadStoreInstruction(MI);
357    break;
358  case ARMII::LdStMulFrm:
359    emitLoadStoreMultipleInstruction(MI);
360    break;
361  case ARMII::MulFrm:
362    emitMulFrmInstruction(MI);
363    break;
364  case ARMII::ExtFrm:
365    emitExtendInstruction(MI);
366    break;
367  case ARMII::ArithMiscFrm:
368    emitMiscArithInstruction(MI);
369    break;
370  case ARMII::BrFrm:
371    emitBranchInstruction(MI);
372    break;
373  case ARMII::BrMiscFrm:
374    emitMiscBranchInstruction(MI);
375    break;
376  // VFP instructions.
377  case ARMII::VFPUnaryFrm:
378  case ARMII::VFPBinaryFrm:
379    emitVFPArithInstruction(MI);
380    break;
381  case ARMII::VFPConv1Frm:
382  case ARMII::VFPConv2Frm:
383  case ARMII::VFPConv3Frm:
384  case ARMII::VFPConv4Frm:
385  case ARMII::VFPConv5Frm:
386    emitVFPConversionInstruction(MI);
387    break;
388  case ARMII::VFPLdStFrm:
389    emitVFPLoadStoreInstruction(MI);
390    break;
391  case ARMII::VFPLdStMulFrm:
392    emitVFPLoadStoreMultipleInstruction(MI);
393    break;
394  case ARMII::VFPMiscFrm:
395    emitMiscInstruction(MI);
396    break;
397  }
398}
399
400template<class CodeEmitter>
401void Emitter<CodeEmitter>::emitConstPoolInstruction(const MachineInstr &MI) {
402  unsigned CPI = MI.getOperand(0).getImm();       // CP instruction index.
403  unsigned CPIndex = MI.getOperand(1).getIndex(); // Actual cp entry index.
404  const MachineConstantPoolEntry &MCPE = (*MCPEs)[CPIndex];
405
406  // Remember the CONSTPOOL_ENTRY address for later relocation.
407  JTI->addConstantPoolEntryAddr(CPI, MCE.getCurrentPCValue());
408
409  // Emit constpool island entry. In most cases, the actual values will be
410  // resolved and relocated after code emission.
411  if (MCPE.isMachineConstantPoolEntry()) {
412    ARMConstantPoolValue *ACPV =
413      static_cast<ARMConstantPoolValue*>(MCPE.Val.MachineCPVal);
414
415    DEBUG(errs() << "  ** ARM constant pool #" << CPI << " @ "
416          << (void*)MCE.getCurrentPCValue() << " " << *ACPV << '\n');
417
418    GlobalValue *GV = ACPV->getGV();
419    if (GV) {
420      assert(!ACPV->isStub() && "Don't know how to deal this yet!");
421      if (ACPV->isNonLazyPointer())
422        MCE.addRelocation(MachineRelocation::getIndirectSymbol(
423                  MCE.getCurrentPCOffset(), ARM::reloc_arm_machine_cp_entry, GV,
424                  (intptr_t)ACPV, false));
425      else
426        emitGlobalAddress(GV, ARM::reloc_arm_machine_cp_entry,
427                          ACPV->isStub() || isa<Function>(GV), (intptr_t)ACPV);
428     } else  {
429      assert(!ACPV->isNonLazyPointer() && "Don't know how to deal this yet!");
430      emitExternalSymbolAddress(ACPV->getSymbol(), ARM::reloc_arm_absolute);
431    }
432    emitWordLE(0);
433  } else {
434    Constant *CV = MCPE.Val.ConstVal;
435
436    DEBUG({
437        errs() << "  ** Constant pool #" << CPI << " @ "
438               << (void*)MCE.getCurrentPCValue() << " ";
439        if (const Function *F = dyn_cast<Function>(CV))
440          errs() << F->getName();
441        else
442          errs() << *CV;
443        errs() << '\n';
444      });
445
446    if (GlobalValue *GV = dyn_cast<GlobalValue>(CV)) {
447      emitGlobalAddress(GV, ARM::reloc_arm_absolute, isa<Function>(GV));
448      emitWordLE(0);
449    } else if (const ConstantInt *CI = dyn_cast<ConstantInt>(CV)) {
450      uint32_t Val = *(uint32_t*)CI->getValue().getRawData();
451      emitWordLE(Val);
452    } else if (const ConstantFP *CFP = dyn_cast<ConstantFP>(CV)) {
453      if (CFP->getType() == Type::getFloatTy(CFP->getContext()))
454        emitWordLE(CFP->getValueAPF().bitcastToAPInt().getZExtValue());
455      else if (CFP->getType() == Type::getDoubleTy(CFP->getContext()))
456        emitDWordLE(CFP->getValueAPF().bitcastToAPInt().getZExtValue());
457      else {
458        llvm_unreachable("Unable to handle this constantpool entry!");
459      }
460    } else {
461      llvm_unreachable("Unable to handle this constantpool entry!");
462    }
463  }
464}
465
466template<class CodeEmitter>
467void Emitter<CodeEmitter>::emitMOVi2piecesInstruction(const MachineInstr &MI) {
468  const MachineOperand &MO0 = MI.getOperand(0);
469  const MachineOperand &MO1 = MI.getOperand(1);
470  assert(MO1.isImm() && ARM_AM::getSOImmVal(MO1.isImm()) != -1 &&
471                                            "Not a valid so_imm value!");
472  unsigned V1 = ARM_AM::getSOImmTwoPartFirst(MO1.getImm());
473  unsigned V2 = ARM_AM::getSOImmTwoPartSecond(MO1.getImm());
474
475  // Emit the 'mov' instruction.
476  unsigned Binary = 0xd << 21;  // mov: Insts{24-21} = 0b1101
477
478  // Set the conditional execution predicate.
479  Binary |= II->getPredicate(&MI) << ARMII::CondShift;
480
481  // Encode Rd.
482  Binary |= getMachineOpValue(MI, MO0) << ARMII::RegRdShift;
483
484  // Encode so_imm.
485  // Set bit I(25) to identify this is the immediate form of <shifter_op>
486  Binary |= 1 << ARMII::I_BitShift;
487  Binary |= getMachineSoImmOpValue(V1);
488  emitWordLE(Binary);
489
490  // Now the 'orr' instruction.
491  Binary = 0xc << 21;  // orr: Insts{24-21} = 0b1100
492
493  // Set the conditional execution predicate.
494  Binary |= II->getPredicate(&MI) << ARMII::CondShift;
495
496  // Encode Rd.
497  Binary |= getMachineOpValue(MI, MO0) << ARMII::RegRdShift;
498
499  // Encode Rn.
500  Binary |= getMachineOpValue(MI, MO0) << ARMII::RegRnShift;
501
502  // Encode so_imm.
503  // Set bit I(25) to identify this is the immediate form of <shifter_op>
504  Binary |= 1 << ARMII::I_BitShift;
505  Binary |= getMachineSoImmOpValue(V2);
506  emitWordLE(Binary);
507}
508
509template<class CodeEmitter>
510void Emitter<CodeEmitter>::emitLEApcrelJTInstruction(const MachineInstr &MI) {
511  // It's basically add r, pc, (LJTI - $+8)
512
513  const TargetInstrDesc &TID = MI.getDesc();
514
515  // Emit the 'add' instruction.
516  unsigned Binary = 0x4 << 21;  // add: Insts{24-31} = 0b0100
517
518  // Set the conditional execution predicate
519  Binary |= II->getPredicate(&MI) << ARMII::CondShift;
520
521  // Encode S bit if MI modifies CPSR.
522  Binary |= getAddrModeSBit(MI, TID);
523
524  // Encode Rd.
525  Binary |= getMachineOpValue(MI, 0) << ARMII::RegRdShift;
526
527  // Encode Rn which is PC.
528  Binary |= ARMRegisterInfo::getRegisterNumbering(ARM::PC) << ARMII::RegRnShift;
529
530  // Encode the displacement.
531  Binary |= 1 << ARMII::I_BitShift;
532  emitJumpTableAddress(MI.getOperand(1).getIndex(), ARM::reloc_arm_jt_base);
533
534  emitWordLE(Binary);
535}
536
537template<class CodeEmitter>
538void Emitter<CodeEmitter>::emitPseudoMoveInstruction(const MachineInstr &MI) {
539  unsigned Opcode = MI.getDesc().Opcode;
540
541  // Part of binary is determined by TableGn.
542  unsigned Binary = getBinaryCodeForInstr(MI);
543
544  // Set the conditional execution predicate
545  Binary |= II->getPredicate(&MI) << ARMII::CondShift;
546
547  // Encode S bit if MI modifies CPSR.
548  if (Opcode == ARM::MOVsrl_flag || Opcode == ARM::MOVsra_flag)
549    Binary |= 1 << ARMII::S_BitShift;
550
551  // Encode register def if there is one.
552  Binary |= getMachineOpValue(MI, 0) << ARMII::RegRdShift;
553
554  // Encode the shift operation.
555  switch (Opcode) {
556  default: break;
557  case ARM::MOVrx:
558    // rrx
559    Binary |= 0x6 << 4;
560    break;
561  case ARM::MOVsrl_flag:
562    // lsr #1
563    Binary |= (0x2 << 4) | (1 << 7);
564    break;
565  case ARM::MOVsra_flag:
566    // asr #1
567    Binary |= (0x4 << 4) | (1 << 7);
568    break;
569  }
570
571  // Encode register Rm.
572  Binary |= getMachineOpValue(MI, 1);
573
574  emitWordLE(Binary);
575}
576
577template<class CodeEmitter>
578void Emitter<CodeEmitter>::addPCLabel(unsigned LabelID) {
579  DEBUG(errs() << "  ** LPC" << LabelID << " @ "
580        << (void*)MCE.getCurrentPCValue() << '\n');
581  JTI->addPCLabelAddr(LabelID, MCE.getCurrentPCValue());
582}
583
584template<class CodeEmitter>
585void Emitter<CodeEmitter>::emitPseudoInstruction(const MachineInstr &MI) {
586  unsigned Opcode = MI.getDesc().Opcode;
587  switch (Opcode) {
588  default:
589    llvm_unreachable("ARMCodeEmitter::emitPseudoInstruction");//FIXME:
590  case TargetInstrInfo::INLINEASM: {
591    // We allow inline assembler nodes with empty bodies - they can
592    // implicitly define registers, which is ok for JIT.
593    if (MI.getOperand(0).getSymbolName()[0]) {
594      llvm_report_error("JIT does not support inline asm!");
595    }
596    break;
597  }
598  case TargetInstrInfo::DBG_LABEL:
599  case TargetInstrInfo::EH_LABEL:
600    MCE.emitLabel(MI.getOperand(0).getImm());
601    break;
602  case TargetInstrInfo::IMPLICIT_DEF:
603  case ARM::DWARF_LOC:
604    // Do nothing.
605    break;
606  case ARM::CONSTPOOL_ENTRY:
607    emitConstPoolInstruction(MI);
608    break;
609  case ARM::PICADD: {
610    // Remember of the address of the PC label for relocation later.
611    addPCLabel(MI.getOperand(2).getImm());
612    // PICADD is just an add instruction that implicitly read pc.
613    emitDataProcessingInstruction(MI, 0, ARM::PC);
614    break;
615  }
616  case ARM::PICLDR:
617  case ARM::PICLDRB:
618  case ARM::PICSTR:
619  case ARM::PICSTRB: {
620    // Remember of the address of the PC label for relocation later.
621    addPCLabel(MI.getOperand(2).getImm());
622    // These are just load / store instructions that implicitly read pc.
623    emitLoadStoreInstruction(MI, 0, ARM::PC);
624    break;
625  }
626  case ARM::PICLDRH:
627  case ARM::PICLDRSH:
628  case ARM::PICLDRSB:
629  case ARM::PICSTRH: {
630    // Remember of the address of the PC label for relocation later.
631    addPCLabel(MI.getOperand(2).getImm());
632    // These are just load / store instructions that implicitly read pc.
633    emitMiscLoadStoreInstruction(MI, ARM::PC);
634    break;
635  }
636  case ARM::MOVi2pieces:
637    // Two instructions to materialize a constant.
638    emitMOVi2piecesInstruction(MI);
639    break;
640  case ARM::LEApcrelJT:
641    // Materialize jumptable address.
642    emitLEApcrelJTInstruction(MI);
643    break;
644  case ARM::MOVrx:
645  case ARM::MOVsrl_flag:
646  case ARM::MOVsra_flag:
647    emitPseudoMoveInstruction(MI);
648    break;
649  }
650}
651
652template<class CodeEmitter>
653unsigned Emitter<CodeEmitter>::getMachineSoRegOpValue(
654                                                const MachineInstr &MI,
655                                                const TargetInstrDesc &TID,
656                                                const MachineOperand &MO,
657                                                unsigned OpIdx) {
658  unsigned Binary = getMachineOpValue(MI, MO);
659
660  const MachineOperand &MO1 = MI.getOperand(OpIdx + 1);
661  const MachineOperand &MO2 = MI.getOperand(OpIdx + 2);
662  ARM_AM::ShiftOpc SOpc = ARM_AM::getSORegShOp(MO2.getImm());
663
664  // Encode the shift opcode.
665  unsigned SBits = 0;
666  unsigned Rs = MO1.getReg();
667  if (Rs) {
668    // Set shift operand (bit[7:4]).
669    // LSL - 0001
670    // LSR - 0011
671    // ASR - 0101
672    // ROR - 0111
673    // RRX - 0110 and bit[11:8] clear.
674    switch (SOpc) {
675    default: llvm_unreachable("Unknown shift opc!");
676    case ARM_AM::lsl: SBits = 0x1; break;
677    case ARM_AM::lsr: SBits = 0x3; break;
678    case ARM_AM::asr: SBits = 0x5; break;
679    case ARM_AM::ror: SBits = 0x7; break;
680    case ARM_AM::rrx: SBits = 0x6; break;
681    }
682  } else {
683    // Set shift operand (bit[6:4]).
684    // LSL - 000
685    // LSR - 010
686    // ASR - 100
687    // ROR - 110
688    switch (SOpc) {
689    default: llvm_unreachable("Unknown shift opc!");
690    case ARM_AM::lsl: SBits = 0x0; break;
691    case ARM_AM::lsr: SBits = 0x2; break;
692    case ARM_AM::asr: SBits = 0x4; break;
693    case ARM_AM::ror: SBits = 0x6; break;
694    }
695  }
696  Binary |= SBits << 4;
697  if (SOpc == ARM_AM::rrx)
698    return Binary;
699
700  // Encode the shift operation Rs or shift_imm (except rrx).
701  if (Rs) {
702    // Encode Rs bit[11:8].
703    assert(ARM_AM::getSORegOffset(MO2.getImm()) == 0);
704    return Binary |
705      (ARMRegisterInfo::getRegisterNumbering(Rs) << ARMII::RegRsShift);
706  }
707
708  // Encode shift_imm bit[11:7].
709  return Binary | ARM_AM::getSORegOffset(MO2.getImm()) << 7;
710}
711
712template<class CodeEmitter>
713unsigned Emitter<CodeEmitter>::getMachineSoImmOpValue(unsigned SoImm) {
714  int SoImmVal = ARM_AM::getSOImmVal(SoImm);
715  assert(SoImmVal != -1 && "Not a valid so_imm value!");
716
717  // Encode rotate_imm.
718  unsigned Binary = (ARM_AM::getSOImmValRot((unsigned)SoImmVal) >> 1)
719    << ARMII::SoRotImmShift;
720
721  // Encode immed_8.
722  Binary |= ARM_AM::getSOImmValImm((unsigned)SoImmVal);
723  return Binary;
724}
725
726template<class CodeEmitter>
727unsigned Emitter<CodeEmitter>::getAddrModeSBit(const MachineInstr &MI,
728                                             const TargetInstrDesc &TID) const {
729  for (unsigned i = MI.getNumOperands(), e = TID.getNumOperands(); i != e; --i){
730    const MachineOperand &MO = MI.getOperand(i-1);
731    if (MO.isReg() && MO.isDef() && MO.getReg() == ARM::CPSR)
732      return 1 << ARMII::S_BitShift;
733  }
734  return 0;
735}
736
737template<class CodeEmitter>
738void Emitter<CodeEmitter>::emitDataProcessingInstruction(
739                                                   const MachineInstr &MI,
740                                                   unsigned ImplicitRd,
741                                                   unsigned ImplicitRn) {
742  const TargetInstrDesc &TID = MI.getDesc();
743
744  if (TID.Opcode == ARM::BFC) {
745    llvm_report_error("ARMv6t2 JIT is not yet supported.");
746  }
747
748  // Part of binary is determined by TableGn.
749  unsigned Binary = getBinaryCodeForInstr(MI);
750
751  // Set the conditional execution predicate
752  Binary |= II->getPredicate(&MI) << ARMII::CondShift;
753
754  // Encode S bit if MI modifies CPSR.
755  Binary |= getAddrModeSBit(MI, TID);
756
757  // Encode register def if there is one.
758  unsigned NumDefs = TID.getNumDefs();
759  unsigned OpIdx = 0;
760  if (NumDefs)
761    Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRdShift;
762  else if (ImplicitRd)
763    // Special handling for implicit use (e.g. PC).
764    Binary |= (ARMRegisterInfo::getRegisterNumbering(ImplicitRd)
765               << ARMII::RegRdShift);
766
767  // If this is a two-address operand, skip it. e.g. MOVCCr operand 1.
768  if (TID.getOperandConstraint(OpIdx, TOI::TIED_TO) != -1)
769    ++OpIdx;
770
771  // Encode first non-shifter register operand if there is one.
772  bool isUnary = TID.TSFlags & ARMII::UnaryDP;
773  if (!isUnary) {
774    if (ImplicitRn)
775      // Special handling for implicit use (e.g. PC).
776      Binary |= (ARMRegisterInfo::getRegisterNumbering(ImplicitRn)
777                 << ARMII::RegRnShift);
778    else {
779      Binary |= getMachineOpValue(MI, OpIdx) << ARMII::RegRnShift;
780      ++OpIdx;
781    }
782  }
783
784  // Encode shifter operand.
785  const MachineOperand &MO = MI.getOperand(OpIdx);
786  if ((TID.TSFlags & ARMII::FormMask) == ARMII::DPSoRegFrm) {
787    // Encode SoReg.
788    emitWordLE(Binary | getMachineSoRegOpValue(MI, TID, MO, OpIdx));
789    return;
790  }
791
792  if (MO.isReg()) {
793    // Encode register Rm.
794    emitWordLE(Binary | ARMRegisterInfo::getRegisterNumbering(MO.getReg()));
795    return;
796  }
797
798  // Encode so_imm.
799  Binary |= getMachineSoImmOpValue((unsigned)MO.getImm());
800
801  emitWordLE(Binary);
802}
803
804template<class CodeEmitter>
805void Emitter<CodeEmitter>::emitLoadStoreInstruction(
806                                              const MachineInstr &MI,
807                                              unsigned ImplicitRd,
808                                              unsigned ImplicitRn) {
809  const TargetInstrDesc &TID = MI.getDesc();
810  unsigned Form = TID.TSFlags & ARMII::FormMask;
811  bool IsPrePost = (TID.TSFlags & ARMII::IndexModeMask) != 0;
812
813  // Part of binary is determined by TableGn.
814  unsigned Binary = getBinaryCodeForInstr(MI);
815
816  // Set the conditional execution predicate
817  Binary |= II->getPredicate(&MI) << ARMII::CondShift;
818
819  unsigned OpIdx = 0;
820
821  // Operand 0 of a pre- and post-indexed store is the address base
822  // writeback. Skip it.
823  bool Skipped = false;
824  if (IsPrePost && Form == ARMII::StFrm) {
825    ++OpIdx;
826    Skipped = true;
827  }
828
829  // Set first operand
830  if (ImplicitRd)
831    // Special handling for implicit use (e.g. PC).
832    Binary |= (ARMRegisterInfo::getRegisterNumbering(ImplicitRd)
833               << ARMII::RegRdShift);
834  else
835    Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRdShift;
836
837  // Set second operand
838  if (ImplicitRn)
839    // Special handling for implicit use (e.g. PC).
840    Binary |= (ARMRegisterInfo::getRegisterNumbering(ImplicitRn)
841               << ARMII::RegRnShift);
842  else
843    Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRnShift;
844
845  // If this is a two-address operand, skip it. e.g. LDR_PRE.
846  if (!Skipped && TID.getOperandConstraint(OpIdx, TOI::TIED_TO) != -1)
847    ++OpIdx;
848
849  const MachineOperand &MO2 = MI.getOperand(OpIdx);
850  unsigned AM2Opc = (ImplicitRn == ARM::PC)
851    ? 0 : MI.getOperand(OpIdx+1).getImm();
852
853  // Set bit U(23) according to sign of immed value (positive or negative).
854  Binary |= ((ARM_AM::getAM2Op(AM2Opc) == ARM_AM::add ? 1 : 0) <<
855             ARMII::U_BitShift);
856  if (!MO2.getReg()) { // is immediate
857    if (ARM_AM::getAM2Offset(AM2Opc))
858      // Set the value of offset_12 field
859      Binary |= ARM_AM::getAM2Offset(AM2Opc);
860    emitWordLE(Binary);
861    return;
862  }
863
864  // Set bit I(25), because this is not in immediate enconding.
865  Binary |= 1 << ARMII::I_BitShift;
866  assert(TargetRegisterInfo::isPhysicalRegister(MO2.getReg()));
867  // Set bit[3:0] to the corresponding Rm register
868  Binary |= ARMRegisterInfo::getRegisterNumbering(MO2.getReg());
869
870  // If this instr is in scaled register offset/index instruction, set
871  // shift_immed(bit[11:7]) and shift(bit[6:5]) fields.
872  if (unsigned ShImm = ARM_AM::getAM2Offset(AM2Opc)) {
873    Binary |= getShiftOp(AM2Opc) << ARMII::ShiftImmShift;  // shift
874    Binary |= ShImm              << ARMII::ShiftShift;     // shift_immed
875  }
876
877  emitWordLE(Binary);
878}
879
880template<class CodeEmitter>
881void Emitter<CodeEmitter>::emitMiscLoadStoreInstruction(const MachineInstr &MI,
882                                                        unsigned ImplicitRn) {
883  const TargetInstrDesc &TID = MI.getDesc();
884  unsigned Form = TID.TSFlags & ARMII::FormMask;
885  bool IsPrePost = (TID.TSFlags & ARMII::IndexModeMask) != 0;
886
887  // Part of binary is determined by TableGn.
888  unsigned Binary = getBinaryCodeForInstr(MI);
889
890  // Set the conditional execution predicate
891  Binary |= II->getPredicate(&MI) << ARMII::CondShift;
892
893  unsigned OpIdx = 0;
894
895  // Operand 0 of a pre- and post-indexed store is the address base
896  // writeback. Skip it.
897  bool Skipped = false;
898  if (IsPrePost && Form == ARMII::StMiscFrm) {
899    ++OpIdx;
900    Skipped = true;
901  }
902
903  // Set first operand
904  Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRdShift;
905
906  // Skip LDRD and STRD's second operand.
907  if (TID.Opcode == ARM::LDRD || TID.Opcode == ARM::STRD)
908    ++OpIdx;
909
910  // Set second operand
911  if (ImplicitRn)
912    // Special handling for implicit use (e.g. PC).
913    Binary |= (ARMRegisterInfo::getRegisterNumbering(ImplicitRn)
914               << ARMII::RegRnShift);
915  else
916    Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRnShift;
917
918  // If this is a two-address operand, skip it. e.g. LDRH_POST.
919  if (!Skipped && TID.getOperandConstraint(OpIdx, TOI::TIED_TO) != -1)
920    ++OpIdx;
921
922  const MachineOperand &MO2 = MI.getOperand(OpIdx);
923  unsigned AM3Opc = (ImplicitRn == ARM::PC)
924    ? 0 : MI.getOperand(OpIdx+1).getImm();
925
926  // Set bit U(23) according to sign of immed value (positive or negative)
927  Binary |= ((ARM_AM::getAM3Op(AM3Opc) == ARM_AM::add ? 1 : 0) <<
928             ARMII::U_BitShift);
929
930  // If this instr is in register offset/index encoding, set bit[3:0]
931  // to the corresponding Rm register.
932  if (MO2.getReg()) {
933    Binary |= ARMRegisterInfo::getRegisterNumbering(MO2.getReg());
934    emitWordLE(Binary);
935    return;
936  }
937
938  // This instr is in immediate offset/index encoding, set bit 22 to 1.
939  Binary |= 1 << ARMII::AM3_I_BitShift;
940  if (unsigned ImmOffs = ARM_AM::getAM3Offset(AM3Opc)) {
941    // Set operands
942    Binary |= (ImmOffs >> 4) << ARMII::ImmHiShift;  // immedH
943    Binary |= (ImmOffs & 0xF);                      // immedL
944  }
945
946  emitWordLE(Binary);
947}
948
949static unsigned getAddrModeUPBits(unsigned Mode) {
950  unsigned Binary = 0;
951
952  // Set addressing mode by modifying bits U(23) and P(24)
953  // IA - Increment after  - bit U = 1 and bit P = 0
954  // IB - Increment before - bit U = 1 and bit P = 1
955  // DA - Decrement after  - bit U = 0 and bit P = 0
956  // DB - Decrement before - bit U = 0 and bit P = 1
957  switch (Mode) {
958  default: llvm_unreachable("Unknown addressing sub-mode!");
959  case ARM_AM::da:                      break;
960  case ARM_AM::db: Binary |= 0x1 << ARMII::P_BitShift; break;
961  case ARM_AM::ia: Binary |= 0x1 << ARMII::U_BitShift; break;
962  case ARM_AM::ib: Binary |= 0x3 << ARMII::U_BitShift; break;
963  }
964
965  return Binary;
966}
967
968template<class CodeEmitter>
969void Emitter<CodeEmitter>::emitLoadStoreMultipleInstruction(
970                                                       const MachineInstr &MI) {
971  // Part of binary is determined by TableGn.
972  unsigned Binary = getBinaryCodeForInstr(MI);
973
974  // Set the conditional execution predicate
975  Binary |= II->getPredicate(&MI) << ARMII::CondShift;
976
977  // Set base address operand
978  Binary |= getMachineOpValue(MI, 0) << ARMII::RegRnShift;
979
980  // Set addressing mode by modifying bits U(23) and P(24)
981  const MachineOperand &MO = MI.getOperand(1);
982  Binary |= getAddrModeUPBits(ARM_AM::getAM4SubMode(MO.getImm()));
983
984  // Set bit W(21)
985  if (ARM_AM::getAM4WBFlag(MO.getImm()))
986    Binary |= 0x1 << ARMII::W_BitShift;
987
988  // Set registers
989  for (unsigned i = 4, e = MI.getNumOperands(); i != e; ++i) {
990    const MachineOperand &MO = MI.getOperand(i);
991    if (!MO.isReg() || MO.isImplicit())
992      break;
993    unsigned RegNum = ARMRegisterInfo::getRegisterNumbering(MO.getReg());
994    assert(TargetRegisterInfo::isPhysicalRegister(MO.getReg()) &&
995           RegNum < 16);
996    Binary |= 0x1 << RegNum;
997  }
998
999  emitWordLE(Binary);
1000}
1001
1002template<class CodeEmitter>
1003void Emitter<CodeEmitter>::emitMulFrmInstruction(const MachineInstr &MI) {
1004  const TargetInstrDesc &TID = MI.getDesc();
1005
1006  // Part of binary is determined by TableGn.
1007  unsigned Binary = getBinaryCodeForInstr(MI);
1008
1009  // Set the conditional execution predicate
1010  Binary |= II->getPredicate(&MI) << ARMII::CondShift;
1011
1012  // Encode S bit if MI modifies CPSR.
1013  Binary |= getAddrModeSBit(MI, TID);
1014
1015  // 32x32->64bit operations have two destination registers. The number
1016  // of register definitions will tell us if that's what we're dealing with.
1017  unsigned OpIdx = 0;
1018  if (TID.getNumDefs() == 2)
1019    Binary |= getMachineOpValue (MI, OpIdx++) << ARMII::RegRdLoShift;
1020
1021  // Encode Rd
1022  Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRdHiShift;
1023
1024  // Encode Rm
1025  Binary |= getMachineOpValue(MI, OpIdx++);
1026
1027  // Encode Rs
1028  Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRsShift;
1029
1030  // Many multiple instructions (e.g. MLA) have three src operands. Encode
1031  // it as Rn (for multiply, that's in the same offset as RdLo.
1032  if (TID.getNumOperands() > OpIdx &&
1033      !TID.OpInfo[OpIdx].isPredicate() &&
1034      !TID.OpInfo[OpIdx].isOptionalDef())
1035    Binary |= getMachineOpValue(MI, OpIdx) << ARMII::RegRdLoShift;
1036
1037  emitWordLE(Binary);
1038}
1039
1040template<class CodeEmitter>
1041void Emitter<CodeEmitter>::emitExtendInstruction(const MachineInstr &MI) {
1042  const TargetInstrDesc &TID = MI.getDesc();
1043
1044  // Part of binary is determined by TableGn.
1045  unsigned Binary = getBinaryCodeForInstr(MI);
1046
1047  // Set the conditional execution predicate
1048  Binary |= II->getPredicate(&MI) << ARMII::CondShift;
1049
1050  unsigned OpIdx = 0;
1051
1052  // Encode Rd
1053  Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRdShift;
1054
1055  const MachineOperand &MO1 = MI.getOperand(OpIdx++);
1056  const MachineOperand &MO2 = MI.getOperand(OpIdx);
1057  if (MO2.isReg()) {
1058    // Two register operand form.
1059    // Encode Rn.
1060    Binary |= getMachineOpValue(MI, MO1) << ARMII::RegRnShift;
1061
1062    // Encode Rm.
1063    Binary |= getMachineOpValue(MI, MO2);
1064    ++OpIdx;
1065  } else {
1066    Binary |= getMachineOpValue(MI, MO1);
1067  }
1068
1069  // Encode rot imm (0, 8, 16, or 24) if it has a rotate immediate operand.
1070  if (MI.getOperand(OpIdx).isImm() &&
1071      !TID.OpInfo[OpIdx].isPredicate() &&
1072      !TID.OpInfo[OpIdx].isOptionalDef())
1073    Binary |= (getMachineOpValue(MI, OpIdx) / 8) << ARMII::ExtRotImmShift;
1074
1075  emitWordLE(Binary);
1076}
1077
1078template<class CodeEmitter>
1079void Emitter<CodeEmitter>::emitMiscArithInstruction(const MachineInstr &MI) {
1080  const TargetInstrDesc &TID = MI.getDesc();
1081
1082  // Part of binary is determined by TableGn.
1083  unsigned Binary = getBinaryCodeForInstr(MI);
1084
1085  // Set the conditional execution predicate
1086  Binary |= II->getPredicate(&MI) << ARMII::CondShift;
1087
1088  unsigned OpIdx = 0;
1089
1090  // Encode Rd
1091  Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRdShift;
1092
1093  const MachineOperand &MO = MI.getOperand(OpIdx++);
1094  if (OpIdx == TID.getNumOperands() ||
1095      TID.OpInfo[OpIdx].isPredicate() ||
1096      TID.OpInfo[OpIdx].isOptionalDef()) {
1097    // Encode Rm and it's done.
1098    Binary |= getMachineOpValue(MI, MO);
1099    emitWordLE(Binary);
1100    return;
1101  }
1102
1103  // Encode Rn.
1104  Binary |= getMachineOpValue(MI, MO) << ARMII::RegRnShift;
1105
1106  // Encode Rm.
1107  Binary |= getMachineOpValue(MI, OpIdx++);
1108
1109  // Encode shift_imm.
1110  unsigned ShiftAmt = MI.getOperand(OpIdx).getImm();
1111  assert(ShiftAmt < 32 && "shift_imm range is 0 to 31!");
1112  Binary |= ShiftAmt << ARMII::ShiftShift;
1113
1114  emitWordLE(Binary);
1115}
1116
1117template<class CodeEmitter>
1118void Emitter<CodeEmitter>::emitBranchInstruction(const MachineInstr &MI) {
1119  const TargetInstrDesc &TID = MI.getDesc();
1120
1121  if (TID.Opcode == ARM::TPsoft) {
1122    llvm_unreachable("ARM::TPsoft FIXME"); // FIXME
1123  }
1124
1125  // Part of binary is determined by TableGn.
1126  unsigned Binary = getBinaryCodeForInstr(MI);
1127
1128  // Set the conditional execution predicate
1129  Binary |= II->getPredicate(&MI) << ARMII::CondShift;
1130
1131  // Set signed_immed_24 field
1132  Binary |= getMachineOpValue(MI, 0);
1133
1134  emitWordLE(Binary);
1135}
1136
1137template<class CodeEmitter>
1138void Emitter<CodeEmitter>::emitInlineJumpTable(unsigned JTIndex) {
1139  // Remember the base address of the inline jump table.
1140  uintptr_t JTBase = MCE.getCurrentPCValue();
1141  JTI->addJumpTableBaseAddr(JTIndex, JTBase);
1142  DEBUG(errs() << "  ** Jump Table #" << JTIndex << " @ " << (void*)JTBase
1143               << '\n');
1144
1145  // Now emit the jump table entries.
1146  const std::vector<MachineBasicBlock*> &MBBs = (*MJTEs)[JTIndex].MBBs;
1147  for (unsigned i = 0, e = MBBs.size(); i != e; ++i) {
1148    if (IsPIC)
1149      // DestBB address - JT base.
1150      emitMachineBasicBlock(MBBs[i], ARM::reloc_arm_pic_jt, JTBase);
1151    else
1152      // Absolute DestBB address.
1153      emitMachineBasicBlock(MBBs[i], ARM::reloc_arm_absolute);
1154    emitWordLE(0);
1155  }
1156}
1157
1158template<class CodeEmitter>
1159void Emitter<CodeEmitter>::emitMiscBranchInstruction(const MachineInstr &MI) {
1160  const TargetInstrDesc &TID = MI.getDesc();
1161
1162  // Handle jump tables.
1163  if (TID.Opcode == ARM::BR_JTr || TID.Opcode == ARM::BR_JTadd) {
1164    // First emit a ldr pc, [] instruction.
1165    emitDataProcessingInstruction(MI, ARM::PC);
1166
1167    // Then emit the inline jump table.
1168    unsigned JTIndex =
1169      (TID.Opcode == ARM::BR_JTr)
1170      ? MI.getOperand(1).getIndex() : MI.getOperand(2).getIndex();
1171    emitInlineJumpTable(JTIndex);
1172    return;
1173  } else if (TID.Opcode == ARM::BR_JTm) {
1174    // First emit a ldr pc, [] instruction.
1175    emitLoadStoreInstruction(MI, ARM::PC);
1176
1177    // Then emit the inline jump table.
1178    emitInlineJumpTable(MI.getOperand(3).getIndex());
1179    return;
1180  }
1181
1182  // Part of binary is determined by TableGn.
1183  unsigned Binary = getBinaryCodeForInstr(MI);
1184
1185  // Set the conditional execution predicate
1186  Binary |= II->getPredicate(&MI) << ARMII::CondShift;
1187
1188  if (TID.Opcode == ARM::BX_RET)
1189    // The return register is LR.
1190    Binary |= ARMRegisterInfo::getRegisterNumbering(ARM::LR);
1191  else
1192    // otherwise, set the return register
1193    Binary |= getMachineOpValue(MI, 0);
1194
1195  emitWordLE(Binary);
1196}
1197
1198static unsigned encodeVFPRd(const MachineInstr &MI, unsigned OpIdx) {
1199  unsigned RegD = MI.getOperand(OpIdx).getReg();
1200  unsigned Binary = 0;
1201  bool isSPVFP = false;
1202  RegD = ARMRegisterInfo::getRegisterNumbering(RegD, &isSPVFP);
1203  if (!isSPVFP)
1204    Binary |=   RegD               << ARMII::RegRdShift;
1205  else {
1206    Binary |= ((RegD & 0x1E) >> 1) << ARMII::RegRdShift;
1207    Binary |=  (RegD & 0x01)       << ARMII::D_BitShift;
1208  }
1209  return Binary;
1210}
1211
1212static unsigned encodeVFPRn(const MachineInstr &MI, unsigned OpIdx) {
1213  unsigned RegN = MI.getOperand(OpIdx).getReg();
1214  unsigned Binary = 0;
1215  bool isSPVFP = false;
1216  RegN = ARMRegisterInfo::getRegisterNumbering(RegN, &isSPVFP);
1217  if (!isSPVFP)
1218    Binary |=   RegN               << ARMII::RegRnShift;
1219  else {
1220    Binary |= ((RegN & 0x1E) >> 1) << ARMII::RegRnShift;
1221    Binary |=  (RegN & 0x01)       << ARMII::N_BitShift;
1222  }
1223  return Binary;
1224}
1225
1226static unsigned encodeVFPRm(const MachineInstr &MI, unsigned OpIdx) {
1227  unsigned RegM = MI.getOperand(OpIdx).getReg();
1228  unsigned Binary = 0;
1229  bool isSPVFP = false;
1230  RegM = ARMRegisterInfo::getRegisterNumbering(RegM, &isSPVFP);
1231  if (!isSPVFP)
1232    Binary |=   RegM;
1233  else {
1234    Binary |= ((RegM & 0x1E) >> 1);
1235    Binary |=  (RegM & 0x01)       << ARMII::M_BitShift;
1236  }
1237  return Binary;
1238}
1239
1240template<class CodeEmitter>
1241void Emitter<CodeEmitter>::emitVFPArithInstruction(const MachineInstr &MI) {
1242  const TargetInstrDesc &TID = MI.getDesc();
1243
1244  // Part of binary is determined by TableGn.
1245  unsigned Binary = getBinaryCodeForInstr(MI);
1246
1247  // Set the conditional execution predicate
1248  Binary |= II->getPredicate(&MI) << ARMII::CondShift;
1249
1250  unsigned OpIdx = 0;
1251  assert((Binary & ARMII::D_BitShift) == 0 &&
1252         (Binary & ARMII::N_BitShift) == 0 &&
1253         (Binary & ARMII::M_BitShift) == 0 && "VFP encoding bug!");
1254
1255  // Encode Dd / Sd.
1256  Binary |= encodeVFPRd(MI, OpIdx++);
1257
1258  // If this is a two-address operand, skip it, e.g. FMACD.
1259  if (TID.getOperandConstraint(OpIdx, TOI::TIED_TO) != -1)
1260    ++OpIdx;
1261
1262  // Encode Dn / Sn.
1263  if ((TID.TSFlags & ARMII::FormMask) == ARMII::VFPBinaryFrm)
1264    Binary |= encodeVFPRn(MI, OpIdx++);
1265
1266  if (OpIdx == TID.getNumOperands() ||
1267      TID.OpInfo[OpIdx].isPredicate() ||
1268      TID.OpInfo[OpIdx].isOptionalDef()) {
1269    // FCMPEZD etc. has only one operand.
1270    emitWordLE(Binary);
1271    return;
1272  }
1273
1274  // Encode Dm / Sm.
1275  Binary |= encodeVFPRm(MI, OpIdx);
1276
1277  emitWordLE(Binary);
1278}
1279
1280template<class CodeEmitter>
1281void Emitter<CodeEmitter>::emitVFPConversionInstruction(
1282      const MachineInstr &MI) {
1283  const TargetInstrDesc &TID = MI.getDesc();
1284  unsigned Form = TID.TSFlags & ARMII::FormMask;
1285
1286  // Part of binary is determined by TableGn.
1287  unsigned Binary = getBinaryCodeForInstr(MI);
1288
1289  // Set the conditional execution predicate
1290  Binary |= II->getPredicate(&MI) << ARMII::CondShift;
1291
1292  switch (Form) {
1293  default: break;
1294  case ARMII::VFPConv1Frm:
1295  case ARMII::VFPConv2Frm:
1296  case ARMII::VFPConv3Frm:
1297    // Encode Dd / Sd.
1298    Binary |= encodeVFPRd(MI, 0);
1299    break;
1300  case ARMII::VFPConv4Frm:
1301    // Encode Dn / Sn.
1302    Binary |= encodeVFPRn(MI, 0);
1303    break;
1304  case ARMII::VFPConv5Frm:
1305    // Encode Dm / Sm.
1306    Binary |= encodeVFPRm(MI, 0);
1307    break;
1308  }
1309
1310  switch (Form) {
1311  default: break;
1312  case ARMII::VFPConv1Frm:
1313    // Encode Dm / Sm.
1314    Binary |= encodeVFPRm(MI, 1);
1315    break;
1316  case ARMII::VFPConv2Frm:
1317  case ARMII::VFPConv3Frm:
1318    // Encode Dn / Sn.
1319    Binary |= encodeVFPRn(MI, 1);
1320    break;
1321  case ARMII::VFPConv4Frm:
1322  case ARMII::VFPConv5Frm:
1323    // Encode Dd / Sd.
1324    Binary |= encodeVFPRd(MI, 1);
1325    break;
1326  }
1327
1328  if (Form == ARMII::VFPConv5Frm)
1329    // Encode Dn / Sn.
1330    Binary |= encodeVFPRn(MI, 2);
1331  else if (Form == ARMII::VFPConv3Frm)
1332    // Encode Dm / Sm.
1333    Binary |= encodeVFPRm(MI, 2);
1334
1335  emitWordLE(Binary);
1336}
1337
1338template<class CodeEmitter>
1339void Emitter<CodeEmitter>::emitVFPLoadStoreInstruction(const MachineInstr &MI) {
1340  // Part of binary is determined by TableGn.
1341  unsigned Binary = getBinaryCodeForInstr(MI);
1342
1343  // Set the conditional execution predicate
1344  Binary |= II->getPredicate(&MI) << ARMII::CondShift;
1345
1346  unsigned OpIdx = 0;
1347
1348  // Encode Dd / Sd.
1349  Binary |= encodeVFPRd(MI, OpIdx++);
1350
1351  // Encode address base.
1352  const MachineOperand &Base = MI.getOperand(OpIdx++);
1353  Binary |= getMachineOpValue(MI, Base) << ARMII::RegRnShift;
1354
1355  // If there is a non-zero immediate offset, encode it.
1356  if (Base.isReg()) {
1357    const MachineOperand &Offset = MI.getOperand(OpIdx);
1358    if (unsigned ImmOffs = ARM_AM::getAM5Offset(Offset.getImm())) {
1359      if (ARM_AM::getAM5Op(Offset.getImm()) == ARM_AM::add)
1360        Binary |= 1 << ARMII::U_BitShift;
1361      Binary |= ImmOffs;
1362      emitWordLE(Binary);
1363      return;
1364    }
1365  }
1366
1367  // If immediate offset is omitted, default to +0.
1368  Binary |= 1 << ARMII::U_BitShift;
1369
1370  emitWordLE(Binary);
1371}
1372
1373template<class CodeEmitter>
1374void Emitter<CodeEmitter>::emitVFPLoadStoreMultipleInstruction(
1375                                                       const MachineInstr &MI) {
1376  // Part of binary is determined by TableGn.
1377  unsigned Binary = getBinaryCodeForInstr(MI);
1378
1379  // Set the conditional execution predicate
1380  Binary |= II->getPredicate(&MI) << ARMII::CondShift;
1381
1382  // Set base address operand
1383  Binary |= getMachineOpValue(MI, 0) << ARMII::RegRnShift;
1384
1385  // Set addressing mode by modifying bits U(23) and P(24)
1386  const MachineOperand &MO = MI.getOperand(1);
1387  Binary |= getAddrModeUPBits(ARM_AM::getAM5SubMode(MO.getImm()));
1388
1389  // Set bit W(21)
1390  if (ARM_AM::getAM5WBFlag(MO.getImm()))
1391    Binary |= 0x1 << ARMII::W_BitShift;
1392
1393  // First register is encoded in Dd.
1394  Binary |= encodeVFPRd(MI, 4);
1395
1396  // Number of registers are encoded in offset field.
1397  unsigned NumRegs = 1;
1398  for (unsigned i = 5, e = MI.getNumOperands(); i != e; ++i) {
1399    const MachineOperand &MO = MI.getOperand(i);
1400    if (!MO.isReg() || MO.isImplicit())
1401      break;
1402    ++NumRegs;
1403  }
1404  Binary |= NumRegs * 2;
1405
1406  emitWordLE(Binary);
1407}
1408
1409template<class CodeEmitter>
1410void Emitter<CodeEmitter>::emitMiscInstruction(const MachineInstr &MI) {
1411  // Part of binary is determined by TableGn.
1412  unsigned Binary = getBinaryCodeForInstr(MI);
1413
1414  // Set the conditional execution predicate
1415  Binary |= II->getPredicate(&MI) << ARMII::CondShift;
1416
1417  emitWordLE(Binary);
1418}
1419
1420#include "ARMGenCodeEmitter.inc"
1421