ARMCodeEmitter.cpp revision 8e744e3ebcd112345c2abe72a28d308bf5e55d96 
1//===-- ARM/ARMCodeEmitter.cpp - Convert ARM code to machine code ---------===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file contains the pass that transforms the ARM machine instructions into
11// relocatable machine code.
12//
13//===----------------------------------------------------------------------===//
14
15#define DEBUG_TYPE "jit"
16#include "ARM.h"
17#include "ARMAddressingModes.h"
18#include "ARMConstantPoolValue.h"
19#include "ARMInstrInfo.h"
20#include "ARMRelocations.h"
21#include "ARMSubtarget.h"
22#include "ARMTargetMachine.h"
23#include "llvm/Constants.h"
24#include "llvm/DerivedTypes.h"
25#include "llvm/Function.h"
26#include "llvm/PassManager.h"
27#include "llvm/CodeGen/JITCodeEmitter.h"
28#include "llvm/CodeGen/MachineConstantPool.h"
29#include "llvm/CodeGen/MachineFunctionPass.h"
30#include "llvm/CodeGen/MachineInstr.h"
31#include "llvm/CodeGen/MachineJumpTableInfo.h"
32#include "llvm/CodeGen/MachineModuleInfo.h"
33#include "llvm/CodeGen/Passes.h"
34#include "llvm/ADT/Statistic.h"
35#include "llvm/Support/Debug.h"
36#include "llvm/Support/ErrorHandling.h"
37#include "llvm/Support/raw_ostream.h"
38#ifndef NDEBUG
39#include <iomanip>
40#endif
41using namespace llvm;
42
43STATISTIC(NumEmitted, "Number of machine instructions emitted");
44
45namespace {
46
47  class ARMCodeEmitter : public MachineFunctionPass {
48    ARMJITInfo                *JTI;
49    const ARMInstrInfo        *II;
50    const TargetData          *TD;
51    const ARMSubtarget        *Subtarget;
52    TargetMachine             &TM;
53    JITCodeEmitter            &MCE;
54    MachineModuleInfo *MMI;
55    const std::vector<MachineConstantPoolEntry> *MCPEs;
56    const std::vector<MachineJumpTableEntry> *MJTEs;
57    bool IsPIC;
58    bool IsThumb;
59
60    void getAnalysisUsage(AnalysisUsage &AU) const {
61      AU.addRequired<MachineModuleInfo>();
62      MachineFunctionPass::getAnalysisUsage(AU);
63    }
64
65    static char ID;
66  public:
67    ARMCodeEmitter(TargetMachine &tm, JITCodeEmitter &mce)
68      : MachineFunctionPass(ID), JTI(0),
69        II((const ARMInstrInfo *)tm.getInstrInfo()),
70        TD(tm.getTargetData()), TM(tm),
71        MCE(mce), MCPEs(0), MJTEs(0),
72        IsPIC(TM.getRelocationModel() == Reloc::PIC_), IsThumb(false) {}
73
74    /// getBinaryCodeForInstr - This function, generated by the
75    /// CodeEmitterGenerator using TableGen, produces the binary encoding for
76    /// machine instructions.
77    unsigned getBinaryCodeForInstr(const MachineInstr &MI) const;
78
79    bool runOnMachineFunction(MachineFunction &MF);
80
81    virtual const char *getPassName() const {
82      return "ARM Machine Code Emitter";
83    }
84
85    void emitInstruction(const MachineInstr &MI);
86
87  private:
88
89    void emitWordLE(unsigned Binary);
90    void emitDWordLE(uint64_t Binary);
91    void emitConstPoolInstruction(const MachineInstr &MI);
92    void emitMOVi32immInstruction(const MachineInstr &MI);
93    void emitMOVi2piecesInstruction(const MachineInstr &MI);
94    void emitLEApcrelJTInstruction(const MachineInstr &MI);
95    void emitPseudoMoveInstruction(const MachineInstr &MI);
96    void addPCLabel(unsigned LabelID);
97    void emitPseudoInstruction(const MachineInstr &MI);
98    unsigned getMachineSoRegOpValue(const MachineInstr &MI,
99                                    const TargetInstrDesc &TID,
100                                    const MachineOperand &MO,
101                                    unsigned OpIdx);
102
103    unsigned getMachineSoImmOpValue(unsigned SoImm);
104
105    unsigned getAddrModeSBit(const MachineInstr &MI,
106                             const TargetInstrDesc &TID) const;
107
108    void emitDataProcessingInstruction(const MachineInstr &MI,
109                                       unsigned ImplicitRd = 0,
110                                       unsigned ImplicitRn = 0);
111
112    void emitLoadStoreInstruction(const MachineInstr &MI,
113                                  unsigned ImplicitRd = 0,
114                                  unsigned ImplicitRn = 0);
115
116    void emitMiscLoadStoreInstruction(const MachineInstr &MI,
117                                      unsigned ImplicitRn = 0);
118
119    void emitLoadStoreMultipleInstruction(const MachineInstr &MI);
120
121    void emitMulFrmInstruction(const MachineInstr &MI);
122
123    void emitExtendInstruction(const MachineInstr &MI);
124
125    void emitMiscArithInstruction(const MachineInstr &MI);
126
127    void emitSaturateInstruction(const MachineInstr &MI);
128
129    void emitBranchInstruction(const MachineInstr &MI);
130
131    void emitInlineJumpTable(unsigned JTIndex);
132
133    void emitMiscBranchInstruction(const MachineInstr &MI);
134
135    void emitVFPArithInstruction(const MachineInstr &MI);
136
137    void emitVFPConversionInstruction(const MachineInstr &MI);
138
139    void emitVFPLoadStoreInstruction(const MachineInstr &MI);
140
141    void emitVFPLoadStoreMultipleInstruction(const MachineInstr &MI);
142
143    void emitNEONLaneInstruction(const MachineInstr &MI);
144    void emitNEONDupInstruction(const MachineInstr &MI);
145    void emitNEON1RegModImmInstruction(const MachineInstr &MI);
146    void emitNEON2RegInstruction(const MachineInstr &MI);
147    void emitNEON3RegInstruction(const MachineInstr &MI);
148
149    /// getMachineOpValue - Return binary encoding of operand. If the machine
150    /// operand requires relocation, record the relocation and return zero.
151    unsigned getMachineOpValue(const MachineInstr &MI,
152                               const MachineOperand &MO) const;
153    unsigned getMachineOpValue(const MachineInstr &MI, unsigned OpIdx) const {
154      return getMachineOpValue(MI, MI.getOperand(OpIdx));
155    }
156
157    // FIXME: The legacy JIT ARMCodeEmitter doesn't rely on the the
158    //  TableGen'erated getBinaryCodeForInstr() function to encode any
159    //  operand values, instead querying getMachineOpValue() directly for
160    //  each operand it needs to encode. Thus, any of the new encoder
161    //  helper functions can simply return 0 as the values the return
162    //  are already handled elsewhere. They are placeholders to allow this
163    //  encoder to continue to function until the MC encoder is sufficiently
164    //  far along that this one can be eliminated entirely.
165    unsigned getCCOutOpValue(const MachineInstr &MI, unsigned Op)
166      const { return 0; }
167    unsigned getSOImmOpValue(const MachineInstr &MI, unsigned Op)
168      const { return 0; }
169    unsigned getSORegOpValue(const MachineInstr &MI, unsigned Op)
170      const { return 0; }
171    unsigned getRotImmOpValue(const MachineInstr &MI, unsigned Op)
172      const { return 0; }
173    unsigned getImmMinusOneOpValue(const MachineInstr &MI, unsigned Op)
174      const { return 0; }
175    unsigned getBitfieldInvertedMaskOpValue(const MachineInstr &MI,
176                                            unsigned Op) const { return 0; }
177    unsigned getAddrModeImm12OpValue(const MachineInstr &MI, unsigned Op)
178      const {
179        // {17-13} = reg
180        // {12}    = (U)nsigned (add == '1', sub == '0')
181        // {11-0}  = imm12
182        const MachineOperand &MO  = MI.getOperand(Op);
183        const MachineOperand &MO1 = MI.getOperand(Op + 1);
184        if (!MO.isReg()) {
185          emitConstPoolAddress(MO.getIndex(), ARM::reloc_arm_cp_entry);
186          return 0;
187        }
188        unsigned Reg = getARMRegisterNumbering(MO.getReg());
189        int32_t Imm12 = MO1.getImm();
190        uint32_t Binary;
191        Binary = Imm12 & 0xfff;
192        if (Imm12 >= 0)
193          Binary |= (1 << 12);
194        Binary |= (Reg << 13);
195        return Binary;
196      }
197    unsigned getNEONVcvtImm32OpValue(const MachineInstr &MI, unsigned Op)
198      const { return 0; }
199
200    unsigned getRegisterListOpValue(const MachineInstr &MI, unsigned Op)
201      const { return 0; }
202
203    /// getMovi32Value - Return binary encoding of operand for movw/movt. If the
204    /// machine operand requires relocation, record the relocation and return
205    /// zero.
206    unsigned getMovi32Value(const MachineInstr &MI,const MachineOperand &MO,
207                            unsigned Reloc);
208
209    /// getShiftOp - Return the shift opcode (bit[6:5]) of the immediate value.
210    ///
211    unsigned getShiftOp(unsigned Imm) const ;
212
213    /// Routines that handle operands which add machine relocations which are
214    /// fixed up by the relocation stage.
215    void emitGlobalAddress(const GlobalValue *GV, unsigned Reloc,
216                           bool MayNeedFarStub,  bool Indirect,
217                           intptr_t ACPV = 0) const;
218    void emitExternalSymbolAddress(const char *ES, unsigned Reloc) const;
219    void emitConstPoolAddress(unsigned CPI, unsigned Reloc) const;
220    void emitJumpTableAddress(unsigned JTIndex, unsigned Reloc) const;
221    void emitMachineBasicBlock(MachineBasicBlock *BB, unsigned Reloc,
222                               intptr_t JTBase = 0) const;
223  };
224}
225
226char ARMCodeEmitter::ID = 0;
227
228/// createARMJITCodeEmitterPass - Return a pass that emits the collected ARM
229/// code to the specified MCE object.
230FunctionPass *llvm::createARMJITCodeEmitterPass(ARMBaseTargetMachine &TM,
231                                                JITCodeEmitter &JCE) {
232  return new ARMCodeEmitter(TM, JCE);
233}
234
235bool ARMCodeEmitter::runOnMachineFunction(MachineFunction &MF) {
236  assert((MF.getTarget().getRelocationModel() != Reloc::Default ||
237          MF.getTarget().getRelocationModel() != Reloc::Static) &&
238         "JIT relocation model must be set to static or default!");
239  JTI = ((ARMTargetMachine &)MF.getTarget()).getJITInfo();
240  II = ((const ARMTargetMachine &)MF.getTarget()).getInstrInfo();
241  TD = ((const ARMTargetMachine &)MF.getTarget()).getTargetData();
242  Subtarget = &TM.getSubtarget<ARMSubtarget>();
243  MCPEs = &MF.getConstantPool()->getConstants();
244  MJTEs = 0;
245  if (MF.getJumpTableInfo()) MJTEs = &MF.getJumpTableInfo()->getJumpTables();
246  IsPIC = TM.getRelocationModel() == Reloc::PIC_;
247  IsThumb = MF.getInfo<ARMFunctionInfo>()->isThumbFunction();
248  JTI->Initialize(MF, IsPIC);
249  MMI = &getAnalysis<MachineModuleInfo>();
250  MCE.setModuleInfo(MMI);
251
252  do {
253    DEBUG(errs() << "JITTing function '"
254          << MF.getFunction()->getName() << "'\n");
255    MCE.startFunction(MF);
256    for (MachineFunction::iterator MBB = MF.begin(), E = MF.end();
257         MBB != E; ++MBB) {
258      MCE.StartMachineBasicBlock(MBB);
259      for (MachineBasicBlock::const_iterator I = MBB->begin(), E = MBB->end();
260           I != E; ++I)
261        emitInstruction(*I);
262    }
263  } while (MCE.finishFunction(MF));
264
265  return false;
266}
267
268/// getShiftOp - Return the shift opcode (bit[6:5]) of the immediate value.
269///
270unsigned ARMCodeEmitter::getShiftOp(unsigned Imm) const {
271  switch (ARM_AM::getAM2ShiftOpc(Imm)) {
272  default: llvm_unreachable("Unknown shift opc!");
273  case ARM_AM::asr: return 2;
274  case ARM_AM::lsl: return 0;
275  case ARM_AM::lsr: return 1;
276  case ARM_AM::ror:
277  case ARM_AM::rrx: return 3;
278  }
279  return 0;
280}
281
282/// getMovi32Value - Return binary encoding of operand for movw/movt. If the
283/// machine operand requires relocation, record the relocation and return zero.
284unsigned ARMCodeEmitter::getMovi32Value(const MachineInstr &MI,
285                                        const MachineOperand &MO,
286                                        unsigned Reloc) {
287  assert(((Reloc == ARM::reloc_arm_movt) || (Reloc == ARM::reloc_arm_movw))
288      && "Relocation to this function should be for movt or movw");
289
290  if (MO.isImm())
291    return static_cast<unsigned>(MO.getImm());
292  else if (MO.isGlobal())
293    emitGlobalAddress(MO.getGlobal(), Reloc, true, false);
294  else if (MO.isSymbol())
295    emitExternalSymbolAddress(MO.getSymbolName(), Reloc);
296  else if (MO.isMBB())
297    emitMachineBasicBlock(MO.getMBB(), Reloc);
298  else {
299#ifndef NDEBUG
300    errs() << MO;
301#endif
302    llvm_unreachable("Unsupported operand type for movw/movt");
303  }
304  return 0;
305}
306
307/// getMachineOpValue - Return binary encoding of operand. If the machine
308/// operand requires relocation, record the relocation and return zero.
309unsigned ARMCodeEmitter::getMachineOpValue(const MachineInstr &MI,
310                                           const MachineOperand &MO) const {
311  if (MO.isReg())
312    return getARMRegisterNumbering(MO.getReg());
313  else if (MO.isImm())
314    return static_cast<unsigned>(MO.getImm());
315  else if (MO.isGlobal())
316    emitGlobalAddress(MO.getGlobal(), ARM::reloc_arm_branch, true, false);
317  else if (MO.isSymbol())
318    emitExternalSymbolAddress(MO.getSymbolName(), ARM::reloc_arm_branch);
319  else if (MO.isCPI()) {
320    const TargetInstrDesc &TID = MI.getDesc();
321    // For VFP load, the immediate offset is multiplied by 4.
322    unsigned Reloc =  ((TID.TSFlags & ARMII::FormMask) == ARMII::VFPLdStFrm)
323      ? ARM::reloc_arm_vfp_cp_entry : ARM::reloc_arm_cp_entry;
324    emitConstPoolAddress(MO.getIndex(), Reloc);
325  } else if (MO.isJTI())
326    emitJumpTableAddress(MO.getIndex(), ARM::reloc_arm_relative);
327  else if (MO.isMBB())
328    emitMachineBasicBlock(MO.getMBB(), ARM::reloc_arm_branch);
329  else {
330#ifndef NDEBUG
331    errs() << MO;
332#endif
333    llvm_unreachable(0);
334  }
335  return 0;
336}
337
338/// emitGlobalAddress - Emit the specified address to the code stream.
339///
340void ARMCodeEmitter::emitGlobalAddress(const GlobalValue *GV, unsigned Reloc,
341                                       bool MayNeedFarStub, bool Indirect,
342                                       intptr_t ACPV) const {
343  MachineRelocation MR = Indirect
344    ? MachineRelocation::getIndirectSymbol(MCE.getCurrentPCOffset(), Reloc,
345                                           const_cast<GlobalValue *>(GV),
346                                           ACPV, MayNeedFarStub)
347    : MachineRelocation::getGV(MCE.getCurrentPCOffset(), Reloc,
348                               const_cast<GlobalValue *>(GV), ACPV,
349                               MayNeedFarStub);
350  MCE.addRelocation(MR);
351}
352
353/// emitExternalSymbolAddress - Arrange for the address of an external symbol to
354/// be emitted to the current location in the function, and allow it to be PC
355/// relative.
356void ARMCodeEmitter::
357emitExternalSymbolAddress(const char *ES, unsigned Reloc) const {
358  MCE.addRelocation(MachineRelocation::getExtSym(MCE.getCurrentPCOffset(),
359                                                 Reloc, ES));
360}
361
362/// emitConstPoolAddress - Arrange for the address of an constant pool
363/// to be emitted to the current location in the function, and allow it to be PC
364/// relative.
365void ARMCodeEmitter::emitConstPoolAddress(unsigned CPI, unsigned Reloc) const {
366  // Tell JIT emitter we'll resolve the address.
367  MCE.addRelocation(MachineRelocation::getConstPool(MCE.getCurrentPCOffset(),
368                                                    Reloc, CPI, 0, true));
369}
370
371/// emitJumpTableAddress - Arrange for the address of a jump table to
372/// be emitted to the current location in the function, and allow it to be PC
373/// relative.
374void ARMCodeEmitter::
375emitJumpTableAddress(unsigned JTIndex, unsigned Reloc) const {
376  MCE.addRelocation(MachineRelocation::getJumpTable(MCE.getCurrentPCOffset(),
377                                                    Reloc, JTIndex, 0, true));
378}
379
380/// emitMachineBasicBlock - Emit the specified address basic block.
381void ARMCodeEmitter::emitMachineBasicBlock(MachineBasicBlock *BB,
382                                           unsigned Reloc,
383                                           intptr_t JTBase) const {
384  MCE.addRelocation(MachineRelocation::getBB(MCE.getCurrentPCOffset(),
385                                             Reloc, BB, JTBase));
386}
387
388void ARMCodeEmitter::emitWordLE(unsigned Binary) {
389  DEBUG(errs() << "  0x";
390        errs().write_hex(Binary) << "\n");
391  MCE.emitWordLE(Binary);
392}
393
394void ARMCodeEmitter::emitDWordLE(uint64_t Binary) {
395  DEBUG(errs() << "  0x";
396        errs().write_hex(Binary) << "\n");
397  MCE.emitDWordLE(Binary);
398}
399
400void ARMCodeEmitter::emitInstruction(const MachineInstr &MI) {
401  DEBUG(errs() << "JIT: " << (void*)MCE.getCurrentPCValue() << ":\t" << MI);
402
403  MCE.processDebugLoc(MI.getDebugLoc(), true);
404
405  ++NumEmitted;  // Keep track of the # of mi's emitted
406  switch (MI.getDesc().TSFlags & ARMII::FormMask) {
407  default: {
408    llvm_unreachable("Unhandled instruction encoding format!");
409    break;
410  }
411  case ARMII::Pseudo:
412    emitPseudoInstruction(MI);
413    break;
414  case ARMII::DPFrm:
415  case ARMII::DPSoRegFrm:
416    emitDataProcessingInstruction(MI);
417    break;
418  case ARMII::LdFrm:
419  case ARMII::StFrm:
420    emitLoadStoreInstruction(MI);
421    break;
422  case ARMII::LdMiscFrm:
423  case ARMII::StMiscFrm:
424    emitMiscLoadStoreInstruction(MI);
425    break;
426  case ARMII::LdStMulFrm:
427    emitLoadStoreMultipleInstruction(MI);
428    break;
429  case ARMII::MulFrm:
430    emitMulFrmInstruction(MI);
431    break;
432  case ARMII::ExtFrm:
433    emitExtendInstruction(MI);
434    break;
435  case ARMII::ArithMiscFrm:
436    emitMiscArithInstruction(MI);
437    break;
438  case ARMII::SatFrm:
439    emitSaturateInstruction(MI);
440    break;
441  case ARMII::BrFrm:
442    emitBranchInstruction(MI);
443    break;
444  case ARMII::BrMiscFrm:
445    emitMiscBranchInstruction(MI);
446    break;
447  // VFP instructions.
448  case ARMII::VFPUnaryFrm:
449  case ARMII::VFPBinaryFrm:
450    emitVFPArithInstruction(MI);
451    break;
452  case ARMII::VFPConv1Frm:
453  case ARMII::VFPConv2Frm:
454  case ARMII::VFPConv3Frm:
455  case ARMII::VFPConv4Frm:
456  case ARMII::VFPConv5Frm:
457    emitVFPConversionInstruction(MI);
458    break;
459  case ARMII::VFPLdStFrm:
460    emitVFPLoadStoreInstruction(MI);
461    break;
462  case ARMII::VFPLdStMulFrm:
463    emitVFPLoadStoreMultipleInstruction(MI);
464    break;
465
466  // NEON instructions.
467  case ARMII::NGetLnFrm:
468  case ARMII::NSetLnFrm:
469    emitNEONLaneInstruction(MI);
470    break;
471  case ARMII::NDupFrm:
472    emitNEONDupInstruction(MI);
473    break;
474  case ARMII::N1RegModImmFrm:
475    emitNEON1RegModImmInstruction(MI);
476    break;
477  case ARMII::N2RegFrm:
478    emitNEON2RegInstruction(MI);
479    break;
480  case ARMII::N3RegFrm:
481    emitNEON3RegInstruction(MI);
482    break;
483  }
484  MCE.processDebugLoc(MI.getDebugLoc(), false);
485}
486
487void ARMCodeEmitter::emitConstPoolInstruction(const MachineInstr &MI) {
488  unsigned CPI = MI.getOperand(0).getImm();       // CP instruction index.
489  unsigned CPIndex = MI.getOperand(1).getIndex(); // Actual cp entry index.
490  const MachineConstantPoolEntry &MCPE = (*MCPEs)[CPIndex];
491
492  // Remember the CONSTPOOL_ENTRY address for later relocation.
493  JTI->addConstantPoolEntryAddr(CPI, MCE.getCurrentPCValue());
494
495  // Emit constpool island entry. In most cases, the actual values will be
496  // resolved and relocated after code emission.
497  if (MCPE.isMachineConstantPoolEntry()) {
498    ARMConstantPoolValue *ACPV =
499      static_cast<ARMConstantPoolValue*>(MCPE.Val.MachineCPVal);
500
501    DEBUG(errs() << "  ** ARM constant pool #" << CPI << " @ "
502          << (void*)MCE.getCurrentPCValue() << " " << *ACPV << '\n');
503
504    assert(ACPV->isGlobalValue() && "unsupported constant pool value");
505    const GlobalValue *GV = ACPV->getGV();
506    if (GV) {
507      Reloc::Model RelocM = TM.getRelocationModel();
508      emitGlobalAddress(GV, ARM::reloc_arm_machine_cp_entry,
509                        isa<Function>(GV),
510                        Subtarget->GVIsIndirectSymbol(GV, RelocM),
511                        (intptr_t)ACPV);
512     } else  {
513      emitExternalSymbolAddress(ACPV->getSymbol(), ARM::reloc_arm_absolute);
514    }
515    emitWordLE(0);
516  } else {
517    const Constant *CV = MCPE.Val.ConstVal;
518
519    DEBUG({
520        errs() << "  ** Constant pool #" << CPI << " @ "
521               << (void*)MCE.getCurrentPCValue() << " ";
522        if (const Function *F = dyn_cast<Function>(CV))
523          errs() << F->getName();
524        else
525          errs() << *CV;
526        errs() << '\n';
527      });
528
529    if (const GlobalValue *GV = dyn_cast<GlobalValue>(CV)) {
530      emitGlobalAddress(GV, ARM::reloc_arm_absolute, isa<Function>(GV), false);
531      emitWordLE(0);
532    } else if (const ConstantInt *CI = dyn_cast<ConstantInt>(CV)) {
533      uint32_t Val = uint32_t(*CI->getValue().getRawData());
534      emitWordLE(Val);
535    } else if (const ConstantFP *CFP = dyn_cast<ConstantFP>(CV)) {
536      if (CFP->getType()->isFloatTy())
537        emitWordLE(CFP->getValueAPF().bitcastToAPInt().getZExtValue());
538      else if (CFP->getType()->isDoubleTy())
539        emitDWordLE(CFP->getValueAPF().bitcastToAPInt().getZExtValue());
540      else {
541        llvm_unreachable("Unable to handle this constantpool entry!");
542      }
543    } else {
544      llvm_unreachable("Unable to handle this constantpool entry!");
545    }
546  }
547}
548
549void ARMCodeEmitter::emitMOVi32immInstruction(const MachineInstr &MI) {
550  const MachineOperand &MO0 = MI.getOperand(0);
551  const MachineOperand &MO1 = MI.getOperand(1);
552
553  // Emit the 'movw' instruction.
554  unsigned Binary = 0x30 << 20;  // mov: Insts{27-20} = 0b00110000
555
556  unsigned Lo16 = getMovi32Value(MI, MO1, ARM::reloc_arm_movw) & 0xFFFF;
557
558  // Set the conditional execution predicate.
559  Binary |= II->getPredicate(&MI) << ARMII::CondShift;
560
561  // Encode Rd.
562  Binary |= getMachineOpValue(MI, MO0) << ARMII::RegRdShift;
563
564  // Encode imm16 as imm4:imm12
565  Binary |= Lo16 & 0xFFF; // Insts{11-0} = imm12
566  Binary |= ((Lo16 >> 12) & 0xF) << 16; // Insts{19-16} = imm4
567  emitWordLE(Binary);
568
569  unsigned Hi16 = getMovi32Value(MI, MO1, ARM::reloc_arm_movt) >> 16;
570  // Emit the 'movt' instruction.
571  Binary = 0x34 << 20; // movt: Insts{27-20} = 0b00110100
572
573  // Set the conditional execution predicate.
574  Binary |= II->getPredicate(&MI) << ARMII::CondShift;
575
576  // Encode Rd.
577  Binary |= getMachineOpValue(MI, MO0) << ARMII::RegRdShift;
578
579  // Encode imm16 as imm4:imm1, same as movw above.
580  Binary |= Hi16 & 0xFFF;
581  Binary |= ((Hi16 >> 12) & 0xF) << 16;
582  emitWordLE(Binary);
583}
584
585void ARMCodeEmitter::emitMOVi2piecesInstruction(const MachineInstr &MI) {
586  const MachineOperand &MO0 = MI.getOperand(0);
587  const MachineOperand &MO1 = MI.getOperand(1);
588  assert(MO1.isImm() && ARM_AM::isSOImmTwoPartVal(MO1.getImm()) &&
589                                                  "Not a valid so_imm value!");
590  unsigned V1 = ARM_AM::getSOImmTwoPartFirst(MO1.getImm());
591  unsigned V2 = ARM_AM::getSOImmTwoPartSecond(MO1.getImm());
592
593  // Emit the 'mov' instruction.
594  unsigned Binary = 0xd << 21;  // mov: Insts{24-21} = 0b1101
595
596  // Set the conditional execution predicate.
597  Binary |= II->getPredicate(&MI) << ARMII::CondShift;
598
599  // Encode Rd.
600  Binary |= getMachineOpValue(MI, MO0) << ARMII::RegRdShift;
601
602  // Encode so_imm.
603  // Set bit I(25) to identify this is the immediate form of <shifter_op>
604  Binary |= 1 << ARMII::I_BitShift;
605  Binary |= getMachineSoImmOpValue(V1);
606  emitWordLE(Binary);
607
608  // Now the 'orr' instruction.
609  Binary = 0xc << 21;  // orr: Insts{24-21} = 0b1100
610
611  // Set the conditional execution predicate.
612  Binary |= II->getPredicate(&MI) << ARMII::CondShift;
613
614  // Encode Rd.
615  Binary |= getMachineOpValue(MI, MO0) << ARMII::RegRdShift;
616
617  // Encode Rn.
618  Binary |= getMachineOpValue(MI, MO0) << ARMII::RegRnShift;
619
620  // Encode so_imm.
621  // Set bit I(25) to identify this is the immediate form of <shifter_op>
622  Binary |= 1 << ARMII::I_BitShift;
623  Binary |= getMachineSoImmOpValue(V2);
624  emitWordLE(Binary);
625}
626
627void ARMCodeEmitter::emitLEApcrelJTInstruction(const MachineInstr &MI) {
628  // It's basically add r, pc, (LJTI - $+8)
629
630  const TargetInstrDesc &TID = MI.getDesc();
631
632  // Emit the 'add' instruction.
633  unsigned Binary = 0x4 << 21;  // add: Insts{24-31} = 0b0100
634
635  // Set the conditional execution predicate
636  Binary |= II->getPredicate(&MI) << ARMII::CondShift;
637
638  // Encode S bit if MI modifies CPSR.
639  Binary |= getAddrModeSBit(MI, TID);
640
641  // Encode Rd.
642  Binary |= getMachineOpValue(MI, 0) << ARMII::RegRdShift;
643
644  // Encode Rn which is PC.
645  Binary |= getARMRegisterNumbering(ARM::PC) << ARMII::RegRnShift;
646
647  // Encode the displacement.
648  Binary |= 1 << ARMII::I_BitShift;
649  emitJumpTableAddress(MI.getOperand(1).getIndex(), ARM::reloc_arm_jt_base);
650
651  emitWordLE(Binary);
652}
653
654void ARMCodeEmitter::emitPseudoMoveInstruction(const MachineInstr &MI) {
655  unsigned Opcode = MI.getDesc().Opcode;
656
657  // Part of binary is determined by TableGn.
658  unsigned Binary = getBinaryCodeForInstr(MI);
659
660  // Set the conditional execution predicate
661  Binary |= II->getPredicate(&MI) << ARMII::CondShift;
662
663  // Encode S bit if MI modifies CPSR.
664  if (Opcode == ARM::MOVsrl_flag || Opcode == ARM::MOVsra_flag)
665    Binary |= 1 << ARMII::S_BitShift;
666
667  // Encode register def if there is one.
668  Binary |= getMachineOpValue(MI, 0) << ARMII::RegRdShift;
669
670  // Encode the shift operation.
671  switch (Opcode) {
672  default: break;
673  case ARM::RRX:
674    // rrx
675    Binary |= 0x6 << 4;
676    break;
677  case ARM::MOVsrl_flag:
678    // lsr #1
679    Binary |= (0x2 << 4) | (1 << 7);
680    break;
681  case ARM::MOVsra_flag:
682    // asr #1
683    Binary |= (0x4 << 4) | (1 << 7);
684    break;
685  }
686
687  // Encode register Rm.
688  Binary |= getMachineOpValue(MI, 1);
689
690  emitWordLE(Binary);
691}
692
693void ARMCodeEmitter::addPCLabel(unsigned LabelID) {
694  DEBUG(errs() << "  ** LPC" << LabelID << " @ "
695        << (void*)MCE.getCurrentPCValue() << '\n');
696  JTI->addPCLabelAddr(LabelID, MCE.getCurrentPCValue());
697}
698
699void ARMCodeEmitter::emitPseudoInstruction(const MachineInstr &MI) {
700  unsigned Opcode = MI.getDesc().Opcode;
701  switch (Opcode) {
702  default:
703    llvm_unreachable("ARMCodeEmitter::emitPseudoInstruction");
704  case ARM::BX:
705  case ARM::BMOVPCRX:
706  case ARM::BXr9:
707  case ARM::BMOVPCRXr9: {
708    // First emit mov lr, pc
709    unsigned Binary = 0x01a0e00f;
710    Binary |= II->getPredicate(&MI) << ARMII::CondShift;
711    emitWordLE(Binary);
712
713    // and then emit the branch.
714    emitMiscBranchInstruction(MI);
715    break;
716  }
717  case TargetOpcode::INLINEASM: {
718    // We allow inline assembler nodes with empty bodies - they can
719    // implicitly define registers, which is ok for JIT.
720    if (MI.getOperand(0).getSymbolName()[0]) {
721      report_fatal_error("JIT does not support inline asm!");
722    }
723    break;
724  }
725  case TargetOpcode::PROLOG_LABEL:
726  case TargetOpcode::EH_LABEL:
727    MCE.emitLabel(MI.getOperand(0).getMCSymbol());
728    break;
729  case TargetOpcode::IMPLICIT_DEF:
730  case TargetOpcode::KILL:
731    // Do nothing.
732    break;
733  case ARM::CONSTPOOL_ENTRY:
734    emitConstPoolInstruction(MI);
735    break;
736  case ARM::PICADD: {
737    // Remember of the address of the PC label for relocation later.
738    addPCLabel(MI.getOperand(2).getImm());
739    // PICADD is just an add instruction that implicitly read pc.
740    emitDataProcessingInstruction(MI, 0, ARM::PC);
741    break;
742  }
743  case ARM::PICLDR:
744  case ARM::PICLDRB:
745  case ARM::PICSTR:
746  case ARM::PICSTRB: {
747    // Remember of the address of the PC label for relocation later.
748    addPCLabel(MI.getOperand(2).getImm());
749    // These are just load / store instructions that implicitly read pc.
750    emitLoadStoreInstruction(MI, 0, ARM::PC);
751    break;
752  }
753  case ARM::PICLDRH:
754  case ARM::PICLDRSH:
755  case ARM::PICLDRSB:
756  case ARM::PICSTRH: {
757    // Remember of the address of the PC label for relocation later.
758    addPCLabel(MI.getOperand(2).getImm());
759    // These are just load / store instructions that implicitly read pc.
760    emitMiscLoadStoreInstruction(MI, ARM::PC);
761    break;
762  }
763
764  case ARM::MOVi32imm:
765    emitMOVi32immInstruction(MI);
766    break;
767
768  case ARM::MOVi2pieces:
769    // Two instructions to materialize a constant.
770    emitMOVi2piecesInstruction(MI);
771    break;
772  case ARM::LEApcrelJT:
773    // Materialize jumptable address.
774    emitLEApcrelJTInstruction(MI);
775    break;
776  case ARM::RRX:
777  case ARM::MOVsrl_flag:
778  case ARM::MOVsra_flag:
779    emitPseudoMoveInstruction(MI);
780    break;
781  }
782}
783
784unsigned ARMCodeEmitter::getMachineSoRegOpValue(const MachineInstr &MI,
785                                                const TargetInstrDesc &TID,
786                                                const MachineOperand &MO,
787                                                unsigned OpIdx) {
788  unsigned Binary = getMachineOpValue(MI, MO);
789
790  const MachineOperand &MO1 = MI.getOperand(OpIdx + 1);
791  const MachineOperand &MO2 = MI.getOperand(OpIdx + 2);
792  ARM_AM::ShiftOpc SOpc = ARM_AM::getSORegShOp(MO2.getImm());
793
794  // Encode the shift opcode.
795  unsigned SBits = 0;
796  unsigned Rs = MO1.getReg();
797  if (Rs) {
798    // Set shift operand (bit[7:4]).
799    // LSL - 0001
800    // LSR - 0011
801    // ASR - 0101
802    // ROR - 0111
803    // RRX - 0110 and bit[11:8] clear.
804    switch (SOpc) {
805    default: llvm_unreachable("Unknown shift opc!");
806    case ARM_AM::lsl: SBits = 0x1; break;
807    case ARM_AM::lsr: SBits = 0x3; break;
808    case ARM_AM::asr: SBits = 0x5; break;
809    case ARM_AM::ror: SBits = 0x7; break;
810    case ARM_AM::rrx: SBits = 0x6; break;
811    }
812  } else {
813    // Set shift operand (bit[6:4]).
814    // LSL - 000
815    // LSR - 010
816    // ASR - 100
817    // ROR - 110
818    switch (SOpc) {
819    default: llvm_unreachable("Unknown shift opc!");
820    case ARM_AM::lsl: SBits = 0x0; break;
821    case ARM_AM::lsr: SBits = 0x2; break;
822    case ARM_AM::asr: SBits = 0x4; break;
823    case ARM_AM::ror: SBits = 0x6; break;
824    }
825  }
826  Binary |= SBits << 4;
827  if (SOpc == ARM_AM::rrx)
828    return Binary;
829
830  // Encode the shift operation Rs or shift_imm (except rrx).
831  if (Rs) {
832    // Encode Rs bit[11:8].
833    assert(ARM_AM::getSORegOffset(MO2.getImm()) == 0);
834    return Binary | (getARMRegisterNumbering(Rs) << ARMII::RegRsShift);
835  }
836
837  // Encode shift_imm bit[11:7].
838  return Binary | ARM_AM::getSORegOffset(MO2.getImm()) << 7;
839}
840
841unsigned ARMCodeEmitter::getMachineSoImmOpValue(unsigned SoImm) {
842  int SoImmVal = ARM_AM::getSOImmVal(SoImm);
843  assert(SoImmVal != -1 && "Not a valid so_imm value!");
844
845  // Encode rotate_imm.
846  unsigned Binary = (ARM_AM::getSOImmValRot((unsigned)SoImmVal) >> 1)
847    << ARMII::SoRotImmShift;
848
849  // Encode immed_8.
850  Binary |= ARM_AM::getSOImmValImm((unsigned)SoImmVal);
851  return Binary;
852}
853
854unsigned ARMCodeEmitter::getAddrModeSBit(const MachineInstr &MI,
855                                         const TargetInstrDesc &TID) const {
856  for (unsigned i = MI.getNumOperands(), e = TID.getNumOperands(); i != e; --i){
857    const MachineOperand &MO = MI.getOperand(i-1);
858    if (MO.isReg() && MO.isDef() && MO.getReg() == ARM::CPSR)
859      return 1 << ARMII::S_BitShift;
860  }
861  return 0;
862}
863
864void ARMCodeEmitter::emitDataProcessingInstruction(const MachineInstr &MI,
865                                                   unsigned ImplicitRd,
866                                                   unsigned ImplicitRn) {
867  const TargetInstrDesc &TID = MI.getDesc();
868
869  // Part of binary is determined by TableGn.
870  unsigned Binary = getBinaryCodeForInstr(MI);
871
872  // Set the conditional execution predicate
873  Binary |= II->getPredicate(&MI) << ARMII::CondShift;
874
875  // Encode S bit if MI modifies CPSR.
876  Binary |= getAddrModeSBit(MI, TID);
877
878  // Encode register def if there is one.
879  unsigned NumDefs = TID.getNumDefs();
880  unsigned OpIdx = 0;
881  if (NumDefs)
882    Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRdShift;
883  else if (ImplicitRd)
884    // Special handling for implicit use (e.g. PC).
885    Binary |= (getARMRegisterNumbering(ImplicitRd) << ARMII::RegRdShift);
886
887  if (TID.Opcode == ARM::MOVi16) {
888      // Get immediate from MI.
889      unsigned Lo16 = getMovi32Value(MI, MI.getOperand(OpIdx),
890                      ARM::reloc_arm_movw);
891      // Encode imm which is the same as in emitMOVi32immInstruction().
892      Binary |= Lo16 & 0xFFF;
893      Binary |= ((Lo16 >> 12) & 0xF) << 16;
894      emitWordLE(Binary);
895      return;
896  } else if(TID.Opcode == ARM::MOVTi16) {
897      unsigned Hi16 = (getMovi32Value(MI, MI.getOperand(OpIdx),
898                       ARM::reloc_arm_movt) >> 16);
899      Binary |= Hi16 & 0xFFF;
900      Binary |= ((Hi16 >> 12) & 0xF) << 16;
901      emitWordLE(Binary);
902      return;
903  } else if ((TID.Opcode == ARM::BFC) || (TID.Opcode == ARM::BFI)) {
904      uint32_t v = ~MI.getOperand(2).getImm();
905      int32_t lsb = CountTrailingZeros_32(v);
906      int32_t msb = (32 - CountLeadingZeros_32(v)) - 1;
907      // Instr{20-16} = msb, Instr{11-7} = lsb
908      Binary |= (msb & 0x1F) << 16;
909      Binary |= (lsb & 0x1F) << 7;
910      emitWordLE(Binary);
911      return;
912  } else if ((TID.Opcode == ARM::UBFX) || (TID.Opcode == ARM::SBFX)) {
913      // Encode Rn in Instr{0-3}
914      Binary |= getMachineOpValue(MI, OpIdx++);
915
916      uint32_t lsb = MI.getOperand(OpIdx++).getImm();
917      uint32_t widthm1 = MI.getOperand(OpIdx++).getImm() - 1;
918
919      // Instr{20-16} = widthm1, Instr{11-7} = lsb
920      Binary |= (widthm1 & 0x1F) << 16;
921      Binary |= (lsb & 0x1F) << 7;
922      emitWordLE(Binary);
923      return;
924  }
925
926  // If this is a two-address operand, skip it. e.g. MOVCCr operand 1.
927  if (TID.getOperandConstraint(OpIdx, TOI::TIED_TO) != -1)
928    ++OpIdx;
929
930  // Encode first non-shifter register operand if there is one.
931  bool isUnary = TID.TSFlags & ARMII::UnaryDP;
932  if (!isUnary) {
933    if (ImplicitRn)
934      // Special handling for implicit use (e.g. PC).
935      Binary |= (getARMRegisterNumbering(ImplicitRn) << ARMII::RegRnShift);
936    else {
937      Binary |= getMachineOpValue(MI, OpIdx) << ARMII::RegRnShift;
938      ++OpIdx;
939    }
940  }
941
942  // Encode shifter operand.
943  const MachineOperand &MO = MI.getOperand(OpIdx);
944  if ((TID.TSFlags & ARMII::FormMask) == ARMII::DPSoRegFrm) {
945    // Encode SoReg.
946    emitWordLE(Binary | getMachineSoRegOpValue(MI, TID, MO, OpIdx));
947    return;
948  }
949
950  if (MO.isReg()) {
951    // Encode register Rm.
952    emitWordLE(Binary | getARMRegisterNumbering(MO.getReg()));
953    return;
954  }
955
956  // Encode so_imm.
957  Binary |= getMachineSoImmOpValue((unsigned)MO.getImm());
958
959  emitWordLE(Binary);
960}
961
962void ARMCodeEmitter::emitLoadStoreInstruction(const MachineInstr &MI,
963                                              unsigned ImplicitRd,
964                                              unsigned ImplicitRn) {
965  const TargetInstrDesc &TID = MI.getDesc();
966  unsigned Form = TID.TSFlags & ARMII::FormMask;
967  bool IsPrePost = (TID.TSFlags & ARMII::IndexModeMask) != 0;
968
969  // Part of binary is determined by TableGn.
970  unsigned Binary = getBinaryCodeForInstr(MI);
971
972  // If this is an LDRi12, STRi12 or LDRcp, nothing more needs be done.
973  if (MI.getOpcode() == ARM::LDRi12 || MI.getOpcode() == ARM::LDRcp ||
974      MI.getOpcode() == ARM::STRi12) {
975    emitWordLE(Binary);
976    return;
977  }
978
979  // Set the conditional execution predicate
980  Binary |= II->getPredicate(&MI) << ARMII::CondShift;
981
982  unsigned OpIdx = 0;
983
984  // Operand 0 of a pre- and post-indexed store is the address base
985  // writeback. Skip it.
986  bool Skipped = false;
987  if (IsPrePost && Form == ARMII::StFrm) {
988    ++OpIdx;
989    Skipped = true;
990  }
991
992  // Set first operand
993  if (ImplicitRd)
994    // Special handling for implicit use (e.g. PC).
995    Binary |= (getARMRegisterNumbering(ImplicitRd) << ARMII::RegRdShift);
996  else
997    Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRdShift;
998
999  // Set second operand
1000  if (ImplicitRn)
1001    // Special handling for implicit use (e.g. PC).
1002    Binary |= (getARMRegisterNumbering(ImplicitRn) << ARMII::RegRnShift);
1003  else
1004    Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRnShift;
1005
1006  // If this is a two-address operand, skip it. e.g. LDR_PRE.
1007  if (!Skipped && TID.getOperandConstraint(OpIdx, TOI::TIED_TO) != -1)
1008    ++OpIdx;
1009
1010  const MachineOperand &MO2 = MI.getOperand(OpIdx);
1011  unsigned AM2Opc = (ImplicitRn == ARM::PC)
1012    ? 0 : MI.getOperand(OpIdx+1).getImm();
1013
1014  // Set bit U(23) according to sign of immed value (positive or negative).
1015  Binary |= ((ARM_AM::getAM2Op(AM2Opc) == ARM_AM::add ? 1 : 0) <<
1016             ARMII::U_BitShift);
1017  if (!MO2.getReg()) { // is immediate
1018    if (ARM_AM::getAM2Offset(AM2Opc))
1019      // Set the value of offset_12 field
1020      Binary |= ARM_AM::getAM2Offset(AM2Opc);
1021    emitWordLE(Binary);
1022    return;
1023  }
1024
1025  // Set bit I(25), because this is not in immediate encoding.
1026  Binary |= 1 << ARMII::I_BitShift;
1027  assert(TargetRegisterInfo::isPhysicalRegister(MO2.getReg()));
1028  // Set bit[3:0] to the corresponding Rm register
1029  Binary |= getARMRegisterNumbering(MO2.getReg());
1030
1031  // If this instr is in scaled register offset/index instruction, set
1032  // shift_immed(bit[11:7]) and shift(bit[6:5]) fields.
1033  if (unsigned ShImm = ARM_AM::getAM2Offset(AM2Opc)) {
1034    Binary |= getShiftOp(AM2Opc) << ARMII::ShiftImmShift;  // shift
1035    Binary |= ShImm              << ARMII::ShiftShift;     // shift_immed
1036  }
1037
1038  emitWordLE(Binary);
1039}
1040
1041void ARMCodeEmitter::emitMiscLoadStoreInstruction(const MachineInstr &MI,
1042                                                  unsigned ImplicitRn) {
1043  const TargetInstrDesc &TID = MI.getDesc();
1044  unsigned Form = TID.TSFlags & ARMII::FormMask;
1045  bool IsPrePost = (TID.TSFlags & ARMII::IndexModeMask) != 0;
1046
1047  // Part of binary is determined by TableGn.
1048  unsigned Binary = getBinaryCodeForInstr(MI);
1049
1050  // Set the conditional execution predicate
1051  Binary |= II->getPredicate(&MI) << ARMII::CondShift;
1052
1053  unsigned OpIdx = 0;
1054
1055  // Operand 0 of a pre- and post-indexed store is the address base
1056  // writeback. Skip it.
1057  bool Skipped = false;
1058  if (IsPrePost && Form == ARMII::StMiscFrm) {
1059    ++OpIdx;
1060    Skipped = true;
1061  }
1062
1063  // Set first operand
1064  Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRdShift;
1065
1066  // Skip LDRD and STRD's second operand.
1067  if (TID.Opcode == ARM::LDRD || TID.Opcode == ARM::STRD)
1068    ++OpIdx;
1069
1070  // Set second operand
1071  if (ImplicitRn)
1072    // Special handling for implicit use (e.g. PC).
1073    Binary |= (getARMRegisterNumbering(ImplicitRn) << ARMII::RegRnShift);
1074  else
1075    Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRnShift;
1076
1077  // If this is a two-address operand, skip it. e.g. LDRH_POST.
1078  if (!Skipped && TID.getOperandConstraint(OpIdx, TOI::TIED_TO) != -1)
1079    ++OpIdx;
1080
1081  const MachineOperand &MO2 = MI.getOperand(OpIdx);
1082  unsigned AM3Opc = (ImplicitRn == ARM::PC)
1083    ? 0 : MI.getOperand(OpIdx+1).getImm();
1084
1085  // Set bit U(23) according to sign of immed value (positive or negative)
1086  Binary |= ((ARM_AM::getAM3Op(AM3Opc) == ARM_AM::add ? 1 : 0) <<
1087             ARMII::U_BitShift);
1088
1089  // If this instr is in register offset/index encoding, set bit[3:0]
1090  // to the corresponding Rm register.
1091  if (MO2.getReg()) {
1092    Binary |= getARMRegisterNumbering(MO2.getReg());
1093    emitWordLE(Binary);
1094    return;
1095  }
1096
1097  // This instr is in immediate offset/index encoding, set bit 22 to 1.
1098  Binary |= 1 << ARMII::AM3_I_BitShift;
1099  if (unsigned ImmOffs = ARM_AM::getAM3Offset(AM3Opc)) {
1100    // Set operands
1101    Binary |= (ImmOffs >> 4) << ARMII::ImmHiShift;  // immedH
1102    Binary |= (ImmOffs & 0xF);                      // immedL
1103  }
1104
1105  emitWordLE(Binary);
1106}
1107
1108static unsigned getAddrModeUPBits(unsigned Mode) {
1109  unsigned Binary = 0;
1110
1111  // Set addressing mode by modifying bits U(23) and P(24)
1112  // IA - Increment after  - bit U = 1 and bit P = 0
1113  // IB - Increment before - bit U = 1 and bit P = 1
1114  // DA - Decrement after  - bit U = 0 and bit P = 0
1115  // DB - Decrement before - bit U = 0 and bit P = 1
1116  switch (Mode) {
1117  default: llvm_unreachable("Unknown addressing sub-mode!");
1118  case ARM_AM::da:                                     break;
1119  case ARM_AM::db: Binary |= 0x1 << ARMII::P_BitShift; break;
1120  case ARM_AM::ia: Binary |= 0x1 << ARMII::U_BitShift; break;
1121  case ARM_AM::ib: Binary |= 0x3 << ARMII::U_BitShift; break;
1122  }
1123
1124  return Binary;
1125}
1126
1127void ARMCodeEmitter::emitLoadStoreMultipleInstruction(const MachineInstr &MI) {
1128  const TargetInstrDesc &TID = MI.getDesc();
1129  bool IsUpdating = (TID.TSFlags & ARMII::IndexModeMask) != 0;
1130
1131  // Part of binary is determined by TableGn.
1132  unsigned Binary = getBinaryCodeForInstr(MI);
1133
1134  // Set the conditional execution predicate
1135  Binary |= II->getPredicate(&MI) << ARMII::CondShift;
1136
1137  // Skip operand 0 of an instruction with base register update.
1138  unsigned OpIdx = 0;
1139  if (IsUpdating)
1140    ++OpIdx;
1141
1142  // Set base address operand
1143  Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRnShift;
1144
1145  // Set addressing mode by modifying bits U(23) and P(24)
1146  const MachineOperand &MO = MI.getOperand(OpIdx++);
1147  Binary |= getAddrModeUPBits(ARM_AM::getAM4SubMode(MO.getImm()));
1148
1149  // Set bit W(21)
1150  if (IsUpdating)
1151    Binary |= 0x1 << ARMII::W_BitShift;
1152
1153  // Set registers
1154  for (unsigned i = OpIdx+2, e = MI.getNumOperands(); i != e; ++i) {
1155    const MachineOperand &MO = MI.getOperand(i);
1156    if (!MO.isReg() || MO.isImplicit())
1157      break;
1158    unsigned RegNum = getARMRegisterNumbering(MO.getReg());
1159    assert(TargetRegisterInfo::isPhysicalRegister(MO.getReg()) &&
1160           RegNum < 16);
1161    Binary |= 0x1 << RegNum;
1162  }
1163
1164  emitWordLE(Binary);
1165}
1166
1167void ARMCodeEmitter::emitMulFrmInstruction(const MachineInstr &MI) {
1168  const TargetInstrDesc &TID = MI.getDesc();
1169
1170  // Part of binary is determined by TableGn.
1171  unsigned Binary = getBinaryCodeForInstr(MI);
1172
1173  // Set the conditional execution predicate
1174  Binary |= II->getPredicate(&MI) << ARMII::CondShift;
1175
1176  // Encode S bit if MI modifies CPSR.
1177  Binary |= getAddrModeSBit(MI, TID);
1178
1179  // 32x32->64bit operations have two destination registers. The number
1180  // of register definitions will tell us if that's what we're dealing with.
1181  unsigned OpIdx = 0;
1182  if (TID.getNumDefs() == 2)
1183    Binary |= getMachineOpValue (MI, OpIdx++) << ARMII::RegRdLoShift;
1184
1185  // Encode Rd
1186  Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRdHiShift;
1187
1188  // Encode Rm
1189  Binary |= getMachineOpValue(MI, OpIdx++);
1190
1191  // Encode Rs
1192  Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRsShift;
1193
1194  // Many multiple instructions (e.g. MLA) have three src operands. Encode
1195  // it as Rn (for multiply, that's in the same offset as RdLo.
1196  if (TID.getNumOperands() > OpIdx &&
1197      !TID.OpInfo[OpIdx].isPredicate() &&
1198      !TID.OpInfo[OpIdx].isOptionalDef())
1199    Binary |= getMachineOpValue(MI, OpIdx) << ARMII::RegRdLoShift;
1200
1201  emitWordLE(Binary);
1202}
1203
1204void ARMCodeEmitter::emitExtendInstruction(const MachineInstr &MI) {
1205  const TargetInstrDesc &TID = MI.getDesc();
1206
1207  // Part of binary is determined by TableGn.
1208  unsigned Binary = getBinaryCodeForInstr(MI);
1209
1210  // Set the conditional execution predicate
1211  Binary |= II->getPredicate(&MI) << ARMII::CondShift;
1212
1213  unsigned OpIdx = 0;
1214
1215  // Encode Rd
1216  Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRdShift;
1217
1218  const MachineOperand &MO1 = MI.getOperand(OpIdx++);
1219  const MachineOperand &MO2 = MI.getOperand(OpIdx);
1220  if (MO2.isReg()) {
1221    // Two register operand form.
1222    // Encode Rn.
1223    Binary |= getMachineOpValue(MI, MO1) << ARMII::RegRnShift;
1224
1225    // Encode Rm.
1226    Binary |= getMachineOpValue(MI, MO2);
1227    ++OpIdx;
1228  } else {
1229    Binary |= getMachineOpValue(MI, MO1);
1230  }
1231
1232  // Encode rot imm (0, 8, 16, or 24) if it has a rotate immediate operand.
1233  if (MI.getOperand(OpIdx).isImm() &&
1234      !TID.OpInfo[OpIdx].isPredicate() &&
1235      !TID.OpInfo[OpIdx].isOptionalDef())
1236    Binary |= (getMachineOpValue(MI, OpIdx) / 8) << ARMII::ExtRotImmShift;
1237
1238  emitWordLE(Binary);
1239}
1240
1241void ARMCodeEmitter::emitMiscArithInstruction(const MachineInstr &MI) {
1242  const TargetInstrDesc &TID = MI.getDesc();
1243
1244  // Part of binary is determined by TableGn.
1245  unsigned Binary = getBinaryCodeForInstr(MI);
1246
1247  // Set the conditional execution predicate
1248  Binary |= II->getPredicate(&MI) << ARMII::CondShift;
1249
1250  unsigned OpIdx = 0;
1251
1252  // Encode Rd
1253  Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRdShift;
1254
1255  const MachineOperand &MO = MI.getOperand(OpIdx++);
1256  if (OpIdx == TID.getNumOperands() ||
1257      TID.OpInfo[OpIdx].isPredicate() ||
1258      TID.OpInfo[OpIdx].isOptionalDef()) {
1259    // Encode Rm and it's done.
1260    Binary |= getMachineOpValue(MI, MO);
1261    emitWordLE(Binary);
1262    return;
1263  }
1264
1265  // Encode Rn.
1266  Binary |= getMachineOpValue(MI, MO) << ARMII::RegRnShift;
1267
1268  // Encode Rm.
1269  Binary |= getMachineOpValue(MI, OpIdx++);
1270
1271  // Encode shift_imm.
1272  unsigned ShiftAmt = MI.getOperand(OpIdx).getImm();
1273  if (TID.Opcode == ARM::PKHTB) {
1274    assert(ShiftAmt != 0 && "PKHTB shift_imm is 0!");
1275    if (ShiftAmt == 32)
1276      ShiftAmt = 0;
1277  }
1278  assert(ShiftAmt < 32 && "shift_imm range is 0 to 31!");
1279  Binary |= ShiftAmt << ARMII::ShiftShift;
1280
1281  emitWordLE(Binary);
1282}
1283
1284void ARMCodeEmitter::emitSaturateInstruction(const MachineInstr &MI) {
1285  const TargetInstrDesc &TID = MI.getDesc();
1286
1287  // Part of binary is determined by TableGen.
1288  unsigned Binary = getBinaryCodeForInstr(MI);
1289
1290  // Set the conditional execution predicate
1291  Binary |= II->getPredicate(&MI) << ARMII::CondShift;
1292
1293  // Encode Rd
1294  Binary |= getMachineOpValue(MI, 0) << ARMII::RegRdShift;
1295
1296  // Encode saturate bit position.
1297  unsigned Pos = MI.getOperand(1).getImm();
1298  if (TID.Opcode == ARM::SSAT || TID.Opcode == ARM::SSAT16)
1299    Pos -= 1;
1300  assert((Pos < 16 || (Pos < 32 &&
1301                       TID.Opcode != ARM::SSAT16 &&
1302                       TID.Opcode != ARM::USAT16)) &&
1303         "saturate bit position out of range");
1304  Binary |= Pos << 16;
1305
1306  // Encode Rm
1307  Binary |= getMachineOpValue(MI, 2);
1308
1309  // Encode shift_imm.
1310  if (TID.getNumOperands() == 4) {
1311    unsigned ShiftOp = MI.getOperand(3).getImm();
1312    ARM_AM::ShiftOpc Opc = ARM_AM::getSORegShOp(ShiftOp);
1313    if (Opc == ARM_AM::asr)
1314      Binary |= (1 << 6);
1315    unsigned ShiftAmt = MI.getOperand(3).getImm();
1316    if (ShiftAmt == 32 && Opc == ARM_AM::asr)
1317      ShiftAmt = 0;
1318    assert(ShiftAmt < 32 && "shift_imm range is 0 to 31!");
1319    Binary |= ShiftAmt << ARMII::ShiftShift;
1320  }
1321
1322  emitWordLE(Binary);
1323}
1324
1325void ARMCodeEmitter::emitBranchInstruction(const MachineInstr &MI) {
1326  const TargetInstrDesc &TID = MI.getDesc();
1327
1328  if (TID.Opcode == ARM::TPsoft) {
1329    llvm_unreachable("ARM::TPsoft FIXME"); // FIXME
1330  }
1331
1332  // Part of binary is determined by TableGn.
1333  unsigned Binary = getBinaryCodeForInstr(MI);
1334
1335  // Set the conditional execution predicate
1336  Binary |= II->getPredicate(&MI) << ARMII::CondShift;
1337
1338  // Set signed_immed_24 field
1339  Binary |= getMachineOpValue(MI, 0);
1340
1341  emitWordLE(Binary);
1342}
1343
1344void ARMCodeEmitter::emitInlineJumpTable(unsigned JTIndex) {
1345  // Remember the base address of the inline jump table.
1346  uintptr_t JTBase = MCE.getCurrentPCValue();
1347  JTI->addJumpTableBaseAddr(JTIndex, JTBase);
1348  DEBUG(errs() << "  ** Jump Table #" << JTIndex << " @ " << (void*)JTBase
1349               << '\n');
1350
1351  // Now emit the jump table entries.
1352  const std::vector<MachineBasicBlock*> &MBBs = (*MJTEs)[JTIndex].MBBs;
1353  for (unsigned i = 0, e = MBBs.size(); i != e; ++i) {
1354    if (IsPIC)
1355      // DestBB address - JT base.
1356      emitMachineBasicBlock(MBBs[i], ARM::reloc_arm_pic_jt, JTBase);
1357    else
1358      // Absolute DestBB address.
1359      emitMachineBasicBlock(MBBs[i], ARM::reloc_arm_absolute);
1360    emitWordLE(0);
1361  }
1362}
1363
1364void ARMCodeEmitter::emitMiscBranchInstruction(const MachineInstr &MI) {
1365  const TargetInstrDesc &TID = MI.getDesc();
1366
1367  // Handle jump tables.
1368  if (TID.Opcode == ARM::BR_JTr || TID.Opcode == ARM::BR_JTadd) {
1369    // First emit a ldr pc, [] instruction.
1370    emitDataProcessingInstruction(MI, ARM::PC);
1371
1372    // Then emit the inline jump table.
1373    unsigned JTIndex =
1374      (TID.Opcode == ARM::BR_JTr)
1375      ? MI.getOperand(1).getIndex() : MI.getOperand(2).getIndex();
1376    emitInlineJumpTable(JTIndex);
1377    return;
1378  } else if (TID.Opcode == ARM::BR_JTm) {
1379    // First emit a ldr pc, [] instruction.
1380    emitLoadStoreInstruction(MI, ARM::PC);
1381
1382    // Then emit the inline jump table.
1383    emitInlineJumpTable(MI.getOperand(3).getIndex());
1384    return;
1385  }
1386
1387  // Part of binary is determined by TableGn.
1388  unsigned Binary = getBinaryCodeForInstr(MI);
1389
1390  // Set the conditional execution predicate
1391  Binary |= II->getPredicate(&MI) << ARMII::CondShift;
1392
1393  if (TID.Opcode == ARM::BX_RET || TID.Opcode == ARM::MOVPCLR)
1394    // The return register is LR.
1395    Binary |= getARMRegisterNumbering(ARM::LR);
1396  else
1397    // otherwise, set the return register
1398    Binary |= getMachineOpValue(MI, 0);
1399
1400  emitWordLE(Binary);
1401}
1402
1403static unsigned encodeVFPRd(const MachineInstr &MI, unsigned OpIdx) {
1404  unsigned RegD = MI.getOperand(OpIdx).getReg();
1405  unsigned Binary = 0;
1406  bool isSPVFP = ARM::SPRRegisterClass->contains(RegD);
1407  RegD = getARMRegisterNumbering(RegD);
1408  if (!isSPVFP)
1409    Binary |=   RegD               << ARMII::RegRdShift;
1410  else {
1411    Binary |= ((RegD & 0x1E) >> 1) << ARMII::RegRdShift;
1412    Binary |=  (RegD & 0x01)       << ARMII::D_BitShift;
1413  }
1414  return Binary;
1415}
1416
1417static unsigned encodeVFPRn(const MachineInstr &MI, unsigned OpIdx) {
1418  unsigned RegN = MI.getOperand(OpIdx).getReg();
1419  unsigned Binary = 0;
1420  bool isSPVFP = ARM::SPRRegisterClass->contains(RegN);
1421  RegN = getARMRegisterNumbering(RegN);
1422  if (!isSPVFP)
1423    Binary |=   RegN               << ARMII::RegRnShift;
1424  else {
1425    Binary |= ((RegN & 0x1E) >> 1) << ARMII::RegRnShift;
1426    Binary |=  (RegN & 0x01)       << ARMII::N_BitShift;
1427  }
1428  return Binary;
1429}
1430
1431static unsigned encodeVFPRm(const MachineInstr &MI, unsigned OpIdx) {
1432  unsigned RegM = MI.getOperand(OpIdx).getReg();
1433  unsigned Binary = 0;
1434  bool isSPVFP = ARM::SPRRegisterClass->contains(RegM);
1435  RegM = getARMRegisterNumbering(RegM);
1436  if (!isSPVFP)
1437    Binary |=   RegM;
1438  else {
1439    Binary |= ((RegM & 0x1E) >> 1);
1440    Binary |=  (RegM & 0x01)       << ARMII::M_BitShift;
1441  }
1442  return Binary;
1443}
1444
1445void ARMCodeEmitter::emitVFPArithInstruction(const MachineInstr &MI) {
1446  const TargetInstrDesc &TID = MI.getDesc();
1447
1448  // Part of binary is determined by TableGn.
1449  unsigned Binary = getBinaryCodeForInstr(MI);
1450
1451  // Set the conditional execution predicate
1452  Binary |= II->getPredicate(&MI) << ARMII::CondShift;
1453
1454  unsigned OpIdx = 0;
1455  assert((Binary & ARMII::D_BitShift) == 0 &&
1456         (Binary & ARMII::N_BitShift) == 0 &&
1457         (Binary & ARMII::M_BitShift) == 0 && "VFP encoding bug!");
1458
1459  // Encode Dd / Sd.
1460  Binary |= encodeVFPRd(MI, OpIdx++);
1461
1462  // If this is a two-address operand, skip it, e.g. FMACD.
1463  if (TID.getOperandConstraint(OpIdx, TOI::TIED_TO) != -1)
1464    ++OpIdx;
1465
1466  // Encode Dn / Sn.
1467  if ((TID.TSFlags & ARMII::FormMask) == ARMII::VFPBinaryFrm)
1468    Binary |= encodeVFPRn(MI, OpIdx++);
1469
1470  if (OpIdx == TID.getNumOperands() ||
1471      TID.OpInfo[OpIdx].isPredicate() ||
1472      TID.OpInfo[OpIdx].isOptionalDef()) {
1473    // FCMPEZD etc. has only one operand.
1474    emitWordLE(Binary);
1475    return;
1476  }
1477
1478  // Encode Dm / Sm.
1479  Binary |= encodeVFPRm(MI, OpIdx);
1480
1481  emitWordLE(Binary);
1482}
1483
1484void ARMCodeEmitter::emitVFPConversionInstruction(const MachineInstr &MI) {
1485  const TargetInstrDesc &TID = MI.getDesc();
1486  unsigned Form = TID.TSFlags & ARMII::FormMask;
1487
1488  // Part of binary is determined by TableGn.
1489  unsigned Binary = getBinaryCodeForInstr(MI);
1490
1491  // Set the conditional execution predicate
1492  Binary |= II->getPredicate(&MI) << ARMII::CondShift;
1493
1494  switch (Form) {
1495  default: break;
1496  case ARMII::VFPConv1Frm:
1497  case ARMII::VFPConv2Frm:
1498  case ARMII::VFPConv3Frm:
1499    // Encode Dd / Sd.
1500    Binary |= encodeVFPRd(MI, 0);
1501    break;
1502  case ARMII::VFPConv4Frm:
1503    // Encode Dn / Sn.
1504    Binary |= encodeVFPRn(MI, 0);
1505    break;
1506  case ARMII::VFPConv5Frm:
1507    // Encode Dm / Sm.
1508    Binary |= encodeVFPRm(MI, 0);
1509    break;
1510  }
1511
1512  switch (Form) {
1513  default: break;
1514  case ARMII::VFPConv1Frm:
1515    // Encode Dm / Sm.
1516    Binary |= encodeVFPRm(MI, 1);
1517    break;
1518  case ARMII::VFPConv2Frm:
1519  case ARMII::VFPConv3Frm:
1520    // Encode Dn / Sn.
1521    Binary |= encodeVFPRn(MI, 1);
1522    break;
1523  case ARMII::VFPConv4Frm:
1524  case ARMII::VFPConv5Frm:
1525    // Encode Dd / Sd.
1526    Binary |= encodeVFPRd(MI, 1);
1527    break;
1528  }
1529
1530  if (Form == ARMII::VFPConv5Frm)
1531    // Encode Dn / Sn.
1532    Binary |= encodeVFPRn(MI, 2);
1533  else if (Form == ARMII::VFPConv3Frm)
1534    // Encode Dm / Sm.
1535    Binary |= encodeVFPRm(MI, 2);
1536
1537  emitWordLE(Binary);
1538}
1539
1540void ARMCodeEmitter::emitVFPLoadStoreInstruction(const MachineInstr &MI) {
1541  // Part of binary is determined by TableGn.
1542  unsigned Binary = getBinaryCodeForInstr(MI);
1543
1544  // Set the conditional execution predicate
1545  Binary |= II->getPredicate(&MI) << ARMII::CondShift;
1546
1547  unsigned OpIdx = 0;
1548
1549  // Encode Dd / Sd.
1550  Binary |= encodeVFPRd(MI, OpIdx++);
1551
1552  // Encode address base.
1553  const MachineOperand &Base = MI.getOperand(OpIdx++);
1554  Binary |= getMachineOpValue(MI, Base) << ARMII::RegRnShift;
1555
1556  // If there is a non-zero immediate offset, encode it.
1557  if (Base.isReg()) {
1558    const MachineOperand &Offset = MI.getOperand(OpIdx);
1559    if (unsigned ImmOffs = ARM_AM::getAM5Offset(Offset.getImm())) {
1560      if (ARM_AM::getAM5Op(Offset.getImm()) == ARM_AM::add)
1561        Binary |= 1 << ARMII::U_BitShift;
1562      Binary |= ImmOffs;
1563      emitWordLE(Binary);
1564      return;
1565    }
1566  }
1567
1568  // If immediate offset is omitted, default to +0.
1569  Binary |= 1 << ARMII::U_BitShift;
1570
1571  emitWordLE(Binary);
1572}
1573
1574void
1575ARMCodeEmitter::emitVFPLoadStoreMultipleInstruction(const MachineInstr &MI) {
1576  const TargetInstrDesc &TID = MI.getDesc();
1577  bool IsUpdating = (TID.TSFlags & ARMII::IndexModeMask) != 0;
1578
1579  // Part of binary is determined by TableGn.
1580  unsigned Binary = getBinaryCodeForInstr(MI);
1581
1582  // Set the conditional execution predicate
1583  Binary |= II->getPredicate(&MI) << ARMII::CondShift;
1584
1585  // Skip operand 0 of an instruction with base register update.
1586  unsigned OpIdx = 0;
1587  if (IsUpdating)
1588    ++OpIdx;
1589
1590  // Set base address operand
1591  Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRnShift;
1592
1593  // Set addressing mode by modifying bits U(23) and P(24)
1594  const MachineOperand &MO = MI.getOperand(OpIdx++);
1595  Binary |= getAddrModeUPBits(ARM_AM::getAM4SubMode(MO.getImm()));
1596
1597  // Set bit W(21)
1598  if (IsUpdating)
1599    Binary |= 0x1 << ARMII::W_BitShift;
1600
1601  // First register is encoded in Dd.
1602  Binary |= encodeVFPRd(MI, OpIdx+2);
1603
1604  // Count the number of registers.
1605  unsigned NumRegs = 1;
1606  for (unsigned i = OpIdx+3, e = MI.getNumOperands(); i != e; ++i) {
1607    const MachineOperand &MO = MI.getOperand(i);
1608    if (!MO.isReg() || MO.isImplicit())
1609      break;
1610    ++NumRegs;
1611  }
1612  // Bit 8 will be set if <list> is consecutive 64-bit registers (e.g., D0)
1613  // Otherwise, it will be 0, in the case of 32-bit registers.
1614  if(Binary & 0x100)
1615    Binary |= NumRegs * 2;
1616  else
1617    Binary |= NumRegs;
1618
1619  emitWordLE(Binary);
1620}
1621
1622static unsigned encodeNEONRd(const MachineInstr &MI, unsigned OpIdx) {
1623  unsigned RegD = MI.getOperand(OpIdx).getReg();
1624  unsigned Binary = 0;
1625  RegD = getARMRegisterNumbering(RegD);
1626  Binary |= (RegD & 0xf) << ARMII::RegRdShift;
1627  Binary |= ((RegD >> 4) & 1) << ARMII::D_BitShift;
1628  return Binary;
1629}
1630
1631static unsigned encodeNEONRn(const MachineInstr &MI, unsigned OpIdx) {
1632  unsigned RegN = MI.getOperand(OpIdx).getReg();
1633  unsigned Binary = 0;
1634  RegN = getARMRegisterNumbering(RegN);
1635  Binary |= (RegN & 0xf) << ARMII::RegRnShift;
1636  Binary |= ((RegN >> 4) & 1) << ARMII::N_BitShift;
1637  return Binary;
1638}
1639
1640static unsigned encodeNEONRm(const MachineInstr &MI, unsigned OpIdx) {
1641  unsigned RegM = MI.getOperand(OpIdx).getReg();
1642  unsigned Binary = 0;
1643  RegM = getARMRegisterNumbering(RegM);
1644  Binary |= (RegM & 0xf);
1645  Binary |= ((RegM >> 4) & 1) << ARMII::M_BitShift;
1646  return Binary;
1647}
1648
1649/// convertNEONDataProcToThumb - Convert the ARM mode encoding for a NEON
1650/// data-processing instruction to the corresponding Thumb encoding.
1651static unsigned convertNEONDataProcToThumb(unsigned Binary) {
1652  assert((Binary & 0xfe000000) == 0xf2000000 &&
1653         "not an ARM NEON data-processing instruction");
1654  unsigned UBit = (Binary >> 24) & 1;
1655  return 0xef000000 | (UBit << 28) | (Binary & 0xffffff);
1656}
1657
1658void ARMCodeEmitter::emitNEONLaneInstruction(const MachineInstr &MI) {
1659  unsigned Binary = getBinaryCodeForInstr(MI);
1660
1661  unsigned RegTOpIdx, RegNOpIdx, LnOpIdx;
1662  const TargetInstrDesc &TID = MI.getDesc();
1663  if ((TID.TSFlags & ARMII::FormMask) == ARMII::NGetLnFrm) {
1664    RegTOpIdx = 0;
1665    RegNOpIdx = 1;
1666    LnOpIdx = 2;
1667  } else { // ARMII::NSetLnFrm
1668    RegTOpIdx = 2;
1669    RegNOpIdx = 0;
1670    LnOpIdx = 3;
1671  }
1672
1673  // Set the conditional execution predicate
1674  Binary |= (IsThumb ? ARMCC::AL : II->getPredicate(&MI)) << ARMII::CondShift;
1675
1676  unsigned RegT = MI.getOperand(RegTOpIdx).getReg();
1677  RegT = getARMRegisterNumbering(RegT);
1678  Binary |= (RegT << ARMII::RegRdShift);
1679  Binary |= encodeNEONRn(MI, RegNOpIdx);
1680
1681  unsigned LaneShift;
1682  if ((Binary & (1 << 22)) != 0)
1683    LaneShift = 0; // 8-bit elements
1684  else if ((Binary & (1 << 5)) != 0)
1685    LaneShift = 1; // 16-bit elements
1686  else
1687    LaneShift = 2; // 32-bit elements
1688
1689  unsigned Lane = MI.getOperand(LnOpIdx).getImm() << LaneShift;
1690  unsigned Opc1 = Lane >> 2;
1691  unsigned Opc2 = Lane & 3;
1692  assert((Opc1 & 3) == 0 && "out-of-range lane number operand");
1693  Binary |= (Opc1 << 21);
1694  Binary |= (Opc2 << 5);
1695
1696  emitWordLE(Binary);
1697}
1698
1699void ARMCodeEmitter::emitNEONDupInstruction(const MachineInstr &MI) {
1700  unsigned Binary = getBinaryCodeForInstr(MI);
1701
1702  // Set the conditional execution predicate
1703  Binary |= (IsThumb ? ARMCC::AL : II->getPredicate(&MI)) << ARMII::CondShift;
1704
1705  unsigned RegT = MI.getOperand(1).getReg();
1706  RegT = getARMRegisterNumbering(RegT);
1707  Binary |= (RegT << ARMII::RegRdShift);
1708  Binary |= encodeNEONRn(MI, 0);
1709  emitWordLE(Binary);
1710}
1711
1712void ARMCodeEmitter::emitNEON1RegModImmInstruction(const MachineInstr &MI) {
1713  unsigned Binary = getBinaryCodeForInstr(MI);
1714  // Destination register is encoded in Dd.
1715  Binary |= encodeNEONRd(MI, 0);
1716  // Immediate fields: Op, Cmode, I, Imm3, Imm4
1717  unsigned Imm = MI.getOperand(1).getImm();
1718  unsigned Op = (Imm >> 12) & 1;
1719  unsigned Cmode = (Imm >> 8) & 0xf;
1720  unsigned I = (Imm >> 7) & 1;
1721  unsigned Imm3 = (Imm >> 4) & 0x7;
1722  unsigned Imm4 = Imm & 0xf;
1723  Binary |= (I << 24) | (Imm3 << 16) | (Cmode << 8) | (Op << 5) | Imm4;
1724  if (IsThumb)
1725    Binary = convertNEONDataProcToThumb(Binary);
1726  emitWordLE(Binary);
1727}
1728
1729void ARMCodeEmitter::emitNEON2RegInstruction(const MachineInstr &MI) {
1730  const TargetInstrDesc &TID = MI.getDesc();
1731  unsigned Binary = getBinaryCodeForInstr(MI);
1732  // Destination register is encoded in Dd; source register in Dm.
1733  unsigned OpIdx = 0;
1734  Binary |= encodeNEONRd(MI, OpIdx++);
1735  if (TID.getOperandConstraint(OpIdx, TOI::TIED_TO) != -1)
1736    ++OpIdx;
1737  Binary |= encodeNEONRm(MI, OpIdx);
1738  if (IsThumb)
1739    Binary = convertNEONDataProcToThumb(Binary);
1740  // FIXME: This does not handle VDUPfdf or VDUPfqf.
1741  emitWordLE(Binary);
1742}
1743
1744void ARMCodeEmitter::emitNEON3RegInstruction(const MachineInstr &MI) {
1745  const TargetInstrDesc &TID = MI.getDesc();
1746  unsigned Binary = getBinaryCodeForInstr(MI);
1747  // Destination register is encoded in Dd; source registers in Dn and Dm.
1748  unsigned OpIdx = 0;
1749  Binary |= encodeNEONRd(MI, OpIdx++);
1750  if (TID.getOperandConstraint(OpIdx, TOI::TIED_TO) != -1)
1751    ++OpIdx;
1752  Binary |= encodeNEONRn(MI, OpIdx++);
1753  if (TID.getOperandConstraint(OpIdx, TOI::TIED_TO) != -1)
1754    ++OpIdx;
1755  Binary |= encodeNEONRm(MI, OpIdx);
1756  if (IsThumb)
1757    Binary = convertNEONDataProcToThumb(Binary);
1758  // FIXME: This does not handle VMOVDneon or VMOVQ.
1759  emitWordLE(Binary);
1760}
1761
1762#include "ARMGenCodeEmitter.inc"
1763