ARMCodeEmitter.cpp revision 90c579de5a383cee278acc3f7e7b9d0a656e6a35 
1//===-- ARM/ARMCodeEmitter.cpp - Convert ARM code to machine code ---------===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file contains the pass that transforms the ARM machine instructions into
11// relocatable machine code.
12//
13//===----------------------------------------------------------------------===//
14
15#define DEBUG_TYPE "jit"
16#include "ARM.h"
17#include "ARMAddressingModes.h"
18#include "ARMConstantPoolValue.h"
19#include "ARMInstrInfo.h"
20#include "ARMRelocations.h"
21#include "ARMSubtarget.h"
22#include "ARMTargetMachine.h"
23#include "llvm/Constants.h"
24#include "llvm/DerivedTypes.h"
25#include "llvm/Function.h"
26#include "llvm/PassManager.h"
27#include "llvm/CodeGen/JITCodeEmitter.h"
28#include "llvm/CodeGen/MachineConstantPool.h"
29#include "llvm/CodeGen/MachineFunctionPass.h"
30#include "llvm/CodeGen/MachineInstr.h"
31#include "llvm/CodeGen/MachineJumpTableInfo.h"
32#include "llvm/CodeGen/MachineModuleInfo.h"
33#include "llvm/CodeGen/Passes.h"
34#include "llvm/ADT/Statistic.h"
35#include "llvm/Support/Debug.h"
36#include "llvm/Support/ErrorHandling.h"
37#include "llvm/Support/raw_ostream.h"
38#ifndef NDEBUG
39#include <iomanip>
40#endif
41using namespace llvm;
42
43STATISTIC(NumEmitted, "Number of machine instructions emitted");
44
45namespace {
46
47  class ARMCodeEmitter : public MachineFunctionPass {
48    ARMJITInfo                *JTI;
49    const ARMInstrInfo        *II;
50    const TargetData          *TD;
51    const ARMSubtarget        *Subtarget;
52    TargetMachine             &TM;
53    JITCodeEmitter            &MCE;
54    MachineModuleInfo *MMI;
55    const std::vector<MachineConstantPoolEntry> *MCPEs;
56    const std::vector<MachineJumpTableEntry> *MJTEs;
57    bool IsPIC;
58    bool IsThumb;
59
60    void getAnalysisUsage(AnalysisUsage &AU) const {
61      AU.addRequired<MachineModuleInfo>();
62      MachineFunctionPass::getAnalysisUsage(AU);
63    }
64
65    static char ID;
66  public:
67    ARMCodeEmitter(TargetMachine &tm, JITCodeEmitter &mce)
68      : MachineFunctionPass(ID), JTI(0),
69        II((const ARMInstrInfo *)tm.getInstrInfo()),
70        TD(tm.getTargetData()), TM(tm),
71        MCE(mce), MCPEs(0), MJTEs(0),
72        IsPIC(TM.getRelocationModel() == Reloc::PIC_), IsThumb(false) {}
73
74    /// getBinaryCodeForInstr - This function, generated by the
75    /// CodeEmitterGenerator using TableGen, produces the binary encoding for
76    /// machine instructions.
77    unsigned getBinaryCodeForInstr(const MachineInstr &MI);
78
79    bool runOnMachineFunction(MachineFunction &MF);
80
81    virtual const char *getPassName() const {
82      return "ARM Machine Code Emitter";
83    }
84
85    void emitInstruction(const MachineInstr &MI);
86
87  private:
88
89    void emitWordLE(unsigned Binary);
90    void emitDWordLE(uint64_t Binary);
91    void emitConstPoolInstruction(const MachineInstr &MI);
92    void emitMOVi32immInstruction(const MachineInstr &MI);
93    void emitMOVi2piecesInstruction(const MachineInstr &MI);
94    void emitLEApcrelJTInstruction(const MachineInstr &MI);
95    void emitPseudoMoveInstruction(const MachineInstr &MI);
96    void addPCLabel(unsigned LabelID);
97    void emitPseudoInstruction(const MachineInstr &MI);
98    unsigned getMachineSoRegOpValue(const MachineInstr &MI,
99                                    const TargetInstrDesc &TID,
100                                    const MachineOperand &MO,
101                                    unsigned OpIdx);
102
103    unsigned getMachineSoImmOpValue(unsigned SoImm);
104
105    unsigned getAddrModeSBit(const MachineInstr &MI,
106                             const TargetInstrDesc &TID) const;
107
108    void emitDataProcessingInstruction(const MachineInstr &MI,
109                                       unsigned ImplicitRd = 0,
110                                       unsigned ImplicitRn = 0);
111
112    void emitLoadStoreInstruction(const MachineInstr &MI,
113                                  unsigned ImplicitRd = 0,
114                                  unsigned ImplicitRn = 0);
115
116    void emitMiscLoadStoreInstruction(const MachineInstr &MI,
117                                      unsigned ImplicitRn = 0);
118
119    void emitLoadStoreMultipleInstruction(const MachineInstr &MI);
120
121    void emitMulFrmInstruction(const MachineInstr &MI);
122
123    void emitExtendInstruction(const MachineInstr &MI);
124
125    void emitMiscArithInstruction(const MachineInstr &MI);
126
127    void emitBranchInstruction(const MachineInstr &MI);
128
129    void emitInlineJumpTable(unsigned JTIndex);
130
131    void emitMiscBranchInstruction(const MachineInstr &MI);
132
133    void emitVFPArithInstruction(const MachineInstr &MI);
134
135    void emitVFPConversionInstruction(const MachineInstr &MI);
136
137    void emitVFPLoadStoreInstruction(const MachineInstr &MI);
138
139    void emitVFPLoadStoreMultipleInstruction(const MachineInstr &MI);
140
141    void emitMiscInstruction(const MachineInstr &MI);
142
143    void emitNEONLaneInstruction(const MachineInstr &MI);
144    void emitNEONDupInstruction(const MachineInstr &MI);
145    void emitNEON1RegModImmInstruction(const MachineInstr &MI);
146    void emitNEON2RegInstruction(const MachineInstr &MI);
147    void emitNEON3RegInstruction(const MachineInstr &MI);
148
149    /// getMachineOpValue - Return binary encoding of operand. If the machine
150    /// operand requires relocation, record the relocation and return zero.
151    unsigned getMachineOpValue(const MachineInstr &MI,const MachineOperand &MO);
152    unsigned getMachineOpValue(const MachineInstr &MI, unsigned OpIdx) {
153      return getMachineOpValue(MI, MI.getOperand(OpIdx));
154    }
155
156    /// getMovi32Value - Return binary encoding of operand for movw/movt. If the
157    /// machine operand requires relocation, record the relocation and return
158    /// zero.
159    unsigned getMovi32Value(const MachineInstr &MI,const MachineOperand &MO,
160                            unsigned Reloc);
161    unsigned getMovi32Value(const MachineInstr &MI, unsigned OpIdx,
162                            unsigned Reloc) {
163      return getMovi32Value(MI, MI.getOperand(OpIdx), Reloc);
164    }
165
166    /// getShiftOp - Return the shift opcode (bit[6:5]) of the immediate value.
167    ///
168    unsigned getShiftOp(unsigned Imm) const ;
169
170    /// Routines that handle operands which add machine relocations which are
171    /// fixed up by the relocation stage.
172    void emitGlobalAddress(const GlobalValue *GV, unsigned Reloc,
173                           bool MayNeedFarStub,  bool Indirect,
174                           intptr_t ACPV = 0);
175    void emitExternalSymbolAddress(const char *ES, unsigned Reloc);
176    void emitConstPoolAddress(unsigned CPI, unsigned Reloc);
177    void emitJumpTableAddress(unsigned JTIndex, unsigned Reloc);
178    void emitMachineBasicBlock(MachineBasicBlock *BB, unsigned Reloc,
179                               intptr_t JTBase = 0);
180  };
181}
182
183char ARMCodeEmitter::ID = 0;
184
185/// createARMJITCodeEmitterPass - Return a pass that emits the collected ARM
186/// code to the specified MCE object.
187FunctionPass *llvm::createARMJITCodeEmitterPass(ARMBaseTargetMachine &TM,
188                                                JITCodeEmitter &JCE) {
189  return new ARMCodeEmitter(TM, JCE);
190}
191
192bool ARMCodeEmitter::runOnMachineFunction(MachineFunction &MF) {
193  assert((MF.getTarget().getRelocationModel() != Reloc::Default ||
194          MF.getTarget().getRelocationModel() != Reloc::Static) &&
195         "JIT relocation model must be set to static or default!");
196  JTI = ((ARMTargetMachine &)MF.getTarget()).getJITInfo();
197  II = ((const ARMTargetMachine &)MF.getTarget()).getInstrInfo();
198  TD = ((const ARMTargetMachine &)MF.getTarget()).getTargetData();
199  Subtarget = &TM.getSubtarget<ARMSubtarget>();
200  MCPEs = &MF.getConstantPool()->getConstants();
201  MJTEs = 0;
202  if (MF.getJumpTableInfo()) MJTEs = &MF.getJumpTableInfo()->getJumpTables();
203  IsPIC = TM.getRelocationModel() == Reloc::PIC_;
204  IsThumb = MF.getInfo<ARMFunctionInfo>()->isThumbFunction();
205  JTI->Initialize(MF, IsPIC);
206  MMI = &getAnalysis<MachineModuleInfo>();
207  MCE.setModuleInfo(MMI);
208
209  do {
210    DEBUG(errs() << "JITTing function '"
211          << MF.getFunction()->getName() << "'\n");
212    MCE.startFunction(MF);
213    for (MachineFunction::iterator MBB = MF.begin(), E = MF.end();
214         MBB != E; ++MBB) {
215      MCE.StartMachineBasicBlock(MBB);
216      for (MachineBasicBlock::const_iterator I = MBB->begin(), E = MBB->end();
217           I != E; ++I)
218        emitInstruction(*I);
219    }
220  } while (MCE.finishFunction(MF));
221
222  return false;
223}
224
225/// getShiftOp - Return the shift opcode (bit[6:5]) of the immediate value.
226///
227unsigned ARMCodeEmitter::getShiftOp(unsigned Imm) const {
228  switch (ARM_AM::getAM2ShiftOpc(Imm)) {
229  default: llvm_unreachable("Unknown shift opc!");
230  case ARM_AM::asr: return 2;
231  case ARM_AM::lsl: return 0;
232  case ARM_AM::lsr: return 1;
233  case ARM_AM::ror:
234  case ARM_AM::rrx: return 3;
235  }
236  return 0;
237}
238
239/// getMovi32Value - Return binary encoding of operand for movw/movt. If the
240/// machine operand requires relocation, record the relocation and return zero.
241unsigned ARMCodeEmitter::getMovi32Value(const MachineInstr &MI,
242                                        const MachineOperand &MO,
243                                        unsigned Reloc) {
244  assert(((Reloc == ARM::reloc_arm_movt) || (Reloc == ARM::reloc_arm_movw))
245      && "Relocation to this function should be for movt or movw");
246
247  if (MO.isImm())
248    return static_cast<unsigned>(MO.getImm());
249  else if (MO.isGlobal())
250    emitGlobalAddress(MO.getGlobal(), Reloc, true, false);
251  else if (MO.isSymbol())
252    emitExternalSymbolAddress(MO.getSymbolName(), Reloc);
253  else if (MO.isMBB())
254    emitMachineBasicBlock(MO.getMBB(), Reloc);
255  else {
256#ifndef NDEBUG
257    errs() << MO;
258#endif
259    llvm_unreachable("Unsupported operand type for movw/movt");
260  }
261  return 0;
262}
263
264/// getMachineOpValue - Return binary encoding of operand. If the machine
265/// operand requires relocation, record the relocation and return zero.
266unsigned ARMCodeEmitter::getMachineOpValue(const MachineInstr &MI,
267                                           const MachineOperand &MO) {
268  if (MO.isReg())
269    return ARMRegisterInfo::getRegisterNumbering(MO.getReg());
270  else if (MO.isImm())
271    return static_cast<unsigned>(MO.getImm());
272  else if (MO.isGlobal())
273    emitGlobalAddress(MO.getGlobal(), ARM::reloc_arm_branch, true, false);
274  else if (MO.isSymbol())
275    emitExternalSymbolAddress(MO.getSymbolName(), ARM::reloc_arm_branch);
276  else if (MO.isCPI()) {
277    const TargetInstrDesc &TID = MI.getDesc();
278    // For VFP load, the immediate offset is multiplied by 4.
279    unsigned Reloc =  ((TID.TSFlags & ARMII::FormMask) == ARMII::VFPLdStFrm)
280      ? ARM::reloc_arm_vfp_cp_entry : ARM::reloc_arm_cp_entry;
281    emitConstPoolAddress(MO.getIndex(), Reloc);
282  } else if (MO.isJTI())
283    emitJumpTableAddress(MO.getIndex(), ARM::reloc_arm_relative);
284  else if (MO.isMBB())
285    emitMachineBasicBlock(MO.getMBB(), ARM::reloc_arm_branch);
286  else {
287#ifndef NDEBUG
288    errs() << MO;
289#endif
290    llvm_unreachable(0);
291  }
292  return 0;
293}
294
295/// emitGlobalAddress - Emit the specified address to the code stream.
296///
297void ARMCodeEmitter::emitGlobalAddress(const GlobalValue *GV, unsigned Reloc,
298                                       bool MayNeedFarStub, bool Indirect,
299                                       intptr_t ACPV) {
300  MachineRelocation MR = Indirect
301    ? MachineRelocation::getIndirectSymbol(MCE.getCurrentPCOffset(), Reloc,
302                                           const_cast<GlobalValue *>(GV),
303                                           ACPV, MayNeedFarStub)
304    : MachineRelocation::getGV(MCE.getCurrentPCOffset(), Reloc,
305                               const_cast<GlobalValue *>(GV), ACPV,
306                               MayNeedFarStub);
307  MCE.addRelocation(MR);
308}
309
310/// emitExternalSymbolAddress - Arrange for the address of an external symbol to
311/// be emitted to the current location in the function, and allow it to be PC
312/// relative.
313void ARMCodeEmitter::emitExternalSymbolAddress(const char *ES, unsigned Reloc) {
314  MCE.addRelocation(MachineRelocation::getExtSym(MCE.getCurrentPCOffset(),
315                                                 Reloc, ES));
316}
317
318/// emitConstPoolAddress - Arrange for the address of an constant pool
319/// to be emitted to the current location in the function, and allow it to be PC
320/// relative.
321void ARMCodeEmitter::emitConstPoolAddress(unsigned CPI, unsigned Reloc) {
322  // Tell JIT emitter we'll resolve the address.
323  MCE.addRelocation(MachineRelocation::getConstPool(MCE.getCurrentPCOffset(),
324                                                    Reloc, CPI, 0, true));
325}
326
327/// emitJumpTableAddress - Arrange for the address of a jump table to
328/// be emitted to the current location in the function, and allow it to be PC
329/// relative.
330void ARMCodeEmitter::emitJumpTableAddress(unsigned JTIndex, unsigned Reloc) {
331  MCE.addRelocation(MachineRelocation::getJumpTable(MCE.getCurrentPCOffset(),
332                                                    Reloc, JTIndex, 0, true));
333}
334
335/// emitMachineBasicBlock - Emit the specified address basic block.
336void ARMCodeEmitter::emitMachineBasicBlock(MachineBasicBlock *BB,
337                                           unsigned Reloc, intptr_t JTBase) {
338  MCE.addRelocation(MachineRelocation::getBB(MCE.getCurrentPCOffset(),
339                                             Reloc, BB, JTBase));
340}
341
342void ARMCodeEmitter::emitWordLE(unsigned Binary) {
343  DEBUG(errs() << "  0x";
344        errs().write_hex(Binary) << "\n");
345  MCE.emitWordLE(Binary);
346}
347
348void ARMCodeEmitter::emitDWordLE(uint64_t Binary) {
349  DEBUG(errs() << "  0x";
350        errs().write_hex(Binary) << "\n");
351  MCE.emitDWordLE(Binary);
352}
353
354void ARMCodeEmitter::emitInstruction(const MachineInstr &MI) {
355  DEBUG(errs() << "JIT: " << (void*)MCE.getCurrentPCValue() << ":\t" << MI);
356
357  MCE.processDebugLoc(MI.getDebugLoc(), true);
358
359  ++NumEmitted;  // Keep track of the # of mi's emitted
360  switch (MI.getDesc().TSFlags & ARMII::FormMask) {
361  default: {
362    llvm_unreachable("Unhandled instruction encoding format!");
363    break;
364  }
365  case ARMII::Pseudo:
366    emitPseudoInstruction(MI);
367    break;
368  case ARMII::DPFrm:
369  case ARMII::DPSoRegFrm:
370    emitDataProcessingInstruction(MI);
371    break;
372  case ARMII::LdFrm:
373  case ARMII::StFrm:
374    emitLoadStoreInstruction(MI);
375    break;
376  case ARMII::LdMiscFrm:
377  case ARMII::StMiscFrm:
378    emitMiscLoadStoreInstruction(MI);
379    break;
380  case ARMII::LdStMulFrm:
381    emitLoadStoreMultipleInstruction(MI);
382    break;
383  case ARMII::MulFrm:
384    emitMulFrmInstruction(MI);
385    break;
386  case ARMII::ExtFrm:
387    emitExtendInstruction(MI);
388    break;
389  case ARMII::ArithMiscFrm:
390    emitMiscArithInstruction(MI);
391    break;
392  case ARMII::BrFrm:
393    emitBranchInstruction(MI);
394    break;
395  case ARMII::BrMiscFrm:
396    emitMiscBranchInstruction(MI);
397    break;
398  // VFP instructions.
399  case ARMII::VFPUnaryFrm:
400  case ARMII::VFPBinaryFrm:
401    emitVFPArithInstruction(MI);
402    break;
403  case ARMII::VFPConv1Frm:
404  case ARMII::VFPConv2Frm:
405  case ARMII::VFPConv3Frm:
406  case ARMII::VFPConv4Frm:
407  case ARMII::VFPConv5Frm:
408    emitVFPConversionInstruction(MI);
409    break;
410  case ARMII::VFPLdStFrm:
411    emitVFPLoadStoreInstruction(MI);
412    break;
413  case ARMII::VFPLdStMulFrm:
414    emitVFPLoadStoreMultipleInstruction(MI);
415    break;
416  case ARMII::VFPMiscFrm:
417    emitMiscInstruction(MI);
418    break;
419  // NEON instructions.
420  case ARMII::NGetLnFrm:
421  case ARMII::NSetLnFrm:
422    emitNEONLaneInstruction(MI);
423    break;
424  case ARMII::NDupFrm:
425    emitNEONDupInstruction(MI);
426    break;
427  case ARMII::N1RegModImmFrm:
428    emitNEON1RegModImmInstruction(MI);
429    break;
430  case ARMII::N2RegFrm:
431    emitNEON2RegInstruction(MI);
432    break;
433  case ARMII::N3RegFrm:
434    emitNEON3RegInstruction(MI);
435    break;
436  }
437  MCE.processDebugLoc(MI.getDebugLoc(), false);
438}
439
440void ARMCodeEmitter::emitConstPoolInstruction(const MachineInstr &MI) {
441  unsigned CPI = MI.getOperand(0).getImm();       // CP instruction index.
442  unsigned CPIndex = MI.getOperand(1).getIndex(); // Actual cp entry index.
443  const MachineConstantPoolEntry &MCPE = (*MCPEs)[CPIndex];
444
445  // Remember the CONSTPOOL_ENTRY address for later relocation.
446  JTI->addConstantPoolEntryAddr(CPI, MCE.getCurrentPCValue());
447
448  // Emit constpool island entry. In most cases, the actual values will be
449  // resolved and relocated after code emission.
450  if (MCPE.isMachineConstantPoolEntry()) {
451    ARMConstantPoolValue *ACPV =
452      static_cast<ARMConstantPoolValue*>(MCPE.Val.MachineCPVal);
453
454    DEBUG(errs() << "  ** ARM constant pool #" << CPI << " @ "
455          << (void*)MCE.getCurrentPCValue() << " " << *ACPV << '\n');
456
457    assert(ACPV->isGlobalValue() && "unsupported constant pool value");
458    const GlobalValue *GV = ACPV->getGV();
459    if (GV) {
460      Reloc::Model RelocM = TM.getRelocationModel();
461      emitGlobalAddress(GV, ARM::reloc_arm_machine_cp_entry,
462                        isa<Function>(GV),
463                        Subtarget->GVIsIndirectSymbol(GV, RelocM),
464                        (intptr_t)ACPV);
465     } else  {
466      emitExternalSymbolAddress(ACPV->getSymbol(), ARM::reloc_arm_absolute);
467    }
468    emitWordLE(0);
469  } else {
470    const Constant *CV = MCPE.Val.ConstVal;
471
472    DEBUG({
473        errs() << "  ** Constant pool #" << CPI << " @ "
474               << (void*)MCE.getCurrentPCValue() << " ";
475        if (const Function *F = dyn_cast<Function>(CV))
476          errs() << F->getName();
477        else
478          errs() << *CV;
479        errs() << '\n';
480      });
481
482    if (const GlobalValue *GV = dyn_cast<GlobalValue>(CV)) {
483      emitGlobalAddress(GV, ARM::reloc_arm_absolute, isa<Function>(GV), false);
484      emitWordLE(0);
485    } else if (const ConstantInt *CI = dyn_cast<ConstantInt>(CV)) {
486      uint32_t Val = *(uint32_t*)CI->getValue().getRawData();
487      emitWordLE(Val);
488    } else if (const ConstantFP *CFP = dyn_cast<ConstantFP>(CV)) {
489      if (CFP->getType()->isFloatTy())
490        emitWordLE(CFP->getValueAPF().bitcastToAPInt().getZExtValue());
491      else if (CFP->getType()->isDoubleTy())
492        emitDWordLE(CFP->getValueAPF().bitcastToAPInt().getZExtValue());
493      else {
494        llvm_unreachable("Unable to handle this constantpool entry!");
495      }
496    } else {
497      llvm_unreachable("Unable to handle this constantpool entry!");
498    }
499  }
500}
501
502void ARMCodeEmitter::emitMOVi32immInstruction(const MachineInstr &MI) {
503  const MachineOperand &MO0 = MI.getOperand(0);
504  const MachineOperand &MO1 = MI.getOperand(1);
505
506  // Emit the 'movw' instruction.
507  unsigned Binary = 0x30 << 20;  // mov: Insts{27-20} = 0b00110000
508
509  unsigned Lo16 = getMovi32Value(MI, MO1, ARM::reloc_arm_movw) & 0xFFFF;
510
511  // Set the conditional execution predicate.
512  Binary |= II->getPredicate(&MI) << ARMII::CondShift;
513
514  // Encode Rd.
515  Binary |= getMachineOpValue(MI, MO0) << ARMII::RegRdShift;
516
517  // Encode imm16 as imm4:imm12
518  Binary |= Lo16 & 0xFFF; // Insts{11-0} = imm12
519  Binary |= ((Lo16 >> 12) & 0xF) << 16; // Insts{19-16} = imm4
520  emitWordLE(Binary);
521
522  unsigned Hi16 = getMovi32Value(MI, MO1, ARM::reloc_arm_movt) >> 16;
523  // Emit the 'movt' instruction.
524  Binary = 0x34 << 20; // movt: Insts{27-20} = 0b00110100
525
526  // Set the conditional execution predicate.
527  Binary |= II->getPredicate(&MI) << ARMII::CondShift;
528
529  // Encode Rd.
530  Binary |= getMachineOpValue(MI, MO0) << ARMII::RegRdShift;
531
532  // Encode imm16 as imm4:imm1, same as movw above.
533  Binary |= Hi16 & 0xFFF;
534  Binary |= ((Hi16 >> 12) & 0xF) << 16;
535  emitWordLE(Binary);
536}
537
538void ARMCodeEmitter::emitMOVi2piecesInstruction(const MachineInstr &MI) {
539  const MachineOperand &MO0 = MI.getOperand(0);
540  const MachineOperand &MO1 = MI.getOperand(1);
541  assert(MO1.isImm() && ARM_AM::isSOImmTwoPartVal(MO1.getImm()) &&
542                                                  "Not a valid so_imm value!");
543  unsigned V1 = ARM_AM::getSOImmTwoPartFirst(MO1.getImm());
544  unsigned V2 = ARM_AM::getSOImmTwoPartSecond(MO1.getImm());
545
546  // Emit the 'mov' instruction.
547  unsigned Binary = 0xd << 21;  // mov: Insts{24-21} = 0b1101
548
549  // Set the conditional execution predicate.
550  Binary |= II->getPredicate(&MI) << ARMII::CondShift;
551
552  // Encode Rd.
553  Binary |= getMachineOpValue(MI, MO0) << ARMII::RegRdShift;
554
555  // Encode so_imm.
556  // Set bit I(25) to identify this is the immediate form of <shifter_op>
557  Binary |= 1 << ARMII::I_BitShift;
558  Binary |= getMachineSoImmOpValue(V1);
559  emitWordLE(Binary);
560
561  // Now the 'orr' instruction.
562  Binary = 0xc << 21;  // orr: Insts{24-21} = 0b1100
563
564  // Set the conditional execution predicate.
565  Binary |= II->getPredicate(&MI) << ARMII::CondShift;
566
567  // Encode Rd.
568  Binary |= getMachineOpValue(MI, MO0) << ARMII::RegRdShift;
569
570  // Encode Rn.
571  Binary |= getMachineOpValue(MI, MO0) << ARMII::RegRnShift;
572
573  // Encode so_imm.
574  // Set bit I(25) to identify this is the immediate form of <shifter_op>
575  Binary |= 1 << ARMII::I_BitShift;
576  Binary |= getMachineSoImmOpValue(V2);
577  emitWordLE(Binary);
578}
579
580void ARMCodeEmitter::emitLEApcrelJTInstruction(const MachineInstr &MI) {
581  // It's basically add r, pc, (LJTI - $+8)
582
583  const TargetInstrDesc &TID = MI.getDesc();
584
585  // Emit the 'add' instruction.
586  unsigned Binary = 0x4 << 21;  // add: Insts{24-31} = 0b0100
587
588  // Set the conditional execution predicate
589  Binary |= II->getPredicate(&MI) << ARMII::CondShift;
590
591  // Encode S bit if MI modifies CPSR.
592  Binary |= getAddrModeSBit(MI, TID);
593
594  // Encode Rd.
595  Binary |= getMachineOpValue(MI, 0) << ARMII::RegRdShift;
596
597  // Encode Rn which is PC.
598  Binary |= ARMRegisterInfo::getRegisterNumbering(ARM::PC) << ARMII::RegRnShift;
599
600  // Encode the displacement.
601  Binary |= 1 << ARMII::I_BitShift;
602  emitJumpTableAddress(MI.getOperand(1).getIndex(), ARM::reloc_arm_jt_base);
603
604  emitWordLE(Binary);
605}
606
607void ARMCodeEmitter::emitPseudoMoveInstruction(const MachineInstr &MI) {
608  unsigned Opcode = MI.getDesc().Opcode;
609
610  // Part of binary is determined by TableGn.
611  unsigned Binary = getBinaryCodeForInstr(MI);
612
613  // Set the conditional execution predicate
614  Binary |= II->getPredicate(&MI) << ARMII::CondShift;
615
616  // Encode S bit if MI modifies CPSR.
617  if (Opcode == ARM::MOVsrl_flag || Opcode == ARM::MOVsra_flag)
618    Binary |= 1 << ARMII::S_BitShift;
619
620  // Encode register def if there is one.
621  Binary |= getMachineOpValue(MI, 0) << ARMII::RegRdShift;
622
623  // Encode the shift operation.
624  switch (Opcode) {
625  default: break;
626  case ARM::MOVrx:
627    // rrx
628    Binary |= 0x6 << 4;
629    break;
630  case ARM::MOVsrl_flag:
631    // lsr #1
632    Binary |= (0x2 << 4) | (1 << 7);
633    break;
634  case ARM::MOVsra_flag:
635    // asr #1
636    Binary |= (0x4 << 4) | (1 << 7);
637    break;
638  }
639
640  // Encode register Rm.
641  Binary |= getMachineOpValue(MI, 1);
642
643  emitWordLE(Binary);
644}
645
646void ARMCodeEmitter::addPCLabel(unsigned LabelID) {
647  DEBUG(errs() << "  ** LPC" << LabelID << " @ "
648        << (void*)MCE.getCurrentPCValue() << '\n');
649  JTI->addPCLabelAddr(LabelID, MCE.getCurrentPCValue());
650}
651
652void ARMCodeEmitter::emitPseudoInstruction(const MachineInstr &MI) {
653  unsigned Opcode = MI.getDesc().Opcode;
654  switch (Opcode) {
655  default:
656    llvm_unreachable("ARMCodeEmitter::emitPseudoInstruction");
657  case ARM::BX:
658  case ARM::BMOVPCRX:
659  case ARM::BXr9:
660  case ARM::BMOVPCRXr9: {
661    // First emit mov lr, pc
662    unsigned Binary = 0x01a0e00f;
663    Binary |= II->getPredicate(&MI) << ARMII::CondShift;
664    emitWordLE(Binary);
665
666    // and then emit the branch.
667    emitMiscBranchInstruction(MI);
668    break;
669  }
670  case TargetOpcode::INLINEASM: {
671    // We allow inline assembler nodes with empty bodies - they can
672    // implicitly define registers, which is ok for JIT.
673    if (MI.getOperand(0).getSymbolName()[0]) {
674      report_fatal_error("JIT does not support inline asm!");
675    }
676    break;
677  }
678  case TargetOpcode::PROLOG_LABEL:
679  case TargetOpcode::EH_LABEL:
680    MCE.emitLabel(MI.getOperand(0).getMCSymbol());
681    break;
682  case TargetOpcode::IMPLICIT_DEF:
683  case TargetOpcode::KILL:
684    // Do nothing.
685    break;
686  case ARM::CONSTPOOL_ENTRY:
687    emitConstPoolInstruction(MI);
688    break;
689  case ARM::PICADD: {
690    // Remember of the address of the PC label for relocation later.
691    addPCLabel(MI.getOperand(2).getImm());
692    // PICADD is just an add instruction that implicitly read pc.
693    emitDataProcessingInstruction(MI, 0, ARM::PC);
694    break;
695  }
696  case ARM::PICLDR:
697  case ARM::PICLDRB:
698  case ARM::PICSTR:
699  case ARM::PICSTRB: {
700    // Remember of the address of the PC label for relocation later.
701    addPCLabel(MI.getOperand(2).getImm());
702    // These are just load / store instructions that implicitly read pc.
703    emitLoadStoreInstruction(MI, 0, ARM::PC);
704    break;
705  }
706  case ARM::PICLDRH:
707  case ARM::PICLDRSH:
708  case ARM::PICLDRSB:
709  case ARM::PICSTRH: {
710    // Remember of the address of the PC label for relocation later.
711    addPCLabel(MI.getOperand(2).getImm());
712    // These are just load / store instructions that implicitly read pc.
713    emitMiscLoadStoreInstruction(MI, ARM::PC);
714    break;
715  }
716
717  case ARM::MOVi32imm:
718    emitMOVi32immInstruction(MI);
719    break;
720
721  case ARM::MOVi2pieces:
722    // Two instructions to materialize a constant.
723    emitMOVi2piecesInstruction(MI);
724    break;
725  case ARM::LEApcrelJT:
726    // Materialize jumptable address.
727    emitLEApcrelJTInstruction(MI);
728    break;
729  case ARM::MOVrx:
730  case ARM::MOVsrl_flag:
731  case ARM::MOVsra_flag:
732    emitPseudoMoveInstruction(MI);
733    break;
734  }
735}
736
737unsigned ARMCodeEmitter::getMachineSoRegOpValue(const MachineInstr &MI,
738                                                const TargetInstrDesc &TID,
739                                                const MachineOperand &MO,
740                                                unsigned OpIdx) {
741  unsigned Binary = getMachineOpValue(MI, MO);
742
743  const MachineOperand &MO1 = MI.getOperand(OpIdx + 1);
744  const MachineOperand &MO2 = MI.getOperand(OpIdx + 2);
745  ARM_AM::ShiftOpc SOpc = ARM_AM::getSORegShOp(MO2.getImm());
746
747  // Encode the shift opcode.
748  unsigned SBits = 0;
749  unsigned Rs = MO1.getReg();
750  if (Rs) {
751    // Set shift operand (bit[7:4]).
752    // LSL - 0001
753    // LSR - 0011
754    // ASR - 0101
755    // ROR - 0111
756    // RRX - 0110 and bit[11:8] clear.
757    switch (SOpc) {
758    default: llvm_unreachable("Unknown shift opc!");
759    case ARM_AM::lsl: SBits = 0x1; break;
760    case ARM_AM::lsr: SBits = 0x3; break;
761    case ARM_AM::asr: SBits = 0x5; break;
762    case ARM_AM::ror: SBits = 0x7; break;
763    case ARM_AM::rrx: SBits = 0x6; break;
764    }
765  } else {
766    // Set shift operand (bit[6:4]).
767    // LSL - 000
768    // LSR - 010
769    // ASR - 100
770    // ROR - 110
771    switch (SOpc) {
772    default: llvm_unreachable("Unknown shift opc!");
773    case ARM_AM::lsl: SBits = 0x0; break;
774    case ARM_AM::lsr: SBits = 0x2; break;
775    case ARM_AM::asr: SBits = 0x4; break;
776    case ARM_AM::ror: SBits = 0x6; break;
777    }
778  }
779  Binary |= SBits << 4;
780  if (SOpc == ARM_AM::rrx)
781    return Binary;
782
783  // Encode the shift operation Rs or shift_imm (except rrx).
784  if (Rs) {
785    // Encode Rs bit[11:8].
786    assert(ARM_AM::getSORegOffset(MO2.getImm()) == 0);
787    return Binary |
788      (ARMRegisterInfo::getRegisterNumbering(Rs) << ARMII::RegRsShift);
789  }
790
791  // Encode shift_imm bit[11:7].
792  return Binary | ARM_AM::getSORegOffset(MO2.getImm()) << 7;
793}
794
795unsigned ARMCodeEmitter::getMachineSoImmOpValue(unsigned SoImm) {
796  int SoImmVal = ARM_AM::getSOImmVal(SoImm);
797  assert(SoImmVal != -1 && "Not a valid so_imm value!");
798
799  // Encode rotate_imm.
800  unsigned Binary = (ARM_AM::getSOImmValRot((unsigned)SoImmVal) >> 1)
801    << ARMII::SoRotImmShift;
802
803  // Encode immed_8.
804  Binary |= ARM_AM::getSOImmValImm((unsigned)SoImmVal);
805  return Binary;
806}
807
808unsigned ARMCodeEmitter::getAddrModeSBit(const MachineInstr &MI,
809                                         const TargetInstrDesc &TID) const {
810  for (unsigned i = MI.getNumOperands(), e = TID.getNumOperands(); i != e; --i){
811    const MachineOperand &MO = MI.getOperand(i-1);
812    if (MO.isReg() && MO.isDef() && MO.getReg() == ARM::CPSR)
813      return 1 << ARMII::S_BitShift;
814  }
815  return 0;
816}
817
818void ARMCodeEmitter::emitDataProcessingInstruction(const MachineInstr &MI,
819                                                   unsigned ImplicitRd,
820                                                   unsigned ImplicitRn) {
821  const TargetInstrDesc &TID = MI.getDesc();
822
823  // Part of binary is determined by TableGn.
824  unsigned Binary = getBinaryCodeForInstr(MI);
825
826  // Set the conditional execution predicate
827  Binary |= II->getPredicate(&MI) << ARMII::CondShift;
828
829  // Encode S bit if MI modifies CPSR.
830  Binary |= getAddrModeSBit(MI, TID);
831
832  // Encode register def if there is one.
833  unsigned NumDefs = TID.getNumDefs();
834  unsigned OpIdx = 0;
835  if (NumDefs)
836    Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRdShift;
837  else if (ImplicitRd)
838    // Special handling for implicit use (e.g. PC).
839    Binary |= (ARMRegisterInfo::getRegisterNumbering(ImplicitRd)
840               << ARMII::RegRdShift);
841
842  if (TID.Opcode == ARM::MOVi16) {
843      // Get immediate from MI.
844      unsigned Lo16 = getMovi32Value(MI, MI.getOperand(OpIdx),
845                      ARM::reloc_arm_movw);
846      // Encode imm which is the same as in emitMOVi32immInstruction().
847      Binary |= Lo16 & 0xFFF;
848      Binary |= ((Lo16 >> 12) & 0xF) << 16;
849      emitWordLE(Binary);
850      return;
851  } else if(TID.Opcode == ARM::MOVTi16) {
852      unsigned Hi16 = (getMovi32Value(MI, MI.getOperand(OpIdx),
853                       ARM::reloc_arm_movt) >> 16);
854      Binary |= Hi16 & 0xFFF;
855      Binary |= ((Hi16 >> 12) & 0xF) << 16;
856      emitWordLE(Binary);
857      return;
858  } else if ((TID.Opcode == ARM::BFC) || (TID.Opcode == ARM::BFI)) {
859      uint32_t v = ~MI.getOperand(2).getImm();
860      int32_t lsb = CountTrailingZeros_32(v);
861      int32_t msb = (32 - CountLeadingZeros_32(v)) - 1;
862      // Instr{20-16} = msb, Instr{11-7} = lsb
863      Binary |= (msb & 0x1F) << 16;
864      Binary |= (lsb & 0x1F) << 7;
865      emitWordLE(Binary);
866      return;
867  } else if ((TID.Opcode == ARM::UBFX) || (TID.Opcode == ARM::SBFX)) {
868      // Encode Rn in Instr{0-3}
869      Binary |= getMachineOpValue(MI, OpIdx++);
870
871      uint32_t lsb = MI.getOperand(OpIdx++).getImm();
872      uint32_t widthm1 = MI.getOperand(OpIdx++).getImm() - 1;
873
874      // Instr{20-16} = widthm1, Instr{11-7} = lsb
875      Binary |= (widthm1 & 0x1F) << 16;
876      Binary |= (lsb & 0x1F) << 7;
877      emitWordLE(Binary);
878      return;
879  }
880
881  // If this is a two-address operand, skip it. e.g. MOVCCr operand 1.
882  if (TID.getOperandConstraint(OpIdx, TOI::TIED_TO) != -1)
883    ++OpIdx;
884
885  // Encode first non-shifter register operand if there is one.
886  bool isUnary = TID.TSFlags & ARMII::UnaryDP;
887  if (!isUnary) {
888    if (ImplicitRn)
889      // Special handling for implicit use (e.g. PC).
890      Binary |= (ARMRegisterInfo::getRegisterNumbering(ImplicitRn)
891                 << ARMII::RegRnShift);
892    else {
893      Binary |= getMachineOpValue(MI, OpIdx) << ARMII::RegRnShift;
894      ++OpIdx;
895    }
896  }
897
898  // Encode shifter operand.
899  const MachineOperand &MO = MI.getOperand(OpIdx);
900  if ((TID.TSFlags & ARMII::FormMask) == ARMII::DPSoRegFrm) {
901    // Encode SoReg.
902    emitWordLE(Binary | getMachineSoRegOpValue(MI, TID, MO, OpIdx));
903    return;
904  }
905
906  if (MO.isReg()) {
907    // Encode register Rm.
908    emitWordLE(Binary | ARMRegisterInfo::getRegisterNumbering(MO.getReg()));
909    return;
910  }
911
912  // Encode so_imm.
913  Binary |= getMachineSoImmOpValue((unsigned)MO.getImm());
914
915  emitWordLE(Binary);
916}
917
918void ARMCodeEmitter::emitLoadStoreInstruction(const MachineInstr &MI,
919                                              unsigned ImplicitRd,
920                                              unsigned ImplicitRn) {
921  const TargetInstrDesc &TID = MI.getDesc();
922  unsigned Form = TID.TSFlags & ARMII::FormMask;
923  bool IsPrePost = (TID.TSFlags & ARMII::IndexModeMask) != 0;
924
925  // Part of binary is determined by TableGn.
926  unsigned Binary = getBinaryCodeForInstr(MI);
927
928  // Set the conditional execution predicate
929  Binary |= II->getPredicate(&MI) << ARMII::CondShift;
930
931  unsigned OpIdx = 0;
932
933  // Operand 0 of a pre- and post-indexed store is the address base
934  // writeback. Skip it.
935  bool Skipped = false;
936  if (IsPrePost && Form == ARMII::StFrm) {
937    ++OpIdx;
938    Skipped = true;
939  }
940
941  // Set first operand
942  if (ImplicitRd)
943    // Special handling for implicit use (e.g. PC).
944    Binary |= (ARMRegisterInfo::getRegisterNumbering(ImplicitRd)
945               << ARMII::RegRdShift);
946  else
947    Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRdShift;
948
949  // Set second operand
950  if (ImplicitRn)
951    // Special handling for implicit use (e.g. PC).
952    Binary |= (ARMRegisterInfo::getRegisterNumbering(ImplicitRn)
953               << ARMII::RegRnShift);
954  else
955    Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRnShift;
956
957  // If this is a two-address operand, skip it. e.g. LDR_PRE.
958  if (!Skipped && TID.getOperandConstraint(OpIdx, TOI::TIED_TO) != -1)
959    ++OpIdx;
960
961  const MachineOperand &MO2 = MI.getOperand(OpIdx);
962  unsigned AM2Opc = (ImplicitRn == ARM::PC)
963    ? 0 : MI.getOperand(OpIdx+1).getImm();
964
965  // Set bit U(23) according to sign of immed value (positive or negative).
966  Binary |= ((ARM_AM::getAM2Op(AM2Opc) == ARM_AM::add ? 1 : 0) <<
967             ARMII::U_BitShift);
968  if (!MO2.getReg()) { // is immediate
969    if (ARM_AM::getAM2Offset(AM2Opc))
970      // Set the value of offset_12 field
971      Binary |= ARM_AM::getAM2Offset(AM2Opc);
972    emitWordLE(Binary);
973    return;
974  }
975
976  // Set bit I(25), because this is not in immediate enconding.
977  Binary |= 1 << ARMII::I_BitShift;
978  assert(TargetRegisterInfo::isPhysicalRegister(MO2.getReg()));
979  // Set bit[3:0] to the corresponding Rm register
980  Binary |= ARMRegisterInfo::getRegisterNumbering(MO2.getReg());
981
982  // If this instr is in scaled register offset/index instruction, set
983  // shift_immed(bit[11:7]) and shift(bit[6:5]) fields.
984  if (unsigned ShImm = ARM_AM::getAM2Offset(AM2Opc)) {
985    Binary |= getShiftOp(AM2Opc) << ARMII::ShiftImmShift;  // shift
986    Binary |= ShImm              << ARMII::ShiftShift;     // shift_immed
987  }
988
989  emitWordLE(Binary);
990}
991
992void ARMCodeEmitter::emitMiscLoadStoreInstruction(const MachineInstr &MI,
993                                                  unsigned ImplicitRn) {
994  const TargetInstrDesc &TID = MI.getDesc();
995  unsigned Form = TID.TSFlags & ARMII::FormMask;
996  bool IsPrePost = (TID.TSFlags & ARMII::IndexModeMask) != 0;
997
998  // Part of binary is determined by TableGn.
999  unsigned Binary = getBinaryCodeForInstr(MI);
1000
1001  // Set the conditional execution predicate
1002  Binary |= II->getPredicate(&MI) << ARMII::CondShift;
1003
1004  unsigned OpIdx = 0;
1005
1006  // Operand 0 of a pre- and post-indexed store is the address base
1007  // writeback. Skip it.
1008  bool Skipped = false;
1009  if (IsPrePost && Form == ARMII::StMiscFrm) {
1010    ++OpIdx;
1011    Skipped = true;
1012  }
1013
1014  // Set first operand
1015  Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRdShift;
1016
1017  // Skip LDRD and STRD's second operand.
1018  if (TID.Opcode == ARM::LDRD || TID.Opcode == ARM::STRD)
1019    ++OpIdx;
1020
1021  // Set second operand
1022  if (ImplicitRn)
1023    // Special handling for implicit use (e.g. PC).
1024    Binary |= (ARMRegisterInfo::getRegisterNumbering(ImplicitRn)
1025               << ARMII::RegRnShift);
1026  else
1027    Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRnShift;
1028
1029  // If this is a two-address operand, skip it. e.g. LDRH_POST.
1030  if (!Skipped && TID.getOperandConstraint(OpIdx, TOI::TIED_TO) != -1)
1031    ++OpIdx;
1032
1033  const MachineOperand &MO2 = MI.getOperand(OpIdx);
1034  unsigned AM3Opc = (ImplicitRn == ARM::PC)
1035    ? 0 : MI.getOperand(OpIdx+1).getImm();
1036
1037  // Set bit U(23) according to sign of immed value (positive or negative)
1038  Binary |= ((ARM_AM::getAM3Op(AM3Opc) == ARM_AM::add ? 1 : 0) <<
1039             ARMII::U_BitShift);
1040
1041  // If this instr is in register offset/index encoding, set bit[3:0]
1042  // to the corresponding Rm register.
1043  if (MO2.getReg()) {
1044    Binary |= ARMRegisterInfo::getRegisterNumbering(MO2.getReg());
1045    emitWordLE(Binary);
1046    return;
1047  }
1048
1049  // This instr is in immediate offset/index encoding, set bit 22 to 1.
1050  Binary |= 1 << ARMII::AM3_I_BitShift;
1051  if (unsigned ImmOffs = ARM_AM::getAM3Offset(AM3Opc)) {
1052    // Set operands
1053    Binary |= (ImmOffs >> 4) << ARMII::ImmHiShift;  // immedH
1054    Binary |= (ImmOffs & 0xF);                      // immedL
1055  }
1056
1057  emitWordLE(Binary);
1058}
1059
1060static unsigned getAddrModeUPBits(unsigned Mode) {
1061  unsigned Binary = 0;
1062
1063  // Set addressing mode by modifying bits U(23) and P(24)
1064  // IA - Increment after  - bit U = 1 and bit P = 0
1065  // IB - Increment before - bit U = 1 and bit P = 1
1066  // DA - Decrement after  - bit U = 0 and bit P = 0
1067  // DB - Decrement before - bit U = 0 and bit P = 1
1068  switch (Mode) {
1069  default: llvm_unreachable("Unknown addressing sub-mode!");
1070  case ARM_AM::da:                                     break;
1071  case ARM_AM::db: Binary |= 0x1 << ARMII::P_BitShift; break;
1072  case ARM_AM::ia: Binary |= 0x1 << ARMII::U_BitShift; break;
1073  case ARM_AM::ib: Binary |= 0x3 << ARMII::U_BitShift; break;
1074  }
1075
1076  return Binary;
1077}
1078
1079void ARMCodeEmitter::emitLoadStoreMultipleInstruction(const MachineInstr &MI) {
1080  const TargetInstrDesc &TID = MI.getDesc();
1081  bool IsUpdating = (TID.TSFlags & ARMII::IndexModeMask) != 0;
1082
1083  // Part of binary is determined by TableGn.
1084  unsigned Binary = getBinaryCodeForInstr(MI);
1085
1086  // Set the conditional execution predicate
1087  Binary |= II->getPredicate(&MI) << ARMII::CondShift;
1088
1089  // Skip operand 0 of an instruction with base register update.
1090  unsigned OpIdx = 0;
1091  if (IsUpdating)
1092    ++OpIdx;
1093
1094  // Set base address operand
1095  Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRnShift;
1096
1097  // Set addressing mode by modifying bits U(23) and P(24)
1098  const MachineOperand &MO = MI.getOperand(OpIdx++);
1099  Binary |= getAddrModeUPBits(ARM_AM::getAM4SubMode(MO.getImm()));
1100
1101  // Set bit W(21)
1102  if (IsUpdating)
1103    Binary |= 0x1 << ARMII::W_BitShift;
1104
1105  // Set registers
1106  for (unsigned i = OpIdx+2, e = MI.getNumOperands(); i != e; ++i) {
1107    const MachineOperand &MO = MI.getOperand(i);
1108    if (!MO.isReg() || MO.isImplicit())
1109      break;
1110    unsigned RegNum = ARMRegisterInfo::getRegisterNumbering(MO.getReg());
1111    assert(TargetRegisterInfo::isPhysicalRegister(MO.getReg()) &&
1112           RegNum < 16);
1113    Binary |= 0x1 << RegNum;
1114  }
1115
1116  emitWordLE(Binary);
1117}
1118
1119void ARMCodeEmitter::emitMulFrmInstruction(const MachineInstr &MI) {
1120  const TargetInstrDesc &TID = MI.getDesc();
1121
1122  // Part of binary is determined by TableGn.
1123  unsigned Binary = getBinaryCodeForInstr(MI);
1124
1125  // Set the conditional execution predicate
1126  Binary |= II->getPredicate(&MI) << ARMII::CondShift;
1127
1128  // Encode S bit if MI modifies CPSR.
1129  Binary |= getAddrModeSBit(MI, TID);
1130
1131  // 32x32->64bit operations have two destination registers. The number
1132  // of register definitions will tell us if that's what we're dealing with.
1133  unsigned OpIdx = 0;
1134  if (TID.getNumDefs() == 2)
1135    Binary |= getMachineOpValue (MI, OpIdx++) << ARMII::RegRdLoShift;
1136
1137  // Encode Rd
1138  Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRdHiShift;
1139
1140  // Encode Rm
1141  Binary |= getMachineOpValue(MI, OpIdx++);
1142
1143  // Encode Rs
1144  Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRsShift;
1145
1146  // Many multiple instructions (e.g. MLA) have three src operands. Encode
1147  // it as Rn (for multiply, that's in the same offset as RdLo.
1148  if (TID.getNumOperands() > OpIdx &&
1149      !TID.OpInfo[OpIdx].isPredicate() &&
1150      !TID.OpInfo[OpIdx].isOptionalDef())
1151    Binary |= getMachineOpValue(MI, OpIdx) << ARMII::RegRdLoShift;
1152
1153  emitWordLE(Binary);
1154}
1155
1156void ARMCodeEmitter::emitExtendInstruction(const MachineInstr &MI) {
1157  const TargetInstrDesc &TID = MI.getDesc();
1158
1159  // Part of binary is determined by TableGn.
1160  unsigned Binary = getBinaryCodeForInstr(MI);
1161
1162  // Set the conditional execution predicate
1163  Binary |= II->getPredicate(&MI) << ARMII::CondShift;
1164
1165  unsigned OpIdx = 0;
1166
1167  // Encode Rd
1168  Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRdShift;
1169
1170  const MachineOperand &MO1 = MI.getOperand(OpIdx++);
1171  const MachineOperand &MO2 = MI.getOperand(OpIdx);
1172  if (MO2.isReg()) {
1173    // Two register operand form.
1174    // Encode Rn.
1175    Binary |= getMachineOpValue(MI, MO1) << ARMII::RegRnShift;
1176
1177    // Encode Rm.
1178    Binary |= getMachineOpValue(MI, MO2);
1179    ++OpIdx;
1180  } else {
1181    Binary |= getMachineOpValue(MI, MO1);
1182  }
1183
1184  // Encode rot imm (0, 8, 16, or 24) if it has a rotate immediate operand.
1185  if (MI.getOperand(OpIdx).isImm() &&
1186      !TID.OpInfo[OpIdx].isPredicate() &&
1187      !TID.OpInfo[OpIdx].isOptionalDef())
1188    Binary |= (getMachineOpValue(MI, OpIdx) / 8) << ARMII::ExtRotImmShift;
1189
1190  emitWordLE(Binary);
1191}
1192
1193void ARMCodeEmitter::emitMiscArithInstruction(const MachineInstr &MI) {
1194  const TargetInstrDesc &TID = MI.getDesc();
1195
1196  // Part of binary is determined by TableGn.
1197  unsigned Binary = getBinaryCodeForInstr(MI);
1198
1199  // Set the conditional execution predicate
1200  Binary |= II->getPredicate(&MI) << ARMII::CondShift;
1201
1202  unsigned OpIdx = 0;
1203
1204  // Encode Rd
1205  Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRdShift;
1206
1207  const MachineOperand &MO = MI.getOperand(OpIdx++);
1208  if (OpIdx == TID.getNumOperands() ||
1209      TID.OpInfo[OpIdx].isPredicate() ||
1210      TID.OpInfo[OpIdx].isOptionalDef()) {
1211    // Encode Rm and it's done.
1212    Binary |= getMachineOpValue(MI, MO);
1213    emitWordLE(Binary);
1214    return;
1215  }
1216
1217  // Encode Rn.
1218  Binary |= getMachineOpValue(MI, MO) << ARMII::RegRnShift;
1219
1220  // Encode Rm.
1221  Binary |= getMachineOpValue(MI, OpIdx++);
1222
1223  // Encode shift_imm.
1224  unsigned ShiftAmt = MI.getOperand(OpIdx).getImm();
1225  assert(ShiftAmt < 32 && "shift_imm range is 0 to 31!");
1226  Binary |= ShiftAmt << ARMII::ShiftShift;
1227
1228  emitWordLE(Binary);
1229}
1230
1231void ARMCodeEmitter::emitBranchInstruction(const MachineInstr &MI) {
1232  const TargetInstrDesc &TID = MI.getDesc();
1233
1234  if (TID.Opcode == ARM::TPsoft) {
1235    llvm_unreachable("ARM::TPsoft FIXME"); // FIXME
1236  }
1237
1238  // Part of binary is determined by TableGn.
1239  unsigned Binary = getBinaryCodeForInstr(MI);
1240
1241  // Set the conditional execution predicate
1242  Binary |= II->getPredicate(&MI) << ARMII::CondShift;
1243
1244  // Set signed_immed_24 field
1245  Binary |= getMachineOpValue(MI, 0);
1246
1247  emitWordLE(Binary);
1248}
1249
1250void ARMCodeEmitter::emitInlineJumpTable(unsigned JTIndex) {
1251  // Remember the base address of the inline jump table.
1252  uintptr_t JTBase = MCE.getCurrentPCValue();
1253  JTI->addJumpTableBaseAddr(JTIndex, JTBase);
1254  DEBUG(errs() << "  ** Jump Table #" << JTIndex << " @ " << (void*)JTBase
1255               << '\n');
1256
1257  // Now emit the jump table entries.
1258  const std::vector<MachineBasicBlock*> &MBBs = (*MJTEs)[JTIndex].MBBs;
1259  for (unsigned i = 0, e = MBBs.size(); i != e; ++i) {
1260    if (IsPIC)
1261      // DestBB address - JT base.
1262      emitMachineBasicBlock(MBBs[i], ARM::reloc_arm_pic_jt, JTBase);
1263    else
1264      // Absolute DestBB address.
1265      emitMachineBasicBlock(MBBs[i], ARM::reloc_arm_absolute);
1266    emitWordLE(0);
1267  }
1268}
1269
1270void ARMCodeEmitter::emitMiscBranchInstruction(const MachineInstr &MI) {
1271  const TargetInstrDesc &TID = MI.getDesc();
1272
1273  // Handle jump tables.
1274  if (TID.Opcode == ARM::BR_JTr || TID.Opcode == ARM::BR_JTadd) {
1275    // First emit a ldr pc, [] instruction.
1276    emitDataProcessingInstruction(MI, ARM::PC);
1277
1278    // Then emit the inline jump table.
1279    unsigned JTIndex =
1280      (TID.Opcode == ARM::BR_JTr)
1281      ? MI.getOperand(1).getIndex() : MI.getOperand(2).getIndex();
1282    emitInlineJumpTable(JTIndex);
1283    return;
1284  } else if (TID.Opcode == ARM::BR_JTm) {
1285    // First emit a ldr pc, [] instruction.
1286    emitLoadStoreInstruction(MI, ARM::PC);
1287
1288    // Then emit the inline jump table.
1289    emitInlineJumpTable(MI.getOperand(3).getIndex());
1290    return;
1291  }
1292
1293  // Part of binary is determined by TableGn.
1294  unsigned Binary = getBinaryCodeForInstr(MI);
1295
1296  // Set the conditional execution predicate
1297  Binary |= II->getPredicate(&MI) << ARMII::CondShift;
1298
1299  if (TID.Opcode == ARM::BX_RET || TID.Opcode == ARM::MOVPCLR)
1300    // The return register is LR.
1301    Binary |= ARMRegisterInfo::getRegisterNumbering(ARM::LR);
1302  else
1303    // otherwise, set the return register
1304    Binary |= getMachineOpValue(MI, 0);
1305
1306  emitWordLE(Binary);
1307}
1308
1309static unsigned encodeVFPRd(const MachineInstr &MI, unsigned OpIdx) {
1310  unsigned RegD = MI.getOperand(OpIdx).getReg();
1311  unsigned Binary = 0;
1312  bool isSPVFP = false;
1313  RegD = ARMRegisterInfo::getRegisterNumbering(RegD, &isSPVFP);
1314  if (!isSPVFP)
1315    Binary |=   RegD               << ARMII::RegRdShift;
1316  else {
1317    Binary |= ((RegD & 0x1E) >> 1) << ARMII::RegRdShift;
1318    Binary |=  (RegD & 0x01)       << ARMII::D_BitShift;
1319  }
1320  return Binary;
1321}
1322
1323static unsigned encodeVFPRn(const MachineInstr &MI, unsigned OpIdx) {
1324  unsigned RegN = MI.getOperand(OpIdx).getReg();
1325  unsigned Binary = 0;
1326  bool isSPVFP = false;
1327  RegN = ARMRegisterInfo::getRegisterNumbering(RegN, &isSPVFP);
1328  if (!isSPVFP)
1329    Binary |=   RegN               << ARMII::RegRnShift;
1330  else {
1331    Binary |= ((RegN & 0x1E) >> 1) << ARMII::RegRnShift;
1332    Binary |=  (RegN & 0x01)       << ARMII::N_BitShift;
1333  }
1334  return Binary;
1335}
1336
1337static unsigned encodeVFPRm(const MachineInstr &MI, unsigned OpIdx) {
1338  unsigned RegM = MI.getOperand(OpIdx).getReg();
1339  unsigned Binary = 0;
1340  bool isSPVFP = false;
1341  RegM = ARMRegisterInfo::getRegisterNumbering(RegM, &isSPVFP);
1342  if (!isSPVFP)
1343    Binary |=   RegM;
1344  else {
1345    Binary |= ((RegM & 0x1E) >> 1);
1346    Binary |=  (RegM & 0x01)       << ARMII::M_BitShift;
1347  }
1348  return Binary;
1349}
1350
1351void ARMCodeEmitter::emitVFPArithInstruction(const MachineInstr &MI) {
1352  const TargetInstrDesc &TID = MI.getDesc();
1353
1354  // Part of binary is determined by TableGn.
1355  unsigned Binary = getBinaryCodeForInstr(MI);
1356
1357  // Set the conditional execution predicate
1358  Binary |= II->getPredicate(&MI) << ARMII::CondShift;
1359
1360  unsigned OpIdx = 0;
1361  assert((Binary & ARMII::D_BitShift) == 0 &&
1362         (Binary & ARMII::N_BitShift) == 0 &&
1363         (Binary & ARMII::M_BitShift) == 0 && "VFP encoding bug!");
1364
1365  // Encode Dd / Sd.
1366  Binary |= encodeVFPRd(MI, OpIdx++);
1367
1368  // If this is a two-address operand, skip it, e.g. FMACD.
1369  if (TID.getOperandConstraint(OpIdx, TOI::TIED_TO) != -1)
1370    ++OpIdx;
1371
1372  // Encode Dn / Sn.
1373  if ((TID.TSFlags & ARMII::FormMask) == ARMII::VFPBinaryFrm)
1374    Binary |= encodeVFPRn(MI, OpIdx++);
1375
1376  if (OpIdx == TID.getNumOperands() ||
1377      TID.OpInfo[OpIdx].isPredicate() ||
1378      TID.OpInfo[OpIdx].isOptionalDef()) {
1379    // FCMPEZD etc. has only one operand.
1380    emitWordLE(Binary);
1381    return;
1382  }
1383
1384  // Encode Dm / Sm.
1385  Binary |= encodeVFPRm(MI, OpIdx);
1386
1387  emitWordLE(Binary);
1388}
1389
1390void ARMCodeEmitter::emitVFPConversionInstruction(const MachineInstr &MI) {
1391  const TargetInstrDesc &TID = MI.getDesc();
1392  unsigned Form = TID.TSFlags & ARMII::FormMask;
1393
1394  // Part of binary is determined by TableGn.
1395  unsigned Binary = getBinaryCodeForInstr(MI);
1396
1397  // Set the conditional execution predicate
1398  Binary |= II->getPredicate(&MI) << ARMII::CondShift;
1399
1400  switch (Form) {
1401  default: break;
1402  case ARMII::VFPConv1Frm:
1403  case ARMII::VFPConv2Frm:
1404  case ARMII::VFPConv3Frm:
1405    // Encode Dd / Sd.
1406    Binary |= encodeVFPRd(MI, 0);
1407    break;
1408  case ARMII::VFPConv4Frm:
1409    // Encode Dn / Sn.
1410    Binary |= encodeVFPRn(MI, 0);
1411    break;
1412  case ARMII::VFPConv5Frm:
1413    // Encode Dm / Sm.
1414    Binary |= encodeVFPRm(MI, 0);
1415    break;
1416  }
1417
1418  switch (Form) {
1419  default: break;
1420  case ARMII::VFPConv1Frm:
1421    // Encode Dm / Sm.
1422    Binary |= encodeVFPRm(MI, 1);
1423    break;
1424  case ARMII::VFPConv2Frm:
1425  case ARMII::VFPConv3Frm:
1426    // Encode Dn / Sn.
1427    Binary |= encodeVFPRn(MI, 1);
1428    break;
1429  case ARMII::VFPConv4Frm:
1430  case ARMII::VFPConv5Frm:
1431    // Encode Dd / Sd.
1432    Binary |= encodeVFPRd(MI, 1);
1433    break;
1434  }
1435
1436  if (Form == ARMII::VFPConv5Frm)
1437    // Encode Dn / Sn.
1438    Binary |= encodeVFPRn(MI, 2);
1439  else if (Form == ARMII::VFPConv3Frm)
1440    // Encode Dm / Sm.
1441    Binary |= encodeVFPRm(MI, 2);
1442
1443  emitWordLE(Binary);
1444}
1445
1446void ARMCodeEmitter::emitVFPLoadStoreInstruction(const MachineInstr &MI) {
1447  // Part of binary is determined by TableGn.
1448  unsigned Binary = getBinaryCodeForInstr(MI);
1449
1450  // Set the conditional execution predicate
1451  Binary |= II->getPredicate(&MI) << ARMII::CondShift;
1452
1453  unsigned OpIdx = 0;
1454
1455  // Encode Dd / Sd.
1456  Binary |= encodeVFPRd(MI, OpIdx++);
1457
1458  // Encode address base.
1459  const MachineOperand &Base = MI.getOperand(OpIdx++);
1460  Binary |= getMachineOpValue(MI, Base) << ARMII::RegRnShift;
1461
1462  // If there is a non-zero immediate offset, encode it.
1463  if (Base.isReg()) {
1464    const MachineOperand &Offset = MI.getOperand(OpIdx);
1465    if (unsigned ImmOffs = ARM_AM::getAM5Offset(Offset.getImm())) {
1466      if (ARM_AM::getAM5Op(Offset.getImm()) == ARM_AM::add)
1467        Binary |= 1 << ARMII::U_BitShift;
1468      Binary |= ImmOffs;
1469      emitWordLE(Binary);
1470      return;
1471    }
1472  }
1473
1474  // If immediate offset is omitted, default to +0.
1475  Binary |= 1 << ARMII::U_BitShift;
1476
1477  emitWordLE(Binary);
1478}
1479
1480void
1481ARMCodeEmitter::emitVFPLoadStoreMultipleInstruction(const MachineInstr &MI) {
1482  const TargetInstrDesc &TID = MI.getDesc();
1483  bool IsUpdating = (TID.TSFlags & ARMII::IndexModeMask) != 0;
1484
1485  // Part of binary is determined by TableGn.
1486  unsigned Binary = getBinaryCodeForInstr(MI);
1487
1488  // Set the conditional execution predicate
1489  Binary |= II->getPredicate(&MI) << ARMII::CondShift;
1490
1491  // Skip operand 0 of an instruction with base register update.
1492  unsigned OpIdx = 0;
1493  if (IsUpdating)
1494    ++OpIdx;
1495
1496  // Set base address operand
1497  Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRnShift;
1498
1499  // Set addressing mode by modifying bits U(23) and P(24)
1500  const MachineOperand &MO = MI.getOperand(OpIdx++);
1501  Binary |= getAddrModeUPBits(ARM_AM::getAM5SubMode(MO.getImm()));
1502
1503  // Set bit W(21)
1504  if (IsUpdating)
1505    Binary |= 0x1 << ARMII::W_BitShift;
1506
1507  // First register is encoded in Dd.
1508  Binary |= encodeVFPRd(MI, OpIdx+2);
1509
1510  // Number of registers are encoded in offset field.
1511  unsigned NumRegs = 1;
1512  for (unsigned i = OpIdx+3, e = MI.getNumOperands(); i != e; ++i) {
1513    const MachineOperand &MO = MI.getOperand(i);
1514    if (!MO.isReg() || MO.isImplicit())
1515      break;
1516    ++NumRegs;
1517  }
1518  // Bit 8 will be set if <list> is consecutive 64-bit registers (e.g., D0)
1519  // Otherwise, it will be 0, in the case of 32-bit registers.
1520  if(Binary & 0x100)
1521    Binary |= NumRegs * 2;
1522  else
1523    Binary |= NumRegs;
1524
1525  emitWordLE(Binary);
1526}
1527
1528void ARMCodeEmitter::emitMiscInstruction(const MachineInstr &MI) {
1529  unsigned Opcode = MI.getDesc().Opcode;
1530  // Part of binary is determined by TableGn.
1531  unsigned Binary = getBinaryCodeForInstr(MI);
1532
1533  // Set the conditional execution predicate
1534  Binary |= II->getPredicate(&MI) << ARMII::CondShift;
1535
1536  switch(Opcode) {
1537  default:
1538    llvm_unreachable("ARMCodeEmitter::emitMiscInstruction");
1539
1540  case ARM::FMSTAT:
1541    // No further encoding needed.
1542    break;
1543
1544  case ARM::VMRS:
1545  case ARM::VMSR: {
1546    const MachineOperand &MO0 = MI.getOperand(0);
1547    // Encode Rt.
1548    Binary |= ARMRegisterInfo::getRegisterNumbering(MO0.getReg())
1549                << ARMII::RegRdShift;
1550    break;
1551  }
1552
1553  case ARM::FCONSTD:
1554  case ARM::FCONSTS: {
1555    // Encode Dd / Sd.
1556    Binary |= encodeVFPRd(MI, 0);
1557
1558    // Encode imm., Table A7-18 VFP modified immediate constants
1559    const MachineOperand &MO1 = MI.getOperand(1);
1560    unsigned Imm = static_cast<unsigned>(MO1.getFPImm()->getValueAPF()
1561                      .bitcastToAPInt().getHiBits(32).getLimitedValue());
1562    unsigned ModifiedImm;
1563
1564    if(Opcode == ARM::FCONSTS)
1565      ModifiedImm = (Imm & 0x80000000) >> 24 | // a
1566                    (Imm & 0x03F80000) >> 19;  // bcdefgh
1567    else // Opcode == ARM::FCONSTD
1568      ModifiedImm = (Imm & 0x80000000) >> 24 | // a
1569                    (Imm & 0x007F0000) >> 16;  // bcdefgh
1570
1571    // Insts{19-16} = abcd, Insts{3-0} = efgh
1572    Binary |= ((ModifiedImm & 0xF0) >> 4) << 16;
1573    Binary |= (ModifiedImm & 0xF);
1574    break;
1575  }
1576  }
1577
1578  emitWordLE(Binary);
1579}
1580
1581static unsigned encodeNEONRd(const MachineInstr &MI, unsigned OpIdx) {
1582  unsigned RegD = MI.getOperand(OpIdx).getReg();
1583  unsigned Binary = 0;
1584  RegD = ARMRegisterInfo::getRegisterNumbering(RegD);
1585  Binary |= (RegD & 0xf) << ARMII::RegRdShift;
1586  Binary |= ((RegD >> 4) & 1) << ARMII::D_BitShift;
1587  return Binary;
1588}
1589
1590static unsigned encodeNEONRn(const MachineInstr &MI, unsigned OpIdx) {
1591  unsigned RegN = MI.getOperand(OpIdx).getReg();
1592  unsigned Binary = 0;
1593  RegN = ARMRegisterInfo::getRegisterNumbering(RegN);
1594  Binary |= (RegN & 0xf) << ARMII::RegRnShift;
1595  Binary |= ((RegN >> 4) & 1) << ARMII::N_BitShift;
1596  return Binary;
1597}
1598
1599static unsigned encodeNEONRm(const MachineInstr &MI, unsigned OpIdx) {
1600  unsigned RegM = MI.getOperand(OpIdx).getReg();
1601  unsigned Binary = 0;
1602  RegM = ARMRegisterInfo::getRegisterNumbering(RegM);
1603  Binary |= (RegM & 0xf);
1604  Binary |= ((RegM >> 4) & 1) << ARMII::M_BitShift;
1605  return Binary;
1606}
1607
1608/// convertNEONDataProcToThumb - Convert the ARM mode encoding for a NEON
1609/// data-processing instruction to the corresponding Thumb encoding.
1610static unsigned convertNEONDataProcToThumb(unsigned Binary) {
1611  assert((Binary & 0xfe000000) == 0xf2000000 &&
1612         "not an ARM NEON data-processing instruction");
1613  unsigned UBit = (Binary >> 24) & 1;
1614  return 0xef000000 | (UBit << 28) | (Binary & 0xffffff);
1615}
1616
1617void ARMCodeEmitter::emitNEONLaneInstruction(const MachineInstr &MI) {
1618  unsigned Binary = getBinaryCodeForInstr(MI);
1619
1620  unsigned RegTOpIdx, RegNOpIdx, LnOpIdx;
1621  const TargetInstrDesc &TID = MI.getDesc();
1622  if ((TID.TSFlags & ARMII::FormMask) == ARMII::NGetLnFrm) {
1623    RegTOpIdx = 0;
1624    RegNOpIdx = 1;
1625    LnOpIdx = 2;
1626  } else { // ARMII::NSetLnFrm
1627    RegTOpIdx = 2;
1628    RegNOpIdx = 0;
1629    LnOpIdx = 3;
1630  }
1631
1632  // Set the conditional execution predicate
1633  Binary |= (IsThumb ? ARMCC::AL : II->getPredicate(&MI)) << ARMII::CondShift;
1634
1635  unsigned RegT = MI.getOperand(RegTOpIdx).getReg();
1636  RegT = ARMRegisterInfo::getRegisterNumbering(RegT);
1637  Binary |= (RegT << ARMII::RegRdShift);
1638  Binary |= encodeNEONRn(MI, RegNOpIdx);
1639
1640  unsigned LaneShift;
1641  if ((Binary & (1 << 22)) != 0)
1642    LaneShift = 0; // 8-bit elements
1643  else if ((Binary & (1 << 5)) != 0)
1644    LaneShift = 1; // 16-bit elements
1645  else
1646    LaneShift = 2; // 32-bit elements
1647
1648  unsigned Lane = MI.getOperand(LnOpIdx).getImm() << LaneShift;
1649  unsigned Opc1 = Lane >> 2;
1650  unsigned Opc2 = Lane & 3;
1651  assert((Opc1 & 3) == 0 && "out-of-range lane number operand");
1652  Binary |= (Opc1 << 21);
1653  Binary |= (Opc2 << 5);
1654
1655  emitWordLE(Binary);
1656}
1657
1658void ARMCodeEmitter::emitNEONDupInstruction(const MachineInstr &MI) {
1659  unsigned Binary = getBinaryCodeForInstr(MI);
1660
1661  // Set the conditional execution predicate
1662  Binary |= (IsThumb ? ARMCC::AL : II->getPredicate(&MI)) << ARMII::CondShift;
1663
1664  unsigned RegT = MI.getOperand(1).getReg();
1665  RegT = ARMRegisterInfo::getRegisterNumbering(RegT);
1666  Binary |= (RegT << ARMII::RegRdShift);
1667  Binary |= encodeNEONRn(MI, 0);
1668  emitWordLE(Binary);
1669}
1670
1671void ARMCodeEmitter::emitNEON1RegModImmInstruction(const MachineInstr &MI) {
1672  unsigned Binary = getBinaryCodeForInstr(MI);
1673  // Destination register is encoded in Dd.
1674  Binary |= encodeNEONRd(MI, 0);
1675  // Immediate fields: Op, Cmode, I, Imm3, Imm4
1676  unsigned Imm = MI.getOperand(1).getImm();
1677  unsigned Op = (Imm >> 12) & 1;
1678  unsigned Cmode = (Imm >> 8) & 0xf;
1679  unsigned I = (Imm >> 7) & 1;
1680  unsigned Imm3 = (Imm >> 4) & 0x7;
1681  unsigned Imm4 = Imm & 0xf;
1682  Binary |= (I << 24) | (Imm3 << 16) | (Cmode << 8) | (Op << 5) | Imm4;
1683  if (IsThumb)
1684    Binary = convertNEONDataProcToThumb(Binary);
1685  emitWordLE(Binary);
1686}
1687
1688void ARMCodeEmitter::emitNEON2RegInstruction(const MachineInstr &MI) {
1689  const TargetInstrDesc &TID = MI.getDesc();
1690  unsigned Binary = getBinaryCodeForInstr(MI);
1691  // Destination register is encoded in Dd; source register in Dm.
1692  unsigned OpIdx = 0;
1693  Binary |= encodeNEONRd(MI, OpIdx++);
1694  if (TID.getOperandConstraint(OpIdx, TOI::TIED_TO) != -1)
1695    ++OpIdx;
1696  Binary |= encodeNEONRm(MI, OpIdx);
1697  if (IsThumb)
1698    Binary = convertNEONDataProcToThumb(Binary);
1699  // FIXME: This does not handle VDUPfdf or VDUPfqf.
1700  emitWordLE(Binary);
1701}
1702
1703void ARMCodeEmitter::emitNEON3RegInstruction(const MachineInstr &MI) {
1704  const TargetInstrDesc &TID = MI.getDesc();
1705  unsigned Binary = getBinaryCodeForInstr(MI);
1706  // Destination register is encoded in Dd; source registers in Dn and Dm.
1707  unsigned OpIdx = 0;
1708  Binary |= encodeNEONRd(MI, OpIdx++);
1709  if (TID.getOperandConstraint(OpIdx, TOI::TIED_TO) != -1)
1710    ++OpIdx;
1711  Binary |= encodeNEONRn(MI, OpIdx++);
1712  if (TID.getOperandConstraint(OpIdx, TOI::TIED_TO) != -1)
1713    ++OpIdx;
1714  Binary |= encodeNEONRm(MI, OpIdx);
1715  if (IsThumb)
1716    Binary = convertNEONDataProcToThumb(Binary);
1717  // FIXME: This does not handle VMOVDneon or VMOVQ.
1718  emitWordLE(Binary);
1719}
1720
1721#include "ARMGenCodeEmitter.inc"
1722