ARMCodeEmitter.cpp revision 9d63d90de5e57ad96f467b270544443a9284eb2b
1//===-- ARM/ARMCodeEmitter.cpp - Convert ARM code to machine code ---------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file contains the pass that transforms the ARM machine instructions into 11// relocatable machine code. 12// 13//===----------------------------------------------------------------------===// 14 15#define DEBUG_TYPE "jit" 16#include "ARM.h" 17#include "ARMAddressingModes.h" 18#include "ARMConstantPoolValue.h" 19#include "ARMInstrInfo.h" 20#include "ARMRelocations.h" 21#include "ARMSubtarget.h" 22#include "ARMTargetMachine.h" 23#include "llvm/Constants.h" 24#include "llvm/DerivedTypes.h" 25#include "llvm/Function.h" 26#include "llvm/PassManager.h" 27#include "llvm/CodeGen/JITCodeEmitter.h" 28#include "llvm/CodeGen/MachineConstantPool.h" 29#include "llvm/CodeGen/MachineFunctionPass.h" 30#include "llvm/CodeGen/MachineInstr.h" 31#include "llvm/CodeGen/MachineJumpTableInfo.h" 32#include "llvm/CodeGen/MachineModuleInfo.h" 33#include "llvm/CodeGen/Passes.h" 34#include "llvm/ADT/Statistic.h" 35#include "llvm/Support/Debug.h" 36#include "llvm/Support/ErrorHandling.h" 37#include "llvm/Support/raw_ostream.h" 38#ifndef NDEBUG 39#include <iomanip> 40#endif 41using namespace llvm; 42 43STATISTIC(NumEmitted, "Number of machine instructions emitted"); 44 45namespace { 46 47 class ARMCodeEmitter : public MachineFunctionPass { 48 ARMJITInfo *JTI; 49 const ARMInstrInfo *II; 50 const TargetData *TD; 51 const ARMSubtarget *Subtarget; 52 TargetMachine &TM; 53 JITCodeEmitter &MCE; 54 MachineModuleInfo *MMI; 55 const std::vector<MachineConstantPoolEntry> *MCPEs; 56 const std::vector<MachineJumpTableEntry> *MJTEs; 57 bool IsPIC; 58 bool IsThumb; 59 60 void getAnalysisUsage(AnalysisUsage &AU) const { 61 AU.addRequired<MachineModuleInfo>(); 62 MachineFunctionPass::getAnalysisUsage(AU); 63 } 64 65 static char ID; 66 public: 67 ARMCodeEmitter(TargetMachine &tm, JITCodeEmitter &mce) 68 : MachineFunctionPass(ID), JTI(0), 69 II((const ARMInstrInfo *)tm.getInstrInfo()), 70 TD(tm.getTargetData()), TM(tm), 71 MCE(mce), MCPEs(0), MJTEs(0), 72 IsPIC(TM.getRelocationModel() == Reloc::PIC_), IsThumb(false) {} 73 74 /// getBinaryCodeForInstr - This function, generated by the 75 /// CodeEmitterGenerator using TableGen, produces the binary encoding for 76 /// machine instructions. 77 unsigned getBinaryCodeForInstr(const MachineInstr &MI) const; 78 79 bool runOnMachineFunction(MachineFunction &MF); 80 81 virtual const char *getPassName() const { 82 return "ARM Machine Code Emitter"; 83 } 84 85 void emitInstruction(const MachineInstr &MI); 86 87 private: 88 89 void emitWordLE(unsigned Binary); 90 void emitDWordLE(uint64_t Binary); 91 void emitConstPoolInstruction(const MachineInstr &MI); 92 void emitMOVi32immInstruction(const MachineInstr &MI); 93 void emitMOVi2piecesInstruction(const MachineInstr &MI); 94 void emitLEApcrelJTInstruction(const MachineInstr &MI); 95 void emitPseudoMoveInstruction(const MachineInstr &MI); 96 void addPCLabel(unsigned LabelID); 97 void emitPseudoInstruction(const MachineInstr &MI); 98 unsigned getMachineSoRegOpValue(const MachineInstr &MI, 99 const TargetInstrDesc &TID, 100 const MachineOperand &MO, 101 unsigned OpIdx); 102 103 unsigned getMachineSoImmOpValue(unsigned SoImm); 104 unsigned getAddrModeSBit(const MachineInstr &MI, 105 const TargetInstrDesc &TID) const; 106 107 void emitDataProcessingInstruction(const MachineInstr &MI, 108 unsigned ImplicitRd = 0, 109 unsigned ImplicitRn = 0); 110 111 void emitLoadStoreInstruction(const MachineInstr &MI, 112 unsigned ImplicitRd = 0, 113 unsigned ImplicitRn = 0); 114 115 void emitMiscLoadStoreInstruction(const MachineInstr &MI, 116 unsigned ImplicitRn = 0); 117 118 void emitLoadStoreMultipleInstruction(const MachineInstr &MI); 119 120 void emitMulFrmInstruction(const MachineInstr &MI); 121 122 void emitExtendInstruction(const MachineInstr &MI); 123 124 void emitMiscArithInstruction(const MachineInstr &MI); 125 126 void emitSaturateInstruction(const MachineInstr &MI); 127 128 void emitBranchInstruction(const MachineInstr &MI); 129 130 void emitInlineJumpTable(unsigned JTIndex); 131 132 void emitMiscBranchInstruction(const MachineInstr &MI); 133 134 void emitVFPArithInstruction(const MachineInstr &MI); 135 136 void emitVFPConversionInstruction(const MachineInstr &MI); 137 138 void emitVFPLoadStoreInstruction(const MachineInstr &MI); 139 140 void emitVFPLoadStoreMultipleInstruction(const MachineInstr &MI); 141 142 void emitNEONLaneInstruction(const MachineInstr &MI); 143 void emitNEONDupInstruction(const MachineInstr &MI); 144 void emitNEON1RegModImmInstruction(const MachineInstr &MI); 145 void emitNEON2RegInstruction(const MachineInstr &MI); 146 void emitNEON3RegInstruction(const MachineInstr &MI); 147 148 /// getMachineOpValue - Return binary encoding of operand. If the machine 149 /// operand requires relocation, record the relocation and return zero. 150 unsigned getMachineOpValue(const MachineInstr &MI, 151 const MachineOperand &MO) const; 152 unsigned getMachineOpValue(const MachineInstr &MI, unsigned OpIdx) const { 153 return getMachineOpValue(MI, MI.getOperand(OpIdx)); 154 } 155 156 // FIXME: The legacy JIT ARMCodeEmitter doesn't rely on the the 157 // TableGen'erated getBinaryCodeForInstr() function to encode any 158 // operand values, instead querying getMachineOpValue() directly for 159 // each operand it needs to encode. Thus, any of the new encoder 160 // helper functions can simply return 0 as the values the return 161 // are already handled elsewhere. They are placeholders to allow this 162 // encoder to continue to function until the MC encoder is sufficiently 163 // far along that this one can be eliminated entirely. 164 unsigned NEONThumb2DataIPostEncoder(const MachineInstr &MI, unsigned Val) 165 const { return 0; } 166 unsigned NEONThumb2LoadStorePostEncoder(const MachineInstr &MI,unsigned Val) 167 const { return 0; } 168 unsigned NEONThumb2DupPostEncoder(const MachineInstr &MI,unsigned Val) 169 const { return 0; } 170 unsigned getBranchTargetOpValue(const MachineInstr &MI, unsigned Op) 171 const { return 0; } 172 unsigned getCCOutOpValue(const MachineInstr &MI, unsigned Op) 173 const { return 0; } 174 unsigned getSOImmOpValue(const MachineInstr &MI, unsigned Op) 175 const { return 0; } 176 unsigned getT2SOImmOpValue(const MachineInstr &MI, unsigned Op) 177 const { return 0; } 178 unsigned getSORegOpValue(const MachineInstr &MI, unsigned Op) 179 const { return 0; } 180 unsigned getT2AddrModeImm12OpValue(const MachineInstr &MI, unsigned Op) 181 const { return 0; } 182 unsigned getT2AddrModeImm8OpValue(const MachineInstr &MI, unsigned Op) 183 const { return 0; } 184 unsigned getT2AddrModeImm8s4OpValue(const MachineInstr &MI, unsigned Op) 185 const { return 0; } 186 unsigned getT2AddrModeImm8OffsetOpValue(const MachineInstr &MI, unsigned Op) 187 const { return 0; } 188 unsigned getT2AddrModeImm12OffsetOpValue(const MachineInstr &MI,unsigned Op) 189 const { return 0; } 190 unsigned getT2AddrModeSORegOpValue(const MachineInstr &MI, unsigned Op) 191 const { return 0; } 192 unsigned getT2SORegOpValue(const MachineInstr &MI, unsigned Op) 193 const { return 0; } 194 unsigned getRotImmOpValue(const MachineInstr &MI, unsigned Op) 195 const { return 0; } 196 unsigned getImmMinusOneOpValue(const MachineInstr &MI, unsigned Op) 197 const { return 0; } 198 unsigned getAddrMode6AddressOpValue(const MachineInstr &MI, unsigned Op) 199 const { return 0; } 200 unsigned getAddrMode6DupAddressOpValue(const MachineInstr &MI, unsigned Op) 201 const { return 0; } 202 unsigned getAddrMode6OffsetOpValue(const MachineInstr &MI, unsigned Op) 203 const { return 0; } 204 unsigned getBitfieldInvertedMaskOpValue(const MachineInstr &MI, 205 unsigned Op) const { return 0; } 206 uint32_t getLdStmModeOpValue(const MachineInstr &MI, unsigned OpIdx) 207 const {return 0; } 208 uint32_t getLdStSORegOpValue(const MachineInstr &MI, unsigned OpIdx) 209 const { return 0; } 210 211 unsigned getAddrModeImm12OpValue(const MachineInstr &MI, unsigned Op) 212 const { 213 // {17-13} = reg 214 // {12} = (U)nsigned (add == '1', sub == '0') 215 // {11-0} = imm12 216 const MachineOperand &MO = MI.getOperand(Op); 217 const MachineOperand &MO1 = MI.getOperand(Op + 1); 218 if (!MO.isReg()) { 219 emitConstPoolAddress(MO.getIndex(), ARM::reloc_arm_cp_entry); 220 return 0; 221 } 222 unsigned Reg = getARMRegisterNumbering(MO.getReg()); 223 int32_t Imm12 = MO1.getImm(); 224 uint32_t Binary; 225 Binary = Imm12 & 0xfff; 226 if (Imm12 >= 0) 227 Binary |= (1 << 12); 228 Binary |= (Reg << 13); 229 return Binary; 230 } 231 232 unsigned getMovtImmOpValue(const MachineInstr &MI, unsigned Op) const { 233 return 0; 234 } 235 236 uint32_t getAddrMode2OpValue(const MachineInstr &MI, unsigned OpIdx) 237 const { return 0;} 238 uint32_t getAddrMode2OffsetOpValue(const MachineInstr &MI, unsigned OpIdx) 239 const { return 0;} 240 uint32_t getAddrMode3OffsetOpValue(const MachineInstr &MI, unsigned OpIdx) 241 const { return 0;} 242 uint32_t getAddrMode3OpValue(const MachineInstr &MI, unsigned Op) 243 const { return 0; } 244 uint32_t getAddrModeS4OpValue(const MachineInstr &MI, unsigned Op) 245 const { return 0; } 246 uint32_t getAddrModeS2OpValue(const MachineInstr &MI, unsigned Op) 247 const { return 0; } 248 uint32_t getAddrModeS1OpValue(const MachineInstr &MI, unsigned Op) 249 const { return 0; } 250 uint32_t getAddrMode5OpValue(const MachineInstr &MI, unsigned Op) const { 251 // {17-13} = reg 252 // {12} = (U)nsigned (add == '1', sub == '0') 253 // {11-0} = imm12 254 const MachineOperand &MO = MI.getOperand(Op); 255 const MachineOperand &MO1 = MI.getOperand(Op + 1); 256 if (!MO.isReg()) { 257 emitConstPoolAddress(MO.getIndex(), ARM::reloc_arm_cp_entry); 258 return 0; 259 } 260 unsigned Reg = getARMRegisterNumbering(MO.getReg()); 261 int32_t Imm12 = MO1.getImm(); 262 263 // Special value for #-0 264 if (Imm12 == INT32_MIN) 265 Imm12 = 0; 266 267 // Immediate is always encoded as positive. The 'U' bit controls add vs 268 // sub. 269 bool isAdd = true; 270 if (Imm12 < 0) { 271 Imm12 = -Imm12; 272 isAdd = false; 273 } 274 275 uint32_t Binary = Imm12 & 0xfff; 276 if (isAdd) 277 Binary |= (1 << 12); 278 Binary |= (Reg << 13); 279 return Binary; 280 } 281 unsigned getNEONVcvtImm32OpValue(const MachineInstr &MI, unsigned Op) 282 const { return 0; } 283 284 unsigned getRegisterListOpValue(const MachineInstr &MI, unsigned Op) 285 const { return 0; } 286 287 /// getMovi32Value - Return binary encoding of operand for movw/movt. If the 288 /// machine operand requires relocation, record the relocation and return 289 /// zero. 290 unsigned getMovi32Value(const MachineInstr &MI,const MachineOperand &MO, 291 unsigned Reloc); 292 293 /// getShiftOp - Return the shift opcode (bit[6:5]) of the immediate value. 294 /// 295 unsigned getShiftOp(unsigned Imm) const ; 296 297 /// Routines that handle operands which add machine relocations which are 298 /// fixed up by the relocation stage. 299 void emitGlobalAddress(const GlobalValue *GV, unsigned Reloc, 300 bool MayNeedFarStub, bool Indirect, 301 intptr_t ACPV = 0) const; 302 void emitExternalSymbolAddress(const char *ES, unsigned Reloc) const; 303 void emitConstPoolAddress(unsigned CPI, unsigned Reloc) const; 304 void emitJumpTableAddress(unsigned JTIndex, unsigned Reloc) const; 305 void emitMachineBasicBlock(MachineBasicBlock *BB, unsigned Reloc, 306 intptr_t JTBase = 0) const; 307 }; 308} 309 310char ARMCodeEmitter::ID = 0; 311 312/// createARMJITCodeEmitterPass - Return a pass that emits the collected ARM 313/// code to the specified MCE object. 314FunctionPass *llvm::createARMJITCodeEmitterPass(ARMBaseTargetMachine &TM, 315 JITCodeEmitter &JCE) { 316 return new ARMCodeEmitter(TM, JCE); 317} 318 319bool ARMCodeEmitter::runOnMachineFunction(MachineFunction &MF) { 320 assert((MF.getTarget().getRelocationModel() != Reloc::Default || 321 MF.getTarget().getRelocationModel() != Reloc::Static) && 322 "JIT relocation model must be set to static or default!"); 323 JTI = ((ARMTargetMachine &)MF.getTarget()).getJITInfo(); 324 II = ((const ARMTargetMachine &)MF.getTarget()).getInstrInfo(); 325 TD = ((const ARMTargetMachine &)MF.getTarget()).getTargetData(); 326 Subtarget = &TM.getSubtarget<ARMSubtarget>(); 327 MCPEs = &MF.getConstantPool()->getConstants(); 328 MJTEs = 0; 329 if (MF.getJumpTableInfo()) MJTEs = &MF.getJumpTableInfo()->getJumpTables(); 330 IsPIC = TM.getRelocationModel() == Reloc::PIC_; 331 IsThumb = MF.getInfo<ARMFunctionInfo>()->isThumbFunction(); 332 JTI->Initialize(MF, IsPIC); 333 MMI = &getAnalysis<MachineModuleInfo>(); 334 MCE.setModuleInfo(MMI); 335 336 do { 337 DEBUG(errs() << "JITTing function '" 338 << MF.getFunction()->getName() << "'\n"); 339 MCE.startFunction(MF); 340 for (MachineFunction::iterator MBB = MF.begin(), E = MF.end(); 341 MBB != E; ++MBB) { 342 MCE.StartMachineBasicBlock(MBB); 343 for (MachineBasicBlock::const_iterator I = MBB->begin(), E = MBB->end(); 344 I != E; ++I) 345 emitInstruction(*I); 346 } 347 } while (MCE.finishFunction(MF)); 348 349 return false; 350} 351 352/// getShiftOp - Return the shift opcode (bit[6:5]) of the immediate value. 353/// 354unsigned ARMCodeEmitter::getShiftOp(unsigned Imm) const { 355 switch (ARM_AM::getAM2ShiftOpc(Imm)) { 356 default: llvm_unreachable("Unknown shift opc!"); 357 case ARM_AM::asr: return 2; 358 case ARM_AM::lsl: return 0; 359 case ARM_AM::lsr: return 1; 360 case ARM_AM::ror: 361 case ARM_AM::rrx: return 3; 362 } 363 return 0; 364} 365 366/// getMovi32Value - Return binary encoding of operand for movw/movt. If the 367/// machine operand requires relocation, record the relocation and return zero. 368unsigned ARMCodeEmitter::getMovi32Value(const MachineInstr &MI, 369 const MachineOperand &MO, 370 unsigned Reloc) { 371 assert(((Reloc == ARM::reloc_arm_movt) || (Reloc == ARM::reloc_arm_movw)) 372 && "Relocation to this function should be for movt or movw"); 373 374 if (MO.isImm()) 375 return static_cast<unsigned>(MO.getImm()); 376 else if (MO.isGlobal()) 377 emitGlobalAddress(MO.getGlobal(), Reloc, true, false); 378 else if (MO.isSymbol()) 379 emitExternalSymbolAddress(MO.getSymbolName(), Reloc); 380 else if (MO.isMBB()) 381 emitMachineBasicBlock(MO.getMBB(), Reloc); 382 else { 383#ifndef NDEBUG 384 errs() << MO; 385#endif 386 llvm_unreachable("Unsupported operand type for movw/movt"); 387 } 388 return 0; 389} 390 391/// getMachineOpValue - Return binary encoding of operand. If the machine 392/// operand requires relocation, record the relocation and return zero. 393unsigned ARMCodeEmitter::getMachineOpValue(const MachineInstr &MI, 394 const MachineOperand &MO) const { 395 if (MO.isReg()) 396 return getARMRegisterNumbering(MO.getReg()); 397 else if (MO.isImm()) 398 return static_cast<unsigned>(MO.getImm()); 399 else if (MO.isGlobal()) 400 emitGlobalAddress(MO.getGlobal(), ARM::reloc_arm_branch, true, false); 401 else if (MO.isSymbol()) 402 emitExternalSymbolAddress(MO.getSymbolName(), ARM::reloc_arm_branch); 403 else if (MO.isCPI()) { 404 const TargetInstrDesc &TID = MI.getDesc(); 405 // For VFP load, the immediate offset is multiplied by 4. 406 unsigned Reloc = ((TID.TSFlags & ARMII::FormMask) == ARMII::VFPLdStFrm) 407 ? ARM::reloc_arm_vfp_cp_entry : ARM::reloc_arm_cp_entry; 408 emitConstPoolAddress(MO.getIndex(), Reloc); 409 } else if (MO.isJTI()) 410 emitJumpTableAddress(MO.getIndex(), ARM::reloc_arm_relative); 411 else if (MO.isMBB()) 412 emitMachineBasicBlock(MO.getMBB(), ARM::reloc_arm_branch); 413 else 414 llvm_unreachable("Unable to encode MachineOperand!"); 415 return 0; 416} 417 418/// emitGlobalAddress - Emit the specified address to the code stream. 419/// 420void ARMCodeEmitter::emitGlobalAddress(const GlobalValue *GV, unsigned Reloc, 421 bool MayNeedFarStub, bool Indirect, 422 intptr_t ACPV) const { 423 MachineRelocation MR = Indirect 424 ? MachineRelocation::getIndirectSymbol(MCE.getCurrentPCOffset(), Reloc, 425 const_cast<GlobalValue *>(GV), 426 ACPV, MayNeedFarStub) 427 : MachineRelocation::getGV(MCE.getCurrentPCOffset(), Reloc, 428 const_cast<GlobalValue *>(GV), ACPV, 429 MayNeedFarStub); 430 MCE.addRelocation(MR); 431} 432 433/// emitExternalSymbolAddress - Arrange for the address of an external symbol to 434/// be emitted to the current location in the function, and allow it to be PC 435/// relative. 436void ARMCodeEmitter:: 437emitExternalSymbolAddress(const char *ES, unsigned Reloc) const { 438 MCE.addRelocation(MachineRelocation::getExtSym(MCE.getCurrentPCOffset(), 439 Reloc, ES)); 440} 441 442/// emitConstPoolAddress - Arrange for the address of an constant pool 443/// to be emitted to the current location in the function, and allow it to be PC 444/// relative. 445void ARMCodeEmitter::emitConstPoolAddress(unsigned CPI, unsigned Reloc) const { 446 // Tell JIT emitter we'll resolve the address. 447 MCE.addRelocation(MachineRelocation::getConstPool(MCE.getCurrentPCOffset(), 448 Reloc, CPI, 0, true)); 449} 450 451/// emitJumpTableAddress - Arrange for the address of a jump table to 452/// be emitted to the current location in the function, and allow it to be PC 453/// relative. 454void ARMCodeEmitter:: 455emitJumpTableAddress(unsigned JTIndex, unsigned Reloc) const { 456 MCE.addRelocation(MachineRelocation::getJumpTable(MCE.getCurrentPCOffset(), 457 Reloc, JTIndex, 0, true)); 458} 459 460/// emitMachineBasicBlock - Emit the specified address basic block. 461void ARMCodeEmitter::emitMachineBasicBlock(MachineBasicBlock *BB, 462 unsigned Reloc, 463 intptr_t JTBase) const { 464 MCE.addRelocation(MachineRelocation::getBB(MCE.getCurrentPCOffset(), 465 Reloc, BB, JTBase)); 466} 467 468void ARMCodeEmitter::emitWordLE(unsigned Binary) { 469 DEBUG(errs() << " 0x"; 470 errs().write_hex(Binary) << "\n"); 471 MCE.emitWordLE(Binary); 472} 473 474void ARMCodeEmitter::emitDWordLE(uint64_t Binary) { 475 DEBUG(errs() << " 0x"; 476 errs().write_hex(Binary) << "\n"); 477 MCE.emitDWordLE(Binary); 478} 479 480void ARMCodeEmitter::emitInstruction(const MachineInstr &MI) { 481 DEBUG(errs() << "JIT: " << (void*)MCE.getCurrentPCValue() << ":\t" << MI); 482 483 MCE.processDebugLoc(MI.getDebugLoc(), true); 484 485 ++NumEmitted; // Keep track of the # of mi's emitted 486 switch (MI.getDesc().TSFlags & ARMII::FormMask) { 487 default: { 488 llvm_unreachable("Unhandled instruction encoding format!"); 489 break; 490 } 491 case ARMII::MiscFrm: 492 if (MI.getOpcode() == ARM::LEApcrelJT) { 493 // Materialize jumptable address. 494 emitLEApcrelJTInstruction(MI); 495 break; 496 } 497 llvm_unreachable("Unhandled instruction encoding!"); 498 break; 499 case ARMII::Pseudo: 500 emitPseudoInstruction(MI); 501 break; 502 case ARMII::DPFrm: 503 case ARMII::DPSoRegFrm: 504 emitDataProcessingInstruction(MI); 505 break; 506 case ARMII::LdFrm: 507 case ARMII::StFrm: 508 emitLoadStoreInstruction(MI); 509 break; 510 case ARMII::LdMiscFrm: 511 case ARMII::StMiscFrm: 512 emitMiscLoadStoreInstruction(MI); 513 break; 514 case ARMII::LdStMulFrm: 515 emitLoadStoreMultipleInstruction(MI); 516 break; 517 case ARMII::MulFrm: 518 emitMulFrmInstruction(MI); 519 break; 520 case ARMII::ExtFrm: 521 emitExtendInstruction(MI); 522 break; 523 case ARMII::ArithMiscFrm: 524 emitMiscArithInstruction(MI); 525 break; 526 case ARMII::SatFrm: 527 emitSaturateInstruction(MI); 528 break; 529 case ARMII::BrFrm: 530 emitBranchInstruction(MI); 531 break; 532 case ARMII::BrMiscFrm: 533 emitMiscBranchInstruction(MI); 534 break; 535 // VFP instructions. 536 case ARMII::VFPUnaryFrm: 537 case ARMII::VFPBinaryFrm: 538 emitVFPArithInstruction(MI); 539 break; 540 case ARMII::VFPConv1Frm: 541 case ARMII::VFPConv2Frm: 542 case ARMII::VFPConv3Frm: 543 case ARMII::VFPConv4Frm: 544 case ARMII::VFPConv5Frm: 545 emitVFPConversionInstruction(MI); 546 break; 547 case ARMII::VFPLdStFrm: 548 emitVFPLoadStoreInstruction(MI); 549 break; 550 case ARMII::VFPLdStMulFrm: 551 emitVFPLoadStoreMultipleInstruction(MI); 552 break; 553 554 // NEON instructions. 555 case ARMII::NGetLnFrm: 556 case ARMII::NSetLnFrm: 557 emitNEONLaneInstruction(MI); 558 break; 559 case ARMII::NDupFrm: 560 emitNEONDupInstruction(MI); 561 break; 562 case ARMII::N1RegModImmFrm: 563 emitNEON1RegModImmInstruction(MI); 564 break; 565 case ARMII::N2RegFrm: 566 emitNEON2RegInstruction(MI); 567 break; 568 case ARMII::N3RegFrm: 569 emitNEON3RegInstruction(MI); 570 break; 571 } 572 MCE.processDebugLoc(MI.getDebugLoc(), false); 573} 574 575void ARMCodeEmitter::emitConstPoolInstruction(const MachineInstr &MI) { 576 unsigned CPI = MI.getOperand(0).getImm(); // CP instruction index. 577 unsigned CPIndex = MI.getOperand(1).getIndex(); // Actual cp entry index. 578 const MachineConstantPoolEntry &MCPE = (*MCPEs)[CPIndex]; 579 580 // Remember the CONSTPOOL_ENTRY address for later relocation. 581 JTI->addConstantPoolEntryAddr(CPI, MCE.getCurrentPCValue()); 582 583 // Emit constpool island entry. In most cases, the actual values will be 584 // resolved and relocated after code emission. 585 if (MCPE.isMachineConstantPoolEntry()) { 586 ARMConstantPoolValue *ACPV = 587 static_cast<ARMConstantPoolValue*>(MCPE.Val.MachineCPVal); 588 589 DEBUG(errs() << " ** ARM constant pool #" << CPI << " @ " 590 << (void*)MCE.getCurrentPCValue() << " " << *ACPV << '\n'); 591 592 assert(ACPV->isGlobalValue() && "unsupported constant pool value"); 593 const GlobalValue *GV = ACPV->getGV(); 594 if (GV) { 595 Reloc::Model RelocM = TM.getRelocationModel(); 596 emitGlobalAddress(GV, ARM::reloc_arm_machine_cp_entry, 597 isa<Function>(GV), 598 Subtarget->GVIsIndirectSymbol(GV, RelocM), 599 (intptr_t)ACPV); 600 } else { 601 emitExternalSymbolAddress(ACPV->getSymbol(), ARM::reloc_arm_absolute); 602 } 603 emitWordLE(0); 604 } else { 605 const Constant *CV = MCPE.Val.ConstVal; 606 607 DEBUG({ 608 errs() << " ** Constant pool #" << CPI << " @ " 609 << (void*)MCE.getCurrentPCValue() << " "; 610 if (const Function *F = dyn_cast<Function>(CV)) 611 errs() << F->getName(); 612 else 613 errs() << *CV; 614 errs() << '\n'; 615 }); 616 617 if (const GlobalValue *GV = dyn_cast<GlobalValue>(CV)) { 618 emitGlobalAddress(GV, ARM::reloc_arm_absolute, isa<Function>(GV), false); 619 emitWordLE(0); 620 } else if (const ConstantInt *CI = dyn_cast<ConstantInt>(CV)) { 621 uint32_t Val = uint32_t(*CI->getValue().getRawData()); 622 emitWordLE(Val); 623 } else if (const ConstantFP *CFP = dyn_cast<ConstantFP>(CV)) { 624 if (CFP->getType()->isFloatTy()) 625 emitWordLE(CFP->getValueAPF().bitcastToAPInt().getZExtValue()); 626 else if (CFP->getType()->isDoubleTy()) 627 emitDWordLE(CFP->getValueAPF().bitcastToAPInt().getZExtValue()); 628 else { 629 llvm_unreachable("Unable to handle this constantpool entry!"); 630 } 631 } else { 632 llvm_unreachable("Unable to handle this constantpool entry!"); 633 } 634 } 635} 636 637void ARMCodeEmitter::emitMOVi32immInstruction(const MachineInstr &MI) { 638 const MachineOperand &MO0 = MI.getOperand(0); 639 const MachineOperand &MO1 = MI.getOperand(1); 640 641 // Emit the 'movw' instruction. 642 unsigned Binary = 0x30 << 20; // mov: Insts{27-20} = 0b00110000 643 644 unsigned Lo16 = getMovi32Value(MI, MO1, ARM::reloc_arm_movw) & 0xFFFF; 645 646 // Set the conditional execution predicate. 647 Binary |= II->getPredicate(&MI) << ARMII::CondShift; 648 649 // Encode Rd. 650 Binary |= getMachineOpValue(MI, MO0) << ARMII::RegRdShift; 651 652 // Encode imm16 as imm4:imm12 653 Binary |= Lo16 & 0xFFF; // Insts{11-0} = imm12 654 Binary |= ((Lo16 >> 12) & 0xF) << 16; // Insts{19-16} = imm4 655 emitWordLE(Binary); 656 657 unsigned Hi16 = getMovi32Value(MI, MO1, ARM::reloc_arm_movt) >> 16; 658 // Emit the 'movt' instruction. 659 Binary = 0x34 << 20; // movt: Insts{27-20} = 0b00110100 660 661 // Set the conditional execution predicate. 662 Binary |= II->getPredicate(&MI) << ARMII::CondShift; 663 664 // Encode Rd. 665 Binary |= getMachineOpValue(MI, MO0) << ARMII::RegRdShift; 666 667 // Encode imm16 as imm4:imm1, same as movw above. 668 Binary |= Hi16 & 0xFFF; 669 Binary |= ((Hi16 >> 12) & 0xF) << 16; 670 emitWordLE(Binary); 671} 672 673void ARMCodeEmitter::emitMOVi2piecesInstruction(const MachineInstr &MI) { 674 const MachineOperand &MO0 = MI.getOperand(0); 675 const MachineOperand &MO1 = MI.getOperand(1); 676 assert(MO1.isImm() && ARM_AM::isSOImmTwoPartVal(MO1.getImm()) && 677 "Not a valid so_imm value!"); 678 unsigned V1 = ARM_AM::getSOImmTwoPartFirst(MO1.getImm()); 679 unsigned V2 = ARM_AM::getSOImmTwoPartSecond(MO1.getImm()); 680 681 // Emit the 'mov' instruction. 682 unsigned Binary = 0xd << 21; // mov: Insts{24-21} = 0b1101 683 684 // Set the conditional execution predicate. 685 Binary |= II->getPredicate(&MI) << ARMII::CondShift; 686 687 // Encode Rd. 688 Binary |= getMachineOpValue(MI, MO0) << ARMII::RegRdShift; 689 690 // Encode so_imm. 691 // Set bit I(25) to identify this is the immediate form of <shifter_op> 692 Binary |= 1 << ARMII::I_BitShift; 693 Binary |= getMachineSoImmOpValue(V1); 694 emitWordLE(Binary); 695 696 // Now the 'orr' instruction. 697 Binary = 0xc << 21; // orr: Insts{24-21} = 0b1100 698 699 // Set the conditional execution predicate. 700 Binary |= II->getPredicate(&MI) << ARMII::CondShift; 701 702 // Encode Rd. 703 Binary |= getMachineOpValue(MI, MO0) << ARMII::RegRdShift; 704 705 // Encode Rn. 706 Binary |= getMachineOpValue(MI, MO0) << ARMII::RegRnShift; 707 708 // Encode so_imm. 709 // Set bit I(25) to identify this is the immediate form of <shifter_op> 710 Binary |= 1 << ARMII::I_BitShift; 711 Binary |= getMachineSoImmOpValue(V2); 712 emitWordLE(Binary); 713} 714 715void ARMCodeEmitter::emitLEApcrelJTInstruction(const MachineInstr &MI) { 716 // It's basically add r, pc, (LJTI - $+8) 717 718 const TargetInstrDesc &TID = MI.getDesc(); 719 720 // Emit the 'add' instruction. 721 unsigned Binary = 0x4 << 21; // add: Insts{24-21} = 0b0100 722 723 // Set the conditional execution predicate 724 Binary |= II->getPredicate(&MI) << ARMII::CondShift; 725 726 // Encode S bit if MI modifies CPSR. 727 Binary |= getAddrModeSBit(MI, TID); 728 729 // Encode Rd. 730 Binary |= getMachineOpValue(MI, 0) << ARMII::RegRdShift; 731 732 // Encode Rn which is PC. 733 Binary |= getARMRegisterNumbering(ARM::PC) << ARMII::RegRnShift; 734 735 // Encode the displacement. 736 Binary |= 1 << ARMII::I_BitShift; 737 emitJumpTableAddress(MI.getOperand(1).getIndex(), ARM::reloc_arm_jt_base); 738 739 emitWordLE(Binary); 740} 741 742void ARMCodeEmitter::emitPseudoMoveInstruction(const MachineInstr &MI) { 743 unsigned Opcode = MI.getDesc().Opcode; 744 745 // Part of binary is determined by TableGn. 746 unsigned Binary = getBinaryCodeForInstr(MI); 747 748 // Set the conditional execution predicate 749 Binary |= II->getPredicate(&MI) << ARMII::CondShift; 750 751 // Encode S bit if MI modifies CPSR. 752 if (Opcode == ARM::MOVsrl_flag || Opcode == ARM::MOVsra_flag) 753 Binary |= 1 << ARMII::S_BitShift; 754 755 // Encode register def if there is one. 756 Binary |= getMachineOpValue(MI, 0) << ARMII::RegRdShift; 757 758 // Encode the shift operation. 759 switch (Opcode) { 760 default: break; 761 case ARM::RRX: 762 // rrx 763 Binary |= 0x6 << 4; 764 break; 765 case ARM::MOVsrl_flag: 766 // lsr #1 767 Binary |= (0x2 << 4) | (1 << 7); 768 break; 769 case ARM::MOVsra_flag: 770 // asr #1 771 Binary |= (0x4 << 4) | (1 << 7); 772 break; 773 } 774 775 // Encode register Rm. 776 Binary |= getMachineOpValue(MI, 1); 777 778 emitWordLE(Binary); 779} 780 781void ARMCodeEmitter::addPCLabel(unsigned LabelID) { 782 DEBUG(errs() << " ** LPC" << LabelID << " @ " 783 << (void*)MCE.getCurrentPCValue() << '\n'); 784 JTI->addPCLabelAddr(LabelID, MCE.getCurrentPCValue()); 785} 786 787void ARMCodeEmitter::emitPseudoInstruction(const MachineInstr &MI) { 788 unsigned Opcode = MI.getDesc().Opcode; 789 switch (Opcode) { 790 default: 791 llvm_unreachable("ARMCodeEmitter::emitPseudoInstruction"); 792 case ARM::BX_CALL: 793 case ARM::BMOVPCRX_CALL: 794 case ARM::BXr9_CALL: 795 case ARM::BMOVPCRXr9_CALL: { 796 // First emit mov lr, pc 797 unsigned Binary = 0x01a0e00f; 798 Binary |= II->getPredicate(&MI) << ARMII::CondShift; 799 emitWordLE(Binary); 800 801 // and then emit the branch. 802 emitMiscBranchInstruction(MI); 803 break; 804 } 805 case TargetOpcode::INLINEASM: { 806 // We allow inline assembler nodes with empty bodies - they can 807 // implicitly define registers, which is ok for JIT. 808 if (MI.getOperand(0).getSymbolName()[0]) { 809 report_fatal_error("JIT does not support inline asm!"); 810 } 811 break; 812 } 813 case TargetOpcode::PROLOG_LABEL: 814 case TargetOpcode::EH_LABEL: 815 MCE.emitLabel(MI.getOperand(0).getMCSymbol()); 816 break; 817 case TargetOpcode::IMPLICIT_DEF: 818 case TargetOpcode::KILL: 819 // Do nothing. 820 break; 821 case ARM::CONSTPOOL_ENTRY: 822 emitConstPoolInstruction(MI); 823 break; 824 case ARM::PICADD: { 825 // Remember of the address of the PC label for relocation later. 826 addPCLabel(MI.getOperand(2).getImm()); 827 // PICADD is just an add instruction that implicitly read pc. 828 emitDataProcessingInstruction(MI, 0, ARM::PC); 829 break; 830 } 831 case ARM::PICLDR: 832 case ARM::PICLDRB: 833 case ARM::PICSTR: 834 case ARM::PICSTRB: { 835 // Remember of the address of the PC label for relocation later. 836 addPCLabel(MI.getOperand(2).getImm()); 837 // These are just load / store instructions that implicitly read pc. 838 emitLoadStoreInstruction(MI, 0, ARM::PC); 839 break; 840 } 841 case ARM::PICLDRH: 842 case ARM::PICLDRSH: 843 case ARM::PICLDRSB: 844 case ARM::PICSTRH: { 845 // Remember of the address of the PC label for relocation later. 846 addPCLabel(MI.getOperand(2).getImm()); 847 // These are just load / store instructions that implicitly read pc. 848 emitMiscLoadStoreInstruction(MI, ARM::PC); 849 break; 850 } 851 852 case ARM::MOVi32imm: 853 // Two instructions to materialize a constant. 854 if (Subtarget->hasV6T2Ops()) 855 emitMOVi32immInstruction(MI); 856 else 857 emitMOVi2piecesInstruction(MI); 858 break; 859 860 case ARM::LEApcrelJT: 861 // Materialize jumptable address. 862 emitLEApcrelJTInstruction(MI); 863 break; 864 case ARM::RRX: 865 case ARM::MOVsrl_flag: 866 case ARM::MOVsra_flag: 867 emitPseudoMoveInstruction(MI); 868 break; 869 } 870} 871 872unsigned ARMCodeEmitter::getMachineSoRegOpValue(const MachineInstr &MI, 873 const TargetInstrDesc &TID, 874 const MachineOperand &MO, 875 unsigned OpIdx) { 876 unsigned Binary = getMachineOpValue(MI, MO); 877 878 const MachineOperand &MO1 = MI.getOperand(OpIdx + 1); 879 const MachineOperand &MO2 = MI.getOperand(OpIdx + 2); 880 ARM_AM::ShiftOpc SOpc = ARM_AM::getSORegShOp(MO2.getImm()); 881 882 // Encode the shift opcode. 883 unsigned SBits = 0; 884 unsigned Rs = MO1.getReg(); 885 if (Rs) { 886 // Set shift operand (bit[7:4]). 887 // LSL - 0001 888 // LSR - 0011 889 // ASR - 0101 890 // ROR - 0111 891 // RRX - 0110 and bit[11:8] clear. 892 switch (SOpc) { 893 default: llvm_unreachable("Unknown shift opc!"); 894 case ARM_AM::lsl: SBits = 0x1; break; 895 case ARM_AM::lsr: SBits = 0x3; break; 896 case ARM_AM::asr: SBits = 0x5; break; 897 case ARM_AM::ror: SBits = 0x7; break; 898 case ARM_AM::rrx: SBits = 0x6; break; 899 } 900 } else { 901 // Set shift operand (bit[6:4]). 902 // LSL - 000 903 // LSR - 010 904 // ASR - 100 905 // ROR - 110 906 switch (SOpc) { 907 default: llvm_unreachable("Unknown shift opc!"); 908 case ARM_AM::lsl: SBits = 0x0; break; 909 case ARM_AM::lsr: SBits = 0x2; break; 910 case ARM_AM::asr: SBits = 0x4; break; 911 case ARM_AM::ror: SBits = 0x6; break; 912 } 913 } 914 Binary |= SBits << 4; 915 if (SOpc == ARM_AM::rrx) 916 return Binary; 917 918 // Encode the shift operation Rs or shift_imm (except rrx). 919 if (Rs) { 920 // Encode Rs bit[11:8]. 921 assert(ARM_AM::getSORegOffset(MO2.getImm()) == 0); 922 return Binary | (getARMRegisterNumbering(Rs) << ARMII::RegRsShift); 923 } 924 925 // Encode shift_imm bit[11:7]. 926 return Binary | ARM_AM::getSORegOffset(MO2.getImm()) << 7; 927} 928 929unsigned ARMCodeEmitter::getMachineSoImmOpValue(unsigned SoImm) { 930 int SoImmVal = ARM_AM::getSOImmVal(SoImm); 931 assert(SoImmVal != -1 && "Not a valid so_imm value!"); 932 933 // Encode rotate_imm. 934 unsigned Binary = (ARM_AM::getSOImmValRot((unsigned)SoImmVal) >> 1) 935 << ARMII::SoRotImmShift; 936 937 // Encode immed_8. 938 Binary |= ARM_AM::getSOImmValImm((unsigned)SoImmVal); 939 return Binary; 940} 941 942unsigned ARMCodeEmitter::getAddrModeSBit(const MachineInstr &MI, 943 const TargetInstrDesc &TID) const { 944 for (unsigned i = MI.getNumOperands(), e = TID.getNumOperands(); i != e; --i){ 945 const MachineOperand &MO = MI.getOperand(i-1); 946 if (MO.isReg() && MO.isDef() && MO.getReg() == ARM::CPSR) 947 return 1 << ARMII::S_BitShift; 948 } 949 return 0; 950} 951 952void ARMCodeEmitter::emitDataProcessingInstruction(const MachineInstr &MI, 953 unsigned ImplicitRd, 954 unsigned ImplicitRn) { 955 const TargetInstrDesc &TID = MI.getDesc(); 956 957 // Part of binary is determined by TableGn. 958 unsigned Binary = getBinaryCodeForInstr(MI); 959 960 // Set the conditional execution predicate 961 Binary |= II->getPredicate(&MI) << ARMII::CondShift; 962 963 // Encode S bit if MI modifies CPSR. 964 Binary |= getAddrModeSBit(MI, TID); 965 966 // Encode register def if there is one. 967 unsigned NumDefs = TID.getNumDefs(); 968 unsigned OpIdx = 0; 969 if (NumDefs) 970 Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRdShift; 971 else if (ImplicitRd) 972 // Special handling for implicit use (e.g. PC). 973 Binary |= (getARMRegisterNumbering(ImplicitRd) << ARMII::RegRdShift); 974 975 if (TID.Opcode == ARM::MOVi16) { 976 // Get immediate from MI. 977 unsigned Lo16 = getMovi32Value(MI, MI.getOperand(OpIdx), 978 ARM::reloc_arm_movw); 979 // Encode imm which is the same as in emitMOVi32immInstruction(). 980 Binary |= Lo16 & 0xFFF; 981 Binary |= ((Lo16 >> 12) & 0xF) << 16; 982 emitWordLE(Binary); 983 return; 984 } else if(TID.Opcode == ARM::MOVTi16) { 985 unsigned Hi16 = (getMovi32Value(MI, MI.getOperand(OpIdx), 986 ARM::reloc_arm_movt) >> 16); 987 Binary |= Hi16 & 0xFFF; 988 Binary |= ((Hi16 >> 12) & 0xF) << 16; 989 emitWordLE(Binary); 990 return; 991 } else if ((TID.Opcode == ARM::BFC) || (TID.Opcode == ARM::BFI)) { 992 uint32_t v = ~MI.getOperand(2).getImm(); 993 int32_t lsb = CountTrailingZeros_32(v); 994 int32_t msb = (32 - CountLeadingZeros_32(v)) - 1; 995 // Instr{20-16} = msb, Instr{11-7} = lsb 996 Binary |= (msb & 0x1F) << 16; 997 Binary |= (lsb & 0x1F) << 7; 998 emitWordLE(Binary); 999 return; 1000 } else if ((TID.Opcode == ARM::UBFX) || (TID.Opcode == ARM::SBFX)) { 1001 // Encode Rn in Instr{0-3} 1002 Binary |= getMachineOpValue(MI, OpIdx++); 1003 1004 uint32_t lsb = MI.getOperand(OpIdx++).getImm(); 1005 uint32_t widthm1 = MI.getOperand(OpIdx++).getImm() - 1; 1006 1007 // Instr{20-16} = widthm1, Instr{11-7} = lsb 1008 Binary |= (widthm1 & 0x1F) << 16; 1009 Binary |= (lsb & 0x1F) << 7; 1010 emitWordLE(Binary); 1011 return; 1012 } 1013 1014 // If this is a two-address operand, skip it. e.g. MOVCCr operand 1. 1015 if (TID.getOperandConstraint(OpIdx, TOI::TIED_TO) != -1) 1016 ++OpIdx; 1017 1018 // Encode first non-shifter register operand if there is one. 1019 bool isUnary = TID.TSFlags & ARMII::UnaryDP; 1020 if (!isUnary) { 1021 if (ImplicitRn) 1022 // Special handling for implicit use (e.g. PC). 1023 Binary |= (getARMRegisterNumbering(ImplicitRn) << ARMII::RegRnShift); 1024 else { 1025 Binary |= getMachineOpValue(MI, OpIdx) << ARMII::RegRnShift; 1026 ++OpIdx; 1027 } 1028 } 1029 1030 // Encode shifter operand. 1031 const MachineOperand &MO = MI.getOperand(OpIdx); 1032 if ((TID.TSFlags & ARMII::FormMask) == ARMII::DPSoRegFrm) { 1033 // Encode SoReg. 1034 emitWordLE(Binary | getMachineSoRegOpValue(MI, TID, MO, OpIdx)); 1035 return; 1036 } 1037 1038 if (MO.isReg()) { 1039 // Encode register Rm. 1040 emitWordLE(Binary | getARMRegisterNumbering(MO.getReg())); 1041 return; 1042 } 1043 1044 // Encode so_imm. 1045 Binary |= getMachineSoImmOpValue((unsigned)MO.getImm()); 1046 1047 emitWordLE(Binary); 1048} 1049 1050void ARMCodeEmitter::emitLoadStoreInstruction(const MachineInstr &MI, 1051 unsigned ImplicitRd, 1052 unsigned ImplicitRn) { 1053 const TargetInstrDesc &TID = MI.getDesc(); 1054 unsigned Form = TID.TSFlags & ARMII::FormMask; 1055 bool IsPrePost = (TID.TSFlags & ARMII::IndexModeMask) != 0; 1056 1057 // Part of binary is determined by TableGn. 1058 unsigned Binary = getBinaryCodeForInstr(MI); 1059 1060 // If this is an LDRi12, STRi12 or LDRcp, nothing more needs be done. 1061 if (MI.getOpcode() == ARM::LDRi12 || MI.getOpcode() == ARM::LDRcp || 1062 MI.getOpcode() == ARM::STRi12) { 1063 emitWordLE(Binary); 1064 return; 1065 } 1066 1067 // Set the conditional execution predicate 1068 Binary |= II->getPredicate(&MI) << ARMII::CondShift; 1069 1070 unsigned OpIdx = 0; 1071 1072 // Operand 0 of a pre- and post-indexed store is the address base 1073 // writeback. Skip it. 1074 bool Skipped = false; 1075 if (IsPrePost && Form == ARMII::StFrm) { 1076 ++OpIdx; 1077 Skipped = true; 1078 } 1079 1080 // Set first operand 1081 if (ImplicitRd) 1082 // Special handling for implicit use (e.g. PC). 1083 Binary |= (getARMRegisterNumbering(ImplicitRd) << ARMII::RegRdShift); 1084 else 1085 Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRdShift; 1086 1087 // Set second operand 1088 if (ImplicitRn) 1089 // Special handling for implicit use (e.g. PC). 1090 Binary |= (getARMRegisterNumbering(ImplicitRn) << ARMII::RegRnShift); 1091 else 1092 Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRnShift; 1093 1094 // If this is a two-address operand, skip it. e.g. LDR_PRE. 1095 if (!Skipped && TID.getOperandConstraint(OpIdx, TOI::TIED_TO) != -1) 1096 ++OpIdx; 1097 1098 const MachineOperand &MO2 = MI.getOperand(OpIdx); 1099 unsigned AM2Opc = (ImplicitRn == ARM::PC) 1100 ? 0 : MI.getOperand(OpIdx+1).getImm(); 1101 1102 // Set bit U(23) according to sign of immed value (positive or negative). 1103 Binary |= ((ARM_AM::getAM2Op(AM2Opc) == ARM_AM::add ? 1 : 0) << 1104 ARMII::U_BitShift); 1105 if (!MO2.getReg()) { // is immediate 1106 if (ARM_AM::getAM2Offset(AM2Opc)) 1107 // Set the value of offset_12 field 1108 Binary |= ARM_AM::getAM2Offset(AM2Opc); 1109 emitWordLE(Binary); 1110 return; 1111 } 1112 1113 // Set bit I(25), because this is not in immediate encoding. 1114 Binary |= 1 << ARMII::I_BitShift; 1115 assert(TargetRegisterInfo::isPhysicalRegister(MO2.getReg())); 1116 // Set bit[3:0] to the corresponding Rm register 1117 Binary |= getARMRegisterNumbering(MO2.getReg()); 1118 1119 // If this instr is in scaled register offset/index instruction, set 1120 // shift_immed(bit[11:7]) and shift(bit[6:5]) fields. 1121 if (unsigned ShImm = ARM_AM::getAM2Offset(AM2Opc)) { 1122 Binary |= getShiftOp(AM2Opc) << ARMII::ShiftImmShift; // shift 1123 Binary |= ShImm << ARMII::ShiftShift; // shift_immed 1124 } 1125 1126 emitWordLE(Binary); 1127} 1128 1129void ARMCodeEmitter::emitMiscLoadStoreInstruction(const MachineInstr &MI, 1130 unsigned ImplicitRn) { 1131 const TargetInstrDesc &TID = MI.getDesc(); 1132 unsigned Form = TID.TSFlags & ARMII::FormMask; 1133 bool IsPrePost = (TID.TSFlags & ARMII::IndexModeMask) != 0; 1134 1135 // Part of binary is determined by TableGn. 1136 unsigned Binary = getBinaryCodeForInstr(MI); 1137 1138 // Set the conditional execution predicate 1139 Binary |= II->getPredicate(&MI) << ARMII::CondShift; 1140 1141 unsigned OpIdx = 0; 1142 1143 // Operand 0 of a pre- and post-indexed store is the address base 1144 // writeback. Skip it. 1145 bool Skipped = false; 1146 if (IsPrePost && Form == ARMII::StMiscFrm) { 1147 ++OpIdx; 1148 Skipped = true; 1149 } 1150 1151 // Set first operand 1152 Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRdShift; 1153 1154 // Skip LDRD and STRD's second operand. 1155 if (TID.Opcode == ARM::LDRD || TID.Opcode == ARM::STRD) 1156 ++OpIdx; 1157 1158 // Set second operand 1159 if (ImplicitRn) 1160 // Special handling for implicit use (e.g. PC). 1161 Binary |= (getARMRegisterNumbering(ImplicitRn) << ARMII::RegRnShift); 1162 else 1163 Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRnShift; 1164 1165 // If this is a two-address operand, skip it. e.g. LDRH_POST. 1166 if (!Skipped && TID.getOperandConstraint(OpIdx, TOI::TIED_TO) != -1) 1167 ++OpIdx; 1168 1169 const MachineOperand &MO2 = MI.getOperand(OpIdx); 1170 unsigned AM3Opc = (ImplicitRn == ARM::PC) 1171 ? 0 : MI.getOperand(OpIdx+1).getImm(); 1172 1173 // Set bit U(23) according to sign of immed value (positive or negative) 1174 Binary |= ((ARM_AM::getAM3Op(AM3Opc) == ARM_AM::add ? 1 : 0) << 1175 ARMII::U_BitShift); 1176 1177 // If this instr is in register offset/index encoding, set bit[3:0] 1178 // to the corresponding Rm register. 1179 if (MO2.getReg()) { 1180 Binary |= getARMRegisterNumbering(MO2.getReg()); 1181 emitWordLE(Binary); 1182 return; 1183 } 1184 1185 // This instr is in immediate offset/index encoding, set bit 22 to 1. 1186 Binary |= 1 << ARMII::AM3_I_BitShift; 1187 if (unsigned ImmOffs = ARM_AM::getAM3Offset(AM3Opc)) { 1188 // Set operands 1189 Binary |= (ImmOffs >> 4) << ARMII::ImmHiShift; // immedH 1190 Binary |= (ImmOffs & 0xF); // immedL 1191 } 1192 1193 emitWordLE(Binary); 1194} 1195 1196static unsigned getAddrModeUPBits(unsigned Mode) { 1197 unsigned Binary = 0; 1198 1199 // Set addressing mode by modifying bits U(23) and P(24) 1200 // IA - Increment after - bit U = 1 and bit P = 0 1201 // IB - Increment before - bit U = 1 and bit P = 1 1202 // DA - Decrement after - bit U = 0 and bit P = 0 1203 // DB - Decrement before - bit U = 0 and bit P = 1 1204 switch (Mode) { 1205 default: llvm_unreachable("Unknown addressing sub-mode!"); 1206 case ARM_AM::da: break; 1207 case ARM_AM::db: Binary |= 0x1 << ARMII::P_BitShift; break; 1208 case ARM_AM::ia: Binary |= 0x1 << ARMII::U_BitShift; break; 1209 case ARM_AM::ib: Binary |= 0x3 << ARMII::U_BitShift; break; 1210 } 1211 1212 return Binary; 1213} 1214 1215void ARMCodeEmitter::emitLoadStoreMultipleInstruction(const MachineInstr &MI) { 1216 const TargetInstrDesc &TID = MI.getDesc(); 1217 bool IsUpdating = (TID.TSFlags & ARMII::IndexModeMask) != 0; 1218 1219 // Part of binary is determined by TableGn. 1220 unsigned Binary = getBinaryCodeForInstr(MI); 1221 1222 // Set the conditional execution predicate 1223 Binary |= II->getPredicate(&MI) << ARMII::CondShift; 1224 1225 // Skip operand 0 of an instruction with base register update. 1226 unsigned OpIdx = 0; 1227 if (IsUpdating) 1228 ++OpIdx; 1229 1230 // Set base address operand 1231 Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRnShift; 1232 1233 // Set addressing mode by modifying bits U(23) and P(24) 1234 ARM_AM::AMSubMode Mode = ARM_AM::getLoadStoreMultipleSubMode(MI.getOpcode()); 1235 Binary |= getAddrModeUPBits(ARM_AM::getAM4SubMode(Mode)); 1236 1237 // Set bit W(21) 1238 if (IsUpdating) 1239 Binary |= 0x1 << ARMII::W_BitShift; 1240 1241 // Set registers 1242 for (unsigned i = OpIdx+2, e = MI.getNumOperands(); i != e; ++i) { 1243 const MachineOperand &MO = MI.getOperand(i); 1244 if (!MO.isReg() || MO.isImplicit()) 1245 break; 1246 unsigned RegNum = getARMRegisterNumbering(MO.getReg()); 1247 assert(TargetRegisterInfo::isPhysicalRegister(MO.getReg()) && 1248 RegNum < 16); 1249 Binary |= 0x1 << RegNum; 1250 } 1251 1252 emitWordLE(Binary); 1253} 1254 1255void ARMCodeEmitter::emitMulFrmInstruction(const MachineInstr &MI) { 1256 const TargetInstrDesc &TID = MI.getDesc(); 1257 1258 // Part of binary is determined by TableGn. 1259 unsigned Binary = getBinaryCodeForInstr(MI); 1260 1261 // Set the conditional execution predicate 1262 Binary |= II->getPredicate(&MI) << ARMII::CondShift; 1263 1264 // Encode S bit if MI modifies CPSR. 1265 Binary |= getAddrModeSBit(MI, TID); 1266 1267 // 32x32->64bit operations have two destination registers. The number 1268 // of register definitions will tell us if that's what we're dealing with. 1269 unsigned OpIdx = 0; 1270 if (TID.getNumDefs() == 2) 1271 Binary |= getMachineOpValue (MI, OpIdx++) << ARMII::RegRdLoShift; 1272 1273 // Encode Rd 1274 Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRdHiShift; 1275 1276 // Encode Rm 1277 Binary |= getMachineOpValue(MI, OpIdx++); 1278 1279 // Encode Rs 1280 Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRsShift; 1281 1282 // Many multiple instructions (e.g. MLA) have three src operands. Encode 1283 // it as Rn (for multiply, that's in the same offset as RdLo. 1284 if (TID.getNumOperands() > OpIdx && 1285 !TID.OpInfo[OpIdx].isPredicate() && 1286 !TID.OpInfo[OpIdx].isOptionalDef()) 1287 Binary |= getMachineOpValue(MI, OpIdx) << ARMII::RegRdLoShift; 1288 1289 emitWordLE(Binary); 1290} 1291 1292void ARMCodeEmitter::emitExtendInstruction(const MachineInstr &MI) { 1293 const TargetInstrDesc &TID = MI.getDesc(); 1294 1295 // Part of binary is determined by TableGn. 1296 unsigned Binary = getBinaryCodeForInstr(MI); 1297 1298 // Set the conditional execution predicate 1299 Binary |= II->getPredicate(&MI) << ARMII::CondShift; 1300 1301 unsigned OpIdx = 0; 1302 1303 // Encode Rd 1304 Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRdShift; 1305 1306 const MachineOperand &MO1 = MI.getOperand(OpIdx++); 1307 const MachineOperand &MO2 = MI.getOperand(OpIdx); 1308 if (MO2.isReg()) { 1309 // Two register operand form. 1310 // Encode Rn. 1311 Binary |= getMachineOpValue(MI, MO1) << ARMII::RegRnShift; 1312 1313 // Encode Rm. 1314 Binary |= getMachineOpValue(MI, MO2); 1315 ++OpIdx; 1316 } else { 1317 Binary |= getMachineOpValue(MI, MO1); 1318 } 1319 1320 // Encode rot imm (0, 8, 16, or 24) if it has a rotate immediate operand. 1321 if (MI.getOperand(OpIdx).isImm() && 1322 !TID.OpInfo[OpIdx].isPredicate() && 1323 !TID.OpInfo[OpIdx].isOptionalDef()) 1324 Binary |= (getMachineOpValue(MI, OpIdx) / 8) << ARMII::ExtRotImmShift; 1325 1326 emitWordLE(Binary); 1327} 1328 1329void ARMCodeEmitter::emitMiscArithInstruction(const MachineInstr &MI) { 1330 const TargetInstrDesc &TID = MI.getDesc(); 1331 1332 // Part of binary is determined by TableGn. 1333 unsigned Binary = getBinaryCodeForInstr(MI); 1334 1335 // Set the conditional execution predicate 1336 Binary |= II->getPredicate(&MI) << ARMII::CondShift; 1337 1338 unsigned OpIdx = 0; 1339 1340 // Encode Rd 1341 Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRdShift; 1342 1343 const MachineOperand &MO = MI.getOperand(OpIdx++); 1344 if (OpIdx == TID.getNumOperands() || 1345 TID.OpInfo[OpIdx].isPredicate() || 1346 TID.OpInfo[OpIdx].isOptionalDef()) { 1347 // Encode Rm and it's done. 1348 Binary |= getMachineOpValue(MI, MO); 1349 emitWordLE(Binary); 1350 return; 1351 } 1352 1353 // Encode Rn. 1354 Binary |= getMachineOpValue(MI, MO) << ARMII::RegRnShift; 1355 1356 // Encode Rm. 1357 Binary |= getMachineOpValue(MI, OpIdx++); 1358 1359 // Encode shift_imm. 1360 unsigned ShiftAmt = MI.getOperand(OpIdx).getImm(); 1361 if (TID.Opcode == ARM::PKHTB) { 1362 assert(ShiftAmt != 0 && "PKHTB shift_imm is 0!"); 1363 if (ShiftAmt == 32) 1364 ShiftAmt = 0; 1365 } 1366 assert(ShiftAmt < 32 && "shift_imm range is 0 to 31!"); 1367 Binary |= ShiftAmt << ARMII::ShiftShift; 1368 1369 emitWordLE(Binary); 1370} 1371 1372void ARMCodeEmitter::emitSaturateInstruction(const MachineInstr &MI) { 1373 const TargetInstrDesc &TID = MI.getDesc(); 1374 1375 // Part of binary is determined by TableGen. 1376 unsigned Binary = getBinaryCodeForInstr(MI); 1377 1378 // Set the conditional execution predicate 1379 Binary |= II->getPredicate(&MI) << ARMII::CondShift; 1380 1381 // Encode Rd 1382 Binary |= getMachineOpValue(MI, 0) << ARMII::RegRdShift; 1383 1384 // Encode saturate bit position. 1385 unsigned Pos = MI.getOperand(1).getImm(); 1386 if (TID.Opcode == ARM::SSAT || TID.Opcode == ARM::SSAT16) 1387 Pos -= 1; 1388 assert((Pos < 16 || (Pos < 32 && 1389 TID.Opcode != ARM::SSAT16 && 1390 TID.Opcode != ARM::USAT16)) && 1391 "saturate bit position out of range"); 1392 Binary |= Pos << 16; 1393 1394 // Encode Rm 1395 Binary |= getMachineOpValue(MI, 2); 1396 1397 // Encode shift_imm. 1398 if (TID.getNumOperands() == 4) { 1399 unsigned ShiftOp = MI.getOperand(3).getImm(); 1400 ARM_AM::ShiftOpc Opc = ARM_AM::getSORegShOp(ShiftOp); 1401 if (Opc == ARM_AM::asr) 1402 Binary |= (1 << 6); 1403 unsigned ShiftAmt = MI.getOperand(3).getImm(); 1404 if (ShiftAmt == 32 && Opc == ARM_AM::asr) 1405 ShiftAmt = 0; 1406 assert(ShiftAmt < 32 && "shift_imm range is 0 to 31!"); 1407 Binary |= ShiftAmt << ARMII::ShiftShift; 1408 } 1409 1410 emitWordLE(Binary); 1411} 1412 1413void ARMCodeEmitter::emitBranchInstruction(const MachineInstr &MI) { 1414 const TargetInstrDesc &TID = MI.getDesc(); 1415 1416 if (TID.Opcode == ARM::TPsoft) { 1417 llvm_unreachable("ARM::TPsoft FIXME"); // FIXME 1418 } 1419 1420 // Part of binary is determined by TableGn. 1421 unsigned Binary = getBinaryCodeForInstr(MI); 1422 1423 // Set the conditional execution predicate 1424 Binary |= II->getPredicate(&MI) << ARMII::CondShift; 1425 1426 // Set signed_immed_24 field 1427 Binary |= getMachineOpValue(MI, 0); 1428 1429 emitWordLE(Binary); 1430} 1431 1432void ARMCodeEmitter::emitInlineJumpTable(unsigned JTIndex) { 1433 // Remember the base address of the inline jump table. 1434 uintptr_t JTBase = MCE.getCurrentPCValue(); 1435 JTI->addJumpTableBaseAddr(JTIndex, JTBase); 1436 DEBUG(errs() << " ** Jump Table #" << JTIndex << " @ " << (void*)JTBase 1437 << '\n'); 1438 1439 // Now emit the jump table entries. 1440 const std::vector<MachineBasicBlock*> &MBBs = (*MJTEs)[JTIndex].MBBs; 1441 for (unsigned i = 0, e = MBBs.size(); i != e; ++i) { 1442 if (IsPIC) 1443 // DestBB address - JT base. 1444 emitMachineBasicBlock(MBBs[i], ARM::reloc_arm_pic_jt, JTBase); 1445 else 1446 // Absolute DestBB address. 1447 emitMachineBasicBlock(MBBs[i], ARM::reloc_arm_absolute); 1448 emitWordLE(0); 1449 } 1450} 1451 1452void ARMCodeEmitter::emitMiscBranchInstruction(const MachineInstr &MI) { 1453 const TargetInstrDesc &TID = MI.getDesc(); 1454 1455 // Handle jump tables. 1456 if (TID.Opcode == ARM::BR_JTr || TID.Opcode == ARM::BR_JTadd) { 1457 // First emit a ldr pc, [] instruction. 1458 emitDataProcessingInstruction(MI, ARM::PC); 1459 1460 // Then emit the inline jump table. 1461 unsigned JTIndex = 1462 (TID.Opcode == ARM::BR_JTr) 1463 ? MI.getOperand(1).getIndex() : MI.getOperand(2).getIndex(); 1464 emitInlineJumpTable(JTIndex); 1465 return; 1466 } else if (TID.Opcode == ARM::BR_JTm) { 1467 // First emit a ldr pc, [] instruction. 1468 emitLoadStoreInstruction(MI, ARM::PC); 1469 1470 // Then emit the inline jump table. 1471 emitInlineJumpTable(MI.getOperand(3).getIndex()); 1472 return; 1473 } 1474 1475 // Part of binary is determined by TableGn. 1476 unsigned Binary = getBinaryCodeForInstr(MI); 1477 1478 // Set the conditional execution predicate 1479 Binary |= II->getPredicate(&MI) << ARMII::CondShift; 1480 1481 if (TID.Opcode == ARM::BX_RET || TID.Opcode == ARM::MOVPCLR) 1482 // The return register is LR. 1483 Binary |= getARMRegisterNumbering(ARM::LR); 1484 else 1485 // otherwise, set the return register 1486 Binary |= getMachineOpValue(MI, 0); 1487 1488 emitWordLE(Binary); 1489} 1490 1491static unsigned encodeVFPRd(const MachineInstr &MI, unsigned OpIdx) { 1492 unsigned RegD = MI.getOperand(OpIdx).getReg(); 1493 unsigned Binary = 0; 1494 bool isSPVFP = ARM::SPRRegisterClass->contains(RegD); 1495 RegD = getARMRegisterNumbering(RegD); 1496 if (!isSPVFP) 1497 Binary |= RegD << ARMII::RegRdShift; 1498 else { 1499 Binary |= ((RegD & 0x1E) >> 1) << ARMII::RegRdShift; 1500 Binary |= (RegD & 0x01) << ARMII::D_BitShift; 1501 } 1502 return Binary; 1503} 1504 1505static unsigned encodeVFPRn(const MachineInstr &MI, unsigned OpIdx) { 1506 unsigned RegN = MI.getOperand(OpIdx).getReg(); 1507 unsigned Binary = 0; 1508 bool isSPVFP = ARM::SPRRegisterClass->contains(RegN); 1509 RegN = getARMRegisterNumbering(RegN); 1510 if (!isSPVFP) 1511 Binary |= RegN << ARMII::RegRnShift; 1512 else { 1513 Binary |= ((RegN & 0x1E) >> 1) << ARMII::RegRnShift; 1514 Binary |= (RegN & 0x01) << ARMII::N_BitShift; 1515 } 1516 return Binary; 1517} 1518 1519static unsigned encodeVFPRm(const MachineInstr &MI, unsigned OpIdx) { 1520 unsigned RegM = MI.getOperand(OpIdx).getReg(); 1521 unsigned Binary = 0; 1522 bool isSPVFP = ARM::SPRRegisterClass->contains(RegM); 1523 RegM = getARMRegisterNumbering(RegM); 1524 if (!isSPVFP) 1525 Binary |= RegM; 1526 else { 1527 Binary |= ((RegM & 0x1E) >> 1); 1528 Binary |= (RegM & 0x01) << ARMII::M_BitShift; 1529 } 1530 return Binary; 1531} 1532 1533void ARMCodeEmitter::emitVFPArithInstruction(const MachineInstr &MI) { 1534 const TargetInstrDesc &TID = MI.getDesc(); 1535 1536 // Part of binary is determined by TableGn. 1537 unsigned Binary = getBinaryCodeForInstr(MI); 1538 1539 // Set the conditional execution predicate 1540 Binary |= II->getPredicate(&MI) << ARMII::CondShift; 1541 1542 unsigned OpIdx = 0; 1543 assert((Binary & ARMII::D_BitShift) == 0 && 1544 (Binary & ARMII::N_BitShift) == 0 && 1545 (Binary & ARMII::M_BitShift) == 0 && "VFP encoding bug!"); 1546 1547 // Encode Dd / Sd. 1548 Binary |= encodeVFPRd(MI, OpIdx++); 1549 1550 // If this is a two-address operand, skip it, e.g. FMACD. 1551 if (TID.getOperandConstraint(OpIdx, TOI::TIED_TO) != -1) 1552 ++OpIdx; 1553 1554 // Encode Dn / Sn. 1555 if ((TID.TSFlags & ARMII::FormMask) == ARMII::VFPBinaryFrm) 1556 Binary |= encodeVFPRn(MI, OpIdx++); 1557 1558 if (OpIdx == TID.getNumOperands() || 1559 TID.OpInfo[OpIdx].isPredicate() || 1560 TID.OpInfo[OpIdx].isOptionalDef()) { 1561 // FCMPEZD etc. has only one operand. 1562 emitWordLE(Binary); 1563 return; 1564 } 1565 1566 // Encode Dm / Sm. 1567 Binary |= encodeVFPRm(MI, OpIdx); 1568 1569 emitWordLE(Binary); 1570} 1571 1572void ARMCodeEmitter::emitVFPConversionInstruction(const MachineInstr &MI) { 1573 const TargetInstrDesc &TID = MI.getDesc(); 1574 unsigned Form = TID.TSFlags & ARMII::FormMask; 1575 1576 // Part of binary is determined by TableGn. 1577 unsigned Binary = getBinaryCodeForInstr(MI); 1578 1579 // Set the conditional execution predicate 1580 Binary |= II->getPredicate(&MI) << ARMII::CondShift; 1581 1582 switch (Form) { 1583 default: break; 1584 case ARMII::VFPConv1Frm: 1585 case ARMII::VFPConv2Frm: 1586 case ARMII::VFPConv3Frm: 1587 // Encode Dd / Sd. 1588 Binary |= encodeVFPRd(MI, 0); 1589 break; 1590 case ARMII::VFPConv4Frm: 1591 // Encode Dn / Sn. 1592 Binary |= encodeVFPRn(MI, 0); 1593 break; 1594 case ARMII::VFPConv5Frm: 1595 // Encode Dm / Sm. 1596 Binary |= encodeVFPRm(MI, 0); 1597 break; 1598 } 1599 1600 switch (Form) { 1601 default: break; 1602 case ARMII::VFPConv1Frm: 1603 // Encode Dm / Sm. 1604 Binary |= encodeVFPRm(MI, 1); 1605 break; 1606 case ARMII::VFPConv2Frm: 1607 case ARMII::VFPConv3Frm: 1608 // Encode Dn / Sn. 1609 Binary |= encodeVFPRn(MI, 1); 1610 break; 1611 case ARMII::VFPConv4Frm: 1612 case ARMII::VFPConv5Frm: 1613 // Encode Dd / Sd. 1614 Binary |= encodeVFPRd(MI, 1); 1615 break; 1616 } 1617 1618 if (Form == ARMII::VFPConv5Frm) 1619 // Encode Dn / Sn. 1620 Binary |= encodeVFPRn(MI, 2); 1621 else if (Form == ARMII::VFPConv3Frm) 1622 // Encode Dm / Sm. 1623 Binary |= encodeVFPRm(MI, 2); 1624 1625 emitWordLE(Binary); 1626} 1627 1628void ARMCodeEmitter::emitVFPLoadStoreInstruction(const MachineInstr &MI) { 1629 // Part of binary is determined by TableGn. 1630 unsigned Binary = getBinaryCodeForInstr(MI); 1631 1632 // Set the conditional execution predicate 1633 Binary |= II->getPredicate(&MI) << ARMII::CondShift; 1634 1635 unsigned OpIdx = 0; 1636 1637 // Encode Dd / Sd. 1638 Binary |= encodeVFPRd(MI, OpIdx++); 1639 1640 // Encode address base. 1641 const MachineOperand &Base = MI.getOperand(OpIdx++); 1642 Binary |= getMachineOpValue(MI, Base) << ARMII::RegRnShift; 1643 1644 // If there is a non-zero immediate offset, encode it. 1645 if (Base.isReg()) { 1646 const MachineOperand &Offset = MI.getOperand(OpIdx); 1647 if (unsigned ImmOffs = ARM_AM::getAM5Offset(Offset.getImm())) { 1648 if (ARM_AM::getAM5Op(Offset.getImm()) == ARM_AM::add) 1649 Binary |= 1 << ARMII::U_BitShift; 1650 Binary |= ImmOffs; 1651 emitWordLE(Binary); 1652 return; 1653 } 1654 } 1655 1656 // If immediate offset is omitted, default to +0. 1657 Binary |= 1 << ARMII::U_BitShift; 1658 1659 emitWordLE(Binary); 1660} 1661 1662void 1663ARMCodeEmitter::emitVFPLoadStoreMultipleInstruction(const MachineInstr &MI) { 1664 const TargetInstrDesc &TID = MI.getDesc(); 1665 bool IsUpdating = (TID.TSFlags & ARMII::IndexModeMask) != 0; 1666 1667 // Part of binary is determined by TableGn. 1668 unsigned Binary = getBinaryCodeForInstr(MI); 1669 1670 // Set the conditional execution predicate 1671 Binary |= II->getPredicate(&MI) << ARMII::CondShift; 1672 1673 // Skip operand 0 of an instruction with base register update. 1674 unsigned OpIdx = 0; 1675 if (IsUpdating) 1676 ++OpIdx; 1677 1678 // Set base address operand 1679 Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRnShift; 1680 1681 // Set addressing mode by modifying bits U(23) and P(24) 1682 ARM_AM::AMSubMode Mode = ARM_AM::getLoadStoreMultipleSubMode(MI.getOpcode()); 1683 Binary |= getAddrModeUPBits(ARM_AM::getAM4SubMode(Mode)); 1684 1685 // Set bit W(21) 1686 if (IsUpdating) 1687 Binary |= 0x1 << ARMII::W_BitShift; 1688 1689 // First register is encoded in Dd. 1690 Binary |= encodeVFPRd(MI, OpIdx+2); 1691 1692 // Count the number of registers. 1693 unsigned NumRegs = 1; 1694 for (unsigned i = OpIdx+3, e = MI.getNumOperands(); i != e; ++i) { 1695 const MachineOperand &MO = MI.getOperand(i); 1696 if (!MO.isReg() || MO.isImplicit()) 1697 break; 1698 ++NumRegs; 1699 } 1700 // Bit 8 will be set if <list> is consecutive 64-bit registers (e.g., D0) 1701 // Otherwise, it will be 0, in the case of 32-bit registers. 1702 if(Binary & 0x100) 1703 Binary |= NumRegs * 2; 1704 else 1705 Binary |= NumRegs; 1706 1707 emitWordLE(Binary); 1708} 1709 1710static unsigned encodeNEONRd(const MachineInstr &MI, unsigned OpIdx) { 1711 unsigned RegD = MI.getOperand(OpIdx).getReg(); 1712 unsigned Binary = 0; 1713 RegD = getARMRegisterNumbering(RegD); 1714 Binary |= (RegD & 0xf) << ARMII::RegRdShift; 1715 Binary |= ((RegD >> 4) & 1) << ARMII::D_BitShift; 1716 return Binary; 1717} 1718 1719static unsigned encodeNEONRn(const MachineInstr &MI, unsigned OpIdx) { 1720 unsigned RegN = MI.getOperand(OpIdx).getReg(); 1721 unsigned Binary = 0; 1722 RegN = getARMRegisterNumbering(RegN); 1723 Binary |= (RegN & 0xf) << ARMII::RegRnShift; 1724 Binary |= ((RegN >> 4) & 1) << ARMII::N_BitShift; 1725 return Binary; 1726} 1727 1728static unsigned encodeNEONRm(const MachineInstr &MI, unsigned OpIdx) { 1729 unsigned RegM = MI.getOperand(OpIdx).getReg(); 1730 unsigned Binary = 0; 1731 RegM = getARMRegisterNumbering(RegM); 1732 Binary |= (RegM & 0xf); 1733 Binary |= ((RegM >> 4) & 1) << ARMII::M_BitShift; 1734 return Binary; 1735} 1736 1737/// convertNEONDataProcToThumb - Convert the ARM mode encoding for a NEON 1738/// data-processing instruction to the corresponding Thumb encoding. 1739static unsigned convertNEONDataProcToThumb(unsigned Binary) { 1740 assert((Binary & 0xfe000000) == 0xf2000000 && 1741 "not an ARM NEON data-processing instruction"); 1742 unsigned UBit = (Binary >> 24) & 1; 1743 return 0xef000000 | (UBit << 28) | (Binary & 0xffffff); 1744} 1745 1746void ARMCodeEmitter::emitNEONLaneInstruction(const MachineInstr &MI) { 1747 unsigned Binary = getBinaryCodeForInstr(MI); 1748 1749 unsigned RegTOpIdx, RegNOpIdx, LnOpIdx; 1750 const TargetInstrDesc &TID = MI.getDesc(); 1751 if ((TID.TSFlags & ARMII::FormMask) == ARMII::NGetLnFrm) { 1752 RegTOpIdx = 0; 1753 RegNOpIdx = 1; 1754 LnOpIdx = 2; 1755 } else { // ARMII::NSetLnFrm 1756 RegTOpIdx = 2; 1757 RegNOpIdx = 0; 1758 LnOpIdx = 3; 1759 } 1760 1761 // Set the conditional execution predicate 1762 Binary |= (IsThumb ? ARMCC::AL : II->getPredicate(&MI)) << ARMII::CondShift; 1763 1764 unsigned RegT = MI.getOperand(RegTOpIdx).getReg(); 1765 RegT = getARMRegisterNumbering(RegT); 1766 Binary |= (RegT << ARMII::RegRdShift); 1767 Binary |= encodeNEONRn(MI, RegNOpIdx); 1768 1769 unsigned LaneShift; 1770 if ((Binary & (1 << 22)) != 0) 1771 LaneShift = 0; // 8-bit elements 1772 else if ((Binary & (1 << 5)) != 0) 1773 LaneShift = 1; // 16-bit elements 1774 else 1775 LaneShift = 2; // 32-bit elements 1776 1777 unsigned Lane = MI.getOperand(LnOpIdx).getImm() << LaneShift; 1778 unsigned Opc1 = Lane >> 2; 1779 unsigned Opc2 = Lane & 3; 1780 assert((Opc1 & 3) == 0 && "out-of-range lane number operand"); 1781 Binary |= (Opc1 << 21); 1782 Binary |= (Opc2 << 5); 1783 1784 emitWordLE(Binary); 1785} 1786 1787void ARMCodeEmitter::emitNEONDupInstruction(const MachineInstr &MI) { 1788 unsigned Binary = getBinaryCodeForInstr(MI); 1789 1790 // Set the conditional execution predicate 1791 Binary |= (IsThumb ? ARMCC::AL : II->getPredicate(&MI)) << ARMII::CondShift; 1792 1793 unsigned RegT = MI.getOperand(1).getReg(); 1794 RegT = getARMRegisterNumbering(RegT); 1795 Binary |= (RegT << ARMII::RegRdShift); 1796 Binary |= encodeNEONRn(MI, 0); 1797 emitWordLE(Binary); 1798} 1799 1800void ARMCodeEmitter::emitNEON1RegModImmInstruction(const MachineInstr &MI) { 1801 unsigned Binary = getBinaryCodeForInstr(MI); 1802 // Destination register is encoded in Dd. 1803 Binary |= encodeNEONRd(MI, 0); 1804 // Immediate fields: Op, Cmode, I, Imm3, Imm4 1805 unsigned Imm = MI.getOperand(1).getImm(); 1806 unsigned Op = (Imm >> 12) & 1; 1807 unsigned Cmode = (Imm >> 8) & 0xf; 1808 unsigned I = (Imm >> 7) & 1; 1809 unsigned Imm3 = (Imm >> 4) & 0x7; 1810 unsigned Imm4 = Imm & 0xf; 1811 Binary |= (I << 24) | (Imm3 << 16) | (Cmode << 8) | (Op << 5) | Imm4; 1812 if (IsThumb) 1813 Binary = convertNEONDataProcToThumb(Binary); 1814 emitWordLE(Binary); 1815} 1816 1817void ARMCodeEmitter::emitNEON2RegInstruction(const MachineInstr &MI) { 1818 const TargetInstrDesc &TID = MI.getDesc(); 1819 unsigned Binary = getBinaryCodeForInstr(MI); 1820 // Destination register is encoded in Dd; source register in Dm. 1821 unsigned OpIdx = 0; 1822 Binary |= encodeNEONRd(MI, OpIdx++); 1823 if (TID.getOperandConstraint(OpIdx, TOI::TIED_TO) != -1) 1824 ++OpIdx; 1825 Binary |= encodeNEONRm(MI, OpIdx); 1826 if (IsThumb) 1827 Binary = convertNEONDataProcToThumb(Binary); 1828 // FIXME: This does not handle VDUPfdf or VDUPfqf. 1829 emitWordLE(Binary); 1830} 1831 1832void ARMCodeEmitter::emitNEON3RegInstruction(const MachineInstr &MI) { 1833 const TargetInstrDesc &TID = MI.getDesc(); 1834 unsigned Binary = getBinaryCodeForInstr(MI); 1835 // Destination register is encoded in Dd; source registers in Dn and Dm. 1836 unsigned OpIdx = 0; 1837 Binary |= encodeNEONRd(MI, OpIdx++); 1838 if (TID.getOperandConstraint(OpIdx, TOI::TIED_TO) != -1) 1839 ++OpIdx; 1840 Binary |= encodeNEONRn(MI, OpIdx++); 1841 if (TID.getOperandConstraint(OpIdx, TOI::TIED_TO) != -1) 1842 ++OpIdx; 1843 Binary |= encodeNEONRm(MI, OpIdx); 1844 if (IsThumb) 1845 Binary = convertNEONDataProcToThumb(Binary); 1846 // FIXME: This does not handle VMOVDneon or VMOVQ. 1847 emitWordLE(Binary); 1848} 1849 1850#include "ARMGenCodeEmitter.inc" 1851