ARMCodeEmitter.cpp revision a06694d3d85c7a604ef0068b687cd5f28a903173
1//===-- ARM/ARMCodeEmitter.cpp - Convert ARM code to machine code ---------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file contains the pass that transforms the ARM machine instructions into 11// relocatable machine code. 12// 13//===----------------------------------------------------------------------===// 14 15#define DEBUG_TYPE "jit" 16#include "ARM.h" 17#include "ARMAddressingModes.h" 18#include "ARMConstantPoolValue.h" 19#include "ARMInstrInfo.h" 20#include "ARMRelocations.h" 21#include "ARMSubtarget.h" 22#include "ARMTargetMachine.h" 23#include "llvm/Constants.h" 24#include "llvm/DerivedTypes.h" 25#include "llvm/Function.h" 26#include "llvm/PassManager.h" 27#include "llvm/CodeGen/MachineCodeEmitter.h" 28#include "llvm/CodeGen/JITCodeEmitter.h" 29#include "llvm/CodeGen/ObjectCodeEmitter.h" 30#include "llvm/CodeGen/MachineConstantPool.h" 31#include "llvm/CodeGen/MachineFunctionPass.h" 32#include "llvm/CodeGen/MachineInstr.h" 33#include "llvm/CodeGen/MachineJumpTableInfo.h" 34#include "llvm/CodeGen/MachineModuleInfo.h" 35#include "llvm/CodeGen/Passes.h" 36#include "llvm/ADT/Statistic.h" 37#include "llvm/Support/Debug.h" 38#include "llvm/Support/ErrorHandling.h" 39#include "llvm/Support/raw_ostream.h" 40#ifndef NDEBUG 41#include <iomanip> 42#endif 43using namespace llvm; 44 45STATISTIC(NumEmitted, "Number of machine instructions emitted"); 46 47namespace { 48 49 class ARMCodeEmitter { 50 public: 51 /// getBinaryCodeForInstr - This function, generated by the 52 /// CodeEmitterGenerator using TableGen, produces the binary encoding for 53 /// machine instructions. 54 unsigned getBinaryCodeForInstr(const MachineInstr &MI); 55 }; 56 57 template<class CodeEmitter> 58 class Emitter : public MachineFunctionPass, public ARMCodeEmitter { 59 ARMJITInfo *JTI; 60 const ARMInstrInfo *II; 61 const TargetData *TD; 62 const ARMSubtarget *Subtarget; 63 TargetMachine &TM; 64 CodeEmitter &MCE; 65 const std::vector<MachineConstantPoolEntry> *MCPEs; 66 const std::vector<MachineJumpTableEntry> *MJTEs; 67 bool IsPIC; 68 69 void getAnalysisUsage(AnalysisUsage &AU) const { 70 AU.addRequired<MachineModuleInfo>(); 71 MachineFunctionPass::getAnalysisUsage(AU); 72 } 73 74 public: 75 static char ID; 76 explicit Emitter(TargetMachine &tm, CodeEmitter &mce) 77 : MachineFunctionPass(&ID), JTI(0), II(0), TD(0), TM(tm), 78 MCE(mce), MCPEs(0), MJTEs(0), 79 IsPIC(TM.getRelocationModel() == Reloc::PIC_) {} 80 Emitter(TargetMachine &tm, CodeEmitter &mce, 81 const ARMInstrInfo &ii, const TargetData &td) 82 : MachineFunctionPass(&ID), JTI(0), II(&ii), TD(&td), TM(tm), 83 MCE(mce), MCPEs(0), MJTEs(0), 84 IsPIC(TM.getRelocationModel() == Reloc::PIC_) {} 85 86 bool runOnMachineFunction(MachineFunction &MF); 87 88 virtual const char *getPassName() const { 89 return "ARM Machine Code Emitter"; 90 } 91 92 void emitInstruction(const MachineInstr &MI); 93 94 private: 95 96 void emitWordLE(unsigned Binary); 97 98 void emitDWordLE(uint64_t Binary); 99 100 void emitConstPoolInstruction(const MachineInstr &MI); 101 102 void emitMOVi2piecesInstruction(const MachineInstr &MI); 103 104 void emitLEApcrelJTInstruction(const MachineInstr &MI); 105 106 void emitPseudoMoveInstruction(const MachineInstr &MI); 107 108 void addPCLabel(unsigned LabelID); 109 110 void emitPseudoInstruction(const MachineInstr &MI); 111 112 unsigned getMachineSoRegOpValue(const MachineInstr &MI, 113 const TargetInstrDesc &TID, 114 const MachineOperand &MO, 115 unsigned OpIdx); 116 117 unsigned getMachineSoImmOpValue(unsigned SoImm); 118 119 unsigned getAddrModeSBit(const MachineInstr &MI, 120 const TargetInstrDesc &TID) const; 121 122 void emitDataProcessingInstruction(const MachineInstr &MI, 123 unsigned ImplicitRd = 0, 124 unsigned ImplicitRn = 0); 125 126 void emitLoadStoreInstruction(const MachineInstr &MI, 127 unsigned ImplicitRd = 0, 128 unsigned ImplicitRn = 0); 129 130 void emitMiscLoadStoreInstruction(const MachineInstr &MI, 131 unsigned ImplicitRn = 0); 132 133 void emitLoadStoreMultipleInstruction(const MachineInstr &MI); 134 135 void emitMulFrmInstruction(const MachineInstr &MI); 136 137 void emitExtendInstruction(const MachineInstr &MI); 138 139 void emitMiscArithInstruction(const MachineInstr &MI); 140 141 void emitBranchInstruction(const MachineInstr &MI); 142 143 void emitInlineJumpTable(unsigned JTIndex); 144 145 void emitMiscBranchInstruction(const MachineInstr &MI); 146 147 void emitVFPArithInstruction(const MachineInstr &MI); 148 149 void emitVFPConversionInstruction(const MachineInstr &MI); 150 151 void emitVFPLoadStoreInstruction(const MachineInstr &MI); 152 153 void emitVFPLoadStoreMultipleInstruction(const MachineInstr &MI); 154 155 void emitMiscInstruction(const MachineInstr &MI); 156 157 /// getMachineOpValue - Return binary encoding of operand. If the machine 158 /// operand requires relocation, record the relocation and return zero. 159 unsigned getMachineOpValue(const MachineInstr &MI,const MachineOperand &MO); 160 unsigned getMachineOpValue(const MachineInstr &MI, unsigned OpIdx) { 161 return getMachineOpValue(MI, MI.getOperand(OpIdx)); 162 } 163 164 /// getShiftOp - Return the shift opcode (bit[6:5]) of the immediate value. 165 /// 166 unsigned getShiftOp(unsigned Imm) const ; 167 168 /// Routines that handle operands which add machine relocations which are 169 /// fixed up by the relocation stage. 170 void emitGlobalAddress(GlobalValue *GV, unsigned Reloc, 171 bool MayNeedFarStub, bool Indirect, 172 intptr_t ACPV = 0); 173 void emitExternalSymbolAddress(const char *ES, unsigned Reloc); 174 void emitConstPoolAddress(unsigned CPI, unsigned Reloc); 175 void emitJumpTableAddress(unsigned JTIndex, unsigned Reloc); 176 void emitMachineBasicBlock(MachineBasicBlock *BB, unsigned Reloc, 177 intptr_t JTBase = 0); 178 }; 179 template <class CodeEmitter> 180 char Emitter<CodeEmitter>::ID = 0; 181} 182 183/// createARMJITCodeEmitterPass - Return a pass that emits the collected ARM 184/// code to the specified MCE object. 185FunctionPass *llvm::createARMJITCodeEmitterPass(ARMBaseTargetMachine &TM, 186 JITCodeEmitter &JCE) { 187 return new Emitter<JITCodeEmitter>(TM, JCE); 188} 189 190template<class CodeEmitter> 191bool Emitter<CodeEmitter>::runOnMachineFunction(MachineFunction &MF) { 192 assert((MF.getTarget().getRelocationModel() != Reloc::Default || 193 MF.getTarget().getRelocationModel() != Reloc::Static) && 194 "JIT relocation model must be set to static or default!"); 195 JTI = ((ARMTargetMachine&)MF.getTarget()).getJITInfo(); 196 II = ((ARMTargetMachine&)MF.getTarget()).getInstrInfo(); 197 TD = ((ARMTargetMachine&)MF.getTarget()).getTargetData(); 198 Subtarget = &TM.getSubtarget<ARMSubtarget>(); 199 MCPEs = &MF.getConstantPool()->getConstants(); 200 MJTEs = 0; 201 if (MF.getJumpTableInfo()) MJTEs = &MF.getJumpTableInfo()->getJumpTables(); 202 IsPIC = TM.getRelocationModel() == Reloc::PIC_; 203 JTI->Initialize(MF, IsPIC); 204 MCE.setModuleInfo(&getAnalysis<MachineModuleInfo>()); 205 206 do { 207 DEBUG(errs() << "JITTing function '" 208 << MF.getFunction()->getName() << "'\n"); 209 MCE.startFunction(MF); 210 for (MachineFunction::iterator MBB = MF.begin(), E = MF.end(); 211 MBB != E; ++MBB) { 212 MCE.StartMachineBasicBlock(MBB); 213 for (MachineBasicBlock::const_iterator I = MBB->begin(), E = MBB->end(); 214 I != E; ++I) 215 emitInstruction(*I); 216 } 217 } while (MCE.finishFunction(MF)); 218 219 return false; 220} 221 222/// getShiftOp - Return the shift opcode (bit[6:5]) of the immediate value. 223/// 224template<class CodeEmitter> 225unsigned Emitter<CodeEmitter>::getShiftOp(unsigned Imm) const { 226 switch (ARM_AM::getAM2ShiftOpc(Imm)) { 227 default: llvm_unreachable("Unknown shift opc!"); 228 case ARM_AM::asr: return 2; 229 case ARM_AM::lsl: return 0; 230 case ARM_AM::lsr: return 1; 231 case ARM_AM::ror: 232 case ARM_AM::rrx: return 3; 233 } 234 return 0; 235} 236 237/// getMachineOpValue - Return binary encoding of operand. If the machine 238/// operand requires relocation, record the relocation and return zero. 239template<class CodeEmitter> 240unsigned Emitter<CodeEmitter>::getMachineOpValue(const MachineInstr &MI, 241 const MachineOperand &MO) { 242 if (MO.isReg()) 243 return ARMRegisterInfo::getRegisterNumbering(MO.getReg()); 244 else if (MO.isImm()) 245 return static_cast<unsigned>(MO.getImm()); 246 else if (MO.isGlobal()) 247 emitGlobalAddress(MO.getGlobal(), ARM::reloc_arm_branch, true, false); 248 else if (MO.isSymbol()) 249 emitExternalSymbolAddress(MO.getSymbolName(), ARM::reloc_arm_branch); 250 else if (MO.isCPI()) { 251 const TargetInstrDesc &TID = MI.getDesc(); 252 // For VFP load, the immediate offset is multiplied by 4. 253 unsigned Reloc = ((TID.TSFlags & ARMII::FormMask) == ARMII::VFPLdStFrm) 254 ? ARM::reloc_arm_vfp_cp_entry : ARM::reloc_arm_cp_entry; 255 emitConstPoolAddress(MO.getIndex(), Reloc); 256 } else if (MO.isJTI()) 257 emitJumpTableAddress(MO.getIndex(), ARM::reloc_arm_relative); 258 else if (MO.isMBB()) 259 emitMachineBasicBlock(MO.getMBB(), ARM::reloc_arm_branch); 260 else { 261#ifndef NDEBUG 262 errs() << MO; 263#endif 264 llvm_unreachable(0); 265 } 266 return 0; 267} 268 269/// emitGlobalAddress - Emit the specified address to the code stream. 270/// 271template<class CodeEmitter> 272void Emitter<CodeEmitter>::emitGlobalAddress(GlobalValue *GV, unsigned Reloc, 273 bool MayNeedFarStub, bool Indirect, 274 intptr_t ACPV) { 275 MachineRelocation MR = Indirect 276 ? MachineRelocation::getIndirectSymbol(MCE.getCurrentPCOffset(), Reloc, 277 GV, ACPV, MayNeedFarStub) 278 : MachineRelocation::getGV(MCE.getCurrentPCOffset(), Reloc, 279 GV, ACPV, MayNeedFarStub); 280 MCE.addRelocation(MR); 281} 282 283/// emitExternalSymbolAddress - Arrange for the address of an external symbol to 284/// be emitted to the current location in the function, and allow it to be PC 285/// relative. 286template<class CodeEmitter> 287void Emitter<CodeEmitter>::emitExternalSymbolAddress(const char *ES, 288 unsigned Reloc) { 289 MCE.addRelocation(MachineRelocation::getExtSym(MCE.getCurrentPCOffset(), 290 Reloc, ES)); 291} 292 293/// emitConstPoolAddress - Arrange for the address of an constant pool 294/// to be emitted to the current location in the function, and allow it to be PC 295/// relative. 296template<class CodeEmitter> 297void Emitter<CodeEmitter>::emitConstPoolAddress(unsigned CPI, 298 unsigned Reloc) { 299 // Tell JIT emitter we'll resolve the address. 300 MCE.addRelocation(MachineRelocation::getConstPool(MCE.getCurrentPCOffset(), 301 Reloc, CPI, 0, true)); 302} 303 304/// emitJumpTableAddress - Arrange for the address of a jump table to 305/// be emitted to the current location in the function, and allow it to be PC 306/// relative. 307template<class CodeEmitter> 308void Emitter<CodeEmitter>::emitJumpTableAddress(unsigned JTIndex, 309 unsigned Reloc) { 310 MCE.addRelocation(MachineRelocation::getJumpTable(MCE.getCurrentPCOffset(), 311 Reloc, JTIndex, 0, true)); 312} 313 314/// emitMachineBasicBlock - Emit the specified address basic block. 315template<class CodeEmitter> 316void Emitter<CodeEmitter>::emitMachineBasicBlock(MachineBasicBlock *BB, 317 unsigned Reloc, intptr_t JTBase) { 318 MCE.addRelocation(MachineRelocation::getBB(MCE.getCurrentPCOffset(), 319 Reloc, BB, JTBase)); 320} 321 322template<class CodeEmitter> 323void Emitter<CodeEmitter>::emitWordLE(unsigned Binary) { 324 DEBUG(errs() << " 0x"; 325 errs().write_hex(Binary) << "\n"); 326 MCE.emitWordLE(Binary); 327} 328 329template<class CodeEmitter> 330void Emitter<CodeEmitter>::emitDWordLE(uint64_t Binary) { 331 DEBUG(errs() << " 0x"; 332 errs().write_hex(Binary) << "\n"); 333 MCE.emitDWordLE(Binary); 334} 335 336template<class CodeEmitter> 337void Emitter<CodeEmitter>::emitInstruction(const MachineInstr &MI) { 338 DEBUG(errs() << "JIT: " << (void*)MCE.getCurrentPCValue() << ":\t" << MI); 339 340 MCE.processDebugLoc(MI.getDebugLoc(), true); 341 342 NumEmitted++; // Keep track of the # of mi's emitted 343 switch (MI.getDesc().TSFlags & ARMII::FormMask) { 344 default: { 345 llvm_unreachable("Unhandled instruction encoding format!"); 346 break; 347 } 348 case ARMII::Pseudo: 349 emitPseudoInstruction(MI); 350 break; 351 case ARMII::DPFrm: 352 case ARMII::DPSoRegFrm: 353 emitDataProcessingInstruction(MI); 354 break; 355 case ARMII::LdFrm: 356 case ARMII::StFrm: 357 emitLoadStoreInstruction(MI); 358 break; 359 case ARMII::LdMiscFrm: 360 case ARMII::StMiscFrm: 361 emitMiscLoadStoreInstruction(MI); 362 break; 363 case ARMII::LdStMulFrm: 364 emitLoadStoreMultipleInstruction(MI); 365 break; 366 case ARMII::MulFrm: 367 emitMulFrmInstruction(MI); 368 break; 369 case ARMII::ExtFrm: 370 emitExtendInstruction(MI); 371 break; 372 case ARMII::ArithMiscFrm: 373 emitMiscArithInstruction(MI); 374 break; 375 case ARMII::BrFrm: 376 emitBranchInstruction(MI); 377 break; 378 case ARMII::BrMiscFrm: 379 emitMiscBranchInstruction(MI); 380 break; 381 // VFP instructions. 382 case ARMII::VFPUnaryFrm: 383 case ARMII::VFPBinaryFrm: 384 emitVFPArithInstruction(MI); 385 break; 386 case ARMII::VFPConv1Frm: 387 case ARMII::VFPConv2Frm: 388 case ARMII::VFPConv3Frm: 389 case ARMII::VFPConv4Frm: 390 case ARMII::VFPConv5Frm: 391 emitVFPConversionInstruction(MI); 392 break; 393 case ARMII::VFPLdStFrm: 394 emitVFPLoadStoreInstruction(MI); 395 break; 396 case ARMII::VFPLdStMulFrm: 397 emitVFPLoadStoreMultipleInstruction(MI); 398 break; 399 case ARMII::VFPMiscFrm: 400 emitMiscInstruction(MI); 401 break; 402 } 403 MCE.processDebugLoc(MI.getDebugLoc(), false); 404} 405 406template<class CodeEmitter> 407void Emitter<CodeEmitter>::emitConstPoolInstruction(const MachineInstr &MI) { 408 unsigned CPI = MI.getOperand(0).getImm(); // CP instruction index. 409 unsigned CPIndex = MI.getOperand(1).getIndex(); // Actual cp entry index. 410 const MachineConstantPoolEntry &MCPE = (*MCPEs)[CPIndex]; 411 412 // Remember the CONSTPOOL_ENTRY address for later relocation. 413 JTI->addConstantPoolEntryAddr(CPI, MCE.getCurrentPCValue()); 414 415 // Emit constpool island entry. In most cases, the actual values will be 416 // resolved and relocated after code emission. 417 if (MCPE.isMachineConstantPoolEntry()) { 418 ARMConstantPoolValue *ACPV = 419 static_cast<ARMConstantPoolValue*>(MCPE.Val.MachineCPVal); 420 421 DEBUG(errs() << " ** ARM constant pool #" << CPI << " @ " 422 << (void*)MCE.getCurrentPCValue() << " " << *ACPV << '\n'); 423 424 assert(ACPV->isGlobalValue() && "unsupported constant pool value"); 425 GlobalValue *GV = ACPV->getGV(); 426 if (GV) { 427 Reloc::Model RelocM = TM.getRelocationModel(); 428 emitGlobalAddress(GV, ARM::reloc_arm_machine_cp_entry, 429 isa<Function>(GV), 430 Subtarget->GVIsIndirectSymbol(GV, RelocM), 431 (intptr_t)ACPV); 432 } else { 433 emitExternalSymbolAddress(ACPV->getSymbol(), ARM::reloc_arm_absolute); 434 } 435 emitWordLE(0); 436 } else { 437 Constant *CV = MCPE.Val.ConstVal; 438 439 DEBUG({ 440 errs() << " ** Constant pool #" << CPI << " @ " 441 << (void*)MCE.getCurrentPCValue() << " "; 442 if (const Function *F = dyn_cast<Function>(CV)) 443 errs() << F->getName(); 444 else 445 errs() << *CV; 446 errs() << '\n'; 447 }); 448 449 if (GlobalValue *GV = dyn_cast<GlobalValue>(CV)) { 450 emitGlobalAddress(GV, ARM::reloc_arm_absolute, isa<Function>(GV), false); 451 emitWordLE(0); 452 } else if (const ConstantInt *CI = dyn_cast<ConstantInt>(CV)) { 453 uint32_t Val = *(uint32_t*)CI->getValue().getRawData(); 454 emitWordLE(Val); 455 } else if (const ConstantFP *CFP = dyn_cast<ConstantFP>(CV)) { 456 if (CFP->getType()->isFloatTy()) 457 emitWordLE(CFP->getValueAPF().bitcastToAPInt().getZExtValue()); 458 else if (CFP->getType()->isDoubleTy()) 459 emitDWordLE(CFP->getValueAPF().bitcastToAPInt().getZExtValue()); 460 else { 461 llvm_unreachable("Unable to handle this constantpool entry!"); 462 } 463 } else { 464 llvm_unreachable("Unable to handle this constantpool entry!"); 465 } 466 } 467} 468 469template<class CodeEmitter> 470void Emitter<CodeEmitter>::emitMOVi2piecesInstruction(const MachineInstr &MI) { 471 const MachineOperand &MO0 = MI.getOperand(0); 472 const MachineOperand &MO1 = MI.getOperand(1); 473 assert(MO1.isImm() && ARM_AM::getSOImmVal(MO1.isImm()) != -1 && 474 "Not a valid so_imm value!"); 475 unsigned V1 = ARM_AM::getSOImmTwoPartFirst(MO1.getImm()); 476 unsigned V2 = ARM_AM::getSOImmTwoPartSecond(MO1.getImm()); 477 478 // Emit the 'mov' instruction. 479 unsigned Binary = 0xd << 21; // mov: Insts{24-21} = 0b1101 480 481 // Set the conditional execution predicate. 482 Binary |= II->getPredicate(&MI) << ARMII::CondShift; 483 484 // Encode Rd. 485 Binary |= getMachineOpValue(MI, MO0) << ARMII::RegRdShift; 486 487 // Encode so_imm. 488 // Set bit I(25) to identify this is the immediate form of <shifter_op> 489 Binary |= 1 << ARMII::I_BitShift; 490 Binary |= getMachineSoImmOpValue(V1); 491 emitWordLE(Binary); 492 493 // Now the 'orr' instruction. 494 Binary = 0xc << 21; // orr: Insts{24-21} = 0b1100 495 496 // Set the conditional execution predicate. 497 Binary |= II->getPredicate(&MI) << ARMII::CondShift; 498 499 // Encode Rd. 500 Binary |= getMachineOpValue(MI, MO0) << ARMII::RegRdShift; 501 502 // Encode Rn. 503 Binary |= getMachineOpValue(MI, MO0) << ARMII::RegRnShift; 504 505 // Encode so_imm. 506 // Set bit I(25) to identify this is the immediate form of <shifter_op> 507 Binary |= 1 << ARMII::I_BitShift; 508 Binary |= getMachineSoImmOpValue(V2); 509 emitWordLE(Binary); 510} 511 512template<class CodeEmitter> 513void Emitter<CodeEmitter>::emitLEApcrelJTInstruction(const MachineInstr &MI) { 514 // It's basically add r, pc, (LJTI - $+8) 515 516 const TargetInstrDesc &TID = MI.getDesc(); 517 518 // Emit the 'add' instruction. 519 unsigned Binary = 0x4 << 21; // add: Insts{24-31} = 0b0100 520 521 // Set the conditional execution predicate 522 Binary |= II->getPredicate(&MI) << ARMII::CondShift; 523 524 // Encode S bit if MI modifies CPSR. 525 Binary |= getAddrModeSBit(MI, TID); 526 527 // Encode Rd. 528 Binary |= getMachineOpValue(MI, 0) << ARMII::RegRdShift; 529 530 // Encode Rn which is PC. 531 Binary |= ARMRegisterInfo::getRegisterNumbering(ARM::PC) << ARMII::RegRnShift; 532 533 // Encode the displacement. 534 Binary |= 1 << ARMII::I_BitShift; 535 emitJumpTableAddress(MI.getOperand(1).getIndex(), ARM::reloc_arm_jt_base); 536 537 emitWordLE(Binary); 538} 539 540template<class CodeEmitter> 541void Emitter<CodeEmitter>::emitPseudoMoveInstruction(const MachineInstr &MI) { 542 unsigned Opcode = MI.getDesc().Opcode; 543 544 // Part of binary is determined by TableGn. 545 unsigned Binary = getBinaryCodeForInstr(MI); 546 547 // Set the conditional execution predicate 548 Binary |= II->getPredicate(&MI) << ARMII::CondShift; 549 550 // Encode S bit if MI modifies CPSR. 551 if (Opcode == ARM::MOVsrl_flag || Opcode == ARM::MOVsra_flag) 552 Binary |= 1 << ARMII::S_BitShift; 553 554 // Encode register def if there is one. 555 Binary |= getMachineOpValue(MI, 0) << ARMII::RegRdShift; 556 557 // Encode the shift operation. 558 switch (Opcode) { 559 default: break; 560 case ARM::MOVrx: 561 // rrx 562 Binary |= 0x6 << 4; 563 break; 564 case ARM::MOVsrl_flag: 565 // lsr #1 566 Binary |= (0x2 << 4) | (1 << 7); 567 break; 568 case ARM::MOVsra_flag: 569 // asr #1 570 Binary |= (0x4 << 4) | (1 << 7); 571 break; 572 } 573 574 // Encode register Rm. 575 Binary |= getMachineOpValue(MI, 1); 576 577 emitWordLE(Binary); 578} 579 580template<class CodeEmitter> 581void Emitter<CodeEmitter>::addPCLabel(unsigned LabelID) { 582 DEBUG(errs() << " ** LPC" << LabelID << " @ " 583 << (void*)MCE.getCurrentPCValue() << '\n'); 584 JTI->addPCLabelAddr(LabelID, MCE.getCurrentPCValue()); 585} 586 587template<class CodeEmitter> 588void Emitter<CodeEmitter>::emitPseudoInstruction(const MachineInstr &MI) { 589 unsigned Opcode = MI.getDesc().Opcode; 590 switch (Opcode) { 591 default: 592 llvm_unreachable("ARMCodeEmitter::emitPseudoInstruction"); 593 // FIXME: Add support for MOVimm32. 594 case TargetInstrInfo::INLINEASM: { 595 // We allow inline assembler nodes with empty bodies - they can 596 // implicitly define registers, which is ok for JIT. 597 if (MI.getOperand(0).getSymbolName()[0]) { 598 llvm_report_error("JIT does not support inline asm!"); 599 } 600 break; 601 } 602 case TargetInstrInfo::DBG_LABEL: 603 case TargetInstrInfo::EH_LABEL: 604 MCE.emitLabel(MI.getOperand(0).getImm()); 605 break; 606 case TargetInstrInfo::IMPLICIT_DEF: 607 case TargetInstrInfo::KILL: 608 // Do nothing. 609 break; 610 case ARM::CONSTPOOL_ENTRY: 611 emitConstPoolInstruction(MI); 612 break; 613 case ARM::PICADD: { 614 // Remember of the address of the PC label for relocation later. 615 addPCLabel(MI.getOperand(2).getImm()); 616 // PICADD is just an add instruction that implicitly read pc. 617 emitDataProcessingInstruction(MI, 0, ARM::PC); 618 break; 619 } 620 case ARM::PICLDR: 621 case ARM::PICLDRB: 622 case ARM::PICSTR: 623 case ARM::PICSTRB: { 624 // Remember of the address of the PC label for relocation later. 625 addPCLabel(MI.getOperand(2).getImm()); 626 // These are just load / store instructions that implicitly read pc. 627 emitLoadStoreInstruction(MI, 0, ARM::PC); 628 break; 629 } 630 case ARM::PICLDRH: 631 case ARM::PICLDRSH: 632 case ARM::PICLDRSB: 633 case ARM::PICSTRH: { 634 // Remember of the address of the PC label for relocation later. 635 addPCLabel(MI.getOperand(2).getImm()); 636 // These are just load / store instructions that implicitly read pc. 637 emitMiscLoadStoreInstruction(MI, ARM::PC); 638 break; 639 } 640 case ARM::MOVi2pieces: 641 // Two instructions to materialize a constant. 642 emitMOVi2piecesInstruction(MI); 643 break; 644 case ARM::LEApcrelJT: 645 // Materialize jumptable address. 646 emitLEApcrelJTInstruction(MI); 647 break; 648 case ARM::MOVrx: 649 case ARM::MOVsrl_flag: 650 case ARM::MOVsra_flag: 651 emitPseudoMoveInstruction(MI); 652 break; 653 } 654} 655 656template<class CodeEmitter> 657unsigned Emitter<CodeEmitter>::getMachineSoRegOpValue( 658 const MachineInstr &MI, 659 const TargetInstrDesc &TID, 660 const MachineOperand &MO, 661 unsigned OpIdx) { 662 unsigned Binary = getMachineOpValue(MI, MO); 663 664 const MachineOperand &MO1 = MI.getOperand(OpIdx + 1); 665 const MachineOperand &MO2 = MI.getOperand(OpIdx + 2); 666 ARM_AM::ShiftOpc SOpc = ARM_AM::getSORegShOp(MO2.getImm()); 667 668 // Encode the shift opcode. 669 unsigned SBits = 0; 670 unsigned Rs = MO1.getReg(); 671 if (Rs) { 672 // Set shift operand (bit[7:4]). 673 // LSL - 0001 674 // LSR - 0011 675 // ASR - 0101 676 // ROR - 0111 677 // RRX - 0110 and bit[11:8] clear. 678 switch (SOpc) { 679 default: llvm_unreachable("Unknown shift opc!"); 680 case ARM_AM::lsl: SBits = 0x1; break; 681 case ARM_AM::lsr: SBits = 0x3; break; 682 case ARM_AM::asr: SBits = 0x5; break; 683 case ARM_AM::ror: SBits = 0x7; break; 684 case ARM_AM::rrx: SBits = 0x6; break; 685 } 686 } else { 687 // Set shift operand (bit[6:4]). 688 // LSL - 000 689 // LSR - 010 690 // ASR - 100 691 // ROR - 110 692 switch (SOpc) { 693 default: llvm_unreachable("Unknown shift opc!"); 694 case ARM_AM::lsl: SBits = 0x0; break; 695 case ARM_AM::lsr: SBits = 0x2; break; 696 case ARM_AM::asr: SBits = 0x4; break; 697 case ARM_AM::ror: SBits = 0x6; break; 698 } 699 } 700 Binary |= SBits << 4; 701 if (SOpc == ARM_AM::rrx) 702 return Binary; 703 704 // Encode the shift operation Rs or shift_imm (except rrx). 705 if (Rs) { 706 // Encode Rs bit[11:8]. 707 assert(ARM_AM::getSORegOffset(MO2.getImm()) == 0); 708 return Binary | 709 (ARMRegisterInfo::getRegisterNumbering(Rs) << ARMII::RegRsShift); 710 } 711 712 // Encode shift_imm bit[11:7]. 713 return Binary | ARM_AM::getSORegOffset(MO2.getImm()) << 7; 714} 715 716template<class CodeEmitter> 717unsigned Emitter<CodeEmitter>::getMachineSoImmOpValue(unsigned SoImm) { 718 int SoImmVal = ARM_AM::getSOImmVal(SoImm); 719 assert(SoImmVal != -1 && "Not a valid so_imm value!"); 720 721 // Encode rotate_imm. 722 unsigned Binary = (ARM_AM::getSOImmValRot((unsigned)SoImmVal) >> 1) 723 << ARMII::SoRotImmShift; 724 725 // Encode immed_8. 726 Binary |= ARM_AM::getSOImmValImm((unsigned)SoImmVal); 727 return Binary; 728} 729 730template<class CodeEmitter> 731unsigned Emitter<CodeEmitter>::getAddrModeSBit(const MachineInstr &MI, 732 const TargetInstrDesc &TID) const { 733 for (unsigned i = MI.getNumOperands(), e = TID.getNumOperands(); i != e; --i){ 734 const MachineOperand &MO = MI.getOperand(i-1); 735 if (MO.isReg() && MO.isDef() && MO.getReg() == ARM::CPSR) 736 return 1 << ARMII::S_BitShift; 737 } 738 return 0; 739} 740 741template<class CodeEmitter> 742void Emitter<CodeEmitter>::emitDataProcessingInstruction( 743 const MachineInstr &MI, 744 unsigned ImplicitRd, 745 unsigned ImplicitRn) { 746 const TargetInstrDesc &TID = MI.getDesc(); 747 748 if (TID.Opcode == ARM::BFC) { 749 llvm_report_error("ARMv6t2 JIT is not yet supported."); 750 } 751 752 // Part of binary is determined by TableGn. 753 unsigned Binary = getBinaryCodeForInstr(MI); 754 755 // Set the conditional execution predicate 756 Binary |= II->getPredicate(&MI) << ARMII::CondShift; 757 758 // Encode S bit if MI modifies CPSR. 759 Binary |= getAddrModeSBit(MI, TID); 760 761 // Encode register def if there is one. 762 unsigned NumDefs = TID.getNumDefs(); 763 unsigned OpIdx = 0; 764 if (NumDefs) 765 Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRdShift; 766 else if (ImplicitRd) 767 // Special handling for implicit use (e.g. PC). 768 Binary |= (ARMRegisterInfo::getRegisterNumbering(ImplicitRd) 769 << ARMII::RegRdShift); 770 771 // If this is a two-address operand, skip it. e.g. MOVCCr operand 1. 772 if (TID.getOperandConstraint(OpIdx, TOI::TIED_TO) != -1) 773 ++OpIdx; 774 775 // Encode first non-shifter register operand if there is one. 776 bool isUnary = TID.TSFlags & ARMII::UnaryDP; 777 if (!isUnary) { 778 if (ImplicitRn) 779 // Special handling for implicit use (e.g. PC). 780 Binary |= (ARMRegisterInfo::getRegisterNumbering(ImplicitRn) 781 << ARMII::RegRnShift); 782 else { 783 Binary |= getMachineOpValue(MI, OpIdx) << ARMII::RegRnShift; 784 ++OpIdx; 785 } 786 } 787 788 // Encode shifter operand. 789 const MachineOperand &MO = MI.getOperand(OpIdx); 790 if ((TID.TSFlags & ARMII::FormMask) == ARMII::DPSoRegFrm) { 791 // Encode SoReg. 792 emitWordLE(Binary | getMachineSoRegOpValue(MI, TID, MO, OpIdx)); 793 return; 794 } 795 796 if (MO.isReg()) { 797 // Encode register Rm. 798 emitWordLE(Binary | ARMRegisterInfo::getRegisterNumbering(MO.getReg())); 799 return; 800 } 801 802 // Encode so_imm. 803 Binary |= getMachineSoImmOpValue((unsigned)MO.getImm()); 804 805 emitWordLE(Binary); 806} 807 808template<class CodeEmitter> 809void Emitter<CodeEmitter>::emitLoadStoreInstruction( 810 const MachineInstr &MI, 811 unsigned ImplicitRd, 812 unsigned ImplicitRn) { 813 const TargetInstrDesc &TID = MI.getDesc(); 814 unsigned Form = TID.TSFlags & ARMII::FormMask; 815 bool IsPrePost = (TID.TSFlags & ARMII::IndexModeMask) != 0; 816 817 // Part of binary is determined by TableGn. 818 unsigned Binary = getBinaryCodeForInstr(MI); 819 820 // Set the conditional execution predicate 821 Binary |= II->getPredicate(&MI) << ARMII::CondShift; 822 823 unsigned OpIdx = 0; 824 825 // Operand 0 of a pre- and post-indexed store is the address base 826 // writeback. Skip it. 827 bool Skipped = false; 828 if (IsPrePost && Form == ARMII::StFrm) { 829 ++OpIdx; 830 Skipped = true; 831 } 832 833 // Set first operand 834 if (ImplicitRd) 835 // Special handling for implicit use (e.g. PC). 836 Binary |= (ARMRegisterInfo::getRegisterNumbering(ImplicitRd) 837 << ARMII::RegRdShift); 838 else 839 Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRdShift; 840 841 // Set second operand 842 if (ImplicitRn) 843 // Special handling for implicit use (e.g. PC). 844 Binary |= (ARMRegisterInfo::getRegisterNumbering(ImplicitRn) 845 << ARMII::RegRnShift); 846 else 847 Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRnShift; 848 849 // If this is a two-address operand, skip it. e.g. LDR_PRE. 850 if (!Skipped && TID.getOperandConstraint(OpIdx, TOI::TIED_TO) != -1) 851 ++OpIdx; 852 853 const MachineOperand &MO2 = MI.getOperand(OpIdx); 854 unsigned AM2Opc = (ImplicitRn == ARM::PC) 855 ? 0 : MI.getOperand(OpIdx+1).getImm(); 856 857 // Set bit U(23) according to sign of immed value (positive or negative). 858 Binary |= ((ARM_AM::getAM2Op(AM2Opc) == ARM_AM::add ? 1 : 0) << 859 ARMII::U_BitShift); 860 if (!MO2.getReg()) { // is immediate 861 if (ARM_AM::getAM2Offset(AM2Opc)) 862 // Set the value of offset_12 field 863 Binary |= ARM_AM::getAM2Offset(AM2Opc); 864 emitWordLE(Binary); 865 return; 866 } 867 868 // Set bit I(25), because this is not in immediate enconding. 869 Binary |= 1 << ARMII::I_BitShift; 870 assert(TargetRegisterInfo::isPhysicalRegister(MO2.getReg())); 871 // Set bit[3:0] to the corresponding Rm register 872 Binary |= ARMRegisterInfo::getRegisterNumbering(MO2.getReg()); 873 874 // If this instr is in scaled register offset/index instruction, set 875 // shift_immed(bit[11:7]) and shift(bit[6:5]) fields. 876 if (unsigned ShImm = ARM_AM::getAM2Offset(AM2Opc)) { 877 Binary |= getShiftOp(AM2Opc) << ARMII::ShiftImmShift; // shift 878 Binary |= ShImm << ARMII::ShiftShift; // shift_immed 879 } 880 881 emitWordLE(Binary); 882} 883 884template<class CodeEmitter> 885void Emitter<CodeEmitter>::emitMiscLoadStoreInstruction(const MachineInstr &MI, 886 unsigned ImplicitRn) { 887 const TargetInstrDesc &TID = MI.getDesc(); 888 unsigned Form = TID.TSFlags & ARMII::FormMask; 889 bool IsPrePost = (TID.TSFlags & ARMII::IndexModeMask) != 0; 890 891 // Part of binary is determined by TableGn. 892 unsigned Binary = getBinaryCodeForInstr(MI); 893 894 // Set the conditional execution predicate 895 Binary |= II->getPredicate(&MI) << ARMII::CondShift; 896 897 unsigned OpIdx = 0; 898 899 // Operand 0 of a pre- and post-indexed store is the address base 900 // writeback. Skip it. 901 bool Skipped = false; 902 if (IsPrePost && Form == ARMII::StMiscFrm) { 903 ++OpIdx; 904 Skipped = true; 905 } 906 907 // Set first operand 908 Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRdShift; 909 910 // Skip LDRD and STRD's second operand. 911 if (TID.Opcode == ARM::LDRD || TID.Opcode == ARM::STRD) 912 ++OpIdx; 913 914 // Set second operand 915 if (ImplicitRn) 916 // Special handling for implicit use (e.g. PC). 917 Binary |= (ARMRegisterInfo::getRegisterNumbering(ImplicitRn) 918 << ARMII::RegRnShift); 919 else 920 Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRnShift; 921 922 // If this is a two-address operand, skip it. e.g. LDRH_POST. 923 if (!Skipped && TID.getOperandConstraint(OpIdx, TOI::TIED_TO) != -1) 924 ++OpIdx; 925 926 const MachineOperand &MO2 = MI.getOperand(OpIdx); 927 unsigned AM3Opc = (ImplicitRn == ARM::PC) 928 ? 0 : MI.getOperand(OpIdx+1).getImm(); 929 930 // Set bit U(23) according to sign of immed value (positive or negative) 931 Binary |= ((ARM_AM::getAM3Op(AM3Opc) == ARM_AM::add ? 1 : 0) << 932 ARMII::U_BitShift); 933 934 // If this instr is in register offset/index encoding, set bit[3:0] 935 // to the corresponding Rm register. 936 if (MO2.getReg()) { 937 Binary |= ARMRegisterInfo::getRegisterNumbering(MO2.getReg()); 938 emitWordLE(Binary); 939 return; 940 } 941 942 // This instr is in immediate offset/index encoding, set bit 22 to 1. 943 Binary |= 1 << ARMII::AM3_I_BitShift; 944 if (unsigned ImmOffs = ARM_AM::getAM3Offset(AM3Opc)) { 945 // Set operands 946 Binary |= (ImmOffs >> 4) << ARMII::ImmHiShift; // immedH 947 Binary |= (ImmOffs & 0xF); // immedL 948 } 949 950 emitWordLE(Binary); 951} 952 953static unsigned getAddrModeUPBits(unsigned Mode) { 954 unsigned Binary = 0; 955 956 // Set addressing mode by modifying bits U(23) and P(24) 957 // IA - Increment after - bit U = 1 and bit P = 0 958 // IB - Increment before - bit U = 1 and bit P = 1 959 // DA - Decrement after - bit U = 0 and bit P = 0 960 // DB - Decrement before - bit U = 0 and bit P = 1 961 switch (Mode) { 962 default: llvm_unreachable("Unknown addressing sub-mode!"); 963 case ARM_AM::da: break; 964 case ARM_AM::db: Binary |= 0x1 << ARMII::P_BitShift; break; 965 case ARM_AM::ia: Binary |= 0x1 << ARMII::U_BitShift; break; 966 case ARM_AM::ib: Binary |= 0x3 << ARMII::U_BitShift; break; 967 } 968 969 return Binary; 970} 971 972template<class CodeEmitter> 973void Emitter<CodeEmitter>::emitLoadStoreMultipleInstruction( 974 const MachineInstr &MI) { 975 // Part of binary is determined by TableGn. 976 unsigned Binary = getBinaryCodeForInstr(MI); 977 978 // Set the conditional execution predicate 979 Binary |= II->getPredicate(&MI) << ARMII::CondShift; 980 981 // Set base address operand 982 Binary |= getMachineOpValue(MI, 0) << ARMII::RegRnShift; 983 984 // Set addressing mode by modifying bits U(23) and P(24) 985 const MachineOperand &MO = MI.getOperand(1); 986 Binary |= getAddrModeUPBits(ARM_AM::getAM4SubMode(MO.getImm())); 987 988 // Set bit W(21) 989 if (ARM_AM::getAM4WBFlag(MO.getImm())) 990 Binary |= 0x1 << ARMII::W_BitShift; 991 992 // Set registers 993 for (unsigned i = 5, e = MI.getNumOperands(); i != e; ++i) { 994 const MachineOperand &MO = MI.getOperand(i); 995 if (!MO.isReg() || MO.isImplicit()) 996 break; 997 unsigned RegNum = ARMRegisterInfo::getRegisterNumbering(MO.getReg()); 998 assert(TargetRegisterInfo::isPhysicalRegister(MO.getReg()) && 999 RegNum < 16); 1000 Binary |= 0x1 << RegNum; 1001 } 1002 1003 emitWordLE(Binary); 1004} 1005 1006template<class CodeEmitter> 1007void Emitter<CodeEmitter>::emitMulFrmInstruction(const MachineInstr &MI) { 1008 const TargetInstrDesc &TID = MI.getDesc(); 1009 1010 // Part of binary is determined by TableGn. 1011 unsigned Binary = getBinaryCodeForInstr(MI); 1012 1013 // Set the conditional execution predicate 1014 Binary |= II->getPredicate(&MI) << ARMII::CondShift; 1015 1016 // Encode S bit if MI modifies CPSR. 1017 Binary |= getAddrModeSBit(MI, TID); 1018 1019 // 32x32->64bit operations have two destination registers. The number 1020 // of register definitions will tell us if that's what we're dealing with. 1021 unsigned OpIdx = 0; 1022 if (TID.getNumDefs() == 2) 1023 Binary |= getMachineOpValue (MI, OpIdx++) << ARMII::RegRdLoShift; 1024 1025 // Encode Rd 1026 Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRdHiShift; 1027 1028 // Encode Rm 1029 Binary |= getMachineOpValue(MI, OpIdx++); 1030 1031 // Encode Rs 1032 Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRsShift; 1033 1034 // Many multiple instructions (e.g. MLA) have three src operands. Encode 1035 // it as Rn (for multiply, that's in the same offset as RdLo. 1036 if (TID.getNumOperands() > OpIdx && 1037 !TID.OpInfo[OpIdx].isPredicate() && 1038 !TID.OpInfo[OpIdx].isOptionalDef()) 1039 Binary |= getMachineOpValue(MI, OpIdx) << ARMII::RegRdLoShift; 1040 1041 emitWordLE(Binary); 1042} 1043 1044template<class CodeEmitter> 1045void Emitter<CodeEmitter>::emitExtendInstruction(const MachineInstr &MI) { 1046 const TargetInstrDesc &TID = MI.getDesc(); 1047 1048 // Part of binary is determined by TableGn. 1049 unsigned Binary = getBinaryCodeForInstr(MI); 1050 1051 // Set the conditional execution predicate 1052 Binary |= II->getPredicate(&MI) << ARMII::CondShift; 1053 1054 unsigned OpIdx = 0; 1055 1056 // Encode Rd 1057 Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRdShift; 1058 1059 const MachineOperand &MO1 = MI.getOperand(OpIdx++); 1060 const MachineOperand &MO2 = MI.getOperand(OpIdx); 1061 if (MO2.isReg()) { 1062 // Two register operand form. 1063 // Encode Rn. 1064 Binary |= getMachineOpValue(MI, MO1) << ARMII::RegRnShift; 1065 1066 // Encode Rm. 1067 Binary |= getMachineOpValue(MI, MO2); 1068 ++OpIdx; 1069 } else { 1070 Binary |= getMachineOpValue(MI, MO1); 1071 } 1072 1073 // Encode rot imm (0, 8, 16, or 24) if it has a rotate immediate operand. 1074 if (MI.getOperand(OpIdx).isImm() && 1075 !TID.OpInfo[OpIdx].isPredicate() && 1076 !TID.OpInfo[OpIdx].isOptionalDef()) 1077 Binary |= (getMachineOpValue(MI, OpIdx) / 8) << ARMII::ExtRotImmShift; 1078 1079 emitWordLE(Binary); 1080} 1081 1082template<class CodeEmitter> 1083void Emitter<CodeEmitter>::emitMiscArithInstruction(const MachineInstr &MI) { 1084 const TargetInstrDesc &TID = MI.getDesc(); 1085 1086 // Part of binary is determined by TableGn. 1087 unsigned Binary = getBinaryCodeForInstr(MI); 1088 1089 // Set the conditional execution predicate 1090 Binary |= II->getPredicate(&MI) << ARMII::CondShift; 1091 1092 unsigned OpIdx = 0; 1093 1094 // Encode Rd 1095 Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRdShift; 1096 1097 const MachineOperand &MO = MI.getOperand(OpIdx++); 1098 if (OpIdx == TID.getNumOperands() || 1099 TID.OpInfo[OpIdx].isPredicate() || 1100 TID.OpInfo[OpIdx].isOptionalDef()) { 1101 // Encode Rm and it's done. 1102 Binary |= getMachineOpValue(MI, MO); 1103 emitWordLE(Binary); 1104 return; 1105 } 1106 1107 // Encode Rn. 1108 Binary |= getMachineOpValue(MI, MO) << ARMII::RegRnShift; 1109 1110 // Encode Rm. 1111 Binary |= getMachineOpValue(MI, OpIdx++); 1112 1113 // Encode shift_imm. 1114 unsigned ShiftAmt = MI.getOperand(OpIdx).getImm(); 1115 assert(ShiftAmt < 32 && "shift_imm range is 0 to 31!"); 1116 Binary |= ShiftAmt << ARMII::ShiftShift; 1117 1118 emitWordLE(Binary); 1119} 1120 1121template<class CodeEmitter> 1122void Emitter<CodeEmitter>::emitBranchInstruction(const MachineInstr &MI) { 1123 const TargetInstrDesc &TID = MI.getDesc(); 1124 1125 if (TID.Opcode == ARM::TPsoft) { 1126 llvm_unreachable("ARM::TPsoft FIXME"); // FIXME 1127 } 1128 1129 // Part of binary is determined by TableGn. 1130 unsigned Binary = getBinaryCodeForInstr(MI); 1131 1132 // Set the conditional execution predicate 1133 Binary |= II->getPredicate(&MI) << ARMII::CondShift; 1134 1135 // Set signed_immed_24 field 1136 Binary |= getMachineOpValue(MI, 0); 1137 1138 emitWordLE(Binary); 1139} 1140 1141template<class CodeEmitter> 1142void Emitter<CodeEmitter>::emitInlineJumpTable(unsigned JTIndex) { 1143 // Remember the base address of the inline jump table. 1144 uintptr_t JTBase = MCE.getCurrentPCValue(); 1145 JTI->addJumpTableBaseAddr(JTIndex, JTBase); 1146 DEBUG(errs() << " ** Jump Table #" << JTIndex << " @ " << (void*)JTBase 1147 << '\n'); 1148 1149 // Now emit the jump table entries. 1150 const std::vector<MachineBasicBlock*> &MBBs = (*MJTEs)[JTIndex].MBBs; 1151 for (unsigned i = 0, e = MBBs.size(); i != e; ++i) { 1152 if (IsPIC) 1153 // DestBB address - JT base. 1154 emitMachineBasicBlock(MBBs[i], ARM::reloc_arm_pic_jt, JTBase); 1155 else 1156 // Absolute DestBB address. 1157 emitMachineBasicBlock(MBBs[i], ARM::reloc_arm_absolute); 1158 emitWordLE(0); 1159 } 1160} 1161 1162template<class CodeEmitter> 1163void Emitter<CodeEmitter>::emitMiscBranchInstruction(const MachineInstr &MI) { 1164 const TargetInstrDesc &TID = MI.getDesc(); 1165 1166 // Handle jump tables. 1167 if (TID.Opcode == ARM::BR_JTr || TID.Opcode == ARM::BR_JTadd) { 1168 // First emit a ldr pc, [] instruction. 1169 emitDataProcessingInstruction(MI, ARM::PC); 1170 1171 // Then emit the inline jump table. 1172 unsigned JTIndex = 1173 (TID.Opcode == ARM::BR_JTr) 1174 ? MI.getOperand(1).getIndex() : MI.getOperand(2).getIndex(); 1175 emitInlineJumpTable(JTIndex); 1176 return; 1177 } else if (TID.Opcode == ARM::BR_JTm) { 1178 // First emit a ldr pc, [] instruction. 1179 emitLoadStoreInstruction(MI, ARM::PC); 1180 1181 // Then emit the inline jump table. 1182 emitInlineJumpTable(MI.getOperand(3).getIndex()); 1183 return; 1184 } 1185 1186 // Part of binary is determined by TableGn. 1187 unsigned Binary = getBinaryCodeForInstr(MI); 1188 1189 // Set the conditional execution predicate 1190 Binary |= II->getPredicate(&MI) << ARMII::CondShift; 1191 1192 if (TID.Opcode == ARM::BX_RET) 1193 // The return register is LR. 1194 Binary |= ARMRegisterInfo::getRegisterNumbering(ARM::LR); 1195 else 1196 // otherwise, set the return register 1197 Binary |= getMachineOpValue(MI, 0); 1198 1199 emitWordLE(Binary); 1200} 1201 1202static unsigned encodeVFPRd(const MachineInstr &MI, unsigned OpIdx) { 1203 unsigned RegD = MI.getOperand(OpIdx).getReg(); 1204 unsigned Binary = 0; 1205 bool isSPVFP = false; 1206 RegD = ARMRegisterInfo::getRegisterNumbering(RegD, &isSPVFP); 1207 if (!isSPVFP) 1208 Binary |= RegD << ARMII::RegRdShift; 1209 else { 1210 Binary |= ((RegD & 0x1E) >> 1) << ARMII::RegRdShift; 1211 Binary |= (RegD & 0x01) << ARMII::D_BitShift; 1212 } 1213 return Binary; 1214} 1215 1216static unsigned encodeVFPRn(const MachineInstr &MI, unsigned OpIdx) { 1217 unsigned RegN = MI.getOperand(OpIdx).getReg(); 1218 unsigned Binary = 0; 1219 bool isSPVFP = false; 1220 RegN = ARMRegisterInfo::getRegisterNumbering(RegN, &isSPVFP); 1221 if (!isSPVFP) 1222 Binary |= RegN << ARMII::RegRnShift; 1223 else { 1224 Binary |= ((RegN & 0x1E) >> 1) << ARMII::RegRnShift; 1225 Binary |= (RegN & 0x01) << ARMII::N_BitShift; 1226 } 1227 return Binary; 1228} 1229 1230static unsigned encodeVFPRm(const MachineInstr &MI, unsigned OpIdx) { 1231 unsigned RegM = MI.getOperand(OpIdx).getReg(); 1232 unsigned Binary = 0; 1233 bool isSPVFP = false; 1234 RegM = ARMRegisterInfo::getRegisterNumbering(RegM, &isSPVFP); 1235 if (!isSPVFP) 1236 Binary |= RegM; 1237 else { 1238 Binary |= ((RegM & 0x1E) >> 1); 1239 Binary |= (RegM & 0x01) << ARMII::M_BitShift; 1240 } 1241 return Binary; 1242} 1243 1244template<class CodeEmitter> 1245void Emitter<CodeEmitter>::emitVFPArithInstruction(const MachineInstr &MI) { 1246 const TargetInstrDesc &TID = MI.getDesc(); 1247 1248 // Part of binary is determined by TableGn. 1249 unsigned Binary = getBinaryCodeForInstr(MI); 1250 1251 // Set the conditional execution predicate 1252 Binary |= II->getPredicate(&MI) << ARMII::CondShift; 1253 1254 unsigned OpIdx = 0; 1255 assert((Binary & ARMII::D_BitShift) == 0 && 1256 (Binary & ARMII::N_BitShift) == 0 && 1257 (Binary & ARMII::M_BitShift) == 0 && "VFP encoding bug!"); 1258 1259 // Encode Dd / Sd. 1260 Binary |= encodeVFPRd(MI, OpIdx++); 1261 1262 // If this is a two-address operand, skip it, e.g. FMACD. 1263 if (TID.getOperandConstraint(OpIdx, TOI::TIED_TO) != -1) 1264 ++OpIdx; 1265 1266 // Encode Dn / Sn. 1267 if ((TID.TSFlags & ARMII::FormMask) == ARMII::VFPBinaryFrm) 1268 Binary |= encodeVFPRn(MI, OpIdx++); 1269 1270 if (OpIdx == TID.getNumOperands() || 1271 TID.OpInfo[OpIdx].isPredicate() || 1272 TID.OpInfo[OpIdx].isOptionalDef()) { 1273 // FCMPEZD etc. has only one operand. 1274 emitWordLE(Binary); 1275 return; 1276 } 1277 1278 // Encode Dm / Sm. 1279 Binary |= encodeVFPRm(MI, OpIdx); 1280 1281 emitWordLE(Binary); 1282} 1283 1284template<class CodeEmitter> 1285void Emitter<CodeEmitter>::emitVFPConversionInstruction( 1286 const MachineInstr &MI) { 1287 const TargetInstrDesc &TID = MI.getDesc(); 1288 unsigned Form = TID.TSFlags & ARMII::FormMask; 1289 1290 // Part of binary is determined by TableGn. 1291 unsigned Binary = getBinaryCodeForInstr(MI); 1292 1293 // Set the conditional execution predicate 1294 Binary |= II->getPredicate(&MI) << ARMII::CondShift; 1295 1296 switch (Form) { 1297 default: break; 1298 case ARMII::VFPConv1Frm: 1299 case ARMII::VFPConv2Frm: 1300 case ARMII::VFPConv3Frm: 1301 // Encode Dd / Sd. 1302 Binary |= encodeVFPRd(MI, 0); 1303 break; 1304 case ARMII::VFPConv4Frm: 1305 // Encode Dn / Sn. 1306 Binary |= encodeVFPRn(MI, 0); 1307 break; 1308 case ARMII::VFPConv5Frm: 1309 // Encode Dm / Sm. 1310 Binary |= encodeVFPRm(MI, 0); 1311 break; 1312 } 1313 1314 switch (Form) { 1315 default: break; 1316 case ARMII::VFPConv1Frm: 1317 // Encode Dm / Sm. 1318 Binary |= encodeVFPRm(MI, 1); 1319 break; 1320 case ARMII::VFPConv2Frm: 1321 case ARMII::VFPConv3Frm: 1322 // Encode Dn / Sn. 1323 Binary |= encodeVFPRn(MI, 1); 1324 break; 1325 case ARMII::VFPConv4Frm: 1326 case ARMII::VFPConv5Frm: 1327 // Encode Dd / Sd. 1328 Binary |= encodeVFPRd(MI, 1); 1329 break; 1330 } 1331 1332 if (Form == ARMII::VFPConv5Frm) 1333 // Encode Dn / Sn. 1334 Binary |= encodeVFPRn(MI, 2); 1335 else if (Form == ARMII::VFPConv3Frm) 1336 // Encode Dm / Sm. 1337 Binary |= encodeVFPRm(MI, 2); 1338 1339 emitWordLE(Binary); 1340} 1341 1342template<class CodeEmitter> 1343void Emitter<CodeEmitter>::emitVFPLoadStoreInstruction(const MachineInstr &MI) { 1344 // Part of binary is determined by TableGn. 1345 unsigned Binary = getBinaryCodeForInstr(MI); 1346 1347 // Set the conditional execution predicate 1348 Binary |= II->getPredicate(&MI) << ARMII::CondShift; 1349 1350 unsigned OpIdx = 0; 1351 1352 // Encode Dd / Sd. 1353 Binary |= encodeVFPRd(MI, OpIdx++); 1354 1355 // Encode address base. 1356 const MachineOperand &Base = MI.getOperand(OpIdx++); 1357 Binary |= getMachineOpValue(MI, Base) << ARMII::RegRnShift; 1358 1359 // If there is a non-zero immediate offset, encode it. 1360 if (Base.isReg()) { 1361 const MachineOperand &Offset = MI.getOperand(OpIdx); 1362 if (unsigned ImmOffs = ARM_AM::getAM5Offset(Offset.getImm())) { 1363 if (ARM_AM::getAM5Op(Offset.getImm()) == ARM_AM::add) 1364 Binary |= 1 << ARMII::U_BitShift; 1365 Binary |= ImmOffs; 1366 emitWordLE(Binary); 1367 return; 1368 } 1369 } 1370 1371 // If immediate offset is omitted, default to +0. 1372 Binary |= 1 << ARMII::U_BitShift; 1373 1374 emitWordLE(Binary); 1375} 1376 1377template<class CodeEmitter> 1378void Emitter<CodeEmitter>::emitVFPLoadStoreMultipleInstruction( 1379 const MachineInstr &MI) { 1380 // Part of binary is determined by TableGn. 1381 unsigned Binary = getBinaryCodeForInstr(MI); 1382 1383 // Set the conditional execution predicate 1384 Binary |= II->getPredicate(&MI) << ARMII::CondShift; 1385 1386 // Set base address operand 1387 Binary |= getMachineOpValue(MI, 0) << ARMII::RegRnShift; 1388 1389 // Set addressing mode by modifying bits U(23) and P(24) 1390 const MachineOperand &MO = MI.getOperand(1); 1391 Binary |= getAddrModeUPBits(ARM_AM::getAM5SubMode(MO.getImm())); 1392 1393 // Set bit W(21) 1394 if (ARM_AM::getAM5WBFlag(MO.getImm())) 1395 Binary |= 0x1 << ARMII::W_BitShift; 1396 1397 // First register is encoded in Dd. 1398 Binary |= encodeVFPRd(MI, 5); 1399 1400 // Number of registers are encoded in offset field. 1401 unsigned NumRegs = 1; 1402 for (unsigned i = 6, e = MI.getNumOperands(); i != e; ++i) { 1403 const MachineOperand &MO = MI.getOperand(i); 1404 if (!MO.isReg() || MO.isImplicit()) 1405 break; 1406 ++NumRegs; 1407 } 1408 Binary |= NumRegs * 2; 1409 1410 emitWordLE(Binary); 1411} 1412 1413template<class CodeEmitter> 1414void Emitter<CodeEmitter>::emitMiscInstruction(const MachineInstr &MI) { 1415 // Part of binary is determined by TableGn. 1416 unsigned Binary = getBinaryCodeForInstr(MI); 1417 1418 // Set the conditional execution predicate 1419 Binary |= II->getPredicate(&MI) << ARMII::CondShift; 1420 1421 emitWordLE(Binary); 1422} 1423 1424#include "ARMGenCodeEmitter.inc" 1425