ARMCodeEmitter.cpp revision aabb9a5359cbb0bf9d25bfb917ecb09c086d034b 
1//===-- ARM/ARMCodeEmitter.cpp - Convert ARM code to machine code ---------===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file contains the pass that transforms the ARM machine instructions into
11// relocatable machine code.
12//
13//===----------------------------------------------------------------------===//
14
15#define DEBUG_TYPE "jit"
16#include "ARM.h"
17#include "ARMAddressingModes.h"
18#include "ARMConstantPoolValue.h"
19#include "ARMInstrInfo.h"
20#include "ARMRelocations.h"
21#include "ARMSubtarget.h"
22#include "ARMTargetMachine.h"
23#include "llvm/Constants.h"
24#include "llvm/DerivedTypes.h"
25#include "llvm/Function.h"
26#include "llvm/PassManager.h"
27#include "llvm/CodeGen/MachineCodeEmitter.h"
28#include "llvm/CodeGen/JITCodeEmitter.h"
29#include "llvm/CodeGen/ObjectCodeEmitter.h"
30#include "llvm/CodeGen/MachineConstantPool.h"
31#include "llvm/CodeGen/MachineFunctionPass.h"
32#include "llvm/CodeGen/MachineInstr.h"
33#include "llvm/CodeGen/MachineJumpTableInfo.h"
34#include "llvm/CodeGen/Passes.h"
35#include "llvm/ADT/Statistic.h"
36#include "llvm/Support/Compiler.h"
37#include "llvm/Support/Debug.h"
38#ifndef NDEBUG
39#include <iomanip>
40#endif
41using namespace llvm;
42
43STATISTIC(NumEmitted, "Number of machine instructions emitted");
44
45namespace {
46
47  class ARMCodeEmitter {
48  public:
49    /// getBinaryCodeForInstr - This function, generated by the
50    /// CodeEmitterGenerator using TableGen, produces the binary encoding for
51    /// machine instructions.
52    unsigned getBinaryCodeForInstr(const MachineInstr &MI);
53  };
54
55  template<class CodeEmitter>
56  class VISIBILITY_HIDDEN Emitter : public MachineFunctionPass,
57                                    public ARMCodeEmitter {
58    ARMJITInfo                *JTI;
59    const ARMInstrInfo        *II;
60    const TargetData          *TD;
61    TargetMachine             &TM;
62    CodeEmitter               &MCE;
63    const std::vector<MachineConstantPoolEntry> *MCPEs;
64    const std::vector<MachineJumpTableEntry> *MJTEs;
65    bool IsPIC;
66
67  public:
68    static char ID;
69    explicit Emitter(TargetMachine &tm, CodeEmitter &mce)
70      : MachineFunctionPass(&ID), JTI(0), II(0), TD(0), TM(tm),
71      MCE(mce), MCPEs(0), MJTEs(0),
72      IsPIC(TM.getRelocationModel() == Reloc::PIC_) {}
73    Emitter(TargetMachine &tm, CodeEmitter &mce,
74            const ARMInstrInfo &ii, const TargetData &td)
75      : MachineFunctionPass(&ID), JTI(0), II(&ii), TD(&td), TM(tm),
76      MCE(mce), MCPEs(0), MJTEs(0),
77      IsPIC(TM.getRelocationModel() == Reloc::PIC_) {}
78
79    bool runOnMachineFunction(MachineFunction &MF);
80
81    virtual const char *getPassName() const {
82      return "ARM Machine Code Emitter";
83    }
84
85    void emitInstruction(const MachineInstr &MI);
86
87  private:
88
89    void emitWordLE(unsigned Binary);
90
91    void emitDWordLE(uint64_t Binary);
92
93    void emitConstPoolInstruction(const MachineInstr &MI);
94
95    void emitMOVi2piecesInstruction(const MachineInstr &MI);
96
97    void emitLEApcrelJTInstruction(const MachineInstr &MI);
98
99    void emitPseudoMoveInstruction(const MachineInstr &MI);
100
101    void addPCLabel(unsigned LabelID);
102
103    void emitPseudoInstruction(const MachineInstr &MI);
104
105    unsigned getMachineSoRegOpValue(const MachineInstr &MI,
106                                    const TargetInstrDesc &TID,
107                                    const MachineOperand &MO,
108                                    unsigned OpIdx);
109
110    unsigned getMachineSoImmOpValue(unsigned SoImm);
111
112    unsigned getAddrModeSBit(const MachineInstr &MI,
113                             const TargetInstrDesc &TID) const;
114
115    void emitDataProcessingInstruction(const MachineInstr &MI,
116                                       unsigned ImplicitRd = 0,
117                                       unsigned ImplicitRn = 0);
118
119    void emitLoadStoreInstruction(const MachineInstr &MI,
120                                  unsigned ImplicitRd = 0,
121                                  unsigned ImplicitRn = 0);
122
123    void emitMiscLoadStoreInstruction(const MachineInstr &MI,
124                                      unsigned ImplicitRn = 0);
125
126    void emitLoadStoreMultipleInstruction(const MachineInstr &MI);
127
128    void emitMulFrmInstruction(const MachineInstr &MI);
129
130    void emitExtendInstruction(const MachineInstr &MI);
131
132    void emitMiscArithInstruction(const MachineInstr &MI);
133
134    void emitBranchInstruction(const MachineInstr &MI);
135
136    void emitInlineJumpTable(unsigned JTIndex);
137
138    void emitMiscBranchInstruction(const MachineInstr &MI);
139
140    void emitVFPArithInstruction(const MachineInstr &MI);
141
142    void emitVFPConversionInstruction(const MachineInstr &MI);
143
144    void emitVFPLoadStoreInstruction(const MachineInstr &MI);
145
146    void emitVFPLoadStoreMultipleInstruction(const MachineInstr &MI);
147
148    void emitMiscInstruction(const MachineInstr &MI);
149
150    /// getMachineOpValue - Return binary encoding of operand. If the machine
151    /// operand requires relocation, record the relocation and return zero.
152    unsigned getMachineOpValue(const MachineInstr &MI,const MachineOperand &MO);
153    unsigned getMachineOpValue(const MachineInstr &MI, unsigned OpIdx) {
154      return getMachineOpValue(MI, MI.getOperand(OpIdx));
155    }
156
157    /// getShiftOp - Return the shift opcode (bit[6:5]) of the immediate value.
158    ///
159    unsigned getShiftOp(unsigned Imm) const ;
160
161    /// Routines that handle operands which add machine relocations which are
162    /// fixed up by the relocation stage.
163    void emitGlobalAddress(GlobalValue *GV, unsigned Reloc,
164                           bool NeedStub, intptr_t ACPV = 0);
165    void emitExternalSymbolAddress(const char *ES, unsigned Reloc);
166    void emitConstPoolAddress(unsigned CPI, unsigned Reloc);
167    void emitJumpTableAddress(unsigned JTIndex, unsigned Reloc);
168    void emitMachineBasicBlock(MachineBasicBlock *BB, unsigned Reloc,
169                               intptr_t JTBase = 0);
170  };
171  template <class CodeEmitter>
172  char Emitter<CodeEmitter>::ID = 0;
173}
174
175/// createARMCodeEmitterPass - Return a pass that emits the collected ARM code
176/// to the specified MCE object.
177
178FunctionPass *llvm::createARMCodeEmitterPass(ARMBaseTargetMachine &TM,
179                                             MachineCodeEmitter &MCE) {
180  return new Emitter<MachineCodeEmitter>(TM, MCE);
181}
182FunctionPass *llvm::createARMJITCodeEmitterPass(ARMBaseTargetMachine &TM,
183                                                JITCodeEmitter &JCE) {
184  return new Emitter<JITCodeEmitter>(TM, JCE);
185}
186FunctionPass *llvm::createARMObjectCodeEmitterPass(ARMBaseTargetMachine &TM,
187                                                   ObjectCodeEmitter &OCE) {
188  return new Emitter<ObjectCodeEmitter>(TM, OCE);
189}
190
191template<class CodeEmitter>
192bool Emitter<CodeEmitter>::runOnMachineFunction(MachineFunction &MF) {
193  assert((MF.getTarget().getRelocationModel() != Reloc::Default ||
194          MF.getTarget().getRelocationModel() != Reloc::Static) &&
195         "JIT relocation model must be set to static or default!");
196  II = ((ARMTargetMachine&)MF.getTarget()).getInstrInfo();
197  TD = ((ARMTargetMachine&)MF.getTarget()).getTargetData();
198  JTI = ((ARMTargetMachine&)MF.getTarget()).getJITInfo();
199  MCPEs = &MF.getConstantPool()->getConstants();
200  MJTEs = &MF.getJumpTableInfo()->getJumpTables();
201  IsPIC = TM.getRelocationModel() == Reloc::PIC_;
202  JTI->Initialize(MF, IsPIC);
203
204  do {
205    DOUT << "JITTing function '" << MF.getFunction()->getName() << "'\n";
206    MCE.startFunction(MF);
207    for (MachineFunction::iterator MBB = MF.begin(), E = MF.end();
208         MBB != E; ++MBB) {
209      MCE.StartMachineBasicBlock(MBB);
210      for (MachineBasicBlock::const_iterator I = MBB->begin(), E = MBB->end();
211           I != E; ++I)
212        emitInstruction(*I);
213    }
214  } while (MCE.finishFunction(MF));
215
216  return false;
217}
218
219/// getShiftOp - Return the shift opcode (bit[6:5]) of the immediate value.
220///
221template<class CodeEmitter>
222unsigned Emitter<CodeEmitter>::getShiftOp(unsigned Imm) const {
223  switch (ARM_AM::getAM2ShiftOpc(Imm)) {
224  default: assert(0 && "Unknown shift opc!");
225  case ARM_AM::asr: return 2;
226  case ARM_AM::lsl: return 0;
227  case ARM_AM::lsr: return 1;
228  case ARM_AM::ror:
229  case ARM_AM::rrx: return 3;
230  }
231  return 0;
232}
233
234/// getMachineOpValue - Return binary encoding of operand. If the machine
235/// operand requires relocation, record the relocation and return zero.
236template<class CodeEmitter>
237unsigned Emitter<CodeEmitter>::getMachineOpValue(const MachineInstr &MI,
238                                                 const MachineOperand &MO) {
239  if (MO.isReg())
240    return ARMRegisterInfo::getRegisterNumbering(MO.getReg());
241  else if (MO.isImm())
242    return static_cast<unsigned>(MO.getImm());
243  else if (MO.isGlobal())
244    emitGlobalAddress(MO.getGlobal(), ARM::reloc_arm_branch, true);
245  else if (MO.isSymbol())
246    emitExternalSymbolAddress(MO.getSymbolName(), ARM::reloc_arm_branch);
247  else if (MO.isCPI()) {
248    const TargetInstrDesc &TID = MI.getDesc();
249    // For VFP load, the immediate offset is multiplied by 4.
250    unsigned Reloc =  ((TID.TSFlags & ARMII::FormMask) == ARMII::VFPLdStFrm)
251      ? ARM::reloc_arm_vfp_cp_entry : ARM::reloc_arm_cp_entry;
252    emitConstPoolAddress(MO.getIndex(), Reloc);
253  } else if (MO.isJTI())
254    emitJumpTableAddress(MO.getIndex(), ARM::reloc_arm_relative);
255  else if (MO.isMBB())
256    emitMachineBasicBlock(MO.getMBB(), ARM::reloc_arm_branch);
257  else {
258    cerr << "ERROR: Unknown type of MachineOperand: " << MO << "\n";
259    abort();
260  }
261  return 0;
262}
263
264/// emitGlobalAddress - Emit the specified address to the code stream.
265///
266template<class CodeEmitter>
267void Emitter<CodeEmitter>::emitGlobalAddress(GlobalValue *GV, unsigned Reloc,
268                                             bool NeedStub, intptr_t ACPV) {
269  MCE.addRelocation(MachineRelocation::getGV(MCE.getCurrentPCOffset(), Reloc,
270                                             GV, ACPV, NeedStub));
271}
272
273/// emitExternalSymbolAddress - Arrange for the address of an external symbol to
274/// be emitted to the current location in the function, and allow it to be PC
275/// relative.
276template<class CodeEmitter>
277void Emitter<CodeEmitter>::emitExternalSymbolAddress(const char *ES,
278                                                     unsigned Reloc) {
279  MCE.addRelocation(MachineRelocation::getExtSym(MCE.getCurrentPCOffset(),
280                                                 Reloc, ES));
281}
282
283/// emitConstPoolAddress - Arrange for the address of an constant pool
284/// to be emitted to the current location in the function, and allow it to be PC
285/// relative.
286template<class CodeEmitter>
287void Emitter<CodeEmitter>::emitConstPoolAddress(unsigned CPI,
288                                                unsigned Reloc) {
289  // Tell JIT emitter we'll resolve the address.
290  MCE.addRelocation(MachineRelocation::getConstPool(MCE.getCurrentPCOffset(),
291                                                    Reloc, CPI, 0, true));
292}
293
294/// emitJumpTableAddress - Arrange for the address of a jump table to
295/// be emitted to the current location in the function, and allow it to be PC
296/// relative.
297template<class CodeEmitter>
298void Emitter<CodeEmitter>::emitJumpTableAddress(unsigned JTIndex,
299                                                unsigned Reloc) {
300  MCE.addRelocation(MachineRelocation::getJumpTable(MCE.getCurrentPCOffset(),
301                                                    Reloc, JTIndex, 0, true));
302}
303
304/// emitMachineBasicBlock - Emit the specified address basic block.
305template<class CodeEmitter>
306void Emitter<CodeEmitter>::emitMachineBasicBlock(MachineBasicBlock *BB,
307                                              unsigned Reloc, intptr_t JTBase) {
308  MCE.addRelocation(MachineRelocation::getBB(MCE.getCurrentPCOffset(),
309                                             Reloc, BB, JTBase));
310}
311
312template<class CodeEmitter>
313void Emitter<CodeEmitter>::emitWordLE(unsigned Binary) {
314#ifndef NDEBUG
315  DOUT << "  0x" << std::hex << std::setw(8) << std::setfill('0')
316       << Binary << std::dec << "\n";
317#endif
318  MCE.emitWordLE(Binary);
319}
320
321template<class CodeEmitter>
322void Emitter<CodeEmitter>::emitDWordLE(uint64_t Binary) {
323#ifndef NDEBUG
324  DOUT << "  0x" << std::hex << std::setw(8) << std::setfill('0')
325       << (unsigned)Binary << std::dec << "\n";
326  DOUT << "  0x" << std::hex << std::setw(8) << std::setfill('0')
327       << (unsigned)(Binary >> 32) << std::dec << "\n";
328#endif
329  MCE.emitDWordLE(Binary);
330}
331
332template<class CodeEmitter>
333void Emitter<CodeEmitter>::emitInstruction(const MachineInstr &MI) {
334  DOUT << "JIT: " << (void*)MCE.getCurrentPCValue() << ":\t" << MI;
335
336  NumEmitted++;  // Keep track of the # of mi's emitted
337  switch (MI.getDesc().TSFlags & ARMII::FormMask) {
338  default: {
339    assert(0 && "Unhandled instruction encoding format!");
340    break;
341  }
342  case ARMII::Pseudo:
343    emitPseudoInstruction(MI);
344    break;
345  case ARMII::DPFrm:
346  case ARMII::DPSoRegFrm:
347    emitDataProcessingInstruction(MI);
348    break;
349  case ARMII::LdFrm:
350  case ARMII::StFrm:
351    emitLoadStoreInstruction(MI);
352    break;
353  case ARMII::LdMiscFrm:
354  case ARMII::StMiscFrm:
355    emitMiscLoadStoreInstruction(MI);
356    break;
357  case ARMII::LdStMulFrm:
358    emitLoadStoreMultipleInstruction(MI);
359    break;
360  case ARMII::MulFrm:
361    emitMulFrmInstruction(MI);
362    break;
363  case ARMII::ExtFrm:
364    emitExtendInstruction(MI);
365    break;
366  case ARMII::ArithMiscFrm:
367    emitMiscArithInstruction(MI);
368    break;
369  case ARMII::BrFrm:
370    emitBranchInstruction(MI);
371    break;
372  case ARMII::BrMiscFrm:
373    emitMiscBranchInstruction(MI);
374    break;
375  // VFP instructions.
376  case ARMII::VFPUnaryFrm:
377  case ARMII::VFPBinaryFrm:
378    emitVFPArithInstruction(MI);
379    break;
380  case ARMII::VFPConv1Frm:
381  case ARMII::VFPConv2Frm:
382  case ARMII::VFPConv3Frm:
383  case ARMII::VFPConv4Frm:
384  case ARMII::VFPConv5Frm:
385    emitVFPConversionInstruction(MI);
386    break;
387  case ARMII::VFPLdStFrm:
388    emitVFPLoadStoreInstruction(MI);
389    break;
390  case ARMII::VFPLdStMulFrm:
391    emitVFPLoadStoreMultipleInstruction(MI);
392    break;
393  case ARMII::VFPMiscFrm:
394    emitMiscInstruction(MI);
395    break;
396  }
397}
398
399template<class CodeEmitter>
400void Emitter<CodeEmitter>::emitConstPoolInstruction(const MachineInstr &MI) {
401  unsigned CPI = MI.getOperand(0).getImm();       // CP instruction index.
402  unsigned CPIndex = MI.getOperand(1).getIndex(); // Actual cp entry index.
403  const MachineConstantPoolEntry &MCPE = (*MCPEs)[CPIndex];
404
405  // Remember the CONSTPOOL_ENTRY address for later relocation.
406  JTI->addConstantPoolEntryAddr(CPI, MCE.getCurrentPCValue());
407
408  // Emit constpool island entry. In most cases, the actual values will be
409  // resolved and relocated after code emission.
410  if (MCPE.isMachineConstantPoolEntry()) {
411    ARMConstantPoolValue *ACPV =
412      static_cast<ARMConstantPoolValue*>(MCPE.Val.MachineCPVal);
413
414    DOUT << "  ** ARM constant pool #" << CPI << " @ "
415         << (void*)MCE.getCurrentPCValue() << " " << *ACPV << '\n';
416
417    GlobalValue *GV = ACPV->getGV();
418    if (GV) {
419      assert(!ACPV->isStub() && "Don't know how to deal this yet!");
420      if (ACPV->isNonLazyPointer())
421        MCE.addRelocation(MachineRelocation::getIndirectSymbol(
422                  MCE.getCurrentPCOffset(), ARM::reloc_arm_machine_cp_entry, GV,
423                  (intptr_t)ACPV, false));
424      else
425        emitGlobalAddress(GV, ARM::reloc_arm_machine_cp_entry,
426                          ACPV->isStub() || isa<Function>(GV), (intptr_t)ACPV);
427     } else  {
428      assert(!ACPV->isNonLazyPointer() && "Don't know how to deal this yet!");
429      emitExternalSymbolAddress(ACPV->getSymbol(), ARM::reloc_arm_absolute);
430    }
431    emitWordLE(0);
432  } else {
433    Constant *CV = MCPE.Val.ConstVal;
434
435#ifndef NDEBUG
436    DOUT << "  ** Constant pool #" << CPI << " @ "
437         << (void*)MCE.getCurrentPCValue() << " ";
438    if (const Function *F = dyn_cast<Function>(CV))
439      DOUT << F->getName();
440    else
441      DOUT << *CV;
442    DOUT << '\n';
443#endif
444
445    if (GlobalValue *GV = dyn_cast<GlobalValue>(CV)) {
446      emitGlobalAddress(GV, ARM::reloc_arm_absolute, isa<Function>(GV));
447      emitWordLE(0);
448    } else if (const ConstantInt *CI = dyn_cast<ConstantInt>(CV)) {
449      uint32_t Val = *(uint32_t*)CI->getValue().getRawData();
450      emitWordLE(Val);
451    } else if (const ConstantFP *CFP = dyn_cast<ConstantFP>(CV)) {
452      if (CFP->getType() == Type::FloatTy)
453        emitWordLE(CFP->getValueAPF().bitcastToAPInt().getZExtValue());
454      else if (CFP->getType() == Type::DoubleTy)
455        emitDWordLE(CFP->getValueAPF().bitcastToAPInt().getZExtValue());
456      else {
457        assert(0 && "Unable to handle this constantpool entry!");
458        abort();
459      }
460    } else {
461      assert(0 && "Unable to handle this constantpool entry!");
462      abort();
463    }
464  }
465}
466
467template<class CodeEmitter>
468void Emitter<CodeEmitter>::emitMOVi2piecesInstruction(const MachineInstr &MI) {
469  const MachineOperand &MO0 = MI.getOperand(0);
470  const MachineOperand &MO1 = MI.getOperand(1);
471  assert(MO1.isImm() && "Not a valid so_imm value!");
472  unsigned V1 = ARM_AM::getSOImmTwoPartFirst(MO1.getImm());
473  unsigned V2 = ARM_AM::getSOImmTwoPartSecond(MO1.getImm());
474
475  // Emit the 'mov' instruction.
476  unsigned Binary = 0xd << 21;  // mov: Insts{24-21} = 0b1101
477
478  // Set the conditional execution predicate.
479  Binary |= II->getPredicate(&MI) << ARMII::CondShift;
480
481  // Encode Rd.
482  Binary |= getMachineOpValue(MI, MO0) << ARMII::RegRdShift;
483
484  // Encode so_imm.
485  // Set bit I(25) to identify this is the immediate form of <shifter_op>
486  Binary |= 1 << ARMII::I_BitShift;
487  Binary |= getMachineSoImmOpValue(ARM_AM::getSOImmVal(V1));
488  emitWordLE(Binary);
489
490  // Now the 'orr' instruction.
491  Binary = 0xc << 21;  // orr: Insts{24-21} = 0b1100
492
493  // Set the conditional execution predicate.
494  Binary |= II->getPredicate(&MI) << ARMII::CondShift;
495
496  // Encode Rd.
497  Binary |= getMachineOpValue(MI, MO0) << ARMII::RegRdShift;
498
499  // Encode Rn.
500  Binary |= getMachineOpValue(MI, MO0) << ARMII::RegRnShift;
501
502  // Encode so_imm.
503  // Set bit I(25) to identify this is the immediate form of <shifter_op>
504  Binary |= 1 << ARMII::I_BitShift;
505  Binary |= getMachineSoImmOpValue(ARM_AM::getSOImmVal(V2));
506  emitWordLE(Binary);
507}
508
509template<class CodeEmitter>
510void Emitter<CodeEmitter>::emitLEApcrelJTInstruction(const MachineInstr &MI) {
511  // It's basically add r, pc, (LJTI - $+8)
512
513  const TargetInstrDesc &TID = MI.getDesc();
514
515  // Emit the 'add' instruction.
516  unsigned Binary = 0x4 << 21;  // add: Insts{24-31} = 0b0100
517
518  // Set the conditional execution predicate
519  Binary |= II->getPredicate(&MI) << ARMII::CondShift;
520
521  // Encode S bit if MI modifies CPSR.
522  Binary |= getAddrModeSBit(MI, TID);
523
524  // Encode Rd.
525  Binary |= getMachineOpValue(MI, 0) << ARMII::RegRdShift;
526
527  // Encode Rn which is PC.
528  Binary |= ARMRegisterInfo::getRegisterNumbering(ARM::PC) << ARMII::RegRnShift;
529
530  // Encode the displacement.
531  // Set bit I(25) to identify this is the immediate form of <shifter_op>.
532  Binary |= 1 << ARMII::I_BitShift;
533  emitJumpTableAddress(MI.getOperand(1).getIndex(), ARM::reloc_arm_jt_base);
534
535  emitWordLE(Binary);
536}
537
538template<class CodeEmitter>
539void Emitter<CodeEmitter>::emitPseudoMoveInstruction(const MachineInstr &MI) {
540  unsigned Opcode = MI.getDesc().Opcode;
541
542  // Part of binary is determined by TableGn.
543  unsigned Binary = getBinaryCodeForInstr(MI);
544
545  // Set the conditional execution predicate
546  Binary |= II->getPredicate(&MI) << ARMII::CondShift;
547
548  // Encode S bit if MI modifies CPSR.
549  if (Opcode == ARM::MOVsrl_flag || Opcode == ARM::MOVsra_flag)
550    Binary |= 1 << ARMII::S_BitShift;
551
552  // Encode register def if there is one.
553  Binary |= getMachineOpValue(MI, 0) << ARMII::RegRdShift;
554
555  // Encode the shift operation.
556  switch (Opcode) {
557  default: break;
558  case ARM::MOVrx:
559    // rrx
560    Binary |= 0x6 << 4;
561    break;
562  case ARM::MOVsrl_flag:
563    // lsr #1
564    Binary |= (0x2 << 4) | (1 << 7);
565    break;
566  case ARM::MOVsra_flag:
567    // asr #1
568    Binary |= (0x4 << 4) | (1 << 7);
569    break;
570  }
571
572  // Encode register Rm.
573  Binary |= getMachineOpValue(MI, 1);
574
575  emitWordLE(Binary);
576}
577
578template<class CodeEmitter>
579void Emitter<CodeEmitter>::addPCLabel(unsigned LabelID) {
580  DOUT << "  ** LPC" << LabelID << " @ "
581       << (void*)MCE.getCurrentPCValue() << '\n';
582  JTI->addPCLabelAddr(LabelID, MCE.getCurrentPCValue());
583}
584
585template<class CodeEmitter>
586void Emitter<CodeEmitter>::emitPseudoInstruction(const MachineInstr &MI) {
587  unsigned Opcode = MI.getDesc().Opcode;
588  switch (Opcode) {
589  default:
590    abort(); // FIXME:
591  case TargetInstrInfo::INLINEASM: {
592    // We allow inline assembler nodes with empty bodies - they can
593    // implicitly define registers, which is ok for JIT.
594    if (MI.getOperand(0).getSymbolName()[0]) {
595      assert(0 && "JIT does not support inline asm!\n");
596      abort();
597    }
598    break;
599  }
600  case TargetInstrInfo::DBG_LABEL:
601  case TargetInstrInfo::EH_LABEL:
602    MCE.emitLabel(MI.getOperand(0).getImm());
603    break;
604  case TargetInstrInfo::IMPLICIT_DEF:
605  case TargetInstrInfo::DECLARE:
606  case ARM::DWARF_LOC:
607    // Do nothing.
608    break;
609  case ARM::CONSTPOOL_ENTRY:
610    emitConstPoolInstruction(MI);
611    break;
612  case ARM::PICADD: {
613    // Remember of the address of the PC label for relocation later.
614    addPCLabel(MI.getOperand(2).getImm());
615    // PICADD is just an add instruction that implicitly read pc.
616    emitDataProcessingInstruction(MI, 0, ARM::PC);
617    break;
618  }
619  case ARM::PICLDR:
620  case ARM::PICLDRB:
621  case ARM::PICSTR:
622  case ARM::PICSTRB: {
623    // Remember of the address of the PC label for relocation later.
624    addPCLabel(MI.getOperand(2).getImm());
625    // These are just load / store instructions that implicitly read pc.
626    emitLoadStoreInstruction(MI, 0, ARM::PC);
627    break;
628  }
629  case ARM::PICLDRH:
630  case ARM::PICLDRSH:
631  case ARM::PICLDRSB:
632  case ARM::PICSTRH: {
633    // Remember of the address of the PC label for relocation later.
634    addPCLabel(MI.getOperand(2).getImm());
635    // These are just load / store instructions that implicitly read pc.
636    emitMiscLoadStoreInstruction(MI, ARM::PC);
637    break;
638  }
639  case ARM::MOVi2pieces:
640    // Two instructions to materialize a constant.
641    emitMOVi2piecesInstruction(MI);
642    break;
643  case ARM::LEApcrelJT:
644    // Materialize jumptable address.
645    emitLEApcrelJTInstruction(MI);
646    break;
647  case ARM::MOVrx:
648  case ARM::MOVsrl_flag:
649  case ARM::MOVsra_flag:
650    emitPseudoMoveInstruction(MI);
651    break;
652  }
653}
654
655template<class CodeEmitter>
656unsigned Emitter<CodeEmitter>::getMachineSoRegOpValue(
657                                                const MachineInstr &MI,
658                                                const TargetInstrDesc &TID,
659                                                const MachineOperand &MO,
660                                                unsigned OpIdx) {
661  unsigned Binary = getMachineOpValue(MI, MO);
662
663  const MachineOperand &MO1 = MI.getOperand(OpIdx + 1);
664  const MachineOperand &MO2 = MI.getOperand(OpIdx + 2);
665  ARM_AM::ShiftOpc SOpc = ARM_AM::getSORegShOp(MO2.getImm());
666
667  // Encode the shift opcode.
668  unsigned SBits = 0;
669  unsigned Rs = MO1.getReg();
670  if (Rs) {
671    // Set shift operand (bit[7:4]).
672    // LSL - 0001
673    // LSR - 0011
674    // ASR - 0101
675    // ROR - 0111
676    // RRX - 0110 and bit[11:8] clear.
677    switch (SOpc) {
678    default: assert(0 && "Unknown shift opc!");
679    case ARM_AM::lsl: SBits = 0x1; break;
680    case ARM_AM::lsr: SBits = 0x3; break;
681    case ARM_AM::asr: SBits = 0x5; break;
682    case ARM_AM::ror: SBits = 0x7; break;
683    case ARM_AM::rrx: SBits = 0x6; break;
684    }
685  } else {
686    // Set shift operand (bit[6:4]).
687    // LSL - 000
688    // LSR - 010
689    // ASR - 100
690    // ROR - 110
691    switch (SOpc) {
692    default: assert(0 && "Unknown shift opc!");
693    case ARM_AM::lsl: SBits = 0x0; break;
694    case ARM_AM::lsr: SBits = 0x2; break;
695    case ARM_AM::asr: SBits = 0x4; break;
696    case ARM_AM::ror: SBits = 0x6; break;
697    }
698  }
699  Binary |= SBits << 4;
700  if (SOpc == ARM_AM::rrx)
701    return Binary;
702
703  // Encode the shift operation Rs or shift_imm (except rrx).
704  if (Rs) {
705    // Encode Rs bit[11:8].
706    assert(ARM_AM::getSORegOffset(MO2.getImm()) == 0);
707    return Binary |
708      (ARMRegisterInfo::getRegisterNumbering(Rs) << ARMII::RegRsShift);
709  }
710
711  // Encode shift_imm bit[11:7].
712  return Binary | ARM_AM::getSORegOffset(MO2.getImm()) << 7;
713}
714
715template<class CodeEmitter>
716unsigned Emitter<CodeEmitter>::getMachineSoImmOpValue(unsigned SoImm) {
717  // Encode rotate_imm.
718  unsigned Binary = (ARM_AM::getSOImmValRot(SoImm) >> 1)
719    << ARMII::SoRotImmShift;
720
721  // Encode immed_8.
722  Binary |= ARM_AM::getSOImmValImm(SoImm);
723  return Binary;
724}
725
726template<class CodeEmitter>
727unsigned Emitter<CodeEmitter>::getAddrModeSBit(const MachineInstr &MI,
728                                             const TargetInstrDesc &TID) const {
729  for (unsigned i = MI.getNumOperands(), e = TID.getNumOperands(); i != e; --i){
730    const MachineOperand &MO = MI.getOperand(i-1);
731    if (MO.isReg() && MO.isDef() && MO.getReg() == ARM::CPSR)
732      return 1 << ARMII::S_BitShift;
733  }
734  return 0;
735}
736
737template<class CodeEmitter>
738void Emitter<CodeEmitter>::emitDataProcessingInstruction(
739                                                   const MachineInstr &MI,
740                                                   unsigned ImplicitRd,
741                                                   unsigned ImplicitRn) {
742  const TargetInstrDesc &TID = MI.getDesc();
743
744  // Part of binary is determined by TableGn.
745  unsigned Binary = getBinaryCodeForInstr(MI);
746
747  // Set the conditional execution predicate
748  Binary |= II->getPredicate(&MI) << ARMII::CondShift;
749
750  // Encode S bit if MI modifies CPSR.
751  Binary |= getAddrModeSBit(MI, TID);
752
753  // Encode register def if there is one.
754  unsigned NumDefs = TID.getNumDefs();
755  unsigned OpIdx = 0;
756  if (NumDefs)
757    Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRdShift;
758  else if (ImplicitRd)
759    // Special handling for implicit use (e.g. PC).
760    Binary |= (ARMRegisterInfo::getRegisterNumbering(ImplicitRd)
761               << ARMII::RegRdShift);
762
763  // If this is a two-address operand, skip it. e.g. MOVCCr operand 1.
764  if (TID.getOperandConstraint(OpIdx, TOI::TIED_TO) != -1)
765    ++OpIdx;
766
767  // Encode first non-shifter register operand if there is one.
768  bool isUnary = TID.TSFlags & ARMII::UnaryDP;
769  if (!isUnary) {
770    if (ImplicitRn)
771      // Special handling for implicit use (e.g. PC).
772      Binary |= (ARMRegisterInfo::getRegisterNumbering(ImplicitRn)
773                 << ARMII::RegRnShift);
774    else {
775      Binary |= getMachineOpValue(MI, OpIdx) << ARMII::RegRnShift;
776      ++OpIdx;
777    }
778  }
779
780  // Encode shifter operand.
781  const MachineOperand &MO = MI.getOperand(OpIdx);
782  if ((TID.TSFlags & ARMII::FormMask) == ARMII::DPSoRegFrm) {
783    // Encode SoReg.
784    emitWordLE(Binary | getMachineSoRegOpValue(MI, TID, MO, OpIdx));
785    return;
786  }
787
788  if (MO.isReg()) {
789    // Encode register Rm.
790    emitWordLE(Binary | ARMRegisterInfo::getRegisterNumbering(MO.getReg()));
791    return;
792  }
793
794  // Encode so_imm.
795  // Set bit I(25) to identify this is the immediate form of <shifter_op>.
796  Binary |= 1 << ARMII::I_BitShift;
797  Binary |= getMachineSoImmOpValue(MO.getImm());
798
799  emitWordLE(Binary);
800}
801
802template<class CodeEmitter>
803void Emitter<CodeEmitter>::emitLoadStoreInstruction(
804                                              const MachineInstr &MI,
805                                              unsigned ImplicitRd,
806                                              unsigned ImplicitRn) {
807  const TargetInstrDesc &TID = MI.getDesc();
808  unsigned Form = TID.TSFlags & ARMII::FormMask;
809  bool IsPrePost = (TID.TSFlags & ARMII::IndexModeMask) != 0;
810
811  // Part of binary is determined by TableGn.
812  unsigned Binary = getBinaryCodeForInstr(MI);
813
814  // Set the conditional execution predicate
815  Binary |= II->getPredicate(&MI) << ARMII::CondShift;
816
817  unsigned OpIdx = 0;
818
819  // Operand 0 of a pre- and post-indexed store is the address base
820  // writeback. Skip it.
821  bool Skipped = false;
822  if (IsPrePost && Form == ARMII::StFrm) {
823    ++OpIdx;
824    Skipped = true;
825  }
826
827  // Set first operand
828  if (ImplicitRd)
829    // Special handling for implicit use (e.g. PC).
830    Binary |= (ARMRegisterInfo::getRegisterNumbering(ImplicitRd)
831               << ARMII::RegRdShift);
832  else
833    Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRdShift;
834
835  // Set second operand
836  if (ImplicitRn)
837    // Special handling for implicit use (e.g. PC).
838    Binary |= (ARMRegisterInfo::getRegisterNumbering(ImplicitRn)
839               << ARMII::RegRnShift);
840  else
841    Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRnShift;
842
843  // If this is a two-address operand, skip it. e.g. LDR_PRE.
844  if (!Skipped && TID.getOperandConstraint(OpIdx, TOI::TIED_TO) != -1)
845    ++OpIdx;
846
847  const MachineOperand &MO2 = MI.getOperand(OpIdx);
848  unsigned AM2Opc = (ImplicitRn == ARM::PC)
849    ? 0 : MI.getOperand(OpIdx+1).getImm();
850
851  // Set bit U(23) according to sign of immed value (positive or negative).
852  Binary |= ((ARM_AM::getAM2Op(AM2Opc) == ARM_AM::add ? 1 : 0) <<
853             ARMII::U_BitShift);
854  if (!MO2.getReg()) { // is immediate
855    if (ARM_AM::getAM2Offset(AM2Opc))
856      // Set the value of offset_12 field
857      Binary |= ARM_AM::getAM2Offset(AM2Opc);
858    emitWordLE(Binary);
859    return;
860  }
861
862  // Set bit I(25), because this is not in immediate enconding.
863  Binary |= 1 << ARMII::I_BitShift;
864  assert(TargetRegisterInfo::isPhysicalRegister(MO2.getReg()));
865  // Set bit[3:0] to the corresponding Rm register
866  Binary |= ARMRegisterInfo::getRegisterNumbering(MO2.getReg());
867
868  // If this instr is in scaled register offset/index instruction, set
869  // shift_immed(bit[11:7]) and shift(bit[6:5]) fields.
870  if (unsigned ShImm = ARM_AM::getAM2Offset(AM2Opc)) {
871    Binary |= getShiftOp(AM2Opc) << ARMII::ShiftImmShift;  // shift
872    Binary |= ShImm              << ARMII::ShiftShift;     // shift_immed
873  }
874
875  emitWordLE(Binary);
876}
877
878template<class CodeEmitter>
879void Emitter<CodeEmitter>::emitMiscLoadStoreInstruction(const MachineInstr &MI,
880                                                        unsigned ImplicitRn) {
881  const TargetInstrDesc &TID = MI.getDesc();
882  unsigned Form = TID.TSFlags & ARMII::FormMask;
883  bool IsPrePost = (TID.TSFlags & ARMII::IndexModeMask) != 0;
884
885  // Part of binary is determined by TableGn.
886  unsigned Binary = getBinaryCodeForInstr(MI);
887
888  // Set the conditional execution predicate
889  Binary |= II->getPredicate(&MI) << ARMII::CondShift;
890
891  unsigned OpIdx = 0;
892
893  // Operand 0 of a pre- and post-indexed store is the address base
894  // writeback. Skip it.
895  bool Skipped = false;
896  if (IsPrePost && Form == ARMII::StMiscFrm) {
897    ++OpIdx;
898    Skipped = true;
899  }
900
901  // Set first operand
902  Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRdShift;
903
904  // Skip LDRD and STRD's second operand.
905  if (TID.Opcode == ARM::LDRD || TID.Opcode == ARM::STRD)
906    ++OpIdx;
907
908  // Set second operand
909  if (ImplicitRn)
910    // Special handling for implicit use (e.g. PC).
911    Binary |= (ARMRegisterInfo::getRegisterNumbering(ImplicitRn)
912               << ARMII::RegRnShift);
913  else
914    Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRnShift;
915
916  // If this is a two-address operand, skip it. e.g. LDRH_POST.
917  if (!Skipped && TID.getOperandConstraint(OpIdx, TOI::TIED_TO) != -1)
918    ++OpIdx;
919
920  const MachineOperand &MO2 = MI.getOperand(OpIdx);
921  unsigned AM3Opc = (ImplicitRn == ARM::PC)
922    ? 0 : MI.getOperand(OpIdx+1).getImm();
923
924  // Set bit U(23) according to sign of immed value (positive or negative)
925  Binary |= ((ARM_AM::getAM3Op(AM3Opc) == ARM_AM::add ? 1 : 0) <<
926             ARMII::U_BitShift);
927
928  // If this instr is in register offset/index encoding, set bit[3:0]
929  // to the corresponding Rm register.
930  if (MO2.getReg()) {
931    Binary |= ARMRegisterInfo::getRegisterNumbering(MO2.getReg());
932    emitWordLE(Binary);
933    return;
934  }
935
936  // This instr is in immediate offset/index encoding, set bit 22 to 1.
937  Binary |= 1 << ARMII::AM3_I_BitShift;
938  if (unsigned ImmOffs = ARM_AM::getAM3Offset(AM3Opc)) {
939    // Set operands
940    Binary |= (ImmOffs >> 4) << ARMII::ImmHiShift;  // immedH
941    Binary |= (ImmOffs & 0xF);                      // immedL
942  }
943
944  emitWordLE(Binary);
945}
946
947static unsigned getAddrModeUPBits(unsigned Mode) {
948  unsigned Binary = 0;
949
950  // Set addressing mode by modifying bits U(23) and P(24)
951  // IA - Increment after  - bit U = 1 and bit P = 0
952  // IB - Increment before - bit U = 1 and bit P = 1
953  // DA - Decrement after  - bit U = 0 and bit P = 0
954  // DB - Decrement before - bit U = 0 and bit P = 1
955  switch (Mode) {
956  default: assert(0 && "Unknown addressing sub-mode!");
957  case ARM_AM::da:                      break;
958  case ARM_AM::db: Binary |= 0x1 << ARMII::P_BitShift; break;
959  case ARM_AM::ia: Binary |= 0x1 << ARMII::U_BitShift; break;
960  case ARM_AM::ib: Binary |= 0x3 << ARMII::U_BitShift; break;
961  }
962
963  return Binary;
964}
965
966template<class CodeEmitter>
967void Emitter<CodeEmitter>::emitLoadStoreMultipleInstruction(
968                                                       const MachineInstr &MI) {
969  // Part of binary is determined by TableGn.
970  unsigned Binary = getBinaryCodeForInstr(MI);
971
972  // Set the conditional execution predicate
973  Binary |= II->getPredicate(&MI) << ARMII::CondShift;
974
975  // Set base address operand
976  Binary |= getMachineOpValue(MI, 0) << ARMII::RegRnShift;
977
978  // Set addressing mode by modifying bits U(23) and P(24)
979  const MachineOperand &MO = MI.getOperand(1);
980  Binary |= getAddrModeUPBits(ARM_AM::getAM4SubMode(MO.getImm()));
981
982  // Set bit W(21)
983  if (ARM_AM::getAM4WBFlag(MO.getImm()))
984    Binary |= 0x1 << ARMII::W_BitShift;
985
986  // Set registers
987  for (unsigned i = 4, e = MI.getNumOperands(); i != e; ++i) {
988    const MachineOperand &MO = MI.getOperand(i);
989    if (!MO.isReg() || MO.isImplicit())
990      break;
991    unsigned RegNum = ARMRegisterInfo::getRegisterNumbering(MO.getReg());
992    assert(TargetRegisterInfo::isPhysicalRegister(MO.getReg()) &&
993           RegNum < 16);
994    Binary |= 0x1 << RegNum;
995  }
996
997  emitWordLE(Binary);
998}
999
1000template<class CodeEmitter>
1001void Emitter<CodeEmitter>::emitMulFrmInstruction(const MachineInstr &MI) {
1002  const TargetInstrDesc &TID = MI.getDesc();
1003
1004  // Part of binary is determined by TableGn.
1005  unsigned Binary = getBinaryCodeForInstr(MI);
1006
1007  // Set the conditional execution predicate
1008  Binary |= II->getPredicate(&MI) << ARMII::CondShift;
1009
1010  // Encode S bit if MI modifies CPSR.
1011  Binary |= getAddrModeSBit(MI, TID);
1012
1013  // 32x32->64bit operations have two destination registers. The number
1014  // of register definitions will tell us if that's what we're dealing with.
1015  unsigned OpIdx = 0;
1016  if (TID.getNumDefs() == 2)
1017    Binary |= getMachineOpValue (MI, OpIdx++) << ARMII::RegRdLoShift;
1018
1019  // Encode Rd
1020  Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRdHiShift;
1021
1022  // Encode Rm
1023  Binary |= getMachineOpValue(MI, OpIdx++);
1024
1025  // Encode Rs
1026  Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRsShift;
1027
1028  // Many multiple instructions (e.g. MLA) have three src operands. Encode
1029  // it as Rn (for multiply, that's in the same offset as RdLo.
1030  if (TID.getNumOperands() > OpIdx &&
1031      !TID.OpInfo[OpIdx].isPredicate() &&
1032      !TID.OpInfo[OpIdx].isOptionalDef())
1033    Binary |= getMachineOpValue(MI, OpIdx) << ARMII::RegRdLoShift;
1034
1035  emitWordLE(Binary);
1036}
1037
1038template<class CodeEmitter>
1039void Emitter<CodeEmitter>::emitExtendInstruction(const MachineInstr &MI) {
1040  const TargetInstrDesc &TID = MI.getDesc();
1041
1042  // Part of binary is determined by TableGn.
1043  unsigned Binary = getBinaryCodeForInstr(MI);
1044
1045  // Set the conditional execution predicate
1046  Binary |= II->getPredicate(&MI) << ARMII::CondShift;
1047
1048  unsigned OpIdx = 0;
1049
1050  // Encode Rd
1051  Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRdShift;
1052
1053  const MachineOperand &MO1 = MI.getOperand(OpIdx++);
1054  const MachineOperand &MO2 = MI.getOperand(OpIdx);
1055  if (MO2.isReg()) {
1056    // Two register operand form.
1057    // Encode Rn.
1058    Binary |= getMachineOpValue(MI, MO1) << ARMII::RegRnShift;
1059
1060    // Encode Rm.
1061    Binary |= getMachineOpValue(MI, MO2);
1062    ++OpIdx;
1063  } else {
1064    Binary |= getMachineOpValue(MI, MO1);
1065  }
1066
1067  // Encode rot imm (0, 8, 16, or 24) if it has a rotate immediate operand.
1068  if (MI.getOperand(OpIdx).isImm() &&
1069      !TID.OpInfo[OpIdx].isPredicate() &&
1070      !TID.OpInfo[OpIdx].isOptionalDef())
1071    Binary |= (getMachineOpValue(MI, OpIdx) / 8) << ARMII::ExtRotImmShift;
1072
1073  emitWordLE(Binary);
1074}
1075
1076template<class CodeEmitter>
1077void Emitter<CodeEmitter>::emitMiscArithInstruction(const MachineInstr &MI) {
1078  const TargetInstrDesc &TID = MI.getDesc();
1079
1080  // Part of binary is determined by TableGn.
1081  unsigned Binary = getBinaryCodeForInstr(MI);
1082
1083  // Set the conditional execution predicate
1084  Binary |= II->getPredicate(&MI) << ARMII::CondShift;
1085
1086  unsigned OpIdx = 0;
1087
1088  // Encode Rd
1089  Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRdShift;
1090
1091  const MachineOperand &MO = MI.getOperand(OpIdx++);
1092  if (OpIdx == TID.getNumOperands() ||
1093      TID.OpInfo[OpIdx].isPredicate() ||
1094      TID.OpInfo[OpIdx].isOptionalDef()) {
1095    // Encode Rm and it's done.
1096    Binary |= getMachineOpValue(MI, MO);
1097    emitWordLE(Binary);
1098    return;
1099  }
1100
1101  // Encode Rn.
1102  Binary |= getMachineOpValue(MI, MO) << ARMII::RegRnShift;
1103
1104  // Encode Rm.
1105  Binary |= getMachineOpValue(MI, OpIdx++);
1106
1107  // Encode shift_imm.
1108  unsigned ShiftAmt = MI.getOperand(OpIdx).getImm();
1109  assert(ShiftAmt < 32 && "shift_imm range is 0 to 31!");
1110  Binary |= ShiftAmt << ARMII::ShiftShift;
1111
1112  emitWordLE(Binary);
1113}
1114
1115template<class CodeEmitter>
1116void Emitter<CodeEmitter>::emitBranchInstruction(const MachineInstr &MI) {
1117  const TargetInstrDesc &TID = MI.getDesc();
1118
1119  if (TID.Opcode == ARM::TPsoft)
1120    abort(); // FIXME
1121
1122  // Part of binary is determined by TableGn.
1123  unsigned Binary = getBinaryCodeForInstr(MI);
1124
1125  // Set the conditional execution predicate
1126  Binary |= II->getPredicate(&MI) << ARMII::CondShift;
1127
1128  // Set signed_immed_24 field
1129  Binary |= getMachineOpValue(MI, 0);
1130
1131  emitWordLE(Binary);
1132}
1133
1134template<class CodeEmitter>
1135void Emitter<CodeEmitter>::emitInlineJumpTable(unsigned JTIndex) {
1136  // Remember the base address of the inline jump table.
1137  uintptr_t JTBase = MCE.getCurrentPCValue();
1138  JTI->addJumpTableBaseAddr(JTIndex, JTBase);
1139  DOUT << "  ** Jump Table #" << JTIndex << " @ " << (void*)JTBase << '\n';
1140
1141  // Now emit the jump table entries.
1142  const std::vector<MachineBasicBlock*> &MBBs = (*MJTEs)[JTIndex].MBBs;
1143  for (unsigned i = 0, e = MBBs.size(); i != e; ++i) {
1144    if (IsPIC)
1145      // DestBB address - JT base.
1146      emitMachineBasicBlock(MBBs[i], ARM::reloc_arm_pic_jt, JTBase);
1147    else
1148      // Absolute DestBB address.
1149      emitMachineBasicBlock(MBBs[i], ARM::reloc_arm_absolute);
1150    emitWordLE(0);
1151  }
1152}
1153
1154template<class CodeEmitter>
1155void Emitter<CodeEmitter>::emitMiscBranchInstruction(const MachineInstr &MI) {
1156  const TargetInstrDesc &TID = MI.getDesc();
1157
1158  // Handle jump tables.
1159  if (TID.Opcode == ARM::BR_JTr || TID.Opcode == ARM::BR_JTadd ||
1160      TID.Opcode == ARM::t2BR_JTr || TID.Opcode == ARM::t2BR_JTadd) {
1161    // First emit a ldr pc, [] instruction.
1162    emitDataProcessingInstruction(MI, ARM::PC);
1163
1164    // Then emit the inline jump table.
1165    unsigned JTIndex = (TID.Opcode == ARM::BR_JTr || TID.Opcode == ARM::t2BR_JTr)
1166      ? MI.getOperand(1).getIndex() : MI.getOperand(2).getIndex();
1167    emitInlineJumpTable(JTIndex);
1168    return;
1169  } else if (TID.Opcode == ARM::BR_JTm || TID.Opcode == ARM::t2BR_JTm) {
1170    // First emit a ldr pc, [] instruction.
1171    emitLoadStoreInstruction(MI, ARM::PC);
1172
1173    // Then emit the inline jump table.
1174    emitInlineJumpTable(MI.getOperand(3).getIndex());
1175    return;
1176  }
1177
1178  // Part of binary is determined by TableGn.
1179  unsigned Binary = getBinaryCodeForInstr(MI);
1180
1181  // Set the conditional execution predicate
1182  Binary |= II->getPredicate(&MI) << ARMII::CondShift;
1183
1184  if (TID.Opcode == ARM::BX_RET)
1185    // The return register is LR.
1186    Binary |= ARMRegisterInfo::getRegisterNumbering(ARM::LR);
1187  else
1188    // otherwise, set the return register
1189    Binary |= getMachineOpValue(MI, 0);
1190
1191  emitWordLE(Binary);
1192}
1193
1194static unsigned encodeVFPRd(const MachineInstr &MI, unsigned OpIdx) {
1195  unsigned RegD = MI.getOperand(OpIdx).getReg();
1196  unsigned Binary = 0;
1197  bool isSPVFP = false;
1198  RegD = ARMRegisterInfo::getRegisterNumbering(RegD, isSPVFP);
1199  if (!isSPVFP)
1200    Binary |=   RegD               << ARMII::RegRdShift;
1201  else {
1202    Binary |= ((RegD & 0x1E) >> 1) << ARMII::RegRdShift;
1203    Binary |=  (RegD & 0x01)       << ARMII::D_BitShift;
1204  }
1205  return Binary;
1206}
1207
1208static unsigned encodeVFPRn(const MachineInstr &MI, unsigned OpIdx) {
1209  unsigned RegN = MI.getOperand(OpIdx).getReg();
1210  unsigned Binary = 0;
1211  bool isSPVFP = false;
1212  RegN = ARMRegisterInfo::getRegisterNumbering(RegN, isSPVFP);
1213  if (!isSPVFP)
1214    Binary |=   RegN               << ARMII::RegRnShift;
1215  else {
1216    Binary |= ((RegN & 0x1E) >> 1) << ARMII::RegRnShift;
1217    Binary |=  (RegN & 0x01)       << ARMII::N_BitShift;
1218  }
1219  return Binary;
1220}
1221
1222static unsigned encodeVFPRm(const MachineInstr &MI, unsigned OpIdx) {
1223  unsigned RegM = MI.getOperand(OpIdx).getReg();
1224  unsigned Binary = 0;
1225  bool isSPVFP = false;
1226  RegM = ARMRegisterInfo::getRegisterNumbering(RegM, isSPVFP);
1227  if (!isSPVFP)
1228    Binary |=   RegM;
1229  else {
1230    Binary |= ((RegM & 0x1E) >> 1);
1231    Binary |=  (RegM & 0x01)       << ARMII::M_BitShift;
1232  }
1233  return Binary;
1234}
1235
1236template<class CodeEmitter>
1237void Emitter<CodeEmitter>::emitVFPArithInstruction(const MachineInstr &MI) {
1238  const TargetInstrDesc &TID = MI.getDesc();
1239
1240  // Part of binary is determined by TableGn.
1241  unsigned Binary = getBinaryCodeForInstr(MI);
1242
1243  // Set the conditional execution predicate
1244  Binary |= II->getPredicate(&MI) << ARMII::CondShift;
1245
1246  unsigned OpIdx = 0;
1247  assert((Binary & ARMII::D_BitShift) == 0 &&
1248         (Binary & ARMII::N_BitShift) == 0 &&
1249         (Binary & ARMII::M_BitShift) == 0 && "VFP encoding bug!");
1250
1251  // Encode Dd / Sd.
1252  Binary |= encodeVFPRd(MI, OpIdx++);
1253
1254  // If this is a two-address operand, skip it, e.g. FMACD.
1255  if (TID.getOperandConstraint(OpIdx, TOI::TIED_TO) != -1)
1256    ++OpIdx;
1257
1258  // Encode Dn / Sn.
1259  if ((TID.TSFlags & ARMII::FormMask) == ARMII::VFPBinaryFrm)
1260    Binary |= encodeVFPRn(MI, OpIdx++);
1261
1262  if (OpIdx == TID.getNumOperands() ||
1263      TID.OpInfo[OpIdx].isPredicate() ||
1264      TID.OpInfo[OpIdx].isOptionalDef()) {
1265    // FCMPEZD etc. has only one operand.
1266    emitWordLE(Binary);
1267    return;
1268  }
1269
1270  // Encode Dm / Sm.
1271  Binary |= encodeVFPRm(MI, OpIdx);
1272
1273  emitWordLE(Binary);
1274}
1275
1276template<class CodeEmitter>
1277void Emitter<CodeEmitter>::emitVFPConversionInstruction(
1278      const MachineInstr &MI) {
1279  const TargetInstrDesc &TID = MI.getDesc();
1280  unsigned Form = TID.TSFlags & ARMII::FormMask;
1281
1282  // Part of binary is determined by TableGn.
1283  unsigned Binary = getBinaryCodeForInstr(MI);
1284
1285  // Set the conditional execution predicate
1286  Binary |= II->getPredicate(&MI) << ARMII::CondShift;
1287
1288  switch (Form) {
1289  default: break;
1290  case ARMII::VFPConv1Frm:
1291  case ARMII::VFPConv2Frm:
1292  case ARMII::VFPConv3Frm:
1293    // Encode Dd / Sd.
1294    Binary |= encodeVFPRd(MI, 0);
1295    break;
1296  case ARMII::VFPConv4Frm:
1297    // Encode Dn / Sn.
1298    Binary |= encodeVFPRn(MI, 0);
1299    break;
1300  case ARMII::VFPConv5Frm:
1301    // Encode Dm / Sm.
1302    Binary |= encodeVFPRm(MI, 0);
1303    break;
1304  }
1305
1306  switch (Form) {
1307  default: break;
1308  case ARMII::VFPConv1Frm:
1309    // Encode Dm / Sm.
1310    Binary |= encodeVFPRm(MI, 1);
1311    break;
1312  case ARMII::VFPConv2Frm:
1313  case ARMII::VFPConv3Frm:
1314    // Encode Dn / Sn.
1315    Binary |= encodeVFPRn(MI, 1);
1316    break;
1317  case ARMII::VFPConv4Frm:
1318  case ARMII::VFPConv5Frm:
1319    // Encode Dd / Sd.
1320    Binary |= encodeVFPRd(MI, 1);
1321    break;
1322  }
1323
1324  if (Form == ARMII::VFPConv5Frm)
1325    // Encode Dn / Sn.
1326    Binary |= encodeVFPRn(MI, 2);
1327  else if (Form == ARMII::VFPConv3Frm)
1328    // Encode Dm / Sm.
1329    Binary |= encodeVFPRm(MI, 2);
1330
1331  emitWordLE(Binary);
1332}
1333
1334template<class CodeEmitter>
1335void Emitter<CodeEmitter>::emitVFPLoadStoreInstruction(const MachineInstr &MI) {
1336  // Part of binary is determined by TableGn.
1337  unsigned Binary = getBinaryCodeForInstr(MI);
1338
1339  // Set the conditional execution predicate
1340  Binary |= II->getPredicate(&MI) << ARMII::CondShift;
1341
1342  unsigned OpIdx = 0;
1343
1344  // Encode Dd / Sd.
1345  Binary |= encodeVFPRd(MI, OpIdx++);
1346
1347  // Encode address base.
1348  const MachineOperand &Base = MI.getOperand(OpIdx++);
1349  Binary |= getMachineOpValue(MI, Base) << ARMII::RegRnShift;
1350
1351  // If there is a non-zero immediate offset, encode it.
1352  if (Base.isReg()) {
1353    const MachineOperand &Offset = MI.getOperand(OpIdx);
1354    if (unsigned ImmOffs = ARM_AM::getAM5Offset(Offset.getImm())) {
1355      if (ARM_AM::getAM5Op(Offset.getImm()) == ARM_AM::add)
1356        Binary |= 1 << ARMII::U_BitShift;
1357      Binary |= ImmOffs;
1358      emitWordLE(Binary);
1359      return;
1360    }
1361  }
1362
1363  // If immediate offset is omitted, default to +0.
1364  Binary |= 1 << ARMII::U_BitShift;
1365
1366  emitWordLE(Binary);
1367}
1368
1369template<class CodeEmitter>
1370void Emitter<CodeEmitter>::emitVFPLoadStoreMultipleInstruction(
1371                                                       const MachineInstr &MI) {
1372  // Part of binary is determined by TableGn.
1373  unsigned Binary = getBinaryCodeForInstr(MI);
1374
1375  // Set the conditional execution predicate
1376  Binary |= II->getPredicate(&MI) << ARMII::CondShift;
1377
1378  // Set base address operand
1379  Binary |= getMachineOpValue(MI, 0) << ARMII::RegRnShift;
1380
1381  // Set addressing mode by modifying bits U(23) and P(24)
1382  const MachineOperand &MO = MI.getOperand(1);
1383  Binary |= getAddrModeUPBits(ARM_AM::getAM5SubMode(MO.getImm()));
1384
1385  // Set bit W(21)
1386  if (ARM_AM::getAM5WBFlag(MO.getImm()))
1387    Binary |= 0x1 << ARMII::W_BitShift;
1388
1389  // First register is encoded in Dd.
1390  Binary |= encodeVFPRd(MI, 4);
1391
1392  // Number of registers are encoded in offset field.
1393  unsigned NumRegs = 1;
1394  for (unsigned i = 5, e = MI.getNumOperands(); i != e; ++i) {
1395    const MachineOperand &MO = MI.getOperand(i);
1396    if (!MO.isReg() || MO.isImplicit())
1397      break;
1398    ++NumRegs;
1399  }
1400  Binary |= NumRegs * 2;
1401
1402  emitWordLE(Binary);
1403}
1404
1405template<class CodeEmitter>
1406void Emitter<CodeEmitter>::emitMiscInstruction(const MachineInstr &MI) {
1407  // Part of binary is determined by TableGn.
1408  unsigned Binary = getBinaryCodeForInstr(MI);
1409
1410  // Set the conditional execution predicate
1411  Binary |= II->getPredicate(&MI) << ARMII::CondShift;
1412
1413  emitWordLE(Binary);
1414}
1415
1416#include "ARMGenCodeEmitter.inc"
1417
1418