ARMCodeEmitter.cpp revision b9ee99d999a51b1d9869853cba4b69e0b5b95e54 
1//===-- ARM/ARMCodeEmitter.cpp - Convert ARM code to machine code ---------===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file contains the pass that transforms the ARM machine instructions into
11// relocatable machine code.
12//
13//===----------------------------------------------------------------------===//
14
15#define DEBUG_TYPE "jit"
16#include "ARM.h"
17#include "ARMAddressingModes.h"
18#include "ARMConstantPoolValue.h"
19#include "ARMInstrInfo.h"
20#include "ARMRelocations.h"
21#include "ARMSubtarget.h"
22#include "ARMTargetMachine.h"
23#include "llvm/Constants.h"
24#include "llvm/DerivedTypes.h"
25#include "llvm/Function.h"
26#include "llvm/PassManager.h"
27#include "llvm/CodeGen/JITCodeEmitter.h"
28#include "llvm/CodeGen/MachineConstantPool.h"
29#include "llvm/CodeGen/MachineFunctionPass.h"
30#include "llvm/CodeGen/MachineInstr.h"
31#include "llvm/CodeGen/MachineJumpTableInfo.h"
32#include "llvm/CodeGen/MachineModuleInfo.h"
33#include "llvm/CodeGen/Passes.h"
34#include "llvm/ADT/Statistic.h"
35#include "llvm/Support/Debug.h"
36#include "llvm/Support/ErrorHandling.h"
37#include "llvm/Support/raw_ostream.h"
38#ifndef NDEBUG
39#include <iomanip>
40#endif
41using namespace llvm;
42
43STATISTIC(NumEmitted, "Number of machine instructions emitted");
44
45namespace {
46
47  class ARMCodeEmitter : public MachineFunctionPass {
48    ARMJITInfo                *JTI;
49    const ARMInstrInfo        *II;
50    const TargetData          *TD;
51    const ARMSubtarget        *Subtarget;
52    TargetMachine             &TM;
53    JITCodeEmitter            &MCE;
54    const std::vector<MachineConstantPoolEntry> *MCPEs;
55    const std::vector<MachineJumpTableEntry> *MJTEs;
56    bool IsPIC;
57
58    void getAnalysisUsage(AnalysisUsage &AU) const {
59      AU.addRequired<MachineModuleInfo>();
60      MachineFunctionPass::getAnalysisUsage(AU);
61    }
62
63    static char ID;
64  public:
65    ARMCodeEmitter(TargetMachine &tm, JITCodeEmitter &mce)
66      : MachineFunctionPass(&ID), JTI(0), II((ARMInstrInfo*)tm.getInstrInfo()),
67        TD(tm.getTargetData()), TM(tm),
68    MCE(mce), MCPEs(0), MJTEs(0),
69    IsPIC(TM.getRelocationModel() == Reloc::PIC_) {}
70
71    /// getBinaryCodeForInstr - This function, generated by the
72    /// CodeEmitterGenerator using TableGen, produces the binary encoding for
73    /// machine instructions.
74    unsigned getBinaryCodeForInstr(const MachineInstr &MI);
75
76    bool runOnMachineFunction(MachineFunction &MF);
77
78    virtual const char *getPassName() const {
79      return "ARM Machine Code Emitter";
80    }
81
82    void emitInstruction(const MachineInstr &MI);
83
84  private:
85
86    void emitWordLE(unsigned Binary);
87    void emitDWordLE(uint64_t Binary);
88    void emitConstPoolInstruction(const MachineInstr &MI);
89    void emitMOVi2piecesInstruction(const MachineInstr &MI);
90    void emitLEApcrelJTInstruction(const MachineInstr &MI);
91    void emitPseudoMoveInstruction(const MachineInstr &MI);
92    void addPCLabel(unsigned LabelID);
93    void emitPseudoInstruction(const MachineInstr &MI);
94    unsigned getMachineSoRegOpValue(const MachineInstr &MI,
95                                    const TargetInstrDesc &TID,
96                                    const MachineOperand &MO,
97                                    unsigned OpIdx);
98
99    unsigned getMachineSoImmOpValue(unsigned SoImm);
100
101    unsigned getAddrModeSBit(const MachineInstr &MI,
102                             const TargetInstrDesc &TID) const;
103
104    void emitDataProcessingInstruction(const MachineInstr &MI,
105                                       unsigned ImplicitRd = 0,
106                                       unsigned ImplicitRn = 0);
107
108    void emitLoadStoreInstruction(const MachineInstr &MI,
109                                  unsigned ImplicitRd = 0,
110                                  unsigned ImplicitRn = 0);
111
112    void emitMiscLoadStoreInstruction(const MachineInstr &MI,
113                                      unsigned ImplicitRn = 0);
114
115    void emitLoadStoreMultipleInstruction(const MachineInstr &MI);
116
117    void emitMulFrmInstruction(const MachineInstr &MI);
118
119    void emitExtendInstruction(const MachineInstr &MI);
120
121    void emitMiscArithInstruction(const MachineInstr &MI);
122
123    void emitBranchInstruction(const MachineInstr &MI);
124
125    void emitInlineJumpTable(unsigned JTIndex);
126
127    void emitMiscBranchInstruction(const MachineInstr &MI);
128
129    void emitVFPArithInstruction(const MachineInstr &MI);
130
131    void emitVFPConversionInstruction(const MachineInstr &MI);
132
133    void emitVFPLoadStoreInstruction(const MachineInstr &MI);
134
135    void emitVFPLoadStoreMultipleInstruction(const MachineInstr &MI);
136
137    void emitMiscInstruction(const MachineInstr &MI);
138
139    /// getMachineOpValue - Return binary encoding of operand. If the machine
140    /// operand requires relocation, record the relocation and return zero.
141    unsigned getMachineOpValue(const MachineInstr &MI,const MachineOperand &MO);
142    unsigned getMachineOpValue(const MachineInstr &MI, unsigned OpIdx) {
143      return getMachineOpValue(MI, MI.getOperand(OpIdx));
144    }
145
146    /// getShiftOp - Return the shift opcode (bit[6:5]) of the immediate value.
147    ///
148    unsigned getShiftOp(unsigned Imm) const ;
149
150    /// Routines that handle operands which add machine relocations which are
151    /// fixed up by the relocation stage.
152    void emitGlobalAddress(GlobalValue *GV, unsigned Reloc,
153                           bool MayNeedFarStub,  bool Indirect,
154                           intptr_t ACPV = 0);
155    void emitExternalSymbolAddress(const char *ES, unsigned Reloc);
156    void emitConstPoolAddress(unsigned CPI, unsigned Reloc);
157    void emitJumpTableAddress(unsigned JTIndex, unsigned Reloc);
158    void emitMachineBasicBlock(MachineBasicBlock *BB, unsigned Reloc,
159                               intptr_t JTBase = 0);
160  };
161}
162
163char ARMCodeEmitter::ID = 0;
164
165/// createARMJITCodeEmitterPass - Return a pass that emits the collected ARM
166/// code to the specified MCE object.
167FunctionPass *llvm::createARMJITCodeEmitterPass(ARMBaseTargetMachine &TM,
168                                                JITCodeEmitter &JCE) {
169  return new ARMCodeEmitter(TM, JCE);
170}
171
172bool ARMCodeEmitter::runOnMachineFunction(MachineFunction &MF) {
173  assert((MF.getTarget().getRelocationModel() != Reloc::Default ||
174          MF.getTarget().getRelocationModel() != Reloc::Static) &&
175         "JIT relocation model must be set to static or default!");
176  JTI = ((ARMTargetMachine&)MF.getTarget()).getJITInfo();
177  II = ((ARMTargetMachine&)MF.getTarget()).getInstrInfo();
178  TD = ((ARMTargetMachine&)MF.getTarget()).getTargetData();
179  Subtarget = &TM.getSubtarget<ARMSubtarget>();
180  MCPEs = &MF.getConstantPool()->getConstants();
181  MJTEs = 0;
182  if (MF.getJumpTableInfo()) MJTEs = &MF.getJumpTableInfo()->getJumpTables();
183  IsPIC = TM.getRelocationModel() == Reloc::PIC_;
184  JTI->Initialize(MF, IsPIC);
185  MCE.setModuleInfo(&getAnalysis<MachineModuleInfo>());
186
187  do {
188    DEBUG(errs() << "JITTing function '"
189          << MF.getFunction()->getName() << "'\n");
190    MCE.startFunction(MF);
191    for (MachineFunction::iterator MBB = MF.begin(), E = MF.end();
192         MBB != E; ++MBB) {
193      MCE.StartMachineBasicBlock(MBB);
194      for (MachineBasicBlock::const_iterator I = MBB->begin(), E = MBB->end();
195           I != E; ++I)
196        emitInstruction(*I);
197    }
198  } while (MCE.finishFunction(MF));
199
200  return false;
201}
202
203/// getShiftOp - Return the shift opcode (bit[6:5]) of the immediate value.
204///
205unsigned ARMCodeEmitter::getShiftOp(unsigned Imm) const {
206  switch (ARM_AM::getAM2ShiftOpc(Imm)) {
207  default: llvm_unreachable("Unknown shift opc!");
208  case ARM_AM::asr: return 2;
209  case ARM_AM::lsl: return 0;
210  case ARM_AM::lsr: return 1;
211  case ARM_AM::ror:
212  case ARM_AM::rrx: return 3;
213  }
214  return 0;
215}
216
217/// getMachineOpValue - Return binary encoding of operand. If the machine
218/// operand requires relocation, record the relocation and return zero.
219unsigned ARMCodeEmitter::getMachineOpValue(const MachineInstr &MI,
220                                           const MachineOperand &MO) {
221  if (MO.isReg())
222    return ARMRegisterInfo::getRegisterNumbering(MO.getReg());
223  else if (MO.isImm())
224    return static_cast<unsigned>(MO.getImm());
225  else if (MO.isGlobal())
226    emitGlobalAddress(MO.getGlobal(), ARM::reloc_arm_branch, true, false);
227  else if (MO.isSymbol())
228    emitExternalSymbolAddress(MO.getSymbolName(), ARM::reloc_arm_branch);
229  else if (MO.isCPI()) {
230    const TargetInstrDesc &TID = MI.getDesc();
231    // For VFP load, the immediate offset is multiplied by 4.
232    unsigned Reloc =  ((TID.TSFlags & ARMII::FormMask) == ARMII::VFPLdStFrm)
233      ? ARM::reloc_arm_vfp_cp_entry : ARM::reloc_arm_cp_entry;
234    emitConstPoolAddress(MO.getIndex(), Reloc);
235  } else if (MO.isJTI())
236    emitJumpTableAddress(MO.getIndex(), ARM::reloc_arm_relative);
237  else if (MO.isMBB())
238    emitMachineBasicBlock(MO.getMBB(), ARM::reloc_arm_branch);
239  else {
240#ifndef NDEBUG
241    errs() << MO;
242#endif
243    llvm_unreachable(0);
244  }
245  return 0;
246}
247
248/// emitGlobalAddress - Emit the specified address to the code stream.
249///
250void ARMCodeEmitter::emitGlobalAddress(GlobalValue *GV, unsigned Reloc,
251                                       bool MayNeedFarStub, bool Indirect,
252                                       intptr_t ACPV) {
253  MachineRelocation MR = Indirect
254    ? MachineRelocation::getIndirectSymbol(MCE.getCurrentPCOffset(), Reloc,
255                                           GV, ACPV, MayNeedFarStub)
256    : MachineRelocation::getGV(MCE.getCurrentPCOffset(), Reloc,
257                               GV, ACPV, MayNeedFarStub);
258  MCE.addRelocation(MR);
259}
260
261/// emitExternalSymbolAddress - Arrange for the address of an external symbol to
262/// be emitted to the current location in the function, and allow it to be PC
263/// relative.
264void ARMCodeEmitter::emitExternalSymbolAddress(const char *ES, unsigned Reloc) {
265  MCE.addRelocation(MachineRelocation::getExtSym(MCE.getCurrentPCOffset(),
266                                                 Reloc, ES));
267}
268
269/// emitConstPoolAddress - Arrange for the address of an constant pool
270/// to be emitted to the current location in the function, and allow it to be PC
271/// relative.
272void ARMCodeEmitter::emitConstPoolAddress(unsigned CPI, unsigned Reloc) {
273  // Tell JIT emitter we'll resolve the address.
274  MCE.addRelocation(MachineRelocation::getConstPool(MCE.getCurrentPCOffset(),
275                                                    Reloc, CPI, 0, true));
276}
277
278/// emitJumpTableAddress - Arrange for the address of a jump table to
279/// be emitted to the current location in the function, and allow it to be PC
280/// relative.
281void ARMCodeEmitter::emitJumpTableAddress(unsigned JTIndex, unsigned Reloc) {
282  MCE.addRelocation(MachineRelocation::getJumpTable(MCE.getCurrentPCOffset(),
283                                                    Reloc, JTIndex, 0, true));
284}
285
286/// emitMachineBasicBlock - Emit the specified address basic block.
287void ARMCodeEmitter::emitMachineBasicBlock(MachineBasicBlock *BB,
288                                           unsigned Reloc, intptr_t JTBase) {
289  MCE.addRelocation(MachineRelocation::getBB(MCE.getCurrentPCOffset(),
290                                             Reloc, BB, JTBase));
291}
292
293void ARMCodeEmitter::emitWordLE(unsigned Binary) {
294  DEBUG(errs() << "  0x";
295        errs().write_hex(Binary) << "\n");
296  MCE.emitWordLE(Binary);
297}
298
299void ARMCodeEmitter::emitDWordLE(uint64_t Binary) {
300  DEBUG(errs() << "  0x";
301        errs().write_hex(Binary) << "\n");
302  MCE.emitDWordLE(Binary);
303}
304
305void ARMCodeEmitter::emitInstruction(const MachineInstr &MI) {
306  DEBUG(errs() << "JIT: " << (void*)MCE.getCurrentPCValue() << ":\t" << MI);
307
308  MCE.processDebugLoc(MI.getDebugLoc(), true);
309
310  NumEmitted++;  // Keep track of the # of mi's emitted
311  switch (MI.getDesc().TSFlags & ARMII::FormMask) {
312  default: {
313    llvm_unreachable("Unhandled instruction encoding format!");
314    break;
315  }
316  case ARMII::Pseudo:
317    emitPseudoInstruction(MI);
318    break;
319  case ARMII::DPFrm:
320  case ARMII::DPSoRegFrm:
321    emitDataProcessingInstruction(MI);
322    break;
323  case ARMII::LdFrm:
324  case ARMII::StFrm:
325    emitLoadStoreInstruction(MI);
326    break;
327  case ARMII::LdMiscFrm:
328  case ARMII::StMiscFrm:
329    emitMiscLoadStoreInstruction(MI);
330    break;
331  case ARMII::LdStMulFrm:
332    emitLoadStoreMultipleInstruction(MI);
333    break;
334  case ARMII::MulFrm:
335    emitMulFrmInstruction(MI);
336    break;
337  case ARMII::ExtFrm:
338    emitExtendInstruction(MI);
339    break;
340  case ARMII::ArithMiscFrm:
341    emitMiscArithInstruction(MI);
342    break;
343  case ARMII::BrFrm:
344    emitBranchInstruction(MI);
345    break;
346  case ARMII::BrMiscFrm:
347    emitMiscBranchInstruction(MI);
348    break;
349  // VFP instructions.
350  case ARMII::VFPUnaryFrm:
351  case ARMII::VFPBinaryFrm:
352    emitVFPArithInstruction(MI);
353    break;
354  case ARMII::VFPConv1Frm:
355  case ARMII::VFPConv2Frm:
356  case ARMII::VFPConv3Frm:
357  case ARMII::VFPConv4Frm:
358  case ARMII::VFPConv5Frm:
359    emitVFPConversionInstruction(MI);
360    break;
361  case ARMII::VFPLdStFrm:
362    emitVFPLoadStoreInstruction(MI);
363    break;
364  case ARMII::VFPLdStMulFrm:
365    emitVFPLoadStoreMultipleInstruction(MI);
366    break;
367  case ARMII::VFPMiscFrm:
368    emitMiscInstruction(MI);
369    break;
370  }
371  MCE.processDebugLoc(MI.getDebugLoc(), false);
372}
373
374void ARMCodeEmitter::emitConstPoolInstruction(const MachineInstr &MI) {
375  unsigned CPI = MI.getOperand(0).getImm();       // CP instruction index.
376  unsigned CPIndex = MI.getOperand(1).getIndex(); // Actual cp entry index.
377  const MachineConstantPoolEntry &MCPE = (*MCPEs)[CPIndex];
378
379  // Remember the CONSTPOOL_ENTRY address for later relocation.
380  JTI->addConstantPoolEntryAddr(CPI, MCE.getCurrentPCValue());
381
382  // Emit constpool island entry. In most cases, the actual values will be
383  // resolved and relocated after code emission.
384  if (MCPE.isMachineConstantPoolEntry()) {
385    ARMConstantPoolValue *ACPV =
386      static_cast<ARMConstantPoolValue*>(MCPE.Val.MachineCPVal);
387
388    DEBUG(errs() << "  ** ARM constant pool #" << CPI << " @ "
389          << (void*)MCE.getCurrentPCValue() << " " << *ACPV << '\n');
390
391    assert(ACPV->isGlobalValue() && "unsupported constant pool value");
392    GlobalValue *GV = ACPV->getGV();
393    if (GV) {
394      Reloc::Model RelocM = TM.getRelocationModel();
395      emitGlobalAddress(GV, ARM::reloc_arm_machine_cp_entry,
396                        isa<Function>(GV),
397                        Subtarget->GVIsIndirectSymbol(GV, RelocM),
398                        (intptr_t)ACPV);
399     } else  {
400      emitExternalSymbolAddress(ACPV->getSymbol(), ARM::reloc_arm_absolute);
401    }
402    emitWordLE(0);
403  } else {
404    Constant *CV = MCPE.Val.ConstVal;
405
406    DEBUG({
407        errs() << "  ** Constant pool #" << CPI << " @ "
408               << (void*)MCE.getCurrentPCValue() << " ";
409        if (const Function *F = dyn_cast<Function>(CV))
410          errs() << F->getName();
411        else
412          errs() << *CV;
413        errs() << '\n';
414      });
415
416    if (GlobalValue *GV = dyn_cast<GlobalValue>(CV)) {
417      emitGlobalAddress(GV, ARM::reloc_arm_absolute, isa<Function>(GV), false);
418      emitWordLE(0);
419    } else if (const ConstantInt *CI = dyn_cast<ConstantInt>(CV)) {
420      uint32_t Val = *(uint32_t*)CI->getValue().getRawData();
421      emitWordLE(Val);
422    } else if (const ConstantFP *CFP = dyn_cast<ConstantFP>(CV)) {
423      if (CFP->getType()->isFloatTy())
424        emitWordLE(CFP->getValueAPF().bitcastToAPInt().getZExtValue());
425      else if (CFP->getType()->isDoubleTy())
426        emitDWordLE(CFP->getValueAPF().bitcastToAPInt().getZExtValue());
427      else {
428        llvm_unreachable("Unable to handle this constantpool entry!");
429      }
430    } else {
431      llvm_unreachable("Unable to handle this constantpool entry!");
432    }
433  }
434}
435
436void ARMCodeEmitter::emitMOVi2piecesInstruction(const MachineInstr &MI) {
437  const MachineOperand &MO0 = MI.getOperand(0);
438  const MachineOperand &MO1 = MI.getOperand(1);
439  assert(MO1.isImm() && ARM_AM::isSOImmTwoPartVal(MO1.getImm()) &&
440                                                  "Not a valid so_imm value!");
441  unsigned V1 = ARM_AM::getSOImmTwoPartFirst(MO1.getImm());
442  unsigned V2 = ARM_AM::getSOImmTwoPartSecond(MO1.getImm());
443
444  // Emit the 'mov' instruction.
445  unsigned Binary = 0xd << 21;  // mov: Insts{24-21} = 0b1101
446
447  // Set the conditional execution predicate.
448  Binary |= II->getPredicate(&MI) << ARMII::CondShift;
449
450  // Encode Rd.
451  Binary |= getMachineOpValue(MI, MO0) << ARMII::RegRdShift;
452
453  // Encode so_imm.
454  // Set bit I(25) to identify this is the immediate form of <shifter_op>
455  Binary |= 1 << ARMII::I_BitShift;
456  Binary |= getMachineSoImmOpValue(V1);
457  emitWordLE(Binary);
458
459  // Now the 'orr' instruction.
460  Binary = 0xc << 21;  // orr: Insts{24-21} = 0b1100
461
462  // Set the conditional execution predicate.
463  Binary |= II->getPredicate(&MI) << ARMII::CondShift;
464
465  // Encode Rd.
466  Binary |= getMachineOpValue(MI, MO0) << ARMII::RegRdShift;
467
468  // Encode Rn.
469  Binary |= getMachineOpValue(MI, MO0) << ARMII::RegRnShift;
470
471  // Encode so_imm.
472  // Set bit I(25) to identify this is the immediate form of <shifter_op>
473  Binary |= 1 << ARMII::I_BitShift;
474  Binary |= getMachineSoImmOpValue(V2);
475  emitWordLE(Binary);
476}
477
478void ARMCodeEmitter::emitLEApcrelJTInstruction(const MachineInstr &MI) {
479  // It's basically add r, pc, (LJTI - $+8)
480
481  const TargetInstrDesc &TID = MI.getDesc();
482
483  // Emit the 'add' instruction.
484  unsigned Binary = 0x4 << 21;  // add: Insts{24-31} = 0b0100
485
486  // Set the conditional execution predicate
487  Binary |= II->getPredicate(&MI) << ARMII::CondShift;
488
489  // Encode S bit if MI modifies CPSR.
490  Binary |= getAddrModeSBit(MI, TID);
491
492  // Encode Rd.
493  Binary |= getMachineOpValue(MI, 0) << ARMII::RegRdShift;
494
495  // Encode Rn which is PC.
496  Binary |= ARMRegisterInfo::getRegisterNumbering(ARM::PC) << ARMII::RegRnShift;
497
498  // Encode the displacement.
499  Binary |= 1 << ARMII::I_BitShift;
500  emitJumpTableAddress(MI.getOperand(1).getIndex(), ARM::reloc_arm_jt_base);
501
502  emitWordLE(Binary);
503}
504
505void ARMCodeEmitter::emitPseudoMoveInstruction(const MachineInstr &MI) {
506  unsigned Opcode = MI.getDesc().Opcode;
507
508  // Part of binary is determined by TableGn.
509  unsigned Binary = getBinaryCodeForInstr(MI);
510
511  // Set the conditional execution predicate
512  Binary |= II->getPredicate(&MI) << ARMII::CondShift;
513
514  // Encode S bit if MI modifies CPSR.
515  if (Opcode == ARM::MOVsrl_flag || Opcode == ARM::MOVsra_flag)
516    Binary |= 1 << ARMII::S_BitShift;
517
518  // Encode register def if there is one.
519  Binary |= getMachineOpValue(MI, 0) << ARMII::RegRdShift;
520
521  // Encode the shift operation.
522  switch (Opcode) {
523  default: break;
524  case ARM::MOVrx:
525    // rrx
526    Binary |= 0x6 << 4;
527    break;
528  case ARM::MOVsrl_flag:
529    // lsr #1
530    Binary |= (0x2 << 4) | (1 << 7);
531    break;
532  case ARM::MOVsra_flag:
533    // asr #1
534    Binary |= (0x4 << 4) | (1 << 7);
535    break;
536  }
537
538  // Encode register Rm.
539  Binary |= getMachineOpValue(MI, 1);
540
541  emitWordLE(Binary);
542}
543
544void ARMCodeEmitter::addPCLabel(unsigned LabelID) {
545  DEBUG(errs() << "  ** LPC" << LabelID << " @ "
546        << (void*)MCE.getCurrentPCValue() << '\n');
547  JTI->addPCLabelAddr(LabelID, MCE.getCurrentPCValue());
548}
549
550void ARMCodeEmitter::emitPseudoInstruction(const MachineInstr &MI) {
551  unsigned Opcode = MI.getDesc().Opcode;
552  switch (Opcode) {
553  default:
554    llvm_unreachable("ARMCodeEmitter::emitPseudoInstruction");
555  // FIXME: Add support for MOVimm32.
556  case TargetOpcode::INLINEASM: {
557    // We allow inline assembler nodes with empty bodies - they can
558    // implicitly define registers, which is ok for JIT.
559    if (MI.getOperand(0).getSymbolName()[0]) {
560      llvm_report_error("JIT does not support inline asm!");
561    }
562    break;
563  }
564  case TargetOpcode::DBG_LABEL:
565  case TargetOpcode::EH_LABEL:
566    MCE.emitLabel(MI.getOperand(0).getImm());
567    break;
568  case TargetOpcode::IMPLICIT_DEF:
569  case TargetOpcode::KILL:
570    // Do nothing.
571    break;
572  case ARM::CONSTPOOL_ENTRY:
573    emitConstPoolInstruction(MI);
574    break;
575  case ARM::PICADD: {
576    // Remember of the address of the PC label for relocation later.
577    addPCLabel(MI.getOperand(2).getImm());
578    // PICADD is just an add instruction that implicitly read pc.
579    emitDataProcessingInstruction(MI, 0, ARM::PC);
580    break;
581  }
582  case ARM::PICLDR:
583  case ARM::PICLDRB:
584  case ARM::PICSTR:
585  case ARM::PICSTRB: {
586    // Remember of the address of the PC label for relocation later.
587    addPCLabel(MI.getOperand(2).getImm());
588    // These are just load / store instructions that implicitly read pc.
589    emitLoadStoreInstruction(MI, 0, ARM::PC);
590    break;
591  }
592  case ARM::PICLDRH:
593  case ARM::PICLDRSH:
594  case ARM::PICLDRSB:
595  case ARM::PICSTRH: {
596    // Remember of the address of the PC label for relocation later.
597    addPCLabel(MI.getOperand(2).getImm());
598    // These are just load / store instructions that implicitly read pc.
599    emitMiscLoadStoreInstruction(MI, ARM::PC);
600    break;
601  }
602  case ARM::MOVi2pieces:
603    // Two instructions to materialize a constant.
604    emitMOVi2piecesInstruction(MI);
605    break;
606  case ARM::LEApcrelJT:
607    // Materialize jumptable address.
608    emitLEApcrelJTInstruction(MI);
609    break;
610  case ARM::MOVrx:
611  case ARM::MOVsrl_flag:
612  case ARM::MOVsra_flag:
613    emitPseudoMoveInstruction(MI);
614    break;
615  }
616}
617
618unsigned ARMCodeEmitter::getMachineSoRegOpValue(
619                                                const MachineInstr &MI,
620                                                const TargetInstrDesc &TID,
621                                                const MachineOperand &MO,
622                                                unsigned OpIdx) {
623  unsigned Binary = getMachineOpValue(MI, MO);
624
625  const MachineOperand &MO1 = MI.getOperand(OpIdx + 1);
626  const MachineOperand &MO2 = MI.getOperand(OpIdx + 2);
627  ARM_AM::ShiftOpc SOpc = ARM_AM::getSORegShOp(MO2.getImm());
628
629  // Encode the shift opcode.
630  unsigned SBits = 0;
631  unsigned Rs = MO1.getReg();
632  if (Rs) {
633    // Set shift operand (bit[7:4]).
634    // LSL - 0001
635    // LSR - 0011
636    // ASR - 0101
637    // ROR - 0111
638    // RRX - 0110 and bit[11:8] clear.
639    switch (SOpc) {
640    default: llvm_unreachable("Unknown shift opc!");
641    case ARM_AM::lsl: SBits = 0x1; break;
642    case ARM_AM::lsr: SBits = 0x3; break;
643    case ARM_AM::asr: SBits = 0x5; break;
644    case ARM_AM::ror: SBits = 0x7; break;
645    case ARM_AM::rrx: SBits = 0x6; break;
646    }
647  } else {
648    // Set shift operand (bit[6:4]).
649    // LSL - 000
650    // LSR - 010
651    // ASR - 100
652    // ROR - 110
653    switch (SOpc) {
654    default: llvm_unreachable("Unknown shift opc!");
655    case ARM_AM::lsl: SBits = 0x0; break;
656    case ARM_AM::lsr: SBits = 0x2; break;
657    case ARM_AM::asr: SBits = 0x4; break;
658    case ARM_AM::ror: SBits = 0x6; break;
659    }
660  }
661  Binary |= SBits << 4;
662  if (SOpc == ARM_AM::rrx)
663    return Binary;
664
665  // Encode the shift operation Rs or shift_imm (except rrx).
666  if (Rs) {
667    // Encode Rs bit[11:8].
668    assert(ARM_AM::getSORegOffset(MO2.getImm()) == 0);
669    return Binary |
670      (ARMRegisterInfo::getRegisterNumbering(Rs) << ARMII::RegRsShift);
671  }
672
673  // Encode shift_imm bit[11:7].
674  return Binary | ARM_AM::getSORegOffset(MO2.getImm()) << 7;
675}
676
677unsigned ARMCodeEmitter::getMachineSoImmOpValue(unsigned SoImm) {
678  int SoImmVal = ARM_AM::getSOImmVal(SoImm);
679  assert(SoImmVal != -1 && "Not a valid so_imm value!");
680
681  // Encode rotate_imm.
682  unsigned Binary = (ARM_AM::getSOImmValRot((unsigned)SoImmVal) >> 1)
683    << ARMII::SoRotImmShift;
684
685  // Encode immed_8.
686  Binary |= ARM_AM::getSOImmValImm((unsigned)SoImmVal);
687  return Binary;
688}
689
690unsigned ARMCodeEmitter::getAddrModeSBit(const MachineInstr &MI,
691                                             const TargetInstrDesc &TID) const {
692  for (unsigned i = MI.getNumOperands(), e = TID.getNumOperands(); i != e; --i){
693    const MachineOperand &MO = MI.getOperand(i-1);
694    if (MO.isReg() && MO.isDef() && MO.getReg() == ARM::CPSR)
695      return 1 << ARMII::S_BitShift;
696  }
697  return 0;
698}
699
700void ARMCodeEmitter::emitDataProcessingInstruction(
701                                                   const MachineInstr &MI,
702                                                   unsigned ImplicitRd,
703                                                   unsigned ImplicitRn) {
704  const TargetInstrDesc &TID = MI.getDesc();
705
706  if (TID.Opcode == ARM::BFC) {
707    llvm_report_error("ARMv6t2 JIT is not yet supported.");
708  }
709
710  // Part of binary is determined by TableGn.
711  unsigned Binary = getBinaryCodeForInstr(MI);
712
713  // Set the conditional execution predicate
714  Binary |= II->getPredicate(&MI) << ARMII::CondShift;
715
716  // Encode S bit if MI modifies CPSR.
717  Binary |= getAddrModeSBit(MI, TID);
718
719  // Encode register def if there is one.
720  unsigned NumDefs = TID.getNumDefs();
721  unsigned OpIdx = 0;
722  if (NumDefs)
723    Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRdShift;
724  else if (ImplicitRd)
725    // Special handling for implicit use (e.g. PC).
726    Binary |= (ARMRegisterInfo::getRegisterNumbering(ImplicitRd)
727               << ARMII::RegRdShift);
728
729  // If this is a two-address operand, skip it. e.g. MOVCCr operand 1.
730  if (TID.getOperandConstraint(OpIdx, TOI::TIED_TO) != -1)
731    ++OpIdx;
732
733  // Encode first non-shifter register operand if there is one.
734  bool isUnary = TID.TSFlags & ARMII::UnaryDP;
735  if (!isUnary) {
736    if (ImplicitRn)
737      // Special handling for implicit use (e.g. PC).
738      Binary |= (ARMRegisterInfo::getRegisterNumbering(ImplicitRn)
739                 << ARMII::RegRnShift);
740    else {
741      Binary |= getMachineOpValue(MI, OpIdx) << ARMII::RegRnShift;
742      ++OpIdx;
743    }
744  }
745
746  // Encode shifter operand.
747  const MachineOperand &MO = MI.getOperand(OpIdx);
748  if ((TID.TSFlags & ARMII::FormMask) == ARMII::DPSoRegFrm) {
749    // Encode SoReg.
750    emitWordLE(Binary | getMachineSoRegOpValue(MI, TID, MO, OpIdx));
751    return;
752  }
753
754  if (MO.isReg()) {
755    // Encode register Rm.
756    emitWordLE(Binary | ARMRegisterInfo::getRegisterNumbering(MO.getReg()));
757    return;
758  }
759
760  // Encode so_imm.
761  Binary |= getMachineSoImmOpValue((unsigned)MO.getImm());
762
763  emitWordLE(Binary);
764}
765
766void ARMCodeEmitter::emitLoadStoreInstruction(
767                                              const MachineInstr &MI,
768                                              unsigned ImplicitRd,
769                                              unsigned ImplicitRn) {
770  const TargetInstrDesc &TID = MI.getDesc();
771  unsigned Form = TID.TSFlags & ARMII::FormMask;
772  bool IsPrePost = (TID.TSFlags & ARMII::IndexModeMask) != 0;
773
774  // Part of binary is determined by TableGn.
775  unsigned Binary = getBinaryCodeForInstr(MI);
776
777  // Set the conditional execution predicate
778  Binary |= II->getPredicate(&MI) << ARMII::CondShift;
779
780  unsigned OpIdx = 0;
781
782  // Operand 0 of a pre- and post-indexed store is the address base
783  // writeback. Skip it.
784  bool Skipped = false;
785  if (IsPrePost && Form == ARMII::StFrm) {
786    ++OpIdx;
787    Skipped = true;
788  }
789
790  // Set first operand
791  if (ImplicitRd)
792    // Special handling for implicit use (e.g. PC).
793    Binary |= (ARMRegisterInfo::getRegisterNumbering(ImplicitRd)
794               << ARMII::RegRdShift);
795  else
796    Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRdShift;
797
798  // Set second operand
799  if (ImplicitRn)
800    // Special handling for implicit use (e.g. PC).
801    Binary |= (ARMRegisterInfo::getRegisterNumbering(ImplicitRn)
802               << ARMII::RegRnShift);
803  else
804    Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRnShift;
805
806  // If this is a two-address operand, skip it. e.g. LDR_PRE.
807  if (!Skipped && TID.getOperandConstraint(OpIdx, TOI::TIED_TO) != -1)
808    ++OpIdx;
809
810  const MachineOperand &MO2 = MI.getOperand(OpIdx);
811  unsigned AM2Opc = (ImplicitRn == ARM::PC)
812    ? 0 : MI.getOperand(OpIdx+1).getImm();
813
814  // Set bit U(23) according to sign of immed value (positive or negative).
815  Binary |= ((ARM_AM::getAM2Op(AM2Opc) == ARM_AM::add ? 1 : 0) <<
816             ARMII::U_BitShift);
817  if (!MO2.getReg()) { // is immediate
818    if (ARM_AM::getAM2Offset(AM2Opc))
819      // Set the value of offset_12 field
820      Binary |= ARM_AM::getAM2Offset(AM2Opc);
821    emitWordLE(Binary);
822    return;
823  }
824
825  // Set bit I(25), because this is not in immediate enconding.
826  Binary |= 1 << ARMII::I_BitShift;
827  assert(TargetRegisterInfo::isPhysicalRegister(MO2.getReg()));
828  // Set bit[3:0] to the corresponding Rm register
829  Binary |= ARMRegisterInfo::getRegisterNumbering(MO2.getReg());
830
831  // If this instr is in scaled register offset/index instruction, set
832  // shift_immed(bit[11:7]) and shift(bit[6:5]) fields.
833  if (unsigned ShImm = ARM_AM::getAM2Offset(AM2Opc)) {
834    Binary |= getShiftOp(AM2Opc) << ARMII::ShiftImmShift;  // shift
835    Binary |= ShImm              << ARMII::ShiftShift;     // shift_immed
836  }
837
838  emitWordLE(Binary);
839}
840
841void ARMCodeEmitter::emitMiscLoadStoreInstruction(const MachineInstr &MI,
842                                                        unsigned ImplicitRn) {
843  const TargetInstrDesc &TID = MI.getDesc();
844  unsigned Form = TID.TSFlags & ARMII::FormMask;
845  bool IsPrePost = (TID.TSFlags & ARMII::IndexModeMask) != 0;
846
847  // Part of binary is determined by TableGn.
848  unsigned Binary = getBinaryCodeForInstr(MI);
849
850  // Set the conditional execution predicate
851  Binary |= II->getPredicate(&MI) << ARMII::CondShift;
852
853  unsigned OpIdx = 0;
854
855  // Operand 0 of a pre- and post-indexed store is the address base
856  // writeback. Skip it.
857  bool Skipped = false;
858  if (IsPrePost && Form == ARMII::StMiscFrm) {
859    ++OpIdx;
860    Skipped = true;
861  }
862
863  // Set first operand
864  Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRdShift;
865
866  // Skip LDRD and STRD's second operand.
867  if (TID.Opcode == ARM::LDRD || TID.Opcode == ARM::STRD)
868    ++OpIdx;
869
870  // Set second operand
871  if (ImplicitRn)
872    // Special handling for implicit use (e.g. PC).
873    Binary |= (ARMRegisterInfo::getRegisterNumbering(ImplicitRn)
874               << ARMII::RegRnShift);
875  else
876    Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRnShift;
877
878  // If this is a two-address operand, skip it. e.g. LDRH_POST.
879  if (!Skipped && TID.getOperandConstraint(OpIdx, TOI::TIED_TO) != -1)
880    ++OpIdx;
881
882  const MachineOperand &MO2 = MI.getOperand(OpIdx);
883  unsigned AM3Opc = (ImplicitRn == ARM::PC)
884    ? 0 : MI.getOperand(OpIdx+1).getImm();
885
886  // Set bit U(23) according to sign of immed value (positive or negative)
887  Binary |= ((ARM_AM::getAM3Op(AM3Opc) == ARM_AM::add ? 1 : 0) <<
888             ARMII::U_BitShift);
889
890  // If this instr is in register offset/index encoding, set bit[3:0]
891  // to the corresponding Rm register.
892  if (MO2.getReg()) {
893    Binary |= ARMRegisterInfo::getRegisterNumbering(MO2.getReg());
894    emitWordLE(Binary);
895    return;
896  }
897
898  // This instr is in immediate offset/index encoding, set bit 22 to 1.
899  Binary |= 1 << ARMII::AM3_I_BitShift;
900  if (unsigned ImmOffs = ARM_AM::getAM3Offset(AM3Opc)) {
901    // Set operands
902    Binary |= (ImmOffs >> 4) << ARMII::ImmHiShift;  // immedH
903    Binary |= (ImmOffs & 0xF);                      // immedL
904  }
905
906  emitWordLE(Binary);
907}
908
909static unsigned getAddrModeUPBits(unsigned Mode) {
910  unsigned Binary = 0;
911
912  // Set addressing mode by modifying bits U(23) and P(24)
913  // IA - Increment after  - bit U = 1 and bit P = 0
914  // IB - Increment before - bit U = 1 and bit P = 1
915  // DA - Decrement after  - bit U = 0 and bit P = 0
916  // DB - Decrement before - bit U = 0 and bit P = 1
917  switch (Mode) {
918  default: llvm_unreachable("Unknown addressing sub-mode!");
919  case ARM_AM::da:                                     break;
920  case ARM_AM::db: Binary |= 0x1 << ARMII::P_BitShift; break;
921  case ARM_AM::ia: Binary |= 0x1 << ARMII::U_BitShift; break;
922  case ARM_AM::ib: Binary |= 0x3 << ARMII::U_BitShift; break;
923  }
924
925  return Binary;
926}
927
928void ARMCodeEmitter::emitLoadStoreMultipleInstruction(const MachineInstr &MI) {
929  const TargetInstrDesc &TID = MI.getDesc();
930  bool IsUpdating = (TID.TSFlags & ARMII::IndexModeMask) != 0;
931
932  // Part of binary is determined by TableGn.
933  unsigned Binary = getBinaryCodeForInstr(MI);
934
935  // Set the conditional execution predicate
936  Binary |= II->getPredicate(&MI) << ARMII::CondShift;
937
938  // Skip operand 0 of an instruction with base register update.
939  unsigned OpIdx = 0;
940  if (IsUpdating)
941    ++OpIdx;
942
943  // Set base address operand
944  Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRnShift;
945
946  // Set addressing mode by modifying bits U(23) and P(24)
947  const MachineOperand &MO = MI.getOperand(OpIdx++);
948  Binary |= getAddrModeUPBits(ARM_AM::getAM4SubMode(MO.getImm()));
949
950  // Set bit W(21)
951  if (ARM_AM::getAM4WBFlag(MO.getImm()))
952    Binary |= 0x1 << ARMII::W_BitShift;
953
954  // Set registers
955  for (unsigned i = OpIdx+2, e = MI.getNumOperands(); i != e; ++i) {
956    const MachineOperand &MO = MI.getOperand(i);
957    if (!MO.isReg() || MO.isImplicit())
958      break;
959    unsigned RegNum = ARMRegisterInfo::getRegisterNumbering(MO.getReg());
960    assert(TargetRegisterInfo::isPhysicalRegister(MO.getReg()) &&
961           RegNum < 16);
962    Binary |= 0x1 << RegNum;
963  }
964
965  emitWordLE(Binary);
966}
967
968void ARMCodeEmitter::emitMulFrmInstruction(const MachineInstr &MI) {
969  const TargetInstrDesc &TID = MI.getDesc();
970
971  // Part of binary is determined by TableGn.
972  unsigned Binary = getBinaryCodeForInstr(MI);
973
974  // Set the conditional execution predicate
975  Binary |= II->getPredicate(&MI) << ARMII::CondShift;
976
977  // Encode S bit if MI modifies CPSR.
978  Binary |= getAddrModeSBit(MI, TID);
979
980  // 32x32->64bit operations have two destination registers. The number
981  // of register definitions will tell us if that's what we're dealing with.
982  unsigned OpIdx = 0;
983  if (TID.getNumDefs() == 2)
984    Binary |= getMachineOpValue (MI, OpIdx++) << ARMII::RegRdLoShift;
985
986  // Encode Rd
987  Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRdHiShift;
988
989  // Encode Rm
990  Binary |= getMachineOpValue(MI, OpIdx++);
991
992  // Encode Rs
993  Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRsShift;
994
995  // Many multiple instructions (e.g. MLA) have three src operands. Encode
996  // it as Rn (for multiply, that's in the same offset as RdLo.
997  if (TID.getNumOperands() > OpIdx &&
998      !TID.OpInfo[OpIdx].isPredicate() &&
999      !TID.OpInfo[OpIdx].isOptionalDef())
1000    Binary |= getMachineOpValue(MI, OpIdx) << ARMII::RegRdLoShift;
1001
1002  emitWordLE(Binary);
1003}
1004
1005void ARMCodeEmitter::emitExtendInstruction(const MachineInstr &MI) {
1006  const TargetInstrDesc &TID = MI.getDesc();
1007
1008  // Part of binary is determined by TableGn.
1009  unsigned Binary = getBinaryCodeForInstr(MI);
1010
1011  // Set the conditional execution predicate
1012  Binary |= II->getPredicate(&MI) << ARMII::CondShift;
1013
1014  unsigned OpIdx = 0;
1015
1016  // Encode Rd
1017  Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRdShift;
1018
1019  const MachineOperand &MO1 = MI.getOperand(OpIdx++);
1020  const MachineOperand &MO2 = MI.getOperand(OpIdx);
1021  if (MO2.isReg()) {
1022    // Two register operand form.
1023    // Encode Rn.
1024    Binary |= getMachineOpValue(MI, MO1) << ARMII::RegRnShift;
1025
1026    // Encode Rm.
1027    Binary |= getMachineOpValue(MI, MO2);
1028    ++OpIdx;
1029  } else {
1030    Binary |= getMachineOpValue(MI, MO1);
1031  }
1032
1033  // Encode rot imm (0, 8, 16, or 24) if it has a rotate immediate operand.
1034  if (MI.getOperand(OpIdx).isImm() &&
1035      !TID.OpInfo[OpIdx].isPredicate() &&
1036      !TID.OpInfo[OpIdx].isOptionalDef())
1037    Binary |= (getMachineOpValue(MI, OpIdx) / 8) << ARMII::ExtRotImmShift;
1038
1039  emitWordLE(Binary);
1040}
1041
1042void ARMCodeEmitter::emitMiscArithInstruction(const MachineInstr &MI) {
1043  const TargetInstrDesc &TID = MI.getDesc();
1044
1045  // Part of binary is determined by TableGn.
1046  unsigned Binary = getBinaryCodeForInstr(MI);
1047
1048  // Set the conditional execution predicate
1049  Binary |= II->getPredicate(&MI) << ARMII::CondShift;
1050
1051  unsigned OpIdx = 0;
1052
1053  // Encode Rd
1054  Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRdShift;
1055
1056  const MachineOperand &MO = MI.getOperand(OpIdx++);
1057  if (OpIdx == TID.getNumOperands() ||
1058      TID.OpInfo[OpIdx].isPredicate() ||
1059      TID.OpInfo[OpIdx].isOptionalDef()) {
1060    // Encode Rm and it's done.
1061    Binary |= getMachineOpValue(MI, MO);
1062    emitWordLE(Binary);
1063    return;
1064  }
1065
1066  // Encode Rn.
1067  Binary |= getMachineOpValue(MI, MO) << ARMII::RegRnShift;
1068
1069  // Encode Rm.
1070  Binary |= getMachineOpValue(MI, OpIdx++);
1071
1072  // Encode shift_imm.
1073  unsigned ShiftAmt = MI.getOperand(OpIdx).getImm();
1074  assert(ShiftAmt < 32 && "shift_imm range is 0 to 31!");
1075  Binary |= ShiftAmt << ARMII::ShiftShift;
1076
1077  emitWordLE(Binary);
1078}
1079
1080void ARMCodeEmitter::emitBranchInstruction(const MachineInstr &MI) {
1081  const TargetInstrDesc &TID = MI.getDesc();
1082
1083  if (TID.Opcode == ARM::TPsoft) {
1084    llvm_unreachable("ARM::TPsoft FIXME"); // FIXME
1085  }
1086
1087  // Part of binary is determined by TableGn.
1088  unsigned Binary = getBinaryCodeForInstr(MI);
1089
1090  // Set the conditional execution predicate
1091  Binary |= II->getPredicate(&MI) << ARMII::CondShift;
1092
1093  // Set signed_immed_24 field
1094  Binary |= getMachineOpValue(MI, 0);
1095
1096  emitWordLE(Binary);
1097}
1098
1099void ARMCodeEmitter::emitInlineJumpTable(unsigned JTIndex) {
1100  // Remember the base address of the inline jump table.
1101  uintptr_t JTBase = MCE.getCurrentPCValue();
1102  JTI->addJumpTableBaseAddr(JTIndex, JTBase);
1103  DEBUG(errs() << "  ** Jump Table #" << JTIndex << " @ " << (void*)JTBase
1104               << '\n');
1105
1106  // Now emit the jump table entries.
1107  const std::vector<MachineBasicBlock*> &MBBs = (*MJTEs)[JTIndex].MBBs;
1108  for (unsigned i = 0, e = MBBs.size(); i != e; ++i) {
1109    if (IsPIC)
1110      // DestBB address - JT base.
1111      emitMachineBasicBlock(MBBs[i], ARM::reloc_arm_pic_jt, JTBase);
1112    else
1113      // Absolute DestBB address.
1114      emitMachineBasicBlock(MBBs[i], ARM::reloc_arm_absolute);
1115    emitWordLE(0);
1116  }
1117}
1118
1119void ARMCodeEmitter::emitMiscBranchInstruction(const MachineInstr &MI) {
1120  const TargetInstrDesc &TID = MI.getDesc();
1121
1122  // Handle jump tables.
1123  if (TID.Opcode == ARM::BR_JTr || TID.Opcode == ARM::BR_JTadd) {
1124    // First emit a ldr pc, [] instruction.
1125    emitDataProcessingInstruction(MI, ARM::PC);
1126
1127    // Then emit the inline jump table.
1128    unsigned JTIndex =
1129      (TID.Opcode == ARM::BR_JTr)
1130      ? MI.getOperand(1).getIndex() : MI.getOperand(2).getIndex();
1131    emitInlineJumpTable(JTIndex);
1132    return;
1133  } else if (TID.Opcode == ARM::BR_JTm) {
1134    // First emit a ldr pc, [] instruction.
1135    emitLoadStoreInstruction(MI, ARM::PC);
1136
1137    // Then emit the inline jump table.
1138    emitInlineJumpTable(MI.getOperand(3).getIndex());
1139    return;
1140  }
1141
1142  // Part of binary is determined by TableGn.
1143  unsigned Binary = getBinaryCodeForInstr(MI);
1144
1145  // Set the conditional execution predicate
1146  Binary |= II->getPredicate(&MI) << ARMII::CondShift;
1147
1148  if (TID.Opcode == ARM::BX_RET || TID.Opcode == ARM::MOVPCLR)
1149    // The return register is LR.
1150    Binary |= ARMRegisterInfo::getRegisterNumbering(ARM::LR);
1151  else
1152    // otherwise, set the return register
1153    Binary |= getMachineOpValue(MI, 0);
1154
1155  emitWordLE(Binary);
1156}
1157
1158static unsigned encodeVFPRd(const MachineInstr &MI, unsigned OpIdx) {
1159  unsigned RegD = MI.getOperand(OpIdx).getReg();
1160  unsigned Binary = 0;
1161  bool isSPVFP = false;
1162  RegD = ARMRegisterInfo::getRegisterNumbering(RegD, &isSPVFP);
1163  if (!isSPVFP)
1164    Binary |=   RegD               << ARMII::RegRdShift;
1165  else {
1166    Binary |= ((RegD & 0x1E) >> 1) << ARMII::RegRdShift;
1167    Binary |=  (RegD & 0x01)       << ARMII::D_BitShift;
1168  }
1169  return Binary;
1170}
1171
1172static unsigned encodeVFPRn(const MachineInstr &MI, unsigned OpIdx) {
1173  unsigned RegN = MI.getOperand(OpIdx).getReg();
1174  unsigned Binary = 0;
1175  bool isSPVFP = false;
1176  RegN = ARMRegisterInfo::getRegisterNumbering(RegN, &isSPVFP);
1177  if (!isSPVFP)
1178    Binary |=   RegN               << ARMII::RegRnShift;
1179  else {
1180    Binary |= ((RegN & 0x1E) >> 1) << ARMII::RegRnShift;
1181    Binary |=  (RegN & 0x01)       << ARMII::N_BitShift;
1182  }
1183  return Binary;
1184}
1185
1186static unsigned encodeVFPRm(const MachineInstr &MI, unsigned OpIdx) {
1187  unsigned RegM = MI.getOperand(OpIdx).getReg();
1188  unsigned Binary = 0;
1189  bool isSPVFP = false;
1190  RegM = ARMRegisterInfo::getRegisterNumbering(RegM, &isSPVFP);
1191  if (!isSPVFP)
1192    Binary |=   RegM;
1193  else {
1194    Binary |= ((RegM & 0x1E) >> 1);
1195    Binary |=  (RegM & 0x01)       << ARMII::M_BitShift;
1196  }
1197  return Binary;
1198}
1199
1200void ARMCodeEmitter::emitVFPArithInstruction(const MachineInstr &MI) {
1201  const TargetInstrDesc &TID = MI.getDesc();
1202
1203  // Part of binary is determined by TableGn.
1204  unsigned Binary = getBinaryCodeForInstr(MI);
1205
1206  // Set the conditional execution predicate
1207  Binary |= II->getPredicate(&MI) << ARMII::CondShift;
1208
1209  unsigned OpIdx = 0;
1210  assert((Binary & ARMII::D_BitShift) == 0 &&
1211         (Binary & ARMII::N_BitShift) == 0 &&
1212         (Binary & ARMII::M_BitShift) == 0 && "VFP encoding bug!");
1213
1214  // Encode Dd / Sd.
1215  Binary |= encodeVFPRd(MI, OpIdx++);
1216
1217  // If this is a two-address operand, skip it, e.g. FMACD.
1218  if (TID.getOperandConstraint(OpIdx, TOI::TIED_TO) != -1)
1219    ++OpIdx;
1220
1221  // Encode Dn / Sn.
1222  if ((TID.TSFlags & ARMII::FormMask) == ARMII::VFPBinaryFrm)
1223    Binary |= encodeVFPRn(MI, OpIdx++);
1224
1225  if (OpIdx == TID.getNumOperands() ||
1226      TID.OpInfo[OpIdx].isPredicate() ||
1227      TID.OpInfo[OpIdx].isOptionalDef()) {
1228    // FCMPEZD etc. has only one operand.
1229    emitWordLE(Binary);
1230    return;
1231  }
1232
1233  // Encode Dm / Sm.
1234  Binary |= encodeVFPRm(MI, OpIdx);
1235
1236  emitWordLE(Binary);
1237}
1238
1239void ARMCodeEmitter::emitVFPConversionInstruction(
1240      const MachineInstr &MI) {
1241  const TargetInstrDesc &TID = MI.getDesc();
1242  unsigned Form = TID.TSFlags & ARMII::FormMask;
1243
1244  // Part of binary is determined by TableGn.
1245  unsigned Binary = getBinaryCodeForInstr(MI);
1246
1247  // Set the conditional execution predicate
1248  Binary |= II->getPredicate(&MI) << ARMII::CondShift;
1249
1250  switch (Form) {
1251  default: break;
1252  case ARMII::VFPConv1Frm:
1253  case ARMII::VFPConv2Frm:
1254  case ARMII::VFPConv3Frm:
1255    // Encode Dd / Sd.
1256    Binary |= encodeVFPRd(MI, 0);
1257    break;
1258  case ARMII::VFPConv4Frm:
1259    // Encode Dn / Sn.
1260    Binary |= encodeVFPRn(MI, 0);
1261    break;
1262  case ARMII::VFPConv5Frm:
1263    // Encode Dm / Sm.
1264    Binary |= encodeVFPRm(MI, 0);
1265    break;
1266  }
1267
1268  switch (Form) {
1269  default: break;
1270  case ARMII::VFPConv1Frm:
1271    // Encode Dm / Sm.
1272    Binary |= encodeVFPRm(MI, 1);
1273    break;
1274  case ARMII::VFPConv2Frm:
1275  case ARMII::VFPConv3Frm:
1276    // Encode Dn / Sn.
1277    Binary |= encodeVFPRn(MI, 1);
1278    break;
1279  case ARMII::VFPConv4Frm:
1280  case ARMII::VFPConv5Frm:
1281    // Encode Dd / Sd.
1282    Binary |= encodeVFPRd(MI, 1);
1283    break;
1284  }
1285
1286  if (Form == ARMII::VFPConv5Frm)
1287    // Encode Dn / Sn.
1288    Binary |= encodeVFPRn(MI, 2);
1289  else if (Form == ARMII::VFPConv3Frm)
1290    // Encode Dm / Sm.
1291    Binary |= encodeVFPRm(MI, 2);
1292
1293  emitWordLE(Binary);
1294}
1295
1296void ARMCodeEmitter::emitVFPLoadStoreInstruction(const MachineInstr &MI) {
1297  // Part of binary is determined by TableGn.
1298  unsigned Binary = getBinaryCodeForInstr(MI);
1299
1300  // Set the conditional execution predicate
1301  Binary |= II->getPredicate(&MI) << ARMII::CondShift;
1302
1303  unsigned OpIdx = 0;
1304
1305  // Encode Dd / Sd.
1306  Binary |= encodeVFPRd(MI, OpIdx++);
1307
1308  // Encode address base.
1309  const MachineOperand &Base = MI.getOperand(OpIdx++);
1310  Binary |= getMachineOpValue(MI, Base) << ARMII::RegRnShift;
1311
1312  // If there is a non-zero immediate offset, encode it.
1313  if (Base.isReg()) {
1314    const MachineOperand &Offset = MI.getOperand(OpIdx);
1315    if (unsigned ImmOffs = ARM_AM::getAM5Offset(Offset.getImm())) {
1316      if (ARM_AM::getAM5Op(Offset.getImm()) == ARM_AM::add)
1317        Binary |= 1 << ARMII::U_BitShift;
1318      Binary |= ImmOffs;
1319      emitWordLE(Binary);
1320      return;
1321    }
1322  }
1323
1324  // If immediate offset is omitted, default to +0.
1325  Binary |= 1 << ARMII::U_BitShift;
1326
1327  emitWordLE(Binary);
1328}
1329
1330void ARMCodeEmitter::emitVFPLoadStoreMultipleInstruction(
1331                                                       const MachineInstr &MI) {
1332  const TargetInstrDesc &TID = MI.getDesc();
1333  bool IsUpdating = (TID.TSFlags & ARMII::IndexModeMask) != 0;
1334
1335  // Part of binary is determined by TableGn.
1336  unsigned Binary = getBinaryCodeForInstr(MI);
1337
1338  // Set the conditional execution predicate
1339  Binary |= II->getPredicate(&MI) << ARMII::CondShift;
1340
1341  // Skip operand 0 of an instruction with base register update.
1342  unsigned OpIdx = 0;
1343  if (IsUpdating)
1344    ++OpIdx;
1345
1346  // Set base address operand
1347  Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRnShift;
1348
1349  // Set addressing mode by modifying bits U(23) and P(24)
1350  const MachineOperand &MO = MI.getOperand(OpIdx++);
1351  Binary |= getAddrModeUPBits(ARM_AM::getAM5SubMode(MO.getImm()));
1352
1353  // Set bit W(21)
1354  if (ARM_AM::getAM5WBFlag(MO.getImm()))
1355    Binary |= 0x1 << ARMII::W_BitShift;
1356
1357  // First register is encoded in Dd.
1358  Binary |= encodeVFPRd(MI, OpIdx+2);
1359
1360  // Number of registers are encoded in offset field.
1361  unsigned NumRegs = 1;
1362  for (unsigned i = OpIdx+3, e = MI.getNumOperands(); i != e; ++i) {
1363    const MachineOperand &MO = MI.getOperand(i);
1364    if (!MO.isReg() || MO.isImplicit())
1365      break;
1366    ++NumRegs;
1367  }
1368  Binary |= NumRegs * 2;
1369
1370  emitWordLE(Binary);
1371}
1372
1373void ARMCodeEmitter::emitMiscInstruction(const MachineInstr &MI) {
1374  // Part of binary is determined by TableGn.
1375  unsigned Binary = getBinaryCodeForInstr(MI);
1376
1377  // Set the conditional execution predicate
1378  Binary |= II->getPredicate(&MI) << ARMII::CondShift;
1379
1380  emitWordLE(Binary);
1381}
1382
1383#include "ARMGenCodeEmitter.inc"
1384