ARMCodeEmitter.cpp revision bc8a94540a65907472bf6d6e43c8fea864116cf5 
1//===-- ARM/ARMCodeEmitter.cpp - Convert ARM code to machine code ---------===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file contains the pass that transforms the ARM machine instructions into
11// relocatable machine code.
12//
13//===----------------------------------------------------------------------===//
14
15#define DEBUG_TYPE "jit"
16#include "ARM.h"
17#include "ARMAddressingModes.h"
18#include "ARMConstantPoolValue.h"
19#include "ARMInstrInfo.h"
20#include "ARMRelocations.h"
21#include "ARMSubtarget.h"
22#include "ARMTargetMachine.h"
23#include "llvm/Constants.h"
24#include "llvm/DerivedTypes.h"
25#include "llvm/Function.h"
26#include "llvm/PassManager.h"
27#include "llvm/CodeGen/MachineCodeEmitter.h"
28#include "llvm/CodeGen/JITCodeEmitter.h"
29#include "llvm/CodeGen/ObjectCodeEmitter.h"
30#include "llvm/CodeGen/MachineConstantPool.h"
31#include "llvm/CodeGen/MachineFunctionPass.h"
32#include "llvm/CodeGen/MachineInstr.h"
33#include "llvm/CodeGen/MachineJumpTableInfo.h"
34#include "llvm/CodeGen/Passes.h"
35#include "llvm/ADT/Statistic.h"
36#include "llvm/Support/Compiler.h"
37#include "llvm/Support/Debug.h"
38#ifndef NDEBUG
39#include <iomanip>
40#endif
41using namespace llvm;
42
43STATISTIC(NumEmitted, "Number of machine instructions emitted");
44
45namespace {
46
47  class ARMCodeEmitter {
48  public:
49    /// getBinaryCodeForInstr - This function, generated by the
50    /// CodeEmitterGenerator using TableGen, produces the binary encoding for
51    /// machine instructions.
52    unsigned getBinaryCodeForInstr(const MachineInstr &MI);
53  };
54
55  template<class CodeEmitter>
56  class VISIBILITY_HIDDEN Emitter : public MachineFunctionPass,
57                                    public ARMCodeEmitter {
58    ARMJITInfo                *JTI;
59    const ARMInstrInfo        *II;
60    const TargetData          *TD;
61    TargetMachine             &TM;
62    CodeEmitter               &MCE;
63    const std::vector<MachineConstantPoolEntry> *MCPEs;
64    const std::vector<MachineJumpTableEntry> *MJTEs;
65    bool IsPIC;
66
67  public:
68    static char ID;
69    explicit Emitter(TargetMachine &tm, CodeEmitter &mce)
70      : MachineFunctionPass(&ID), JTI(0), II(0), TD(0), TM(tm),
71      MCE(mce), MCPEs(0), MJTEs(0),
72      IsPIC(TM.getRelocationModel() == Reloc::PIC_) {}
73    Emitter(TargetMachine &tm, CodeEmitter &mce,
74            const ARMInstrInfo &ii, const TargetData &td)
75      : MachineFunctionPass(&ID), JTI(0), II(&ii), TD(&td), TM(tm),
76      MCE(mce), MCPEs(0), MJTEs(0),
77      IsPIC(TM.getRelocationModel() == Reloc::PIC_) {}
78
79    bool runOnMachineFunction(MachineFunction &MF);
80
81    virtual const char *getPassName() const {
82      return "ARM Machine Code Emitter";
83    }
84
85    void emitInstruction(const MachineInstr &MI);
86
87  private:
88
89    void emitWordLE(unsigned Binary);
90
91    void emitDWordLE(uint64_t Binary);
92
93    void emitConstPoolInstruction(const MachineInstr &MI);
94
95    void emitMOVi2piecesInstruction(const MachineInstr &MI);
96
97    void emitLEApcrelJTInstruction(const MachineInstr &MI);
98
99    void emitPseudoMoveInstruction(const MachineInstr &MI);
100
101    void addPCLabel(unsigned LabelID);
102
103    void emitPseudoInstruction(const MachineInstr &MI);
104
105    unsigned getMachineSoRegOpValue(const MachineInstr &MI,
106                                    const TargetInstrDesc &TID,
107                                    const MachineOperand &MO,
108                                    unsigned OpIdx);
109
110    unsigned getMachineSoImmOpValue(unsigned SoImm);
111
112    unsigned getAddrModeSBit(const MachineInstr &MI,
113                             const TargetInstrDesc &TID) const;
114
115    void emitDataProcessingInstruction(const MachineInstr &MI,
116                                       unsigned ImplicitRd = 0,
117                                       unsigned ImplicitRn = 0);
118
119    void emitLoadStoreInstruction(const MachineInstr &MI,
120                                  unsigned ImplicitRd = 0,
121                                  unsigned ImplicitRn = 0);
122
123    void emitMiscLoadStoreInstruction(const MachineInstr &MI,
124                                      unsigned ImplicitRn = 0);
125
126    void emitLoadStoreMultipleInstruction(const MachineInstr &MI);
127
128    void emitMulFrmInstruction(const MachineInstr &MI);
129
130    void emitExtendInstruction(const MachineInstr &MI);
131
132    void emitMiscArithInstruction(const MachineInstr &MI);
133
134    void emitBranchInstruction(const MachineInstr &MI);
135
136    void emitInlineJumpTable(unsigned JTIndex);
137
138    void emitMiscBranchInstruction(const MachineInstr &MI);
139
140    void emitVFPArithInstruction(const MachineInstr &MI);
141
142    void emitVFPConversionInstruction(const MachineInstr &MI);
143
144    void emitVFPLoadStoreInstruction(const MachineInstr &MI);
145
146    void emitVFPLoadStoreMultipleInstruction(const MachineInstr &MI);
147
148    void emitMiscInstruction(const MachineInstr &MI);
149
150    /// getMachineOpValue - Return binary encoding of operand. If the machine
151    /// operand requires relocation, record the relocation and return zero.
152    unsigned getMachineOpValue(const MachineInstr &MI,const MachineOperand &MO);
153    unsigned getMachineOpValue(const MachineInstr &MI, unsigned OpIdx) {
154      return getMachineOpValue(MI, MI.getOperand(OpIdx));
155    }
156
157    /// getShiftOp - Return the shift opcode (bit[6:5]) of the immediate value.
158    ///
159    unsigned getShiftOp(unsigned Imm) const ;
160
161    /// Routines that handle operands which add machine relocations which are
162    /// fixed up by the relocation stage.
163    void emitGlobalAddress(GlobalValue *GV, unsigned Reloc,
164                           bool NeedStub, intptr_t ACPV = 0);
165    void emitExternalSymbolAddress(const char *ES, unsigned Reloc);
166    void emitConstPoolAddress(unsigned CPI, unsigned Reloc);
167    void emitJumpTableAddress(unsigned JTIndex, unsigned Reloc);
168    void emitMachineBasicBlock(MachineBasicBlock *BB, unsigned Reloc,
169                               intptr_t JTBase = 0);
170  };
171  template <class CodeEmitter>
172  char Emitter<CodeEmitter>::ID = 0;
173}
174
175/// createARMCodeEmitterPass - Return a pass that emits the collected ARM code
176/// to the specified MCE object.
177
178FunctionPass *llvm::createARMCodeEmitterPass(ARMBaseTargetMachine &TM,
179                                             MachineCodeEmitter &MCE) {
180  return new Emitter<MachineCodeEmitter>(TM, MCE);
181}
182FunctionPass *llvm::createARMJITCodeEmitterPass(ARMBaseTargetMachine &TM,
183                                                JITCodeEmitter &JCE) {
184  return new Emitter<JITCodeEmitter>(TM, JCE);
185}
186FunctionPass *llvm::createARMObjectCodeEmitterPass(ARMBaseTargetMachine &TM,
187                                                   ObjectCodeEmitter &OCE) {
188  return new Emitter<ObjectCodeEmitter>(TM, OCE);
189}
190
191template<class CodeEmitter>
192bool Emitter<CodeEmitter>::runOnMachineFunction(MachineFunction &MF) {
193  assert((MF.getTarget().getRelocationModel() != Reloc::Default ||
194          MF.getTarget().getRelocationModel() != Reloc::Static) &&
195         "JIT relocation model must be set to static or default!");
196  II = ((ARMTargetMachine&)MF.getTarget()).getInstrInfo();
197  TD = ((ARMTargetMachine&)MF.getTarget()).getTargetData();
198  JTI = ((ARMTargetMachine&)MF.getTarget()).getJITInfo();
199  MCPEs = &MF.getConstantPool()->getConstants();
200  MJTEs = &MF.getJumpTableInfo()->getJumpTables();
201  IsPIC = TM.getRelocationModel() == Reloc::PIC_;
202  JTI->Initialize(MF, IsPIC);
203
204  do {
205    DOUT << "JITTing function '" << MF.getFunction()->getName() << "'\n";
206    MCE.startFunction(MF);
207    for (MachineFunction::iterator MBB = MF.begin(), E = MF.end();
208         MBB != E; ++MBB) {
209      MCE.StartMachineBasicBlock(MBB);
210      for (MachineBasicBlock::const_iterator I = MBB->begin(), E = MBB->end();
211           I != E; ++I)
212        emitInstruction(*I);
213    }
214  } while (MCE.finishFunction(MF));
215
216  return false;
217}
218
219/// getShiftOp - Return the shift opcode (bit[6:5]) of the immediate value.
220///
221template<class CodeEmitter>
222unsigned Emitter<CodeEmitter>::getShiftOp(unsigned Imm) const {
223  switch (ARM_AM::getAM2ShiftOpc(Imm)) {
224  default: assert(0 && "Unknown shift opc!");
225  case ARM_AM::asr: return 2;
226  case ARM_AM::lsl: return 0;
227  case ARM_AM::lsr: return 1;
228  case ARM_AM::ror:
229  case ARM_AM::rrx: return 3;
230  }
231  return 0;
232}
233
234/// getMachineOpValue - Return binary encoding of operand. If the machine
235/// operand requires relocation, record the relocation and return zero.
236template<class CodeEmitter>
237unsigned Emitter<CodeEmitter>::getMachineOpValue(const MachineInstr &MI,
238                                                 const MachineOperand &MO) {
239  if (MO.isReg())
240    return ARMRegisterInfo::getRegisterNumbering(MO.getReg());
241  else if (MO.isImm())
242    return static_cast<unsigned>(MO.getImm());
243  else if (MO.isGlobal())
244    emitGlobalAddress(MO.getGlobal(), ARM::reloc_arm_branch, true);
245  else if (MO.isSymbol())
246    emitExternalSymbolAddress(MO.getSymbolName(), ARM::reloc_arm_branch);
247  else if (MO.isCPI()) {
248    const TargetInstrDesc &TID = MI.getDesc();
249    // For VFP load, the immediate offset is multiplied by 4.
250    unsigned Reloc =  ((TID.TSFlags & ARMII::FormMask) == ARMII::VFPLdStFrm)
251      ? ARM::reloc_arm_vfp_cp_entry : ARM::reloc_arm_cp_entry;
252    emitConstPoolAddress(MO.getIndex(), Reloc);
253  } else if (MO.isJTI())
254    emitJumpTableAddress(MO.getIndex(), ARM::reloc_arm_relative);
255  else if (MO.isMBB())
256    emitMachineBasicBlock(MO.getMBB(), ARM::reloc_arm_branch);
257  else {
258    cerr << "ERROR: Unknown type of MachineOperand: " << MO << "\n";
259    abort();
260  }
261  return 0;
262}
263
264/// emitGlobalAddress - Emit the specified address to the code stream.
265///
266template<class CodeEmitter>
267void Emitter<CodeEmitter>::emitGlobalAddress(GlobalValue *GV, unsigned Reloc,
268                                             bool NeedStub, intptr_t ACPV) {
269  MCE.addRelocation(MachineRelocation::getGV(MCE.getCurrentPCOffset(), Reloc,
270                                             GV, ACPV, NeedStub));
271}
272
273/// emitExternalSymbolAddress - Arrange for the address of an external symbol to
274/// be emitted to the current location in the function, and allow it to be PC
275/// relative.
276template<class CodeEmitter>
277void Emitter<CodeEmitter>::emitExternalSymbolAddress(const char *ES,
278                                                     unsigned Reloc) {
279  MCE.addRelocation(MachineRelocation::getExtSym(MCE.getCurrentPCOffset(),
280                                                 Reloc, ES));
281}
282
283/// emitConstPoolAddress - Arrange for the address of an constant pool
284/// to be emitted to the current location in the function, and allow it to be PC
285/// relative.
286template<class CodeEmitter>
287void Emitter<CodeEmitter>::emitConstPoolAddress(unsigned CPI,
288                                                unsigned Reloc) {
289  // Tell JIT emitter we'll resolve the address.
290  MCE.addRelocation(MachineRelocation::getConstPool(MCE.getCurrentPCOffset(),
291                                                    Reloc, CPI, 0, true));
292}
293
294/// emitJumpTableAddress - Arrange for the address of a jump table to
295/// be emitted to the current location in the function, and allow it to be PC
296/// relative.
297template<class CodeEmitter>
298void Emitter<CodeEmitter>::emitJumpTableAddress(unsigned JTIndex,
299                                                unsigned Reloc) {
300  MCE.addRelocation(MachineRelocation::getJumpTable(MCE.getCurrentPCOffset(),
301                                                    Reloc, JTIndex, 0, true));
302}
303
304/// emitMachineBasicBlock - Emit the specified address basic block.
305template<class CodeEmitter>
306void Emitter<CodeEmitter>::emitMachineBasicBlock(MachineBasicBlock *BB,
307                                              unsigned Reloc, intptr_t JTBase) {
308  MCE.addRelocation(MachineRelocation::getBB(MCE.getCurrentPCOffset(),
309                                             Reloc, BB, JTBase));
310}
311
312template<class CodeEmitter>
313void Emitter<CodeEmitter>::emitWordLE(unsigned Binary) {
314#ifndef NDEBUG
315  DOUT << "  0x" << std::hex << std::setw(8) << std::setfill('0')
316       << Binary << std::dec << "\n";
317#endif
318  MCE.emitWordLE(Binary);
319}
320
321template<class CodeEmitter>
322void Emitter<CodeEmitter>::emitDWordLE(uint64_t Binary) {
323#ifndef NDEBUG
324  DOUT << "  0x" << std::hex << std::setw(8) << std::setfill('0')
325       << (unsigned)Binary << std::dec << "\n";
326  DOUT << "  0x" << std::hex << std::setw(8) << std::setfill('0')
327       << (unsigned)(Binary >> 32) << std::dec << "\n";
328#endif
329  MCE.emitDWordLE(Binary);
330}
331
332template<class CodeEmitter>
333void Emitter<CodeEmitter>::emitInstruction(const MachineInstr &MI) {
334  DOUT << "JIT: " << (void*)MCE.getCurrentPCValue() << ":\t" << MI;
335
336  NumEmitted++;  // Keep track of the # of mi's emitted
337  switch (MI.getDesc().TSFlags & ARMII::FormMask) {
338  default: {
339    assert(0 && "Unhandled instruction encoding format!");
340    break;
341  }
342  case ARMII::Pseudo:
343    emitPseudoInstruction(MI);
344    break;
345  case ARMII::DPFrm:
346  case ARMII::DPSoRegFrm:
347    emitDataProcessingInstruction(MI);
348    break;
349  case ARMII::LdFrm:
350  case ARMII::StFrm:
351    emitLoadStoreInstruction(MI);
352    break;
353  case ARMII::LdMiscFrm:
354  case ARMII::StMiscFrm:
355    emitMiscLoadStoreInstruction(MI);
356    break;
357  case ARMII::LdStMulFrm:
358    emitLoadStoreMultipleInstruction(MI);
359    break;
360  case ARMII::MulFrm:
361    emitMulFrmInstruction(MI);
362    break;
363  case ARMII::ExtFrm:
364    emitExtendInstruction(MI);
365    break;
366  case ARMII::ArithMiscFrm:
367    emitMiscArithInstruction(MI);
368    break;
369  case ARMII::BrFrm:
370    emitBranchInstruction(MI);
371    break;
372  case ARMII::BrMiscFrm:
373    emitMiscBranchInstruction(MI);
374    break;
375  // VFP instructions.
376  case ARMII::VFPUnaryFrm:
377  case ARMII::VFPBinaryFrm:
378    emitVFPArithInstruction(MI);
379    break;
380  case ARMII::VFPConv1Frm:
381  case ARMII::VFPConv2Frm:
382  case ARMII::VFPConv3Frm:
383  case ARMII::VFPConv4Frm:
384  case ARMII::VFPConv5Frm:
385    emitVFPConversionInstruction(MI);
386    break;
387  case ARMII::VFPLdStFrm:
388    emitVFPLoadStoreInstruction(MI);
389    break;
390  case ARMII::VFPLdStMulFrm:
391    emitVFPLoadStoreMultipleInstruction(MI);
392    break;
393  case ARMII::VFPMiscFrm:
394    emitMiscInstruction(MI);
395    break;
396  }
397}
398
399template<class CodeEmitter>
400void Emitter<CodeEmitter>::emitConstPoolInstruction(const MachineInstr &MI) {
401  unsigned CPI = MI.getOperand(0).getImm();       // CP instruction index.
402  unsigned CPIndex = MI.getOperand(1).getIndex(); // Actual cp entry index.
403  const MachineConstantPoolEntry &MCPE = (*MCPEs)[CPIndex];
404
405  // Remember the CONSTPOOL_ENTRY address for later relocation.
406  JTI->addConstantPoolEntryAddr(CPI, MCE.getCurrentPCValue());
407
408  // Emit constpool island entry. In most cases, the actual values will be
409  // resolved and relocated after code emission.
410  if (MCPE.isMachineConstantPoolEntry()) {
411    ARMConstantPoolValue *ACPV =
412      static_cast<ARMConstantPoolValue*>(MCPE.Val.MachineCPVal);
413
414    DOUT << "  ** ARM constant pool #" << CPI << " @ "
415         << (void*)MCE.getCurrentPCValue() << " " << *ACPV << '\n';
416
417    GlobalValue *GV = ACPV->getGV();
418    if (GV) {
419      assert(!ACPV->isStub() && "Don't know how to deal this yet!");
420      if (ACPV->isNonLazyPointer())
421        MCE.addRelocation(MachineRelocation::getIndirectSymbol(
422                  MCE.getCurrentPCOffset(), ARM::reloc_arm_machine_cp_entry, GV,
423                  (intptr_t)ACPV, false));
424      else
425        emitGlobalAddress(GV, ARM::reloc_arm_machine_cp_entry,
426                          ACPV->isStub() || isa<Function>(GV), (intptr_t)ACPV);
427     } else  {
428      assert(!ACPV->isNonLazyPointer() && "Don't know how to deal this yet!");
429      emitExternalSymbolAddress(ACPV->getSymbol(), ARM::reloc_arm_absolute);
430    }
431    emitWordLE(0);
432  } else {
433    Constant *CV = MCPE.Val.ConstVal;
434
435#ifndef NDEBUG
436    DOUT << "  ** Constant pool #" << CPI << " @ "
437         << (void*)MCE.getCurrentPCValue() << " ";
438    if (const Function *F = dyn_cast<Function>(CV))
439      DOUT << F->getName();
440    else
441      DOUT << *CV;
442    DOUT << '\n';
443#endif
444
445    if (GlobalValue *GV = dyn_cast<GlobalValue>(CV)) {
446      emitGlobalAddress(GV, ARM::reloc_arm_absolute, isa<Function>(GV));
447      emitWordLE(0);
448    } else if (const ConstantInt *CI = dyn_cast<ConstantInt>(CV)) {
449      uint32_t Val = *(uint32_t*)CI->getValue().getRawData();
450      emitWordLE(Val);
451    } else if (const ConstantFP *CFP = dyn_cast<ConstantFP>(CV)) {
452      if (CFP->getType() == Type::FloatTy)
453        emitWordLE(CFP->getValueAPF().bitcastToAPInt().getZExtValue());
454      else if (CFP->getType() == Type::DoubleTy)
455        emitDWordLE(CFP->getValueAPF().bitcastToAPInt().getZExtValue());
456      else {
457        assert(0 && "Unable to handle this constantpool entry!");
458        abort();
459      }
460    } else {
461      assert(0 && "Unable to handle this constantpool entry!");
462      abort();
463    }
464  }
465}
466
467template<class CodeEmitter>
468void Emitter<CodeEmitter>::emitMOVi2piecesInstruction(const MachineInstr &MI) {
469  const MachineOperand &MO0 = MI.getOperand(0);
470  const MachineOperand &MO1 = MI.getOperand(1);
471  assert(MO1.isImm() && "Not a valid so_imm value!");
472  unsigned V1 = ARM_AM::getSOImmTwoPartFirst(MO1.getImm());
473  unsigned V2 = ARM_AM::getSOImmTwoPartSecond(MO1.getImm());
474
475  // Emit the 'mov' instruction.
476  unsigned Binary = 0xd << 21;  // mov: Insts{24-21} = 0b1101
477
478  // Set the conditional execution predicate.
479  Binary |= II->getPredicate(&MI) << ARMII::CondShift;
480
481  // Encode Rd.
482  Binary |= getMachineOpValue(MI, MO0) << ARMII::RegRdShift;
483
484  // Encode so_imm.
485  // Set bit I(25) to identify this is the immediate form of <shifter_op>
486  Binary |= 1 << ARMII::I_BitShift;
487  Binary |= getMachineSoImmOpValue(ARM_AM::getSOImmVal(V1));
488  emitWordLE(Binary);
489
490  // Now the 'orr' instruction.
491  Binary = 0xc << 21;  // orr: Insts{24-21} = 0b1100
492
493  // Set the conditional execution predicate.
494  Binary |= II->getPredicate(&MI) << ARMII::CondShift;
495
496  // Encode Rd.
497  Binary |= getMachineOpValue(MI, MO0) << ARMII::RegRdShift;
498
499  // Encode Rn.
500  Binary |= getMachineOpValue(MI, MO0) << ARMII::RegRnShift;
501
502  // Encode so_imm.
503  // Set bit I(25) to identify this is the immediate form of <shifter_op>
504  Binary |= 1 << ARMII::I_BitShift;
505  Binary |= getMachineSoImmOpValue(ARM_AM::getSOImmVal(V2));
506  emitWordLE(Binary);
507}
508
509template<class CodeEmitter>
510void Emitter<CodeEmitter>::emitLEApcrelJTInstruction(const MachineInstr &MI) {
511  // It's basically add r, pc, (LJTI - $+8)
512
513  const TargetInstrDesc &TID = MI.getDesc();
514
515  // Emit the 'add' instruction.
516  unsigned Binary = 0x4 << 21;  // add: Insts{24-31} = 0b0100
517
518  // Set the conditional execution predicate
519  Binary |= II->getPredicate(&MI) << ARMII::CondShift;
520
521  // Encode S bit if MI modifies CPSR.
522  Binary |= getAddrModeSBit(MI, TID);
523
524  // Encode Rd.
525  Binary |= getMachineOpValue(MI, 0) << ARMII::RegRdShift;
526
527  // Encode Rn which is PC.
528  Binary |= ARMRegisterInfo::getRegisterNumbering(ARM::PC) << ARMII::RegRnShift;
529
530  // Encode the displacement.
531  Binary |= 1 << ARMII::I_BitShift;
532  emitJumpTableAddress(MI.getOperand(1).getIndex(), ARM::reloc_arm_jt_base);
533
534  emitWordLE(Binary);
535}
536
537template<class CodeEmitter>
538void Emitter<CodeEmitter>::emitPseudoMoveInstruction(const MachineInstr &MI) {
539  unsigned Opcode = MI.getDesc().Opcode;
540
541  // Part of binary is determined by TableGn.
542  unsigned Binary = getBinaryCodeForInstr(MI);
543
544  // Set the conditional execution predicate
545  Binary |= II->getPredicate(&MI) << ARMII::CondShift;
546
547  // Encode S bit if MI modifies CPSR.
548  if (Opcode == ARM::MOVsrl_flag || Opcode == ARM::MOVsra_flag)
549    Binary |= 1 << ARMII::S_BitShift;
550
551  // Encode register def if there is one.
552  Binary |= getMachineOpValue(MI, 0) << ARMII::RegRdShift;
553
554  // Encode the shift operation.
555  switch (Opcode) {
556  default: break;
557  case ARM::MOVrx:
558    // rrx
559    Binary |= 0x6 << 4;
560    break;
561  case ARM::MOVsrl_flag:
562    // lsr #1
563    Binary |= (0x2 << 4) | (1 << 7);
564    break;
565  case ARM::MOVsra_flag:
566    // asr #1
567    Binary |= (0x4 << 4) | (1 << 7);
568    break;
569  }
570
571  // Encode register Rm.
572  Binary |= getMachineOpValue(MI, 1);
573
574  emitWordLE(Binary);
575}
576
577template<class CodeEmitter>
578void Emitter<CodeEmitter>::addPCLabel(unsigned LabelID) {
579  DOUT << "  ** LPC" << LabelID << " @ "
580       << (void*)MCE.getCurrentPCValue() << '\n';
581  JTI->addPCLabelAddr(LabelID, MCE.getCurrentPCValue());
582}
583
584template<class CodeEmitter>
585void Emitter<CodeEmitter>::emitPseudoInstruction(const MachineInstr &MI) {
586  unsigned Opcode = MI.getDesc().Opcode;
587  switch (Opcode) {
588  default:
589    abort(); // FIXME:
590  case TargetInstrInfo::INLINEASM: {
591    // We allow inline assembler nodes with empty bodies - they can
592    // implicitly define registers, which is ok for JIT.
593    if (MI.getOperand(0).getSymbolName()[0]) {
594      assert(0 && "JIT does not support inline asm!\n");
595      abort();
596    }
597    break;
598  }
599  case TargetInstrInfo::DBG_LABEL:
600  case TargetInstrInfo::EH_LABEL:
601    MCE.emitLabel(MI.getOperand(0).getImm());
602    break;
603  case TargetInstrInfo::IMPLICIT_DEF:
604  case TargetInstrInfo::DECLARE:
605  case ARM::DWARF_LOC:
606    // Do nothing.
607    break;
608  case ARM::CONSTPOOL_ENTRY:
609    emitConstPoolInstruction(MI);
610    break;
611  case ARM::PICADD: {
612    // Remember of the address of the PC label for relocation later.
613    addPCLabel(MI.getOperand(2).getImm());
614    // PICADD is just an add instruction that implicitly read pc.
615    emitDataProcessingInstruction(MI, 0, ARM::PC);
616    break;
617  }
618  case ARM::PICLDR:
619  case ARM::PICLDRB:
620  case ARM::PICSTR:
621  case ARM::PICSTRB: {
622    // Remember of the address of the PC label for relocation later.
623    addPCLabel(MI.getOperand(2).getImm());
624    // These are just load / store instructions that implicitly read pc.
625    emitLoadStoreInstruction(MI, 0, ARM::PC);
626    break;
627  }
628  case ARM::PICLDRH:
629  case ARM::PICLDRSH:
630  case ARM::PICLDRSB:
631  case ARM::PICSTRH: {
632    // Remember of the address of the PC label for relocation later.
633    addPCLabel(MI.getOperand(2).getImm());
634    // These are just load / store instructions that implicitly read pc.
635    emitMiscLoadStoreInstruction(MI, ARM::PC);
636    break;
637  }
638  case ARM::MOVi2pieces:
639    // Two instructions to materialize a constant.
640    emitMOVi2piecesInstruction(MI);
641    break;
642  case ARM::LEApcrelJT:
643    // Materialize jumptable address.
644    emitLEApcrelJTInstruction(MI);
645    break;
646  case ARM::MOVrx:
647  case ARM::MOVsrl_flag:
648  case ARM::MOVsra_flag:
649    emitPseudoMoveInstruction(MI);
650    break;
651  }
652}
653
654template<class CodeEmitter>
655unsigned Emitter<CodeEmitter>::getMachineSoRegOpValue(
656                                                const MachineInstr &MI,
657                                                const TargetInstrDesc &TID,
658                                                const MachineOperand &MO,
659                                                unsigned OpIdx) {
660  unsigned Binary = getMachineOpValue(MI, MO);
661
662  const MachineOperand &MO1 = MI.getOperand(OpIdx + 1);
663  const MachineOperand &MO2 = MI.getOperand(OpIdx + 2);
664  ARM_AM::ShiftOpc SOpc = ARM_AM::getSORegShOp(MO2.getImm());
665
666  // Encode the shift opcode.
667  unsigned SBits = 0;
668  unsigned Rs = MO1.getReg();
669  if (Rs) {
670    // Set shift operand (bit[7:4]).
671    // LSL - 0001
672    // LSR - 0011
673    // ASR - 0101
674    // ROR - 0111
675    // RRX - 0110 and bit[11:8] clear.
676    switch (SOpc) {
677    default: assert(0 && "Unknown shift opc!");
678    case ARM_AM::lsl: SBits = 0x1; break;
679    case ARM_AM::lsr: SBits = 0x3; break;
680    case ARM_AM::asr: SBits = 0x5; break;
681    case ARM_AM::ror: SBits = 0x7; break;
682    case ARM_AM::rrx: SBits = 0x6; break;
683    }
684  } else {
685    // Set shift operand (bit[6:4]).
686    // LSL - 000
687    // LSR - 010
688    // ASR - 100
689    // ROR - 110
690    switch (SOpc) {
691    default: assert(0 && "Unknown shift opc!");
692    case ARM_AM::lsl: SBits = 0x0; break;
693    case ARM_AM::lsr: SBits = 0x2; break;
694    case ARM_AM::asr: SBits = 0x4; break;
695    case ARM_AM::ror: SBits = 0x6; break;
696    }
697  }
698  Binary |= SBits << 4;
699  if (SOpc == ARM_AM::rrx)
700    return Binary;
701
702  // Encode the shift operation Rs or shift_imm (except rrx).
703  if (Rs) {
704    // Encode Rs bit[11:8].
705    assert(ARM_AM::getSORegOffset(MO2.getImm()) == 0);
706    return Binary |
707      (ARMRegisterInfo::getRegisterNumbering(Rs) << ARMII::RegRsShift);
708  }
709
710  // Encode shift_imm bit[11:7].
711  return Binary | ARM_AM::getSORegOffset(MO2.getImm()) << 7;
712}
713
714template<class CodeEmitter>
715unsigned Emitter<CodeEmitter>::getMachineSoImmOpValue(unsigned SoImm) {
716  // Encode rotate_imm.
717  unsigned Binary = (ARM_AM::getSOImmValRot(SoImm) >> 1)
718    << ARMII::SoRotImmShift;
719
720  // Encode immed_8.
721  Binary |= ARM_AM::getSOImmValImm(SoImm);
722  return Binary;
723}
724
725template<class CodeEmitter>
726unsigned Emitter<CodeEmitter>::getAddrModeSBit(const MachineInstr &MI,
727                                             const TargetInstrDesc &TID) const {
728  for (unsigned i = MI.getNumOperands(), e = TID.getNumOperands(); i != e; --i){
729    const MachineOperand &MO = MI.getOperand(i-1);
730    if (MO.isReg() && MO.isDef() && MO.getReg() == ARM::CPSR)
731      return 1 << ARMII::S_BitShift;
732  }
733  return 0;
734}
735
736template<class CodeEmitter>
737void Emitter<CodeEmitter>::emitDataProcessingInstruction(
738                                                   const MachineInstr &MI,
739                                                   unsigned ImplicitRd,
740                                                   unsigned ImplicitRn) {
741  const TargetInstrDesc &TID = MI.getDesc();
742
743  if (TID.Opcode == ARM::BFC) {
744    cerr << "ERROR: ARMv6t2 JIT is not yet supported.\n";
745    abort();
746  }
747
748  // Part of binary is determined by TableGn.
749  unsigned Binary = getBinaryCodeForInstr(MI);
750
751  // Set the conditional execution predicate
752  Binary |= II->getPredicate(&MI) << ARMII::CondShift;
753
754  // Encode S bit if MI modifies CPSR.
755  Binary |= getAddrModeSBit(MI, TID);
756
757  // Encode register def if there is one.
758  unsigned NumDefs = TID.getNumDefs();
759  unsigned OpIdx = 0;
760  if (NumDefs)
761    Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRdShift;
762  else if (ImplicitRd)
763    // Special handling for implicit use (e.g. PC).
764    Binary |= (ARMRegisterInfo::getRegisterNumbering(ImplicitRd)
765               << ARMII::RegRdShift);
766
767  // If this is a two-address operand, skip it. e.g. MOVCCr operand 1.
768  if (TID.getOperandConstraint(OpIdx, TOI::TIED_TO) != -1)
769    ++OpIdx;
770
771  // Encode first non-shifter register operand if there is one.
772  bool isUnary = TID.TSFlags & ARMII::UnaryDP;
773  if (!isUnary) {
774    if (ImplicitRn)
775      // Special handling for implicit use (e.g. PC).
776      Binary |= (ARMRegisterInfo::getRegisterNumbering(ImplicitRn)
777                 << ARMII::RegRnShift);
778    else {
779      Binary |= getMachineOpValue(MI, OpIdx) << ARMII::RegRnShift;
780      ++OpIdx;
781    }
782  }
783
784  // Encode shifter operand.
785  const MachineOperand &MO = MI.getOperand(OpIdx);
786  if ((TID.TSFlags & ARMII::FormMask) == ARMII::DPSoRegFrm) {
787    // Encode SoReg.
788    emitWordLE(Binary | getMachineSoRegOpValue(MI, TID, MO, OpIdx));
789    return;
790  }
791
792  if (MO.isReg()) {
793    // Encode register Rm.
794    emitWordLE(Binary | ARMRegisterInfo::getRegisterNumbering(MO.getReg()));
795    return;
796  }
797
798  // Encode so_imm.
799  Binary |= 1 << ARMII::I_BitShift;
800  Binary |= getMachineSoImmOpValue(MO.getImm());
801
802  emitWordLE(Binary);
803}
804
805template<class CodeEmitter>
806void Emitter<CodeEmitter>::emitLoadStoreInstruction(
807                                              const MachineInstr &MI,
808                                              unsigned ImplicitRd,
809                                              unsigned ImplicitRn) {
810  const TargetInstrDesc &TID = MI.getDesc();
811  unsigned Form = TID.TSFlags & ARMII::FormMask;
812  bool IsPrePost = (TID.TSFlags & ARMII::IndexModeMask) != 0;
813
814  // Part of binary is determined by TableGn.
815  unsigned Binary = getBinaryCodeForInstr(MI);
816
817  // Set the conditional execution predicate
818  Binary |= II->getPredicate(&MI) << ARMII::CondShift;
819
820  unsigned OpIdx = 0;
821
822  // Operand 0 of a pre- and post-indexed store is the address base
823  // writeback. Skip it.
824  bool Skipped = false;
825  if (IsPrePost && Form == ARMII::StFrm) {
826    ++OpIdx;
827    Skipped = true;
828  }
829
830  // Set first operand
831  if (ImplicitRd)
832    // Special handling for implicit use (e.g. PC).
833    Binary |= (ARMRegisterInfo::getRegisterNumbering(ImplicitRd)
834               << ARMII::RegRdShift);
835  else
836    Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRdShift;
837
838  // Set second operand
839  if (ImplicitRn)
840    // Special handling for implicit use (e.g. PC).
841    Binary |= (ARMRegisterInfo::getRegisterNumbering(ImplicitRn)
842               << ARMII::RegRnShift);
843  else
844    Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRnShift;
845
846  // If this is a two-address operand, skip it. e.g. LDR_PRE.
847  if (!Skipped && TID.getOperandConstraint(OpIdx, TOI::TIED_TO) != -1)
848    ++OpIdx;
849
850  const MachineOperand &MO2 = MI.getOperand(OpIdx);
851  unsigned AM2Opc = (ImplicitRn == ARM::PC)
852    ? 0 : MI.getOperand(OpIdx+1).getImm();
853
854  // Set bit U(23) according to sign of immed value (positive or negative).
855  Binary |= ((ARM_AM::getAM2Op(AM2Opc) == ARM_AM::add ? 1 : 0) <<
856             ARMII::U_BitShift);
857  if (!MO2.getReg()) { // is immediate
858    if (ARM_AM::getAM2Offset(AM2Opc))
859      // Set the value of offset_12 field
860      Binary |= ARM_AM::getAM2Offset(AM2Opc);
861    emitWordLE(Binary);
862    return;
863  }
864
865  // Set bit I(25), because this is not in immediate enconding.
866  Binary |= 1 << ARMII::I_BitShift;
867  assert(TargetRegisterInfo::isPhysicalRegister(MO2.getReg()));
868  // Set bit[3:0] to the corresponding Rm register
869  Binary |= ARMRegisterInfo::getRegisterNumbering(MO2.getReg());
870
871  // If this instr is in scaled register offset/index instruction, set
872  // shift_immed(bit[11:7]) and shift(bit[6:5]) fields.
873  if (unsigned ShImm = ARM_AM::getAM2Offset(AM2Opc)) {
874    Binary |= getShiftOp(AM2Opc) << ARMII::ShiftImmShift;  // shift
875    Binary |= ShImm              << ARMII::ShiftShift;     // shift_immed
876  }
877
878  emitWordLE(Binary);
879}
880
881template<class CodeEmitter>
882void Emitter<CodeEmitter>::emitMiscLoadStoreInstruction(const MachineInstr &MI,
883                                                        unsigned ImplicitRn) {
884  const TargetInstrDesc &TID = MI.getDesc();
885  unsigned Form = TID.TSFlags & ARMII::FormMask;
886  bool IsPrePost = (TID.TSFlags & ARMII::IndexModeMask) != 0;
887
888  // Part of binary is determined by TableGn.
889  unsigned Binary = getBinaryCodeForInstr(MI);
890
891  // Set the conditional execution predicate
892  Binary |= II->getPredicate(&MI) << ARMII::CondShift;
893
894  unsigned OpIdx = 0;
895
896  // Operand 0 of a pre- and post-indexed store is the address base
897  // writeback. Skip it.
898  bool Skipped = false;
899  if (IsPrePost && Form == ARMII::StMiscFrm) {
900    ++OpIdx;
901    Skipped = true;
902  }
903
904  // Set first operand
905  Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRdShift;
906
907  // Skip LDRD and STRD's second operand.
908  if (TID.Opcode == ARM::LDRD || TID.Opcode == ARM::STRD)
909    ++OpIdx;
910
911  // Set second operand
912  if (ImplicitRn)
913    // Special handling for implicit use (e.g. PC).
914    Binary |= (ARMRegisterInfo::getRegisterNumbering(ImplicitRn)
915               << ARMII::RegRnShift);
916  else
917    Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRnShift;
918
919  // If this is a two-address operand, skip it. e.g. LDRH_POST.
920  if (!Skipped && TID.getOperandConstraint(OpIdx, TOI::TIED_TO) != -1)
921    ++OpIdx;
922
923  const MachineOperand &MO2 = MI.getOperand(OpIdx);
924  unsigned AM3Opc = (ImplicitRn == ARM::PC)
925    ? 0 : MI.getOperand(OpIdx+1).getImm();
926
927  // Set bit U(23) according to sign of immed value (positive or negative)
928  Binary |= ((ARM_AM::getAM3Op(AM3Opc) == ARM_AM::add ? 1 : 0) <<
929             ARMII::U_BitShift);
930
931  // If this instr is in register offset/index encoding, set bit[3:0]
932  // to the corresponding Rm register.
933  if (MO2.getReg()) {
934    Binary |= ARMRegisterInfo::getRegisterNumbering(MO2.getReg());
935    emitWordLE(Binary);
936    return;
937  }
938
939  // This instr is in immediate offset/index encoding, set bit 22 to 1.
940  Binary |= 1 << ARMII::AM3_I_BitShift;
941  if (unsigned ImmOffs = ARM_AM::getAM3Offset(AM3Opc)) {
942    // Set operands
943    Binary |= (ImmOffs >> 4) << ARMII::ImmHiShift;  // immedH
944    Binary |= (ImmOffs & 0xF);                      // immedL
945  }
946
947  emitWordLE(Binary);
948}
949
950static unsigned getAddrModeUPBits(unsigned Mode) {
951  unsigned Binary = 0;
952
953  // Set addressing mode by modifying bits U(23) and P(24)
954  // IA - Increment after  - bit U = 1 and bit P = 0
955  // IB - Increment before - bit U = 1 and bit P = 1
956  // DA - Decrement after  - bit U = 0 and bit P = 0
957  // DB - Decrement before - bit U = 0 and bit P = 1
958  switch (Mode) {
959  default: assert(0 && "Unknown addressing sub-mode!");
960  case ARM_AM::da:                      break;
961  case ARM_AM::db: Binary |= 0x1 << ARMII::P_BitShift; break;
962  case ARM_AM::ia: Binary |= 0x1 << ARMII::U_BitShift; break;
963  case ARM_AM::ib: Binary |= 0x3 << ARMII::U_BitShift; break;
964  }
965
966  return Binary;
967}
968
969template<class CodeEmitter>
970void Emitter<CodeEmitter>::emitLoadStoreMultipleInstruction(
971                                                       const MachineInstr &MI) {
972  // Part of binary is determined by TableGn.
973  unsigned Binary = getBinaryCodeForInstr(MI);
974
975  // Set the conditional execution predicate
976  Binary |= II->getPredicate(&MI) << ARMII::CondShift;
977
978  // Set base address operand
979  Binary |= getMachineOpValue(MI, 0) << ARMII::RegRnShift;
980
981  // Set addressing mode by modifying bits U(23) and P(24)
982  const MachineOperand &MO = MI.getOperand(1);
983  Binary |= getAddrModeUPBits(ARM_AM::getAM4SubMode(MO.getImm()));
984
985  // Set bit W(21)
986  if (ARM_AM::getAM4WBFlag(MO.getImm()))
987    Binary |= 0x1 << ARMII::W_BitShift;
988
989  // Set registers
990  for (unsigned i = 4, e = MI.getNumOperands(); i != e; ++i) {
991    const MachineOperand &MO = MI.getOperand(i);
992    if (!MO.isReg() || MO.isImplicit())
993      break;
994    unsigned RegNum = ARMRegisterInfo::getRegisterNumbering(MO.getReg());
995    assert(TargetRegisterInfo::isPhysicalRegister(MO.getReg()) &&
996           RegNum < 16);
997    Binary |= 0x1 << RegNum;
998  }
999
1000  emitWordLE(Binary);
1001}
1002
1003template<class CodeEmitter>
1004void Emitter<CodeEmitter>::emitMulFrmInstruction(const MachineInstr &MI) {
1005  const TargetInstrDesc &TID = MI.getDesc();
1006
1007  // Part of binary is determined by TableGn.
1008  unsigned Binary = getBinaryCodeForInstr(MI);
1009
1010  // Set the conditional execution predicate
1011  Binary |= II->getPredicate(&MI) << ARMII::CondShift;
1012
1013  // Encode S bit if MI modifies CPSR.
1014  Binary |= getAddrModeSBit(MI, TID);
1015
1016  // 32x32->64bit operations have two destination registers. The number
1017  // of register definitions will tell us if that's what we're dealing with.
1018  unsigned OpIdx = 0;
1019  if (TID.getNumDefs() == 2)
1020    Binary |= getMachineOpValue (MI, OpIdx++) << ARMII::RegRdLoShift;
1021
1022  // Encode Rd
1023  Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRdHiShift;
1024
1025  // Encode Rm
1026  Binary |= getMachineOpValue(MI, OpIdx++);
1027
1028  // Encode Rs
1029  Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRsShift;
1030
1031  // Many multiple instructions (e.g. MLA) have three src operands. Encode
1032  // it as Rn (for multiply, that's in the same offset as RdLo.
1033  if (TID.getNumOperands() > OpIdx &&
1034      !TID.OpInfo[OpIdx].isPredicate() &&
1035      !TID.OpInfo[OpIdx].isOptionalDef())
1036    Binary |= getMachineOpValue(MI, OpIdx) << ARMII::RegRdLoShift;
1037
1038  emitWordLE(Binary);
1039}
1040
1041template<class CodeEmitter>
1042void Emitter<CodeEmitter>::emitExtendInstruction(const MachineInstr &MI) {
1043  const TargetInstrDesc &TID = MI.getDesc();
1044
1045  // Part of binary is determined by TableGn.
1046  unsigned Binary = getBinaryCodeForInstr(MI);
1047
1048  // Set the conditional execution predicate
1049  Binary |= II->getPredicate(&MI) << ARMII::CondShift;
1050
1051  unsigned OpIdx = 0;
1052
1053  // Encode Rd
1054  Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRdShift;
1055
1056  const MachineOperand &MO1 = MI.getOperand(OpIdx++);
1057  const MachineOperand &MO2 = MI.getOperand(OpIdx);
1058  if (MO2.isReg()) {
1059    // Two register operand form.
1060    // Encode Rn.
1061    Binary |= getMachineOpValue(MI, MO1) << ARMII::RegRnShift;
1062
1063    // Encode Rm.
1064    Binary |= getMachineOpValue(MI, MO2);
1065    ++OpIdx;
1066  } else {
1067    Binary |= getMachineOpValue(MI, MO1);
1068  }
1069
1070  // Encode rot imm (0, 8, 16, or 24) if it has a rotate immediate operand.
1071  if (MI.getOperand(OpIdx).isImm() &&
1072      !TID.OpInfo[OpIdx].isPredicate() &&
1073      !TID.OpInfo[OpIdx].isOptionalDef())
1074    Binary |= (getMachineOpValue(MI, OpIdx) / 8) << ARMII::ExtRotImmShift;
1075
1076  emitWordLE(Binary);
1077}
1078
1079template<class CodeEmitter>
1080void Emitter<CodeEmitter>::emitMiscArithInstruction(const MachineInstr &MI) {
1081  const TargetInstrDesc &TID = MI.getDesc();
1082
1083  // Part of binary is determined by TableGn.
1084  unsigned Binary = getBinaryCodeForInstr(MI);
1085
1086  // Set the conditional execution predicate
1087  Binary |= II->getPredicate(&MI) << ARMII::CondShift;
1088
1089  unsigned OpIdx = 0;
1090
1091  // Encode Rd
1092  Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRdShift;
1093
1094  const MachineOperand &MO = MI.getOperand(OpIdx++);
1095  if (OpIdx == TID.getNumOperands() ||
1096      TID.OpInfo[OpIdx].isPredicate() ||
1097      TID.OpInfo[OpIdx].isOptionalDef()) {
1098    // Encode Rm and it's done.
1099    Binary |= getMachineOpValue(MI, MO);
1100    emitWordLE(Binary);
1101    return;
1102  }
1103
1104  // Encode Rn.
1105  Binary |= getMachineOpValue(MI, MO) << ARMII::RegRnShift;
1106
1107  // Encode Rm.
1108  Binary |= getMachineOpValue(MI, OpIdx++);
1109
1110  // Encode shift_imm.
1111  unsigned ShiftAmt = MI.getOperand(OpIdx).getImm();
1112  assert(ShiftAmt < 32 && "shift_imm range is 0 to 31!");
1113  Binary |= ShiftAmt << ARMII::ShiftShift;
1114
1115  emitWordLE(Binary);
1116}
1117
1118template<class CodeEmitter>
1119void Emitter<CodeEmitter>::emitBranchInstruction(const MachineInstr &MI) {
1120  const TargetInstrDesc &TID = MI.getDesc();
1121
1122  if (TID.Opcode == ARM::TPsoft)
1123    abort(); // FIXME
1124
1125  // Part of binary is determined by TableGn.
1126  unsigned Binary = getBinaryCodeForInstr(MI);
1127
1128  // Set the conditional execution predicate
1129  Binary |= II->getPredicate(&MI) << ARMII::CondShift;
1130
1131  // Set signed_immed_24 field
1132  Binary |= getMachineOpValue(MI, 0);
1133
1134  emitWordLE(Binary);
1135}
1136
1137template<class CodeEmitter>
1138void Emitter<CodeEmitter>::emitInlineJumpTable(unsigned JTIndex) {
1139  // Remember the base address of the inline jump table.
1140  uintptr_t JTBase = MCE.getCurrentPCValue();
1141  JTI->addJumpTableBaseAddr(JTIndex, JTBase);
1142  DOUT << "  ** Jump Table #" << JTIndex << " @ " << (void*)JTBase << '\n';
1143
1144  // Now emit the jump table entries.
1145  const std::vector<MachineBasicBlock*> &MBBs = (*MJTEs)[JTIndex].MBBs;
1146  for (unsigned i = 0, e = MBBs.size(); i != e; ++i) {
1147    if (IsPIC)
1148      // DestBB address - JT base.
1149      emitMachineBasicBlock(MBBs[i], ARM::reloc_arm_pic_jt, JTBase);
1150    else
1151      // Absolute DestBB address.
1152      emitMachineBasicBlock(MBBs[i], ARM::reloc_arm_absolute);
1153    emitWordLE(0);
1154  }
1155}
1156
1157template<class CodeEmitter>
1158void Emitter<CodeEmitter>::emitMiscBranchInstruction(const MachineInstr &MI) {
1159  const TargetInstrDesc &TID = MI.getDesc();
1160
1161  // Handle jump tables.
1162  if (TID.Opcode == ARM::BR_JTr || TID.Opcode == ARM::BR_JTadd ||
1163      TID.Opcode == ARM::t2BR_JTr || TID.Opcode == ARM::t2BR_JTadd) {
1164    // First emit a ldr pc, [] instruction.
1165    emitDataProcessingInstruction(MI, ARM::PC);
1166
1167    // Then emit the inline jump table.
1168    unsigned JTIndex = (TID.Opcode == ARM::BR_JTr || TID.Opcode == ARM::t2BR_JTr)
1169      ? MI.getOperand(1).getIndex() : MI.getOperand(2).getIndex();
1170    emitInlineJumpTable(JTIndex);
1171    return;
1172  } else if (TID.Opcode == ARM::BR_JTm || TID.Opcode == ARM::t2BR_JTm) {
1173    // First emit a ldr pc, [] instruction.
1174    emitLoadStoreInstruction(MI, ARM::PC);
1175
1176    // Then emit the inline jump table.
1177    emitInlineJumpTable(MI.getOperand(3).getIndex());
1178    return;
1179  }
1180
1181  // Part of binary is determined by TableGn.
1182  unsigned Binary = getBinaryCodeForInstr(MI);
1183
1184  // Set the conditional execution predicate
1185  Binary |= II->getPredicate(&MI) << ARMII::CondShift;
1186
1187  if (TID.Opcode == ARM::BX_RET)
1188    // The return register is LR.
1189    Binary |= ARMRegisterInfo::getRegisterNumbering(ARM::LR);
1190  else
1191    // otherwise, set the return register
1192    Binary |= getMachineOpValue(MI, 0);
1193
1194  emitWordLE(Binary);
1195}
1196
1197static unsigned encodeVFPRd(const MachineInstr &MI, unsigned OpIdx) {
1198  unsigned RegD = MI.getOperand(OpIdx).getReg();
1199  unsigned Binary = 0;
1200  bool isSPVFP = false;
1201  RegD = ARMRegisterInfo::getRegisterNumbering(RegD, isSPVFP);
1202  if (!isSPVFP)
1203    Binary |=   RegD               << ARMII::RegRdShift;
1204  else {
1205    Binary |= ((RegD & 0x1E) >> 1) << ARMII::RegRdShift;
1206    Binary |=  (RegD & 0x01)       << ARMII::D_BitShift;
1207  }
1208  return Binary;
1209}
1210
1211static unsigned encodeVFPRn(const MachineInstr &MI, unsigned OpIdx) {
1212  unsigned RegN = MI.getOperand(OpIdx).getReg();
1213  unsigned Binary = 0;
1214  bool isSPVFP = false;
1215  RegN = ARMRegisterInfo::getRegisterNumbering(RegN, isSPVFP);
1216  if (!isSPVFP)
1217    Binary |=   RegN               << ARMII::RegRnShift;
1218  else {
1219    Binary |= ((RegN & 0x1E) >> 1) << ARMII::RegRnShift;
1220    Binary |=  (RegN & 0x01)       << ARMII::N_BitShift;
1221  }
1222  return Binary;
1223}
1224
1225static unsigned encodeVFPRm(const MachineInstr &MI, unsigned OpIdx) {
1226  unsigned RegM = MI.getOperand(OpIdx).getReg();
1227  unsigned Binary = 0;
1228  bool isSPVFP = false;
1229  RegM = ARMRegisterInfo::getRegisterNumbering(RegM, isSPVFP);
1230  if (!isSPVFP)
1231    Binary |=   RegM;
1232  else {
1233    Binary |= ((RegM & 0x1E) >> 1);
1234    Binary |=  (RegM & 0x01)       << ARMII::M_BitShift;
1235  }
1236  return Binary;
1237}
1238
1239template<class CodeEmitter>
1240void Emitter<CodeEmitter>::emitVFPArithInstruction(const MachineInstr &MI) {
1241  const TargetInstrDesc &TID = MI.getDesc();
1242
1243  // Part of binary is determined by TableGn.
1244  unsigned Binary = getBinaryCodeForInstr(MI);
1245
1246  // Set the conditional execution predicate
1247  Binary |= II->getPredicate(&MI) << ARMII::CondShift;
1248
1249  unsigned OpIdx = 0;
1250  assert((Binary & ARMII::D_BitShift) == 0 &&
1251         (Binary & ARMII::N_BitShift) == 0 &&
1252         (Binary & ARMII::M_BitShift) == 0 && "VFP encoding bug!");
1253
1254  // Encode Dd / Sd.
1255  Binary |= encodeVFPRd(MI, OpIdx++);
1256
1257  // If this is a two-address operand, skip it, e.g. FMACD.
1258  if (TID.getOperandConstraint(OpIdx, TOI::TIED_TO) != -1)
1259    ++OpIdx;
1260
1261  // Encode Dn / Sn.
1262  if ((TID.TSFlags & ARMII::FormMask) == ARMII::VFPBinaryFrm)
1263    Binary |= encodeVFPRn(MI, OpIdx++);
1264
1265  if (OpIdx == TID.getNumOperands() ||
1266      TID.OpInfo[OpIdx].isPredicate() ||
1267      TID.OpInfo[OpIdx].isOptionalDef()) {
1268    // FCMPEZD etc. has only one operand.
1269    emitWordLE(Binary);
1270    return;
1271  }
1272
1273  // Encode Dm / Sm.
1274  Binary |= encodeVFPRm(MI, OpIdx);
1275
1276  emitWordLE(Binary);
1277}
1278
1279template<class CodeEmitter>
1280void Emitter<CodeEmitter>::emitVFPConversionInstruction(
1281      const MachineInstr &MI) {
1282  const TargetInstrDesc &TID = MI.getDesc();
1283  unsigned Form = TID.TSFlags & ARMII::FormMask;
1284
1285  // Part of binary is determined by TableGn.
1286  unsigned Binary = getBinaryCodeForInstr(MI);
1287
1288  // Set the conditional execution predicate
1289  Binary |= II->getPredicate(&MI) << ARMII::CondShift;
1290
1291  switch (Form) {
1292  default: break;
1293  case ARMII::VFPConv1Frm:
1294  case ARMII::VFPConv2Frm:
1295  case ARMII::VFPConv3Frm:
1296    // Encode Dd / Sd.
1297    Binary |= encodeVFPRd(MI, 0);
1298    break;
1299  case ARMII::VFPConv4Frm:
1300    // Encode Dn / Sn.
1301    Binary |= encodeVFPRn(MI, 0);
1302    break;
1303  case ARMII::VFPConv5Frm:
1304    // Encode Dm / Sm.
1305    Binary |= encodeVFPRm(MI, 0);
1306    break;
1307  }
1308
1309  switch (Form) {
1310  default: break;
1311  case ARMII::VFPConv1Frm:
1312    // Encode Dm / Sm.
1313    Binary |= encodeVFPRm(MI, 1);
1314    break;
1315  case ARMII::VFPConv2Frm:
1316  case ARMII::VFPConv3Frm:
1317    // Encode Dn / Sn.
1318    Binary |= encodeVFPRn(MI, 1);
1319    break;
1320  case ARMII::VFPConv4Frm:
1321  case ARMII::VFPConv5Frm:
1322    // Encode Dd / Sd.
1323    Binary |= encodeVFPRd(MI, 1);
1324    break;
1325  }
1326
1327  if (Form == ARMII::VFPConv5Frm)
1328    // Encode Dn / Sn.
1329    Binary |= encodeVFPRn(MI, 2);
1330  else if (Form == ARMII::VFPConv3Frm)
1331    // Encode Dm / Sm.
1332    Binary |= encodeVFPRm(MI, 2);
1333
1334  emitWordLE(Binary);
1335}
1336
1337template<class CodeEmitter>
1338void Emitter<CodeEmitter>::emitVFPLoadStoreInstruction(const MachineInstr &MI) {
1339  // Part of binary is determined by TableGn.
1340  unsigned Binary = getBinaryCodeForInstr(MI);
1341
1342  // Set the conditional execution predicate
1343  Binary |= II->getPredicate(&MI) << ARMII::CondShift;
1344
1345  unsigned OpIdx = 0;
1346
1347  // Encode Dd / Sd.
1348  Binary |= encodeVFPRd(MI, OpIdx++);
1349
1350  // Encode address base.
1351  const MachineOperand &Base = MI.getOperand(OpIdx++);
1352  Binary |= getMachineOpValue(MI, Base) << ARMII::RegRnShift;
1353
1354  // If there is a non-zero immediate offset, encode it.
1355  if (Base.isReg()) {
1356    const MachineOperand &Offset = MI.getOperand(OpIdx);
1357    if (unsigned ImmOffs = ARM_AM::getAM5Offset(Offset.getImm())) {
1358      if (ARM_AM::getAM5Op(Offset.getImm()) == ARM_AM::add)
1359        Binary |= 1 << ARMII::U_BitShift;
1360      Binary |= ImmOffs;
1361      emitWordLE(Binary);
1362      return;
1363    }
1364  }
1365
1366  // If immediate offset is omitted, default to +0.
1367  Binary |= 1 << ARMII::U_BitShift;
1368
1369  emitWordLE(Binary);
1370}
1371
1372template<class CodeEmitter>
1373void Emitter<CodeEmitter>::emitVFPLoadStoreMultipleInstruction(
1374                                                       const MachineInstr &MI) {
1375  // Part of binary is determined by TableGn.
1376  unsigned Binary = getBinaryCodeForInstr(MI);
1377
1378  // Set the conditional execution predicate
1379  Binary |= II->getPredicate(&MI) << ARMII::CondShift;
1380
1381  // Set base address operand
1382  Binary |= getMachineOpValue(MI, 0) << ARMII::RegRnShift;
1383
1384  // Set addressing mode by modifying bits U(23) and P(24)
1385  const MachineOperand &MO = MI.getOperand(1);
1386  Binary |= getAddrModeUPBits(ARM_AM::getAM5SubMode(MO.getImm()));
1387
1388  // Set bit W(21)
1389  if (ARM_AM::getAM5WBFlag(MO.getImm()))
1390    Binary |= 0x1 << ARMII::W_BitShift;
1391
1392  // First register is encoded in Dd.
1393  Binary |= encodeVFPRd(MI, 4);
1394
1395  // Number of registers are encoded in offset field.
1396  unsigned NumRegs = 1;
1397  for (unsigned i = 5, e = MI.getNumOperands(); i != e; ++i) {
1398    const MachineOperand &MO = MI.getOperand(i);
1399    if (!MO.isReg() || MO.isImplicit())
1400      break;
1401    ++NumRegs;
1402  }
1403  Binary |= NumRegs * 2;
1404
1405  emitWordLE(Binary);
1406}
1407
1408template<class CodeEmitter>
1409void Emitter<CodeEmitter>::emitMiscInstruction(const MachineInstr &MI) {
1410  // Part of binary is determined by TableGn.
1411  unsigned Binary = getBinaryCodeForInstr(MI);
1412
1413  // Set the conditional execution predicate
1414  Binary |= II->getPredicate(&MI) << ARMII::CondShift;
1415
1416  emitWordLE(Binary);
1417}
1418
1419#include "ARMGenCodeEmitter.inc"
1420
1421