ARMCodeEmitter.cpp revision c3f0e98f40f1382870c679b6aef1c5d01540637f 
1//===-- ARM/ARMCodeEmitter.cpp - Convert ARM code to machine code ---------===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file contains the pass that transforms the ARM machine instructions into
11// relocatable machine code.
12//
13//===----------------------------------------------------------------------===//
14
15#define DEBUG_TYPE "jit"
16#include "ARM.h"
17#include "ARMConstantPoolValue.h"
18#include "ARMBaseInstrInfo.h"
19#include "ARMRelocations.h"
20#include "ARMSubtarget.h"
21#include "ARMTargetMachine.h"
22#include "MCTargetDesc/ARMAddressingModes.h"
23#include "llvm/Constants.h"
24#include "llvm/DerivedTypes.h"
25#include "llvm/Function.h"
26#include "llvm/PassManager.h"
27#include "llvm/CodeGen/JITCodeEmitter.h"
28#include "llvm/CodeGen/MachineConstantPool.h"
29#include "llvm/CodeGen/MachineFunctionPass.h"
30#include "llvm/CodeGen/MachineInstr.h"
31#include "llvm/CodeGen/MachineJumpTableInfo.h"
32#include "llvm/CodeGen/MachineModuleInfo.h"
33#include "llvm/CodeGen/Passes.h"
34#include "llvm/ADT/Statistic.h"
35#include "llvm/Support/Debug.h"
36#include "llvm/Support/ErrorHandling.h"
37#include "llvm/Support/raw_ostream.h"
38#ifndef NDEBUG
39#include <iomanip>
40#endif
41using namespace llvm;
42
43STATISTIC(NumEmitted, "Number of machine instructions emitted");
44
45namespace {
46
47  class ARMCodeEmitter : public MachineFunctionPass {
48    ARMJITInfo                *JTI;
49    const ARMBaseInstrInfo    *II;
50    const TargetData          *TD;
51    const ARMSubtarget        *Subtarget;
52    TargetMachine             &TM;
53    JITCodeEmitter            &MCE;
54    MachineModuleInfo *MMI;
55    const std::vector<MachineConstantPoolEntry> *MCPEs;
56    const std::vector<MachineJumpTableEntry> *MJTEs;
57    bool IsPIC;
58    bool IsThumb;
59
60    void getAnalysisUsage(AnalysisUsage &AU) const {
61      AU.addRequired<MachineModuleInfo>();
62      MachineFunctionPass::getAnalysisUsage(AU);
63    }
64
65    static char ID;
66  public:
67    ARMCodeEmitter(TargetMachine &tm, JITCodeEmitter &mce)
68      : MachineFunctionPass(ID), JTI(0),
69        II((const ARMBaseInstrInfo *)tm.getInstrInfo()),
70        TD(tm.getTargetData()), TM(tm),
71        MCE(mce), MCPEs(0), MJTEs(0),
72        IsPIC(TM.getRelocationModel() == Reloc::PIC_), IsThumb(false) {}
73
74    /// getBinaryCodeForInstr - This function, generated by the
75    /// CodeEmitterGenerator using TableGen, produces the binary encoding for
76    /// machine instructions.
77    uint64_t getBinaryCodeForInstr(const MachineInstr &MI) const;
78
79    bool runOnMachineFunction(MachineFunction &MF);
80
81    virtual const char *getPassName() const {
82      return "ARM Machine Code Emitter";
83    }
84
85    void emitInstruction(const MachineInstr &MI);
86
87  private:
88
89    void emitWordLE(unsigned Binary);
90    void emitDWordLE(uint64_t Binary);
91    void emitConstantToMemory(unsigned CPI, const Constant *CV);
92    void emitConstPoolInstruction(const MachineInstr &MI);
93    void emitMOVi32immInstruction(const MachineInstr &MI);
94    void emitMOVi2piecesInstruction(const MachineInstr &MI);
95    void emitLEApcrelInstruction(const MachineInstr &MI);
96    void emitLEApcrelJTInstruction(const MachineInstr &MI);
97    void emitPseudoMoveInstruction(const MachineInstr &MI);
98    void addPCLabel(unsigned LabelID);
99    void emitPseudoInstruction(const MachineInstr &MI);
100    unsigned getMachineSoRegOpValue(const MachineInstr &MI,
101                                    const MCInstrDesc &MCID,
102                                    const MachineOperand &MO,
103                                    unsigned OpIdx);
104
105    unsigned getMachineSoImmOpValue(unsigned SoImm);
106    unsigned getAddrModeSBit(const MachineInstr &MI,
107                             const MCInstrDesc &MCID) const;
108
109    void emitDataProcessingInstruction(const MachineInstr &MI,
110                                       unsigned ImplicitRd = 0,
111                                       unsigned ImplicitRn = 0);
112
113    void emitLoadStoreInstruction(const MachineInstr &MI,
114                                  unsigned ImplicitRd = 0,
115                                  unsigned ImplicitRn = 0);
116
117    void emitMiscLoadStoreInstruction(const MachineInstr &MI,
118                                      unsigned ImplicitRn = 0);
119
120    void emitLoadStoreMultipleInstruction(const MachineInstr &MI);
121
122    void emitMulFrmInstruction(const MachineInstr &MI);
123
124    void emitExtendInstruction(const MachineInstr &MI);
125
126    void emitMiscArithInstruction(const MachineInstr &MI);
127
128    void emitSaturateInstruction(const MachineInstr &MI);
129
130    void emitBranchInstruction(const MachineInstr &MI);
131
132    void emitInlineJumpTable(unsigned JTIndex);
133
134    void emitMiscBranchInstruction(const MachineInstr &MI);
135
136    void emitVFPArithInstruction(const MachineInstr &MI);
137
138    void emitVFPConversionInstruction(const MachineInstr &MI);
139
140    void emitVFPLoadStoreInstruction(const MachineInstr &MI);
141
142    void emitVFPLoadStoreMultipleInstruction(const MachineInstr &MI);
143
144    void emitMiscInstruction(const MachineInstr &MI);
145
146    void emitNEONLaneInstruction(const MachineInstr &MI);
147    void emitNEONDupInstruction(const MachineInstr &MI);
148    void emitNEON1RegModImmInstruction(const MachineInstr &MI);
149    void emitNEON2RegInstruction(const MachineInstr &MI);
150    void emitNEON3RegInstruction(const MachineInstr &MI);
151
152    /// getMachineOpValue - Return binary encoding of operand. If the machine
153    /// operand requires relocation, record the relocation and return zero.
154    unsigned getMachineOpValue(const MachineInstr &MI,
155                               const MachineOperand &MO) const;
156    unsigned getMachineOpValue(const MachineInstr &MI, unsigned OpIdx) const {
157      return getMachineOpValue(MI, MI.getOperand(OpIdx));
158    }
159
160    // FIXME: The legacy JIT ARMCodeEmitter doesn't rely on the the
161    //  TableGen'erated getBinaryCodeForInstr() function to encode any
162    //  operand values, instead querying getMachineOpValue() directly for
163    //  each operand it needs to encode. Thus, any of the new encoder
164    //  helper functions can simply return 0 as the values the return
165    //  are already handled elsewhere. They are placeholders to allow this
166    //  encoder to continue to function until the MC encoder is sufficiently
167    //  far along that this one can be eliminated entirely.
168    unsigned NEONThumb2DataIPostEncoder(const MachineInstr &MI, unsigned Val)
169      const { return 0; }
170    unsigned NEONThumb2LoadStorePostEncoder(const MachineInstr &MI,unsigned Val)
171      const { return 0; }
172    unsigned NEONThumb2DupPostEncoder(const MachineInstr &MI,unsigned Val)
173      const { return 0; }
174    unsigned VFPThumb2PostEncoder(const MachineInstr&MI, unsigned Val)
175      const {
176      if (IsThumb) {
177        Val &= 0x0FFFFFFF;
178        Val |= 0xE0000000;
179      }
180      return Val;
181    }
182    unsigned getAdrLabelOpValue(const MachineInstr &MI, unsigned Op)
183      const { return 0; }
184    unsigned getThumbAdrLabelOpValue(const MachineInstr &MI, unsigned Op)
185      const { return 0; }
186    unsigned getThumbBLTargetOpValue(const MachineInstr &MI, unsigned Op)
187      const { return 0; }
188    unsigned getThumbBLXTargetOpValue(const MachineInstr &MI, unsigned Op)
189      const { return 0; }
190    unsigned getThumbBRTargetOpValue(const MachineInstr &MI, unsigned Op)
191      const { return 0; }
192    unsigned getThumbBCCTargetOpValue(const MachineInstr &MI, unsigned Op)
193      const { return 0; }
194    unsigned getThumbCBTargetOpValue(const MachineInstr &MI, unsigned Op)
195      const { return 0; }
196    unsigned getBranchTargetOpValue(const MachineInstr &MI, unsigned Op)
197      const { return 0; }
198    unsigned getUnconditionalBranchTargetOpValue(const MachineInstr &MI,
199      unsigned Op) const { return 0; }
200    unsigned getARMBranchTargetOpValue(const MachineInstr &MI, unsigned Op)
201      const { return 0; }
202    unsigned getARMBLTargetOpValue(const MachineInstr &MI, unsigned Op)
203      const { return 0; }
204    unsigned getARMBLXTargetOpValue(const MachineInstr &MI, unsigned Op)
205      const { return 0; }
206    unsigned getCCOutOpValue(const MachineInstr &MI, unsigned Op)
207      const { return 0; }
208    unsigned getSOImmOpValue(const MachineInstr &MI, unsigned Op)
209      const { return 0; }
210    unsigned getT2SOImmOpValue(const MachineInstr &MI, unsigned Op)
211      const { return 0; }
212    unsigned getSORegRegOpValue(const MachineInstr &MI, unsigned Op)
213      const { return 0; }
214    unsigned getSORegImmOpValue(const MachineInstr &MI, unsigned Op)
215      const { return 0; }
216    unsigned getThumbAddrModeRegRegOpValue(const MachineInstr &MI, unsigned Op)
217      const { return 0; }
218    unsigned getT2AddrModeImm12OpValue(const MachineInstr &MI, unsigned Op)
219      const { return 0; }
220    unsigned getT2AddrModeImm8OpValue(const MachineInstr &MI, unsigned Op)
221      const { return 0; }
222    unsigned getT2Imm8s4OpValue(const MachineInstr &MI, unsigned Op)
223      const { return 0; }
224    unsigned getT2AddrModeImm8s4OpValue(const MachineInstr &MI, unsigned Op)
225      const { return 0; }
226    unsigned getT2AddrModeImm0_1020s4OpValue(const MachineInstr &MI,unsigned Op)
227      const { return 0; }
228    unsigned getT2AddrModeImm8OffsetOpValue(const MachineInstr &MI, unsigned Op)
229      const { return 0; }
230    unsigned getT2AddrModeImm12OffsetOpValue(const MachineInstr &MI,unsigned Op)
231      const { return 0; }
232    unsigned getT2AddrModeSORegOpValue(const MachineInstr &MI, unsigned Op)
233      const { return 0; }
234    unsigned getT2SORegOpValue(const MachineInstr &MI, unsigned Op)
235      const { return 0; }
236    unsigned getT2AdrLabelOpValue(const MachineInstr &MI, unsigned Op)
237      const { return 0; }
238    unsigned getAddrMode6AddressOpValue(const MachineInstr &MI, unsigned Op)
239      const { return 0; }
240    unsigned getAddrMode6OneLane32AddressOpValue(const MachineInstr &MI,
241                                                 unsigned Op)
242      const { return 0; }
243    unsigned getAddrMode6DupAddressOpValue(const MachineInstr &MI, unsigned Op)
244      const { return 0; }
245    unsigned getAddrMode6OffsetOpValue(const MachineInstr &MI, unsigned Op)
246      const { return 0; }
247    unsigned getBitfieldInvertedMaskOpValue(const MachineInstr &MI,
248                                            unsigned Op) const { return 0; }
249    unsigned getSsatBitPosValue(const MachineInstr &MI,
250                                unsigned Op) const { return 0; }
251    uint32_t getLdStmModeOpValue(const MachineInstr &MI, unsigned OpIdx)
252      const {return 0; }
253    uint32_t getLdStSORegOpValue(const MachineInstr &MI, unsigned OpIdx)
254      const { return 0; }
255
256    unsigned getAddrModeImm12OpValue(const MachineInstr &MI, unsigned Op)
257      const {
258      // {17-13} = reg
259      // {12}    = (U)nsigned (add == '1', sub == '0')
260      // {11-0}  = imm12
261      const MachineOperand &MO  = MI.getOperand(Op);
262      const MachineOperand &MO1 = MI.getOperand(Op + 1);
263      if (!MO.isReg()) {
264        emitConstPoolAddress(MO.getIndex(), ARM::reloc_arm_cp_entry);
265        return 0;
266      }
267      unsigned Reg = getARMRegisterNumbering(MO.getReg());
268      int32_t Imm12 = MO1.getImm();
269      uint32_t Binary;
270      Binary = Imm12 & 0xfff;
271      if (Imm12 >= 0)
272        Binary |= (1 << 12);
273      Binary |= (Reg << 13);
274      return Binary;
275    }
276
277    unsigned getHiLo16ImmOpValue(const MachineInstr &MI, unsigned Op)
278      const {
279      const MCInstrDesc &MCID = MI.getDesc();
280      const MachineOperand &MO = MI.getOperand(Op);
281
282      unsigned Reloc = (MCID.Opcode == ARM::MOVi16 ?
283                       ARM::reloc_arm_movw : ARM::reloc_arm_movt);
284
285      if (!MO.isImm()) {
286        emitGlobalAddress(MO.getGlobal(), Reloc, true, false);
287        return 0;
288      }
289      unsigned Imm16 = static_cast<unsigned>(MO.getImm());
290      return Imm16;
291    }
292
293    uint32_t getAddrMode2OpValue(const MachineInstr &MI, unsigned OpIdx)
294      const { return 0;}
295    uint32_t getAddrMode2OffsetOpValue(const MachineInstr &MI, unsigned OpIdx)
296      const { return 0;}
297    uint32_t getPostIdxRegOpValue(const MachineInstr &MI, unsigned OpIdx)
298      const { return 0;}
299    uint32_t getAddrMode3OffsetOpValue(const MachineInstr &MI, unsigned OpIdx)
300      const { return 0;}
301    uint32_t getAddrMode3OpValue(const MachineInstr &MI, unsigned Op)
302      const { return 0; }
303    uint32_t getAddrModeThumbSPOpValue(const MachineInstr &MI, unsigned Op)
304      const { return 0; }
305    uint32_t getAddrModeSOpValue(const MachineInstr &MI, unsigned Op)
306      const { return 0; }
307    uint32_t getAddrModeISOpValue(const MachineInstr &MI, unsigned Op)
308      const { return 0; }
309    uint32_t getAddrModePCOpValue(const MachineInstr &MI, unsigned Op)
310      const { return 0; }
311    uint32_t getAddrMode5OpValue(const MachineInstr &MI, unsigned Op) const {
312      // {12-9}  = reg
313      // {8}     = (U)nsigned (add == '1', sub == '0')
314      // {7-0}   = imm8
315      uint32_t Binary = 0;
316      const MachineOperand &MO  = MI.getOperand(Op);
317      uint32_t Reg = getMachineOpValue(MI, MO);
318      Binary |= (Reg << 9);
319
320      // If there is a non-zero immediate offset, encode it.
321      if (MO.isReg()) {
322          const MachineOperand &MO1 = MI.getOperand(Op + 1);
323        if (uint32_t ImmOffs = ARM_AM::getAM5Offset(MO1.getImm())) {
324          if (ARM_AM::getAM5Op(MO1.getImm()) == ARM_AM::add)
325            Binary |= 1 << 8;
326          Binary |= ImmOffs & 0xff;
327          return Binary;
328        }
329      }
330
331      // If immediate offset is omitted, default to +0.
332      Binary |= 1 << 8;
333      return Binary;
334    }
335    unsigned getNEONVcvtImm32OpValue(const MachineInstr &MI, unsigned Op)
336      const { return 0; }
337
338    unsigned getRegisterListOpValue(const MachineInstr &MI, unsigned Op)
339      const { return 0; }
340
341    unsigned getShiftRight8Imm(const MachineInstr &MI, unsigned Op)
342      const { return 0; }
343    unsigned getShiftRight16Imm(const MachineInstr &MI, unsigned Op)
344      const { return 0; }
345    unsigned getShiftRight32Imm(const MachineInstr &MI, unsigned Op)
346      const { return 0; }
347    unsigned getShiftRight64Imm(const MachineInstr &MI, unsigned Op)
348      const { return 0; }
349
350    /// getMovi32Value - Return binary encoding of operand for movw/movt. If the
351    /// machine operand requires relocation, record the relocation and return
352    /// zero.
353    unsigned getMovi32Value(const MachineInstr &MI,const MachineOperand &MO,
354                            unsigned Reloc);
355
356    /// getShiftOp - Return the shift opcode (bit[6:5]) of the immediate value.
357    ///
358    unsigned getShiftOp(unsigned Imm) const ;
359
360    /// Routines that handle operands which add machine relocations which are
361    /// fixed up by the relocation stage.
362    void emitGlobalAddress(const GlobalValue *GV, unsigned Reloc,
363                           bool MayNeedFarStub,  bool Indirect,
364                           intptr_t ACPV = 0) const;
365    void emitExternalSymbolAddress(const char *ES, unsigned Reloc) const;
366    void emitConstPoolAddress(unsigned CPI, unsigned Reloc) const;
367    void emitJumpTableAddress(unsigned JTIndex, unsigned Reloc) const;
368    void emitMachineBasicBlock(MachineBasicBlock *BB, unsigned Reloc,
369                               intptr_t JTBase = 0) const;
370  };
371}
372
373char ARMCodeEmitter::ID = 0;
374
375/// createARMJITCodeEmitterPass - Return a pass that emits the collected ARM
376/// code to the specified MCE object.
377FunctionPass *llvm::createARMJITCodeEmitterPass(ARMBaseTargetMachine &TM,
378                                                JITCodeEmitter &JCE) {
379  return new ARMCodeEmitter(TM, JCE);
380}
381
382bool ARMCodeEmitter::runOnMachineFunction(MachineFunction &MF) {
383  assert((MF.getTarget().getRelocationModel() != Reloc::Default ||
384          MF.getTarget().getRelocationModel() != Reloc::Static) &&
385         "JIT relocation model must be set to static or default!");
386  JTI = ((ARMBaseTargetMachine &)MF.getTarget()).getJITInfo();
387  II = (const ARMBaseInstrInfo *)MF.getTarget().getInstrInfo();
388  TD = MF.getTarget().getTargetData();
389  Subtarget = &TM.getSubtarget<ARMSubtarget>();
390  MCPEs = &MF.getConstantPool()->getConstants();
391  MJTEs = 0;
392  if (MF.getJumpTableInfo()) MJTEs = &MF.getJumpTableInfo()->getJumpTables();
393  IsPIC = TM.getRelocationModel() == Reloc::PIC_;
394  IsThumb = MF.getInfo<ARMFunctionInfo>()->isThumbFunction();
395  JTI->Initialize(MF, IsPIC);
396  MMI = &getAnalysis<MachineModuleInfo>();
397  MCE.setModuleInfo(MMI);
398
399  do {
400    DEBUG(errs() << "JITTing function '"
401          << MF.getFunction()->getName() << "'\n");
402    MCE.startFunction(MF);
403    for (MachineFunction::iterator MBB = MF.begin(), E = MF.end();
404         MBB != E; ++MBB) {
405      MCE.StartMachineBasicBlock(MBB);
406      for (MachineBasicBlock::iterator I = MBB->begin(), E = MBB->end();
407           I != E; ++I)
408        emitInstruction(*I);
409    }
410  } while (MCE.finishFunction(MF));
411
412  return false;
413}
414
415/// getShiftOp - Return the shift opcode (bit[6:5]) of the immediate value.
416///
417unsigned ARMCodeEmitter::getShiftOp(unsigned Imm) const {
418  switch (ARM_AM::getAM2ShiftOpc(Imm)) {
419  default: llvm_unreachable("Unknown shift opc!");
420  case ARM_AM::asr: return 2;
421  case ARM_AM::lsl: return 0;
422  case ARM_AM::lsr: return 1;
423  case ARM_AM::ror:
424  case ARM_AM::rrx: return 3;
425  }
426}
427
428/// getMovi32Value - Return binary encoding of operand for movw/movt. If the
429/// machine operand requires relocation, record the relocation and return zero.
430unsigned ARMCodeEmitter::getMovi32Value(const MachineInstr &MI,
431                                        const MachineOperand &MO,
432                                        unsigned Reloc) {
433  assert(((Reloc == ARM::reloc_arm_movt) || (Reloc == ARM::reloc_arm_movw))
434      && "Relocation to this function should be for movt or movw");
435
436  if (MO.isImm())
437    return static_cast<unsigned>(MO.getImm());
438  else if (MO.isGlobal())
439    emitGlobalAddress(MO.getGlobal(), Reloc, true, false);
440  else if (MO.isSymbol())
441    emitExternalSymbolAddress(MO.getSymbolName(), Reloc);
442  else if (MO.isMBB())
443    emitMachineBasicBlock(MO.getMBB(), Reloc);
444  else {
445#ifndef NDEBUG
446    errs() << MO;
447#endif
448    llvm_unreachable("Unsupported operand type for movw/movt");
449  }
450  return 0;
451}
452
453/// getMachineOpValue - Return binary encoding of operand. If the machine
454/// operand requires relocation, record the relocation and return zero.
455unsigned ARMCodeEmitter::getMachineOpValue(const MachineInstr &MI,
456                                           const MachineOperand &MO) const {
457  if (MO.isReg())
458    return getARMRegisterNumbering(MO.getReg());
459  else if (MO.isImm())
460    return static_cast<unsigned>(MO.getImm());
461  else if (MO.isFPImm())
462    return static_cast<unsigned>(MO.getFPImm()->getValueAPF()
463                      .bitcastToAPInt().getHiBits(32).getLimitedValue());
464  else if (MO.isGlobal())
465    emitGlobalAddress(MO.getGlobal(), ARM::reloc_arm_branch, true, false);
466  else if (MO.isSymbol())
467    emitExternalSymbolAddress(MO.getSymbolName(), ARM::reloc_arm_branch);
468  else if (MO.isCPI()) {
469    const MCInstrDesc &MCID = MI.getDesc();
470    // For VFP load, the immediate offset is multiplied by 4.
471    unsigned Reloc =  ((MCID.TSFlags & ARMII::FormMask) == ARMII::VFPLdStFrm)
472      ? ARM::reloc_arm_vfp_cp_entry : ARM::reloc_arm_cp_entry;
473    emitConstPoolAddress(MO.getIndex(), Reloc);
474  } else if (MO.isJTI())
475    emitJumpTableAddress(MO.getIndex(), ARM::reloc_arm_relative);
476  else if (MO.isMBB())
477    emitMachineBasicBlock(MO.getMBB(), ARM::reloc_arm_branch);
478  else
479    llvm_unreachable("Unable to encode MachineOperand!");
480  return 0;
481}
482
483/// emitGlobalAddress - Emit the specified address to the code stream.
484///
485void ARMCodeEmitter::emitGlobalAddress(const GlobalValue *GV, unsigned Reloc,
486                                       bool MayNeedFarStub, bool Indirect,
487                                       intptr_t ACPV) const {
488  MachineRelocation MR = Indirect
489    ? MachineRelocation::getIndirectSymbol(MCE.getCurrentPCOffset(), Reloc,
490                                           const_cast<GlobalValue *>(GV),
491                                           ACPV, MayNeedFarStub)
492    : MachineRelocation::getGV(MCE.getCurrentPCOffset(), Reloc,
493                               const_cast<GlobalValue *>(GV), ACPV,
494                               MayNeedFarStub);
495  MCE.addRelocation(MR);
496}
497
498/// emitExternalSymbolAddress - Arrange for the address of an external symbol to
499/// be emitted to the current location in the function, and allow it to be PC
500/// relative.
501void ARMCodeEmitter::
502emitExternalSymbolAddress(const char *ES, unsigned Reloc) const {
503  MCE.addRelocation(MachineRelocation::getExtSym(MCE.getCurrentPCOffset(),
504                                                 Reloc, ES));
505}
506
507/// emitConstPoolAddress - Arrange for the address of an constant pool
508/// to be emitted to the current location in the function, and allow it to be PC
509/// relative.
510void ARMCodeEmitter::emitConstPoolAddress(unsigned CPI, unsigned Reloc) const {
511  // Tell JIT emitter we'll resolve the address.
512  MCE.addRelocation(MachineRelocation::getConstPool(MCE.getCurrentPCOffset(),
513                                                    Reloc, CPI, 0, true));
514}
515
516/// emitJumpTableAddress - Arrange for the address of a jump table to
517/// be emitted to the current location in the function, and allow it to be PC
518/// relative.
519void ARMCodeEmitter::
520emitJumpTableAddress(unsigned JTIndex, unsigned Reloc) const {
521  MCE.addRelocation(MachineRelocation::getJumpTable(MCE.getCurrentPCOffset(),
522                                                    Reloc, JTIndex, 0, true));
523}
524
525/// emitMachineBasicBlock - Emit the specified address basic block.
526void ARMCodeEmitter::emitMachineBasicBlock(MachineBasicBlock *BB,
527                                           unsigned Reloc,
528                                           intptr_t JTBase) const {
529  MCE.addRelocation(MachineRelocation::getBB(MCE.getCurrentPCOffset(),
530                                             Reloc, BB, JTBase));
531}
532
533void ARMCodeEmitter::emitWordLE(unsigned Binary) {
534  DEBUG(errs() << "  0x";
535        errs().write_hex(Binary) << "\n");
536  MCE.emitWordLE(Binary);
537}
538
539void ARMCodeEmitter::emitDWordLE(uint64_t Binary) {
540  DEBUG(errs() << "  0x";
541        errs().write_hex(Binary) << "\n");
542  MCE.emitDWordLE(Binary);
543}
544
545void ARMCodeEmitter::emitInstruction(const MachineInstr &MI) {
546  DEBUG(errs() << "JIT: " << (void*)MCE.getCurrentPCValue() << ":\t" << MI);
547
548  MCE.processDebugLoc(MI.getDebugLoc(), true);
549
550  ++NumEmitted;  // Keep track of the # of mi's emitted
551  switch (MI.getDesc().TSFlags & ARMII::FormMask) {
552  default: {
553    llvm_unreachable("Unhandled instruction encoding format!");
554  }
555  case ARMII::MiscFrm:
556    if (MI.getOpcode() == ARM::LEApcrelJT) {
557      // Materialize jumptable address.
558      emitLEApcrelJTInstruction(MI);
559      break;
560    }
561    llvm_unreachable("Unhandled instruction encoding!");
562  case ARMII::Pseudo:
563    emitPseudoInstruction(MI);
564    break;
565  case ARMII::DPFrm:
566  case ARMII::DPSoRegFrm:
567    emitDataProcessingInstruction(MI);
568    break;
569  case ARMII::LdFrm:
570  case ARMII::StFrm:
571    emitLoadStoreInstruction(MI);
572    break;
573  case ARMII::LdMiscFrm:
574  case ARMII::StMiscFrm:
575    emitMiscLoadStoreInstruction(MI);
576    break;
577  case ARMII::LdStMulFrm:
578    emitLoadStoreMultipleInstruction(MI);
579    break;
580  case ARMII::MulFrm:
581    emitMulFrmInstruction(MI);
582    break;
583  case ARMII::ExtFrm:
584    emitExtendInstruction(MI);
585    break;
586  case ARMII::ArithMiscFrm:
587    emitMiscArithInstruction(MI);
588    break;
589  case ARMII::SatFrm:
590    emitSaturateInstruction(MI);
591    break;
592  case ARMII::BrFrm:
593    emitBranchInstruction(MI);
594    break;
595  case ARMII::BrMiscFrm:
596    emitMiscBranchInstruction(MI);
597    break;
598  // VFP instructions.
599  case ARMII::VFPUnaryFrm:
600  case ARMII::VFPBinaryFrm:
601    emitVFPArithInstruction(MI);
602    break;
603  case ARMII::VFPConv1Frm:
604  case ARMII::VFPConv2Frm:
605  case ARMII::VFPConv3Frm:
606  case ARMII::VFPConv4Frm:
607  case ARMII::VFPConv5Frm:
608    emitVFPConversionInstruction(MI);
609    break;
610  case ARMII::VFPLdStFrm:
611    emitVFPLoadStoreInstruction(MI);
612    break;
613  case ARMII::VFPLdStMulFrm:
614    emitVFPLoadStoreMultipleInstruction(MI);
615    break;
616  case ARMII::VFPMiscFrm:
617    emitMiscInstruction(MI);
618    break;
619  // NEON instructions.
620  case ARMII::NGetLnFrm:
621  case ARMII::NSetLnFrm:
622    emitNEONLaneInstruction(MI);
623    break;
624  case ARMII::NDupFrm:
625    emitNEONDupInstruction(MI);
626    break;
627  case ARMII::N1RegModImmFrm:
628    emitNEON1RegModImmInstruction(MI);
629    break;
630  case ARMII::N2RegFrm:
631    emitNEON2RegInstruction(MI);
632    break;
633  case ARMII::N3RegFrm:
634    emitNEON3RegInstruction(MI);
635    break;
636  }
637  MCE.processDebugLoc(MI.getDebugLoc(), false);
638}
639
640void ARMCodeEmitter::emitConstantToMemory(unsigned CPI, const Constant *C) {
641  DEBUG({
642      errs() << "  ** Constant pool #" << CPI << " @ "
643             << (void*)MCE.getCurrentPCValue() << " ";
644      if (const Function *F = dyn_cast<Function>(C))
645        errs() << F->getName();
646      else
647        errs() << *C;
648      errs() << '\n';
649    });
650
651  switch (C->getValueID()) {
652  default: {
653    llvm_unreachable("Unable to handle this constantpool entry!");
654    break;
655  }
656  case Value::GlobalVariableVal: {
657    emitGlobalAddress(static_cast<const GlobalValue*>(C),
658                      ARM::reloc_arm_absolute, isa<Function>(C), false);
659    emitWordLE(0);
660    break;
661  }
662  case Value::ConstantIntVal: {
663    const ConstantInt *CI = static_cast<const ConstantInt*>(C);
664    uint32_t Val = *(uint32_t*)CI->getValue().getRawData();
665    emitWordLE(Val);
666    break;
667  }
668  case Value::ConstantFPVal: {
669    const ConstantFP *CFP = static_cast<const ConstantFP*>(C);
670    if (CFP->getType()->isFloatTy())
671      emitWordLE(CFP->getValueAPF().bitcastToAPInt().getZExtValue());
672    else if (CFP->getType()->isDoubleTy())
673      emitDWordLE(CFP->getValueAPF().bitcastToAPInt().getZExtValue());
674    else {
675      llvm_unreachable("Unable to handle this constantpool entry!");
676    }
677    break;
678  }
679  case Value::ConstantArrayVal: {
680    const ConstantArray *CA = static_cast<const ConstantArray*>(C);
681    for (unsigned i = 0, e = CA->getNumOperands(); i != e; ++i)
682      emitConstantToMemory(CPI, CA->getOperand(i));
683    break;
684  }
685  }
686
687  return;
688}
689
690void ARMCodeEmitter::emitConstPoolInstruction(const MachineInstr &MI) {
691  unsigned CPI = MI.getOperand(0).getImm();       // CP instruction index.
692  unsigned CPIndex = MI.getOperand(1).getIndex(); // Actual cp entry index.
693  const MachineConstantPoolEntry &MCPE = (*MCPEs)[CPIndex];
694
695  // Remember the CONSTPOOL_ENTRY address for later relocation.
696  JTI->addConstantPoolEntryAddr(CPI, MCE.getCurrentPCValue());
697
698  // Emit constpool island entry. In most cases, the actual values will be
699  // resolved and relocated after code emission.
700  if (MCPE.isMachineConstantPoolEntry()) {
701    ARMConstantPoolValue *ACPV =
702      static_cast<ARMConstantPoolValue*>(MCPE.Val.MachineCPVal);
703
704    DEBUG(errs() << "  ** ARM constant pool #" << CPI << " @ "
705          << (void*)MCE.getCurrentPCValue() << " " << *ACPV << '\n');
706
707    assert(ACPV->isGlobalValue() && "unsupported constant pool value");
708    const GlobalValue *GV = cast<ARMConstantPoolConstant>(ACPV)->getGV();
709    if (GV) {
710      Reloc::Model RelocM = TM.getRelocationModel();
711      emitGlobalAddress(GV, ARM::reloc_arm_machine_cp_entry,
712                        isa<Function>(GV),
713                        Subtarget->GVIsIndirectSymbol(GV, RelocM),
714                        (intptr_t)ACPV);
715    } else  {
716      const char *Sym = cast<ARMConstantPoolSymbol>(ACPV)->getSymbol();
717      emitExternalSymbolAddress(Sym, ARM::reloc_arm_absolute);
718    }
719    emitWordLE(0);
720  } else {
721    emitConstantToMemory(CPI, MCPE.Val.ConstVal);
722  }
723}
724
725void ARMCodeEmitter::emitMOVi32immInstruction(const MachineInstr &MI) {
726  const MachineOperand &MO0 = MI.getOperand(0);
727  const MachineOperand &MO1 = MI.getOperand(1);
728
729  // Emit the 'movw' instruction.
730  unsigned Binary = 0x30 << 20;  // mov: Insts{27-20} = 0b00110000
731
732  unsigned Lo16 = getMovi32Value(MI, MO1, ARM::reloc_arm_movw) & 0xFFFF;
733
734  // Set the conditional execution predicate.
735  Binary |= II->getPredicate(&MI) << ARMII::CondShift;
736
737  // Encode Rd.
738  Binary |= getMachineOpValue(MI, MO0) << ARMII::RegRdShift;
739
740  // Encode imm16 as imm4:imm12
741  Binary |= Lo16 & 0xFFF; // Insts{11-0} = imm12
742  Binary |= ((Lo16 >> 12) & 0xF) << 16; // Insts{19-16} = imm4
743  emitWordLE(Binary);
744
745  unsigned Hi16 = getMovi32Value(MI, MO1, ARM::reloc_arm_movt) >> 16;
746  // Emit the 'movt' instruction.
747  Binary = 0x34 << 20; // movt: Insts{27-20} = 0b00110100
748
749  // Set the conditional execution predicate.
750  Binary |= II->getPredicate(&MI) << ARMII::CondShift;
751
752  // Encode Rd.
753  Binary |= getMachineOpValue(MI, MO0) << ARMII::RegRdShift;
754
755  // Encode imm16 as imm4:imm1, same as movw above.
756  Binary |= Hi16 & 0xFFF;
757  Binary |= ((Hi16 >> 12) & 0xF) << 16;
758  emitWordLE(Binary);
759}
760
761void ARMCodeEmitter::emitMOVi2piecesInstruction(const MachineInstr &MI) {
762  const MachineOperand &MO0 = MI.getOperand(0);
763  const MachineOperand &MO1 = MI.getOperand(1);
764  assert(MO1.isImm() && ARM_AM::isSOImmTwoPartVal(MO1.getImm()) &&
765                                                  "Not a valid so_imm value!");
766  unsigned V1 = ARM_AM::getSOImmTwoPartFirst(MO1.getImm());
767  unsigned V2 = ARM_AM::getSOImmTwoPartSecond(MO1.getImm());
768
769  // Emit the 'mov' instruction.
770  unsigned Binary = 0xd << 21;  // mov: Insts{24-21} = 0b1101
771
772  // Set the conditional execution predicate.
773  Binary |= II->getPredicate(&MI) << ARMII::CondShift;
774
775  // Encode Rd.
776  Binary |= getMachineOpValue(MI, MO0) << ARMII::RegRdShift;
777
778  // Encode so_imm.
779  // Set bit I(25) to identify this is the immediate form of <shifter_op>
780  Binary |= 1 << ARMII::I_BitShift;
781  Binary |= getMachineSoImmOpValue(V1);
782  emitWordLE(Binary);
783
784  // Now the 'orr' instruction.
785  Binary = 0xc << 21;  // orr: Insts{24-21} = 0b1100
786
787  // Set the conditional execution predicate.
788  Binary |= II->getPredicate(&MI) << ARMII::CondShift;
789
790  // Encode Rd.
791  Binary |= getMachineOpValue(MI, MO0) << ARMII::RegRdShift;
792
793  // Encode Rn.
794  Binary |= getMachineOpValue(MI, MO0) << ARMII::RegRnShift;
795
796  // Encode so_imm.
797  // Set bit I(25) to identify this is the immediate form of <shifter_op>
798  Binary |= 1 << ARMII::I_BitShift;
799  Binary |= getMachineSoImmOpValue(V2);
800  emitWordLE(Binary);
801}
802
803void ARMCodeEmitter::emitLEApcrelInstruction(const MachineInstr &MI) {
804  // It's basically add r, pc, (LCPI - $+8)
805  const MCInstrDesc &MCID = MI.getDesc();
806
807  unsigned Binary = 0;
808
809  // Set the conditional execution predicate
810  Binary |= II->getPredicate(&MI) << ARMII::CondShift;
811
812  // Encode S bit if MI modifies CPSR.
813  Binary |= getAddrModeSBit(MI, MCID);
814
815  // Encode Rd.
816  Binary |= getMachineOpValue(MI, 0) << ARMII::RegRdShift;
817
818  // Encode Rn which is PC.
819  Binary |= getARMRegisterNumbering(ARM::PC) << ARMII::RegRnShift;
820
821  // Encode the displacement which is a so_imm.
822  // Set bit I(25) to identify this is the immediate form of <shifter_op>
823  Binary |= 1 << ARMII::I_BitShift;
824  emitConstPoolAddress(MI.getOperand(1).getIndex(), ARM::reloc_arm_so_imm_cp_entry);
825
826  emitWordLE(Binary);
827}
828
829void ARMCodeEmitter::emitLEApcrelJTInstruction(const MachineInstr &MI) {
830  // It's basically add r, pc, (LJTI - $+8)
831
832  const MCInstrDesc &MCID = MI.getDesc();
833
834  // Emit the 'add' instruction.
835  unsigned Binary = 0x4 << 21;  // add: Insts{24-21} = 0b0100
836
837  // Set the conditional execution predicate
838  Binary |= II->getPredicate(&MI) << ARMII::CondShift;
839
840  // Encode S bit if MI modifies CPSR.
841  Binary |= getAddrModeSBit(MI, MCID);
842
843  // Encode Rd.
844  Binary |= getMachineOpValue(MI, 0) << ARMII::RegRdShift;
845
846  // Encode Rn which is PC.
847  Binary |= getARMRegisterNumbering(ARM::PC) << ARMII::RegRnShift;
848
849  // Encode the displacement.
850  Binary |= 1 << ARMII::I_BitShift;
851  emitJumpTableAddress(MI.getOperand(1).getIndex(), ARM::reloc_arm_jt_base);
852
853  emitWordLE(Binary);
854}
855
856void ARMCodeEmitter::emitPseudoMoveInstruction(const MachineInstr &MI) {
857  unsigned Opcode = MI.getDesc().Opcode;
858
859  // Part of binary is determined by TableGn.
860  unsigned Binary = getBinaryCodeForInstr(MI);
861
862  // Set the conditional execution predicate
863  Binary |= II->getPredicate(&MI) << ARMII::CondShift;
864
865  // Encode S bit if MI modifies CPSR.
866  if (Opcode == ARM::MOVsrl_flag || Opcode == ARM::MOVsra_flag)
867    Binary |= 1 << ARMII::S_BitShift;
868
869  // Encode register def if there is one.
870  Binary |= getMachineOpValue(MI, 0) << ARMII::RegRdShift;
871
872  // Encode the shift operation.
873  switch (Opcode) {
874  default: break;
875  case ARM::RRX:
876    // rrx
877    Binary |= 0x6 << 4;
878    break;
879  case ARM::MOVsrl_flag:
880    // lsr #1
881    Binary |= (0x2 << 4) | (1 << 7);
882    break;
883  case ARM::MOVsra_flag:
884    // asr #1
885    Binary |= (0x4 << 4) | (1 << 7);
886    break;
887  }
888
889  // Encode register Rm.
890  Binary |= getMachineOpValue(MI, 1);
891
892  emitWordLE(Binary);
893}
894
895void ARMCodeEmitter::addPCLabel(unsigned LabelID) {
896  DEBUG(errs() << "  ** LPC" << LabelID << " @ "
897        << (void*)MCE.getCurrentPCValue() << '\n');
898  JTI->addPCLabelAddr(LabelID, MCE.getCurrentPCValue());
899}
900
901void ARMCodeEmitter::emitPseudoInstruction(const MachineInstr &MI) {
902  unsigned Opcode = MI.getDesc().Opcode;
903  switch (Opcode) {
904  default:
905    llvm_unreachable("ARMCodeEmitter::emitPseudoInstruction");
906  case ARM::B:
907    emitBranchInstruction(MI);
908    break;
909  case ARM::BR_JTr:
910  case ARM::BR_JTm:
911  case ARM::BR_JTadd:
912    emitMiscBranchInstruction(MI);
913    break;
914  case ARM::BX_CALL:
915  case ARM::BMOVPCRX_CALL: {
916    // First emit mov lr, pc
917    unsigned Binary = 0x01a0e00f;
918    Binary |= II->getPredicate(&MI) << ARMII::CondShift;
919    emitWordLE(Binary);
920
921    // and then emit the branch.
922    emitMiscBranchInstruction(MI);
923    break;
924  }
925  case TargetOpcode::INLINEASM: {
926    // We allow inline assembler nodes with empty bodies - they can
927    // implicitly define registers, which is ok for JIT.
928    if (MI.getOperand(0).getSymbolName()[0]) {
929      report_fatal_error("JIT does not support inline asm!");
930    }
931    break;
932  }
933  case TargetOpcode::PROLOG_LABEL:
934  case TargetOpcode::EH_LABEL:
935    MCE.emitLabel(MI.getOperand(0).getMCSymbol());
936    break;
937  case TargetOpcode::IMPLICIT_DEF:
938  case TargetOpcode::KILL:
939    // Do nothing.
940    break;
941  case ARM::CONSTPOOL_ENTRY:
942    emitConstPoolInstruction(MI);
943    break;
944  case ARM::LDMIA_RET:
945    emitLoadStoreMultipleInstruction(MI);
946    break;
947  case ARM::PICADD: {
948    // Remember of the address of the PC label for relocation later.
949    addPCLabel(MI.getOperand(2).getImm());
950    // PICADD is just an add instruction that implicitly read pc.
951    emitDataProcessingInstruction(MI, 0, ARM::PC);
952    break;
953  }
954  case ARM::PICLDR:
955  case ARM::PICLDRB:
956  case ARM::PICSTR:
957  case ARM::PICSTRB: {
958    // Remember of the address of the PC label for relocation later.
959    addPCLabel(MI.getOperand(2).getImm());
960    // These are just load / store instructions that implicitly read pc.
961    emitLoadStoreInstruction(MI, 0, ARM::PC);
962    break;
963  }
964  case ARM::PICLDRH:
965  case ARM::PICLDRSH:
966  case ARM::PICLDRSB:
967  case ARM::PICSTRH: {
968    // Remember of the address of the PC label for relocation later.
969    addPCLabel(MI.getOperand(2).getImm());
970    // These are just load / store instructions that implicitly read pc.
971    emitMiscLoadStoreInstruction(MI, ARM::PC);
972    break;
973  }
974
975  case ARM::MOVi32imm:
976    // Two instructions to materialize a constant.
977    if (Subtarget->hasV6T2Ops())
978      emitMOVi32immInstruction(MI);
979    else
980      emitMOVi2piecesInstruction(MI);
981    break;
982  case ARM::LEApcrel:
983    // Materialize constantpool index address.
984    emitLEApcrelInstruction(MI);
985    break;
986  case ARM::LEApcrelJT:
987    // Materialize jumptable address.
988    emitLEApcrelJTInstruction(MI);
989    break;
990  case ARM::RRX:
991  case ARM::MOVsrl_flag:
992  case ARM::MOVsra_flag:
993    emitPseudoMoveInstruction(MI);
994    break;
995  }
996}
997
998unsigned ARMCodeEmitter::getMachineSoRegOpValue(const MachineInstr &MI,
999                                                const MCInstrDesc &MCID,
1000                                                const MachineOperand &MO,
1001                                                unsigned OpIdx) {
1002  unsigned Binary = getMachineOpValue(MI, MO);
1003
1004  const MachineOperand &MO1 = MI.getOperand(OpIdx + 1);
1005  const MachineOperand &MO2 = MI.getOperand(OpIdx + 2);
1006  ARM_AM::ShiftOpc SOpc = ARM_AM::getSORegShOp(MO2.getImm());
1007
1008  // Encode the shift opcode.
1009  unsigned SBits = 0;
1010  unsigned Rs = MO1.getReg();
1011  if (Rs) {
1012    // Set shift operand (bit[7:4]).
1013    // LSL - 0001
1014    // LSR - 0011
1015    // ASR - 0101
1016    // ROR - 0111
1017    // RRX - 0110 and bit[11:8] clear.
1018    switch (SOpc) {
1019    default: llvm_unreachable("Unknown shift opc!");
1020    case ARM_AM::lsl: SBits = 0x1; break;
1021    case ARM_AM::lsr: SBits = 0x3; break;
1022    case ARM_AM::asr: SBits = 0x5; break;
1023    case ARM_AM::ror: SBits = 0x7; break;
1024    case ARM_AM::rrx: SBits = 0x6; break;
1025    }
1026  } else {
1027    // Set shift operand (bit[6:4]).
1028    // LSL - 000
1029    // LSR - 010
1030    // ASR - 100
1031    // ROR - 110
1032    switch (SOpc) {
1033    default: llvm_unreachable("Unknown shift opc!");
1034    case ARM_AM::lsl: SBits = 0x0; break;
1035    case ARM_AM::lsr: SBits = 0x2; break;
1036    case ARM_AM::asr: SBits = 0x4; break;
1037    case ARM_AM::ror: SBits = 0x6; break;
1038    }
1039  }
1040  Binary |= SBits << 4;
1041  if (SOpc == ARM_AM::rrx)
1042    return Binary;
1043
1044  // Encode the shift operation Rs or shift_imm (except rrx).
1045  if (Rs) {
1046    // Encode Rs bit[11:8].
1047    assert(ARM_AM::getSORegOffset(MO2.getImm()) == 0);
1048    return Binary | (getARMRegisterNumbering(Rs) << ARMII::RegRsShift);
1049  }
1050
1051  // Encode shift_imm bit[11:7].
1052  return Binary | ARM_AM::getSORegOffset(MO2.getImm()) << 7;
1053}
1054
1055unsigned ARMCodeEmitter::getMachineSoImmOpValue(unsigned SoImm) {
1056  int SoImmVal = ARM_AM::getSOImmVal(SoImm);
1057  assert(SoImmVal != -1 && "Not a valid so_imm value!");
1058
1059  // Encode rotate_imm.
1060  unsigned Binary = (ARM_AM::getSOImmValRot((unsigned)SoImmVal) >> 1)
1061    << ARMII::SoRotImmShift;
1062
1063  // Encode immed_8.
1064  Binary |= ARM_AM::getSOImmValImm((unsigned)SoImmVal);
1065  return Binary;
1066}
1067
1068unsigned ARMCodeEmitter::getAddrModeSBit(const MachineInstr &MI,
1069                                         const MCInstrDesc &MCID) const {
1070  for (unsigned i = MI.getNumOperands(), e = MCID.getNumOperands(); i >= e;--i){
1071    const MachineOperand &MO = MI.getOperand(i-1);
1072    if (MO.isReg() && MO.isDef() && MO.getReg() == ARM::CPSR)
1073      return 1 << ARMII::S_BitShift;
1074  }
1075  return 0;
1076}
1077
1078void ARMCodeEmitter::emitDataProcessingInstruction(const MachineInstr &MI,
1079                                                   unsigned ImplicitRd,
1080                                                   unsigned ImplicitRn) {
1081  const MCInstrDesc &MCID = MI.getDesc();
1082
1083  // Part of binary is determined by TableGn.
1084  unsigned Binary = getBinaryCodeForInstr(MI);
1085
1086  if (MCID.Opcode == ARM::MOVi16 || MCID.Opcode == ARM::MOVTi16) {
1087      emitWordLE(Binary);
1088      return;
1089  }
1090
1091  // Set the conditional execution predicate
1092  Binary |= II->getPredicate(&MI) << ARMII::CondShift;
1093
1094  // Encode S bit if MI modifies CPSR.
1095  Binary |= getAddrModeSBit(MI, MCID);
1096
1097  // Encode register def if there is one.
1098  unsigned NumDefs = MCID.getNumDefs();
1099  unsigned OpIdx = 0;
1100  if (NumDefs)
1101    Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRdShift;
1102  else if (ImplicitRd)
1103    // Special handling for implicit use (e.g. PC).
1104    Binary |= (getARMRegisterNumbering(ImplicitRd) << ARMII::RegRdShift);
1105
1106  if (MCID.Opcode == ARM::MOVi16) {
1107      // Get immediate from MI.
1108      unsigned Lo16 = getMovi32Value(MI, MI.getOperand(OpIdx),
1109                      ARM::reloc_arm_movw);
1110      // Encode imm which is the same as in emitMOVi32immInstruction().
1111      Binary |= Lo16 & 0xFFF;
1112      Binary |= ((Lo16 >> 12) & 0xF) << 16;
1113      emitWordLE(Binary);
1114      return;
1115  } else if(MCID.Opcode == ARM::MOVTi16) {
1116      unsigned Hi16 = (getMovi32Value(MI, MI.getOperand(OpIdx),
1117                       ARM::reloc_arm_movt) >> 16);
1118      Binary |= Hi16 & 0xFFF;
1119      Binary |= ((Hi16 >> 12) & 0xF) << 16;
1120      emitWordLE(Binary);
1121      return;
1122  } else if ((MCID.Opcode == ARM::BFC) || (MCID.Opcode == ARM::BFI)) {
1123      uint32_t v = ~MI.getOperand(2).getImm();
1124      int32_t lsb = CountTrailingZeros_32(v);
1125      int32_t msb = (32 - CountLeadingZeros_32(v)) - 1;
1126      // Instr{20-16} = msb, Instr{11-7} = lsb
1127      Binary |= (msb & 0x1F) << 16;
1128      Binary |= (lsb & 0x1F) << 7;
1129      emitWordLE(Binary);
1130      return;
1131  } else if ((MCID.Opcode == ARM::UBFX) || (MCID.Opcode == ARM::SBFX)) {
1132      // Encode Rn in Instr{0-3}
1133      Binary |= getMachineOpValue(MI, OpIdx++);
1134
1135      uint32_t lsb = MI.getOperand(OpIdx++).getImm();
1136      uint32_t widthm1 = MI.getOperand(OpIdx++).getImm() - 1;
1137
1138      // Instr{20-16} = widthm1, Instr{11-7} = lsb
1139      Binary |= (widthm1 & 0x1F) << 16;
1140      Binary |= (lsb & 0x1F) << 7;
1141      emitWordLE(Binary);
1142      return;
1143  }
1144
1145  // If this is a two-address operand, skip it. e.g. MOVCCr operand 1.
1146  if (MCID.getOperandConstraint(OpIdx, MCOI::TIED_TO) != -1)
1147    ++OpIdx;
1148
1149  // Encode first non-shifter register operand if there is one.
1150  bool isUnary = MCID.TSFlags & ARMII::UnaryDP;
1151  if (!isUnary) {
1152    if (ImplicitRn)
1153      // Special handling for implicit use (e.g. PC).
1154      Binary |= (getARMRegisterNumbering(ImplicitRn) << ARMII::RegRnShift);
1155    else {
1156      Binary |= getMachineOpValue(MI, OpIdx) << ARMII::RegRnShift;
1157      ++OpIdx;
1158    }
1159  }
1160
1161  // Encode shifter operand.
1162  const MachineOperand &MO = MI.getOperand(OpIdx);
1163  if ((MCID.TSFlags & ARMII::FormMask) == ARMII::DPSoRegFrm) {
1164    // Encode SoReg.
1165    emitWordLE(Binary | getMachineSoRegOpValue(MI, MCID, MO, OpIdx));
1166    return;
1167  }
1168
1169  if (MO.isReg()) {
1170    // Encode register Rm.
1171    emitWordLE(Binary | getARMRegisterNumbering(MO.getReg()));
1172    return;
1173  }
1174
1175  // Encode so_imm.
1176  Binary |= getMachineSoImmOpValue((unsigned)MO.getImm());
1177
1178  emitWordLE(Binary);
1179}
1180
1181void ARMCodeEmitter::emitLoadStoreInstruction(const MachineInstr &MI,
1182                                              unsigned ImplicitRd,
1183                                              unsigned ImplicitRn) {
1184  const MCInstrDesc &MCID = MI.getDesc();
1185  unsigned Form = MCID.TSFlags & ARMII::FormMask;
1186  bool IsPrePost = (MCID.TSFlags & ARMII::IndexModeMask) != 0;
1187
1188  // Part of binary is determined by TableGn.
1189  unsigned Binary = getBinaryCodeForInstr(MI);
1190
1191  // If this is an LDRi12, STRi12 or LDRcp, nothing more needs be done.
1192  if (MI.getOpcode() == ARM::LDRi12 || MI.getOpcode() == ARM::LDRcp ||
1193      MI.getOpcode() == ARM::STRi12 || MI.getOpcode() == ARM::LDRBi12 ||
1194      MI.getOpcode() == ARM::STRBi12) {
1195    emitWordLE(Binary);
1196    return;
1197  }
1198
1199  if (MI.getOpcode() == ARM::BR_JTm)
1200    Binary = 0x710F000;
1201  else if (MI.getOpcode() == ARM::BR_JTr)
1202    Binary = 0x1A0F000;
1203
1204  // Set the conditional execution predicate
1205  Binary |= II->getPredicate(&MI) << ARMII::CondShift;
1206
1207  unsigned OpIdx = 0;
1208
1209  // Operand 0 of a pre- and post-indexed store is the address base
1210  // writeback. Skip it.
1211  bool Skipped = false;
1212  if (IsPrePost && Form == ARMII::StFrm) {
1213    ++OpIdx;
1214    Skipped = true;
1215  }
1216
1217  // Set first operand
1218  if (ImplicitRd)
1219    // Special handling for implicit use (e.g. PC).
1220    Binary |= (getARMRegisterNumbering(ImplicitRd) << ARMII::RegRdShift);
1221  else
1222    Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRdShift;
1223
1224  // Set second operand
1225  if (ImplicitRn)
1226    // Special handling for implicit use (e.g. PC).
1227    Binary |= (getARMRegisterNumbering(ImplicitRn) << ARMII::RegRnShift);
1228  else
1229    Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRnShift;
1230
1231  // If this is a two-address operand, skip it. e.g. LDR_PRE.
1232  if (!Skipped && MCID.getOperandConstraint(OpIdx, MCOI::TIED_TO) != -1)
1233    ++OpIdx;
1234
1235  const MachineOperand &MO2 = MI.getOperand(OpIdx);
1236  unsigned AM2Opc = (ImplicitRn == ARM::PC)
1237    ? 0 : MI.getOperand(OpIdx+1).getImm();
1238
1239  // Set bit U(23) according to sign of immed value (positive or negative).
1240  Binary |= ((ARM_AM::getAM2Op(AM2Opc) == ARM_AM::add ? 1 : 0) <<
1241             ARMII::U_BitShift);
1242  if (!MO2.getReg()) { // is immediate
1243    if (ARM_AM::getAM2Offset(AM2Opc))
1244      // Set the value of offset_12 field
1245      Binary |= ARM_AM::getAM2Offset(AM2Opc);
1246    emitWordLE(Binary);
1247    return;
1248  }
1249
1250  // Set bit I(25), because this is not in immediate encoding.
1251  Binary |= 1 << ARMII::I_BitShift;
1252  assert(TargetRegisterInfo::isPhysicalRegister(MO2.getReg()));
1253  // Set bit[3:0] to the corresponding Rm register
1254  Binary |= getARMRegisterNumbering(MO2.getReg());
1255
1256  // If this instr is in scaled register offset/index instruction, set
1257  // shift_immed(bit[11:7]) and shift(bit[6:5]) fields.
1258  if (unsigned ShImm = ARM_AM::getAM2Offset(AM2Opc)) {
1259    Binary |= getShiftOp(AM2Opc) << ARMII::ShiftImmShift;  // shift
1260    Binary |= ShImm              << ARMII::ShiftShift;     // shift_immed
1261  }
1262
1263  emitWordLE(Binary);
1264}
1265
1266void ARMCodeEmitter::emitMiscLoadStoreInstruction(const MachineInstr &MI,
1267                                                  unsigned ImplicitRn) {
1268  const MCInstrDesc &MCID = MI.getDesc();
1269  unsigned Form = MCID.TSFlags & ARMII::FormMask;
1270  bool IsPrePost = (MCID.TSFlags & ARMII::IndexModeMask) != 0;
1271
1272  // Part of binary is determined by TableGn.
1273  unsigned Binary = getBinaryCodeForInstr(MI);
1274
1275  // Set the conditional execution predicate
1276  Binary |= II->getPredicate(&MI) << ARMII::CondShift;
1277
1278  unsigned OpIdx = 0;
1279
1280  // Operand 0 of a pre- and post-indexed store is the address base
1281  // writeback. Skip it.
1282  bool Skipped = false;
1283  if (IsPrePost && Form == ARMII::StMiscFrm) {
1284    ++OpIdx;
1285    Skipped = true;
1286  }
1287
1288  // Set first operand
1289  Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRdShift;
1290
1291  // Skip LDRD and STRD's second operand.
1292  if (MCID.Opcode == ARM::LDRD || MCID.Opcode == ARM::STRD)
1293    ++OpIdx;
1294
1295  // Set second operand
1296  if (ImplicitRn)
1297    // Special handling for implicit use (e.g. PC).
1298    Binary |= (getARMRegisterNumbering(ImplicitRn) << ARMII::RegRnShift);
1299  else
1300    Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRnShift;
1301
1302  // If this is a two-address operand, skip it. e.g. LDRH_POST.
1303  if (!Skipped && MCID.getOperandConstraint(OpIdx, MCOI::TIED_TO) != -1)
1304    ++OpIdx;
1305
1306  const MachineOperand &MO2 = MI.getOperand(OpIdx);
1307  unsigned AM3Opc = (ImplicitRn == ARM::PC)
1308    ? 0 : MI.getOperand(OpIdx+1).getImm();
1309
1310  // Set bit U(23) according to sign of immed value (positive or negative)
1311  Binary |= ((ARM_AM::getAM3Op(AM3Opc) == ARM_AM::add ? 1 : 0) <<
1312             ARMII::U_BitShift);
1313
1314  // If this instr is in register offset/index encoding, set bit[3:0]
1315  // to the corresponding Rm register.
1316  if (MO2.getReg()) {
1317    Binary |= getARMRegisterNumbering(MO2.getReg());
1318    emitWordLE(Binary);
1319    return;
1320  }
1321
1322  // This instr is in immediate offset/index encoding, set bit 22 to 1.
1323  Binary |= 1 << ARMII::AM3_I_BitShift;
1324  if (unsigned ImmOffs = ARM_AM::getAM3Offset(AM3Opc)) {
1325    // Set operands
1326    Binary |= (ImmOffs >> 4) << ARMII::ImmHiShift;  // immedH
1327    Binary |= (ImmOffs & 0xF);                      // immedL
1328  }
1329
1330  emitWordLE(Binary);
1331}
1332
1333static unsigned getAddrModeUPBits(unsigned Mode) {
1334  unsigned Binary = 0;
1335
1336  // Set addressing mode by modifying bits U(23) and P(24)
1337  // IA - Increment after  - bit U = 1 and bit P = 0
1338  // IB - Increment before - bit U = 1 and bit P = 1
1339  // DA - Decrement after  - bit U = 0 and bit P = 0
1340  // DB - Decrement before - bit U = 0 and bit P = 1
1341  switch (Mode) {
1342  default: llvm_unreachable("Unknown addressing sub-mode!");
1343  case ARM_AM::da:                                     break;
1344  case ARM_AM::db: Binary |= 0x1 << ARMII::P_BitShift; break;
1345  case ARM_AM::ia: Binary |= 0x1 << ARMII::U_BitShift; break;
1346  case ARM_AM::ib: Binary |= 0x3 << ARMII::U_BitShift; break;
1347  }
1348
1349  return Binary;
1350}
1351
1352void ARMCodeEmitter::emitLoadStoreMultipleInstruction(const MachineInstr &MI) {
1353  const MCInstrDesc &MCID = MI.getDesc();
1354  bool IsUpdating = (MCID.TSFlags & ARMII::IndexModeMask) != 0;
1355
1356  // Part of binary is determined by TableGn.
1357  unsigned Binary = getBinaryCodeForInstr(MI);
1358
1359  if (MCID.getOpcode() == ARM::LDMIA_RET) {
1360    IsUpdating = true;
1361    Binary |= 0x8B00000;
1362  }
1363
1364  // Set the conditional execution predicate
1365  Binary |= II->getPredicate(&MI) << ARMII::CondShift;
1366
1367  // Skip operand 0 of an instruction with base register update.
1368  unsigned OpIdx = 0;
1369  if (IsUpdating)
1370    ++OpIdx;
1371
1372  // Set base address operand
1373  Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRnShift;
1374
1375  // Set addressing mode by modifying bits U(23) and P(24)
1376  ARM_AM::AMSubMode Mode = ARM_AM::getLoadStoreMultipleSubMode(MI.getOpcode());
1377  Binary |= getAddrModeUPBits(ARM_AM::getAM4SubMode(Mode));
1378
1379  // Set bit W(21)
1380  if (IsUpdating)
1381    Binary |= 0x1 << ARMII::W_BitShift;
1382
1383  // Set registers
1384  for (unsigned i = OpIdx+2, e = MI.getNumOperands(); i != e; ++i) {
1385    const MachineOperand &MO = MI.getOperand(i);
1386    if (!MO.isReg() || MO.isImplicit())
1387      break;
1388    unsigned RegNum = getARMRegisterNumbering(MO.getReg());
1389    assert(TargetRegisterInfo::isPhysicalRegister(MO.getReg()) &&
1390           RegNum < 16);
1391    Binary |= 0x1 << RegNum;
1392  }
1393
1394  emitWordLE(Binary);
1395}
1396
1397void ARMCodeEmitter::emitMulFrmInstruction(const MachineInstr &MI) {
1398  const MCInstrDesc &MCID = MI.getDesc();
1399
1400  // Part of binary is determined by TableGn.
1401  unsigned Binary = getBinaryCodeForInstr(MI);
1402
1403  // Set the conditional execution predicate
1404  Binary |= II->getPredicate(&MI) << ARMII::CondShift;
1405
1406  // Encode S bit if MI modifies CPSR.
1407  Binary |= getAddrModeSBit(MI, MCID);
1408
1409  // 32x32->64bit operations have two destination registers. The number
1410  // of register definitions will tell us if that's what we're dealing with.
1411  unsigned OpIdx = 0;
1412  if (MCID.getNumDefs() == 2)
1413    Binary |= getMachineOpValue (MI, OpIdx++) << ARMII::RegRdLoShift;
1414
1415  // Encode Rd
1416  Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRdHiShift;
1417
1418  // Encode Rm
1419  Binary |= getMachineOpValue(MI, OpIdx++);
1420
1421  // Encode Rs
1422  Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRsShift;
1423
1424  // Many multiple instructions (e.g. MLA) have three src operands. Encode
1425  // it as Rn (for multiply, that's in the same offset as RdLo.
1426  if (MCID.getNumOperands() > OpIdx &&
1427      !MCID.OpInfo[OpIdx].isPredicate() &&
1428      !MCID.OpInfo[OpIdx].isOptionalDef())
1429    Binary |= getMachineOpValue(MI, OpIdx) << ARMII::RegRdLoShift;
1430
1431  emitWordLE(Binary);
1432}
1433
1434void ARMCodeEmitter::emitExtendInstruction(const MachineInstr &MI) {
1435  const MCInstrDesc &MCID = MI.getDesc();
1436
1437  // Part of binary is determined by TableGn.
1438  unsigned Binary = getBinaryCodeForInstr(MI);
1439
1440  // Set the conditional execution predicate
1441  Binary |= II->getPredicate(&MI) << ARMII::CondShift;
1442
1443  unsigned OpIdx = 0;
1444
1445  // Encode Rd
1446  Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRdShift;
1447
1448  const MachineOperand &MO1 = MI.getOperand(OpIdx++);
1449  const MachineOperand &MO2 = MI.getOperand(OpIdx);
1450  if (MO2.isReg()) {
1451    // Two register operand form.
1452    // Encode Rn.
1453    Binary |= getMachineOpValue(MI, MO1) << ARMII::RegRnShift;
1454
1455    // Encode Rm.
1456    Binary |= getMachineOpValue(MI, MO2);
1457    ++OpIdx;
1458  } else {
1459    Binary |= getMachineOpValue(MI, MO1);
1460  }
1461
1462  // Encode rot imm (0, 8, 16, or 24) if it has a rotate immediate operand.
1463  if (MI.getOperand(OpIdx).isImm() &&
1464      !MCID.OpInfo[OpIdx].isPredicate() &&
1465      !MCID.OpInfo[OpIdx].isOptionalDef())
1466    Binary |= (getMachineOpValue(MI, OpIdx) / 8) << ARMII::ExtRotImmShift;
1467
1468  emitWordLE(Binary);
1469}
1470
1471void ARMCodeEmitter::emitMiscArithInstruction(const MachineInstr &MI) {
1472  const MCInstrDesc &MCID = MI.getDesc();
1473
1474  // Part of binary is determined by TableGn.
1475  unsigned Binary = getBinaryCodeForInstr(MI);
1476
1477  // Set the conditional execution predicate
1478  Binary |= II->getPredicate(&MI) << ARMII::CondShift;
1479
1480  // PKH instructions are finished at this point
1481  if (MCID.Opcode == ARM::PKHBT || MCID.Opcode == ARM::PKHTB) {
1482    emitWordLE(Binary);
1483    return;
1484  }
1485
1486  unsigned OpIdx = 0;
1487
1488  // Encode Rd
1489  Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRdShift;
1490
1491  const MachineOperand &MO = MI.getOperand(OpIdx++);
1492  if (OpIdx == MCID.getNumOperands() ||
1493      MCID.OpInfo[OpIdx].isPredicate() ||
1494      MCID.OpInfo[OpIdx].isOptionalDef()) {
1495    // Encode Rm and it's done.
1496    Binary |= getMachineOpValue(MI, MO);
1497    emitWordLE(Binary);
1498    return;
1499  }
1500
1501  // Encode Rn.
1502  Binary |= getMachineOpValue(MI, MO) << ARMII::RegRnShift;
1503
1504  // Encode Rm.
1505  Binary |= getMachineOpValue(MI, OpIdx++);
1506
1507  // Encode shift_imm.
1508  unsigned ShiftAmt = MI.getOperand(OpIdx).getImm();
1509  if (MCID.Opcode == ARM::PKHTB) {
1510    assert(ShiftAmt != 0 && "PKHTB shift_imm is 0!");
1511    if (ShiftAmt == 32)
1512      ShiftAmt = 0;
1513  }
1514  assert(ShiftAmt < 32 && "shift_imm range is 0 to 31!");
1515  Binary |= ShiftAmt << ARMII::ShiftShift;
1516
1517  emitWordLE(Binary);
1518}
1519
1520void ARMCodeEmitter::emitSaturateInstruction(const MachineInstr &MI) {
1521  const MCInstrDesc &MCID = MI.getDesc();
1522
1523  // Part of binary is determined by TableGen.
1524  unsigned Binary = getBinaryCodeForInstr(MI);
1525
1526  // Set the conditional execution predicate
1527  Binary |= II->getPredicate(&MI) << ARMII::CondShift;
1528
1529  // Encode Rd
1530  Binary |= getMachineOpValue(MI, 0) << ARMII::RegRdShift;
1531
1532  // Encode saturate bit position.
1533  unsigned Pos = MI.getOperand(1).getImm();
1534  if (MCID.Opcode == ARM::SSAT || MCID.Opcode == ARM::SSAT16)
1535    Pos -= 1;
1536  assert((Pos < 16 || (Pos < 32 &&
1537                       MCID.Opcode != ARM::SSAT16 &&
1538                       MCID.Opcode != ARM::USAT16)) &&
1539         "saturate bit position out of range");
1540  Binary |= Pos << 16;
1541
1542  // Encode Rm
1543  Binary |= getMachineOpValue(MI, 2);
1544
1545  // Encode shift_imm.
1546  if (MCID.getNumOperands() == 4) {
1547    unsigned ShiftOp = MI.getOperand(3).getImm();
1548    ARM_AM::ShiftOpc Opc = ARM_AM::getSORegShOp(ShiftOp);
1549    if (Opc == ARM_AM::asr)
1550      Binary |= (1 << 6);
1551    unsigned ShiftAmt = MI.getOperand(3).getImm();
1552    if (ShiftAmt == 32 && Opc == ARM_AM::asr)
1553      ShiftAmt = 0;
1554    assert(ShiftAmt < 32 && "shift_imm range is 0 to 31!");
1555    Binary |= ShiftAmt << ARMII::ShiftShift;
1556  }
1557
1558  emitWordLE(Binary);
1559}
1560
1561void ARMCodeEmitter::emitBranchInstruction(const MachineInstr &MI) {
1562  const MCInstrDesc &MCID = MI.getDesc();
1563
1564  if (MCID.Opcode == ARM::TPsoft) {
1565    llvm_unreachable("ARM::TPsoft FIXME"); // FIXME
1566  }
1567
1568  // Part of binary is determined by TableGn.
1569  unsigned Binary = getBinaryCodeForInstr(MI);
1570
1571  if (MCID.Opcode == ARM::B) {
1572    Binary = 0xEA000000;
1573  }
1574
1575  // Set the conditional execution predicate
1576  Binary |= II->getPredicate(&MI) << ARMII::CondShift;
1577
1578  // Set signed_immed_24 field
1579  Binary |= getMachineOpValue(MI, 0);
1580
1581  emitWordLE(Binary);
1582}
1583
1584void ARMCodeEmitter::emitInlineJumpTable(unsigned JTIndex) {
1585  // Remember the base address of the inline jump table.
1586  uintptr_t JTBase = MCE.getCurrentPCValue();
1587  JTI->addJumpTableBaseAddr(JTIndex, JTBase);
1588  DEBUG(errs() << "  ** Jump Table #" << JTIndex << " @ " << (void*)JTBase
1589               << '\n');
1590
1591  // Now emit the jump table entries.
1592  const std::vector<MachineBasicBlock*> &MBBs = (*MJTEs)[JTIndex].MBBs;
1593  for (unsigned i = 0, e = MBBs.size(); i != e; ++i) {
1594    if (IsPIC)
1595      // DestBB address - JT base.
1596      emitMachineBasicBlock(MBBs[i], ARM::reloc_arm_pic_jt, JTBase);
1597    else
1598      // Absolute DestBB address.
1599      emitMachineBasicBlock(MBBs[i], ARM::reloc_arm_absolute);
1600    emitWordLE(0);
1601  }
1602}
1603
1604void ARMCodeEmitter::emitMiscBranchInstruction(const MachineInstr &MI) {
1605  const MCInstrDesc &MCID = MI.getDesc();
1606
1607  // Handle jump tables.
1608  if (MCID.Opcode == ARM::BR_JTr || MCID.Opcode == ARM::BR_JTadd) {
1609    // First emit a ldr pc, [] instruction.
1610    emitDataProcessingInstruction(MI, ARM::PC);
1611
1612    // Then emit the inline jump table.
1613    unsigned JTIndex =
1614      (MCID.Opcode == ARM::BR_JTr)
1615      ? MI.getOperand(1).getIndex() : MI.getOperand(2).getIndex();
1616    emitInlineJumpTable(JTIndex);
1617    return;
1618  } else if (MCID.Opcode == ARM::BR_JTm) {
1619    // First emit a ldr pc, [] instruction.
1620    emitLoadStoreInstruction(MI, ARM::PC);
1621
1622    // Then emit the inline jump table.
1623    emitInlineJumpTable(MI.getOperand(3).getIndex());
1624    return;
1625  }
1626
1627  // Part of binary is determined by TableGn.
1628  unsigned Binary = getBinaryCodeForInstr(MI);
1629
1630  // Set the conditional execution predicate
1631  Binary |= II->getPredicate(&MI) << ARMII::CondShift;
1632
1633  if (MCID.Opcode == ARM::BX_RET || MCID.Opcode == ARM::MOVPCLR)
1634    // The return register is LR.
1635    Binary |= getARMRegisterNumbering(ARM::LR);
1636  else
1637    // otherwise, set the return register
1638    Binary |= getMachineOpValue(MI, 0);
1639
1640  emitWordLE(Binary);
1641}
1642
1643static unsigned encodeVFPRd(const MachineInstr &MI, unsigned OpIdx) {
1644  unsigned RegD = MI.getOperand(OpIdx).getReg();
1645  unsigned Binary = 0;
1646  bool isSPVFP = ARM::SPRRegClass.contains(RegD);
1647  RegD = getARMRegisterNumbering(RegD);
1648  if (!isSPVFP) {
1649    Binary |=  (RegD & 0x0F)       << ARMII::RegRdShift;
1650    Binary |= ((RegD & 0x10) >> 4) << ARMII::D_BitShift;
1651  } else {
1652    Binary |= ((RegD & 0x1E) >> 1) << ARMII::RegRdShift;
1653    Binary |=  (RegD & 0x01)       << ARMII::D_BitShift;
1654  }
1655  return Binary;
1656}
1657
1658static unsigned encodeVFPRn(const MachineInstr &MI, unsigned OpIdx) {
1659  unsigned RegN = MI.getOperand(OpIdx).getReg();
1660  unsigned Binary = 0;
1661  bool isSPVFP = ARM::SPRRegClass.contains(RegN);
1662  RegN = getARMRegisterNumbering(RegN);
1663  if (!isSPVFP) {
1664    Binary |=  (RegN & 0x0F)       << ARMII::RegRnShift;
1665    Binary |= ((RegN & 0x10) >> 4) << ARMII::N_BitShift;
1666  } else {
1667    Binary |= ((RegN & 0x1E) >> 1) << ARMII::RegRnShift;
1668    Binary |=  (RegN & 0x01)       << ARMII::N_BitShift;
1669  }
1670  return Binary;
1671}
1672
1673static unsigned encodeVFPRm(const MachineInstr &MI, unsigned OpIdx) {
1674  unsigned RegM = MI.getOperand(OpIdx).getReg();
1675  unsigned Binary = 0;
1676  bool isSPVFP = ARM::SPRRegClass.contains(RegM);
1677  RegM = getARMRegisterNumbering(RegM);
1678  if (!isSPVFP) {
1679    Binary |=  (RegM & 0x0F);
1680    Binary |= ((RegM & 0x10) >> 4) << ARMII::M_BitShift;
1681  } else {
1682    Binary |= ((RegM & 0x1E) >> 1);
1683    Binary |=  (RegM & 0x01)       << ARMII::M_BitShift;
1684  }
1685  return Binary;
1686}
1687
1688void ARMCodeEmitter::emitVFPArithInstruction(const MachineInstr &MI) {
1689  const MCInstrDesc &MCID = MI.getDesc();
1690
1691  // Part of binary is determined by TableGn.
1692  unsigned Binary = getBinaryCodeForInstr(MI);
1693
1694  // Set the conditional execution predicate
1695  Binary |= II->getPredicate(&MI) << ARMII::CondShift;
1696
1697  unsigned OpIdx = 0;
1698
1699  // Encode Dd / Sd.
1700  Binary |= encodeVFPRd(MI, OpIdx++);
1701
1702  // If this is a two-address operand, skip it, e.g. FMACD.
1703  if (MCID.getOperandConstraint(OpIdx, MCOI::TIED_TO) != -1)
1704    ++OpIdx;
1705
1706  // Encode Dn / Sn.
1707  if ((MCID.TSFlags & ARMII::FormMask) == ARMII::VFPBinaryFrm)
1708    Binary |= encodeVFPRn(MI, OpIdx++);
1709
1710  if (OpIdx == MCID.getNumOperands() ||
1711      MCID.OpInfo[OpIdx].isPredicate() ||
1712      MCID.OpInfo[OpIdx].isOptionalDef()) {
1713    // FCMPEZD etc. has only one operand.
1714    emitWordLE(Binary);
1715    return;
1716  }
1717
1718  // Encode Dm / Sm.
1719  Binary |= encodeVFPRm(MI, OpIdx);
1720
1721  emitWordLE(Binary);
1722}
1723
1724void ARMCodeEmitter::emitVFPConversionInstruction(const MachineInstr &MI) {
1725  const MCInstrDesc &MCID = MI.getDesc();
1726  unsigned Form = MCID.TSFlags & ARMII::FormMask;
1727
1728  // Part of binary is determined by TableGn.
1729  unsigned Binary = getBinaryCodeForInstr(MI);
1730
1731  // Set the conditional execution predicate
1732  Binary |= II->getPredicate(&MI) << ARMII::CondShift;
1733
1734  switch (Form) {
1735  default: break;
1736  case ARMII::VFPConv1Frm:
1737  case ARMII::VFPConv2Frm:
1738  case ARMII::VFPConv3Frm:
1739    // Encode Dd / Sd.
1740    Binary |= encodeVFPRd(MI, 0);
1741    break;
1742  case ARMII::VFPConv4Frm:
1743    // Encode Dn / Sn.
1744    Binary |= encodeVFPRn(MI, 0);
1745    break;
1746  case ARMII::VFPConv5Frm:
1747    // Encode Dm / Sm.
1748    Binary |= encodeVFPRm(MI, 0);
1749    break;
1750  }
1751
1752  switch (Form) {
1753  default: break;
1754  case ARMII::VFPConv1Frm:
1755    // Encode Dm / Sm.
1756    Binary |= encodeVFPRm(MI, 1);
1757    break;
1758  case ARMII::VFPConv2Frm:
1759  case ARMII::VFPConv3Frm:
1760    // Encode Dn / Sn.
1761    Binary |= encodeVFPRn(MI, 1);
1762    break;
1763  case ARMII::VFPConv4Frm:
1764  case ARMII::VFPConv5Frm:
1765    // Encode Dd / Sd.
1766    Binary |= encodeVFPRd(MI, 1);
1767    break;
1768  }
1769
1770  if (Form == ARMII::VFPConv5Frm)
1771    // Encode Dn / Sn.
1772    Binary |= encodeVFPRn(MI, 2);
1773  else if (Form == ARMII::VFPConv3Frm)
1774    // Encode Dm / Sm.
1775    Binary |= encodeVFPRm(MI, 2);
1776
1777  emitWordLE(Binary);
1778}
1779
1780void ARMCodeEmitter::emitVFPLoadStoreInstruction(const MachineInstr &MI) {
1781  // Part of binary is determined by TableGn.
1782  unsigned Binary = getBinaryCodeForInstr(MI);
1783
1784  // Set the conditional execution predicate
1785  Binary |= II->getPredicate(&MI) << ARMII::CondShift;
1786
1787  if (MI.getOpcode() == ARM::VLDRS || MI.getOpcode() == ARM::VLDRD ||
1788      MI.getOpcode() == ARM::VSTRS || MI.getOpcode() == ARM::VSTRD){
1789    emitWordLE(Binary);
1790    return;
1791  }
1792
1793  unsigned OpIdx = 0;
1794
1795  // Encode Dd / Sd.
1796  Binary |= encodeVFPRd(MI, OpIdx++);
1797
1798  // Encode address base.
1799  const MachineOperand &Base = MI.getOperand(OpIdx++);
1800  Binary |= getMachineOpValue(MI, Base) << ARMII::RegRnShift;
1801
1802  // If there is a non-zero immediate offset, encode it.
1803  if (Base.isReg()) {
1804    const MachineOperand &Offset = MI.getOperand(OpIdx);
1805    if (unsigned ImmOffs = ARM_AM::getAM5Offset(Offset.getImm())) {
1806      if (ARM_AM::getAM5Op(Offset.getImm()) == ARM_AM::add)
1807        Binary |= 1 << ARMII::U_BitShift;
1808      Binary |= ImmOffs;
1809      emitWordLE(Binary);
1810      return;
1811    }
1812  }
1813
1814  // If immediate offset is omitted, default to +0.
1815  Binary |= 1 << ARMII::U_BitShift;
1816
1817  emitWordLE(Binary);
1818}
1819
1820void
1821ARMCodeEmitter::emitVFPLoadStoreMultipleInstruction(const MachineInstr &MI) {
1822  const MCInstrDesc &MCID = MI.getDesc();
1823  bool IsUpdating = (MCID.TSFlags & ARMII::IndexModeMask) != 0;
1824
1825  // Part of binary is determined by TableGn.
1826  unsigned Binary = getBinaryCodeForInstr(MI);
1827
1828  // Set the conditional execution predicate
1829  Binary |= II->getPredicate(&MI) << ARMII::CondShift;
1830
1831  // Skip operand 0 of an instruction with base register update.
1832  unsigned OpIdx = 0;
1833  if (IsUpdating)
1834    ++OpIdx;
1835
1836  // Set base address operand
1837  Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRnShift;
1838
1839  // Set addressing mode by modifying bits U(23) and P(24)
1840  ARM_AM::AMSubMode Mode = ARM_AM::getLoadStoreMultipleSubMode(MI.getOpcode());
1841  Binary |= getAddrModeUPBits(ARM_AM::getAM4SubMode(Mode));
1842
1843  // Set bit W(21)
1844  if (IsUpdating)
1845    Binary |= 0x1 << ARMII::W_BitShift;
1846
1847  // First register is encoded in Dd.
1848  Binary |= encodeVFPRd(MI, OpIdx+2);
1849
1850  // Count the number of registers.
1851  unsigned NumRegs = 1;
1852  for (unsigned i = OpIdx+3, e = MI.getNumOperands(); i != e; ++i) {
1853    const MachineOperand &MO = MI.getOperand(i);
1854    if (!MO.isReg() || MO.isImplicit())
1855      break;
1856    ++NumRegs;
1857  }
1858  // Bit 8 will be set if <list> is consecutive 64-bit registers (e.g., D0)
1859  // Otherwise, it will be 0, in the case of 32-bit registers.
1860  if(Binary & 0x100)
1861    Binary |= NumRegs * 2;
1862  else
1863    Binary |= NumRegs;
1864
1865  emitWordLE(Binary);
1866}
1867
1868void ARMCodeEmitter::emitMiscInstruction(const MachineInstr &MI) {
1869  unsigned Opcode = MI.getDesc().Opcode;
1870  // Part of binary is determined by TableGn.
1871  unsigned Binary = getBinaryCodeForInstr(MI);
1872
1873  if (Opcode == ARM::FCONSTS) {
1874    unsigned Imm = getMachineOpValue(MI, 1);
1875    Binary &= ~(0x780000 >> 19);
1876    Binary |= (Imm & 0x780000) >> 19;
1877    Binary &= ~(0x3800000 >> 7);
1878    Binary |= (Imm & 0x3800000) >> 7;
1879    Binary = VFPThumb2PostEncoder(MI, Binary);
1880  }
1881
1882  // Set the conditional execution predicate
1883  Binary |= II->getPredicate(&MI) << ARMII::CondShift;
1884
1885  emitWordLE(Binary);
1886}
1887
1888static unsigned encodeNEONRd(const MachineInstr &MI, unsigned OpIdx) {
1889  unsigned RegD = MI.getOperand(OpIdx).getReg();
1890  unsigned Binary = 0;
1891  RegD = getARMRegisterNumbering(RegD);
1892  Binary |= (RegD & 0xf) << ARMII::RegRdShift;
1893  Binary |= ((RegD >> 4) & 1) << ARMII::D_BitShift;
1894  return Binary;
1895}
1896
1897static unsigned encodeNEONRn(const MachineInstr &MI, unsigned OpIdx) {
1898  unsigned RegN = MI.getOperand(OpIdx).getReg();
1899  unsigned Binary = 0;
1900  RegN = getARMRegisterNumbering(RegN);
1901  Binary |= (RegN & 0xf) << ARMII::RegRnShift;
1902  Binary |= ((RegN >> 4) & 1) << ARMII::N_BitShift;
1903  return Binary;
1904}
1905
1906static unsigned encodeNEONRm(const MachineInstr &MI, unsigned OpIdx) {
1907  unsigned RegM = MI.getOperand(OpIdx).getReg();
1908  unsigned Binary = 0;
1909  RegM = getARMRegisterNumbering(RegM);
1910  Binary |= (RegM & 0xf);
1911  Binary |= ((RegM >> 4) & 1) << ARMII::M_BitShift;
1912  return Binary;
1913}
1914
1915/// convertNEONDataProcToThumb - Convert the ARM mode encoding for a NEON
1916/// data-processing instruction to the corresponding Thumb encoding.
1917static unsigned convertNEONDataProcToThumb(unsigned Binary) {
1918  assert((Binary & 0xfe000000) == 0xf2000000 &&
1919         "not an ARM NEON data-processing instruction");
1920  unsigned UBit = (Binary >> 24) & 1;
1921  return 0xef000000 | (UBit << 28) | (Binary & 0xffffff);
1922}
1923
1924void ARMCodeEmitter::emitNEONLaneInstruction(const MachineInstr &MI) {
1925  unsigned Binary = getBinaryCodeForInstr(MI);
1926
1927  unsigned RegTOpIdx, RegNOpIdx, LnOpIdx;
1928  const MCInstrDesc &MCID = MI.getDesc();
1929  if ((MCID.TSFlags & ARMII::FormMask) == ARMII::NGetLnFrm) {
1930    RegTOpIdx = 0;
1931    RegNOpIdx = 1;
1932    LnOpIdx = 2;
1933  } else { // ARMII::NSetLnFrm
1934    RegTOpIdx = 2;
1935    RegNOpIdx = 0;
1936    LnOpIdx = 3;
1937  }
1938
1939  // Set the conditional execution predicate
1940  Binary |= (IsThumb ? ARMCC::AL : II->getPredicate(&MI)) << ARMII::CondShift;
1941
1942  unsigned RegT = MI.getOperand(RegTOpIdx).getReg();
1943  RegT = getARMRegisterNumbering(RegT);
1944  Binary |= (RegT << ARMII::RegRdShift);
1945  Binary |= encodeNEONRn(MI, RegNOpIdx);
1946
1947  unsigned LaneShift;
1948  if ((Binary & (1 << 22)) != 0)
1949    LaneShift = 0; // 8-bit elements
1950  else if ((Binary & (1 << 5)) != 0)
1951    LaneShift = 1; // 16-bit elements
1952  else
1953    LaneShift = 2; // 32-bit elements
1954
1955  unsigned Lane = MI.getOperand(LnOpIdx).getImm() << LaneShift;
1956  unsigned Opc1 = Lane >> 2;
1957  unsigned Opc2 = Lane & 3;
1958  assert((Opc1 & 3) == 0 && "out-of-range lane number operand");
1959  Binary |= (Opc1 << 21);
1960  Binary |= (Opc2 << 5);
1961
1962  emitWordLE(Binary);
1963}
1964
1965void ARMCodeEmitter::emitNEONDupInstruction(const MachineInstr &MI) {
1966  unsigned Binary = getBinaryCodeForInstr(MI);
1967
1968  // Set the conditional execution predicate
1969  Binary |= (IsThumb ? ARMCC::AL : II->getPredicate(&MI)) << ARMII::CondShift;
1970
1971  unsigned RegT = MI.getOperand(1).getReg();
1972  RegT = getARMRegisterNumbering(RegT);
1973  Binary |= (RegT << ARMII::RegRdShift);
1974  Binary |= encodeNEONRn(MI, 0);
1975  emitWordLE(Binary);
1976}
1977
1978void ARMCodeEmitter::emitNEON1RegModImmInstruction(const MachineInstr &MI) {
1979  unsigned Binary = getBinaryCodeForInstr(MI);
1980  // Destination register is encoded in Dd.
1981  Binary |= encodeNEONRd(MI, 0);
1982  // Immediate fields: Op, Cmode, I, Imm3, Imm4
1983  unsigned Imm = MI.getOperand(1).getImm();
1984  unsigned Op = (Imm >> 12) & 1;
1985  unsigned Cmode = (Imm >> 8) & 0xf;
1986  unsigned I = (Imm >> 7) & 1;
1987  unsigned Imm3 = (Imm >> 4) & 0x7;
1988  unsigned Imm4 = Imm & 0xf;
1989  Binary |= (I << 24) | (Imm3 << 16) | (Cmode << 8) | (Op << 5) | Imm4;
1990  if (IsThumb)
1991    Binary = convertNEONDataProcToThumb(Binary);
1992  emitWordLE(Binary);
1993}
1994
1995void ARMCodeEmitter::emitNEON2RegInstruction(const MachineInstr &MI) {
1996  const MCInstrDesc &MCID = MI.getDesc();
1997  unsigned Binary = getBinaryCodeForInstr(MI);
1998  // Destination register is encoded in Dd; source register in Dm.
1999  unsigned OpIdx = 0;
2000  Binary |= encodeNEONRd(MI, OpIdx++);
2001  if (MCID.getOperandConstraint(OpIdx, MCOI::TIED_TO) != -1)
2002    ++OpIdx;
2003  Binary |= encodeNEONRm(MI, OpIdx);
2004  if (IsThumb)
2005    Binary = convertNEONDataProcToThumb(Binary);
2006  // FIXME: This does not handle VDUPfdf or VDUPfqf.
2007  emitWordLE(Binary);
2008}
2009
2010void ARMCodeEmitter::emitNEON3RegInstruction(const MachineInstr &MI) {
2011  const MCInstrDesc &MCID = MI.getDesc();
2012  unsigned Binary = getBinaryCodeForInstr(MI);
2013  // Destination register is encoded in Dd; source registers in Dn and Dm.
2014  unsigned OpIdx = 0;
2015  Binary |= encodeNEONRd(MI, OpIdx++);
2016  if (MCID.getOperandConstraint(OpIdx, MCOI::TIED_TO) != -1)
2017    ++OpIdx;
2018  Binary |= encodeNEONRn(MI, OpIdx++);
2019  if (MCID.getOperandConstraint(OpIdx, MCOI::TIED_TO) != -1)
2020    ++OpIdx;
2021  Binary |= encodeNEONRm(MI, OpIdx);
2022  if (IsThumb)
2023    Binary = convertNEONDataProcToThumb(Binary);
2024  // FIXME: This does not handle VMOVDneon or VMOVQ.
2025  emitWordLE(Binary);
2026}
2027
2028#include "ARMGenCodeEmitter.inc"
2029