ARMCodeEmitter.cpp revision c41fb3151784f7fccb4731ef594c4ea3dc685d5f 
1//===-- ARM/ARMCodeEmitter.cpp - Convert ARM code to machine code ---------===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file contains the pass that transforms the ARM machine instructions into
11// relocatable machine code.
12//
13//===----------------------------------------------------------------------===//
14
15#define DEBUG_TYPE "jit"
16#include "ARM.h"
17#include "ARMAddressingModes.h"
18#include "ARMConstantPoolValue.h"
19#include "ARMInstrInfo.h"
20#include "ARMRelocations.h"
21#include "ARMSubtarget.h"
22#include "ARMTargetMachine.h"
23#include "llvm/Constants.h"
24#include "llvm/DerivedTypes.h"
25#include "llvm/Function.h"
26#include "llvm/PassManager.h"
27#include "llvm/CodeGen/MachineCodeEmitter.h"
28#include "llvm/CodeGen/MachineConstantPool.h"
29#include "llvm/CodeGen/MachineFunctionPass.h"
30#include "llvm/CodeGen/MachineInstr.h"
31#include "llvm/CodeGen/Passes.h"
32#include "llvm/ADT/Statistic.h"
33#include "llvm/Support/Compiler.h"
34#include "llvm/Support/Debug.h"
35using namespace llvm;
36
37STATISTIC(NumEmitted, "Number of machine instructions emitted");
38
39namespace {
40  class VISIBILITY_HIDDEN ARMCodeEmitter : public MachineFunctionPass {
41    ARMJITInfo                *JTI;
42    const ARMInstrInfo        *II;
43    const TargetData          *TD;
44    TargetMachine             &TM;
45    MachineCodeEmitter        &MCE;
46    const std::vector<MachineConstantPoolEntry> *MCPEs;
47
48  public:
49    static char ID;
50    explicit ARMCodeEmitter(TargetMachine &tm, MachineCodeEmitter &mce)
51      : MachineFunctionPass(&ID), JTI(0), II(0), TD(0), TM(tm),
52      MCE(mce), MCPEs(0) {}
53    ARMCodeEmitter(TargetMachine &tm, MachineCodeEmitter &mce,
54            const ARMInstrInfo &ii, const TargetData &td)
55      : MachineFunctionPass(&ID), JTI(0), II(&ii), TD(&td), TM(tm),
56      MCE(mce), MCPEs(0) {}
57
58    bool runOnMachineFunction(MachineFunction &MF);
59
60    virtual const char *getPassName() const {
61      return "ARM Machine Code Emitter";
62    }
63
64    void emitInstruction(const MachineInstr &MI);
65
66  private:
67
68    void emitWordLE(unsigned Binary);
69
70    void emitConstPoolInstruction(const MachineInstr &MI);
71
72    void addPCLabel(unsigned LabelID);
73
74    void emitPseudoInstruction(const MachineInstr &MI);
75
76    unsigned getMachineSoRegOpValue(const MachineInstr &MI,
77                                    const TargetInstrDesc &TID,
78                                    const MachineOperand &MO,
79                                    unsigned OpIdx);
80
81    unsigned getMachineSoImmOpValue(const MachineInstr &MI,
82                                    const TargetInstrDesc &TID,
83                                    const MachineOperand &MO);
84
85    unsigned getAddrModeSBit(const MachineInstr &MI,
86                             const TargetInstrDesc &TID) const;
87
88    void emitDataProcessingInstruction(const MachineInstr &MI,
89                                       unsigned ImplicitRn = 0);
90
91    void emitLoadStoreInstruction(const MachineInstr &MI,
92                                  unsigned ImplicitRn = 0);
93
94    void emitMiscLoadStoreInstruction(const MachineInstr &MI,
95                                      unsigned ImplicitRn = 0);
96
97    void emitLoadStoreMultipleInstruction(const MachineInstr &MI);
98
99    void emitMulFrm1Instruction(const MachineInstr &MI);
100
101    void emitBranchInstruction(const MachineInstr &MI);
102
103    void emitMiscBranchInstruction(const MachineInstr &MI);
104
105    /// getBinaryCodeForInstr - This function, generated by the
106    /// CodeEmitterGenerator using TableGen, produces the binary encoding for
107    /// machine instructions.
108    ///
109    unsigned getBinaryCodeForInstr(const MachineInstr &MI);
110
111    /// getMachineOpValue - Return binary encoding of operand. If the machine
112    /// operand requires relocation, record the relocation and return zero.
113    unsigned getMachineOpValue(const MachineInstr &MI,const MachineOperand &MO);
114    unsigned getMachineOpValue(const MachineInstr &MI, unsigned OpIdx) {
115      return getMachineOpValue(MI, MI.getOperand(OpIdx));
116    }
117
118    /// getBaseOpcodeFor - Return the opcode value.
119    ///
120    unsigned getBaseOpcodeFor(const TargetInstrDesc &TID) const {
121      return (TID.TSFlags & ARMII::OpcodeMask) >> ARMII::OpcodeShift;
122    }
123
124    /// getShiftOp - Return the shift opcode (bit[6:5]) of the immediate value.
125    ///
126    unsigned getShiftOp(unsigned Imm) const ;
127
128    /// Routines that handle operands which add machine relocations which are
129    /// fixed up by the JIT fixup stage.
130    void emitGlobalAddress(GlobalValue *GV, unsigned Reloc,
131                           bool NeedStub);
132    void emitExternalSymbolAddress(const char *ES, unsigned Reloc);
133    void emitConstPoolAddress(unsigned CPI, unsigned Reloc,
134                              int Disp = 0, unsigned PCAdj = 0 );
135    void emitJumpTableAddress(unsigned JTIndex, unsigned Reloc,
136                              unsigned PCAdj = 0);
137    void emitGlobalConstant(const Constant *CV);
138    void emitMachineBasicBlock(MachineBasicBlock *BB);
139  };
140  char ARMCodeEmitter::ID = 0;
141}
142
143/// createARMCodeEmitterPass - Return a pass that emits the collected ARM code
144/// to the specified MCE object.
145FunctionPass *llvm::createARMCodeEmitterPass(ARMTargetMachine &TM,
146                                             MachineCodeEmitter &MCE) {
147  return new ARMCodeEmitter(TM, MCE);
148}
149
150bool ARMCodeEmitter::runOnMachineFunction(MachineFunction &MF) {
151  assert((MF.getTarget().getRelocationModel() != Reloc::Default ||
152          MF.getTarget().getRelocationModel() != Reloc::Static) &&
153         "JIT relocation model must be set to static or default!");
154  II = ((ARMTargetMachine&)MF.getTarget()).getInstrInfo();
155  TD = ((ARMTargetMachine&)MF.getTarget()).getTargetData();
156  JTI = ((ARMTargetMachine&)MF.getTarget()).getJITInfo();
157  MCPEs = &MF.getConstantPool()->getConstants();
158  JTI->Initialize(MCPEs);
159
160  do {
161    DOUT << "JITTing function '" << MF.getFunction()->getName() << "'\n";
162    MCE.startFunction(MF);
163    for (MachineFunction::iterator MBB = MF.begin(), E = MF.end();
164         MBB != E; ++MBB) {
165      MCE.StartMachineBasicBlock(MBB);
166      for (MachineBasicBlock::const_iterator I = MBB->begin(), E = MBB->end();
167           I != E; ++I)
168        emitInstruction(*I);
169    }
170  } while (MCE.finishFunction(MF));
171
172  return false;
173}
174
175/// getShiftOp - Return the shift opcode (bit[6:5]) of the immediate value.
176///
177unsigned ARMCodeEmitter::getShiftOp(unsigned Imm) const {
178  switch (ARM_AM::getAM2ShiftOpc(Imm)) {
179  default: assert(0 && "Unknown shift opc!");
180  case ARM_AM::asr: return 2;
181  case ARM_AM::lsl: return 0;
182  case ARM_AM::lsr: return 1;
183  case ARM_AM::ror:
184  case ARM_AM::rrx: return 3;
185  }
186  return 0;
187}
188
189/// getMachineOpValue - Return binary encoding of operand. If the machine
190/// operand requires relocation, record the relocation and return zero.
191unsigned ARMCodeEmitter::getMachineOpValue(const MachineInstr &MI,
192                                           const MachineOperand &MO) {
193  if (MO.isReg())
194    return ARMRegisterInfo::getRegisterNumbering(MO.getReg());
195  else if (MO.isImm())
196    return static_cast<unsigned>(MO.getImm());
197  else if (MO.isGlobal())
198    emitGlobalAddress(MO.getGlobal(), ARM::reloc_arm_branch, true);
199  else if (MO.isSymbol())
200    emitExternalSymbolAddress(MO.getSymbolName(), ARM::reloc_arm_relative);
201  else if (MO.isCPI())
202    emitConstPoolAddress(MO.getIndex(), ARM::reloc_arm_cp_entry);
203  else if (MO.isJTI())
204    emitJumpTableAddress(MO.getIndex(), ARM::reloc_arm_relative);
205  else if (MO.isMBB())
206    emitMachineBasicBlock(MO.getMBB());
207  else {
208    cerr << "ERROR: Unknown type of MachineOperand: " << MO << "\n";
209    abort();
210  }
211  return 0;
212}
213
214/// emitGlobalAddress - Emit the specified address to the code stream.
215///
216void ARMCodeEmitter::emitGlobalAddress(GlobalValue *GV,
217                                       unsigned Reloc, bool NeedStub) {
218  MCE.addRelocation(MachineRelocation::getGV(MCE.getCurrentPCOffset(),
219                                             Reloc, GV, 0, NeedStub));
220}
221
222/// emitExternalSymbolAddress - Arrange for the address of an external symbol to
223/// be emitted to the current location in the function, and allow it to be PC
224/// relative.
225void ARMCodeEmitter::emitExternalSymbolAddress(const char *ES, unsigned Reloc) {
226  MCE.addRelocation(MachineRelocation::getExtSym(MCE.getCurrentPCOffset(),
227                                                 Reloc, ES));
228}
229
230/// emitConstPoolAddress - Arrange for the address of an constant pool
231/// to be emitted to the current location in the function, and allow it to be PC
232/// relative.
233void ARMCodeEmitter::emitConstPoolAddress(unsigned CPI, unsigned Reloc,
234                                          int Disp /* = 0 */,
235                                          unsigned PCAdj /* = 0 */) {
236  // Tell JIT emitter we'll resolve the address.
237  MCE.addRelocation(MachineRelocation::getConstPool(MCE.getCurrentPCOffset(),
238                                                    Reloc, CPI, PCAdj, true));
239}
240
241/// emitJumpTableAddress - Arrange for the address of a jump table to
242/// be emitted to the current location in the function, and allow it to be PC
243/// relative.
244void ARMCodeEmitter::emitJumpTableAddress(unsigned JTIndex, unsigned Reloc,
245                                          unsigned PCAdj /* = 0 */) {
246  MCE.addRelocation(MachineRelocation::getJumpTable(MCE.getCurrentPCOffset(),
247                                                    Reloc, JTIndex, PCAdj));
248}
249
250/// emitMachineBasicBlock - Emit the specified address basic block.
251void ARMCodeEmitter::emitMachineBasicBlock(MachineBasicBlock *BB) {
252  MCE.addRelocation(MachineRelocation::getBB(MCE.getCurrentPCOffset(),
253                                             ARM::reloc_arm_branch, BB));
254}
255
256void ARMCodeEmitter::emitWordLE(unsigned Binary) {
257  DOUT << "\t" << (void*)Binary << "\n";
258  MCE.emitWordLE(Binary);
259}
260
261void ARMCodeEmitter::emitInstruction(const MachineInstr &MI) {
262  DOUT << "JIT: " << (void*)MCE.getCurrentPCValue() << ":\t" << MI;
263
264  NumEmitted++;  // Keep track of the # of mi's emitted
265  switch (MI.getDesc().TSFlags & ARMII::FormMask) {
266  default:
267    assert(0 && "Unhandled instruction encoding format!");
268    break;
269  case ARMII::Pseudo:
270    emitPseudoInstruction(MI);
271    break;
272  case ARMII::DPFrm:
273  case ARMII::DPSoRegFrm:
274    emitDataProcessingInstruction(MI);
275    break;
276  case ARMII::LdFrm:
277  case ARMII::StFrm:
278    emitLoadStoreInstruction(MI);
279    break;
280  case ARMII::LdMiscFrm:
281  case ARMII::StMiscFrm:
282    emitMiscLoadStoreInstruction(MI);
283    break;
284  case ARMII::LdMulFrm:
285  case ARMII::StMulFrm:
286    emitLoadStoreMultipleInstruction(MI);
287    break;
288  case ARMII::MulFrm1:
289    emitMulFrm1Instruction(MI);
290    break;
291  case ARMII::Branch:
292    emitBranchInstruction(MI);
293    break;
294  case ARMII::BranchMisc:
295    emitMiscBranchInstruction(MI);
296    break;
297  }
298}
299
300void ARMCodeEmitter::emitConstPoolInstruction(const MachineInstr &MI) {
301  unsigned CPI = MI.getOperand(0).getImm();
302  unsigned CPIndex = MI.getOperand(1).getIndex();
303  const MachineConstantPoolEntry &MCPE = (*MCPEs)[CPIndex];
304
305  // Remember the CONSTPOOL_ENTRY address for later relocation.
306  JTI->addConstantPoolEntryAddr(CPI, MCE.getCurrentPCValue());
307
308  // Emit constpool island entry. In most cases, the actual values will be
309  // resolved and relocated after code emission.
310  if (MCPE.isMachineConstantPoolEntry()) {
311    ARMConstantPoolValue *ACPV =
312      static_cast<ARMConstantPoolValue*>(MCPE.Val.MachineCPVal);
313
314    DOUT << "\t** ARM constant pool #" << CPI << " @ "
315         << (void*)MCE.getCurrentPCValue() << " " << *ACPV << "\n";
316
317    GlobalValue *GV = ACPV->getGV();
318    if (GV) {
319      assert(!ACPV->isStub() && "Don't know how to deal this yet!");
320      MCE.addRelocation(MachineRelocation::getGV(MCE.getCurrentPCOffset(),
321                                                ARM::reloc_arm_machine_cp_entry,
322                                                GV, CPIndex, false));
323     } else  {
324      assert(!ACPV->isNonLazyPointer() && "Don't know how to deal this yet!");
325      emitExternalSymbolAddress(ACPV->getSymbol(), ARM::reloc_arm_absolute);
326    }
327    emitWordLE(0);
328  } else {
329    Constant *CV = MCPE.Val.ConstVal;
330
331    DOUT << "\t** Constant pool #" << CPI << " @ "
332         << (void*)MCE.getCurrentPCValue() << " " << *CV << "\n";
333
334    if (GlobalValue *GV = dyn_cast<GlobalValue>(CV)) {
335      emitGlobalAddress(GV, ARM::reloc_arm_absolute, false);
336      emitWordLE(0);
337    } else {
338      assert(CV->getType()->isInteger() &&
339             "Not expecting non-integer constpool entries yet!");
340      const ConstantInt *CI = dyn_cast<ConstantInt>(CV);
341      uint32_t Val = *(uint32_t*)CI->getValue().getRawData();
342      emitWordLE(Val);
343    }
344  }
345}
346
347void ARMCodeEmitter::addPCLabel(unsigned LabelID) {
348  DOUT << "\t** LPC" << LabelID << " @ "
349       << (void*)MCE.getCurrentPCValue() << '\n';
350  JTI->addPCLabelAddr(LabelID, MCE.getCurrentPCValue());
351}
352
353void ARMCodeEmitter::emitPseudoInstruction(const MachineInstr &MI) {
354  unsigned Opcode = MI.getDesc().Opcode;
355  switch (Opcode) {
356  default:
357    abort(); // FIXME:
358  case ARM::CONSTPOOL_ENTRY:
359    emitConstPoolInstruction(MI);
360    break;
361  case ARM::PICADD: {
362    // Remember of the address of the PC label for relocation later.
363    addPCLabel(MI.getOperand(2).getImm());
364    // PICADD is just an add instruction that implicitly read pc.
365    emitDataProcessingInstruction(MI, ARM::PC);
366    break;
367  }
368  case ARM::PICLDR:
369  case ARM::PICLDRB:
370  case ARM::PICSTR:
371  case ARM::PICSTRB: {
372    // Remember of the address of the PC label for relocation later.
373    addPCLabel(MI.getOperand(2).getImm());
374    // These are just load / store instructions that implicitly read pc.
375    emitLoadStoreInstruction(MI, ARM::PC);
376    break;
377  }
378  case ARM::PICLDRH:
379  case ARM::PICLDRSH:
380  case ARM::PICLDRSB:
381  case ARM::PICSTRH: {
382    // Remember of the address of the PC label for relocation later.
383    addPCLabel(MI.getOperand(2).getImm());
384    // These are just load / store instructions that implicitly read pc.
385    emitMiscLoadStoreInstruction(MI, ARM::PC);
386    break;
387  }
388  }
389}
390
391
392unsigned ARMCodeEmitter::getMachineSoRegOpValue(const MachineInstr &MI,
393                                                const TargetInstrDesc &TID,
394                                                const MachineOperand &MO,
395                                                unsigned OpIdx) {
396  unsigned Binary = getMachineOpValue(MI, MO);
397
398  const MachineOperand &MO1 = MI.getOperand(OpIdx + 1);
399  const MachineOperand &MO2 = MI.getOperand(OpIdx + 2);
400  ARM_AM::ShiftOpc SOpc = ARM_AM::getSORegShOp(MO2.getImm());
401
402  // Encode the shift opcode.
403  unsigned SBits = 0;
404  unsigned Rs = MO1.getReg();
405  if (Rs) {
406    // Set shift operand (bit[7:4]).
407    // LSL - 0001
408    // LSR - 0011
409    // ASR - 0101
410    // ROR - 0111
411    // RRX - 0110 and bit[11:8] clear.
412    switch (SOpc) {
413    default: assert(0 && "Unknown shift opc!");
414    case ARM_AM::lsl: SBits = 0x1; break;
415    case ARM_AM::lsr: SBits = 0x3; break;
416    case ARM_AM::asr: SBits = 0x5; break;
417    case ARM_AM::ror: SBits = 0x7; break;
418    case ARM_AM::rrx: SBits = 0x6; break;
419    }
420  } else {
421    // Set shift operand (bit[6:4]).
422    // LSL - 000
423    // LSR - 010
424    // ASR - 100
425    // ROR - 110
426    switch (SOpc) {
427    default: assert(0 && "Unknown shift opc!");
428    case ARM_AM::lsl: SBits = 0x0; break;
429    case ARM_AM::lsr: SBits = 0x2; break;
430    case ARM_AM::asr: SBits = 0x4; break;
431    case ARM_AM::ror: SBits = 0x6; break;
432    }
433  }
434  Binary |= SBits << 4;
435  if (SOpc == ARM_AM::rrx)
436    return Binary;
437
438  // Encode the shift operation Rs or shift_imm (except rrx).
439  if (Rs) {
440    // Encode Rs bit[11:8].
441    assert(ARM_AM::getSORegOffset(MO2.getImm()) == 0);
442    return Binary |
443      (ARMRegisterInfo::getRegisterNumbering(Rs) << ARMII::RegRsShift);
444  }
445
446  // Encode shift_imm bit[11:7].
447  return Binary | ARM_AM::getSORegOffset(MO2.getImm()) << 7;
448}
449
450unsigned ARMCodeEmitter::getMachineSoImmOpValue(const MachineInstr &MI,
451                                                const TargetInstrDesc &TID,
452                                                const MachineOperand &MO) {
453  unsigned SoImm = MO.getImm();
454  // Encode rotate_imm.
455  unsigned Binary = ARM_AM::getSOImmValRot(SoImm) << ARMII::RotImmShift;
456  // Encode immed_8.
457  Binary |= ARM_AM::getSOImmVal(SoImm);
458  return Binary;
459}
460
461unsigned ARMCodeEmitter::getAddrModeSBit(const MachineInstr &MI,
462                                         const TargetInstrDesc &TID) const {
463  for (unsigned i = MI.getNumOperands(), e = TID.getNumOperands(); i != e; --i){
464    const MachineOperand &MO = MI.getOperand(i-1);
465    if (MO.isReg() && MO.isDef() && MO.getReg() == ARM::CPSR)
466      return 1 << ARMII::S_BitShift;
467  }
468  return 0;
469}
470
471void ARMCodeEmitter::emitDataProcessingInstruction(const MachineInstr &MI,
472                                                   unsigned ImplicitRn) {
473  const TargetInstrDesc &TID = MI.getDesc();
474  if (TID.getOpcode() == ARM::MOVi2pieces)
475    abort(); // FIXME
476
477  // Part of binary is determined by TableGn.
478  unsigned Binary = getBinaryCodeForInstr(MI);
479
480  // Set the conditional execution predicate
481  Binary |= II->getPredicate(&MI) << 28;
482
483  // Encode S bit if MI modifies CPSR.
484  Binary |= getAddrModeSBit(MI, TID);
485
486  // Encode register def if there is one.
487  unsigned NumDefs = TID.getNumDefs();
488  unsigned OpIdx = 0;
489  if (NumDefs) {
490    Binary |= getMachineOpValue(MI, OpIdx) << ARMII::RegRdShift;
491    ++OpIdx;
492  }
493
494  // Encode first non-shifter register operand if there is one.
495  bool isUnary = TID.TSFlags & ARMII::UnaryDP;
496  if (!isUnary) {
497    if (ImplicitRn)
498      // Special handling for implicit use (e.g. PC).
499      Binary |= (ARMRegisterInfo::getRegisterNumbering(ImplicitRn)
500                 << ARMII::RegRnShift);
501    else {
502      Binary |= getMachineOpValue(MI, OpIdx) << ARMII::RegRnShift;
503      ++OpIdx;
504    }
505  }
506
507  // Encode shifter operand.
508  const MachineOperand &MO = MI.getOperand(OpIdx);
509  if ((TID.TSFlags & ARMII::FormMask) == ARMII::DPSoRegFrm) {
510    // Encode SoReg.
511    emitWordLE(Binary | getMachineSoRegOpValue(MI, TID, MO, OpIdx));
512    return;
513  }
514
515  if (MO.isReg()) {
516    // Encode register Rm.
517    emitWordLE(Binary | ARMRegisterInfo::getRegisterNumbering(MO.getReg()));
518    return;
519  }
520
521  // Encode so_imm.
522  // Set bit I(25) to identify this is the immediate form of <shifter_op>
523  Binary |= 1 << ARMII::I_BitShift;
524  Binary |= getMachineSoImmOpValue(MI, TID, MO);
525
526  emitWordLE(Binary);
527}
528
529void ARMCodeEmitter::emitLoadStoreInstruction(const MachineInstr &MI,
530                                              unsigned ImplicitRn) {
531  const TargetInstrDesc &TID = MI.getDesc();
532
533  // Part of binary is determined by TableGn.
534  unsigned Binary = getBinaryCodeForInstr(MI);
535
536  // Set the conditional execution predicate
537  Binary |= II->getPredicate(&MI) << 28;
538
539  // Set first operand
540  Binary |= getMachineOpValue(MI, 0) << ARMII::RegRdShift;
541
542  // Set second operand
543  unsigned OpIdx = 1;
544  if (ImplicitRn)
545    // Special handling for implicit use (e.g. PC).
546    Binary |= (ARMRegisterInfo::getRegisterNumbering(ImplicitRn)
547               << ARMII::RegRnShift);
548  else {
549    Binary |= getMachineOpValue(MI, OpIdx) << ARMII::RegRnShift;
550    ++OpIdx;
551  }
552
553  const MachineOperand &MO2 = MI.getOperand(OpIdx);
554  unsigned AM2Opc = (OpIdx == TID.getNumOperands())
555    ? 0 : MI.getOperand(OpIdx+1).getImm();
556
557  // Set bit U(23) according to sign of immed value (positive or negative).
558  Binary |= ((ARM_AM::getAM2Op(AM2Opc) == ARM_AM::add ? 1 : 0) <<
559             ARMII::U_BitShift);
560  if (!MO2.getReg()) { // is immediate
561    if (ARM_AM::getAM2Offset(AM2Opc))
562      // Set the value of offset_12 field
563      Binary |= ARM_AM::getAM2Offset(AM2Opc);
564    emitWordLE(Binary);
565    return;
566  }
567
568  // Set bit I(25), because this is not in immediate enconding.
569  Binary |= 1 << ARMII::I_BitShift;
570  assert(TargetRegisterInfo::isPhysicalRegister(MO2.getReg()));
571  // Set bit[3:0] to the corresponding Rm register
572  Binary |= ARMRegisterInfo::getRegisterNumbering(MO2.getReg());
573
574  // if this instr is in scaled register offset/index instruction, set
575  // shift_immed(bit[11:7]) and shift(bit[6:5]) fields.
576  if (unsigned ShImm = ARM_AM::getAM2Offset(AM2Opc)) {
577    Binary |= getShiftOp(AM2Opc) << 5;  // shift
578    Binary |= ShImm              << 7;  // shift_immed
579  }
580
581  emitWordLE(Binary);
582}
583
584void ARMCodeEmitter::emitMiscLoadStoreInstruction(const MachineInstr &MI,
585                                                  unsigned ImplicitRn) {
586  const TargetInstrDesc &TID = MI.getDesc();
587
588  // Part of binary is determined by TableGn.
589  unsigned Binary = getBinaryCodeForInstr(MI);
590
591  // Set the conditional execution predicate
592  Binary |= II->getPredicate(&MI) << 28;
593
594  // Set first operand
595  Binary |= getMachineOpValue(MI, 0) << ARMII::RegRdShift;
596
597  // Set second operand
598  unsigned OpIdx = 1;
599  if (ImplicitRn)
600    // Special handling for implicit use (e.g. PC).
601    Binary |= (ARMRegisterInfo::getRegisterNumbering(ImplicitRn)
602               << ARMII::RegRnShift);
603  else {
604    Binary |= getMachineOpValue(MI, OpIdx) << ARMII::RegRnShift;
605    ++OpIdx;
606  }
607
608  const MachineOperand &MO2 = MI.getOperand(OpIdx);
609  unsigned AM3Opc = (OpIdx == TID.getNumOperands())
610    ? 0 : MI.getOperand(OpIdx+1).getImm();
611
612  // Set bit U(23) according to sign of immed value (positive or negative)
613  Binary |= ((ARM_AM::getAM3Op(AM3Opc) == ARM_AM::add ? 1 : 0) <<
614             ARMII::U_BitShift);
615
616  // If this instr is in register offset/index encoding, set bit[3:0]
617  // to the corresponding Rm register.
618  if (MO2.getReg()) {
619    Binary |= ARMRegisterInfo::getRegisterNumbering(MO2.getReg());
620    emitWordLE(Binary);
621    return;
622  }
623
624  // if this instr is in immediate offset/index encoding, set bit 22 to 1
625  if (unsigned ImmOffs = ARM_AM::getAM3Offset(AM3Opc)) {
626    Binary |= 1 << 22;
627    // Set operands
628    Binary |= (ImmOffs >> 4) << 8;  // immedH
629    Binary |= (ImmOffs & ~0xF);     // immedL
630  }
631
632  emitWordLE(Binary);
633}
634
635void ARMCodeEmitter::emitLoadStoreMultipleInstruction(const MachineInstr &MI) {
636  // Part of binary is determined by TableGn.
637  unsigned Binary = getBinaryCodeForInstr(MI);
638
639  // Set the conditional execution predicate
640  Binary |= II->getPredicate(&MI) << 28;
641
642  // Set first operand
643  Binary |= getMachineOpValue(MI, 0) << ARMII::RegRnShift;
644
645  // Set addressing mode by modifying bits U(23) and P(24)
646  // IA - Increment after  - bit U = 1 and bit P = 0
647  // IB - Increment before - bit U = 1 and bit P = 1
648  // DA - Decrement after  - bit U = 0 and bit P = 0
649  // DB - Decrement before - bit U = 0 and bit P = 1
650  const MachineOperand &MO = MI.getOperand(1);
651  ARM_AM::AMSubMode Mode = ARM_AM::getAM4SubMode(MO.getImm());
652  switch (Mode) {
653  default: assert(0 && "Unknown addressing sub-mode!");
654  case ARM_AM::da:                      break;
655  case ARM_AM::db: Binary |= 0x1 << 24; break;
656  case ARM_AM::ia: Binary |= 0x1 << 23; break;
657  case ARM_AM::ib: Binary |= 0x3 << 23; break;
658  }
659
660  // Set bit W(21)
661  if (ARM_AM::getAM4WBFlag(MO.getImm()))
662    Binary |= 0x1 << 21;
663
664  // Set registers
665  for (unsigned i = 4, e = MI.getNumOperands(); i != e; ++i) {
666    const MachineOperand &MO = MI.getOperand(i);
667    if (MO.isReg() && MO.isImplicit())
668      continue;
669    unsigned RegNum = ARMRegisterInfo::getRegisterNumbering(MO.getReg());
670    assert(TargetRegisterInfo::isPhysicalRegister(MO.getReg()) &&
671           RegNum < 16);
672    Binary |= 0x1 << RegNum;
673  }
674
675  emitWordLE(Binary);
676}
677
678void ARMCodeEmitter::emitMulFrm1Instruction(const MachineInstr &MI) {
679  const TargetInstrDesc &TID = MI.getDesc();
680
681  // Part of binary is determined by TableGn.
682  unsigned Binary = getBinaryCodeForInstr(MI);
683
684  // Set the conditional execution predicate
685  Binary |= II->getPredicate(&MI) << 28;
686
687  // Encode S bit if MI modifies CPSR.
688  Binary |= getAddrModeSBit(MI, TID);
689
690  // 32x32->64bit operations have two destination registers. The number
691  // of register definitions will tell us if that's what we're dealing with.
692  int OpIdx = 0;
693  if (TID.getNumDefs() == 2)
694    Binary |= getMachineOpValue (MI, OpIdx++) << ARMII::RegRdLoShift;
695
696  // Encode Rd
697  Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRdHiShift;
698
699  // Encode Rm
700  Binary |= getMachineOpValue(MI, OpIdx++);
701
702  // Encode Rs
703  Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRsShift;
704
705  emitWordLE(Binary);
706}
707
708void ARMCodeEmitter::emitBranchInstruction(const MachineInstr &MI) {
709  const TargetInstrDesc &TID = MI.getDesc();
710
711  // Part of binary is determined by TableGn.
712  unsigned Binary = getBinaryCodeForInstr(MI);
713
714  // Set the conditional execution predicate
715  Binary |= II->getPredicate(&MI) << 28;
716
717  // Set signed_immed_24 field
718  Binary |= getMachineOpValue(MI, 0);
719
720  // if it is a conditional branch, set cond field
721  if (TID.Opcode == ARM::Bcc) {
722    Binary &= 0x0FFFFFFF;                      // clear conditional field
723    Binary |= getMachineOpValue(MI, 1) << 28;  // set conditional field
724  }
725
726  emitWordLE(Binary);
727}
728
729void ARMCodeEmitter::emitMiscBranchInstruction(const MachineInstr &MI) {
730  const TargetInstrDesc &TID = MI.getDesc();
731  if (TID.Opcode == ARM::BX)
732    abort(); // FIXME
733
734  // Part of binary is determined by TableGn.
735  unsigned Binary = getBinaryCodeForInstr(MI);
736
737  // Set the conditional execution predicate
738  Binary |= II->getPredicate(&MI) << 28;
739
740  if (TID.Opcode == ARM::BX_RET)
741    // The return register is LR.
742    Binary |= ARMRegisterInfo::getRegisterNumbering(ARM::LR);
743  else
744    // otherwise, set the return register
745    Binary |= getMachineOpValue(MI, 0);
746
747  emitWordLE(Binary);
748}
749
750#include "ARMGenCodeEmitter.inc"
751