ARMCodeEmitter.cpp revision c4bc2111a75dc1ba2383a7021dc95750b3398efe 
1//===-- ARM/ARMCodeEmitter.cpp - Convert ARM code to machine code ---------===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file contains the pass that transforms the ARM machine instructions into
11// relocatable machine code.
12//
13//===----------------------------------------------------------------------===//
14
15#define DEBUG_TYPE "jit"
16#include "ARM.h"
17#include "ARMAddressingModes.h"
18#include "ARMConstantPoolValue.h"
19#include "ARMInstrInfo.h"
20#include "ARMRelocations.h"
21#include "ARMSubtarget.h"
22#include "ARMTargetMachine.h"
23#include "llvm/Constants.h"
24#include "llvm/DerivedTypes.h"
25#include "llvm/Function.h"
26#include "llvm/PassManager.h"
27#include "llvm/CodeGen/JITCodeEmitter.h"
28#include "llvm/CodeGen/MachineConstantPool.h"
29#include "llvm/CodeGen/MachineFunctionPass.h"
30#include "llvm/CodeGen/MachineInstr.h"
31#include "llvm/CodeGen/MachineJumpTableInfo.h"
32#include "llvm/CodeGen/MachineModuleInfo.h"
33#include "llvm/CodeGen/Passes.h"
34#include "llvm/ADT/Statistic.h"
35#include "llvm/Support/Debug.h"
36#include "llvm/Support/ErrorHandling.h"
37#include "llvm/Support/raw_ostream.h"
38#ifndef NDEBUG
39#include <iomanip>
40#endif
41using namespace llvm;
42
43STATISTIC(NumEmitted, "Number of machine instructions emitted");
44
45namespace {
46
47  class ARMCodeEmitter : public MachineFunctionPass {
48    ARMJITInfo                *JTI;
49    const ARMInstrInfo        *II;
50    const TargetData          *TD;
51    const ARMSubtarget        *Subtarget;
52    TargetMachine             &TM;
53    JITCodeEmitter            &MCE;
54    MachineModuleInfo *MMI;
55    const std::vector<MachineConstantPoolEntry> *MCPEs;
56    const std::vector<MachineJumpTableEntry> *MJTEs;
57    bool IsPIC;
58    bool IsThumb;
59
60    void getAnalysisUsage(AnalysisUsage &AU) const {
61      AU.addRequired<MachineModuleInfo>();
62      MachineFunctionPass::getAnalysisUsage(AU);
63    }
64
65    static char ID;
66  public:
67    ARMCodeEmitter(TargetMachine &tm, JITCodeEmitter &mce)
68      : MachineFunctionPass(ID), JTI(0),
69        II((const ARMInstrInfo *)tm.getInstrInfo()),
70        TD(tm.getTargetData()), TM(tm),
71        MCE(mce), MCPEs(0), MJTEs(0),
72        IsPIC(TM.getRelocationModel() == Reloc::PIC_), IsThumb(false) {}
73
74    /// getBinaryCodeForInstr - This function, generated by the
75    /// CodeEmitterGenerator using TableGen, produces the binary encoding for
76    /// machine instructions.
77    unsigned getBinaryCodeForInstr(const MachineInstr &MI) const;
78
79    bool runOnMachineFunction(MachineFunction &MF);
80
81    virtual const char *getPassName() const {
82      return "ARM Machine Code Emitter";
83    }
84
85    void emitInstruction(const MachineInstr &MI);
86
87  private:
88
89    void emitWordLE(unsigned Binary);
90    void emitDWordLE(uint64_t Binary);
91    void emitConstPoolInstruction(const MachineInstr &MI);
92    void emitMOVi32immInstruction(const MachineInstr &MI);
93    void emitMOVi2piecesInstruction(const MachineInstr &MI);
94    void emitLEApcrelJTInstruction(const MachineInstr &MI);
95    void emitPseudoMoveInstruction(const MachineInstr &MI);
96    void addPCLabel(unsigned LabelID);
97    void emitPseudoInstruction(const MachineInstr &MI);
98    unsigned getMachineSoRegOpValue(const MachineInstr &MI,
99                                    const TargetInstrDesc &TID,
100                                    const MachineOperand &MO,
101                                    unsigned OpIdx);
102
103    unsigned getMachineSoImmOpValue(unsigned SoImm);
104
105    unsigned getAddrModeSBit(const MachineInstr &MI,
106                             const TargetInstrDesc &TID) const;
107
108    void emitDataProcessingInstruction(const MachineInstr &MI,
109                                       unsigned ImplicitRd = 0,
110                                       unsigned ImplicitRn = 0);
111
112    void emitLoadStoreInstruction(const MachineInstr &MI,
113                                  unsigned ImplicitRd = 0,
114                                  unsigned ImplicitRn = 0);
115
116    void emitMiscLoadStoreInstruction(const MachineInstr &MI,
117                                      unsigned ImplicitRn = 0);
118
119    void emitLoadStoreMultipleInstruction(const MachineInstr &MI);
120
121    void emitMulFrmInstruction(const MachineInstr &MI);
122
123    void emitExtendInstruction(const MachineInstr &MI);
124
125    void emitMiscArithInstruction(const MachineInstr &MI);
126
127    void emitSaturateInstruction(const MachineInstr &MI);
128
129    void emitBranchInstruction(const MachineInstr &MI);
130
131    void emitInlineJumpTable(unsigned JTIndex);
132
133    void emitMiscBranchInstruction(const MachineInstr &MI);
134
135    void emitVFPArithInstruction(const MachineInstr &MI);
136
137    void emitVFPConversionInstruction(const MachineInstr &MI);
138
139    void emitVFPLoadStoreInstruction(const MachineInstr &MI);
140
141    void emitVFPLoadStoreMultipleInstruction(const MachineInstr &MI);
142
143    void emitNEONLaneInstruction(const MachineInstr &MI);
144    void emitNEONDupInstruction(const MachineInstr &MI);
145    void emitNEON1RegModImmInstruction(const MachineInstr &MI);
146    void emitNEON2RegInstruction(const MachineInstr &MI);
147    void emitNEON3RegInstruction(const MachineInstr &MI);
148
149    /// getMachineOpValue - Return binary encoding of operand. If the machine
150    /// operand requires relocation, record the relocation and return zero.
151    unsigned getMachineOpValue(const MachineInstr &MI,
152                               const MachineOperand &MO) const;
153    unsigned getMachineOpValue(const MachineInstr &MI, unsigned OpIdx) const {
154      return getMachineOpValue(MI, MI.getOperand(OpIdx));
155    }
156
157    // FIXME: The legacy JIT ARMCodeEmitter doesn't rely on the the
158    //  TableGen'erated getBinaryCodeForInstr() function to encode any
159    //  operand values, instead querying getMachineOpValue() directly for
160    //  each operand it needs to encode. Thus, any of the new encoder
161    //  helper functions can simply return 0 as the values the return
162    //  are already handled elsewhere. They are placeholders to allow this
163    //  encoder to continue to function until the MC encoder is sufficiently
164    //  far along that this one can be eliminated entirely.
165    unsigned getCCOutOpValue(const MachineInstr &MI, unsigned Op)
166      const { return 0; }
167    unsigned getSOImmOpValue(const MachineInstr &MI, unsigned Op)
168      const { return 0; }
169    unsigned getSORegOpValue(const MachineInstr &MI, unsigned Op)
170      const { return 0; }
171    unsigned getRotImmOpValue(const MachineInstr &MI, unsigned Op)
172      const { return 0; }
173    unsigned getImmMinusOneOpValue(const MachineInstr &MI, unsigned Op)
174      const { return 0; }
175    unsigned getBitfieldInvertedMaskOpValue(const MachineInstr &MI,
176                                            unsigned Op) const { return 0; }
177    unsigned getAddrModeImm12OpValue(const MachineInstr &MI, unsigned Op)
178      const {
179        // {17-13} = reg
180        // {12}    = (U)nsigned (add == '1', sub == '0')
181        // {11-0}  = imm12
182        const MachineOperand &MO  = MI.getOperand(Op);
183        const MachineOperand &MO1 = MI.getOperand(Op + 1);
184        if (!MO.isReg()) {
185          emitConstPoolAddress(MO.getIndex(), ARM::reloc_arm_cp_entry);
186          return 0;
187        }
188        unsigned Reg = getARMRegisterNumbering(MO.getReg());
189        int32_t Imm12 = MO1.getImm();
190        uint32_t Binary;
191        Binary = Imm12 & 0xfff;
192        if (Imm12 >= 0)
193          Binary |= (1 << 12);
194        Binary |= (Reg << 13);
195        return Binary;
196      }
197    unsigned getNEONVcvtImm32OpValue(const MachineInstr &MI, unsigned Op)
198      const { return 0; }
199
200    /// getMovi32Value - Return binary encoding of operand for movw/movt. If the
201    /// machine operand requires relocation, record the relocation and return
202    /// zero.
203    unsigned getMovi32Value(const MachineInstr &MI,const MachineOperand &MO,
204                            unsigned Reloc);
205
206    /// getShiftOp - Return the shift opcode (bit[6:5]) of the immediate value.
207    ///
208    unsigned getShiftOp(unsigned Imm) const ;
209
210    /// Routines that handle operands which add machine relocations which are
211    /// fixed up by the relocation stage.
212    void emitGlobalAddress(const GlobalValue *GV, unsigned Reloc,
213                           bool MayNeedFarStub,  bool Indirect,
214                           intptr_t ACPV = 0) const;
215    void emitExternalSymbolAddress(const char *ES, unsigned Reloc) const;
216    void emitConstPoolAddress(unsigned CPI, unsigned Reloc) const;
217    void emitJumpTableAddress(unsigned JTIndex, unsigned Reloc) const;
218    void emitMachineBasicBlock(MachineBasicBlock *BB, unsigned Reloc,
219                               intptr_t JTBase = 0) const;
220  };
221}
222
223char ARMCodeEmitter::ID = 0;
224
225/// createARMJITCodeEmitterPass - Return a pass that emits the collected ARM
226/// code to the specified MCE object.
227FunctionPass *llvm::createARMJITCodeEmitterPass(ARMBaseTargetMachine &TM,
228                                                JITCodeEmitter &JCE) {
229  return new ARMCodeEmitter(TM, JCE);
230}
231
232bool ARMCodeEmitter::runOnMachineFunction(MachineFunction &MF) {
233  assert((MF.getTarget().getRelocationModel() != Reloc::Default ||
234          MF.getTarget().getRelocationModel() != Reloc::Static) &&
235         "JIT relocation model must be set to static or default!");
236  JTI = ((ARMTargetMachine &)MF.getTarget()).getJITInfo();
237  II = ((const ARMTargetMachine &)MF.getTarget()).getInstrInfo();
238  TD = ((const ARMTargetMachine &)MF.getTarget()).getTargetData();
239  Subtarget = &TM.getSubtarget<ARMSubtarget>();
240  MCPEs = &MF.getConstantPool()->getConstants();
241  MJTEs = 0;
242  if (MF.getJumpTableInfo()) MJTEs = &MF.getJumpTableInfo()->getJumpTables();
243  IsPIC = TM.getRelocationModel() == Reloc::PIC_;
244  IsThumb = MF.getInfo<ARMFunctionInfo>()->isThumbFunction();
245  JTI->Initialize(MF, IsPIC);
246  MMI = &getAnalysis<MachineModuleInfo>();
247  MCE.setModuleInfo(MMI);
248
249  do {
250    DEBUG(errs() << "JITTing function '"
251          << MF.getFunction()->getName() << "'\n");
252    MCE.startFunction(MF);
253    for (MachineFunction::iterator MBB = MF.begin(), E = MF.end();
254         MBB != E; ++MBB) {
255      MCE.StartMachineBasicBlock(MBB);
256      for (MachineBasicBlock::const_iterator I = MBB->begin(), E = MBB->end();
257           I != E; ++I)
258        emitInstruction(*I);
259    }
260  } while (MCE.finishFunction(MF));
261
262  return false;
263}
264
265/// getShiftOp - Return the shift opcode (bit[6:5]) of the immediate value.
266///
267unsigned ARMCodeEmitter::getShiftOp(unsigned Imm) const {
268  switch (ARM_AM::getAM2ShiftOpc(Imm)) {
269  default: llvm_unreachable("Unknown shift opc!");
270  case ARM_AM::asr: return 2;
271  case ARM_AM::lsl: return 0;
272  case ARM_AM::lsr: return 1;
273  case ARM_AM::ror:
274  case ARM_AM::rrx: return 3;
275  }
276  return 0;
277}
278
279/// getMovi32Value - Return binary encoding of operand for movw/movt. If the
280/// machine operand requires relocation, record the relocation and return zero.
281unsigned ARMCodeEmitter::getMovi32Value(const MachineInstr &MI,
282                                        const MachineOperand &MO,
283                                        unsigned Reloc) {
284  assert(((Reloc == ARM::reloc_arm_movt) || (Reloc == ARM::reloc_arm_movw))
285      && "Relocation to this function should be for movt or movw");
286
287  if (MO.isImm())
288    return static_cast<unsigned>(MO.getImm());
289  else if (MO.isGlobal())
290    emitGlobalAddress(MO.getGlobal(), Reloc, true, false);
291  else if (MO.isSymbol())
292    emitExternalSymbolAddress(MO.getSymbolName(), Reloc);
293  else if (MO.isMBB())
294    emitMachineBasicBlock(MO.getMBB(), Reloc);
295  else {
296#ifndef NDEBUG
297    errs() << MO;
298#endif
299    llvm_unreachable("Unsupported operand type for movw/movt");
300  }
301  return 0;
302}
303
304/// getMachineOpValue - Return binary encoding of operand. If the machine
305/// operand requires relocation, record the relocation and return zero.
306unsigned ARMCodeEmitter::getMachineOpValue(const MachineInstr &MI,
307                                           const MachineOperand &MO) const {
308  if (MO.isReg())
309    return getARMRegisterNumbering(MO.getReg());
310  else if (MO.isImm())
311    return static_cast<unsigned>(MO.getImm());
312  else if (MO.isGlobal())
313    emitGlobalAddress(MO.getGlobal(), ARM::reloc_arm_branch, true, false);
314  else if (MO.isSymbol())
315    emitExternalSymbolAddress(MO.getSymbolName(), ARM::reloc_arm_branch);
316  else if (MO.isCPI()) {
317    const TargetInstrDesc &TID = MI.getDesc();
318    // For VFP load, the immediate offset is multiplied by 4.
319    unsigned Reloc =  ((TID.TSFlags & ARMII::FormMask) == ARMII::VFPLdStFrm)
320      ? ARM::reloc_arm_vfp_cp_entry : ARM::reloc_arm_cp_entry;
321    emitConstPoolAddress(MO.getIndex(), Reloc);
322  } else if (MO.isJTI())
323    emitJumpTableAddress(MO.getIndex(), ARM::reloc_arm_relative);
324  else if (MO.isMBB())
325    emitMachineBasicBlock(MO.getMBB(), ARM::reloc_arm_branch);
326  else {
327#ifndef NDEBUG
328    errs() << MO;
329#endif
330    llvm_unreachable(0);
331  }
332  return 0;
333}
334
335/// emitGlobalAddress - Emit the specified address to the code stream.
336///
337void ARMCodeEmitter::emitGlobalAddress(const GlobalValue *GV, unsigned Reloc,
338                                       bool MayNeedFarStub, bool Indirect,
339                                       intptr_t ACPV) const {
340  MachineRelocation MR = Indirect
341    ? MachineRelocation::getIndirectSymbol(MCE.getCurrentPCOffset(), Reloc,
342                                           const_cast<GlobalValue *>(GV),
343                                           ACPV, MayNeedFarStub)
344    : MachineRelocation::getGV(MCE.getCurrentPCOffset(), Reloc,
345                               const_cast<GlobalValue *>(GV), ACPV,
346                               MayNeedFarStub);
347  MCE.addRelocation(MR);
348}
349
350/// emitExternalSymbolAddress - Arrange for the address of an external symbol to
351/// be emitted to the current location in the function, and allow it to be PC
352/// relative.
353void ARMCodeEmitter::
354emitExternalSymbolAddress(const char *ES, unsigned Reloc) const {
355  MCE.addRelocation(MachineRelocation::getExtSym(MCE.getCurrentPCOffset(),
356                                                 Reloc, ES));
357}
358
359/// emitConstPoolAddress - Arrange for the address of an constant pool
360/// to be emitted to the current location in the function, and allow it to be PC
361/// relative.
362void ARMCodeEmitter::emitConstPoolAddress(unsigned CPI, unsigned Reloc) const {
363  // Tell JIT emitter we'll resolve the address.
364  MCE.addRelocation(MachineRelocation::getConstPool(MCE.getCurrentPCOffset(),
365                                                    Reloc, CPI, 0, true));
366}
367
368/// emitJumpTableAddress - Arrange for the address of a jump table to
369/// be emitted to the current location in the function, and allow it to be PC
370/// relative.
371void ARMCodeEmitter::
372emitJumpTableAddress(unsigned JTIndex, unsigned Reloc) const {
373  MCE.addRelocation(MachineRelocation::getJumpTable(MCE.getCurrentPCOffset(),
374                                                    Reloc, JTIndex, 0, true));
375}
376
377/// emitMachineBasicBlock - Emit the specified address basic block.
378void ARMCodeEmitter::emitMachineBasicBlock(MachineBasicBlock *BB,
379                                           unsigned Reloc,
380                                           intptr_t JTBase) const {
381  MCE.addRelocation(MachineRelocation::getBB(MCE.getCurrentPCOffset(),
382                                             Reloc, BB, JTBase));
383}
384
385void ARMCodeEmitter::emitWordLE(unsigned Binary) {
386  DEBUG(errs() << "  0x";
387        errs().write_hex(Binary) << "\n");
388  MCE.emitWordLE(Binary);
389}
390
391void ARMCodeEmitter::emitDWordLE(uint64_t Binary) {
392  DEBUG(errs() << "  0x";
393        errs().write_hex(Binary) << "\n");
394  MCE.emitDWordLE(Binary);
395}
396
397void ARMCodeEmitter::emitInstruction(const MachineInstr &MI) {
398  DEBUG(errs() << "JIT: " << (void*)MCE.getCurrentPCValue() << ":\t" << MI);
399
400  MCE.processDebugLoc(MI.getDebugLoc(), true);
401
402  ++NumEmitted;  // Keep track of the # of mi's emitted
403  switch (MI.getDesc().TSFlags & ARMII::FormMask) {
404  default: {
405    llvm_unreachable("Unhandled instruction encoding format!");
406    break;
407  }
408  case ARMII::Pseudo:
409    emitPseudoInstruction(MI);
410    break;
411  case ARMII::DPFrm:
412  case ARMII::DPSoRegFrm:
413    emitDataProcessingInstruction(MI);
414    break;
415  case ARMII::LdFrm:
416  case ARMII::StFrm:
417    emitLoadStoreInstruction(MI);
418    break;
419  case ARMII::LdMiscFrm:
420  case ARMII::StMiscFrm:
421    emitMiscLoadStoreInstruction(MI);
422    break;
423  case ARMII::LdStMulFrm:
424    emitLoadStoreMultipleInstruction(MI);
425    break;
426  case ARMII::MulFrm:
427    emitMulFrmInstruction(MI);
428    break;
429  case ARMII::ExtFrm:
430    emitExtendInstruction(MI);
431    break;
432  case ARMII::ArithMiscFrm:
433    emitMiscArithInstruction(MI);
434    break;
435  case ARMII::SatFrm:
436    emitSaturateInstruction(MI);
437    break;
438  case ARMII::BrFrm:
439    emitBranchInstruction(MI);
440    break;
441  case ARMII::BrMiscFrm:
442    emitMiscBranchInstruction(MI);
443    break;
444  // VFP instructions.
445  case ARMII::VFPUnaryFrm:
446  case ARMII::VFPBinaryFrm:
447    emitVFPArithInstruction(MI);
448    break;
449  case ARMII::VFPConv1Frm:
450  case ARMII::VFPConv2Frm:
451  case ARMII::VFPConv3Frm:
452  case ARMII::VFPConv4Frm:
453  case ARMII::VFPConv5Frm:
454    emitVFPConversionInstruction(MI);
455    break;
456  case ARMII::VFPLdStFrm:
457    emitVFPLoadStoreInstruction(MI);
458    break;
459  case ARMII::VFPLdStMulFrm:
460    emitVFPLoadStoreMultipleInstruction(MI);
461    break;
462
463  // NEON instructions.
464  case ARMII::NGetLnFrm:
465  case ARMII::NSetLnFrm:
466    emitNEONLaneInstruction(MI);
467    break;
468  case ARMII::NDupFrm:
469    emitNEONDupInstruction(MI);
470    break;
471  case ARMII::N1RegModImmFrm:
472    emitNEON1RegModImmInstruction(MI);
473    break;
474  case ARMII::N2RegFrm:
475    emitNEON2RegInstruction(MI);
476    break;
477  case ARMII::N3RegFrm:
478    emitNEON3RegInstruction(MI);
479    break;
480  }
481  MCE.processDebugLoc(MI.getDebugLoc(), false);
482}
483
484void ARMCodeEmitter::emitConstPoolInstruction(const MachineInstr &MI) {
485  unsigned CPI = MI.getOperand(0).getImm();       // CP instruction index.
486  unsigned CPIndex = MI.getOperand(1).getIndex(); // Actual cp entry index.
487  const MachineConstantPoolEntry &MCPE = (*MCPEs)[CPIndex];
488
489  // Remember the CONSTPOOL_ENTRY address for later relocation.
490  JTI->addConstantPoolEntryAddr(CPI, MCE.getCurrentPCValue());
491
492  // Emit constpool island entry. In most cases, the actual values will be
493  // resolved and relocated after code emission.
494  if (MCPE.isMachineConstantPoolEntry()) {
495    ARMConstantPoolValue *ACPV =
496      static_cast<ARMConstantPoolValue*>(MCPE.Val.MachineCPVal);
497
498    DEBUG(errs() << "  ** ARM constant pool #" << CPI << " @ "
499          << (void*)MCE.getCurrentPCValue() << " " << *ACPV << '\n');
500
501    assert(ACPV->isGlobalValue() && "unsupported constant pool value");
502    const GlobalValue *GV = ACPV->getGV();
503    if (GV) {
504      Reloc::Model RelocM = TM.getRelocationModel();
505      emitGlobalAddress(GV, ARM::reloc_arm_machine_cp_entry,
506                        isa<Function>(GV),
507                        Subtarget->GVIsIndirectSymbol(GV, RelocM),
508                        (intptr_t)ACPV);
509     } else  {
510      emitExternalSymbolAddress(ACPV->getSymbol(), ARM::reloc_arm_absolute);
511    }
512    emitWordLE(0);
513  } else {
514    const Constant *CV = MCPE.Val.ConstVal;
515
516    DEBUG({
517        errs() << "  ** Constant pool #" << CPI << " @ "
518               << (void*)MCE.getCurrentPCValue() << " ";
519        if (const Function *F = dyn_cast<Function>(CV))
520          errs() << F->getName();
521        else
522          errs() << *CV;
523        errs() << '\n';
524      });
525
526    if (const GlobalValue *GV = dyn_cast<GlobalValue>(CV)) {
527      emitGlobalAddress(GV, ARM::reloc_arm_absolute, isa<Function>(GV), false);
528      emitWordLE(0);
529    } else if (const ConstantInt *CI = dyn_cast<ConstantInt>(CV)) {
530      uint32_t Val = uint32_t(*CI->getValue().getRawData());
531      emitWordLE(Val);
532    } else if (const ConstantFP *CFP = dyn_cast<ConstantFP>(CV)) {
533      if (CFP->getType()->isFloatTy())
534        emitWordLE(CFP->getValueAPF().bitcastToAPInt().getZExtValue());
535      else if (CFP->getType()->isDoubleTy())
536        emitDWordLE(CFP->getValueAPF().bitcastToAPInt().getZExtValue());
537      else {
538        llvm_unreachable("Unable to handle this constantpool entry!");
539      }
540    } else {
541      llvm_unreachable("Unable to handle this constantpool entry!");
542    }
543  }
544}
545
546void ARMCodeEmitter::emitMOVi32immInstruction(const MachineInstr &MI) {
547  const MachineOperand &MO0 = MI.getOperand(0);
548  const MachineOperand &MO1 = MI.getOperand(1);
549
550  // Emit the 'movw' instruction.
551  unsigned Binary = 0x30 << 20;  // mov: Insts{27-20} = 0b00110000
552
553  unsigned Lo16 = getMovi32Value(MI, MO1, ARM::reloc_arm_movw) & 0xFFFF;
554
555  // Set the conditional execution predicate.
556  Binary |= II->getPredicate(&MI) << ARMII::CondShift;
557
558  // Encode Rd.
559  Binary |= getMachineOpValue(MI, MO0) << ARMII::RegRdShift;
560
561  // Encode imm16 as imm4:imm12
562  Binary |= Lo16 & 0xFFF; // Insts{11-0} = imm12
563  Binary |= ((Lo16 >> 12) & 0xF) << 16; // Insts{19-16} = imm4
564  emitWordLE(Binary);
565
566  unsigned Hi16 = getMovi32Value(MI, MO1, ARM::reloc_arm_movt) >> 16;
567  // Emit the 'movt' instruction.
568  Binary = 0x34 << 20; // movt: Insts{27-20} = 0b00110100
569
570  // Set the conditional execution predicate.
571  Binary |= II->getPredicate(&MI) << ARMII::CondShift;
572
573  // Encode Rd.
574  Binary |= getMachineOpValue(MI, MO0) << ARMII::RegRdShift;
575
576  // Encode imm16 as imm4:imm1, same as movw above.
577  Binary |= Hi16 & 0xFFF;
578  Binary |= ((Hi16 >> 12) & 0xF) << 16;
579  emitWordLE(Binary);
580}
581
582void ARMCodeEmitter::emitMOVi2piecesInstruction(const MachineInstr &MI) {
583  const MachineOperand &MO0 = MI.getOperand(0);
584  const MachineOperand &MO1 = MI.getOperand(1);
585  assert(MO1.isImm() && ARM_AM::isSOImmTwoPartVal(MO1.getImm()) &&
586                                                  "Not a valid so_imm value!");
587  unsigned V1 = ARM_AM::getSOImmTwoPartFirst(MO1.getImm());
588  unsigned V2 = ARM_AM::getSOImmTwoPartSecond(MO1.getImm());
589
590  // Emit the 'mov' instruction.
591  unsigned Binary = 0xd << 21;  // mov: Insts{24-21} = 0b1101
592
593  // Set the conditional execution predicate.
594  Binary |= II->getPredicate(&MI) << ARMII::CondShift;
595
596  // Encode Rd.
597  Binary |= getMachineOpValue(MI, MO0) << ARMII::RegRdShift;
598
599  // Encode so_imm.
600  // Set bit I(25) to identify this is the immediate form of <shifter_op>
601  Binary |= 1 << ARMII::I_BitShift;
602  Binary |= getMachineSoImmOpValue(V1);
603  emitWordLE(Binary);
604
605  // Now the 'orr' instruction.
606  Binary = 0xc << 21;  // orr: Insts{24-21} = 0b1100
607
608  // Set the conditional execution predicate.
609  Binary |= II->getPredicate(&MI) << ARMII::CondShift;
610
611  // Encode Rd.
612  Binary |= getMachineOpValue(MI, MO0) << ARMII::RegRdShift;
613
614  // Encode Rn.
615  Binary |= getMachineOpValue(MI, MO0) << ARMII::RegRnShift;
616
617  // Encode so_imm.
618  // Set bit I(25) to identify this is the immediate form of <shifter_op>
619  Binary |= 1 << ARMII::I_BitShift;
620  Binary |= getMachineSoImmOpValue(V2);
621  emitWordLE(Binary);
622}
623
624void ARMCodeEmitter::emitLEApcrelJTInstruction(const MachineInstr &MI) {
625  // It's basically add r, pc, (LJTI - $+8)
626
627  const TargetInstrDesc &TID = MI.getDesc();
628
629  // Emit the 'add' instruction.
630  unsigned Binary = 0x4 << 21;  // add: Insts{24-31} = 0b0100
631
632  // Set the conditional execution predicate
633  Binary |= II->getPredicate(&MI) << ARMII::CondShift;
634
635  // Encode S bit if MI modifies CPSR.
636  Binary |= getAddrModeSBit(MI, TID);
637
638  // Encode Rd.
639  Binary |= getMachineOpValue(MI, 0) << ARMII::RegRdShift;
640
641  // Encode Rn which is PC.
642  Binary |= getARMRegisterNumbering(ARM::PC) << ARMII::RegRnShift;
643
644  // Encode the displacement.
645  Binary |= 1 << ARMII::I_BitShift;
646  emitJumpTableAddress(MI.getOperand(1).getIndex(), ARM::reloc_arm_jt_base);
647
648  emitWordLE(Binary);
649}
650
651void ARMCodeEmitter::emitPseudoMoveInstruction(const MachineInstr &MI) {
652  unsigned Opcode = MI.getDesc().Opcode;
653
654  // Part of binary is determined by TableGn.
655  unsigned Binary = getBinaryCodeForInstr(MI);
656
657  // Set the conditional execution predicate
658  Binary |= II->getPredicate(&MI) << ARMII::CondShift;
659
660  // Encode S bit if MI modifies CPSR.
661  if (Opcode == ARM::MOVsrl_flag || Opcode == ARM::MOVsra_flag)
662    Binary |= 1 << ARMII::S_BitShift;
663
664  // Encode register def if there is one.
665  Binary |= getMachineOpValue(MI, 0) << ARMII::RegRdShift;
666
667  // Encode the shift operation.
668  switch (Opcode) {
669  default: break;
670  case ARM::RRX:
671    // rrx
672    Binary |= 0x6 << 4;
673    break;
674  case ARM::MOVsrl_flag:
675    // lsr #1
676    Binary |= (0x2 << 4) | (1 << 7);
677    break;
678  case ARM::MOVsra_flag:
679    // asr #1
680    Binary |= (0x4 << 4) | (1 << 7);
681    break;
682  }
683
684  // Encode register Rm.
685  Binary |= getMachineOpValue(MI, 1);
686
687  emitWordLE(Binary);
688}
689
690void ARMCodeEmitter::addPCLabel(unsigned LabelID) {
691  DEBUG(errs() << "  ** LPC" << LabelID << " @ "
692        << (void*)MCE.getCurrentPCValue() << '\n');
693  JTI->addPCLabelAddr(LabelID, MCE.getCurrentPCValue());
694}
695
696void ARMCodeEmitter::emitPseudoInstruction(const MachineInstr &MI) {
697  unsigned Opcode = MI.getDesc().Opcode;
698  switch (Opcode) {
699  default:
700    llvm_unreachable("ARMCodeEmitter::emitPseudoInstruction");
701  case ARM::BX:
702  case ARM::BMOVPCRX:
703  case ARM::BXr9:
704  case ARM::BMOVPCRXr9: {
705    // First emit mov lr, pc
706    unsigned Binary = 0x01a0e00f;
707    Binary |= II->getPredicate(&MI) << ARMII::CondShift;
708    emitWordLE(Binary);
709
710    // and then emit the branch.
711    emitMiscBranchInstruction(MI);
712    break;
713  }
714  case TargetOpcode::INLINEASM: {
715    // We allow inline assembler nodes with empty bodies - they can
716    // implicitly define registers, which is ok for JIT.
717    if (MI.getOperand(0).getSymbolName()[0]) {
718      report_fatal_error("JIT does not support inline asm!");
719    }
720    break;
721  }
722  case TargetOpcode::PROLOG_LABEL:
723  case TargetOpcode::EH_LABEL:
724    MCE.emitLabel(MI.getOperand(0).getMCSymbol());
725    break;
726  case TargetOpcode::IMPLICIT_DEF:
727  case TargetOpcode::KILL:
728    // Do nothing.
729    break;
730  case ARM::CONSTPOOL_ENTRY:
731    emitConstPoolInstruction(MI);
732    break;
733  case ARM::PICADD: {
734    // Remember of the address of the PC label for relocation later.
735    addPCLabel(MI.getOperand(2).getImm());
736    // PICADD is just an add instruction that implicitly read pc.
737    emitDataProcessingInstruction(MI, 0, ARM::PC);
738    break;
739  }
740  case ARM::PICLDR:
741  case ARM::PICLDRB:
742  case ARM::PICSTR:
743  case ARM::PICSTRB: {
744    // Remember of the address of the PC label for relocation later.
745    addPCLabel(MI.getOperand(2).getImm());
746    // These are just load / store instructions that implicitly read pc.
747    emitLoadStoreInstruction(MI, 0, ARM::PC);
748    break;
749  }
750  case ARM::PICLDRH:
751  case ARM::PICLDRSH:
752  case ARM::PICLDRSB:
753  case ARM::PICSTRH: {
754    // Remember of the address of the PC label for relocation later.
755    addPCLabel(MI.getOperand(2).getImm());
756    // These are just load / store instructions that implicitly read pc.
757    emitMiscLoadStoreInstruction(MI, ARM::PC);
758    break;
759  }
760
761  case ARM::MOVi32imm:
762    emitMOVi32immInstruction(MI);
763    break;
764
765  case ARM::MOVi2pieces:
766    // Two instructions to materialize a constant.
767    emitMOVi2piecesInstruction(MI);
768    break;
769  case ARM::LEApcrelJT:
770    // Materialize jumptable address.
771    emitLEApcrelJTInstruction(MI);
772    break;
773  case ARM::RRX:
774  case ARM::MOVsrl_flag:
775  case ARM::MOVsra_flag:
776    emitPseudoMoveInstruction(MI);
777    break;
778  }
779}
780
781unsigned ARMCodeEmitter::getMachineSoRegOpValue(const MachineInstr &MI,
782                                                const TargetInstrDesc &TID,
783                                                const MachineOperand &MO,
784                                                unsigned OpIdx) {
785  unsigned Binary = getMachineOpValue(MI, MO);
786
787  const MachineOperand &MO1 = MI.getOperand(OpIdx + 1);
788  const MachineOperand &MO2 = MI.getOperand(OpIdx + 2);
789  ARM_AM::ShiftOpc SOpc = ARM_AM::getSORegShOp(MO2.getImm());
790
791  // Encode the shift opcode.
792  unsigned SBits = 0;
793  unsigned Rs = MO1.getReg();
794  if (Rs) {
795    // Set shift operand (bit[7:4]).
796    // LSL - 0001
797    // LSR - 0011
798    // ASR - 0101
799    // ROR - 0111
800    // RRX - 0110 and bit[11:8] clear.
801    switch (SOpc) {
802    default: llvm_unreachable("Unknown shift opc!");
803    case ARM_AM::lsl: SBits = 0x1; break;
804    case ARM_AM::lsr: SBits = 0x3; break;
805    case ARM_AM::asr: SBits = 0x5; break;
806    case ARM_AM::ror: SBits = 0x7; break;
807    case ARM_AM::rrx: SBits = 0x6; break;
808    }
809  } else {
810    // Set shift operand (bit[6:4]).
811    // LSL - 000
812    // LSR - 010
813    // ASR - 100
814    // ROR - 110
815    switch (SOpc) {
816    default: llvm_unreachable("Unknown shift opc!");
817    case ARM_AM::lsl: SBits = 0x0; break;
818    case ARM_AM::lsr: SBits = 0x2; break;
819    case ARM_AM::asr: SBits = 0x4; break;
820    case ARM_AM::ror: SBits = 0x6; break;
821    }
822  }
823  Binary |= SBits << 4;
824  if (SOpc == ARM_AM::rrx)
825    return Binary;
826
827  // Encode the shift operation Rs or shift_imm (except rrx).
828  if (Rs) {
829    // Encode Rs bit[11:8].
830    assert(ARM_AM::getSORegOffset(MO2.getImm()) == 0);
831    return Binary | (getARMRegisterNumbering(Rs) << ARMII::RegRsShift);
832  }
833
834  // Encode shift_imm bit[11:7].
835  return Binary | ARM_AM::getSORegOffset(MO2.getImm()) << 7;
836}
837
838unsigned ARMCodeEmitter::getMachineSoImmOpValue(unsigned SoImm) {
839  int SoImmVal = ARM_AM::getSOImmVal(SoImm);
840  assert(SoImmVal != -1 && "Not a valid so_imm value!");
841
842  // Encode rotate_imm.
843  unsigned Binary = (ARM_AM::getSOImmValRot((unsigned)SoImmVal) >> 1)
844    << ARMII::SoRotImmShift;
845
846  // Encode immed_8.
847  Binary |= ARM_AM::getSOImmValImm((unsigned)SoImmVal);
848  return Binary;
849}
850
851unsigned ARMCodeEmitter::getAddrModeSBit(const MachineInstr &MI,
852                                         const TargetInstrDesc &TID) const {
853  for (unsigned i = MI.getNumOperands(), e = TID.getNumOperands(); i != e; --i){
854    const MachineOperand &MO = MI.getOperand(i-1);
855    if (MO.isReg() && MO.isDef() && MO.getReg() == ARM::CPSR)
856      return 1 << ARMII::S_BitShift;
857  }
858  return 0;
859}
860
861void ARMCodeEmitter::emitDataProcessingInstruction(const MachineInstr &MI,
862                                                   unsigned ImplicitRd,
863                                                   unsigned ImplicitRn) {
864  const TargetInstrDesc &TID = MI.getDesc();
865
866  // Part of binary is determined by TableGn.
867  unsigned Binary = getBinaryCodeForInstr(MI);
868
869  // Set the conditional execution predicate
870  Binary |= II->getPredicate(&MI) << ARMII::CondShift;
871
872  // Encode S bit if MI modifies CPSR.
873  Binary |= getAddrModeSBit(MI, TID);
874
875  // Encode register def if there is one.
876  unsigned NumDefs = TID.getNumDefs();
877  unsigned OpIdx = 0;
878  if (NumDefs)
879    Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRdShift;
880  else if (ImplicitRd)
881    // Special handling for implicit use (e.g. PC).
882    Binary |= (getARMRegisterNumbering(ImplicitRd) << ARMII::RegRdShift);
883
884  if (TID.Opcode == ARM::MOVi16) {
885      // Get immediate from MI.
886      unsigned Lo16 = getMovi32Value(MI, MI.getOperand(OpIdx),
887                      ARM::reloc_arm_movw);
888      // Encode imm which is the same as in emitMOVi32immInstruction().
889      Binary |= Lo16 & 0xFFF;
890      Binary |= ((Lo16 >> 12) & 0xF) << 16;
891      emitWordLE(Binary);
892      return;
893  } else if(TID.Opcode == ARM::MOVTi16) {
894      unsigned Hi16 = (getMovi32Value(MI, MI.getOperand(OpIdx),
895                       ARM::reloc_arm_movt) >> 16);
896      Binary |= Hi16 & 0xFFF;
897      Binary |= ((Hi16 >> 12) & 0xF) << 16;
898      emitWordLE(Binary);
899      return;
900  } else if ((TID.Opcode == ARM::BFC) || (TID.Opcode == ARM::BFI)) {
901      uint32_t v = ~MI.getOperand(2).getImm();
902      int32_t lsb = CountTrailingZeros_32(v);
903      int32_t msb = (32 - CountLeadingZeros_32(v)) - 1;
904      // Instr{20-16} = msb, Instr{11-7} = lsb
905      Binary |= (msb & 0x1F) << 16;
906      Binary |= (lsb & 0x1F) << 7;
907      emitWordLE(Binary);
908      return;
909  } else if ((TID.Opcode == ARM::UBFX) || (TID.Opcode == ARM::SBFX)) {
910      // Encode Rn in Instr{0-3}
911      Binary |= getMachineOpValue(MI, OpIdx++);
912
913      uint32_t lsb = MI.getOperand(OpIdx++).getImm();
914      uint32_t widthm1 = MI.getOperand(OpIdx++).getImm() - 1;
915
916      // Instr{20-16} = widthm1, Instr{11-7} = lsb
917      Binary |= (widthm1 & 0x1F) << 16;
918      Binary |= (lsb & 0x1F) << 7;
919      emitWordLE(Binary);
920      return;
921  }
922
923  // If this is a two-address operand, skip it. e.g. MOVCCr operand 1.
924  if (TID.getOperandConstraint(OpIdx, TOI::TIED_TO) != -1)
925    ++OpIdx;
926
927  // Encode first non-shifter register operand if there is one.
928  bool isUnary = TID.TSFlags & ARMII::UnaryDP;
929  if (!isUnary) {
930    if (ImplicitRn)
931      // Special handling for implicit use (e.g. PC).
932      Binary |= (getARMRegisterNumbering(ImplicitRn) << ARMII::RegRnShift);
933    else {
934      Binary |= getMachineOpValue(MI, OpIdx) << ARMII::RegRnShift;
935      ++OpIdx;
936    }
937  }
938
939  // Encode shifter operand.
940  const MachineOperand &MO = MI.getOperand(OpIdx);
941  if ((TID.TSFlags & ARMII::FormMask) == ARMII::DPSoRegFrm) {
942    // Encode SoReg.
943    emitWordLE(Binary | getMachineSoRegOpValue(MI, TID, MO, OpIdx));
944    return;
945  }
946
947  if (MO.isReg()) {
948    // Encode register Rm.
949    emitWordLE(Binary | getARMRegisterNumbering(MO.getReg()));
950    return;
951  }
952
953  // Encode so_imm.
954  Binary |= getMachineSoImmOpValue((unsigned)MO.getImm());
955
956  emitWordLE(Binary);
957}
958
959void ARMCodeEmitter::emitLoadStoreInstruction(const MachineInstr &MI,
960                                              unsigned ImplicitRd,
961                                              unsigned ImplicitRn) {
962  const TargetInstrDesc &TID = MI.getDesc();
963  unsigned Form = TID.TSFlags & ARMII::FormMask;
964  bool IsPrePost = (TID.TSFlags & ARMII::IndexModeMask) != 0;
965
966  // Part of binary is determined by TableGn.
967  unsigned Binary = getBinaryCodeForInstr(MI);
968
969  // If this is an LDRi12, STRi12 or LDRcp, nothing more needs be done.
970  if (MI.getOpcode() == ARM::LDRi12 || MI.getOpcode() == ARM::LDRcp ||
971      MI.getOpcode() == ARM::STRi12) {
972    emitWordLE(Binary);
973    return;
974  }
975
976  // Set the conditional execution predicate
977  Binary |= II->getPredicate(&MI) << ARMII::CondShift;
978
979  unsigned OpIdx = 0;
980
981  // Operand 0 of a pre- and post-indexed store is the address base
982  // writeback. Skip it.
983  bool Skipped = false;
984  if (IsPrePost && Form == ARMII::StFrm) {
985    ++OpIdx;
986    Skipped = true;
987  }
988
989  // Set first operand
990  if (ImplicitRd)
991    // Special handling for implicit use (e.g. PC).
992    Binary |= (getARMRegisterNumbering(ImplicitRd) << ARMII::RegRdShift);
993  else
994    Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRdShift;
995
996  // Set second operand
997  if (ImplicitRn)
998    // Special handling for implicit use (e.g. PC).
999    Binary |= (getARMRegisterNumbering(ImplicitRn) << ARMII::RegRnShift);
1000  else
1001    Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRnShift;
1002
1003  // If this is a two-address operand, skip it. e.g. LDR_PRE.
1004  if (!Skipped && TID.getOperandConstraint(OpIdx, TOI::TIED_TO) != -1)
1005    ++OpIdx;
1006
1007  const MachineOperand &MO2 = MI.getOperand(OpIdx);
1008  unsigned AM2Opc = (ImplicitRn == ARM::PC)
1009    ? 0 : MI.getOperand(OpIdx+1).getImm();
1010
1011  // Set bit U(23) according to sign of immed value (positive or negative).
1012  Binary |= ((ARM_AM::getAM2Op(AM2Opc) == ARM_AM::add ? 1 : 0) <<
1013             ARMII::U_BitShift);
1014  if (!MO2.getReg()) { // is immediate
1015    if (ARM_AM::getAM2Offset(AM2Opc))
1016      // Set the value of offset_12 field
1017      Binary |= ARM_AM::getAM2Offset(AM2Opc);
1018    emitWordLE(Binary);
1019    return;
1020  }
1021
1022  // Set bit I(25), because this is not in immediate encoding.
1023  Binary |= 1 << ARMII::I_BitShift;
1024  assert(TargetRegisterInfo::isPhysicalRegister(MO2.getReg()));
1025  // Set bit[3:0] to the corresponding Rm register
1026  Binary |= getARMRegisterNumbering(MO2.getReg());
1027
1028  // If this instr is in scaled register offset/index instruction, set
1029  // shift_immed(bit[11:7]) and shift(bit[6:5]) fields.
1030  if (unsigned ShImm = ARM_AM::getAM2Offset(AM2Opc)) {
1031    Binary |= getShiftOp(AM2Opc) << ARMII::ShiftImmShift;  // shift
1032    Binary |= ShImm              << ARMII::ShiftShift;     // shift_immed
1033  }
1034
1035  emitWordLE(Binary);
1036}
1037
1038void ARMCodeEmitter::emitMiscLoadStoreInstruction(const MachineInstr &MI,
1039                                                  unsigned ImplicitRn) {
1040  const TargetInstrDesc &TID = MI.getDesc();
1041  unsigned Form = TID.TSFlags & ARMII::FormMask;
1042  bool IsPrePost = (TID.TSFlags & ARMII::IndexModeMask) != 0;
1043
1044  // Part of binary is determined by TableGn.
1045  unsigned Binary = getBinaryCodeForInstr(MI);
1046
1047  // Set the conditional execution predicate
1048  Binary |= II->getPredicate(&MI) << ARMII::CondShift;
1049
1050  unsigned OpIdx = 0;
1051
1052  // Operand 0 of a pre- and post-indexed store is the address base
1053  // writeback. Skip it.
1054  bool Skipped = false;
1055  if (IsPrePost && Form == ARMII::StMiscFrm) {
1056    ++OpIdx;
1057    Skipped = true;
1058  }
1059
1060  // Set first operand
1061  Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRdShift;
1062
1063  // Skip LDRD and STRD's second operand.
1064  if (TID.Opcode == ARM::LDRD || TID.Opcode == ARM::STRD)
1065    ++OpIdx;
1066
1067  // Set second operand
1068  if (ImplicitRn)
1069    // Special handling for implicit use (e.g. PC).
1070    Binary |= (getARMRegisterNumbering(ImplicitRn) << ARMII::RegRnShift);
1071  else
1072    Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRnShift;
1073
1074  // If this is a two-address operand, skip it. e.g. LDRH_POST.
1075  if (!Skipped && TID.getOperandConstraint(OpIdx, TOI::TIED_TO) != -1)
1076    ++OpIdx;
1077
1078  const MachineOperand &MO2 = MI.getOperand(OpIdx);
1079  unsigned AM3Opc = (ImplicitRn == ARM::PC)
1080    ? 0 : MI.getOperand(OpIdx+1).getImm();
1081
1082  // Set bit U(23) according to sign of immed value (positive or negative)
1083  Binary |= ((ARM_AM::getAM3Op(AM3Opc) == ARM_AM::add ? 1 : 0) <<
1084             ARMII::U_BitShift);
1085
1086  // If this instr is in register offset/index encoding, set bit[3:0]
1087  // to the corresponding Rm register.
1088  if (MO2.getReg()) {
1089    Binary |= getARMRegisterNumbering(MO2.getReg());
1090    emitWordLE(Binary);
1091    return;
1092  }
1093
1094  // This instr is in immediate offset/index encoding, set bit 22 to 1.
1095  Binary |= 1 << ARMII::AM3_I_BitShift;
1096  if (unsigned ImmOffs = ARM_AM::getAM3Offset(AM3Opc)) {
1097    // Set operands
1098    Binary |= (ImmOffs >> 4) << ARMII::ImmHiShift;  // immedH
1099    Binary |= (ImmOffs & 0xF);                      // immedL
1100  }
1101
1102  emitWordLE(Binary);
1103}
1104
1105static unsigned getAddrModeUPBits(unsigned Mode) {
1106  unsigned Binary = 0;
1107
1108  // Set addressing mode by modifying bits U(23) and P(24)
1109  // IA - Increment after  - bit U = 1 and bit P = 0
1110  // IB - Increment before - bit U = 1 and bit P = 1
1111  // DA - Decrement after  - bit U = 0 and bit P = 0
1112  // DB - Decrement before - bit U = 0 and bit P = 1
1113  switch (Mode) {
1114  default: llvm_unreachable("Unknown addressing sub-mode!");
1115  case ARM_AM::da:                                     break;
1116  case ARM_AM::db: Binary |= 0x1 << ARMII::P_BitShift; break;
1117  case ARM_AM::ia: Binary |= 0x1 << ARMII::U_BitShift; break;
1118  case ARM_AM::ib: Binary |= 0x3 << ARMII::U_BitShift; break;
1119  }
1120
1121  return Binary;
1122}
1123
1124void ARMCodeEmitter::emitLoadStoreMultipleInstruction(const MachineInstr &MI) {
1125  const TargetInstrDesc &TID = MI.getDesc();
1126  bool IsUpdating = (TID.TSFlags & ARMII::IndexModeMask) != 0;
1127
1128  // Part of binary is determined by TableGn.
1129  unsigned Binary = getBinaryCodeForInstr(MI);
1130
1131  // Set the conditional execution predicate
1132  Binary |= II->getPredicate(&MI) << ARMII::CondShift;
1133
1134  // Skip operand 0 of an instruction with base register update.
1135  unsigned OpIdx = 0;
1136  if (IsUpdating)
1137    ++OpIdx;
1138
1139  // Set base address operand
1140  Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRnShift;
1141
1142  // Set addressing mode by modifying bits U(23) and P(24)
1143  const MachineOperand &MO = MI.getOperand(OpIdx++);
1144  Binary |= getAddrModeUPBits(ARM_AM::getAM4SubMode(MO.getImm()));
1145
1146  // Set bit W(21)
1147  if (IsUpdating)
1148    Binary |= 0x1 << ARMII::W_BitShift;
1149
1150  // Set registers
1151  for (unsigned i = OpIdx+2, e = MI.getNumOperands(); i != e; ++i) {
1152    const MachineOperand &MO = MI.getOperand(i);
1153    if (!MO.isReg() || MO.isImplicit())
1154      break;
1155    unsigned RegNum = getARMRegisterNumbering(MO.getReg());
1156    assert(TargetRegisterInfo::isPhysicalRegister(MO.getReg()) &&
1157           RegNum < 16);
1158    Binary |= 0x1 << RegNum;
1159  }
1160
1161  emitWordLE(Binary);
1162}
1163
1164void ARMCodeEmitter::emitMulFrmInstruction(const MachineInstr &MI) {
1165  const TargetInstrDesc &TID = MI.getDesc();
1166
1167  // Part of binary is determined by TableGn.
1168  unsigned Binary = getBinaryCodeForInstr(MI);
1169
1170  // Set the conditional execution predicate
1171  Binary |= II->getPredicate(&MI) << ARMII::CondShift;
1172
1173  // Encode S bit if MI modifies CPSR.
1174  Binary |= getAddrModeSBit(MI, TID);
1175
1176  // 32x32->64bit operations have two destination registers. The number
1177  // of register definitions will tell us if that's what we're dealing with.
1178  unsigned OpIdx = 0;
1179  if (TID.getNumDefs() == 2)
1180    Binary |= getMachineOpValue (MI, OpIdx++) << ARMII::RegRdLoShift;
1181
1182  // Encode Rd
1183  Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRdHiShift;
1184
1185  // Encode Rm
1186  Binary |= getMachineOpValue(MI, OpIdx++);
1187
1188  // Encode Rs
1189  Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRsShift;
1190
1191  // Many multiple instructions (e.g. MLA) have three src operands. Encode
1192  // it as Rn (for multiply, that's in the same offset as RdLo.
1193  if (TID.getNumOperands() > OpIdx &&
1194      !TID.OpInfo[OpIdx].isPredicate() &&
1195      !TID.OpInfo[OpIdx].isOptionalDef())
1196    Binary |= getMachineOpValue(MI, OpIdx) << ARMII::RegRdLoShift;
1197
1198  emitWordLE(Binary);
1199}
1200
1201void ARMCodeEmitter::emitExtendInstruction(const MachineInstr &MI) {
1202  const TargetInstrDesc &TID = MI.getDesc();
1203
1204  // Part of binary is determined by TableGn.
1205  unsigned Binary = getBinaryCodeForInstr(MI);
1206
1207  // Set the conditional execution predicate
1208  Binary |= II->getPredicate(&MI) << ARMII::CondShift;
1209
1210  unsigned OpIdx = 0;
1211
1212  // Encode Rd
1213  Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRdShift;
1214
1215  const MachineOperand &MO1 = MI.getOperand(OpIdx++);
1216  const MachineOperand &MO2 = MI.getOperand(OpIdx);
1217  if (MO2.isReg()) {
1218    // Two register operand form.
1219    // Encode Rn.
1220    Binary |= getMachineOpValue(MI, MO1) << ARMII::RegRnShift;
1221
1222    // Encode Rm.
1223    Binary |= getMachineOpValue(MI, MO2);
1224    ++OpIdx;
1225  } else {
1226    Binary |= getMachineOpValue(MI, MO1);
1227  }
1228
1229  // Encode rot imm (0, 8, 16, or 24) if it has a rotate immediate operand.
1230  if (MI.getOperand(OpIdx).isImm() &&
1231      !TID.OpInfo[OpIdx].isPredicate() &&
1232      !TID.OpInfo[OpIdx].isOptionalDef())
1233    Binary |= (getMachineOpValue(MI, OpIdx) / 8) << ARMII::ExtRotImmShift;
1234
1235  emitWordLE(Binary);
1236}
1237
1238void ARMCodeEmitter::emitMiscArithInstruction(const MachineInstr &MI) {
1239  const TargetInstrDesc &TID = MI.getDesc();
1240
1241  // Part of binary is determined by TableGn.
1242  unsigned Binary = getBinaryCodeForInstr(MI);
1243
1244  // Set the conditional execution predicate
1245  Binary |= II->getPredicate(&MI) << ARMII::CondShift;
1246
1247  unsigned OpIdx = 0;
1248
1249  // Encode Rd
1250  Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRdShift;
1251
1252  const MachineOperand &MO = MI.getOperand(OpIdx++);
1253  if (OpIdx == TID.getNumOperands() ||
1254      TID.OpInfo[OpIdx].isPredicate() ||
1255      TID.OpInfo[OpIdx].isOptionalDef()) {
1256    // Encode Rm and it's done.
1257    Binary |= getMachineOpValue(MI, MO);
1258    emitWordLE(Binary);
1259    return;
1260  }
1261
1262  // Encode Rn.
1263  Binary |= getMachineOpValue(MI, MO) << ARMII::RegRnShift;
1264
1265  // Encode Rm.
1266  Binary |= getMachineOpValue(MI, OpIdx++);
1267
1268  // Encode shift_imm.
1269  unsigned ShiftAmt = MI.getOperand(OpIdx).getImm();
1270  if (TID.Opcode == ARM::PKHTB) {
1271    assert(ShiftAmt != 0 && "PKHTB shift_imm is 0!");
1272    if (ShiftAmt == 32)
1273      ShiftAmt = 0;
1274  }
1275  assert(ShiftAmt < 32 && "shift_imm range is 0 to 31!");
1276  Binary |= ShiftAmt << ARMII::ShiftShift;
1277
1278  emitWordLE(Binary);
1279}
1280
1281void ARMCodeEmitter::emitSaturateInstruction(const MachineInstr &MI) {
1282  const TargetInstrDesc &TID = MI.getDesc();
1283
1284  // Part of binary is determined by TableGen.
1285  unsigned Binary = getBinaryCodeForInstr(MI);
1286
1287  // Set the conditional execution predicate
1288  Binary |= II->getPredicate(&MI) << ARMII::CondShift;
1289
1290  // Encode Rd
1291  Binary |= getMachineOpValue(MI, 0) << ARMII::RegRdShift;
1292
1293  // Encode saturate bit position.
1294  unsigned Pos = MI.getOperand(1).getImm();
1295  if (TID.Opcode == ARM::SSAT || TID.Opcode == ARM::SSAT16)
1296    Pos -= 1;
1297  assert((Pos < 16 || (Pos < 32 &&
1298                       TID.Opcode != ARM::SSAT16 &&
1299                       TID.Opcode != ARM::USAT16)) &&
1300         "saturate bit position out of range");
1301  Binary |= Pos << 16;
1302
1303  // Encode Rm
1304  Binary |= getMachineOpValue(MI, 2);
1305
1306  // Encode shift_imm.
1307  if (TID.getNumOperands() == 4) {
1308    unsigned ShiftOp = MI.getOperand(3).getImm();
1309    ARM_AM::ShiftOpc Opc = ARM_AM::getSORegShOp(ShiftOp);
1310    if (Opc == ARM_AM::asr)
1311      Binary |= (1 << 6);
1312    unsigned ShiftAmt = MI.getOperand(3).getImm();
1313    if (ShiftAmt == 32 && Opc == ARM_AM::asr)
1314      ShiftAmt = 0;
1315    assert(ShiftAmt < 32 && "shift_imm range is 0 to 31!");
1316    Binary |= ShiftAmt << ARMII::ShiftShift;
1317  }
1318
1319  emitWordLE(Binary);
1320}
1321
1322void ARMCodeEmitter::emitBranchInstruction(const MachineInstr &MI) {
1323  const TargetInstrDesc &TID = MI.getDesc();
1324
1325  if (TID.Opcode == ARM::TPsoft) {
1326    llvm_unreachable("ARM::TPsoft FIXME"); // FIXME
1327  }
1328
1329  // Part of binary is determined by TableGn.
1330  unsigned Binary = getBinaryCodeForInstr(MI);
1331
1332  // Set the conditional execution predicate
1333  Binary |= II->getPredicate(&MI) << ARMII::CondShift;
1334
1335  // Set signed_immed_24 field
1336  Binary |= getMachineOpValue(MI, 0);
1337
1338  emitWordLE(Binary);
1339}
1340
1341void ARMCodeEmitter::emitInlineJumpTable(unsigned JTIndex) {
1342  // Remember the base address of the inline jump table.
1343  uintptr_t JTBase = MCE.getCurrentPCValue();
1344  JTI->addJumpTableBaseAddr(JTIndex, JTBase);
1345  DEBUG(errs() << "  ** Jump Table #" << JTIndex << " @ " << (void*)JTBase
1346               << '\n');
1347
1348  // Now emit the jump table entries.
1349  const std::vector<MachineBasicBlock*> &MBBs = (*MJTEs)[JTIndex].MBBs;
1350  for (unsigned i = 0, e = MBBs.size(); i != e; ++i) {
1351    if (IsPIC)
1352      // DestBB address - JT base.
1353      emitMachineBasicBlock(MBBs[i], ARM::reloc_arm_pic_jt, JTBase);
1354    else
1355      // Absolute DestBB address.
1356      emitMachineBasicBlock(MBBs[i], ARM::reloc_arm_absolute);
1357    emitWordLE(0);
1358  }
1359}
1360
1361void ARMCodeEmitter::emitMiscBranchInstruction(const MachineInstr &MI) {
1362  const TargetInstrDesc &TID = MI.getDesc();
1363
1364  // Handle jump tables.
1365  if (TID.Opcode == ARM::BR_JTr || TID.Opcode == ARM::BR_JTadd) {
1366    // First emit a ldr pc, [] instruction.
1367    emitDataProcessingInstruction(MI, ARM::PC);
1368
1369    // Then emit the inline jump table.
1370    unsigned JTIndex =
1371      (TID.Opcode == ARM::BR_JTr)
1372      ? MI.getOperand(1).getIndex() : MI.getOperand(2).getIndex();
1373    emitInlineJumpTable(JTIndex);
1374    return;
1375  } else if (TID.Opcode == ARM::BR_JTm) {
1376    // First emit a ldr pc, [] instruction.
1377    emitLoadStoreInstruction(MI, ARM::PC);
1378
1379    // Then emit the inline jump table.
1380    emitInlineJumpTable(MI.getOperand(3).getIndex());
1381    return;
1382  }
1383
1384  // Part of binary is determined by TableGn.
1385  unsigned Binary = getBinaryCodeForInstr(MI);
1386
1387  // Set the conditional execution predicate
1388  Binary |= II->getPredicate(&MI) << ARMII::CondShift;
1389
1390  if (TID.Opcode == ARM::BX_RET || TID.Opcode == ARM::MOVPCLR)
1391    // The return register is LR.
1392    Binary |= getARMRegisterNumbering(ARM::LR);
1393  else
1394    // otherwise, set the return register
1395    Binary |= getMachineOpValue(MI, 0);
1396
1397  emitWordLE(Binary);
1398}
1399
1400static unsigned encodeVFPRd(const MachineInstr &MI, unsigned OpIdx) {
1401  unsigned RegD = MI.getOperand(OpIdx).getReg();
1402  unsigned Binary = 0;
1403  bool isSPVFP = ARM::SPRRegisterClass->contains(RegD);
1404  RegD = getARMRegisterNumbering(RegD);
1405  if (!isSPVFP)
1406    Binary |=   RegD               << ARMII::RegRdShift;
1407  else {
1408    Binary |= ((RegD & 0x1E) >> 1) << ARMII::RegRdShift;
1409    Binary |=  (RegD & 0x01)       << ARMII::D_BitShift;
1410  }
1411  return Binary;
1412}
1413
1414static unsigned encodeVFPRn(const MachineInstr &MI, unsigned OpIdx) {
1415  unsigned RegN = MI.getOperand(OpIdx).getReg();
1416  unsigned Binary = 0;
1417  bool isSPVFP = ARM::SPRRegisterClass->contains(RegN);
1418  RegN = getARMRegisterNumbering(RegN);
1419  if (!isSPVFP)
1420    Binary |=   RegN               << ARMII::RegRnShift;
1421  else {
1422    Binary |= ((RegN & 0x1E) >> 1) << ARMII::RegRnShift;
1423    Binary |=  (RegN & 0x01)       << ARMII::N_BitShift;
1424  }
1425  return Binary;
1426}
1427
1428static unsigned encodeVFPRm(const MachineInstr &MI, unsigned OpIdx) {
1429  unsigned RegM = MI.getOperand(OpIdx).getReg();
1430  unsigned Binary = 0;
1431  bool isSPVFP = ARM::SPRRegisterClass->contains(RegM);
1432  RegM = getARMRegisterNumbering(RegM);
1433  if (!isSPVFP)
1434    Binary |=   RegM;
1435  else {
1436    Binary |= ((RegM & 0x1E) >> 1);
1437    Binary |=  (RegM & 0x01)       << ARMII::M_BitShift;
1438  }
1439  return Binary;
1440}
1441
1442void ARMCodeEmitter::emitVFPArithInstruction(const MachineInstr &MI) {
1443  const TargetInstrDesc &TID = MI.getDesc();
1444
1445  // Part of binary is determined by TableGn.
1446  unsigned Binary = getBinaryCodeForInstr(MI);
1447
1448  // Set the conditional execution predicate
1449  Binary |= II->getPredicate(&MI) << ARMII::CondShift;
1450
1451  unsigned OpIdx = 0;
1452  assert((Binary & ARMII::D_BitShift) == 0 &&
1453         (Binary & ARMII::N_BitShift) == 0 &&
1454         (Binary & ARMII::M_BitShift) == 0 && "VFP encoding bug!");
1455
1456  // Encode Dd / Sd.
1457  Binary |= encodeVFPRd(MI, OpIdx++);
1458
1459  // If this is a two-address operand, skip it, e.g. FMACD.
1460  if (TID.getOperandConstraint(OpIdx, TOI::TIED_TO) != -1)
1461    ++OpIdx;
1462
1463  // Encode Dn / Sn.
1464  if ((TID.TSFlags & ARMII::FormMask) == ARMII::VFPBinaryFrm)
1465    Binary |= encodeVFPRn(MI, OpIdx++);
1466
1467  if (OpIdx == TID.getNumOperands() ||
1468      TID.OpInfo[OpIdx].isPredicate() ||
1469      TID.OpInfo[OpIdx].isOptionalDef()) {
1470    // FCMPEZD etc. has only one operand.
1471    emitWordLE(Binary);
1472    return;
1473  }
1474
1475  // Encode Dm / Sm.
1476  Binary |= encodeVFPRm(MI, OpIdx);
1477
1478  emitWordLE(Binary);
1479}
1480
1481void ARMCodeEmitter::emitVFPConversionInstruction(const MachineInstr &MI) {
1482  const TargetInstrDesc &TID = MI.getDesc();
1483  unsigned Form = TID.TSFlags & ARMII::FormMask;
1484
1485  // Part of binary is determined by TableGn.
1486  unsigned Binary = getBinaryCodeForInstr(MI);
1487
1488  // Set the conditional execution predicate
1489  Binary |= II->getPredicate(&MI) << ARMII::CondShift;
1490
1491  switch (Form) {
1492  default: break;
1493  case ARMII::VFPConv1Frm:
1494  case ARMII::VFPConv2Frm:
1495  case ARMII::VFPConv3Frm:
1496    // Encode Dd / Sd.
1497    Binary |= encodeVFPRd(MI, 0);
1498    break;
1499  case ARMII::VFPConv4Frm:
1500    // Encode Dn / Sn.
1501    Binary |= encodeVFPRn(MI, 0);
1502    break;
1503  case ARMII::VFPConv5Frm:
1504    // Encode Dm / Sm.
1505    Binary |= encodeVFPRm(MI, 0);
1506    break;
1507  }
1508
1509  switch (Form) {
1510  default: break;
1511  case ARMII::VFPConv1Frm:
1512    // Encode Dm / Sm.
1513    Binary |= encodeVFPRm(MI, 1);
1514    break;
1515  case ARMII::VFPConv2Frm:
1516  case ARMII::VFPConv3Frm:
1517    // Encode Dn / Sn.
1518    Binary |= encodeVFPRn(MI, 1);
1519    break;
1520  case ARMII::VFPConv4Frm:
1521  case ARMII::VFPConv5Frm:
1522    // Encode Dd / Sd.
1523    Binary |= encodeVFPRd(MI, 1);
1524    break;
1525  }
1526
1527  if (Form == ARMII::VFPConv5Frm)
1528    // Encode Dn / Sn.
1529    Binary |= encodeVFPRn(MI, 2);
1530  else if (Form == ARMII::VFPConv3Frm)
1531    // Encode Dm / Sm.
1532    Binary |= encodeVFPRm(MI, 2);
1533
1534  emitWordLE(Binary);
1535}
1536
1537void ARMCodeEmitter::emitVFPLoadStoreInstruction(const MachineInstr &MI) {
1538  // Part of binary is determined by TableGn.
1539  unsigned Binary = getBinaryCodeForInstr(MI);
1540
1541  // Set the conditional execution predicate
1542  Binary |= II->getPredicate(&MI) << ARMII::CondShift;
1543
1544  unsigned OpIdx = 0;
1545
1546  // Encode Dd / Sd.
1547  Binary |= encodeVFPRd(MI, OpIdx++);
1548
1549  // Encode address base.
1550  const MachineOperand &Base = MI.getOperand(OpIdx++);
1551  Binary |= getMachineOpValue(MI, Base) << ARMII::RegRnShift;
1552
1553  // If there is a non-zero immediate offset, encode it.
1554  if (Base.isReg()) {
1555    const MachineOperand &Offset = MI.getOperand(OpIdx);
1556    if (unsigned ImmOffs = ARM_AM::getAM5Offset(Offset.getImm())) {
1557      if (ARM_AM::getAM5Op(Offset.getImm()) == ARM_AM::add)
1558        Binary |= 1 << ARMII::U_BitShift;
1559      Binary |= ImmOffs;
1560      emitWordLE(Binary);
1561      return;
1562    }
1563  }
1564
1565  // If immediate offset is omitted, default to +0.
1566  Binary |= 1 << ARMII::U_BitShift;
1567
1568  emitWordLE(Binary);
1569}
1570
1571void
1572ARMCodeEmitter::emitVFPLoadStoreMultipleInstruction(const MachineInstr &MI) {
1573  const TargetInstrDesc &TID = MI.getDesc();
1574  bool IsUpdating = (TID.TSFlags & ARMII::IndexModeMask) != 0;
1575
1576  // Part of binary is determined by TableGn.
1577  unsigned Binary = getBinaryCodeForInstr(MI);
1578
1579  // Set the conditional execution predicate
1580  Binary |= II->getPredicate(&MI) << ARMII::CondShift;
1581
1582  // Skip operand 0 of an instruction with base register update.
1583  unsigned OpIdx = 0;
1584  if (IsUpdating)
1585    ++OpIdx;
1586
1587  // Set base address operand
1588  Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRnShift;
1589
1590  // Set addressing mode by modifying bits U(23) and P(24)
1591  const MachineOperand &MO = MI.getOperand(OpIdx++);
1592  Binary |= getAddrModeUPBits(ARM_AM::getAM4SubMode(MO.getImm()));
1593
1594  // Set bit W(21)
1595  if (IsUpdating)
1596    Binary |= 0x1 << ARMII::W_BitShift;
1597
1598  // First register is encoded in Dd.
1599  Binary |= encodeVFPRd(MI, OpIdx+2);
1600
1601  // Count the number of registers.
1602  unsigned NumRegs = 1;
1603  for (unsigned i = OpIdx+3, e = MI.getNumOperands(); i != e; ++i) {
1604    const MachineOperand &MO = MI.getOperand(i);
1605    if (!MO.isReg() || MO.isImplicit())
1606      break;
1607    ++NumRegs;
1608  }
1609  // Bit 8 will be set if <list> is consecutive 64-bit registers (e.g., D0)
1610  // Otherwise, it will be 0, in the case of 32-bit registers.
1611  if(Binary & 0x100)
1612    Binary |= NumRegs * 2;
1613  else
1614    Binary |= NumRegs;
1615
1616  emitWordLE(Binary);
1617}
1618
1619static unsigned encodeNEONRd(const MachineInstr &MI, unsigned OpIdx) {
1620  unsigned RegD = MI.getOperand(OpIdx).getReg();
1621  unsigned Binary = 0;
1622  RegD = getARMRegisterNumbering(RegD);
1623  Binary |= (RegD & 0xf) << ARMII::RegRdShift;
1624  Binary |= ((RegD >> 4) & 1) << ARMII::D_BitShift;
1625  return Binary;
1626}
1627
1628static unsigned encodeNEONRn(const MachineInstr &MI, unsigned OpIdx) {
1629  unsigned RegN = MI.getOperand(OpIdx).getReg();
1630  unsigned Binary = 0;
1631  RegN = getARMRegisterNumbering(RegN);
1632  Binary |= (RegN & 0xf) << ARMII::RegRnShift;
1633  Binary |= ((RegN >> 4) & 1) << ARMII::N_BitShift;
1634  return Binary;
1635}
1636
1637static unsigned encodeNEONRm(const MachineInstr &MI, unsigned OpIdx) {
1638  unsigned RegM = MI.getOperand(OpIdx).getReg();
1639  unsigned Binary = 0;
1640  RegM = getARMRegisterNumbering(RegM);
1641  Binary |= (RegM & 0xf);
1642  Binary |= ((RegM >> 4) & 1) << ARMII::M_BitShift;
1643  return Binary;
1644}
1645
1646/// convertNEONDataProcToThumb - Convert the ARM mode encoding for a NEON
1647/// data-processing instruction to the corresponding Thumb encoding.
1648static unsigned convertNEONDataProcToThumb(unsigned Binary) {
1649  assert((Binary & 0xfe000000) == 0xf2000000 &&
1650         "not an ARM NEON data-processing instruction");
1651  unsigned UBit = (Binary >> 24) & 1;
1652  return 0xef000000 | (UBit << 28) | (Binary & 0xffffff);
1653}
1654
1655void ARMCodeEmitter::emitNEONLaneInstruction(const MachineInstr &MI) {
1656  unsigned Binary = getBinaryCodeForInstr(MI);
1657
1658  unsigned RegTOpIdx, RegNOpIdx, LnOpIdx;
1659  const TargetInstrDesc &TID = MI.getDesc();
1660  if ((TID.TSFlags & ARMII::FormMask) == ARMII::NGetLnFrm) {
1661    RegTOpIdx = 0;
1662    RegNOpIdx = 1;
1663    LnOpIdx = 2;
1664  } else { // ARMII::NSetLnFrm
1665    RegTOpIdx = 2;
1666    RegNOpIdx = 0;
1667    LnOpIdx = 3;
1668  }
1669
1670  // Set the conditional execution predicate
1671  Binary |= (IsThumb ? ARMCC::AL : II->getPredicate(&MI)) << ARMII::CondShift;
1672
1673  unsigned RegT = MI.getOperand(RegTOpIdx).getReg();
1674  RegT = getARMRegisterNumbering(RegT);
1675  Binary |= (RegT << ARMII::RegRdShift);
1676  Binary |= encodeNEONRn(MI, RegNOpIdx);
1677
1678  unsigned LaneShift;
1679  if ((Binary & (1 << 22)) != 0)
1680    LaneShift = 0; // 8-bit elements
1681  else if ((Binary & (1 << 5)) != 0)
1682    LaneShift = 1; // 16-bit elements
1683  else
1684    LaneShift = 2; // 32-bit elements
1685
1686  unsigned Lane = MI.getOperand(LnOpIdx).getImm() << LaneShift;
1687  unsigned Opc1 = Lane >> 2;
1688  unsigned Opc2 = Lane & 3;
1689  assert((Opc1 & 3) == 0 && "out-of-range lane number operand");
1690  Binary |= (Opc1 << 21);
1691  Binary |= (Opc2 << 5);
1692
1693  emitWordLE(Binary);
1694}
1695
1696void ARMCodeEmitter::emitNEONDupInstruction(const MachineInstr &MI) {
1697  unsigned Binary = getBinaryCodeForInstr(MI);
1698
1699  // Set the conditional execution predicate
1700  Binary |= (IsThumb ? ARMCC::AL : II->getPredicate(&MI)) << ARMII::CondShift;
1701
1702  unsigned RegT = MI.getOperand(1).getReg();
1703  RegT = getARMRegisterNumbering(RegT);
1704  Binary |= (RegT << ARMII::RegRdShift);
1705  Binary |= encodeNEONRn(MI, 0);
1706  emitWordLE(Binary);
1707}
1708
1709void ARMCodeEmitter::emitNEON1RegModImmInstruction(const MachineInstr &MI) {
1710  unsigned Binary = getBinaryCodeForInstr(MI);
1711  // Destination register is encoded in Dd.
1712  Binary |= encodeNEONRd(MI, 0);
1713  // Immediate fields: Op, Cmode, I, Imm3, Imm4
1714  unsigned Imm = MI.getOperand(1).getImm();
1715  unsigned Op = (Imm >> 12) & 1;
1716  unsigned Cmode = (Imm >> 8) & 0xf;
1717  unsigned I = (Imm >> 7) & 1;
1718  unsigned Imm3 = (Imm >> 4) & 0x7;
1719  unsigned Imm4 = Imm & 0xf;
1720  Binary |= (I << 24) | (Imm3 << 16) | (Cmode << 8) | (Op << 5) | Imm4;
1721  if (IsThumb)
1722    Binary = convertNEONDataProcToThumb(Binary);
1723  emitWordLE(Binary);
1724}
1725
1726void ARMCodeEmitter::emitNEON2RegInstruction(const MachineInstr &MI) {
1727  const TargetInstrDesc &TID = MI.getDesc();
1728  unsigned Binary = getBinaryCodeForInstr(MI);
1729  // Destination register is encoded in Dd; source register in Dm.
1730  unsigned OpIdx = 0;
1731  Binary |= encodeNEONRd(MI, OpIdx++);
1732  if (TID.getOperandConstraint(OpIdx, TOI::TIED_TO) != -1)
1733    ++OpIdx;
1734  Binary |= encodeNEONRm(MI, OpIdx);
1735  if (IsThumb)
1736    Binary = convertNEONDataProcToThumb(Binary);
1737  // FIXME: This does not handle VDUPfdf or VDUPfqf.
1738  emitWordLE(Binary);
1739}
1740
1741void ARMCodeEmitter::emitNEON3RegInstruction(const MachineInstr &MI) {
1742  const TargetInstrDesc &TID = MI.getDesc();
1743  unsigned Binary = getBinaryCodeForInstr(MI);
1744  // Destination register is encoded in Dd; source registers in Dn and Dm.
1745  unsigned OpIdx = 0;
1746  Binary |= encodeNEONRd(MI, OpIdx++);
1747  if (TID.getOperandConstraint(OpIdx, TOI::TIED_TO) != -1)
1748    ++OpIdx;
1749  Binary |= encodeNEONRn(MI, OpIdx++);
1750  if (TID.getOperandConstraint(OpIdx, TOI::TIED_TO) != -1)
1751    ++OpIdx;
1752  Binary |= encodeNEONRm(MI, OpIdx);
1753  if (IsThumb)
1754    Binary = convertNEONDataProcToThumb(Binary);
1755  // FIXME: This does not handle VMOVDneon or VMOVQ.
1756  emitWordLE(Binary);
1757}
1758
1759#include "ARMGenCodeEmitter.inc"
1760