ARMCodeEmitter.cpp revision cd8e66a1efdb31f0514270387207fb8c63bae4ed 
1//===-- ARM/ARMCodeEmitter.cpp - Convert ARM code to machine code ---------===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file contains the pass that transforms the ARM machine instructions into
11// relocatable machine code.
12//
13//===----------------------------------------------------------------------===//
14
15#define DEBUG_TYPE "jit"
16#include "ARM.h"
17#include "ARMAddressingModes.h"
18#include "ARMConstantPoolValue.h"
19#include "ARMInstrInfo.h"
20#include "ARMRelocations.h"
21#include "ARMSubtarget.h"
22#include "ARMTargetMachine.h"
23#include "llvm/Constants.h"
24#include "llvm/DerivedTypes.h"
25#include "llvm/Function.h"
26#include "llvm/PassManager.h"
27#include "llvm/CodeGen/MachineCodeEmitter.h"
28#include "llvm/CodeGen/MachineConstantPool.h"
29#include "llvm/CodeGen/MachineFunctionPass.h"
30#include "llvm/CodeGen/MachineInstr.h"
31#include "llvm/CodeGen/MachineJumpTableInfo.h"
32#include "llvm/CodeGen/Passes.h"
33#include "llvm/ADT/Statistic.h"
34#include "llvm/Support/Compiler.h"
35#include "llvm/Support/Debug.h"
36#ifndef NDEBUG
37#include <iomanip>
38#endif
39using namespace llvm;
40
41STATISTIC(NumEmitted, "Number of machine instructions emitted");
42
43namespace {
44  class VISIBILITY_HIDDEN ARMCodeEmitter : public MachineFunctionPass {
45    ARMJITInfo                *JTI;
46    const ARMInstrInfo        *II;
47    const TargetData          *TD;
48    TargetMachine             &TM;
49    MachineCodeEmitter        &MCE;
50    const std::vector<MachineConstantPoolEntry> *MCPEs;
51    const std::vector<MachineJumpTableEntry> *MJTEs;
52    bool IsPIC;
53
54  public:
55    static char ID;
56    explicit ARMCodeEmitter(TargetMachine &tm, MachineCodeEmitter &mce)
57      : MachineFunctionPass(&ID), JTI(0), II(0), TD(0), TM(tm),
58      MCE(mce), MCPEs(0), MJTEs(0),
59      IsPIC(TM.getRelocationModel() == Reloc::PIC_) {}
60    ARMCodeEmitter(TargetMachine &tm, MachineCodeEmitter &mce,
61            const ARMInstrInfo &ii, const TargetData &td)
62      : MachineFunctionPass(&ID), JTI(0), II(&ii), TD(&td), TM(tm),
63      MCE(mce), MCPEs(0), MJTEs(0),
64      IsPIC(TM.getRelocationModel() == Reloc::PIC_) {}
65
66    bool runOnMachineFunction(MachineFunction &MF);
67
68    virtual const char *getPassName() const {
69      return "ARM Machine Code Emitter";
70    }
71
72    void emitInstruction(const MachineInstr &MI);
73
74  private:
75
76    void emitWordLE(unsigned Binary);
77
78    void emitConstPoolInstruction(const MachineInstr &MI);
79
80    void emitMOVi2piecesInstruction(const MachineInstr &MI);
81
82    void emitLEApcrelJTInstruction(const MachineInstr &MI);
83
84    void addPCLabel(unsigned LabelID);
85
86    void emitPseudoInstruction(const MachineInstr &MI);
87
88    unsigned getMachineSoRegOpValue(const MachineInstr &MI,
89                                    const TargetInstrDesc &TID,
90                                    const MachineOperand &MO,
91                                    unsigned OpIdx);
92
93    unsigned getMachineSoImmOpValue(unsigned SoImm);
94
95    unsigned getAddrModeSBit(const MachineInstr &MI,
96                             const TargetInstrDesc &TID) const;
97
98    void emitDataProcessingInstruction(const MachineInstr &MI,
99                                       unsigned ImplicitRd = 0,
100                                       unsigned ImplicitRn = 0);
101
102    void emitLoadStoreInstruction(const MachineInstr &MI,
103                                  unsigned ImplicitRd = 0,
104                                  unsigned ImplicitRn = 0);
105
106    void emitMiscLoadStoreInstruction(const MachineInstr &MI,
107                                      unsigned ImplicitRn = 0);
108
109    void emitLoadStoreMultipleInstruction(const MachineInstr &MI);
110
111    void emitMulFrmInstruction(const MachineInstr &MI);
112
113    void emitExtendInstruction(const MachineInstr &MI);
114
115    void emitMiscArithInstruction(const MachineInstr &MI);
116
117    void emitBranchInstruction(const MachineInstr &MI);
118
119    void emitInlineJumpTable(unsigned JTIndex);
120
121    void emitMiscBranchInstruction(const MachineInstr &MI);
122
123    void emitVFPArithInstruction(const MachineInstr &MI);
124
125    void emitVFPConversionInstruction(const MachineInstr &MI);
126
127    void emitVFPLoadStoreInstruction(const MachineInstr &MI);
128
129    void emitVFPLoadStoreMultipleInstruction(const MachineInstr &MI);
130
131    void emitMiscInstruction(const MachineInstr &MI);
132
133    /// getBinaryCodeForInstr - This function, generated by the
134    /// CodeEmitterGenerator using TableGen, produces the binary encoding for
135    /// machine instructions.
136    ///
137    unsigned getBinaryCodeForInstr(const MachineInstr &MI);
138
139    /// getMachineOpValue - Return binary encoding of operand. If the machine
140    /// operand requires relocation, record the relocation and return zero.
141    unsigned getMachineOpValue(const MachineInstr &MI,const MachineOperand &MO);
142    unsigned getMachineOpValue(const MachineInstr &MI, unsigned OpIdx) {
143      return getMachineOpValue(MI, MI.getOperand(OpIdx));
144    }
145
146    /// getShiftOp - Return the shift opcode (bit[6:5]) of the immediate value.
147    ///
148    unsigned getShiftOp(unsigned Imm) const ;
149
150    /// Routines that handle operands which add machine relocations which are
151    /// fixed up by the relocation stage.
152    void emitGlobalAddress(GlobalValue *GV, unsigned Reloc,
153                           bool NeedStub, intptr_t ACPV = 0);
154    void emitExternalSymbolAddress(const char *ES, unsigned Reloc);
155    void emitConstPoolAddress(unsigned CPI, unsigned Reloc);
156    void emitJumpTableAddress(unsigned JTIndex, unsigned Reloc);
157    void emitMachineBasicBlock(MachineBasicBlock *BB, unsigned Reloc,
158                               intptr_t JTBase = 0);
159  };
160  char ARMCodeEmitter::ID = 0;
161}
162
163/// createARMCodeEmitterPass - Return a pass that emits the collected ARM code
164/// to the specified MCE object.
165FunctionPass *llvm::createARMCodeEmitterPass(ARMTargetMachine &TM,
166                                             MachineCodeEmitter &MCE) {
167  return new ARMCodeEmitter(TM, MCE);
168}
169
170bool ARMCodeEmitter::runOnMachineFunction(MachineFunction &MF) {
171  assert((MF.getTarget().getRelocationModel() != Reloc::Default ||
172          MF.getTarget().getRelocationModel() != Reloc::Static) &&
173         "JIT relocation model must be set to static or default!");
174  II = ((ARMTargetMachine&)MF.getTarget()).getInstrInfo();
175  TD = ((ARMTargetMachine&)MF.getTarget()).getTargetData();
176  JTI = ((ARMTargetMachine&)MF.getTarget()).getJITInfo();
177  MCPEs = &MF.getConstantPool()->getConstants();
178  MJTEs = &MF.getJumpTableInfo()->getJumpTables();
179  IsPIC = TM.getRelocationModel() == Reloc::PIC_;
180  JTI->Initialize(MF, IsPIC);
181
182  do {
183    DOUT << "JITTing function '" << MF.getFunction()->getName() << "'\n";
184    MCE.startFunction(MF);
185    for (MachineFunction::iterator MBB = MF.begin(), E = MF.end();
186         MBB != E; ++MBB) {
187      MCE.StartMachineBasicBlock(MBB);
188      for (MachineBasicBlock::const_iterator I = MBB->begin(), E = MBB->end();
189           I != E; ++I)
190        emitInstruction(*I);
191    }
192  } while (MCE.finishFunction(MF));
193
194  return false;
195}
196
197/// getShiftOp - Return the shift opcode (bit[6:5]) of the immediate value.
198///
199unsigned ARMCodeEmitter::getShiftOp(unsigned Imm) const {
200  switch (ARM_AM::getAM2ShiftOpc(Imm)) {
201  default: assert(0 && "Unknown shift opc!");
202  case ARM_AM::asr: return 2;
203  case ARM_AM::lsl: return 0;
204  case ARM_AM::lsr: return 1;
205  case ARM_AM::ror:
206  case ARM_AM::rrx: return 3;
207  }
208  return 0;
209}
210
211/// getMachineOpValue - Return binary encoding of operand. If the machine
212/// operand requires relocation, record the relocation and return zero.
213unsigned ARMCodeEmitter::getMachineOpValue(const MachineInstr &MI,
214                                           const MachineOperand &MO) {
215  if (MO.isReg())
216    return ARMRegisterInfo::getRegisterNumbering(MO.getReg());
217  else if (MO.isImm())
218    return static_cast<unsigned>(MO.getImm());
219  else if (MO.isGlobal())
220    emitGlobalAddress(MO.getGlobal(), ARM::reloc_arm_branch, true);
221  else if (MO.isSymbol())
222    emitExternalSymbolAddress(MO.getSymbolName(), ARM::reloc_arm_branch);
223  else if (MO.isCPI())
224    emitConstPoolAddress(MO.getIndex(), ARM::reloc_arm_cp_entry);
225  else if (MO.isJTI())
226    emitJumpTableAddress(MO.getIndex(), ARM::reloc_arm_relative);
227  else if (MO.isMBB())
228    emitMachineBasicBlock(MO.getMBB(), ARM::reloc_arm_branch);
229  else {
230    cerr << "ERROR: Unknown type of MachineOperand: " << MO << "\n";
231    abort();
232  }
233  return 0;
234}
235
236/// emitGlobalAddress - Emit the specified address to the code stream.
237///
238void ARMCodeEmitter::emitGlobalAddress(GlobalValue *GV, unsigned Reloc,
239                                       bool NeedStub, intptr_t ACPV) {
240  MCE.addRelocation(MachineRelocation::getGV(MCE.getCurrentPCOffset(),
241                                             Reloc, GV, ACPV, NeedStub));
242}
243
244/// emitExternalSymbolAddress - Arrange for the address of an external symbol to
245/// be emitted to the current location in the function, and allow it to be PC
246/// relative.
247void ARMCodeEmitter::emitExternalSymbolAddress(const char *ES, unsigned Reloc) {
248  MCE.addRelocation(MachineRelocation::getExtSym(MCE.getCurrentPCOffset(),
249                                                 Reloc, ES));
250}
251
252/// emitConstPoolAddress - Arrange for the address of an constant pool
253/// to be emitted to the current location in the function, and allow it to be PC
254/// relative.
255void ARMCodeEmitter::emitConstPoolAddress(unsigned CPI, unsigned Reloc) {
256  // Tell JIT emitter we'll resolve the address.
257  MCE.addRelocation(MachineRelocation::getConstPool(MCE.getCurrentPCOffset(),
258                                                    Reloc, CPI, 0, true));
259}
260
261/// emitJumpTableAddress - Arrange for the address of a jump table to
262/// be emitted to the current location in the function, and allow it to be PC
263/// relative.
264void ARMCodeEmitter::emitJumpTableAddress(unsigned JTIndex, unsigned Reloc) {
265  MCE.addRelocation(MachineRelocation::getJumpTable(MCE.getCurrentPCOffset(),
266                                                    Reloc, JTIndex, 0, true));
267}
268
269/// emitMachineBasicBlock - Emit the specified address basic block.
270void ARMCodeEmitter::emitMachineBasicBlock(MachineBasicBlock *BB,
271                                           unsigned Reloc, intptr_t JTBase) {
272  MCE.addRelocation(MachineRelocation::getBB(MCE.getCurrentPCOffset(),
273                                             Reloc, BB, JTBase));
274}
275
276void ARMCodeEmitter::emitWordLE(unsigned Binary) {
277#ifndef NDEBUG
278  DOUT << "  0x" << std::hex << std::setw(8) << std::setfill('0')
279       << Binary << std::dec << "\n";
280#endif
281  MCE.emitWordLE(Binary);
282}
283
284void ARMCodeEmitter::emitInstruction(const MachineInstr &MI) {
285  DOUT << "JIT: " << (void*)MCE.getCurrentPCValue() << ":\t" << MI;
286
287  NumEmitted++;  // Keep track of the # of mi's emitted
288  switch (MI.getDesc().TSFlags & ARMII::FormMask) {
289  default:
290    assert(0 && "Unhandled instruction encoding format!");
291    break;
292  case ARMII::Pseudo:
293    emitPseudoInstruction(MI);
294    break;
295  case ARMII::DPFrm:
296  case ARMII::DPSoRegFrm:
297    emitDataProcessingInstruction(MI);
298    break;
299  case ARMII::LdFrm:
300  case ARMII::StFrm:
301    emitLoadStoreInstruction(MI);
302    break;
303  case ARMII::LdMiscFrm:
304  case ARMII::StMiscFrm:
305    emitMiscLoadStoreInstruction(MI);
306    break;
307  case ARMII::LdMulFrm:
308  case ARMII::StMulFrm:
309    emitLoadStoreMultipleInstruction(MI);
310    break;
311  case ARMII::MulFrm:
312    emitMulFrmInstruction(MI);
313    break;
314  case ARMII::ExtFrm:
315    emitExtendInstruction(MI);
316    break;
317  case ARMII::ArithMiscFrm:
318    emitMiscArithInstruction(MI);
319    break;
320  case ARMII::BrFrm:
321    emitBranchInstruction(MI);
322    break;
323  case ARMII::BrMiscFrm:
324    emitMiscBranchInstruction(MI);
325    break;
326  // VFP instructions.
327  case ARMII::VFPUnaryFrm:
328  case ARMII::VFPBinaryFrm:
329    emitVFPArithInstruction(MI);
330    break;
331  case ARMII::VFPConv1Frm:
332  case ARMII::VFPConv2Frm:
333    emitVFPConversionInstruction(MI);
334    break;
335  case ARMII::VFPLdStFrm:
336    emitVFPLoadStoreInstruction(MI);
337    break;
338  case ARMII::VFPLdStMulFrm:
339    emitVFPLoadStoreMultipleInstruction(MI);
340    break;
341  case ARMII::VFPMiscFrm:
342    emitMiscInstruction(MI);
343    break;
344  }
345}
346
347void ARMCodeEmitter::emitConstPoolInstruction(const MachineInstr &MI) {
348  unsigned CPI = MI.getOperand(0).getImm();       // CP instruction index.
349  unsigned CPIndex = MI.getOperand(1).getIndex(); // Actual cp entry index.
350  const MachineConstantPoolEntry &MCPE = (*MCPEs)[CPIndex];
351
352  // Remember the CONSTPOOL_ENTRY address for later relocation.
353  JTI->addConstantPoolEntryAddr(CPI, MCE.getCurrentPCValue());
354
355  // Emit constpool island entry. In most cases, the actual values will be
356  // resolved and relocated after code emission.
357  if (MCPE.isMachineConstantPoolEntry()) {
358    ARMConstantPoolValue *ACPV =
359      static_cast<ARMConstantPoolValue*>(MCPE.Val.MachineCPVal);
360
361    DOUT << "  ** ARM constant pool #" << CPI << " @ "
362         << (void*)MCE.getCurrentPCValue() << " " << *ACPV << '\n';
363
364    GlobalValue *GV = ACPV->getGV();
365    if (GV) {
366      assert(!ACPV->isStub() && "Don't know how to deal this yet!");
367      if (ACPV->isNonLazyPointer())
368        MCE.addRelocation(MachineRelocation::getIndirectSymbol(
369                  MCE.getCurrentPCOffset(), ARM::reloc_arm_machine_cp_entry, GV,
370                  (intptr_t)ACPV, false));
371      else
372        emitGlobalAddress(GV, ARM::reloc_arm_machine_cp_entry,
373                          ACPV->isStub(), (intptr_t)ACPV);
374     } else  {
375      assert(!ACPV->isNonLazyPointer() && "Don't know how to deal this yet!");
376      emitExternalSymbolAddress(ACPV->getSymbol(), ARM::reloc_arm_absolute);
377    }
378    emitWordLE(0);
379  } else {
380    Constant *CV = MCPE.Val.ConstVal;
381
382    DOUT << "  ** Constant pool #" << CPI << " @ "
383         << (void*)MCE.getCurrentPCValue() << " " << *CV << '\n';
384
385    if (GlobalValue *GV = dyn_cast<GlobalValue>(CV)) {
386      emitGlobalAddress(GV, ARM::reloc_arm_absolute, false);
387      emitWordLE(0);
388    } else {
389      assert(CV->getType()->isInteger() &&
390             "Not expecting non-integer constpool entries yet!");
391      const ConstantInt *CI = dyn_cast<ConstantInt>(CV);
392      uint32_t Val = *(uint32_t*)CI->getValue().getRawData();
393      emitWordLE(Val);
394    }
395  }
396}
397
398void ARMCodeEmitter::emitMOVi2piecesInstruction(const MachineInstr &MI) {
399  const MachineOperand &MO0 = MI.getOperand(0);
400  const MachineOperand &MO1 = MI.getOperand(1);
401  assert(MO1.isImm() && "Not a valid so_imm value!");
402  unsigned V1 = ARM_AM::getSOImmTwoPartFirst(MO1.getImm());
403  unsigned V2 = ARM_AM::getSOImmTwoPartSecond(MO1.getImm());
404
405  // Emit the 'mov' instruction.
406  unsigned Binary = 0xd << 21;  // mov: Insts{24-21} = 0b1101
407
408  // Set the conditional execution predicate.
409  Binary |= II->getPredicate(&MI) << ARMII::CondShift;
410
411  // Encode Rd.
412  Binary |= getMachineOpValue(MI, MO0) << ARMII::RegRdShift;
413
414  // Encode so_imm.
415  // Set bit I(25) to identify this is the immediate form of <shifter_op>
416  Binary |= 1 << ARMII::I_BitShift;
417  Binary |= getMachineSoImmOpValue(ARM_AM::getSOImmVal(V1));
418  emitWordLE(Binary);
419
420  // Now the 'orr' instruction.
421  Binary = 0xc << 21;  // orr: Insts{24-21} = 0b1100
422
423  // Set the conditional execution predicate.
424  Binary |= II->getPredicate(&MI) << ARMII::CondShift;
425
426  // Encode Rd.
427  Binary |= getMachineOpValue(MI, MO0) << ARMII::RegRdShift;
428
429  // Encode Rn.
430  Binary |= getMachineOpValue(MI, MO0) << ARMII::RegRnShift;
431
432  // Encode so_imm.
433  // Set bit I(25) to identify this is the immediate form of <shifter_op>
434  Binary |= 1 << ARMII::I_BitShift;
435  Binary |= getMachineSoImmOpValue(ARM_AM::getSOImmVal(V2));
436  emitWordLE(Binary);
437}
438
439void ARMCodeEmitter::emitLEApcrelJTInstruction(const MachineInstr &MI) {
440  // It's basically add r, pc, (LJTI - $+8)
441
442  const TargetInstrDesc &TID = MI.getDesc();
443
444  // Emit the 'add' instruction.
445  unsigned Binary = 0x4 << 21;  // add: Insts{24-31} = 0b0100
446
447  // Set the conditional execution predicate
448  Binary |= II->getPredicate(&MI) << ARMII::CondShift;
449
450  // Encode S bit if MI modifies CPSR.
451  Binary |= getAddrModeSBit(MI, TID);
452
453  // Encode Rd.
454  Binary |= getMachineOpValue(MI, 0) << ARMII::RegRdShift;
455
456  // Encode Rn which is PC.
457  Binary |= ARMRegisterInfo::getRegisterNumbering(ARM::PC) << ARMII::RegRnShift;
458
459  // Encode the displacement.
460  // Set bit I(25) to identify this is the immediate form of <shifter_op>.
461  Binary |= 1 << ARMII::I_BitShift;
462  emitJumpTableAddress(MI.getOperand(1).getIndex(), ARM::reloc_arm_jt_base);
463
464  emitWordLE(Binary);
465}
466
467void ARMCodeEmitter::addPCLabel(unsigned LabelID) {
468  DOUT << "  ** LPC" << LabelID << " @ "
469       << (void*)MCE.getCurrentPCValue() << '\n';
470  JTI->addPCLabelAddr(LabelID, MCE.getCurrentPCValue());
471}
472
473void ARMCodeEmitter::emitPseudoInstruction(const MachineInstr &MI) {
474  unsigned Opcode = MI.getDesc().Opcode;
475  switch (Opcode) {
476  default:
477    abort(); // FIXME:
478  case ARM::CONSTPOOL_ENTRY:
479    emitConstPoolInstruction(MI);
480    break;
481  case ARM::PICADD: {
482    // Remember of the address of the PC label for relocation later.
483    addPCLabel(MI.getOperand(2).getImm());
484    // PICADD is just an add instruction that implicitly read pc.
485    emitDataProcessingInstruction(MI, 0, ARM::PC);
486    break;
487  }
488  case ARM::PICLDR:
489  case ARM::PICLDRB:
490  case ARM::PICSTR:
491  case ARM::PICSTRB: {
492    // Remember of the address of the PC label for relocation later.
493    addPCLabel(MI.getOperand(2).getImm());
494    // These are just load / store instructions that implicitly read pc.
495    emitLoadStoreInstruction(MI, 0, ARM::PC);
496    break;
497  }
498  case ARM::PICLDRH:
499  case ARM::PICLDRSH:
500  case ARM::PICLDRSB:
501  case ARM::PICSTRH: {
502    // Remember of the address of the PC label for relocation later.
503    addPCLabel(MI.getOperand(2).getImm());
504    // These are just load / store instructions that implicitly read pc.
505    emitMiscLoadStoreInstruction(MI, ARM::PC);
506    break;
507  }
508  case ARM::MOVi2pieces:
509    // Two instructions to materialize a constant.
510    emitMOVi2piecesInstruction(MI);
511    break;
512  case ARM::LEApcrelJT:
513    // Materialize jumptable address.
514    emitLEApcrelJTInstruction(MI);
515    break;
516  }
517}
518
519
520unsigned ARMCodeEmitter::getMachineSoRegOpValue(const MachineInstr &MI,
521                                                const TargetInstrDesc &TID,
522                                                const MachineOperand &MO,
523                                                unsigned OpIdx) {
524  unsigned Binary = getMachineOpValue(MI, MO);
525
526  const MachineOperand &MO1 = MI.getOperand(OpIdx + 1);
527  const MachineOperand &MO2 = MI.getOperand(OpIdx + 2);
528  ARM_AM::ShiftOpc SOpc = ARM_AM::getSORegShOp(MO2.getImm());
529
530  // Encode the shift opcode.
531  unsigned SBits = 0;
532  unsigned Rs = MO1.getReg();
533  if (Rs) {
534    // Set shift operand (bit[7:4]).
535    // LSL - 0001
536    // LSR - 0011
537    // ASR - 0101
538    // ROR - 0111
539    // RRX - 0110 and bit[11:8] clear.
540    switch (SOpc) {
541    default: assert(0 && "Unknown shift opc!");
542    case ARM_AM::lsl: SBits = 0x1; break;
543    case ARM_AM::lsr: SBits = 0x3; break;
544    case ARM_AM::asr: SBits = 0x5; break;
545    case ARM_AM::ror: SBits = 0x7; break;
546    case ARM_AM::rrx: SBits = 0x6; break;
547    }
548  } else {
549    // Set shift operand (bit[6:4]).
550    // LSL - 000
551    // LSR - 010
552    // ASR - 100
553    // ROR - 110
554    switch (SOpc) {
555    default: assert(0 && "Unknown shift opc!");
556    case ARM_AM::lsl: SBits = 0x0; break;
557    case ARM_AM::lsr: SBits = 0x2; break;
558    case ARM_AM::asr: SBits = 0x4; break;
559    case ARM_AM::ror: SBits = 0x6; break;
560    }
561  }
562  Binary |= SBits << 4;
563  if (SOpc == ARM_AM::rrx)
564    return Binary;
565
566  // Encode the shift operation Rs or shift_imm (except rrx).
567  if (Rs) {
568    // Encode Rs bit[11:8].
569    assert(ARM_AM::getSORegOffset(MO2.getImm()) == 0);
570    return Binary |
571      (ARMRegisterInfo::getRegisterNumbering(Rs) << ARMII::RegRsShift);
572  }
573
574  // Encode shift_imm bit[11:7].
575  return Binary | ARM_AM::getSORegOffset(MO2.getImm()) << 7;
576}
577
578unsigned ARMCodeEmitter::getMachineSoImmOpValue(unsigned SoImm) {
579  // Encode rotate_imm.
580  unsigned Binary = (ARM_AM::getSOImmValRot(SoImm) >> 1)
581    << ARMII::SoRotImmShift;
582
583  // Encode immed_8.
584  Binary |= ARM_AM::getSOImmValImm(SoImm);
585  return Binary;
586}
587
588unsigned ARMCodeEmitter::getAddrModeSBit(const MachineInstr &MI,
589                                         const TargetInstrDesc &TID) const {
590  for (unsigned i = MI.getNumOperands(), e = TID.getNumOperands(); i != e; --i){
591    const MachineOperand &MO = MI.getOperand(i-1);
592    if (MO.isReg() && MO.isDef() && MO.getReg() == ARM::CPSR)
593      return 1 << ARMII::S_BitShift;
594  }
595  return 0;
596}
597
598void ARMCodeEmitter::emitDataProcessingInstruction(const MachineInstr &MI,
599                                                   unsigned ImplicitRd,
600                                                   unsigned ImplicitRn) {
601  const TargetInstrDesc &TID = MI.getDesc();
602
603  // Part of binary is determined by TableGn.
604  unsigned Binary = getBinaryCodeForInstr(MI);
605
606  // Set the conditional execution predicate
607  Binary |= II->getPredicate(&MI) << ARMII::CondShift;
608
609  // Encode S bit if MI modifies CPSR.
610  Binary |= getAddrModeSBit(MI, TID);
611
612  // Encode register def if there is one.
613  unsigned NumDefs = TID.getNumDefs();
614  unsigned OpIdx = 0;
615  if (NumDefs)
616    Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRdShift;
617  else if (ImplicitRd)
618    // Special handling for implicit use (e.g. PC).
619    Binary |= (ARMRegisterInfo::getRegisterNumbering(ImplicitRd)
620               << ARMII::RegRdShift);
621
622  // If this is a two-address operand, skip it. e.g. MOVCCr operand 1.
623  if (TID.getOperandConstraint(OpIdx, TOI::TIED_TO) != -1)
624    ++OpIdx;
625
626  // Encode first non-shifter register operand if there is one.
627  bool isUnary = TID.TSFlags & ARMII::UnaryDP;
628  if (!isUnary) {
629    if (ImplicitRn)
630      // Special handling for implicit use (e.g. PC).
631      Binary |= (ARMRegisterInfo::getRegisterNumbering(ImplicitRn)
632                 << ARMII::RegRnShift);
633    else {
634      Binary |= getMachineOpValue(MI, OpIdx) << ARMII::RegRnShift;
635      ++OpIdx;
636    }
637  }
638
639  // Encode shifter operand.
640  const MachineOperand &MO = MI.getOperand(OpIdx);
641  if ((TID.TSFlags & ARMII::FormMask) == ARMII::DPSoRegFrm) {
642    // Encode SoReg.
643    emitWordLE(Binary | getMachineSoRegOpValue(MI, TID, MO, OpIdx));
644    return;
645  }
646
647  if (MO.isReg()) {
648    // Encode register Rm.
649    emitWordLE(Binary | ARMRegisterInfo::getRegisterNumbering(MO.getReg()));
650    return;
651  }
652
653  // Encode so_imm.
654  // Set bit I(25) to identify this is the immediate form of <shifter_op>.
655  Binary |= 1 << ARMII::I_BitShift;
656  Binary |= getMachineSoImmOpValue(MO.getImm());
657
658  emitWordLE(Binary);
659}
660
661void ARMCodeEmitter::emitLoadStoreInstruction(const MachineInstr &MI,
662                                              unsigned ImplicitRd,
663                                              unsigned ImplicitRn) {
664  const TargetInstrDesc &TID = MI.getDesc();
665
666  // Part of binary is determined by TableGn.
667  unsigned Binary = getBinaryCodeForInstr(MI);
668
669  // Set the conditional execution predicate
670  Binary |= II->getPredicate(&MI) << ARMII::CondShift;
671
672  // Set first operand
673  unsigned OpIdx = 0;
674  if (ImplicitRd)
675    // Special handling for implicit use (e.g. PC).
676    Binary |= (ARMRegisterInfo::getRegisterNumbering(ImplicitRd)
677               << ARMII::RegRdShift);
678  else
679    Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRdShift;
680
681  // Set second operand
682  if (ImplicitRn)
683    // Special handling for implicit use (e.g. PC).
684    Binary |= (ARMRegisterInfo::getRegisterNumbering(ImplicitRn)
685               << ARMII::RegRnShift);
686  else
687    Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRnShift;
688
689  // If this is a two-address operand, skip it. e.g. LDR_PRE.
690  if (TID.getOperandConstraint(OpIdx, TOI::TIED_TO) != -1)
691    ++OpIdx;
692
693  const MachineOperand &MO2 = MI.getOperand(OpIdx);
694  unsigned AM2Opc = (ImplicitRn == ARM::PC)
695    ? 0 : MI.getOperand(OpIdx+1).getImm();
696
697  // Set bit U(23) according to sign of immed value (positive or negative).
698  Binary |= ((ARM_AM::getAM2Op(AM2Opc) == ARM_AM::add ? 1 : 0) <<
699             ARMII::U_BitShift);
700  if (!MO2.getReg()) { // is immediate
701    if (ARM_AM::getAM2Offset(AM2Opc))
702      // Set the value of offset_12 field
703      Binary |= ARM_AM::getAM2Offset(AM2Opc);
704    emitWordLE(Binary);
705    return;
706  }
707
708  // Set bit I(25), because this is not in immediate enconding.
709  Binary |= 1 << ARMII::I_BitShift;
710  assert(TargetRegisterInfo::isPhysicalRegister(MO2.getReg()));
711  // Set bit[3:0] to the corresponding Rm register
712  Binary |= ARMRegisterInfo::getRegisterNumbering(MO2.getReg());
713
714  // if this instr is in scaled register offset/index instruction, set
715  // shift_immed(bit[11:7]) and shift(bit[6:5]) fields.
716  if (unsigned ShImm = ARM_AM::getAM2Offset(AM2Opc)) {
717    Binary |= getShiftOp(AM2Opc) << 5;  // shift
718    Binary |= ShImm              << 7;  // shift_immed
719  }
720
721  emitWordLE(Binary);
722}
723
724void ARMCodeEmitter::emitMiscLoadStoreInstruction(const MachineInstr &MI,
725                                                  unsigned ImplicitRn) {
726  const TargetInstrDesc &TID = MI.getDesc();
727
728  // Part of binary is determined by TableGn.
729  unsigned Binary = getBinaryCodeForInstr(MI);
730
731  // Set the conditional execution predicate
732  Binary |= II->getPredicate(&MI) << ARMII::CondShift;
733
734  // Set first operand
735  Binary |= getMachineOpValue(MI, 0) << ARMII::RegRdShift;
736
737  // Set second operand
738  unsigned OpIdx = 1;
739  if (ImplicitRn)
740    // Special handling for implicit use (e.g. PC).
741    Binary |= (ARMRegisterInfo::getRegisterNumbering(ImplicitRn)
742               << ARMII::RegRnShift);
743  else
744    Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRnShift;
745
746  // If this is a two-address operand, skip it. e.g. LDRH_POST.
747  if (TID.getOperandConstraint(OpIdx, TOI::TIED_TO) != -1)
748    ++OpIdx;
749
750  const MachineOperand &MO2 = MI.getOperand(OpIdx);
751  unsigned AM3Opc = (ImplicitRn == ARM::PC)
752    ? 0 : MI.getOperand(OpIdx+1).getImm();
753
754  // Set bit U(23) according to sign of immed value (positive or negative)
755  Binary |= ((ARM_AM::getAM3Op(AM3Opc) == ARM_AM::add ? 1 : 0) <<
756             ARMII::U_BitShift);
757
758  // If this instr is in register offset/index encoding, set bit[3:0]
759  // to the corresponding Rm register.
760  if (MO2.getReg()) {
761    Binary |= ARMRegisterInfo::getRegisterNumbering(MO2.getReg());
762    emitWordLE(Binary);
763    return;
764  }
765
766  // This instr is in immediate offset/index encoding, set bit 22 to 1.
767  Binary |= 1 << ARMII::AM3_I_BitShift;
768  if (unsigned ImmOffs = ARM_AM::getAM3Offset(AM3Opc)) {
769    // Set operands
770    Binary |= (ImmOffs >> 4) << 8;  // immedH
771    Binary |= (ImmOffs & ~0xF);     // immedL
772  }
773
774  emitWordLE(Binary);
775}
776
777static unsigned getAddrModeUPBits(unsigned Mode) {
778  unsigned Binary = 0;
779
780  // Set addressing mode by modifying bits U(23) and P(24)
781  // IA - Increment after  - bit U = 1 and bit P = 0
782  // IB - Increment before - bit U = 1 and bit P = 1
783  // DA - Decrement after  - bit U = 0 and bit P = 0
784  // DB - Decrement before - bit U = 0 and bit P = 1
785  switch (Mode) {
786  default: assert(0 && "Unknown addressing sub-mode!");
787  case ARM_AM::da:                      break;
788  case ARM_AM::db: Binary |= 0x1 << ARMII::P_BitShift; break;
789  case ARM_AM::ia: Binary |= 0x1 << ARMII::U_BitShift; break;
790  case ARM_AM::ib: Binary |= 0x3 << ARMII::U_BitShift; break;
791  }
792
793  return Binary;
794}
795
796void ARMCodeEmitter::emitLoadStoreMultipleInstruction(const MachineInstr &MI) {
797  // Part of binary is determined by TableGn.
798  unsigned Binary = getBinaryCodeForInstr(MI);
799
800  // Set the conditional execution predicate
801  Binary |= II->getPredicate(&MI) << ARMII::CondShift;
802
803  // Set base address operand
804  Binary |= getMachineOpValue(MI, 0) << ARMII::RegRnShift;
805
806  // Set addressing mode by modifying bits U(23) and P(24)
807  const MachineOperand &MO = MI.getOperand(1);
808  Binary |= getAddrModeUPBits(ARM_AM::getAM4SubMode(MO.getImm()));
809
810  // Set bit W(21)
811  if (ARM_AM::getAM4WBFlag(MO.getImm()))
812    Binary |= 0x1 << ARMII::W_BitShift;
813
814  // Set registers
815  for (unsigned i = 4, e = MI.getNumOperands(); i != e; ++i) {
816    const MachineOperand &MO = MI.getOperand(i);
817    if (!MO.isReg() || MO.isImplicit())
818      break;
819    unsigned RegNum = ARMRegisterInfo::getRegisterNumbering(MO.getReg());
820    assert(TargetRegisterInfo::isPhysicalRegister(MO.getReg()) &&
821           RegNum < 16);
822    Binary |= 0x1 << RegNum;
823  }
824
825  emitWordLE(Binary);
826}
827
828void ARMCodeEmitter::emitMulFrmInstruction(const MachineInstr &MI) {
829  const TargetInstrDesc &TID = MI.getDesc();
830
831  // Part of binary is determined by TableGn.
832  unsigned Binary = getBinaryCodeForInstr(MI);
833
834  // Set the conditional execution predicate
835  Binary |= II->getPredicate(&MI) << ARMII::CondShift;
836
837  // Encode S bit if MI modifies CPSR.
838  Binary |= getAddrModeSBit(MI, TID);
839
840  // 32x32->64bit operations have two destination registers. The number
841  // of register definitions will tell us if that's what we're dealing with.
842  unsigned OpIdx = 0;
843  if (TID.getNumDefs() == 2)
844    Binary |= getMachineOpValue (MI, OpIdx++) << ARMII::RegRdLoShift;
845
846  // Encode Rd
847  Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRdHiShift;
848
849  // Encode Rm
850  Binary |= getMachineOpValue(MI, OpIdx++);
851
852  // Encode Rs
853  Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRsShift;
854
855  // Many multiple instructions (e.g. MLA) have three src operands. Encode
856  // it as Rn (for multiply, that's in the same offset as RdLo.
857  if (TID.getNumOperands() > OpIdx &&
858      !TID.OpInfo[OpIdx].isPredicate() &&
859      !TID.OpInfo[OpIdx].isOptionalDef())
860    Binary |= getMachineOpValue(MI, OpIdx) << ARMII::RegRdLoShift;
861
862  emitWordLE(Binary);
863}
864
865void ARMCodeEmitter::emitExtendInstruction(const MachineInstr &MI) {
866  const TargetInstrDesc &TID = MI.getDesc();
867
868  // Part of binary is determined by TableGn.
869  unsigned Binary = getBinaryCodeForInstr(MI);
870
871  // Set the conditional execution predicate
872  Binary |= II->getPredicate(&MI) << ARMII::CondShift;
873
874  unsigned OpIdx = 0;
875
876  // Encode Rd
877  Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRdShift;
878
879  const MachineOperand &MO1 = MI.getOperand(OpIdx++);
880  const MachineOperand &MO2 = MI.getOperand(OpIdx);
881  if (MO2.isReg()) {
882    // Two register operand form.
883    // Encode Rn.
884    Binary |= getMachineOpValue(MI, MO1) << ARMII::RegRnShift;
885
886    // Encode Rm.
887    Binary |= getMachineOpValue(MI, MO2);
888    ++OpIdx;
889  } else {
890    Binary |= getMachineOpValue(MI, MO1);
891  }
892
893  // Encode rot imm (0, 8, 16, or 24) if it has a rotate immediate operand.
894  if (MI.getOperand(OpIdx).isImm() &&
895      !TID.OpInfo[OpIdx].isPredicate() &&
896      !TID.OpInfo[OpIdx].isOptionalDef())
897    Binary |= (getMachineOpValue(MI, OpIdx) / 8) << ARMII::ExtRotImmShift;
898
899  emitWordLE(Binary);
900}
901
902void ARMCodeEmitter::emitMiscArithInstruction(const MachineInstr &MI) {
903  const TargetInstrDesc &TID = MI.getDesc();
904
905  // Part of binary is determined by TableGn.
906  unsigned Binary = getBinaryCodeForInstr(MI);
907
908  // Set the conditional execution predicate
909  Binary |= II->getPredicate(&MI) << ARMII::CondShift;
910
911  unsigned OpIdx = 0;
912
913  // Encode Rd
914  Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRdShift;
915
916  const MachineOperand &MO = MI.getOperand(OpIdx++);
917  if (OpIdx == TID.getNumOperands() ||
918      TID.OpInfo[OpIdx].isPredicate() ||
919      TID.OpInfo[OpIdx].isOptionalDef()) {
920    // Encode Rm and it's done.
921    Binary |= getMachineOpValue(MI, MO);
922    emitWordLE(Binary);
923    return;
924  }
925
926  // Encode Rn.
927  Binary |= getMachineOpValue(MI, MO) << ARMII::RegRnShift;
928
929  // Encode Rm.
930  Binary |= getMachineOpValue(MI, OpIdx++);
931
932  // Encode shift_imm.
933  unsigned ShiftAmt = MI.getOperand(OpIdx).getImm();
934  assert(ShiftAmt < 32 && "shift_imm range is 0 to 31!");
935  Binary |= ShiftAmt << ARMII::ShiftShift;
936
937  emitWordLE(Binary);
938}
939
940void ARMCodeEmitter::emitBranchInstruction(const MachineInstr &MI) {
941  const TargetInstrDesc &TID = MI.getDesc();
942
943  if (TID.Opcode == ARM::TPsoft)
944    abort(); // FIXME
945
946  // Part of binary is determined by TableGn.
947  unsigned Binary = getBinaryCodeForInstr(MI);
948
949  // Set the conditional execution predicate
950  Binary |= II->getPredicate(&MI) << ARMII::CondShift;
951
952  // Set signed_immed_24 field
953  Binary |= getMachineOpValue(MI, 0);
954
955  emitWordLE(Binary);
956}
957
958void ARMCodeEmitter::emitInlineJumpTable(unsigned JTIndex) {
959  // Remember the base address of the inline jump table.
960  intptr_t JTBase = MCE.getCurrentPCValue();
961  JTI->addJumpTableBaseAddr(JTIndex, JTBase);
962  DOUT << "  ** Jump Table #" << JTIndex << " @ " << (void*)JTBase << '\n';
963
964  // Now emit the jump table entries.
965  const std::vector<MachineBasicBlock*> &MBBs = (*MJTEs)[JTIndex].MBBs;
966  for (unsigned i = 0, e = MBBs.size(); i != e; ++i) {
967    if (IsPIC)
968      // DestBB address - JT base.
969      emitMachineBasicBlock(MBBs[i], ARM::reloc_arm_pic_jt, JTBase);
970    else
971      // Absolute DestBB address.
972      emitMachineBasicBlock(MBBs[i], ARM::reloc_arm_absolute);
973    emitWordLE(0);
974  }
975}
976
977void ARMCodeEmitter::emitMiscBranchInstruction(const MachineInstr &MI) {
978  const TargetInstrDesc &TID = MI.getDesc();
979
980  // Handle jump tables.
981  if (TID.Opcode == ARM::BR_JTr || TID.Opcode == ARM::BR_JTadd) {
982    // First emit a ldr pc, [] instruction.
983    emitDataProcessingInstruction(MI, ARM::PC);
984
985    // Then emit the inline jump table.
986    unsigned JTIndex = (TID.Opcode == ARM::BR_JTr)
987      ? MI.getOperand(1).getIndex() : MI.getOperand(2).getIndex();
988    emitInlineJumpTable(JTIndex);
989    return;
990  } else if (TID.Opcode == ARM::BR_JTm) {
991    // First emit a ldr pc, [] instruction.
992    emitLoadStoreInstruction(MI, ARM::PC);
993
994    // Then emit the inline jump table.
995    emitInlineJumpTable(MI.getOperand(3).getIndex());
996    return;
997  }
998
999  // Part of binary is determined by TableGn.
1000  unsigned Binary = getBinaryCodeForInstr(MI);
1001
1002  // Set the conditional execution predicate
1003  Binary |= II->getPredicate(&MI) << ARMII::CondShift;
1004
1005  if (TID.Opcode == ARM::BX_RET)
1006    // The return register is LR.
1007    Binary |= ARMRegisterInfo::getRegisterNumbering(ARM::LR);
1008  else
1009    // otherwise, set the return register
1010    Binary |= getMachineOpValue(MI, 0);
1011
1012  emitWordLE(Binary);
1013}
1014
1015void ARMCodeEmitter::emitVFPArithInstruction(const MachineInstr &MI) {
1016  const TargetInstrDesc &TID = MI.getDesc();
1017
1018  // Part of binary is determined by TableGn.
1019  unsigned Binary = getBinaryCodeForInstr(MI);
1020
1021  // Set the conditional execution predicate
1022  Binary |= II->getPredicate(&MI) << ARMII::CondShift;
1023
1024  unsigned OpIdx = 0;
1025  assert((Binary & ARMII::D_BitShift) == 0 &&
1026         (Binary & ARMII::N_BitShift) == 0 &&
1027         (Binary & ARMII::M_BitShift) == 0 && "VFP encoding bug!");
1028
1029  // Encode Dd / Sd.
1030  unsigned RegD = getMachineOpValue(MI, OpIdx++);
1031  Binary |= (RegD & 0x0f) << ARMII::RegRdShift;
1032  Binary |= (RegD & 0x10) << ARMII::D_BitShift;
1033
1034  // If this is a two-address operand, skip it, e.g. FMACD.
1035  if (TID.getOperandConstraint(OpIdx, TOI::TIED_TO) != -1)
1036    ++OpIdx;
1037
1038  // Encode Dn / Sn.
1039  if ((TID.TSFlags & ARMII::FormMask) == ARMII::VFPBinaryFrm) {
1040    unsigned RegN = getMachineOpValue(MI, OpIdx++);
1041    Binary |= (RegN & 0x0f) << ARMII::RegRnShift;
1042    Binary |= (RegN & 0x10) << ARMII::N_BitShift;
1043  }
1044
1045  // Encode Dm / Sm.
1046  unsigned RegM = getMachineOpValue(MI, OpIdx++);
1047  Binary |= (RegM & 0x0f);
1048  Binary |= (RegM & 0x10) << ARMII::M_BitShift;
1049
1050  emitWordLE(Binary);
1051}
1052
1053void ARMCodeEmitter::emitVFPConversionInstruction(const MachineInstr &MI) {
1054  const TargetInstrDesc &TID = MI.getDesc();
1055
1056  // Part of binary is determined by TableGn.
1057  unsigned Binary = getBinaryCodeForInstr(MI);
1058
1059  // Set the conditional execution predicate
1060  Binary |= II->getPredicate(&MI) << ARMII::CondShift;
1061
1062  unsigned OpIdx = 0;
1063
1064  // Encode Dd / Sd.
1065  unsigned RegD = getMachineOpValue(MI, OpIdx++);
1066  Binary |= (RegD & 0x0f) << ARMII::RegRdShift;
1067  Binary |= (RegD & 0x10) << ARMII::D_BitShift;
1068
1069  // Encode Dn / Sn.
1070  if ((TID.TSFlags & ARMII::FormMask) == ARMII::VFPConv1Frm) {
1071    unsigned RegN = getMachineOpValue(MI, OpIdx++);
1072    Binary |= (RegN & 0x0f) << ARMII::RegRnShift;
1073    Binary |= (RegN & 0x10) << ARMII::N_BitShift;
1074
1075    // FMRS / FMSR do not have Rm.
1076    if (!TID.OpInfo[2].isPredicate()) {
1077      unsigned RegM = getMachineOpValue(MI, OpIdx++);
1078      Binary |= (RegM & 0x0f);
1079      Binary |= (RegM & 0x10) << ARMII::M_BitShift;
1080    }
1081  } else {
1082    unsigned RegM = getMachineOpValue(MI, OpIdx++);
1083    Binary |= (RegM & 0x0f);
1084    Binary |= (RegM & 0x10) << ARMII::M_BitShift;
1085  }
1086
1087  emitWordLE(Binary);
1088}
1089
1090void ARMCodeEmitter::emitVFPLoadStoreInstruction(const MachineInstr &MI) {
1091  // Part of binary is determined by TableGn.
1092  unsigned Binary = getBinaryCodeForInstr(MI);
1093
1094  // Set the conditional execution predicate
1095  Binary |= II->getPredicate(&MI) << ARMII::CondShift;
1096
1097  unsigned OpIdx = 0;
1098
1099  // Encode Dd / Sd.
1100  unsigned RegD = getMachineOpValue(MI, OpIdx++);
1101  Binary |= (RegD & 0x0f) << ARMII::RegRdShift;
1102  Binary |= (RegD & 0x10) << ARMII::D_BitShift;
1103
1104  // Encode address base.
1105  const MachineOperand &Base = MI.getOperand(OpIdx++);
1106  Binary |= getMachineOpValue(MI, Base) << ARMII::RegRnShift;
1107
1108  // If there is a non-zero immediate offset, encode it.
1109  if (Base.isReg()) {
1110    const MachineOperand &Offset = MI.getOperand(OpIdx);
1111    if (unsigned ImmOffs = ARM_AM::getAM5Offset(Offset.getImm())) {
1112      if (ARM_AM::getAM5Op(Offset.getImm()) == ARM_AM::add)
1113        Binary |= 1 << ARMII::U_BitShift;
1114      // Immediate offset is multiplied by 4.
1115      Binary |= ImmOffs >> 2;
1116      emitWordLE(Binary);
1117      return;
1118    }
1119  }
1120
1121  // If immediate offset is omitted, default to +0.
1122  Binary |= 1 << ARMII::U_BitShift;
1123
1124  emitWordLE(Binary);
1125}
1126
1127void
1128ARMCodeEmitter::emitVFPLoadStoreMultipleInstruction(const MachineInstr &MI) {
1129  // Part of binary is determined by TableGn.
1130  unsigned Binary = getBinaryCodeForInstr(MI);
1131
1132  // Set the conditional execution predicate
1133  Binary |= II->getPredicate(&MI) << ARMII::CondShift;
1134
1135  // Set base address operand
1136  Binary |= getMachineOpValue(MI, 0) << ARMII::RegRnShift;
1137
1138  // Set addressing mode by modifying bits U(23) and P(24)
1139  const MachineOperand &MO = MI.getOperand(1);
1140  Binary |= getAddrModeUPBits(ARM_AM::getAM5SubMode(MO.getImm()));
1141
1142  // Set bit W(21)
1143  if (ARM_AM::getAM5WBFlag(MO.getImm()))
1144    Binary |= 0x1 << ARMII::W_BitShift;
1145
1146  // First register is encoded in Dd.
1147  unsigned FirstReg = MI.getOperand(4).getReg();
1148  Binary |= ARMRegisterInfo::getRegisterNumbering(FirstReg)<< ARMII::RegRdShift;
1149
1150  // Number of registers are encoded in offset field.
1151  unsigned NumRegs = 1;
1152  for (unsigned i = 5, e = MI.getNumOperands(); i != e; ++i) {
1153    const MachineOperand &MO = MI.getOperand(i);
1154    if (!MO.isReg() || MO.isImplicit())
1155      break;
1156    ++NumRegs;
1157  }
1158  Binary |= NumRegs * 2;
1159
1160  emitWordLE(Binary);
1161}
1162
1163void ARMCodeEmitter::emitMiscInstruction(const MachineInstr &MI) {
1164  // Part of binary is determined by TableGn.
1165  unsigned Binary = getBinaryCodeForInstr(MI);
1166
1167  // Set the conditional execution predicate
1168  Binary |= II->getPredicate(&MI) << ARMII::CondShift;
1169
1170  emitWordLE(Binary);
1171}
1172
1173#include "ARMGenCodeEmitter.inc"
1174