ARMCodeEmitter.cpp revision dc3c93266cd023dd0c8015626ef412b2d35d04bd 
1//===-- ARM/ARMCodeEmitter.cpp - Convert ARM code to machine code ---------===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file contains the pass that transforms the ARM machine instructions into
11// relocatable machine code.
12//
13//===----------------------------------------------------------------------===//
14
15#define DEBUG_TYPE "jit"
16#include "ARM.h"
17#include "ARMAddressingModes.h"
18#include "ARMConstantPoolValue.h"
19#include "ARMInstrInfo.h"
20#include "ARMRelocations.h"
21#include "ARMSubtarget.h"
22#include "ARMTargetMachine.h"
23#include "llvm/Constants.h"
24#include "llvm/DerivedTypes.h"
25#include "llvm/Function.h"
26#include "llvm/PassManager.h"
27#include "llvm/CodeGen/JITCodeEmitter.h"
28#include "llvm/CodeGen/MachineConstantPool.h"
29#include "llvm/CodeGen/MachineFunctionPass.h"
30#include "llvm/CodeGen/MachineInstr.h"
31#include "llvm/CodeGen/MachineJumpTableInfo.h"
32#include "llvm/CodeGen/MachineModuleInfo.h"
33#include "llvm/CodeGen/Passes.h"
34#include "llvm/ADT/Statistic.h"
35#include "llvm/Support/Debug.h"
36#include "llvm/Support/ErrorHandling.h"
37#include "llvm/Support/raw_ostream.h"
38#ifndef NDEBUG
39#include <iomanip>
40#endif
41using namespace llvm;
42
43STATISTIC(NumEmitted, "Number of machine instructions emitted");
44
45namespace {
46
47  class ARMCodeEmitter : public MachineFunctionPass {
48    ARMJITInfo                *JTI;
49    const ARMInstrInfo        *II;
50    const TargetData          *TD;
51    const ARMSubtarget        *Subtarget;
52    TargetMachine             &TM;
53    JITCodeEmitter            &MCE;
54    MachineModuleInfo *MMI;
55    const std::vector<MachineConstantPoolEntry> *MCPEs;
56    const std::vector<MachineJumpTableEntry> *MJTEs;
57    bool IsPIC;
58    bool IsThumb;
59
60    void getAnalysisUsage(AnalysisUsage &AU) const {
61      AU.addRequired<MachineModuleInfo>();
62      MachineFunctionPass::getAnalysisUsage(AU);
63    }
64
65    static char ID;
66  public:
67    ARMCodeEmitter(TargetMachine &tm, JITCodeEmitter &mce)
68      : MachineFunctionPass(ID), JTI(0),
69        II((const ARMInstrInfo *)tm.getInstrInfo()),
70        TD(tm.getTargetData()), TM(tm),
71        MCE(mce), MCPEs(0), MJTEs(0),
72        IsPIC(TM.getRelocationModel() == Reloc::PIC_), IsThumb(false) {}
73
74    /// getBinaryCodeForInstr - This function, generated by the
75    /// CodeEmitterGenerator using TableGen, produces the binary encoding for
76    /// machine instructions.
77    unsigned getBinaryCodeForInstr(const MachineInstr &MI);
78
79    bool runOnMachineFunction(MachineFunction &MF);
80
81    virtual const char *getPassName() const {
82      return "ARM Machine Code Emitter";
83    }
84
85    void emitInstruction(const MachineInstr &MI);
86
87  private:
88
89    void emitWordLE(unsigned Binary);
90    void emitDWordLE(uint64_t Binary);
91    void emitConstPoolInstruction(const MachineInstr &MI);
92    void emitMOVi32immInstruction(const MachineInstr &MI);
93    void emitMOVi2piecesInstruction(const MachineInstr &MI);
94    void emitLEApcrelJTInstruction(const MachineInstr &MI);
95    void emitPseudoMoveInstruction(const MachineInstr &MI);
96    void addPCLabel(unsigned LabelID);
97    void emitPseudoInstruction(const MachineInstr &MI);
98    unsigned getMachineSoRegOpValue(const MachineInstr &MI,
99                                    const TargetInstrDesc &TID,
100                                    const MachineOperand &MO,
101                                    unsigned OpIdx);
102
103    unsigned getMachineSoImmOpValue(unsigned SoImm);
104
105    unsigned getAddrModeSBit(const MachineInstr &MI,
106                             const TargetInstrDesc &TID) const;
107
108    void emitDataProcessingInstruction(const MachineInstr &MI,
109                                       unsigned ImplicitRd = 0,
110                                       unsigned ImplicitRn = 0);
111
112    void emitLoadStoreInstruction(const MachineInstr &MI,
113                                  unsigned ImplicitRd = 0,
114                                  unsigned ImplicitRn = 0);
115
116    void emitMiscLoadStoreInstruction(const MachineInstr &MI,
117                                      unsigned ImplicitRn = 0);
118
119    void emitLoadStoreMultipleInstruction(const MachineInstr &MI);
120
121    void emitMulFrmInstruction(const MachineInstr &MI);
122
123    void emitExtendInstruction(const MachineInstr &MI);
124
125    void emitMiscArithInstruction(const MachineInstr &MI);
126
127    void emitSaturateInstruction(const MachineInstr &MI);
128
129    void emitBranchInstruction(const MachineInstr &MI);
130
131    void emitInlineJumpTable(unsigned JTIndex);
132
133    void emitMiscBranchInstruction(const MachineInstr &MI);
134
135    void emitVFPArithInstruction(const MachineInstr &MI);
136
137    void emitVFPConversionInstruction(const MachineInstr &MI);
138
139    void emitVFPLoadStoreInstruction(const MachineInstr &MI);
140
141    void emitVFPLoadStoreMultipleInstruction(const MachineInstr &MI);
142
143    void emitMiscInstruction(const MachineInstr &MI);
144
145    void emitNEONLaneInstruction(const MachineInstr &MI);
146    void emitNEONDupInstruction(const MachineInstr &MI);
147    void emitNEON1RegModImmInstruction(const MachineInstr &MI);
148    void emitNEON2RegInstruction(const MachineInstr &MI);
149    void emitNEON3RegInstruction(const MachineInstr &MI);
150
151    /// getMachineOpValue - Return binary encoding of operand. If the machine
152    /// operand requires relocation, record the relocation and return zero.
153    unsigned getMachineOpValue(const MachineInstr &MI,const MachineOperand &MO);
154    unsigned getMachineOpValue(const MachineInstr &MI, unsigned OpIdx) {
155      return getMachineOpValue(MI, MI.getOperand(OpIdx));
156    }
157
158    /// getMovi32Value - Return binary encoding of operand for movw/movt. If the
159    /// machine operand requires relocation, record the relocation and return
160    /// zero.
161    unsigned getMovi32Value(const MachineInstr &MI,const MachineOperand &MO,
162                            unsigned Reloc);
163
164    /// getShiftOp - Return the shift opcode (bit[6:5]) of the immediate value.
165    ///
166    unsigned getShiftOp(unsigned Imm) const ;
167
168    /// Routines that handle operands which add machine relocations which are
169    /// fixed up by the relocation stage.
170    void emitGlobalAddress(const GlobalValue *GV, unsigned Reloc,
171                           bool MayNeedFarStub,  bool Indirect,
172                           intptr_t ACPV = 0);
173    void emitExternalSymbolAddress(const char *ES, unsigned Reloc);
174    void emitConstPoolAddress(unsigned CPI, unsigned Reloc);
175    void emitJumpTableAddress(unsigned JTIndex, unsigned Reloc);
176    void emitMachineBasicBlock(MachineBasicBlock *BB, unsigned Reloc,
177                               intptr_t JTBase = 0);
178  };
179}
180
181char ARMCodeEmitter::ID = 0;
182
183/// createARMJITCodeEmitterPass - Return a pass that emits the collected ARM
184/// code to the specified MCE object.
185FunctionPass *llvm::createARMJITCodeEmitterPass(ARMBaseTargetMachine &TM,
186                                                JITCodeEmitter &JCE) {
187  return new ARMCodeEmitter(TM, JCE);
188}
189
190bool ARMCodeEmitter::runOnMachineFunction(MachineFunction &MF) {
191  assert((MF.getTarget().getRelocationModel() != Reloc::Default ||
192          MF.getTarget().getRelocationModel() != Reloc::Static) &&
193         "JIT relocation model must be set to static or default!");
194  JTI = ((ARMTargetMachine &)MF.getTarget()).getJITInfo();
195  II = ((const ARMTargetMachine &)MF.getTarget()).getInstrInfo();
196  TD = ((const ARMTargetMachine &)MF.getTarget()).getTargetData();
197  Subtarget = &TM.getSubtarget<ARMSubtarget>();
198  MCPEs = &MF.getConstantPool()->getConstants();
199  MJTEs = 0;
200  if (MF.getJumpTableInfo()) MJTEs = &MF.getJumpTableInfo()->getJumpTables();
201  IsPIC = TM.getRelocationModel() == Reloc::PIC_;
202  IsThumb = MF.getInfo<ARMFunctionInfo>()->isThumbFunction();
203  JTI->Initialize(MF, IsPIC);
204  MMI = &getAnalysis<MachineModuleInfo>();
205  MCE.setModuleInfo(MMI);
206
207  do {
208    DEBUG(errs() << "JITTing function '"
209          << MF.getFunction()->getName() << "'\n");
210    MCE.startFunction(MF);
211    for (MachineFunction::iterator MBB = MF.begin(), E = MF.end();
212         MBB != E; ++MBB) {
213      MCE.StartMachineBasicBlock(MBB);
214      for (MachineBasicBlock::const_iterator I = MBB->begin(), E = MBB->end();
215           I != E; ++I)
216        emitInstruction(*I);
217    }
218  } while (MCE.finishFunction(MF));
219
220  return false;
221}
222
223/// getShiftOp - Return the shift opcode (bit[6:5]) of the immediate value.
224///
225unsigned ARMCodeEmitter::getShiftOp(unsigned Imm) const {
226  switch (ARM_AM::getAM2ShiftOpc(Imm)) {
227  default: llvm_unreachable("Unknown shift opc!");
228  case ARM_AM::asr: return 2;
229  case ARM_AM::lsl: return 0;
230  case ARM_AM::lsr: return 1;
231  case ARM_AM::ror:
232  case ARM_AM::rrx: return 3;
233  }
234  return 0;
235}
236
237/// getMovi32Value - Return binary encoding of operand for movw/movt. If the
238/// machine operand requires relocation, record the relocation and return zero.
239unsigned ARMCodeEmitter::getMovi32Value(const MachineInstr &MI,
240                                        const MachineOperand &MO,
241                                        unsigned Reloc) {
242  assert(((Reloc == ARM::reloc_arm_movt) || (Reloc == ARM::reloc_arm_movw))
243      && "Relocation to this function should be for movt or movw");
244
245  if (MO.isImm())
246    return static_cast<unsigned>(MO.getImm());
247  else if (MO.isGlobal())
248    emitGlobalAddress(MO.getGlobal(), Reloc, true, false);
249  else if (MO.isSymbol())
250    emitExternalSymbolAddress(MO.getSymbolName(), Reloc);
251  else if (MO.isMBB())
252    emitMachineBasicBlock(MO.getMBB(), Reloc);
253  else {
254#ifndef NDEBUG
255    errs() << MO;
256#endif
257    llvm_unreachable("Unsupported operand type for movw/movt");
258  }
259  return 0;
260}
261
262/// getMachineOpValue - Return binary encoding of operand. If the machine
263/// operand requires relocation, record the relocation and return zero.
264unsigned ARMCodeEmitter::getMachineOpValue(const MachineInstr &MI,
265                                           const MachineOperand &MO) {
266  if (MO.isReg())
267    return getARMRegisterNumbering(MO.getReg());
268  else if (MO.isImm())
269    return static_cast<unsigned>(MO.getImm());
270  else if (MO.isGlobal())
271    emitGlobalAddress(MO.getGlobal(), ARM::reloc_arm_branch, true, false);
272  else if (MO.isSymbol())
273    emitExternalSymbolAddress(MO.getSymbolName(), ARM::reloc_arm_branch);
274  else if (MO.isCPI()) {
275    const TargetInstrDesc &TID = MI.getDesc();
276    // For VFP load, the immediate offset is multiplied by 4.
277    unsigned Reloc =  ((TID.TSFlags & ARMII::FormMask) == ARMII::VFPLdStFrm)
278      ? ARM::reloc_arm_vfp_cp_entry : ARM::reloc_arm_cp_entry;
279    emitConstPoolAddress(MO.getIndex(), Reloc);
280  } else if (MO.isJTI())
281    emitJumpTableAddress(MO.getIndex(), ARM::reloc_arm_relative);
282  else if (MO.isMBB())
283    emitMachineBasicBlock(MO.getMBB(), ARM::reloc_arm_branch);
284  else {
285#ifndef NDEBUG
286    errs() << MO;
287#endif
288    llvm_unreachable(0);
289  }
290  return 0;
291}
292
293/// emitGlobalAddress - Emit the specified address to the code stream.
294///
295void ARMCodeEmitter::emitGlobalAddress(const GlobalValue *GV, unsigned Reloc,
296                                       bool MayNeedFarStub, bool Indirect,
297                                       intptr_t ACPV) {
298  MachineRelocation MR = Indirect
299    ? MachineRelocation::getIndirectSymbol(MCE.getCurrentPCOffset(), Reloc,
300                                           const_cast<GlobalValue *>(GV),
301                                           ACPV, MayNeedFarStub)
302    : MachineRelocation::getGV(MCE.getCurrentPCOffset(), Reloc,
303                               const_cast<GlobalValue *>(GV), ACPV,
304                               MayNeedFarStub);
305  MCE.addRelocation(MR);
306}
307
308/// emitExternalSymbolAddress - Arrange for the address of an external symbol to
309/// be emitted to the current location in the function, and allow it to be PC
310/// relative.
311void ARMCodeEmitter::emitExternalSymbolAddress(const char *ES, unsigned Reloc) {
312  MCE.addRelocation(MachineRelocation::getExtSym(MCE.getCurrentPCOffset(),
313                                                 Reloc, ES));
314}
315
316/// emitConstPoolAddress - Arrange for the address of an constant pool
317/// to be emitted to the current location in the function, and allow it to be PC
318/// relative.
319void ARMCodeEmitter::emitConstPoolAddress(unsigned CPI, unsigned Reloc) {
320  // Tell JIT emitter we'll resolve the address.
321  MCE.addRelocation(MachineRelocation::getConstPool(MCE.getCurrentPCOffset(),
322                                                    Reloc, CPI, 0, true));
323}
324
325/// emitJumpTableAddress - Arrange for the address of a jump table to
326/// be emitted to the current location in the function, and allow it to be PC
327/// relative.
328void ARMCodeEmitter::emitJumpTableAddress(unsigned JTIndex, unsigned Reloc) {
329  MCE.addRelocation(MachineRelocation::getJumpTable(MCE.getCurrentPCOffset(),
330                                                    Reloc, JTIndex, 0, true));
331}
332
333/// emitMachineBasicBlock - Emit the specified address basic block.
334void ARMCodeEmitter::emitMachineBasicBlock(MachineBasicBlock *BB,
335                                           unsigned Reloc, intptr_t JTBase) {
336  MCE.addRelocation(MachineRelocation::getBB(MCE.getCurrentPCOffset(),
337                                             Reloc, BB, JTBase));
338}
339
340void ARMCodeEmitter::emitWordLE(unsigned Binary) {
341  DEBUG(errs() << "  0x";
342        errs().write_hex(Binary) << "\n");
343  MCE.emitWordLE(Binary);
344}
345
346void ARMCodeEmitter::emitDWordLE(uint64_t Binary) {
347  DEBUG(errs() << "  0x";
348        errs().write_hex(Binary) << "\n");
349  MCE.emitDWordLE(Binary);
350}
351
352void ARMCodeEmitter::emitInstruction(const MachineInstr &MI) {
353  DEBUG(errs() << "JIT: " << (void*)MCE.getCurrentPCValue() << ":\t" << MI);
354
355  MCE.processDebugLoc(MI.getDebugLoc(), true);
356
357  ++NumEmitted;  // Keep track of the # of mi's emitted
358  switch (MI.getDesc().TSFlags & ARMII::FormMask) {
359  default: {
360    llvm_unreachable("Unhandled instruction encoding format!");
361    break;
362  }
363  case ARMII::Pseudo:
364    emitPseudoInstruction(MI);
365    break;
366  case ARMII::DPFrm:
367  case ARMII::DPSoRegFrm:
368    emitDataProcessingInstruction(MI);
369    break;
370  case ARMII::LdFrm:
371  case ARMII::StFrm:
372    emitLoadStoreInstruction(MI);
373    break;
374  case ARMII::LdMiscFrm:
375  case ARMII::StMiscFrm:
376    emitMiscLoadStoreInstruction(MI);
377    break;
378  case ARMII::LdStMulFrm:
379    emitLoadStoreMultipleInstruction(MI);
380    break;
381  case ARMII::MulFrm:
382    emitMulFrmInstruction(MI);
383    break;
384  case ARMII::ExtFrm:
385    emitExtendInstruction(MI);
386    break;
387  case ARMII::ArithMiscFrm:
388    emitMiscArithInstruction(MI);
389    break;
390  case ARMII::SatFrm:
391    emitSaturateInstruction(MI);
392    break;
393  case ARMII::BrFrm:
394    emitBranchInstruction(MI);
395    break;
396  case ARMII::BrMiscFrm:
397    emitMiscBranchInstruction(MI);
398    break;
399  // VFP instructions.
400  case ARMII::VFPUnaryFrm:
401  case ARMII::VFPBinaryFrm:
402    emitVFPArithInstruction(MI);
403    break;
404  case ARMII::VFPConv1Frm:
405  case ARMII::VFPConv2Frm:
406  case ARMII::VFPConv3Frm:
407  case ARMII::VFPConv4Frm:
408  case ARMII::VFPConv5Frm:
409    emitVFPConversionInstruction(MI);
410    break;
411  case ARMII::VFPLdStFrm:
412    emitVFPLoadStoreInstruction(MI);
413    break;
414  case ARMII::VFPLdStMulFrm:
415    emitVFPLoadStoreMultipleInstruction(MI);
416    break;
417  case ARMII::VFPMiscFrm:
418    emitMiscInstruction(MI);
419    break;
420  // NEON instructions.
421  case ARMII::NGetLnFrm:
422  case ARMII::NSetLnFrm:
423    emitNEONLaneInstruction(MI);
424    break;
425  case ARMII::NDupFrm:
426    emitNEONDupInstruction(MI);
427    break;
428  case ARMII::N1RegModImmFrm:
429    emitNEON1RegModImmInstruction(MI);
430    break;
431  case ARMII::N2RegFrm:
432    emitNEON2RegInstruction(MI);
433    break;
434  case ARMII::N3RegFrm:
435    emitNEON3RegInstruction(MI);
436    break;
437  }
438  MCE.processDebugLoc(MI.getDebugLoc(), false);
439}
440
441void ARMCodeEmitter::emitConstPoolInstruction(const MachineInstr &MI) {
442  unsigned CPI = MI.getOperand(0).getImm();       // CP instruction index.
443  unsigned CPIndex = MI.getOperand(1).getIndex(); // Actual cp entry index.
444  const MachineConstantPoolEntry &MCPE = (*MCPEs)[CPIndex];
445
446  // Remember the CONSTPOOL_ENTRY address for later relocation.
447  JTI->addConstantPoolEntryAddr(CPI, MCE.getCurrentPCValue());
448
449  // Emit constpool island entry. In most cases, the actual values will be
450  // resolved and relocated after code emission.
451  if (MCPE.isMachineConstantPoolEntry()) {
452    ARMConstantPoolValue *ACPV =
453      static_cast<ARMConstantPoolValue*>(MCPE.Val.MachineCPVal);
454
455    DEBUG(errs() << "  ** ARM constant pool #" << CPI << " @ "
456          << (void*)MCE.getCurrentPCValue() << " " << *ACPV << '\n');
457
458    assert(ACPV->isGlobalValue() && "unsupported constant pool value");
459    const GlobalValue *GV = ACPV->getGV();
460    if (GV) {
461      Reloc::Model RelocM = TM.getRelocationModel();
462      emitGlobalAddress(GV, ARM::reloc_arm_machine_cp_entry,
463                        isa<Function>(GV),
464                        Subtarget->GVIsIndirectSymbol(GV, RelocM),
465                        (intptr_t)ACPV);
466     } else  {
467      emitExternalSymbolAddress(ACPV->getSymbol(), ARM::reloc_arm_absolute);
468    }
469    emitWordLE(0);
470  } else {
471    const Constant *CV = MCPE.Val.ConstVal;
472
473    DEBUG({
474        errs() << "  ** Constant pool #" << CPI << " @ "
475               << (void*)MCE.getCurrentPCValue() << " ";
476        if (const Function *F = dyn_cast<Function>(CV))
477          errs() << F->getName();
478        else
479          errs() << *CV;
480        errs() << '\n';
481      });
482
483    if (const GlobalValue *GV = dyn_cast<GlobalValue>(CV)) {
484      emitGlobalAddress(GV, ARM::reloc_arm_absolute, isa<Function>(GV), false);
485      emitWordLE(0);
486    } else if (const ConstantInt *CI = dyn_cast<ConstantInt>(CV)) {
487      uint32_t Val = *(uint32_t*)CI->getValue().getRawData();
488      emitWordLE(Val);
489    } else if (const ConstantFP *CFP = dyn_cast<ConstantFP>(CV)) {
490      if (CFP->getType()->isFloatTy())
491        emitWordLE(CFP->getValueAPF().bitcastToAPInt().getZExtValue());
492      else if (CFP->getType()->isDoubleTy())
493        emitDWordLE(CFP->getValueAPF().bitcastToAPInt().getZExtValue());
494      else {
495        llvm_unreachable("Unable to handle this constantpool entry!");
496      }
497    } else {
498      llvm_unreachable("Unable to handle this constantpool entry!");
499    }
500  }
501}
502
503void ARMCodeEmitter::emitMOVi32immInstruction(const MachineInstr &MI) {
504  const MachineOperand &MO0 = MI.getOperand(0);
505  const MachineOperand &MO1 = MI.getOperand(1);
506
507  // Emit the 'movw' instruction.
508  unsigned Binary = 0x30 << 20;  // mov: Insts{27-20} = 0b00110000
509
510  unsigned Lo16 = getMovi32Value(MI, MO1, ARM::reloc_arm_movw) & 0xFFFF;
511
512  // Set the conditional execution predicate.
513  Binary |= II->getPredicate(&MI) << ARMII::CondShift;
514
515  // Encode Rd.
516  Binary |= getMachineOpValue(MI, MO0) << ARMII::RegRdShift;
517
518  // Encode imm16 as imm4:imm12
519  Binary |= Lo16 & 0xFFF; // Insts{11-0} = imm12
520  Binary |= ((Lo16 >> 12) & 0xF) << 16; // Insts{19-16} = imm4
521  emitWordLE(Binary);
522
523  unsigned Hi16 = getMovi32Value(MI, MO1, ARM::reloc_arm_movt) >> 16;
524  // Emit the 'movt' instruction.
525  Binary = 0x34 << 20; // movt: Insts{27-20} = 0b00110100
526
527  // Set the conditional execution predicate.
528  Binary |= II->getPredicate(&MI) << ARMII::CondShift;
529
530  // Encode Rd.
531  Binary |= getMachineOpValue(MI, MO0) << ARMII::RegRdShift;
532
533  // Encode imm16 as imm4:imm1, same as movw above.
534  Binary |= Hi16 & 0xFFF;
535  Binary |= ((Hi16 >> 12) & 0xF) << 16;
536  emitWordLE(Binary);
537}
538
539void ARMCodeEmitter::emitMOVi2piecesInstruction(const MachineInstr &MI) {
540  const MachineOperand &MO0 = MI.getOperand(0);
541  const MachineOperand &MO1 = MI.getOperand(1);
542  assert(MO1.isImm() && ARM_AM::isSOImmTwoPartVal(MO1.getImm()) &&
543                                                  "Not a valid so_imm value!");
544  unsigned V1 = ARM_AM::getSOImmTwoPartFirst(MO1.getImm());
545  unsigned V2 = ARM_AM::getSOImmTwoPartSecond(MO1.getImm());
546
547  // Emit the 'mov' instruction.
548  unsigned Binary = 0xd << 21;  // mov: Insts{24-21} = 0b1101
549
550  // Set the conditional execution predicate.
551  Binary |= II->getPredicate(&MI) << ARMII::CondShift;
552
553  // Encode Rd.
554  Binary |= getMachineOpValue(MI, MO0) << ARMII::RegRdShift;
555
556  // Encode so_imm.
557  // Set bit I(25) to identify this is the immediate form of <shifter_op>
558  Binary |= 1 << ARMII::I_BitShift;
559  Binary |= getMachineSoImmOpValue(V1);
560  emitWordLE(Binary);
561
562  // Now the 'orr' instruction.
563  Binary = 0xc << 21;  // orr: Insts{24-21} = 0b1100
564
565  // Set the conditional execution predicate.
566  Binary |= II->getPredicate(&MI) << ARMII::CondShift;
567
568  // Encode Rd.
569  Binary |= getMachineOpValue(MI, MO0) << ARMII::RegRdShift;
570
571  // Encode Rn.
572  Binary |= getMachineOpValue(MI, MO0) << ARMII::RegRnShift;
573
574  // Encode so_imm.
575  // Set bit I(25) to identify this is the immediate form of <shifter_op>
576  Binary |= 1 << ARMII::I_BitShift;
577  Binary |= getMachineSoImmOpValue(V2);
578  emitWordLE(Binary);
579}
580
581void ARMCodeEmitter::emitLEApcrelJTInstruction(const MachineInstr &MI) {
582  // It's basically add r, pc, (LJTI - $+8)
583
584  const TargetInstrDesc &TID = MI.getDesc();
585
586  // Emit the 'add' instruction.
587  unsigned Binary = 0x4 << 21;  // add: Insts{24-31} = 0b0100
588
589  // Set the conditional execution predicate
590  Binary |= II->getPredicate(&MI) << ARMII::CondShift;
591
592  // Encode S bit if MI modifies CPSR.
593  Binary |= getAddrModeSBit(MI, TID);
594
595  // Encode Rd.
596  Binary |= getMachineOpValue(MI, 0) << ARMII::RegRdShift;
597
598  // Encode Rn which is PC.
599  Binary |= getARMRegisterNumbering(ARM::PC) << ARMII::RegRnShift;
600
601  // Encode the displacement.
602  Binary |= 1 << ARMII::I_BitShift;
603  emitJumpTableAddress(MI.getOperand(1).getIndex(), ARM::reloc_arm_jt_base);
604
605  emitWordLE(Binary);
606}
607
608void ARMCodeEmitter::emitPseudoMoveInstruction(const MachineInstr &MI) {
609  unsigned Opcode = MI.getDesc().Opcode;
610
611  // Part of binary is determined by TableGn.
612  unsigned Binary = getBinaryCodeForInstr(MI);
613
614  // Set the conditional execution predicate
615  Binary |= II->getPredicate(&MI) << ARMII::CondShift;
616
617  // Encode S bit if MI modifies CPSR.
618  if (Opcode == ARM::MOVsrl_flag || Opcode == ARM::MOVsra_flag)
619    Binary |= 1 << ARMII::S_BitShift;
620
621  // Encode register def if there is one.
622  Binary |= getMachineOpValue(MI, 0) << ARMII::RegRdShift;
623
624  // Encode the shift operation.
625  switch (Opcode) {
626  default: break;
627  case ARM::MOVrx:
628    // rrx
629    Binary |= 0x6 << 4;
630    break;
631  case ARM::MOVsrl_flag:
632    // lsr #1
633    Binary |= (0x2 << 4) | (1 << 7);
634    break;
635  case ARM::MOVsra_flag:
636    // asr #1
637    Binary |= (0x4 << 4) | (1 << 7);
638    break;
639  }
640
641  // Encode register Rm.
642  Binary |= getMachineOpValue(MI, 1);
643
644  emitWordLE(Binary);
645}
646
647void ARMCodeEmitter::addPCLabel(unsigned LabelID) {
648  DEBUG(errs() << "  ** LPC" << LabelID << " @ "
649        << (void*)MCE.getCurrentPCValue() << '\n');
650  JTI->addPCLabelAddr(LabelID, MCE.getCurrentPCValue());
651}
652
653void ARMCodeEmitter::emitPseudoInstruction(const MachineInstr &MI) {
654  unsigned Opcode = MI.getDesc().Opcode;
655  switch (Opcode) {
656  default:
657    llvm_unreachable("ARMCodeEmitter::emitPseudoInstruction");
658  case ARM::BX:
659  case ARM::BMOVPCRX:
660  case ARM::BXr9:
661  case ARM::BMOVPCRXr9: {
662    // First emit mov lr, pc
663    unsigned Binary = 0x01a0e00f;
664    Binary |= II->getPredicate(&MI) << ARMII::CondShift;
665    emitWordLE(Binary);
666
667    // and then emit the branch.
668    emitMiscBranchInstruction(MI);
669    break;
670  }
671  case TargetOpcode::INLINEASM: {
672    // We allow inline assembler nodes with empty bodies - they can
673    // implicitly define registers, which is ok for JIT.
674    if (MI.getOperand(0).getSymbolName()[0]) {
675      report_fatal_error("JIT does not support inline asm!");
676    }
677    break;
678  }
679  case TargetOpcode::PROLOG_LABEL:
680  case TargetOpcode::EH_LABEL:
681    MCE.emitLabel(MI.getOperand(0).getMCSymbol());
682    break;
683  case TargetOpcode::IMPLICIT_DEF:
684  case TargetOpcode::KILL:
685    // Do nothing.
686    break;
687  case ARM::CONSTPOOL_ENTRY:
688    emitConstPoolInstruction(MI);
689    break;
690  case ARM::PICADD: {
691    // Remember of the address of the PC label for relocation later.
692    addPCLabel(MI.getOperand(2).getImm());
693    // PICADD is just an add instruction that implicitly read pc.
694    emitDataProcessingInstruction(MI, 0, ARM::PC);
695    break;
696  }
697  case ARM::PICLDR:
698  case ARM::PICLDRB:
699  case ARM::PICSTR:
700  case ARM::PICSTRB: {
701    // Remember of the address of the PC label for relocation later.
702    addPCLabel(MI.getOperand(2).getImm());
703    // These are just load / store instructions that implicitly read pc.
704    emitLoadStoreInstruction(MI, 0, ARM::PC);
705    break;
706  }
707  case ARM::PICLDRH:
708  case ARM::PICLDRSH:
709  case ARM::PICLDRSB:
710  case ARM::PICSTRH: {
711    // Remember of the address of the PC label for relocation later.
712    addPCLabel(MI.getOperand(2).getImm());
713    // These are just load / store instructions that implicitly read pc.
714    emitMiscLoadStoreInstruction(MI, ARM::PC);
715    break;
716  }
717
718  case ARM::MOVi32imm:
719    emitMOVi32immInstruction(MI);
720    break;
721
722  case ARM::MOVi2pieces:
723    // Two instructions to materialize a constant.
724    emitMOVi2piecesInstruction(MI);
725    break;
726  case ARM::LEApcrelJT:
727    // Materialize jumptable address.
728    emitLEApcrelJTInstruction(MI);
729    break;
730  case ARM::MOVrx:
731  case ARM::MOVsrl_flag:
732  case ARM::MOVsra_flag:
733    emitPseudoMoveInstruction(MI);
734    break;
735  }
736}
737
738unsigned ARMCodeEmitter::getMachineSoRegOpValue(const MachineInstr &MI,
739                                                const TargetInstrDesc &TID,
740                                                const MachineOperand &MO,
741                                                unsigned OpIdx) {
742  unsigned Binary = getMachineOpValue(MI, MO);
743
744  const MachineOperand &MO1 = MI.getOperand(OpIdx + 1);
745  const MachineOperand &MO2 = MI.getOperand(OpIdx + 2);
746  ARM_AM::ShiftOpc SOpc = ARM_AM::getSORegShOp(MO2.getImm());
747
748  // Encode the shift opcode.
749  unsigned SBits = 0;
750  unsigned Rs = MO1.getReg();
751  if (Rs) {
752    // Set shift operand (bit[7:4]).
753    // LSL - 0001
754    // LSR - 0011
755    // ASR - 0101
756    // ROR - 0111
757    // RRX - 0110 and bit[11:8] clear.
758    switch (SOpc) {
759    default: llvm_unreachable("Unknown shift opc!");
760    case ARM_AM::lsl: SBits = 0x1; break;
761    case ARM_AM::lsr: SBits = 0x3; break;
762    case ARM_AM::asr: SBits = 0x5; break;
763    case ARM_AM::ror: SBits = 0x7; break;
764    case ARM_AM::rrx: SBits = 0x6; break;
765    }
766  } else {
767    // Set shift operand (bit[6:4]).
768    // LSL - 000
769    // LSR - 010
770    // ASR - 100
771    // ROR - 110
772    switch (SOpc) {
773    default: llvm_unreachable("Unknown shift opc!");
774    case ARM_AM::lsl: SBits = 0x0; break;
775    case ARM_AM::lsr: SBits = 0x2; break;
776    case ARM_AM::asr: SBits = 0x4; break;
777    case ARM_AM::ror: SBits = 0x6; break;
778    }
779  }
780  Binary |= SBits << 4;
781  if (SOpc == ARM_AM::rrx)
782    return Binary;
783
784  // Encode the shift operation Rs or shift_imm (except rrx).
785  if (Rs) {
786    // Encode Rs bit[11:8].
787    assert(ARM_AM::getSORegOffset(MO2.getImm()) == 0);
788    return Binary | (getARMRegisterNumbering(Rs) << ARMII::RegRsShift);
789  }
790
791  // Encode shift_imm bit[11:7].
792  return Binary | ARM_AM::getSORegOffset(MO2.getImm()) << 7;
793}
794
795unsigned ARMCodeEmitter::getMachineSoImmOpValue(unsigned SoImm) {
796  int SoImmVal = ARM_AM::getSOImmVal(SoImm);
797  assert(SoImmVal != -1 && "Not a valid so_imm value!");
798
799  // Encode rotate_imm.
800  unsigned Binary = (ARM_AM::getSOImmValRot((unsigned)SoImmVal) >> 1)
801    << ARMII::SoRotImmShift;
802
803  // Encode immed_8.
804  Binary |= ARM_AM::getSOImmValImm((unsigned)SoImmVal);
805  return Binary;
806}
807
808unsigned ARMCodeEmitter::getAddrModeSBit(const MachineInstr &MI,
809                                         const TargetInstrDesc &TID) const {
810  for (unsigned i = MI.getNumOperands(), e = TID.getNumOperands(); i != e; --i){
811    const MachineOperand &MO = MI.getOperand(i-1);
812    if (MO.isReg() && MO.isDef() && MO.getReg() == ARM::CPSR)
813      return 1 << ARMII::S_BitShift;
814  }
815  return 0;
816}
817
818void ARMCodeEmitter::emitDataProcessingInstruction(const MachineInstr &MI,
819                                                   unsigned ImplicitRd,
820                                                   unsigned ImplicitRn) {
821  const TargetInstrDesc &TID = MI.getDesc();
822
823  // Part of binary is determined by TableGn.
824  unsigned Binary = getBinaryCodeForInstr(MI);
825
826  // Set the conditional execution predicate
827  Binary |= II->getPredicate(&MI) << ARMII::CondShift;
828
829  // Encode S bit if MI modifies CPSR.
830  Binary |= getAddrModeSBit(MI, TID);
831
832  // Encode register def if there is one.
833  unsigned NumDefs = TID.getNumDefs();
834  unsigned OpIdx = 0;
835  if (NumDefs)
836    Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRdShift;
837  else if (ImplicitRd)
838    // Special handling for implicit use (e.g. PC).
839    Binary |= (getARMRegisterNumbering(ImplicitRd) << ARMII::RegRdShift);
840
841  if (TID.Opcode == ARM::MOVi16) {
842      // Get immediate from MI.
843      unsigned Lo16 = getMovi32Value(MI, MI.getOperand(OpIdx),
844                      ARM::reloc_arm_movw);
845      // Encode imm which is the same as in emitMOVi32immInstruction().
846      Binary |= Lo16 & 0xFFF;
847      Binary |= ((Lo16 >> 12) & 0xF) << 16;
848      emitWordLE(Binary);
849      return;
850  } else if(TID.Opcode == ARM::MOVTi16) {
851      unsigned Hi16 = (getMovi32Value(MI, MI.getOperand(OpIdx),
852                       ARM::reloc_arm_movt) >> 16);
853      Binary |= Hi16 & 0xFFF;
854      Binary |= ((Hi16 >> 12) & 0xF) << 16;
855      emitWordLE(Binary);
856      return;
857  } else if ((TID.Opcode == ARM::BFC) || (TID.Opcode == ARM::BFI)) {
858      uint32_t v = ~MI.getOperand(2).getImm();
859      int32_t lsb = CountTrailingZeros_32(v);
860      int32_t msb = (32 - CountLeadingZeros_32(v)) - 1;
861      // Instr{20-16} = msb, Instr{11-7} = lsb
862      Binary |= (msb & 0x1F) << 16;
863      Binary |= (lsb & 0x1F) << 7;
864      emitWordLE(Binary);
865      return;
866  } else if ((TID.Opcode == ARM::UBFX) || (TID.Opcode == ARM::SBFX)) {
867      // Encode Rn in Instr{0-3}
868      Binary |= getMachineOpValue(MI, OpIdx++);
869
870      uint32_t lsb = MI.getOperand(OpIdx++).getImm();
871      uint32_t widthm1 = MI.getOperand(OpIdx++).getImm() - 1;
872
873      // Instr{20-16} = widthm1, Instr{11-7} = lsb
874      Binary |= (widthm1 & 0x1F) << 16;
875      Binary |= (lsb & 0x1F) << 7;
876      emitWordLE(Binary);
877      return;
878  }
879
880  // If this is a two-address operand, skip it. e.g. MOVCCr operand 1.
881  if (TID.getOperandConstraint(OpIdx, TOI::TIED_TO) != -1)
882    ++OpIdx;
883
884  // Encode first non-shifter register operand if there is one.
885  bool isUnary = TID.TSFlags & ARMII::UnaryDP;
886  if (!isUnary) {
887    if (ImplicitRn)
888      // Special handling for implicit use (e.g. PC).
889      Binary |= (getARMRegisterNumbering(ImplicitRn) << ARMII::RegRnShift);
890    else {
891      Binary |= getMachineOpValue(MI, OpIdx) << ARMII::RegRnShift;
892      ++OpIdx;
893    }
894  }
895
896  // Encode shifter operand.
897  const MachineOperand &MO = MI.getOperand(OpIdx);
898  if ((TID.TSFlags & ARMII::FormMask) == ARMII::DPSoRegFrm) {
899    // Encode SoReg.
900    emitWordLE(Binary | getMachineSoRegOpValue(MI, TID, MO, OpIdx));
901    return;
902  }
903
904  if (MO.isReg()) {
905    // Encode register Rm.
906    emitWordLE(Binary | getARMRegisterNumbering(MO.getReg()));
907    return;
908  }
909
910  // Encode so_imm.
911  Binary |= getMachineSoImmOpValue((unsigned)MO.getImm());
912
913  emitWordLE(Binary);
914}
915
916void ARMCodeEmitter::emitLoadStoreInstruction(const MachineInstr &MI,
917                                              unsigned ImplicitRd,
918                                              unsigned ImplicitRn) {
919  const TargetInstrDesc &TID = MI.getDesc();
920  unsigned Form = TID.TSFlags & ARMII::FormMask;
921  bool IsPrePost = (TID.TSFlags & ARMII::IndexModeMask) != 0;
922
923  // Part of binary is determined by TableGn.
924  unsigned Binary = getBinaryCodeForInstr(MI);
925
926  // Set the conditional execution predicate
927  Binary |= II->getPredicate(&MI) << ARMII::CondShift;
928
929  unsigned OpIdx = 0;
930
931  // Operand 0 of a pre- and post-indexed store is the address base
932  // writeback. Skip it.
933  bool Skipped = false;
934  if (IsPrePost && Form == ARMII::StFrm) {
935    ++OpIdx;
936    Skipped = true;
937  }
938
939  // Set first operand
940  if (ImplicitRd)
941    // Special handling for implicit use (e.g. PC).
942    Binary |= (getARMRegisterNumbering(ImplicitRd) << ARMII::RegRdShift);
943  else
944    Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRdShift;
945
946  // Set second operand
947  if (ImplicitRn)
948    // Special handling for implicit use (e.g. PC).
949    Binary |= (getARMRegisterNumbering(ImplicitRn) << ARMII::RegRnShift);
950  else
951    Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRnShift;
952
953  // If this is a two-address operand, skip it. e.g. LDR_PRE.
954  if (!Skipped && TID.getOperandConstraint(OpIdx, TOI::TIED_TO) != -1)
955    ++OpIdx;
956
957  const MachineOperand &MO2 = MI.getOperand(OpIdx);
958  unsigned AM2Opc = (ImplicitRn == ARM::PC)
959    ? 0 : MI.getOperand(OpIdx+1).getImm();
960
961  // Set bit U(23) according to sign of immed value (positive or negative).
962  Binary |= ((ARM_AM::getAM2Op(AM2Opc) == ARM_AM::add ? 1 : 0) <<
963             ARMII::U_BitShift);
964  if (!MO2.getReg()) { // is immediate
965    if (ARM_AM::getAM2Offset(AM2Opc))
966      // Set the value of offset_12 field
967      Binary |= ARM_AM::getAM2Offset(AM2Opc);
968    emitWordLE(Binary);
969    return;
970  }
971
972  // Set bit I(25), because this is not in immediate enconding.
973  Binary |= 1 << ARMII::I_BitShift;
974  assert(TargetRegisterInfo::isPhysicalRegister(MO2.getReg()));
975  // Set bit[3:0] to the corresponding Rm register
976  Binary |= getARMRegisterNumbering(MO2.getReg());
977
978  // If this instr is in scaled register offset/index instruction, set
979  // shift_immed(bit[11:7]) and shift(bit[6:5]) fields.
980  if (unsigned ShImm = ARM_AM::getAM2Offset(AM2Opc)) {
981    Binary |= getShiftOp(AM2Opc) << ARMII::ShiftImmShift;  // shift
982    Binary |= ShImm              << ARMII::ShiftShift;     // shift_immed
983  }
984
985  emitWordLE(Binary);
986}
987
988void ARMCodeEmitter::emitMiscLoadStoreInstruction(const MachineInstr &MI,
989                                                  unsigned ImplicitRn) {
990  const TargetInstrDesc &TID = MI.getDesc();
991  unsigned Form = TID.TSFlags & ARMII::FormMask;
992  bool IsPrePost = (TID.TSFlags & ARMII::IndexModeMask) != 0;
993
994  // Part of binary is determined by TableGn.
995  unsigned Binary = getBinaryCodeForInstr(MI);
996
997  // Set the conditional execution predicate
998  Binary |= II->getPredicate(&MI) << ARMII::CondShift;
999
1000  unsigned OpIdx = 0;
1001
1002  // Operand 0 of a pre- and post-indexed store is the address base
1003  // writeback. Skip it.
1004  bool Skipped = false;
1005  if (IsPrePost && Form == ARMII::StMiscFrm) {
1006    ++OpIdx;
1007    Skipped = true;
1008  }
1009
1010  // Set first operand
1011  Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRdShift;
1012
1013  // Skip LDRD and STRD's second operand.
1014  if (TID.Opcode == ARM::LDRD || TID.Opcode == ARM::STRD)
1015    ++OpIdx;
1016
1017  // Set second operand
1018  if (ImplicitRn)
1019    // Special handling for implicit use (e.g. PC).
1020    Binary |= (getARMRegisterNumbering(ImplicitRn) << ARMII::RegRnShift);
1021  else
1022    Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRnShift;
1023
1024  // If this is a two-address operand, skip it. e.g. LDRH_POST.
1025  if (!Skipped && TID.getOperandConstraint(OpIdx, TOI::TIED_TO) != -1)
1026    ++OpIdx;
1027
1028  const MachineOperand &MO2 = MI.getOperand(OpIdx);
1029  unsigned AM3Opc = (ImplicitRn == ARM::PC)
1030    ? 0 : MI.getOperand(OpIdx+1).getImm();
1031
1032  // Set bit U(23) according to sign of immed value (positive or negative)
1033  Binary |= ((ARM_AM::getAM3Op(AM3Opc) == ARM_AM::add ? 1 : 0) <<
1034             ARMII::U_BitShift);
1035
1036  // If this instr is in register offset/index encoding, set bit[3:0]
1037  // to the corresponding Rm register.
1038  if (MO2.getReg()) {
1039    Binary |= getARMRegisterNumbering(MO2.getReg());
1040    emitWordLE(Binary);
1041    return;
1042  }
1043
1044  // This instr is in immediate offset/index encoding, set bit 22 to 1.
1045  Binary |= 1 << ARMII::AM3_I_BitShift;
1046  if (unsigned ImmOffs = ARM_AM::getAM3Offset(AM3Opc)) {
1047    // Set operands
1048    Binary |= (ImmOffs >> 4) << ARMII::ImmHiShift;  // immedH
1049    Binary |= (ImmOffs & 0xF);                      // immedL
1050  }
1051
1052  emitWordLE(Binary);
1053}
1054
1055static unsigned getAddrModeUPBits(unsigned Mode) {
1056  unsigned Binary = 0;
1057
1058  // Set addressing mode by modifying bits U(23) and P(24)
1059  // IA - Increment after  - bit U = 1 and bit P = 0
1060  // IB - Increment before - bit U = 1 and bit P = 1
1061  // DA - Decrement after  - bit U = 0 and bit P = 0
1062  // DB - Decrement before - bit U = 0 and bit P = 1
1063  switch (Mode) {
1064  default: llvm_unreachable("Unknown addressing sub-mode!");
1065  case ARM_AM::da:                                     break;
1066  case ARM_AM::db: Binary |= 0x1 << ARMII::P_BitShift; break;
1067  case ARM_AM::ia: Binary |= 0x1 << ARMII::U_BitShift; break;
1068  case ARM_AM::ib: Binary |= 0x3 << ARMII::U_BitShift; break;
1069  }
1070
1071  return Binary;
1072}
1073
1074void ARMCodeEmitter::emitLoadStoreMultipleInstruction(const MachineInstr &MI) {
1075  const TargetInstrDesc &TID = MI.getDesc();
1076  bool IsUpdating = (TID.TSFlags & ARMII::IndexModeMask) != 0;
1077
1078  // Part of binary is determined by TableGn.
1079  unsigned Binary = getBinaryCodeForInstr(MI);
1080
1081  // Set the conditional execution predicate
1082  Binary |= II->getPredicate(&MI) << ARMII::CondShift;
1083
1084  // Skip operand 0 of an instruction with base register update.
1085  unsigned OpIdx = 0;
1086  if (IsUpdating)
1087    ++OpIdx;
1088
1089  // Set base address operand
1090  Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRnShift;
1091
1092  // Set addressing mode by modifying bits U(23) and P(24)
1093  const MachineOperand &MO = MI.getOperand(OpIdx++);
1094  Binary |= getAddrModeUPBits(ARM_AM::getAM4SubMode(MO.getImm()));
1095
1096  // Set bit W(21)
1097  if (IsUpdating)
1098    Binary |= 0x1 << ARMII::W_BitShift;
1099
1100  // Set registers
1101  for (unsigned i = OpIdx+2, e = MI.getNumOperands(); i != e; ++i) {
1102    const MachineOperand &MO = MI.getOperand(i);
1103    if (!MO.isReg() || MO.isImplicit())
1104      break;
1105    unsigned RegNum = getARMRegisterNumbering(MO.getReg());
1106    assert(TargetRegisterInfo::isPhysicalRegister(MO.getReg()) &&
1107           RegNum < 16);
1108    Binary |= 0x1 << RegNum;
1109  }
1110
1111  emitWordLE(Binary);
1112}
1113
1114void ARMCodeEmitter::emitMulFrmInstruction(const MachineInstr &MI) {
1115  const TargetInstrDesc &TID = MI.getDesc();
1116
1117  // Part of binary is determined by TableGn.
1118  unsigned Binary = getBinaryCodeForInstr(MI);
1119
1120  // Set the conditional execution predicate
1121  Binary |= II->getPredicate(&MI) << ARMII::CondShift;
1122
1123  // Encode S bit if MI modifies CPSR.
1124  Binary |= getAddrModeSBit(MI, TID);
1125
1126  // 32x32->64bit operations have two destination registers. The number
1127  // of register definitions will tell us if that's what we're dealing with.
1128  unsigned OpIdx = 0;
1129  if (TID.getNumDefs() == 2)
1130    Binary |= getMachineOpValue (MI, OpIdx++) << ARMII::RegRdLoShift;
1131
1132  // Encode Rd
1133  Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRdHiShift;
1134
1135  // Encode Rm
1136  Binary |= getMachineOpValue(MI, OpIdx++);
1137
1138  // Encode Rs
1139  Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRsShift;
1140
1141  // Many multiple instructions (e.g. MLA) have three src operands. Encode
1142  // it as Rn (for multiply, that's in the same offset as RdLo.
1143  if (TID.getNumOperands() > OpIdx &&
1144      !TID.OpInfo[OpIdx].isPredicate() &&
1145      !TID.OpInfo[OpIdx].isOptionalDef())
1146    Binary |= getMachineOpValue(MI, OpIdx) << ARMII::RegRdLoShift;
1147
1148  emitWordLE(Binary);
1149}
1150
1151void ARMCodeEmitter::emitExtendInstruction(const MachineInstr &MI) {
1152  const TargetInstrDesc &TID = MI.getDesc();
1153
1154  // Part of binary is determined by TableGn.
1155  unsigned Binary = getBinaryCodeForInstr(MI);
1156
1157  // Set the conditional execution predicate
1158  Binary |= II->getPredicate(&MI) << ARMII::CondShift;
1159
1160  unsigned OpIdx = 0;
1161
1162  // Encode Rd
1163  Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRdShift;
1164
1165  const MachineOperand &MO1 = MI.getOperand(OpIdx++);
1166  const MachineOperand &MO2 = MI.getOperand(OpIdx);
1167  if (MO2.isReg()) {
1168    // Two register operand form.
1169    // Encode Rn.
1170    Binary |= getMachineOpValue(MI, MO1) << ARMII::RegRnShift;
1171
1172    // Encode Rm.
1173    Binary |= getMachineOpValue(MI, MO2);
1174    ++OpIdx;
1175  } else {
1176    Binary |= getMachineOpValue(MI, MO1);
1177  }
1178
1179  // Encode rot imm (0, 8, 16, or 24) if it has a rotate immediate operand.
1180  if (MI.getOperand(OpIdx).isImm() &&
1181      !TID.OpInfo[OpIdx].isPredicate() &&
1182      !TID.OpInfo[OpIdx].isOptionalDef())
1183    Binary |= (getMachineOpValue(MI, OpIdx) / 8) << ARMII::ExtRotImmShift;
1184
1185  emitWordLE(Binary);
1186}
1187
1188void ARMCodeEmitter::emitMiscArithInstruction(const MachineInstr &MI) {
1189  const TargetInstrDesc &TID = MI.getDesc();
1190
1191  // Part of binary is determined by TableGn.
1192  unsigned Binary = getBinaryCodeForInstr(MI);
1193
1194  // Set the conditional execution predicate
1195  Binary |= II->getPredicate(&MI) << ARMII::CondShift;
1196
1197  unsigned OpIdx = 0;
1198
1199  // Encode Rd
1200  Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRdShift;
1201
1202  const MachineOperand &MO = MI.getOperand(OpIdx++);
1203  if (OpIdx == TID.getNumOperands() ||
1204      TID.OpInfo[OpIdx].isPredicate() ||
1205      TID.OpInfo[OpIdx].isOptionalDef()) {
1206    // Encode Rm and it's done.
1207    Binary |= getMachineOpValue(MI, MO);
1208    emitWordLE(Binary);
1209    return;
1210  }
1211
1212  // Encode Rn.
1213  Binary |= getMachineOpValue(MI, MO) << ARMII::RegRnShift;
1214
1215  // Encode Rm.
1216  Binary |= getMachineOpValue(MI, OpIdx++);
1217
1218  // Encode shift_imm.
1219  unsigned ShiftAmt = MI.getOperand(OpIdx).getImm();
1220  if (TID.Opcode == ARM::PKHTB) {
1221    assert(ShiftAmt != 0 && "PKHTB shift_imm is 0!");
1222    if (ShiftAmt == 32)
1223      ShiftAmt = 0;
1224  }
1225  assert(ShiftAmt < 32 && "shift_imm range is 0 to 31!");
1226  Binary |= ShiftAmt << ARMII::ShiftShift;
1227
1228  emitWordLE(Binary);
1229}
1230
1231void ARMCodeEmitter::emitSaturateInstruction(const MachineInstr &MI) {
1232  const TargetInstrDesc &TID = MI.getDesc();
1233
1234  // Part of binary is determined by TableGen.
1235  unsigned Binary = getBinaryCodeForInstr(MI);
1236
1237  // Set the conditional execution predicate
1238  Binary |= II->getPredicate(&MI) << ARMII::CondShift;
1239
1240  // Encode Rd
1241  Binary |= getMachineOpValue(MI, 0) << ARMII::RegRdShift;
1242
1243  // Encode saturate bit position.
1244  unsigned Pos = MI.getOperand(1).getImm();
1245  if (TID.Opcode == ARM::SSAT || TID.Opcode == ARM::SSAT16)
1246    Pos -= 1;
1247  assert((Pos < 16 || (Pos < 32 &&
1248                       TID.Opcode != ARM::SSAT16 &&
1249                       TID.Opcode != ARM::USAT16)) &&
1250         "saturate bit position out of range");
1251  Binary |= Pos << 16;
1252
1253  // Encode Rm
1254  Binary |= getMachineOpValue(MI, 2);
1255
1256  // Encode shift_imm.
1257  if (TID.getNumOperands() == 4) {
1258    unsigned ShiftOp = MI.getOperand(3).getImm();
1259    ARM_AM::ShiftOpc Opc = ARM_AM::getSORegShOp(ShiftOp);
1260    if (Opc == ARM_AM::asr)
1261      Binary |= (1 << 6);
1262    unsigned ShiftAmt = MI.getOperand(3).getImm();
1263    if (ShiftAmt == 32 && Opc == ARM_AM::asr)
1264      ShiftAmt = 0;
1265    assert(ShiftAmt < 32 && "shift_imm range is 0 to 31!");
1266    Binary |= ShiftAmt << ARMII::ShiftShift;
1267  }
1268
1269  emitWordLE(Binary);
1270}
1271
1272void ARMCodeEmitter::emitBranchInstruction(const MachineInstr &MI) {
1273  const TargetInstrDesc &TID = MI.getDesc();
1274
1275  if (TID.Opcode == ARM::TPsoft) {
1276    llvm_unreachable("ARM::TPsoft FIXME"); // FIXME
1277  }
1278
1279  // Part of binary is determined by TableGn.
1280  unsigned Binary = getBinaryCodeForInstr(MI);
1281
1282  // Set the conditional execution predicate
1283  Binary |= II->getPredicate(&MI) << ARMII::CondShift;
1284
1285  // Set signed_immed_24 field
1286  Binary |= getMachineOpValue(MI, 0);
1287
1288  emitWordLE(Binary);
1289}
1290
1291void ARMCodeEmitter::emitInlineJumpTable(unsigned JTIndex) {
1292  // Remember the base address of the inline jump table.
1293  uintptr_t JTBase = MCE.getCurrentPCValue();
1294  JTI->addJumpTableBaseAddr(JTIndex, JTBase);
1295  DEBUG(errs() << "  ** Jump Table #" << JTIndex << " @ " << (void*)JTBase
1296               << '\n');
1297
1298  // Now emit the jump table entries.
1299  const std::vector<MachineBasicBlock*> &MBBs = (*MJTEs)[JTIndex].MBBs;
1300  for (unsigned i = 0, e = MBBs.size(); i != e; ++i) {
1301    if (IsPIC)
1302      // DestBB address - JT base.
1303      emitMachineBasicBlock(MBBs[i], ARM::reloc_arm_pic_jt, JTBase);
1304    else
1305      // Absolute DestBB address.
1306      emitMachineBasicBlock(MBBs[i], ARM::reloc_arm_absolute);
1307    emitWordLE(0);
1308  }
1309}
1310
1311void ARMCodeEmitter::emitMiscBranchInstruction(const MachineInstr &MI) {
1312  const TargetInstrDesc &TID = MI.getDesc();
1313
1314  // Handle jump tables.
1315  if (TID.Opcode == ARM::BR_JTr || TID.Opcode == ARM::BR_JTadd) {
1316    // First emit a ldr pc, [] instruction.
1317    emitDataProcessingInstruction(MI, ARM::PC);
1318
1319    // Then emit the inline jump table.
1320    unsigned JTIndex =
1321      (TID.Opcode == ARM::BR_JTr)
1322      ? MI.getOperand(1).getIndex() : MI.getOperand(2).getIndex();
1323    emitInlineJumpTable(JTIndex);
1324    return;
1325  } else if (TID.Opcode == ARM::BR_JTm) {
1326    // First emit a ldr pc, [] instruction.
1327    emitLoadStoreInstruction(MI, ARM::PC);
1328
1329    // Then emit the inline jump table.
1330    emitInlineJumpTable(MI.getOperand(3).getIndex());
1331    return;
1332  }
1333
1334  // Part of binary is determined by TableGn.
1335  unsigned Binary = getBinaryCodeForInstr(MI);
1336
1337  // Set the conditional execution predicate
1338  Binary |= II->getPredicate(&MI) << ARMII::CondShift;
1339
1340  if (TID.Opcode == ARM::BX_RET || TID.Opcode == ARM::MOVPCLR)
1341    // The return register is LR.
1342    Binary |= getARMRegisterNumbering(ARM::LR);
1343  else
1344    // otherwise, set the return register
1345    Binary |= getMachineOpValue(MI, 0);
1346
1347  emitWordLE(Binary);
1348}
1349
1350static unsigned encodeVFPRd(const MachineInstr &MI, unsigned OpIdx) {
1351  unsigned RegD = MI.getOperand(OpIdx).getReg();
1352  unsigned Binary = 0;
1353  bool isSPVFP = ARM::SPRRegisterClass->contains(RegD);
1354  RegD = getARMRegisterNumbering(RegD);
1355  if (!isSPVFP)
1356    Binary |=   RegD               << ARMII::RegRdShift;
1357  else {
1358    Binary |= ((RegD & 0x1E) >> 1) << ARMII::RegRdShift;
1359    Binary |=  (RegD & 0x01)       << ARMII::D_BitShift;
1360  }
1361  return Binary;
1362}
1363
1364static unsigned encodeVFPRn(const MachineInstr &MI, unsigned OpIdx) {
1365  unsigned RegN = MI.getOperand(OpIdx).getReg();
1366  unsigned Binary = 0;
1367  bool isSPVFP = ARM::SPRRegisterClass->contains(RegN);
1368  RegN = getARMRegisterNumbering(RegN);
1369  if (!isSPVFP)
1370    Binary |=   RegN               << ARMII::RegRnShift;
1371  else {
1372    Binary |= ((RegN & 0x1E) >> 1) << ARMII::RegRnShift;
1373    Binary |=  (RegN & 0x01)       << ARMII::N_BitShift;
1374  }
1375  return Binary;
1376}
1377
1378static unsigned encodeVFPRm(const MachineInstr &MI, unsigned OpIdx) {
1379  unsigned RegM = MI.getOperand(OpIdx).getReg();
1380  unsigned Binary = 0;
1381  bool isSPVFP = ARM::SPRRegisterClass->contains(RegM);
1382  RegM = getARMRegisterNumbering(RegM);
1383  if (!isSPVFP)
1384    Binary |=   RegM;
1385  else {
1386    Binary |= ((RegM & 0x1E) >> 1);
1387    Binary |=  (RegM & 0x01)       << ARMII::M_BitShift;
1388  }
1389  return Binary;
1390}
1391
1392void ARMCodeEmitter::emitVFPArithInstruction(const MachineInstr &MI) {
1393  const TargetInstrDesc &TID = MI.getDesc();
1394
1395  // Part of binary is determined by TableGn.
1396  unsigned Binary = getBinaryCodeForInstr(MI);
1397
1398  // Set the conditional execution predicate
1399  Binary |= II->getPredicate(&MI) << ARMII::CondShift;
1400
1401  unsigned OpIdx = 0;
1402  assert((Binary & ARMII::D_BitShift) == 0 &&
1403         (Binary & ARMII::N_BitShift) == 0 &&
1404         (Binary & ARMII::M_BitShift) == 0 && "VFP encoding bug!");
1405
1406  // Encode Dd / Sd.
1407  Binary |= encodeVFPRd(MI, OpIdx++);
1408
1409  // If this is a two-address operand, skip it, e.g. FMACD.
1410  if (TID.getOperandConstraint(OpIdx, TOI::TIED_TO) != -1)
1411    ++OpIdx;
1412
1413  // Encode Dn / Sn.
1414  if ((TID.TSFlags & ARMII::FormMask) == ARMII::VFPBinaryFrm)
1415    Binary |= encodeVFPRn(MI, OpIdx++);
1416
1417  if (OpIdx == TID.getNumOperands() ||
1418      TID.OpInfo[OpIdx].isPredicate() ||
1419      TID.OpInfo[OpIdx].isOptionalDef()) {
1420    // FCMPEZD etc. has only one operand.
1421    emitWordLE(Binary);
1422    return;
1423  }
1424
1425  // Encode Dm / Sm.
1426  Binary |= encodeVFPRm(MI, OpIdx);
1427
1428  emitWordLE(Binary);
1429}
1430
1431void ARMCodeEmitter::emitVFPConversionInstruction(const MachineInstr &MI) {
1432  const TargetInstrDesc &TID = MI.getDesc();
1433  unsigned Form = TID.TSFlags & ARMII::FormMask;
1434
1435  // Part of binary is determined by TableGn.
1436  unsigned Binary = getBinaryCodeForInstr(MI);
1437
1438  // Set the conditional execution predicate
1439  Binary |= II->getPredicate(&MI) << ARMII::CondShift;
1440
1441  switch (Form) {
1442  default: break;
1443  case ARMII::VFPConv1Frm:
1444  case ARMII::VFPConv2Frm:
1445  case ARMII::VFPConv3Frm:
1446    // Encode Dd / Sd.
1447    Binary |= encodeVFPRd(MI, 0);
1448    break;
1449  case ARMII::VFPConv4Frm:
1450    // Encode Dn / Sn.
1451    Binary |= encodeVFPRn(MI, 0);
1452    break;
1453  case ARMII::VFPConv5Frm:
1454    // Encode Dm / Sm.
1455    Binary |= encodeVFPRm(MI, 0);
1456    break;
1457  }
1458
1459  switch (Form) {
1460  default: break;
1461  case ARMII::VFPConv1Frm:
1462    // Encode Dm / Sm.
1463    Binary |= encodeVFPRm(MI, 1);
1464    break;
1465  case ARMII::VFPConv2Frm:
1466  case ARMII::VFPConv3Frm:
1467    // Encode Dn / Sn.
1468    Binary |= encodeVFPRn(MI, 1);
1469    break;
1470  case ARMII::VFPConv4Frm:
1471  case ARMII::VFPConv5Frm:
1472    // Encode Dd / Sd.
1473    Binary |= encodeVFPRd(MI, 1);
1474    break;
1475  }
1476
1477  if (Form == ARMII::VFPConv5Frm)
1478    // Encode Dn / Sn.
1479    Binary |= encodeVFPRn(MI, 2);
1480  else if (Form == ARMII::VFPConv3Frm)
1481    // Encode Dm / Sm.
1482    Binary |= encodeVFPRm(MI, 2);
1483
1484  emitWordLE(Binary);
1485}
1486
1487void ARMCodeEmitter::emitVFPLoadStoreInstruction(const MachineInstr &MI) {
1488  // Part of binary is determined by TableGn.
1489  unsigned Binary = getBinaryCodeForInstr(MI);
1490
1491  // Set the conditional execution predicate
1492  Binary |= II->getPredicate(&MI) << ARMII::CondShift;
1493
1494  unsigned OpIdx = 0;
1495
1496  // Encode Dd / Sd.
1497  Binary |= encodeVFPRd(MI, OpIdx++);
1498
1499  // Encode address base.
1500  const MachineOperand &Base = MI.getOperand(OpIdx++);
1501  Binary |= getMachineOpValue(MI, Base) << ARMII::RegRnShift;
1502
1503  // If there is a non-zero immediate offset, encode it.
1504  if (Base.isReg()) {
1505    const MachineOperand &Offset = MI.getOperand(OpIdx);
1506    if (unsigned ImmOffs = ARM_AM::getAM5Offset(Offset.getImm())) {
1507      if (ARM_AM::getAM5Op(Offset.getImm()) == ARM_AM::add)
1508        Binary |= 1 << ARMII::U_BitShift;
1509      Binary |= ImmOffs;
1510      emitWordLE(Binary);
1511      return;
1512    }
1513  }
1514
1515  // If immediate offset is omitted, default to +0.
1516  Binary |= 1 << ARMII::U_BitShift;
1517
1518  emitWordLE(Binary);
1519}
1520
1521void
1522ARMCodeEmitter::emitVFPLoadStoreMultipleInstruction(const MachineInstr &MI) {
1523  const TargetInstrDesc &TID = MI.getDesc();
1524  bool IsUpdating = (TID.TSFlags & ARMII::IndexModeMask) != 0;
1525
1526  // Part of binary is determined by TableGn.
1527  unsigned Binary = getBinaryCodeForInstr(MI);
1528
1529  // Set the conditional execution predicate
1530  Binary |= II->getPredicate(&MI) << ARMII::CondShift;
1531
1532  // Skip operand 0 of an instruction with base register update.
1533  unsigned OpIdx = 0;
1534  if (IsUpdating)
1535    ++OpIdx;
1536
1537  // Set base address operand
1538  Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRnShift;
1539
1540  // Set addressing mode by modifying bits U(23) and P(24)
1541  const MachineOperand &MO = MI.getOperand(OpIdx++);
1542  Binary |= getAddrModeUPBits(ARM_AM::getAM4SubMode(MO.getImm()));
1543
1544  // Set bit W(21)
1545  if (IsUpdating)
1546    Binary |= 0x1 << ARMII::W_BitShift;
1547
1548  // First register is encoded in Dd.
1549  Binary |= encodeVFPRd(MI, OpIdx+2);
1550
1551  // Count the number of registers.
1552  unsigned NumRegs = 1;
1553  for (unsigned i = OpIdx+3, e = MI.getNumOperands(); i != e; ++i) {
1554    const MachineOperand &MO = MI.getOperand(i);
1555    if (!MO.isReg() || MO.isImplicit())
1556      break;
1557    ++NumRegs;
1558  }
1559  // Bit 8 will be set if <list> is consecutive 64-bit registers (e.g., D0)
1560  // Otherwise, it will be 0, in the case of 32-bit registers.
1561  if(Binary & 0x100)
1562    Binary |= NumRegs * 2;
1563  else
1564    Binary |= NumRegs;
1565
1566  emitWordLE(Binary);
1567}
1568
1569void ARMCodeEmitter::emitMiscInstruction(const MachineInstr &MI) {
1570  unsigned Opcode = MI.getDesc().Opcode;
1571  // Part of binary is determined by TableGn.
1572  unsigned Binary = getBinaryCodeForInstr(MI);
1573
1574  // Set the conditional execution predicate
1575  Binary |= II->getPredicate(&MI) << ARMII::CondShift;
1576
1577  switch(Opcode) {
1578  default:
1579    llvm_unreachable("ARMCodeEmitter::emitMiscInstruction");
1580
1581  case ARM::FMSTAT:
1582    // No further encoding needed.
1583    break;
1584
1585  case ARM::VMRS:
1586  case ARM::VMSR: {
1587    const MachineOperand &MO0 = MI.getOperand(0);
1588    // Encode Rt.
1589    Binary |= getARMRegisterNumbering(MO0.getReg()) << ARMII::RegRdShift;
1590    break;
1591  }
1592
1593  case ARM::FCONSTD:
1594  case ARM::FCONSTS: {
1595    // Encode Dd / Sd.
1596    Binary |= encodeVFPRd(MI, 0);
1597
1598    // Encode imm., Table A7-18 VFP modified immediate constants
1599    const MachineOperand &MO1 = MI.getOperand(1);
1600    unsigned Imm = static_cast<unsigned>(MO1.getFPImm()->getValueAPF()
1601                      .bitcastToAPInt().getHiBits(32).getLimitedValue());
1602    unsigned ModifiedImm;
1603
1604    if(Opcode == ARM::FCONSTS)
1605      ModifiedImm = (Imm & 0x80000000) >> 24 | // a
1606                    (Imm & 0x03F80000) >> 19;  // bcdefgh
1607    else // Opcode == ARM::FCONSTD
1608      ModifiedImm = (Imm & 0x80000000) >> 24 | // a
1609                    (Imm & 0x007F0000) >> 16;  // bcdefgh
1610
1611    // Insts{19-16} = abcd, Insts{3-0} = efgh
1612    Binary |= ((ModifiedImm & 0xF0) >> 4) << 16;
1613    Binary |= (ModifiedImm & 0xF);
1614    break;
1615  }
1616  }
1617
1618  emitWordLE(Binary);
1619}
1620
1621static unsigned encodeNEONRd(const MachineInstr &MI, unsigned OpIdx) {
1622  unsigned RegD = MI.getOperand(OpIdx).getReg();
1623  unsigned Binary = 0;
1624  RegD = getARMRegisterNumbering(RegD);
1625  Binary |= (RegD & 0xf) << ARMII::RegRdShift;
1626  Binary |= ((RegD >> 4) & 1) << ARMII::D_BitShift;
1627  return Binary;
1628}
1629
1630static unsigned encodeNEONRn(const MachineInstr &MI, unsigned OpIdx) {
1631  unsigned RegN = MI.getOperand(OpIdx).getReg();
1632  unsigned Binary = 0;
1633  RegN = getARMRegisterNumbering(RegN);
1634  Binary |= (RegN & 0xf) << ARMII::RegRnShift;
1635  Binary |= ((RegN >> 4) & 1) << ARMII::N_BitShift;
1636  return Binary;
1637}
1638
1639static unsigned encodeNEONRm(const MachineInstr &MI, unsigned OpIdx) {
1640  unsigned RegM = MI.getOperand(OpIdx).getReg();
1641  unsigned Binary = 0;
1642  RegM = getARMRegisterNumbering(RegM);
1643  Binary |= (RegM & 0xf);
1644  Binary |= ((RegM >> 4) & 1) << ARMII::M_BitShift;
1645  return Binary;
1646}
1647
1648/// convertNEONDataProcToThumb - Convert the ARM mode encoding for a NEON
1649/// data-processing instruction to the corresponding Thumb encoding.
1650static unsigned convertNEONDataProcToThumb(unsigned Binary) {
1651  assert((Binary & 0xfe000000) == 0xf2000000 &&
1652         "not an ARM NEON data-processing instruction");
1653  unsigned UBit = (Binary >> 24) & 1;
1654  return 0xef000000 | (UBit << 28) | (Binary & 0xffffff);
1655}
1656
1657void ARMCodeEmitter::emitNEONLaneInstruction(const MachineInstr &MI) {
1658  unsigned Binary = getBinaryCodeForInstr(MI);
1659
1660  unsigned RegTOpIdx, RegNOpIdx, LnOpIdx;
1661  const TargetInstrDesc &TID = MI.getDesc();
1662  if ((TID.TSFlags & ARMII::FormMask) == ARMII::NGetLnFrm) {
1663    RegTOpIdx = 0;
1664    RegNOpIdx = 1;
1665    LnOpIdx = 2;
1666  } else { // ARMII::NSetLnFrm
1667    RegTOpIdx = 2;
1668    RegNOpIdx = 0;
1669    LnOpIdx = 3;
1670  }
1671
1672  // Set the conditional execution predicate
1673  Binary |= (IsThumb ? ARMCC::AL : II->getPredicate(&MI)) << ARMII::CondShift;
1674
1675  unsigned RegT = MI.getOperand(RegTOpIdx).getReg();
1676  RegT = getARMRegisterNumbering(RegT);
1677  Binary |= (RegT << ARMII::RegRdShift);
1678  Binary |= encodeNEONRn(MI, RegNOpIdx);
1679
1680  unsigned LaneShift;
1681  if ((Binary & (1 << 22)) != 0)
1682    LaneShift = 0; // 8-bit elements
1683  else if ((Binary & (1 << 5)) != 0)
1684    LaneShift = 1; // 16-bit elements
1685  else
1686    LaneShift = 2; // 32-bit elements
1687
1688  unsigned Lane = MI.getOperand(LnOpIdx).getImm() << LaneShift;
1689  unsigned Opc1 = Lane >> 2;
1690  unsigned Opc2 = Lane & 3;
1691  assert((Opc1 & 3) == 0 && "out-of-range lane number operand");
1692  Binary |= (Opc1 << 21);
1693  Binary |= (Opc2 << 5);
1694
1695  emitWordLE(Binary);
1696}
1697
1698void ARMCodeEmitter::emitNEONDupInstruction(const MachineInstr &MI) {
1699  unsigned Binary = getBinaryCodeForInstr(MI);
1700
1701  // Set the conditional execution predicate
1702  Binary |= (IsThumb ? ARMCC::AL : II->getPredicate(&MI)) << ARMII::CondShift;
1703
1704  unsigned RegT = MI.getOperand(1).getReg();
1705  RegT = getARMRegisterNumbering(RegT);
1706  Binary |= (RegT << ARMII::RegRdShift);
1707  Binary |= encodeNEONRn(MI, 0);
1708  emitWordLE(Binary);
1709}
1710
1711void ARMCodeEmitter::emitNEON1RegModImmInstruction(const MachineInstr &MI) {
1712  unsigned Binary = getBinaryCodeForInstr(MI);
1713  // Destination register is encoded in Dd.
1714  Binary |= encodeNEONRd(MI, 0);
1715  // Immediate fields: Op, Cmode, I, Imm3, Imm4
1716  unsigned Imm = MI.getOperand(1).getImm();
1717  unsigned Op = (Imm >> 12) & 1;
1718  unsigned Cmode = (Imm >> 8) & 0xf;
1719  unsigned I = (Imm >> 7) & 1;
1720  unsigned Imm3 = (Imm >> 4) & 0x7;
1721  unsigned Imm4 = Imm & 0xf;
1722  Binary |= (I << 24) | (Imm3 << 16) | (Cmode << 8) | (Op << 5) | Imm4;
1723  if (IsThumb)
1724    Binary = convertNEONDataProcToThumb(Binary);
1725  emitWordLE(Binary);
1726}
1727
1728void ARMCodeEmitter::emitNEON2RegInstruction(const MachineInstr &MI) {
1729  const TargetInstrDesc &TID = MI.getDesc();
1730  unsigned Binary = getBinaryCodeForInstr(MI);
1731  // Destination register is encoded in Dd; source register in Dm.
1732  unsigned OpIdx = 0;
1733  Binary |= encodeNEONRd(MI, OpIdx++);
1734  if (TID.getOperandConstraint(OpIdx, TOI::TIED_TO) != -1)
1735    ++OpIdx;
1736  Binary |= encodeNEONRm(MI, OpIdx);
1737  if (IsThumb)
1738    Binary = convertNEONDataProcToThumb(Binary);
1739  // FIXME: This does not handle VDUPfdf or VDUPfqf.
1740  emitWordLE(Binary);
1741}
1742
1743void ARMCodeEmitter::emitNEON3RegInstruction(const MachineInstr &MI) {
1744  const TargetInstrDesc &TID = MI.getDesc();
1745  unsigned Binary = getBinaryCodeForInstr(MI);
1746  // Destination register is encoded in Dd; source registers in Dn and Dm.
1747  unsigned OpIdx = 0;
1748  Binary |= encodeNEONRd(MI, OpIdx++);
1749  if (TID.getOperandConstraint(OpIdx, TOI::TIED_TO) != -1)
1750    ++OpIdx;
1751  Binary |= encodeNEONRn(MI, OpIdx++);
1752  if (TID.getOperandConstraint(OpIdx, TOI::TIED_TO) != -1)
1753    ++OpIdx;
1754  Binary |= encodeNEONRm(MI, OpIdx);
1755  if (IsThumb)
1756    Binary = convertNEONDataProcToThumb(Binary);
1757  // FIXME: This does not handle VMOVDneon or VMOVQ.
1758  emitWordLE(Binary);
1759}
1760
1761#include "ARMGenCodeEmitter.inc"
1762