ARMCodeEmitter.cpp revision dce4a407a24b04eebc6a376f8e62b41aaa7b071f
1//===-- ARM/ARMCodeEmitter.cpp - Convert ARM code to machine code ---------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file contains the pass that transforms the ARM machine instructions into 11// relocatable machine code. 12// 13//===----------------------------------------------------------------------===// 14 15#include "ARM.h" 16#include "ARMBaseInstrInfo.h" 17#include "ARMConstantPoolValue.h" 18#include "ARMRelocations.h" 19#include "ARMSubtarget.h" 20#include "ARMTargetMachine.h" 21#include "MCTargetDesc/ARMAddressingModes.h" 22#include "llvm/ADT/Statistic.h" 23#include "llvm/CodeGen/JITCodeEmitter.h" 24#include "llvm/CodeGen/MachineConstantPool.h" 25#include "llvm/CodeGen/MachineFunctionPass.h" 26#include "llvm/CodeGen/MachineInstr.h" 27#include "llvm/CodeGen/MachineJumpTableInfo.h" 28#include "llvm/CodeGen/MachineModuleInfo.h" 29#include "llvm/CodeGen/Passes.h" 30#include "llvm/IR/Constants.h" 31#include "llvm/IR/DerivedTypes.h" 32#include "llvm/IR/Function.h" 33#include "llvm/PassManager.h" 34#include "llvm/Support/Debug.h" 35#include "llvm/Support/ErrorHandling.h" 36#include "llvm/Support/raw_ostream.h" 37#ifndef NDEBUG 38#include <iomanip> 39#endif 40using namespace llvm; 41 42#define DEBUG_TYPE "jit" 43 44STATISTIC(NumEmitted, "Number of machine instructions emitted"); 45 46namespace { 47 48 class ARMCodeEmitter : public MachineFunctionPass { 49 ARMJITInfo *JTI; 50 const ARMBaseInstrInfo *II; 51 const DataLayout *TD; 52 const ARMSubtarget *Subtarget; 53 TargetMachine &TM; 54 JITCodeEmitter &MCE; 55 MachineModuleInfo *MMI; 56 const std::vector<MachineConstantPoolEntry> *MCPEs; 57 const std::vector<MachineJumpTableEntry> *MJTEs; 58 bool IsPIC; 59 bool IsThumb; 60 61 void getAnalysisUsage(AnalysisUsage &AU) const override { 62 AU.addRequired<MachineModuleInfo>(); 63 MachineFunctionPass::getAnalysisUsage(AU); 64 } 65 66 static char ID; 67 public: 68 ARMCodeEmitter(TargetMachine &tm, JITCodeEmitter &mce) 69 : MachineFunctionPass(ID), JTI(nullptr), 70 II((const ARMBaseInstrInfo *)tm.getInstrInfo()), 71 TD(tm.getDataLayout()), TM(tm), 72 MCE(mce), MCPEs(nullptr), MJTEs(nullptr), 73 IsPIC(TM.getRelocationModel() == Reloc::PIC_), IsThumb(false) {} 74 75 /// getBinaryCodeForInstr - This function, generated by the 76 /// CodeEmitterGenerator using TableGen, produces the binary encoding for 77 /// machine instructions. 78 uint64_t getBinaryCodeForInstr(const MachineInstr &MI) const; 79 80 bool runOnMachineFunction(MachineFunction &MF) override; 81 82 const char *getPassName() const override { 83 return "ARM Machine Code Emitter"; 84 } 85 86 void emitInstruction(const MachineInstr &MI); 87 88 private: 89 90 void emitWordLE(unsigned Binary); 91 void emitDWordLE(uint64_t Binary); 92 void emitConstPoolInstruction(const MachineInstr &MI); 93 void emitMOVi32immInstruction(const MachineInstr &MI); 94 void emitMOVi2piecesInstruction(const MachineInstr &MI); 95 void emitLEApcrelJTInstruction(const MachineInstr &MI); 96 void emitPseudoMoveInstruction(const MachineInstr &MI); 97 void addPCLabel(unsigned LabelID); 98 void emitPseudoInstruction(const MachineInstr &MI); 99 unsigned getMachineSoRegOpValue(const MachineInstr &MI, 100 const MCInstrDesc &MCID, 101 const MachineOperand &MO, 102 unsigned OpIdx); 103 104 unsigned getMachineSoImmOpValue(unsigned SoImm); 105 unsigned getAddrModeSBit(const MachineInstr &MI, 106 const MCInstrDesc &MCID) const; 107 108 void emitDataProcessingInstruction(const MachineInstr &MI, 109 unsigned ImplicitRd = 0, 110 unsigned ImplicitRn = 0); 111 112 void emitLoadStoreInstruction(const MachineInstr &MI, 113 unsigned ImplicitRd = 0, 114 unsigned ImplicitRn = 0); 115 116 void emitMiscLoadStoreInstruction(const MachineInstr &MI, 117 unsigned ImplicitRn = 0); 118 119 void emitLoadStoreMultipleInstruction(const MachineInstr &MI); 120 121 void emitMulFrmInstruction(const MachineInstr &MI); 122 123 void emitExtendInstruction(const MachineInstr &MI); 124 125 void emitMiscArithInstruction(const MachineInstr &MI); 126 127 void emitSaturateInstruction(const MachineInstr &MI); 128 129 void emitBranchInstruction(const MachineInstr &MI); 130 131 void emitInlineJumpTable(unsigned JTIndex); 132 133 void emitMiscBranchInstruction(const MachineInstr &MI); 134 135 void emitVFPArithInstruction(const MachineInstr &MI); 136 137 void emitVFPConversionInstruction(const MachineInstr &MI); 138 139 void emitVFPLoadStoreInstruction(const MachineInstr &MI); 140 141 void emitVFPLoadStoreMultipleInstruction(const MachineInstr &MI); 142 143 void emitNEONLaneInstruction(const MachineInstr &MI); 144 void emitNEONDupInstruction(const MachineInstr &MI); 145 void emitNEON1RegModImmInstruction(const MachineInstr &MI); 146 void emitNEON2RegInstruction(const MachineInstr &MI); 147 void emitNEON3RegInstruction(const MachineInstr &MI); 148 149 /// getMachineOpValue - Return binary encoding of operand. If the machine 150 /// operand requires relocation, record the relocation and return zero. 151 unsigned getMachineOpValue(const MachineInstr &MI, 152 const MachineOperand &MO) const; 153 unsigned getMachineOpValue(const MachineInstr &MI, unsigned OpIdx) const { 154 return getMachineOpValue(MI, MI.getOperand(OpIdx)); 155 } 156 157 // FIXME: The legacy JIT ARMCodeEmitter doesn't rely on the the 158 // TableGen'erated getBinaryCodeForInstr() function to encode any 159 // operand values, instead querying getMachineOpValue() directly for 160 // each operand it needs to encode. Thus, any of the new encoder 161 // helper functions can simply return 0 as the values the return 162 // are already handled elsewhere. They are placeholders to allow this 163 // encoder to continue to function until the MC encoder is sufficiently 164 // far along that this one can be eliminated entirely. 165 unsigned NEONThumb2DataIPostEncoder(const MachineInstr &MI, unsigned Val) 166 const { return 0; } 167 unsigned NEONThumb2LoadStorePostEncoder(const MachineInstr &MI,unsigned Val) 168 const { return 0; } 169 unsigned NEONThumb2DupPostEncoder(const MachineInstr &MI,unsigned Val) 170 const { return 0; } 171 unsigned NEONThumb2V8PostEncoder(const MachineInstr &MI,unsigned Val) 172 const { return 0; } 173 unsigned VFPThumb2PostEncoder(const MachineInstr&MI, unsigned Val) 174 const { return 0; } 175 unsigned getAdrLabelOpValue(const MachineInstr &MI, unsigned Op) 176 const { return 0; } 177 unsigned getThumbAdrLabelOpValue(const MachineInstr &MI, unsigned Op) 178 const { return 0; } 179 unsigned getThumbBLTargetOpValue(const MachineInstr &MI, unsigned Op) 180 const { return 0; } 181 unsigned getThumbBLXTargetOpValue(const MachineInstr &MI, unsigned Op) 182 const { return 0; } 183 unsigned getThumbBRTargetOpValue(const MachineInstr &MI, unsigned Op) 184 const { return 0; } 185 unsigned getThumbBCCTargetOpValue(const MachineInstr &MI, unsigned Op) 186 const { return 0; } 187 unsigned getThumbCBTargetOpValue(const MachineInstr &MI, unsigned Op) 188 const { return 0; } 189 unsigned getBranchTargetOpValue(const MachineInstr &MI, unsigned Op) 190 const { return 0; } 191 unsigned getUnconditionalBranchTargetOpValue(const MachineInstr &MI, 192 unsigned Op) const { return 0; } 193 unsigned getARMBranchTargetOpValue(const MachineInstr &MI, unsigned Op) 194 const { return 0; } 195 unsigned getARMBLTargetOpValue(const MachineInstr &MI, unsigned Op) 196 const { return 0; } 197 unsigned getARMBLXTargetOpValue(const MachineInstr &MI, unsigned Op) 198 const { return 0; } 199 unsigned getCCOutOpValue(const MachineInstr &MI, unsigned Op) 200 const { return 0; } 201 unsigned getSOImmOpValue(const MachineInstr &MI, unsigned Op) 202 const { return 0; } 203 unsigned getT2SOImmOpValue(const MachineInstr &MI, unsigned Op) 204 const { return 0; } 205 unsigned getSORegRegOpValue(const MachineInstr &MI, unsigned Op) 206 const { return 0; } 207 unsigned getSORegImmOpValue(const MachineInstr &MI, unsigned Op) 208 const { return 0; } 209 unsigned getThumbAddrModeRegRegOpValue(const MachineInstr &MI, unsigned Op) 210 const { return 0; } 211 unsigned getT2AddrModeImm8OpValue(const MachineInstr &MI, unsigned Op) 212 const { return 0; } 213 unsigned getT2Imm8s4OpValue(const MachineInstr &MI, unsigned Op) 214 const { return 0; } 215 unsigned getT2AddrModeImm8s4OpValue(const MachineInstr &MI, unsigned Op) 216 const { return 0; } 217 unsigned getT2AddrModeImm0_1020s4OpValue(const MachineInstr &MI,unsigned Op) 218 const { return 0; } 219 unsigned getT2AddrModeImm8OffsetOpValue(const MachineInstr &MI, unsigned Op) 220 const { return 0; } 221 unsigned getT2AddrModeSORegOpValue(const MachineInstr &MI, unsigned Op) 222 const { return 0; } 223 unsigned getT2SORegOpValue(const MachineInstr &MI, unsigned Op) 224 const { return 0; } 225 unsigned getT2AdrLabelOpValue(const MachineInstr &MI, unsigned Op) 226 const { return 0; } 227 unsigned getAddrMode6AddressOpValue(const MachineInstr &MI, unsigned Op) 228 const { return 0; } 229 unsigned getAddrMode6OneLane32AddressOpValue(const MachineInstr &MI, 230 unsigned Op) 231 const { return 0; } 232 unsigned getAddrMode6DupAddressOpValue(const MachineInstr &MI, unsigned Op) 233 const { return 0; } 234 unsigned getAddrMode6OffsetOpValue(const MachineInstr &MI, unsigned Op) 235 const { return 0; } 236 unsigned getBitfieldInvertedMaskOpValue(const MachineInstr &MI, 237 unsigned Op) const { return 0; } 238 uint32_t getLdStSORegOpValue(const MachineInstr &MI, unsigned OpIdx) 239 const { return 0; } 240 241 unsigned getAddrModeImm12OpValue(const MachineInstr &MI, unsigned Op) 242 const { 243 // {17-13} = reg 244 // {12} = (U)nsigned (add == '1', sub == '0') 245 // {11-0} = imm12 246 const MachineOperand &MO = MI.getOperand(Op); 247 const MachineOperand &MO1 = MI.getOperand(Op + 1); 248 if (!MO.isReg()) { 249 emitConstPoolAddress(MO.getIndex(), ARM::reloc_arm_cp_entry); 250 return 0; 251 } 252 unsigned Reg = II->getRegisterInfo().getEncodingValue(MO.getReg()); 253 int32_t Imm12 = MO1.getImm(); 254 uint32_t Binary; 255 Binary = Imm12 & 0xfff; 256 if (Imm12 >= 0) 257 Binary |= (1 << 12); 258 Binary |= (Reg << 13); 259 return Binary; 260 } 261 262 unsigned getHiLo16ImmOpValue(const MachineInstr &MI, unsigned Op) const { 263 return 0; 264 } 265 266 uint32_t getAddrMode2OffsetOpValue(const MachineInstr &MI, unsigned OpIdx) 267 const { return 0;} 268 uint32_t getPostIdxRegOpValue(const MachineInstr &MI, unsigned OpIdx) 269 const { return 0;} 270 uint32_t getAddrMode3OffsetOpValue(const MachineInstr &MI, unsigned OpIdx) 271 const { return 0;} 272 uint32_t getAddrMode3OpValue(const MachineInstr &MI, unsigned Op) 273 const { return 0; } 274 uint32_t getAddrModeThumbSPOpValue(const MachineInstr &MI, unsigned Op) 275 const { return 0; } 276 uint32_t getAddrModeISOpValue(const MachineInstr &MI, unsigned Op) 277 const { return 0; } 278 uint32_t getAddrModePCOpValue(const MachineInstr &MI, unsigned Op) 279 const { return 0; } 280 uint32_t getAddrMode5OpValue(const MachineInstr &MI, unsigned Op) const { 281 // {17-13} = reg 282 // {12} = (U)nsigned (add == '1', sub == '0') 283 // {11-0} = imm12 284 const MachineOperand &MO = MI.getOperand(Op); 285 const MachineOperand &MO1 = MI.getOperand(Op + 1); 286 if (!MO.isReg()) { 287 emitConstPoolAddress(MO.getIndex(), ARM::reloc_arm_cp_entry); 288 return 0; 289 } 290 unsigned Reg = II->getRegisterInfo().getEncodingValue(MO.getReg()); 291 int32_t Imm12 = MO1.getImm(); 292 293 // Special value for #-0 294 if (Imm12 == INT32_MIN) 295 Imm12 = 0; 296 297 // Immediate is always encoded as positive. The 'U' bit controls add vs 298 // sub. 299 bool isAdd = true; 300 if (Imm12 < 0) { 301 Imm12 = -Imm12; 302 isAdd = false; 303 } 304 305 uint32_t Binary = Imm12 & 0xfff; 306 if (isAdd) 307 Binary |= (1 << 12); 308 Binary |= (Reg << 13); 309 return Binary; 310 } 311 unsigned getNEONVcvtImm32OpValue(const MachineInstr &MI, unsigned Op) 312 const { return 0; } 313 314 unsigned getRegisterListOpValue(const MachineInstr &MI, unsigned Op) 315 const { return 0; } 316 317 unsigned getShiftRight8Imm(const MachineInstr &MI, unsigned Op) 318 const { return 0; } 319 unsigned getShiftRight16Imm(const MachineInstr &MI, unsigned Op) 320 const { return 0; } 321 unsigned getShiftRight32Imm(const MachineInstr &MI, unsigned Op) 322 const { return 0; } 323 unsigned getShiftRight64Imm(const MachineInstr &MI, unsigned Op) 324 const { return 0; } 325 326 /// getMovi32Value - Return binary encoding of operand for movw/movt. If the 327 /// machine operand requires relocation, record the relocation and return 328 /// zero. 329 unsigned getMovi32Value(const MachineInstr &MI,const MachineOperand &MO, 330 unsigned Reloc); 331 332 /// getShiftOp - Return the shift opcode (bit[6:5]) of the immediate value. 333 /// 334 unsigned getShiftOp(unsigned Imm) const ; 335 336 /// Routines that handle operands which add machine relocations which are 337 /// fixed up by the relocation stage. 338 void emitGlobalAddress(const GlobalValue *GV, unsigned Reloc, 339 bool MayNeedFarStub, bool Indirect, 340 intptr_t ACPV = 0) const; 341 void emitExternalSymbolAddress(const char *ES, unsigned Reloc) const; 342 void emitConstPoolAddress(unsigned CPI, unsigned Reloc) const; 343 void emitJumpTableAddress(unsigned JTIndex, unsigned Reloc) const; 344 void emitMachineBasicBlock(MachineBasicBlock *BB, unsigned Reloc, 345 intptr_t JTBase = 0) const; 346 unsigned encodeVFPRd(const MachineInstr &MI, unsigned OpIdx) const; 347 unsigned encodeVFPRn(const MachineInstr &MI, unsigned OpIdx) const; 348 unsigned encodeVFPRm(const MachineInstr &MI, unsigned OpIdx) const; 349 unsigned encodeNEONRd(const MachineInstr &MI, unsigned OpIdx) const; 350 unsigned encodeNEONRn(const MachineInstr &MI, unsigned OpIdx) const; 351 unsigned encodeNEONRm(const MachineInstr &MI, unsigned OpIdx) const; 352 }; 353} 354 355char ARMCodeEmitter::ID = 0; 356 357/// createARMJITCodeEmitterPass - Return a pass that emits the collected ARM 358/// code to the specified MCE object. 359FunctionPass *llvm::createARMJITCodeEmitterPass(ARMBaseTargetMachine &TM, 360 JITCodeEmitter &JCE) { 361 return new ARMCodeEmitter(TM, JCE); 362} 363 364bool ARMCodeEmitter::runOnMachineFunction(MachineFunction &MF) { 365 TargetMachine &Target = const_cast<TargetMachine&>(MF.getTarget()); 366 367 assert((Target.getRelocationModel() != Reloc::Default || 368 Target.getRelocationModel() != Reloc::Static) && 369 "JIT relocation model must be set to static or default!"); 370 371 JTI = static_cast<ARMJITInfo*>(Target.getJITInfo()); 372 II = static_cast<const ARMBaseInstrInfo*>(Target.getInstrInfo()); 373 TD = Target.getDataLayout(); 374 375 Subtarget = &TM.getSubtarget<ARMSubtarget>(); 376 MCPEs = &MF.getConstantPool()->getConstants(); 377 MJTEs = nullptr; 378 if (MF.getJumpTableInfo()) MJTEs = &MF.getJumpTableInfo()->getJumpTables(); 379 IsPIC = TM.getRelocationModel() == Reloc::PIC_; 380 IsThumb = MF.getInfo<ARMFunctionInfo>()->isThumbFunction(); 381 JTI->Initialize(MF, IsPIC); 382 MMI = &getAnalysis<MachineModuleInfo>(); 383 MCE.setModuleInfo(MMI); 384 385 do { 386 DEBUG(errs() << "JITTing function '" 387 << MF.getName() << "'\n"); 388 MCE.startFunction(MF); 389 for (MachineFunction::iterator MBB = MF.begin(), E = MF.end(); 390 MBB != E; ++MBB) { 391 MCE.StartMachineBasicBlock(MBB); 392 for (MachineBasicBlock::iterator I = MBB->begin(), E = MBB->end(); 393 I != E; ++I) 394 emitInstruction(*I); 395 } 396 } while (MCE.finishFunction(MF)); 397 398 return false; 399} 400 401/// getShiftOp - Return the shift opcode (bit[6:5]) of the immediate value. 402/// 403unsigned ARMCodeEmitter::getShiftOp(unsigned Imm) const { 404 switch (ARM_AM::getAM2ShiftOpc(Imm)) { 405 default: llvm_unreachable("Unknown shift opc!"); 406 case ARM_AM::asr: return 2; 407 case ARM_AM::lsl: return 0; 408 case ARM_AM::lsr: return 1; 409 case ARM_AM::ror: 410 case ARM_AM::rrx: return 3; 411 } 412} 413 414/// getMovi32Value - Return binary encoding of operand for movw/movt. If the 415/// machine operand requires relocation, record the relocation and return zero. 416unsigned ARMCodeEmitter::getMovi32Value(const MachineInstr &MI, 417 const MachineOperand &MO, 418 unsigned Reloc) { 419 assert(((Reloc == ARM::reloc_arm_movt) || (Reloc == ARM::reloc_arm_movw)) 420 && "Relocation to this function should be for movt or movw"); 421 422 if (MO.isImm()) 423 return static_cast<unsigned>(MO.getImm()); 424 else if (MO.isGlobal()) 425 emitGlobalAddress(MO.getGlobal(), Reloc, true, false); 426 else if (MO.isSymbol()) 427 emitExternalSymbolAddress(MO.getSymbolName(), Reloc); 428 else if (MO.isMBB()) 429 emitMachineBasicBlock(MO.getMBB(), Reloc); 430 else { 431#ifndef NDEBUG 432 errs() << MO; 433#endif 434 llvm_unreachable("Unsupported operand type for movw/movt"); 435 } 436 return 0; 437} 438 439/// getMachineOpValue - Return binary encoding of operand. If the machine 440/// operand requires relocation, record the relocation and return zero. 441unsigned ARMCodeEmitter::getMachineOpValue(const MachineInstr &MI, 442 const MachineOperand &MO) const { 443 if (MO.isReg()) 444 return II->getRegisterInfo().getEncodingValue(MO.getReg()); 445 else if (MO.isImm()) 446 return static_cast<unsigned>(MO.getImm()); 447 else if (MO.isGlobal()) 448 emitGlobalAddress(MO.getGlobal(), ARM::reloc_arm_branch, true, false); 449 else if (MO.isSymbol()) 450 emitExternalSymbolAddress(MO.getSymbolName(), ARM::reloc_arm_branch); 451 else if (MO.isCPI()) { 452 const MCInstrDesc &MCID = MI.getDesc(); 453 // For VFP load, the immediate offset is multiplied by 4. 454 unsigned Reloc = ((MCID.TSFlags & ARMII::FormMask) == ARMII::VFPLdStFrm) 455 ? ARM::reloc_arm_vfp_cp_entry : ARM::reloc_arm_cp_entry; 456 emitConstPoolAddress(MO.getIndex(), Reloc); 457 } else if (MO.isJTI()) 458 emitJumpTableAddress(MO.getIndex(), ARM::reloc_arm_relative); 459 else if (MO.isMBB()) 460 emitMachineBasicBlock(MO.getMBB(), ARM::reloc_arm_branch); 461 else 462 llvm_unreachable("Unable to encode MachineOperand!"); 463 return 0; 464} 465 466/// emitGlobalAddress - Emit the specified address to the code stream. 467/// 468void ARMCodeEmitter::emitGlobalAddress(const GlobalValue *GV, unsigned Reloc, 469 bool MayNeedFarStub, bool Indirect, 470 intptr_t ACPV) const { 471 MachineRelocation MR = Indirect 472 ? MachineRelocation::getIndirectSymbol(MCE.getCurrentPCOffset(), Reloc, 473 const_cast<GlobalValue *>(GV), 474 ACPV, MayNeedFarStub) 475 : MachineRelocation::getGV(MCE.getCurrentPCOffset(), Reloc, 476 const_cast<GlobalValue *>(GV), ACPV, 477 MayNeedFarStub); 478 MCE.addRelocation(MR); 479} 480 481/// emitExternalSymbolAddress - Arrange for the address of an external symbol to 482/// be emitted to the current location in the function, and allow it to be PC 483/// relative. 484void ARMCodeEmitter:: 485emitExternalSymbolAddress(const char *ES, unsigned Reloc) const { 486 MCE.addRelocation(MachineRelocation::getExtSym(MCE.getCurrentPCOffset(), 487 Reloc, ES)); 488} 489 490/// emitConstPoolAddress - Arrange for the address of an constant pool 491/// to be emitted to the current location in the function, and allow it to be PC 492/// relative. 493void ARMCodeEmitter::emitConstPoolAddress(unsigned CPI, unsigned Reloc) const { 494 // Tell JIT emitter we'll resolve the address. 495 MCE.addRelocation(MachineRelocation::getConstPool(MCE.getCurrentPCOffset(), 496 Reloc, CPI, 0, true)); 497} 498 499/// emitJumpTableAddress - Arrange for the address of a jump table to 500/// be emitted to the current location in the function, and allow it to be PC 501/// relative. 502void ARMCodeEmitter:: 503emitJumpTableAddress(unsigned JTIndex, unsigned Reloc) const { 504 MCE.addRelocation(MachineRelocation::getJumpTable(MCE.getCurrentPCOffset(), 505 Reloc, JTIndex, 0, true)); 506} 507 508/// emitMachineBasicBlock - Emit the specified address basic block. 509void ARMCodeEmitter::emitMachineBasicBlock(MachineBasicBlock *BB, 510 unsigned Reloc, 511 intptr_t JTBase) const { 512 MCE.addRelocation(MachineRelocation::getBB(MCE.getCurrentPCOffset(), 513 Reloc, BB, JTBase)); 514} 515 516void ARMCodeEmitter::emitWordLE(unsigned Binary) { 517 DEBUG(errs() << " 0x"; 518 errs().write_hex(Binary) << "\n"); 519 MCE.emitWordLE(Binary); 520} 521 522void ARMCodeEmitter::emitDWordLE(uint64_t Binary) { 523 DEBUG(errs() << " 0x"; 524 errs().write_hex(Binary) << "\n"); 525 MCE.emitDWordLE(Binary); 526} 527 528void ARMCodeEmitter::emitInstruction(const MachineInstr &MI) { 529 DEBUG(errs() << "JIT: " << (void*)MCE.getCurrentPCValue() << ":\t" << MI); 530 531 MCE.processDebugLoc(MI.getDebugLoc(), true); 532 533 ++NumEmitted; // Keep track of the # of mi's emitted 534 switch (MI.getDesc().TSFlags & ARMII::FormMask) { 535 default: { 536 llvm_unreachable("Unhandled instruction encoding format!"); 537 } 538 case ARMII::MiscFrm: 539 if (MI.getOpcode() == ARM::LEApcrelJT) { 540 // Materialize jumptable address. 541 emitLEApcrelJTInstruction(MI); 542 break; 543 } 544 llvm_unreachable("Unhandled instruction encoding!"); 545 case ARMII::Pseudo: 546 emitPseudoInstruction(MI); 547 break; 548 case ARMII::DPFrm: 549 case ARMII::DPSoRegFrm: 550 emitDataProcessingInstruction(MI); 551 break; 552 case ARMII::LdFrm: 553 case ARMII::StFrm: 554 emitLoadStoreInstruction(MI); 555 break; 556 case ARMII::LdMiscFrm: 557 case ARMII::StMiscFrm: 558 emitMiscLoadStoreInstruction(MI); 559 break; 560 case ARMII::LdStMulFrm: 561 emitLoadStoreMultipleInstruction(MI); 562 break; 563 case ARMII::MulFrm: 564 emitMulFrmInstruction(MI); 565 break; 566 case ARMII::ExtFrm: 567 emitExtendInstruction(MI); 568 break; 569 case ARMII::ArithMiscFrm: 570 emitMiscArithInstruction(MI); 571 break; 572 case ARMII::SatFrm: 573 emitSaturateInstruction(MI); 574 break; 575 case ARMII::BrFrm: 576 emitBranchInstruction(MI); 577 break; 578 case ARMII::BrMiscFrm: 579 emitMiscBranchInstruction(MI); 580 break; 581 // VFP instructions. 582 case ARMII::VFPUnaryFrm: 583 case ARMII::VFPBinaryFrm: 584 emitVFPArithInstruction(MI); 585 break; 586 case ARMII::VFPConv1Frm: 587 case ARMII::VFPConv2Frm: 588 case ARMII::VFPConv3Frm: 589 case ARMII::VFPConv4Frm: 590 case ARMII::VFPConv5Frm: 591 emitVFPConversionInstruction(MI); 592 break; 593 case ARMII::VFPLdStFrm: 594 emitVFPLoadStoreInstruction(MI); 595 break; 596 case ARMII::VFPLdStMulFrm: 597 emitVFPLoadStoreMultipleInstruction(MI); 598 break; 599 600 // NEON instructions. 601 case ARMII::NGetLnFrm: 602 case ARMII::NSetLnFrm: 603 emitNEONLaneInstruction(MI); 604 break; 605 case ARMII::NDupFrm: 606 emitNEONDupInstruction(MI); 607 break; 608 case ARMII::N1RegModImmFrm: 609 emitNEON1RegModImmInstruction(MI); 610 break; 611 case ARMII::N2RegFrm: 612 emitNEON2RegInstruction(MI); 613 break; 614 case ARMII::N3RegFrm: 615 emitNEON3RegInstruction(MI); 616 break; 617 } 618 MCE.processDebugLoc(MI.getDebugLoc(), false); 619} 620 621void ARMCodeEmitter::emitConstPoolInstruction(const MachineInstr &MI) { 622 unsigned CPI = MI.getOperand(0).getImm(); // CP instruction index. 623 unsigned CPIndex = MI.getOperand(1).getIndex(); // Actual cp entry index. 624 const MachineConstantPoolEntry &MCPE = (*MCPEs)[CPIndex]; 625 626 // Remember the CONSTPOOL_ENTRY address for later relocation. 627 JTI->addConstantPoolEntryAddr(CPI, MCE.getCurrentPCValue()); 628 629 // Emit constpool island entry. In most cases, the actual values will be 630 // resolved and relocated after code emission. 631 if (MCPE.isMachineConstantPoolEntry()) { 632 ARMConstantPoolValue *ACPV = 633 static_cast<ARMConstantPoolValue*>(MCPE.Val.MachineCPVal); 634 635 DEBUG(errs() << " ** ARM constant pool #" << CPI << " @ " 636 << (void*)MCE.getCurrentPCValue() << " " << *ACPV << '\n'); 637 638 assert(ACPV->isGlobalValue() && "unsupported constant pool value"); 639 const GlobalValue *GV = cast<ARMConstantPoolConstant>(ACPV)->getGV(); 640 if (GV) { 641 Reloc::Model RelocM = TM.getRelocationModel(); 642 emitGlobalAddress(GV, ARM::reloc_arm_machine_cp_entry, 643 isa<Function>(GV), 644 Subtarget->GVIsIndirectSymbol(GV, RelocM), 645 (intptr_t)ACPV); 646 } else { 647 const char *Sym = cast<ARMConstantPoolSymbol>(ACPV)->getSymbol(); 648 emitExternalSymbolAddress(Sym, ARM::reloc_arm_absolute); 649 } 650 emitWordLE(0); 651 } else { 652 const Constant *CV = MCPE.Val.ConstVal; 653 654 DEBUG({ 655 errs() << " ** Constant pool #" << CPI << " @ " 656 << (void*)MCE.getCurrentPCValue() << " "; 657 if (const Function *F = dyn_cast<Function>(CV)) 658 errs() << F->getName(); 659 else 660 errs() << *CV; 661 errs() << '\n'; 662 }); 663 664 if (const GlobalValue *GV = dyn_cast<GlobalValue>(CV)) { 665 emitGlobalAddress(GV, ARM::reloc_arm_absolute, isa<Function>(GV), false); 666 emitWordLE(0); 667 } else if (const ConstantInt *CI = dyn_cast<ConstantInt>(CV)) { 668 uint32_t Val = uint32_t(*CI->getValue().getRawData()); 669 emitWordLE(Val); 670 } else if (const ConstantFP *CFP = dyn_cast<ConstantFP>(CV)) { 671 if (CFP->getType()->isFloatTy()) 672 emitWordLE(CFP->getValueAPF().bitcastToAPInt().getZExtValue()); 673 else if (CFP->getType()->isDoubleTy()) 674 emitDWordLE(CFP->getValueAPF().bitcastToAPInt().getZExtValue()); 675 else { 676 llvm_unreachable("Unable to handle this constantpool entry!"); 677 } 678 } else { 679 llvm_unreachable("Unable to handle this constantpool entry!"); 680 } 681 } 682} 683 684void ARMCodeEmitter::emitMOVi32immInstruction(const MachineInstr &MI) { 685 const MachineOperand &MO0 = MI.getOperand(0); 686 const MachineOperand &MO1 = MI.getOperand(1); 687 688 // Emit the 'movw' instruction. 689 unsigned Binary = 0x30 << 20; // mov: Insts{27-20} = 0b00110000 690 691 unsigned Lo16 = getMovi32Value(MI, MO1, ARM::reloc_arm_movw) & 0xFFFF; 692 693 // Set the conditional execution predicate. 694 Binary |= II->getPredicate(&MI) << ARMII::CondShift; 695 696 // Encode Rd. 697 Binary |= getMachineOpValue(MI, MO0) << ARMII::RegRdShift; 698 699 // Encode imm16 as imm4:imm12 700 Binary |= Lo16 & 0xFFF; // Insts{11-0} = imm12 701 Binary |= ((Lo16 >> 12) & 0xF) << 16; // Insts{19-16} = imm4 702 emitWordLE(Binary); 703 704 unsigned Hi16 = getMovi32Value(MI, MO1, ARM::reloc_arm_movt) >> 16; 705 // Emit the 'movt' instruction. 706 Binary = 0x34 << 20; // movt: Insts{27-20} = 0b00110100 707 708 // Set the conditional execution predicate. 709 Binary |= II->getPredicate(&MI) << ARMII::CondShift; 710 711 // Encode Rd. 712 Binary |= getMachineOpValue(MI, MO0) << ARMII::RegRdShift; 713 714 // Encode imm16 as imm4:imm1, same as movw above. 715 Binary |= Hi16 & 0xFFF; 716 Binary |= ((Hi16 >> 12) & 0xF) << 16; 717 emitWordLE(Binary); 718} 719 720void ARMCodeEmitter::emitMOVi2piecesInstruction(const MachineInstr &MI) { 721 const MachineOperand &MO0 = MI.getOperand(0); 722 const MachineOperand &MO1 = MI.getOperand(1); 723 assert(MO1.isImm() && ARM_AM::isSOImmTwoPartVal(MO1.getImm()) && 724 "Not a valid so_imm value!"); 725 unsigned V1 = ARM_AM::getSOImmTwoPartFirst(MO1.getImm()); 726 unsigned V2 = ARM_AM::getSOImmTwoPartSecond(MO1.getImm()); 727 728 // Emit the 'mov' instruction. 729 unsigned Binary = 0xd << 21; // mov: Insts{24-21} = 0b1101 730 731 // Set the conditional execution predicate. 732 Binary |= II->getPredicate(&MI) << ARMII::CondShift; 733 734 // Encode Rd. 735 Binary |= getMachineOpValue(MI, MO0) << ARMII::RegRdShift; 736 737 // Encode so_imm. 738 // Set bit I(25) to identify this is the immediate form of <shifter_op> 739 Binary |= 1 << ARMII::I_BitShift; 740 Binary |= getMachineSoImmOpValue(V1); 741 emitWordLE(Binary); 742 743 // Now the 'orr' instruction. 744 Binary = 0xc << 21; // orr: Insts{24-21} = 0b1100 745 746 // Set the conditional execution predicate. 747 Binary |= II->getPredicate(&MI) << ARMII::CondShift; 748 749 // Encode Rd. 750 Binary |= getMachineOpValue(MI, MO0) << ARMII::RegRdShift; 751 752 // Encode Rn. 753 Binary |= getMachineOpValue(MI, MO0) << ARMII::RegRnShift; 754 755 // Encode so_imm. 756 // Set bit I(25) to identify this is the immediate form of <shifter_op> 757 Binary |= 1 << ARMII::I_BitShift; 758 Binary |= getMachineSoImmOpValue(V2); 759 emitWordLE(Binary); 760} 761 762void ARMCodeEmitter::emitLEApcrelJTInstruction(const MachineInstr &MI) { 763 // It's basically add r, pc, (LJTI - $+8) 764 765 const MCInstrDesc &MCID = MI.getDesc(); 766 767 // Emit the 'add' instruction. 768 unsigned Binary = 0x4 << 21; // add: Insts{24-21} = 0b0100 769 770 // Set the conditional execution predicate 771 Binary |= II->getPredicate(&MI) << ARMII::CondShift; 772 773 // Encode S bit if MI modifies CPSR. 774 Binary |= getAddrModeSBit(MI, MCID); 775 776 // Encode Rd. 777 Binary |= getMachineOpValue(MI, 0) << ARMII::RegRdShift; 778 779 // Encode Rn which is PC. 780 Binary |= II->getRegisterInfo().getEncodingValue(ARM::PC) << ARMII::RegRnShift; 781 782 // Encode the displacement. 783 Binary |= 1 << ARMII::I_BitShift; 784 emitJumpTableAddress(MI.getOperand(1).getIndex(), ARM::reloc_arm_jt_base); 785 786 emitWordLE(Binary); 787} 788 789void ARMCodeEmitter::emitPseudoMoveInstruction(const MachineInstr &MI) { 790 unsigned Opcode = MI.getDesc().Opcode; 791 792 // Part of binary is determined by TableGn. 793 unsigned Binary = getBinaryCodeForInstr(MI); 794 795 // Set the conditional execution predicate 796 Binary |= II->getPredicate(&MI) << ARMII::CondShift; 797 798 // Encode S bit if MI modifies CPSR. 799 if (Opcode == ARM::MOVsrl_flag || Opcode == ARM::MOVsra_flag) 800 Binary |= 1 << ARMII::S_BitShift; 801 802 // Encode register def if there is one. 803 Binary |= getMachineOpValue(MI, 0) << ARMII::RegRdShift; 804 805 // Encode the shift operation. 806 switch (Opcode) { 807 default: break; 808 case ARM::RRX: 809 // rrx 810 Binary |= 0x6 << 4; 811 break; 812 case ARM::MOVsrl_flag: 813 // lsr #1 814 Binary |= (0x2 << 4) | (1 << 7); 815 break; 816 case ARM::MOVsra_flag: 817 // asr #1 818 Binary |= (0x4 << 4) | (1 << 7); 819 break; 820 } 821 822 // Encode register Rm. 823 Binary |= getMachineOpValue(MI, 1); 824 825 emitWordLE(Binary); 826} 827 828void ARMCodeEmitter::addPCLabel(unsigned LabelID) { 829 DEBUG(errs() << " ** LPC" << LabelID << " @ " 830 << (void*)MCE.getCurrentPCValue() << '\n'); 831 JTI->addPCLabelAddr(LabelID, MCE.getCurrentPCValue()); 832} 833 834void ARMCodeEmitter::emitPseudoInstruction(const MachineInstr &MI) { 835 unsigned Opcode = MI.getDesc().Opcode; 836 switch (Opcode) { 837 default: 838 llvm_unreachable("ARMCodeEmitter::emitPseudoInstruction"); 839 case ARM::BX_CALL: 840 case ARM::BMOVPCRX_CALL: { 841 // First emit mov lr, pc 842 unsigned Binary = 0x01a0e00f; 843 Binary |= II->getPredicate(&MI) << ARMII::CondShift; 844 emitWordLE(Binary); 845 846 // and then emit the branch. 847 emitMiscBranchInstruction(MI); 848 break; 849 } 850 case TargetOpcode::INLINEASM: { 851 // We allow inline assembler nodes with empty bodies - they can 852 // implicitly define registers, which is ok for JIT. 853 if (MI.getOperand(0).getSymbolName()[0]) { 854 report_fatal_error("JIT does not support inline asm!"); 855 } 856 break; 857 } 858 case TargetOpcode::CFI_INSTRUCTION: 859 break; 860 case TargetOpcode::EH_LABEL: 861 MCE.emitLabel(MI.getOperand(0).getMCSymbol()); 862 break; 863 case TargetOpcode::IMPLICIT_DEF: 864 case TargetOpcode::KILL: 865 // Do nothing. 866 break; 867 case ARM::CONSTPOOL_ENTRY: 868 emitConstPoolInstruction(MI); 869 break; 870 case ARM::PICADD: { 871 // Remember of the address of the PC label for relocation later. 872 addPCLabel(MI.getOperand(2).getImm()); 873 // PICADD is just an add instruction that implicitly read pc. 874 emitDataProcessingInstruction(MI, 0, ARM::PC); 875 break; 876 } 877 case ARM::PICLDR: 878 case ARM::PICLDRB: 879 case ARM::PICSTR: 880 case ARM::PICSTRB: { 881 // Remember of the address of the PC label for relocation later. 882 addPCLabel(MI.getOperand(2).getImm()); 883 // These are just load / store instructions that implicitly read pc. 884 emitLoadStoreInstruction(MI, 0, ARM::PC); 885 break; 886 } 887 case ARM::PICLDRH: 888 case ARM::PICLDRSH: 889 case ARM::PICLDRSB: 890 case ARM::PICSTRH: { 891 // Remember of the address of the PC label for relocation later. 892 addPCLabel(MI.getOperand(2).getImm()); 893 // These are just load / store instructions that implicitly read pc. 894 emitMiscLoadStoreInstruction(MI, ARM::PC); 895 break; 896 } 897 898 case ARM::MOVi32imm: 899 // Two instructions to materialize a constant. 900 if (Subtarget->hasV6T2Ops()) 901 emitMOVi32immInstruction(MI); 902 else 903 emitMOVi2piecesInstruction(MI); 904 break; 905 906 case ARM::LEApcrelJT: 907 // Materialize jumptable address. 908 emitLEApcrelJTInstruction(MI); 909 break; 910 case ARM::RRX: 911 case ARM::MOVsrl_flag: 912 case ARM::MOVsra_flag: 913 emitPseudoMoveInstruction(MI); 914 break; 915 } 916} 917 918unsigned ARMCodeEmitter::getMachineSoRegOpValue(const MachineInstr &MI, 919 const MCInstrDesc &MCID, 920 const MachineOperand &MO, 921 unsigned OpIdx) { 922 unsigned Binary = getMachineOpValue(MI, MO); 923 924 const MachineOperand &MO1 = MI.getOperand(OpIdx + 1); 925 const MachineOperand &MO2 = MI.getOperand(OpIdx + 2); 926 ARM_AM::ShiftOpc SOpc = ARM_AM::getSORegShOp(MO2.getImm()); 927 928 // Encode the shift opcode. 929 unsigned SBits = 0; 930 unsigned Rs = MO1.getReg(); 931 if (Rs) { 932 // Set shift operand (bit[7:4]). 933 // LSL - 0001 934 // LSR - 0011 935 // ASR - 0101 936 // ROR - 0111 937 // RRX - 0110 and bit[11:8] clear. 938 switch (SOpc) { 939 default: llvm_unreachable("Unknown shift opc!"); 940 case ARM_AM::lsl: SBits = 0x1; break; 941 case ARM_AM::lsr: SBits = 0x3; break; 942 case ARM_AM::asr: SBits = 0x5; break; 943 case ARM_AM::ror: SBits = 0x7; break; 944 case ARM_AM::rrx: SBits = 0x6; break; 945 } 946 } else { 947 // Set shift operand (bit[6:4]). 948 // LSL - 000 949 // LSR - 010 950 // ASR - 100 951 // ROR - 110 952 switch (SOpc) { 953 default: llvm_unreachable("Unknown shift opc!"); 954 case ARM_AM::lsl: SBits = 0x0; break; 955 case ARM_AM::lsr: SBits = 0x2; break; 956 case ARM_AM::asr: SBits = 0x4; break; 957 case ARM_AM::ror: SBits = 0x6; break; 958 } 959 } 960 Binary |= SBits << 4; 961 if (SOpc == ARM_AM::rrx) 962 return Binary; 963 964 // Encode the shift operation Rs or shift_imm (except rrx). 965 if (Rs) { 966 // Encode Rs bit[11:8]. 967 assert(ARM_AM::getSORegOffset(MO2.getImm()) == 0); 968 return Binary | (II->getRegisterInfo().getEncodingValue(Rs) << ARMII::RegRsShift); 969 } 970 971 // Encode shift_imm bit[11:7]. 972 return Binary | ARM_AM::getSORegOffset(MO2.getImm()) << 7; 973} 974 975unsigned ARMCodeEmitter::getMachineSoImmOpValue(unsigned SoImm) { 976 int SoImmVal = ARM_AM::getSOImmVal(SoImm); 977 assert(SoImmVal != -1 && "Not a valid so_imm value!"); 978 979 // Encode rotate_imm. 980 unsigned Binary = (ARM_AM::getSOImmValRot((unsigned)SoImmVal) >> 1) 981 << ARMII::SoRotImmShift; 982 983 // Encode immed_8. 984 Binary |= ARM_AM::getSOImmValImm((unsigned)SoImmVal); 985 return Binary; 986} 987 988unsigned ARMCodeEmitter::getAddrModeSBit(const MachineInstr &MI, 989 const MCInstrDesc &MCID) const { 990 for (unsigned i = MI.getNumOperands(), e = MCID.getNumOperands(); i >= e;--i){ 991 const MachineOperand &MO = MI.getOperand(i-1); 992 if (MO.isReg() && MO.isDef() && MO.getReg() == ARM::CPSR) 993 return 1 << ARMII::S_BitShift; 994 } 995 return 0; 996} 997 998void ARMCodeEmitter::emitDataProcessingInstruction(const MachineInstr &MI, 999 unsigned ImplicitRd, 1000 unsigned ImplicitRn) { 1001 const MCInstrDesc &MCID = MI.getDesc(); 1002 1003 // Part of binary is determined by TableGn. 1004 unsigned Binary = getBinaryCodeForInstr(MI); 1005 1006 // Set the conditional execution predicate 1007 Binary |= II->getPredicate(&MI) << ARMII::CondShift; 1008 1009 // Encode S bit if MI modifies CPSR. 1010 Binary |= getAddrModeSBit(MI, MCID); 1011 1012 // Encode register def if there is one. 1013 unsigned NumDefs = MCID.getNumDefs(); 1014 unsigned OpIdx = 0; 1015 if (NumDefs) 1016 Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRdShift; 1017 else if (ImplicitRd) 1018 // Special handling for implicit use (e.g. PC). 1019 Binary |= (II->getRegisterInfo().getEncodingValue(ImplicitRd) << ARMII::RegRdShift); 1020 1021 if (MCID.Opcode == ARM::MOVi16) { 1022 // Get immediate from MI. 1023 unsigned Lo16 = getMovi32Value(MI, MI.getOperand(OpIdx), 1024 ARM::reloc_arm_movw); 1025 // Encode imm which is the same as in emitMOVi32immInstruction(). 1026 Binary |= Lo16 & 0xFFF; 1027 Binary |= ((Lo16 >> 12) & 0xF) << 16; 1028 emitWordLE(Binary); 1029 return; 1030 } else if(MCID.Opcode == ARM::MOVTi16) { 1031 unsigned Hi16 = (getMovi32Value(MI, MI.getOperand(OpIdx), 1032 ARM::reloc_arm_movt) >> 16); 1033 Binary |= Hi16 & 0xFFF; 1034 Binary |= ((Hi16 >> 12) & 0xF) << 16; 1035 emitWordLE(Binary); 1036 return; 1037 } else if ((MCID.Opcode == ARM::BFC) || (MCID.Opcode == ARM::BFI)) { 1038 uint32_t v = ~MI.getOperand(2).getImm(); 1039 int32_t lsb = countTrailingZeros(v); 1040 int32_t msb = (32 - countLeadingZeros(v)) - 1; 1041 // Instr{20-16} = msb, Instr{11-7} = lsb 1042 Binary |= (msb & 0x1F) << 16; 1043 Binary |= (lsb & 0x1F) << 7; 1044 emitWordLE(Binary); 1045 return; 1046 } else if ((MCID.Opcode == ARM::UBFX) || (MCID.Opcode == ARM::SBFX)) { 1047 // Encode Rn in Instr{0-3} 1048 Binary |= getMachineOpValue(MI, OpIdx++); 1049 1050 uint32_t lsb = MI.getOperand(OpIdx++).getImm(); 1051 uint32_t widthm1 = MI.getOperand(OpIdx++).getImm() - 1; 1052 1053 // Instr{20-16} = widthm1, Instr{11-7} = lsb 1054 Binary |= (widthm1 & 0x1F) << 16; 1055 Binary |= (lsb & 0x1F) << 7; 1056 emitWordLE(Binary); 1057 return; 1058 } 1059 1060 // If this is a two-address operand, skip it. e.g. MOVCCr operand 1. 1061 if (MCID.getOperandConstraint(OpIdx, MCOI::TIED_TO) != -1) 1062 ++OpIdx; 1063 1064 // Encode first non-shifter register operand if there is one. 1065 bool isUnary = MCID.TSFlags & ARMII::UnaryDP; 1066 if (!isUnary) { 1067 if (ImplicitRn) 1068 // Special handling for implicit use (e.g. PC). 1069 Binary |= (II->getRegisterInfo().getEncodingValue(ImplicitRn) << ARMII::RegRnShift); 1070 else { 1071 Binary |= getMachineOpValue(MI, OpIdx) << ARMII::RegRnShift; 1072 ++OpIdx; 1073 } 1074 } 1075 1076 // Encode shifter operand. 1077 const MachineOperand &MO = MI.getOperand(OpIdx); 1078 if ((MCID.TSFlags & ARMII::FormMask) == ARMII::DPSoRegFrm) { 1079 // Encode SoReg. 1080 emitWordLE(Binary | getMachineSoRegOpValue(MI, MCID, MO, OpIdx)); 1081 return; 1082 } 1083 1084 if (MO.isReg()) { 1085 // Encode register Rm. 1086 emitWordLE(Binary | II->getRegisterInfo().getEncodingValue(MO.getReg())); 1087 return; 1088 } 1089 1090 // Encode so_imm. 1091 Binary |= getMachineSoImmOpValue((unsigned)MO.getImm()); 1092 1093 emitWordLE(Binary); 1094} 1095 1096void ARMCodeEmitter::emitLoadStoreInstruction(const MachineInstr &MI, 1097 unsigned ImplicitRd, 1098 unsigned ImplicitRn) { 1099 const MCInstrDesc &MCID = MI.getDesc(); 1100 unsigned Form = MCID.TSFlags & ARMII::FormMask; 1101 bool IsPrePost = (MCID.TSFlags & ARMII::IndexModeMask) != 0; 1102 1103 // Part of binary is determined by TableGn. 1104 unsigned Binary = getBinaryCodeForInstr(MI); 1105 1106 // If this is an LDRi12, STRi12 or LDRcp, nothing more needs be done. 1107 if (MI.getOpcode() == ARM::LDRi12 || MI.getOpcode() == ARM::LDRcp || 1108 MI.getOpcode() == ARM::STRi12) { 1109 emitWordLE(Binary); 1110 return; 1111 } 1112 1113 // Set the conditional execution predicate 1114 Binary |= II->getPredicate(&MI) << ARMII::CondShift; 1115 1116 unsigned OpIdx = 0; 1117 1118 // Operand 0 of a pre- and post-indexed store is the address base 1119 // writeback. Skip it. 1120 bool Skipped = false; 1121 if (IsPrePost && Form == ARMII::StFrm) { 1122 ++OpIdx; 1123 Skipped = true; 1124 } 1125 1126 // Set first operand 1127 if (ImplicitRd) 1128 // Special handling for implicit use (e.g. PC). 1129 Binary |= (II->getRegisterInfo().getEncodingValue(ImplicitRd) << ARMII::RegRdShift); 1130 else 1131 Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRdShift; 1132 1133 // Set second operand 1134 if (ImplicitRn) 1135 // Special handling for implicit use (e.g. PC). 1136 Binary |= (II->getRegisterInfo().getEncodingValue(ImplicitRn) << ARMII::RegRnShift); 1137 else 1138 Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRnShift; 1139 1140 // If this is a two-address operand, skip it. e.g. LDR_PRE. 1141 if (!Skipped && MCID.getOperandConstraint(OpIdx, MCOI::TIED_TO) != -1) 1142 ++OpIdx; 1143 1144 const MachineOperand &MO2 = MI.getOperand(OpIdx); 1145 unsigned AM2Opc = (ImplicitRn == ARM::PC) 1146 ? 0 : MI.getOperand(OpIdx+1).getImm(); 1147 1148 // Set bit U(23) according to sign of immed value (positive or negative). 1149 Binary |= ((ARM_AM::getAM2Op(AM2Opc) == ARM_AM::add ? 1 : 0) << 1150 ARMII::U_BitShift); 1151 if (!MO2.getReg()) { // is immediate 1152 if (ARM_AM::getAM2Offset(AM2Opc)) 1153 // Set the value of offset_12 field 1154 Binary |= ARM_AM::getAM2Offset(AM2Opc); 1155 emitWordLE(Binary); 1156 return; 1157 } 1158 1159 // Set bit I(25), because this is not in immediate encoding. 1160 Binary |= 1 << ARMII::I_BitShift; 1161 assert(TargetRegisterInfo::isPhysicalRegister(MO2.getReg())); 1162 // Set bit[3:0] to the corresponding Rm register 1163 Binary |= II->getRegisterInfo().getEncodingValue(MO2.getReg()); 1164 1165 // If this instr is in scaled register offset/index instruction, set 1166 // shift_immed(bit[11:7]) and shift(bit[6:5]) fields. 1167 if (unsigned ShImm = ARM_AM::getAM2Offset(AM2Opc)) { 1168 Binary |= getShiftOp(AM2Opc) << ARMII::ShiftImmShift; // shift 1169 Binary |= ShImm << ARMII::ShiftShift; // shift_immed 1170 } 1171 1172 emitWordLE(Binary); 1173} 1174 1175void ARMCodeEmitter::emitMiscLoadStoreInstruction(const MachineInstr &MI, 1176 unsigned ImplicitRn) { 1177 const MCInstrDesc &MCID = MI.getDesc(); 1178 unsigned Form = MCID.TSFlags & ARMII::FormMask; 1179 bool IsPrePost = (MCID.TSFlags & ARMII::IndexModeMask) != 0; 1180 1181 // Part of binary is determined by TableGn. 1182 unsigned Binary = getBinaryCodeForInstr(MI); 1183 1184 // Set the conditional execution predicate 1185 Binary |= II->getPredicate(&MI) << ARMII::CondShift; 1186 1187 unsigned OpIdx = 0; 1188 1189 // Operand 0 of a pre- and post-indexed store is the address base 1190 // writeback. Skip it. 1191 bool Skipped = false; 1192 if (IsPrePost && Form == ARMII::StMiscFrm) { 1193 ++OpIdx; 1194 Skipped = true; 1195 } 1196 1197 // Set first operand 1198 Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRdShift; 1199 1200 // Skip LDRD and STRD's second operand. 1201 if (MCID.Opcode == ARM::LDRD || MCID.Opcode == ARM::STRD) 1202 ++OpIdx; 1203 1204 // Set second operand 1205 if (ImplicitRn) 1206 // Special handling for implicit use (e.g. PC). 1207 Binary |= (II->getRegisterInfo().getEncodingValue(ImplicitRn) << ARMII::RegRnShift); 1208 else 1209 Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRnShift; 1210 1211 // If this is a two-address operand, skip it. e.g. LDRH_POST. 1212 if (!Skipped && MCID.getOperandConstraint(OpIdx, MCOI::TIED_TO) != -1) 1213 ++OpIdx; 1214 1215 const MachineOperand &MO2 = MI.getOperand(OpIdx); 1216 unsigned AM3Opc = (ImplicitRn == ARM::PC) 1217 ? 0 : MI.getOperand(OpIdx+1).getImm(); 1218 1219 // Set bit U(23) according to sign of immed value (positive or negative) 1220 Binary |= ((ARM_AM::getAM3Op(AM3Opc) == ARM_AM::add ? 1 : 0) << 1221 ARMII::U_BitShift); 1222 1223 // If this instr is in register offset/index encoding, set bit[3:0] 1224 // to the corresponding Rm register. 1225 if (MO2.getReg()) { 1226 Binary |= II->getRegisterInfo().getEncodingValue(MO2.getReg()); 1227 emitWordLE(Binary); 1228 return; 1229 } 1230 1231 // This instr is in immediate offset/index encoding, set bit 22 to 1. 1232 Binary |= 1 << ARMII::AM3_I_BitShift; 1233 if (unsigned ImmOffs = ARM_AM::getAM3Offset(AM3Opc)) { 1234 // Set operands 1235 Binary |= (ImmOffs >> 4) << ARMII::ImmHiShift; // immedH 1236 Binary |= (ImmOffs & 0xF); // immedL 1237 } 1238 1239 emitWordLE(Binary); 1240} 1241 1242static unsigned getAddrModeUPBits(unsigned Mode) { 1243 unsigned Binary = 0; 1244 1245 // Set addressing mode by modifying bits U(23) and P(24) 1246 // IA - Increment after - bit U = 1 and bit P = 0 1247 // IB - Increment before - bit U = 1 and bit P = 1 1248 // DA - Decrement after - bit U = 0 and bit P = 0 1249 // DB - Decrement before - bit U = 0 and bit P = 1 1250 switch (Mode) { 1251 default: llvm_unreachable("Unknown addressing sub-mode!"); 1252 case ARM_AM::da: break; 1253 case ARM_AM::db: Binary |= 0x1 << ARMII::P_BitShift; break; 1254 case ARM_AM::ia: Binary |= 0x1 << ARMII::U_BitShift; break; 1255 case ARM_AM::ib: Binary |= 0x3 << ARMII::U_BitShift; break; 1256 } 1257 1258 return Binary; 1259} 1260 1261void ARMCodeEmitter::emitLoadStoreMultipleInstruction(const MachineInstr &MI) { 1262 const MCInstrDesc &MCID = MI.getDesc(); 1263 bool IsUpdating = (MCID.TSFlags & ARMII::IndexModeMask) != 0; 1264 1265 // Part of binary is determined by TableGn. 1266 unsigned Binary = getBinaryCodeForInstr(MI); 1267 1268 // Set the conditional execution predicate 1269 Binary |= II->getPredicate(&MI) << ARMII::CondShift; 1270 1271 // Skip operand 0 of an instruction with base register update. 1272 unsigned OpIdx = 0; 1273 if (IsUpdating) 1274 ++OpIdx; 1275 1276 // Set base address operand 1277 Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRnShift; 1278 1279 // Set addressing mode by modifying bits U(23) and P(24) 1280 ARM_AM::AMSubMode Mode = ARM_AM::getLoadStoreMultipleSubMode(MI.getOpcode()); 1281 Binary |= getAddrModeUPBits(ARM_AM::getAM4SubMode(Mode)); 1282 1283 // Set bit W(21) 1284 if (IsUpdating) 1285 Binary |= 0x1 << ARMII::W_BitShift; 1286 1287 // Set registers 1288 for (unsigned i = OpIdx+2, e = MI.getNumOperands(); i != e; ++i) { 1289 const MachineOperand &MO = MI.getOperand(i); 1290 if (!MO.isReg() || MO.isImplicit()) 1291 break; 1292 unsigned RegNum = II->getRegisterInfo().getEncodingValue(MO.getReg()); 1293 assert(TargetRegisterInfo::isPhysicalRegister(MO.getReg()) && 1294 RegNum < 16); 1295 Binary |= 0x1 << RegNum; 1296 } 1297 1298 emitWordLE(Binary); 1299} 1300 1301void ARMCodeEmitter::emitMulFrmInstruction(const MachineInstr &MI) { 1302 const MCInstrDesc &MCID = MI.getDesc(); 1303 1304 // Part of binary is determined by TableGn. 1305 unsigned Binary = getBinaryCodeForInstr(MI); 1306 1307 // Set the conditional execution predicate 1308 Binary |= II->getPredicate(&MI) << ARMII::CondShift; 1309 1310 // Encode S bit if MI modifies CPSR. 1311 Binary |= getAddrModeSBit(MI, MCID); 1312 1313 // 32x32->64bit operations have two destination registers. The number 1314 // of register definitions will tell us if that's what we're dealing with. 1315 unsigned OpIdx = 0; 1316 if (MCID.getNumDefs() == 2) 1317 Binary |= getMachineOpValue (MI, OpIdx++) << ARMII::RegRdLoShift; 1318 1319 // Encode Rd 1320 Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRdHiShift; 1321 1322 // Encode Rm 1323 Binary |= getMachineOpValue(MI, OpIdx++); 1324 1325 // Encode Rs 1326 Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRsShift; 1327 1328 // Many multiple instructions (e.g. MLA) have three src operands. Encode 1329 // it as Rn (for multiply, that's in the same offset as RdLo. 1330 if (MCID.getNumOperands() > OpIdx && 1331 !MCID.OpInfo[OpIdx].isPredicate() && 1332 !MCID.OpInfo[OpIdx].isOptionalDef()) 1333 Binary |= getMachineOpValue(MI, OpIdx) << ARMII::RegRdLoShift; 1334 1335 emitWordLE(Binary); 1336} 1337 1338void ARMCodeEmitter::emitExtendInstruction(const MachineInstr &MI) { 1339 const MCInstrDesc &MCID = MI.getDesc(); 1340 1341 // Part of binary is determined by TableGn. 1342 unsigned Binary = getBinaryCodeForInstr(MI); 1343 1344 // Set the conditional execution predicate 1345 Binary |= II->getPredicate(&MI) << ARMII::CondShift; 1346 1347 unsigned OpIdx = 0; 1348 1349 // Encode Rd 1350 Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRdShift; 1351 1352 const MachineOperand &MO1 = MI.getOperand(OpIdx++); 1353 const MachineOperand &MO2 = MI.getOperand(OpIdx); 1354 if (MO2.isReg()) { 1355 // Two register operand form. 1356 // Encode Rn. 1357 Binary |= getMachineOpValue(MI, MO1) << ARMII::RegRnShift; 1358 1359 // Encode Rm. 1360 Binary |= getMachineOpValue(MI, MO2); 1361 ++OpIdx; 1362 } else { 1363 Binary |= getMachineOpValue(MI, MO1); 1364 } 1365 1366 // Encode rot imm (0, 8, 16, or 24) if it has a rotate immediate operand. 1367 if (MI.getOperand(OpIdx).isImm() && 1368 !MCID.OpInfo[OpIdx].isPredicate() && 1369 !MCID.OpInfo[OpIdx].isOptionalDef()) 1370 Binary |= (getMachineOpValue(MI, OpIdx) / 8) << ARMII::ExtRotImmShift; 1371 1372 emitWordLE(Binary); 1373} 1374 1375void ARMCodeEmitter::emitMiscArithInstruction(const MachineInstr &MI) { 1376 const MCInstrDesc &MCID = MI.getDesc(); 1377 1378 // Part of binary is determined by TableGn. 1379 unsigned Binary = getBinaryCodeForInstr(MI); 1380 1381 // Set the conditional execution predicate 1382 Binary |= II->getPredicate(&MI) << ARMII::CondShift; 1383 1384 // PKH instructions are finished at this point 1385 if (MCID.Opcode == ARM::PKHBT || MCID.Opcode == ARM::PKHTB) { 1386 emitWordLE(Binary); 1387 return; 1388 } 1389 1390 unsigned OpIdx = 0; 1391 1392 // Encode Rd 1393 Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRdShift; 1394 1395 const MachineOperand &MO = MI.getOperand(OpIdx++); 1396 if (OpIdx == MCID.getNumOperands() || 1397 MCID.OpInfo[OpIdx].isPredicate() || 1398 MCID.OpInfo[OpIdx].isOptionalDef()) { 1399 // Encode Rm and it's done. 1400 Binary |= getMachineOpValue(MI, MO); 1401 emitWordLE(Binary); 1402 return; 1403 } 1404 1405 // Encode Rn. 1406 Binary |= getMachineOpValue(MI, MO) << ARMII::RegRnShift; 1407 1408 // Encode Rm. 1409 Binary |= getMachineOpValue(MI, OpIdx++); 1410 1411 // Encode shift_imm. 1412 unsigned ShiftAmt = MI.getOperand(OpIdx).getImm(); 1413 if (MCID.Opcode == ARM::PKHTB) { 1414 assert(ShiftAmt != 0 && "PKHTB shift_imm is 0!"); 1415 if (ShiftAmt == 32) 1416 ShiftAmt = 0; 1417 } 1418 assert(ShiftAmt < 32 && "shift_imm range is 0 to 31!"); 1419 Binary |= ShiftAmt << ARMII::ShiftShift; 1420 1421 emitWordLE(Binary); 1422} 1423 1424void ARMCodeEmitter::emitSaturateInstruction(const MachineInstr &MI) { 1425 const MCInstrDesc &MCID = MI.getDesc(); 1426 1427 // Part of binary is determined by TableGen. 1428 unsigned Binary = getBinaryCodeForInstr(MI); 1429 1430 // Set the conditional execution predicate 1431 Binary |= II->getPredicate(&MI) << ARMII::CondShift; 1432 1433 // Encode Rd 1434 Binary |= getMachineOpValue(MI, 0) << ARMII::RegRdShift; 1435 1436 // Encode saturate bit position. 1437 unsigned Pos = MI.getOperand(1).getImm(); 1438 if (MCID.Opcode == ARM::SSAT || MCID.Opcode == ARM::SSAT16) 1439 Pos -= 1; 1440 assert((Pos < 16 || (Pos < 32 && 1441 MCID.Opcode != ARM::SSAT16 && 1442 MCID.Opcode != ARM::USAT16)) && 1443 "saturate bit position out of range"); 1444 Binary |= Pos << 16; 1445 1446 // Encode Rm 1447 Binary |= getMachineOpValue(MI, 2); 1448 1449 // Encode shift_imm. 1450 if (MCID.getNumOperands() == 4) { 1451 unsigned ShiftOp = MI.getOperand(3).getImm(); 1452 ARM_AM::ShiftOpc Opc = ARM_AM::getSORegShOp(ShiftOp); 1453 if (Opc == ARM_AM::asr) 1454 Binary |= (1 << 6); 1455 unsigned ShiftAmt = MI.getOperand(3).getImm(); 1456 if (ShiftAmt == 32 && Opc == ARM_AM::asr) 1457 ShiftAmt = 0; 1458 assert(ShiftAmt < 32 && "shift_imm range is 0 to 31!"); 1459 Binary |= ShiftAmt << ARMII::ShiftShift; 1460 } 1461 1462 emitWordLE(Binary); 1463} 1464 1465void ARMCodeEmitter::emitBranchInstruction(const MachineInstr &MI) { 1466 const MCInstrDesc &MCID = MI.getDesc(); 1467 1468 if (MCID.Opcode == ARM::TPsoft) { 1469 llvm_unreachable("ARM::TPsoft FIXME"); // FIXME 1470 } 1471 1472 // Part of binary is determined by TableGn. 1473 unsigned Binary = getBinaryCodeForInstr(MI); 1474 1475 // Set the conditional execution predicate 1476 Binary |= II->getPredicate(&MI) << ARMII::CondShift; 1477 1478 // Set signed_immed_24 field 1479 Binary |= getMachineOpValue(MI, 0); 1480 1481 emitWordLE(Binary); 1482} 1483 1484void ARMCodeEmitter::emitInlineJumpTable(unsigned JTIndex) { 1485 // Remember the base address of the inline jump table. 1486 uintptr_t JTBase = MCE.getCurrentPCValue(); 1487 JTI->addJumpTableBaseAddr(JTIndex, JTBase); 1488 DEBUG(errs() << " ** Jump Table #" << JTIndex << " @ " << (void*)JTBase 1489 << '\n'); 1490 1491 // Now emit the jump table entries. 1492 const std::vector<MachineBasicBlock*> &MBBs = (*MJTEs)[JTIndex].MBBs; 1493 for (unsigned i = 0, e = MBBs.size(); i != e; ++i) { 1494 if (IsPIC) 1495 // DestBB address - JT base. 1496 emitMachineBasicBlock(MBBs[i], ARM::reloc_arm_pic_jt, JTBase); 1497 else 1498 // Absolute DestBB address. 1499 emitMachineBasicBlock(MBBs[i], ARM::reloc_arm_absolute); 1500 emitWordLE(0); 1501 } 1502} 1503 1504void ARMCodeEmitter::emitMiscBranchInstruction(const MachineInstr &MI) { 1505 const MCInstrDesc &MCID = MI.getDesc(); 1506 1507 // Handle jump tables. 1508 if (MCID.Opcode == ARM::BR_JTr || MCID.Opcode == ARM::BR_JTadd) { 1509 // First emit a ldr pc, [] instruction. 1510 emitDataProcessingInstruction(MI, ARM::PC); 1511 1512 // Then emit the inline jump table. 1513 unsigned JTIndex = 1514 (MCID.Opcode == ARM::BR_JTr) 1515 ? MI.getOperand(1).getIndex() : MI.getOperand(2).getIndex(); 1516 emitInlineJumpTable(JTIndex); 1517 return; 1518 } else if (MCID.Opcode == ARM::BR_JTm) { 1519 // First emit a ldr pc, [] instruction. 1520 emitLoadStoreInstruction(MI, ARM::PC); 1521 1522 // Then emit the inline jump table. 1523 emitInlineJumpTable(MI.getOperand(3).getIndex()); 1524 return; 1525 } 1526 1527 // Part of binary is determined by TableGn. 1528 unsigned Binary = getBinaryCodeForInstr(MI); 1529 1530 // Set the conditional execution predicate 1531 Binary |= II->getPredicate(&MI) << ARMII::CondShift; 1532 1533 if (MCID.Opcode == ARM::BX_RET || MCID.Opcode == ARM::MOVPCLR) 1534 // The return register is LR. 1535 Binary |= II->getRegisterInfo().getEncodingValue(ARM::LR); 1536 else 1537 // otherwise, set the return register 1538 Binary |= getMachineOpValue(MI, 0); 1539 1540 emitWordLE(Binary); 1541} 1542 1543unsigned ARMCodeEmitter::encodeVFPRd(const MachineInstr &MI, 1544 unsigned OpIdx) const { 1545 unsigned RegD = MI.getOperand(OpIdx).getReg(); 1546 unsigned Binary = 0; 1547 bool isSPVFP = ARM::SPRRegClass.contains(RegD); 1548 RegD = II->getRegisterInfo().getEncodingValue(RegD); 1549 if (!isSPVFP) 1550 Binary |= RegD << ARMII::RegRdShift; 1551 else { 1552 Binary |= ((RegD & 0x1E) >> 1) << ARMII::RegRdShift; 1553 Binary |= (RegD & 0x01) << ARMII::D_BitShift; 1554 } 1555 return Binary; 1556} 1557 1558unsigned ARMCodeEmitter::encodeVFPRn(const MachineInstr &MI, 1559 unsigned OpIdx) const { 1560 unsigned RegN = MI.getOperand(OpIdx).getReg(); 1561 unsigned Binary = 0; 1562 bool isSPVFP = ARM::SPRRegClass.contains(RegN); 1563 RegN = II->getRegisterInfo().getEncodingValue(RegN); 1564 if (!isSPVFP) 1565 Binary |= RegN << ARMII::RegRnShift; 1566 else { 1567 Binary |= ((RegN & 0x1E) >> 1) << ARMII::RegRnShift; 1568 Binary |= (RegN & 0x01) << ARMII::N_BitShift; 1569 } 1570 return Binary; 1571} 1572 1573unsigned ARMCodeEmitter::encodeVFPRm(const MachineInstr &MI, 1574 unsigned OpIdx) const { 1575 unsigned RegM = MI.getOperand(OpIdx).getReg(); 1576 unsigned Binary = 0; 1577 bool isSPVFP = ARM::SPRRegClass.contains(RegM); 1578 RegM = II->getRegisterInfo().getEncodingValue(RegM); 1579 if (!isSPVFP) 1580 Binary |= RegM; 1581 else { 1582 Binary |= ((RegM & 0x1E) >> 1); 1583 Binary |= (RegM & 0x01) << ARMII::M_BitShift; 1584 } 1585 return Binary; 1586} 1587 1588void ARMCodeEmitter::emitVFPArithInstruction(const MachineInstr &MI) { 1589 const MCInstrDesc &MCID = MI.getDesc(); 1590 1591 // Part of binary is determined by TableGn. 1592 unsigned Binary = getBinaryCodeForInstr(MI); 1593 1594 // Set the conditional execution predicate 1595 Binary |= II->getPredicate(&MI) << ARMII::CondShift; 1596 1597 unsigned OpIdx = 0; 1598 assert((Binary & ARMII::D_BitShift) == 0 && 1599 (Binary & ARMII::N_BitShift) == 0 && 1600 (Binary & ARMII::M_BitShift) == 0 && "VFP encoding bug!"); 1601 1602 // Encode Dd / Sd. 1603 Binary |= encodeVFPRd(MI, OpIdx++); 1604 1605 // If this is a two-address operand, skip it, e.g. FMACD. 1606 if (MCID.getOperandConstraint(OpIdx, MCOI::TIED_TO) != -1) 1607 ++OpIdx; 1608 1609 // Encode Dn / Sn. 1610 if ((MCID.TSFlags & ARMII::FormMask) == ARMII::VFPBinaryFrm) 1611 Binary |= encodeVFPRn(MI, OpIdx++); 1612 1613 if (OpIdx == MCID.getNumOperands() || 1614 MCID.OpInfo[OpIdx].isPredicate() || 1615 MCID.OpInfo[OpIdx].isOptionalDef()) { 1616 // FCMPEZD etc. has only one operand. 1617 emitWordLE(Binary); 1618 return; 1619 } 1620 1621 // Encode Dm / Sm. 1622 Binary |= encodeVFPRm(MI, OpIdx); 1623 1624 emitWordLE(Binary); 1625} 1626 1627void ARMCodeEmitter::emitVFPConversionInstruction(const MachineInstr &MI) { 1628 const MCInstrDesc &MCID = MI.getDesc(); 1629 unsigned Form = MCID.TSFlags & ARMII::FormMask; 1630 1631 // Part of binary is determined by TableGn. 1632 unsigned Binary = getBinaryCodeForInstr(MI); 1633 1634 // Set the conditional execution predicate 1635 Binary |= II->getPredicate(&MI) << ARMII::CondShift; 1636 1637 switch (Form) { 1638 default: break; 1639 case ARMII::VFPConv1Frm: 1640 case ARMII::VFPConv2Frm: 1641 case ARMII::VFPConv3Frm: 1642 // Encode Dd / Sd. 1643 Binary |= encodeVFPRd(MI, 0); 1644 break; 1645 case ARMII::VFPConv4Frm: 1646 // Encode Dn / Sn. 1647 Binary |= encodeVFPRn(MI, 0); 1648 break; 1649 case ARMII::VFPConv5Frm: 1650 // Encode Dm / Sm. 1651 Binary |= encodeVFPRm(MI, 0); 1652 break; 1653 } 1654 1655 switch (Form) { 1656 default: break; 1657 case ARMII::VFPConv1Frm: 1658 // Encode Dm / Sm. 1659 Binary |= encodeVFPRm(MI, 1); 1660 break; 1661 case ARMII::VFPConv2Frm: 1662 case ARMII::VFPConv3Frm: 1663 // Encode Dn / Sn. 1664 Binary |= encodeVFPRn(MI, 1); 1665 break; 1666 case ARMII::VFPConv4Frm: 1667 case ARMII::VFPConv5Frm: 1668 // Encode Dd / Sd. 1669 Binary |= encodeVFPRd(MI, 1); 1670 break; 1671 } 1672 1673 if (Form == ARMII::VFPConv5Frm) 1674 // Encode Dn / Sn. 1675 Binary |= encodeVFPRn(MI, 2); 1676 else if (Form == ARMII::VFPConv3Frm) 1677 // Encode Dm / Sm. 1678 Binary |= encodeVFPRm(MI, 2); 1679 1680 emitWordLE(Binary); 1681} 1682 1683void ARMCodeEmitter::emitVFPLoadStoreInstruction(const MachineInstr &MI) { 1684 // Part of binary is determined by TableGn. 1685 unsigned Binary = getBinaryCodeForInstr(MI); 1686 1687 // Set the conditional execution predicate 1688 Binary |= II->getPredicate(&MI) << ARMII::CondShift; 1689 1690 unsigned OpIdx = 0; 1691 1692 // Encode Dd / Sd. 1693 Binary |= encodeVFPRd(MI, OpIdx++); 1694 1695 // Encode address base. 1696 const MachineOperand &Base = MI.getOperand(OpIdx++); 1697 Binary |= getMachineOpValue(MI, Base) << ARMII::RegRnShift; 1698 1699 // If there is a non-zero immediate offset, encode it. 1700 if (Base.isReg()) { 1701 const MachineOperand &Offset = MI.getOperand(OpIdx); 1702 if (unsigned ImmOffs = ARM_AM::getAM5Offset(Offset.getImm())) { 1703 if (ARM_AM::getAM5Op(Offset.getImm()) == ARM_AM::add) 1704 Binary |= 1 << ARMII::U_BitShift; 1705 Binary |= ImmOffs; 1706 emitWordLE(Binary); 1707 return; 1708 } 1709 } 1710 1711 // If immediate offset is omitted, default to +0. 1712 Binary |= 1 << ARMII::U_BitShift; 1713 1714 emitWordLE(Binary); 1715} 1716 1717void 1718ARMCodeEmitter::emitVFPLoadStoreMultipleInstruction(const MachineInstr &MI) { 1719 const MCInstrDesc &MCID = MI.getDesc(); 1720 bool IsUpdating = (MCID.TSFlags & ARMII::IndexModeMask) != 0; 1721 1722 // Part of binary is determined by TableGn. 1723 unsigned Binary = getBinaryCodeForInstr(MI); 1724 1725 // Set the conditional execution predicate 1726 Binary |= II->getPredicate(&MI) << ARMII::CondShift; 1727 1728 // Skip operand 0 of an instruction with base register update. 1729 unsigned OpIdx = 0; 1730 if (IsUpdating) 1731 ++OpIdx; 1732 1733 // Set base address operand 1734 Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRnShift; 1735 1736 // Set addressing mode by modifying bits U(23) and P(24) 1737 ARM_AM::AMSubMode Mode = ARM_AM::getLoadStoreMultipleSubMode(MI.getOpcode()); 1738 Binary |= getAddrModeUPBits(ARM_AM::getAM4SubMode(Mode)); 1739 1740 // Set bit W(21) 1741 if (IsUpdating) 1742 Binary |= 0x1 << ARMII::W_BitShift; 1743 1744 // First register is encoded in Dd. 1745 Binary |= encodeVFPRd(MI, OpIdx+2); 1746 1747 // Count the number of registers. 1748 unsigned NumRegs = 1; 1749 for (unsigned i = OpIdx+3, e = MI.getNumOperands(); i != e; ++i) { 1750 const MachineOperand &MO = MI.getOperand(i); 1751 if (!MO.isReg() || MO.isImplicit()) 1752 break; 1753 ++NumRegs; 1754 } 1755 // Bit 8 will be set if <list> is consecutive 64-bit registers (e.g., D0) 1756 // Otherwise, it will be 0, in the case of 32-bit registers. 1757 if(Binary & 0x100) 1758 Binary |= NumRegs * 2; 1759 else 1760 Binary |= NumRegs; 1761 1762 emitWordLE(Binary); 1763} 1764 1765unsigned ARMCodeEmitter::encodeNEONRd(const MachineInstr &MI, 1766 unsigned OpIdx) const { 1767 unsigned RegD = MI.getOperand(OpIdx).getReg(); 1768 unsigned Binary = 0; 1769 RegD = II->getRegisterInfo().getEncodingValue(RegD); 1770 Binary |= (RegD & 0xf) << ARMII::RegRdShift; 1771 Binary |= ((RegD >> 4) & 1) << ARMII::D_BitShift; 1772 return Binary; 1773} 1774 1775unsigned ARMCodeEmitter::encodeNEONRn(const MachineInstr &MI, 1776 unsigned OpIdx) const { 1777 unsigned RegN = MI.getOperand(OpIdx).getReg(); 1778 unsigned Binary = 0; 1779 RegN = II->getRegisterInfo().getEncodingValue(RegN); 1780 Binary |= (RegN & 0xf) << ARMII::RegRnShift; 1781 Binary |= ((RegN >> 4) & 1) << ARMII::N_BitShift; 1782 return Binary; 1783} 1784 1785unsigned ARMCodeEmitter::encodeNEONRm(const MachineInstr &MI, 1786 unsigned OpIdx) const { 1787 unsigned RegM = MI.getOperand(OpIdx).getReg(); 1788 unsigned Binary = 0; 1789 RegM = II->getRegisterInfo().getEncodingValue(RegM); 1790 Binary |= (RegM & 0xf); 1791 Binary |= ((RegM >> 4) & 1) << ARMII::M_BitShift; 1792 return Binary; 1793} 1794 1795/// convertNEONDataProcToThumb - Convert the ARM mode encoding for a NEON 1796/// data-processing instruction to the corresponding Thumb encoding. 1797static unsigned convertNEONDataProcToThumb(unsigned Binary) { 1798 assert((Binary & 0xfe000000) == 0xf2000000 && 1799 "not an ARM NEON data-processing instruction"); 1800 unsigned UBit = (Binary >> 24) & 1; 1801 return 0xef000000 | (UBit << 28) | (Binary & 0xffffff); 1802} 1803 1804void ARMCodeEmitter::emitNEONLaneInstruction(const MachineInstr &MI) { 1805 unsigned Binary = getBinaryCodeForInstr(MI); 1806 1807 unsigned RegTOpIdx, RegNOpIdx, LnOpIdx; 1808 const MCInstrDesc &MCID = MI.getDesc(); 1809 if ((MCID.TSFlags & ARMII::FormMask) == ARMII::NGetLnFrm) { 1810 RegTOpIdx = 0; 1811 RegNOpIdx = 1; 1812 LnOpIdx = 2; 1813 } else { // ARMII::NSetLnFrm 1814 RegTOpIdx = 2; 1815 RegNOpIdx = 0; 1816 LnOpIdx = 3; 1817 } 1818 1819 // Set the conditional execution predicate 1820 Binary |= (IsThumb ? ARMCC::AL : II->getPredicate(&MI)) << ARMII::CondShift; 1821 1822 unsigned RegT = MI.getOperand(RegTOpIdx).getReg(); 1823 RegT = II->getRegisterInfo().getEncodingValue(RegT); 1824 Binary |= (RegT << ARMII::RegRdShift); 1825 Binary |= encodeNEONRn(MI, RegNOpIdx); 1826 1827 unsigned LaneShift; 1828 if ((Binary & (1 << 22)) != 0) 1829 LaneShift = 0; // 8-bit elements 1830 else if ((Binary & (1 << 5)) != 0) 1831 LaneShift = 1; // 16-bit elements 1832 else 1833 LaneShift = 2; // 32-bit elements 1834 1835 unsigned Lane = MI.getOperand(LnOpIdx).getImm() << LaneShift; 1836 unsigned Opc1 = Lane >> 2; 1837 unsigned Opc2 = Lane & 3; 1838 assert((Opc1 & 3) == 0 && "out-of-range lane number operand"); 1839 Binary |= (Opc1 << 21); 1840 Binary |= (Opc2 << 5); 1841 1842 emitWordLE(Binary); 1843} 1844 1845void ARMCodeEmitter::emitNEONDupInstruction(const MachineInstr &MI) { 1846 unsigned Binary = getBinaryCodeForInstr(MI); 1847 1848 // Set the conditional execution predicate 1849 Binary |= (IsThumb ? ARMCC::AL : II->getPredicate(&MI)) << ARMII::CondShift; 1850 1851 unsigned RegT = MI.getOperand(1).getReg(); 1852 RegT = II->getRegisterInfo().getEncodingValue(RegT); 1853 Binary |= (RegT << ARMII::RegRdShift); 1854 Binary |= encodeNEONRn(MI, 0); 1855 emitWordLE(Binary); 1856} 1857 1858void ARMCodeEmitter::emitNEON1RegModImmInstruction(const MachineInstr &MI) { 1859 unsigned Binary = getBinaryCodeForInstr(MI); 1860 // Destination register is encoded in Dd. 1861 Binary |= encodeNEONRd(MI, 0); 1862 // Immediate fields: Op, Cmode, I, Imm3, Imm4 1863 unsigned Imm = MI.getOperand(1).getImm(); 1864 unsigned Op = (Imm >> 12) & 1; 1865 unsigned Cmode = (Imm >> 8) & 0xf; 1866 unsigned I = (Imm >> 7) & 1; 1867 unsigned Imm3 = (Imm >> 4) & 0x7; 1868 unsigned Imm4 = Imm & 0xf; 1869 Binary |= (I << 24) | (Imm3 << 16) | (Cmode << 8) | (Op << 5) | Imm4; 1870 if (IsThumb) 1871 Binary = convertNEONDataProcToThumb(Binary); 1872 emitWordLE(Binary); 1873} 1874 1875void ARMCodeEmitter::emitNEON2RegInstruction(const MachineInstr &MI) { 1876 const MCInstrDesc &MCID = MI.getDesc(); 1877 unsigned Binary = getBinaryCodeForInstr(MI); 1878 // Destination register is encoded in Dd; source register in Dm. 1879 unsigned OpIdx = 0; 1880 Binary |= encodeNEONRd(MI, OpIdx++); 1881 if (MCID.getOperandConstraint(OpIdx, MCOI::TIED_TO) != -1) 1882 ++OpIdx; 1883 Binary |= encodeNEONRm(MI, OpIdx); 1884 if (IsThumb) 1885 Binary = convertNEONDataProcToThumb(Binary); 1886 // FIXME: This does not handle VDUPfdf or VDUPfqf. 1887 emitWordLE(Binary); 1888} 1889 1890void ARMCodeEmitter::emitNEON3RegInstruction(const MachineInstr &MI) { 1891 const MCInstrDesc &MCID = MI.getDesc(); 1892 unsigned Binary = getBinaryCodeForInstr(MI); 1893 // Destination register is encoded in Dd; source registers in Dn and Dm. 1894 unsigned OpIdx = 0; 1895 Binary |= encodeNEONRd(MI, OpIdx++); 1896 if (MCID.getOperandConstraint(OpIdx, MCOI::TIED_TO) != -1) 1897 ++OpIdx; 1898 Binary |= encodeNEONRn(MI, OpIdx++); 1899 if (MCID.getOperandConstraint(OpIdx, MCOI::TIED_TO) != -1) 1900 ++OpIdx; 1901 Binary |= encodeNEONRm(MI, OpIdx); 1902 if (IsThumb) 1903 Binary = convertNEONDataProcToThumb(Binary); 1904 // FIXME: This does not handle VMOVDneon or VMOVQ. 1905 emitWordLE(Binary); 1906} 1907 1908#include "ARMGenCodeEmitter.inc" 1909