ARMCodeEmitter.cpp revision df1c637ac4b6f6587c037be55cafed665c732d8f 
1//===-- ARM/ARMCodeEmitter.cpp - Convert ARM code to machine code ---------===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file contains the pass that transforms the ARM machine instructions into
11// relocatable machine code.
12//
13//===----------------------------------------------------------------------===//
14
15#define DEBUG_TYPE "jit"
16#include "ARM.h"
17#include "ARMConstantPoolValue.h"
18#include "ARMBaseInstrInfo.h"
19#include "ARMRelocations.h"
20#include "ARMSubtarget.h"
21#include "ARMTargetMachine.h"
22#include "MCTargetDesc/ARMAddressingModes.h"
23#include "llvm/Constants.h"
24#include "llvm/DerivedTypes.h"
25#include "llvm/Function.h"
26#include "llvm/PassManager.h"
27#include "llvm/CodeGen/JITCodeEmitter.h"
28#include "llvm/CodeGen/MachineConstantPool.h"
29#include "llvm/CodeGen/MachineFunctionPass.h"
30#include "llvm/CodeGen/MachineInstr.h"
31#include "llvm/CodeGen/MachineJumpTableInfo.h"
32#include "llvm/CodeGen/MachineModuleInfo.h"
33#include "llvm/CodeGen/Passes.h"
34#include "llvm/ADT/Statistic.h"
35#include "llvm/Support/Debug.h"
36#include "llvm/Support/ErrorHandling.h"
37#include "llvm/Support/raw_ostream.h"
38#ifndef NDEBUG
39#include <iomanip>
40#endif
41using namespace llvm;
42
43STATISTIC(NumEmitted, "Number of machine instructions emitted");
44
45namespace {
46
47  class ARMCodeEmitter : public MachineFunctionPass {
48    ARMJITInfo                *JTI;
49    const ARMBaseInstrInfo    *II;
50    const TargetData          *TD;
51    const ARMSubtarget        *Subtarget;
52    TargetMachine             &TM;
53    JITCodeEmitter            &MCE;
54    MachineModuleInfo *MMI;
55    const std::vector<MachineConstantPoolEntry> *MCPEs;
56    const std::vector<MachineJumpTableEntry> *MJTEs;
57    bool IsPIC;
58    bool IsThumb;
59
60    void getAnalysisUsage(AnalysisUsage &AU) const {
61      AU.addRequired<MachineModuleInfo>();
62      MachineFunctionPass::getAnalysisUsage(AU);
63    }
64
65    static char ID;
66  public:
67    ARMCodeEmitter(TargetMachine &tm, JITCodeEmitter &mce)
68      : MachineFunctionPass(ID), JTI(0),
69        II((const ARMBaseInstrInfo *)tm.getInstrInfo()),
70        TD(tm.getTargetData()), TM(tm),
71        MCE(mce), MCPEs(0), MJTEs(0),
72        IsPIC(TM.getRelocationModel() == Reloc::PIC_), IsThumb(false) {}
73
74    /// getBinaryCodeForInstr - This function, generated by the
75    /// CodeEmitterGenerator using TableGen, produces the binary encoding for
76    /// machine instructions.
77    uint64_t getBinaryCodeForInstr(const MachineInstr &MI) const;
78
79    bool runOnMachineFunction(MachineFunction &MF);
80
81    virtual const char *getPassName() const {
82      return "ARM Machine Code Emitter";
83    }
84
85    void emitInstruction(const MachineInstr &MI);
86
87  private:
88
89    void emitWordLE(unsigned Binary);
90    void emitDWordLE(uint64_t Binary);
91    void emitConstPoolInstruction(const MachineInstr &MI);
92    void emitMOVi32immInstruction(const MachineInstr &MI);
93    void emitMOVi2piecesInstruction(const MachineInstr &MI);
94    void emitLEApcrelJTInstruction(const MachineInstr &MI);
95    void emitPseudoMoveInstruction(const MachineInstr &MI);
96    void addPCLabel(unsigned LabelID);
97    void emitPseudoInstruction(const MachineInstr &MI);
98    unsigned getMachineSoRegOpValue(const MachineInstr &MI,
99                                    const MCInstrDesc &MCID,
100                                    const MachineOperand &MO,
101                                    unsigned OpIdx);
102
103    unsigned getMachineSoImmOpValue(unsigned SoImm);
104    unsigned getAddrModeSBit(const MachineInstr &MI,
105                             const MCInstrDesc &MCID) const;
106
107    void emitDataProcessingInstruction(const MachineInstr &MI,
108                                       unsigned ImplicitRd = 0,
109                                       unsigned ImplicitRn = 0);
110
111    void emitLoadStoreInstruction(const MachineInstr &MI,
112                                  unsigned ImplicitRd = 0,
113                                  unsigned ImplicitRn = 0);
114
115    void emitMiscLoadStoreInstruction(const MachineInstr &MI,
116                                      unsigned ImplicitRn = 0);
117
118    void emitLoadStoreMultipleInstruction(const MachineInstr &MI);
119
120    void emitMulFrmInstruction(const MachineInstr &MI);
121
122    void emitExtendInstruction(const MachineInstr &MI);
123
124    void emitMiscArithInstruction(const MachineInstr &MI);
125
126    void emitSaturateInstruction(const MachineInstr &MI);
127
128    void emitBranchInstruction(const MachineInstr &MI);
129
130    void emitInlineJumpTable(unsigned JTIndex);
131
132    void emitMiscBranchInstruction(const MachineInstr &MI);
133
134    void emitVFPArithInstruction(const MachineInstr &MI);
135
136    void emitVFPConversionInstruction(const MachineInstr &MI);
137
138    void emitVFPLoadStoreInstruction(const MachineInstr &MI);
139
140    void emitVFPLoadStoreMultipleInstruction(const MachineInstr &MI);
141
142    void emitNEONLaneInstruction(const MachineInstr &MI);
143    void emitNEONDupInstruction(const MachineInstr &MI);
144    void emitNEON1RegModImmInstruction(const MachineInstr &MI);
145    void emitNEON2RegInstruction(const MachineInstr &MI);
146    void emitNEON3RegInstruction(const MachineInstr &MI);
147
148    /// getMachineOpValue - Return binary encoding of operand. If the machine
149    /// operand requires relocation, record the relocation and return zero.
150    unsigned getMachineOpValue(const MachineInstr &MI,
151                               const MachineOperand &MO) const;
152    unsigned getMachineOpValue(const MachineInstr &MI, unsigned OpIdx) const {
153      return getMachineOpValue(MI, MI.getOperand(OpIdx));
154    }
155
156    // FIXME: The legacy JIT ARMCodeEmitter doesn't rely on the the
157    //  TableGen'erated getBinaryCodeForInstr() function to encode any
158    //  operand values, instead querying getMachineOpValue() directly for
159    //  each operand it needs to encode. Thus, any of the new encoder
160    //  helper functions can simply return 0 as the values the return
161    //  are already handled elsewhere. They are placeholders to allow this
162    //  encoder to continue to function until the MC encoder is sufficiently
163    //  far along that this one can be eliminated entirely.
164    unsigned NEONThumb2DataIPostEncoder(const MachineInstr &MI, unsigned Val)
165      const { return 0; }
166    unsigned NEONThumb2LoadStorePostEncoder(const MachineInstr &MI,unsigned Val)
167      const { return 0; }
168    unsigned NEONThumb2DupPostEncoder(const MachineInstr &MI,unsigned Val)
169      const { return 0; }
170    unsigned VFPThumb2PostEncoder(const MachineInstr&MI, unsigned Val)
171      const { return 0; }
172    unsigned getAdrLabelOpValue(const MachineInstr &MI, unsigned Op)
173      const { return 0; }
174    unsigned getThumbAdrLabelOpValue(const MachineInstr &MI, unsigned Op)
175      const { return 0; }
176    unsigned getThumbBLTargetOpValue(const MachineInstr &MI, unsigned Op)
177      const { return 0; }
178    unsigned getThumbBLXTargetOpValue(const MachineInstr &MI, unsigned Op)
179      const { return 0; }
180    unsigned getThumbBRTargetOpValue(const MachineInstr &MI, unsigned Op)
181      const { return 0; }
182    unsigned getThumbBCCTargetOpValue(const MachineInstr &MI, unsigned Op)
183      const { return 0; }
184    unsigned getThumbCBTargetOpValue(const MachineInstr &MI, unsigned Op)
185      const { return 0; }
186    unsigned getBranchTargetOpValue(const MachineInstr &MI, unsigned Op)
187      const { return 0; }
188    unsigned getUnconditionalBranchTargetOpValue(const MachineInstr &MI,
189      unsigned Op) const { return 0; }
190    unsigned getARMBranchTargetOpValue(const MachineInstr &MI, unsigned Op)
191      const { return 0; }
192    unsigned getARMBLTargetOpValue(const MachineInstr &MI, unsigned Op)
193      const { return 0; }
194    unsigned getARMBLXTargetOpValue(const MachineInstr &MI, unsigned Op)
195      const { return 0; }
196    unsigned getCCOutOpValue(const MachineInstr &MI, unsigned Op)
197      const { return 0; }
198    unsigned getSOImmOpValue(const MachineInstr &MI, unsigned Op)
199      const { return 0; }
200    unsigned getT2SOImmOpValue(const MachineInstr &MI, unsigned Op)
201      const { return 0; }
202    unsigned getSORegRegOpValue(const MachineInstr &MI, unsigned Op)
203      const { return 0; }
204    unsigned getSORegImmOpValue(const MachineInstr &MI, unsigned Op)
205      const { return 0; }
206    unsigned getThumbAddrModeRegRegOpValue(const MachineInstr &MI, unsigned Op)
207      const { return 0; }
208    unsigned getT2AddrModeImm12OpValue(const MachineInstr &MI, unsigned Op)
209      const { return 0; }
210    unsigned getT2AddrModeImm8OpValue(const MachineInstr &MI, unsigned Op)
211      const { return 0; }
212    unsigned getT2Imm8s4OpValue(const MachineInstr &MI, unsigned Op)
213      const { return 0; }
214    unsigned getT2AddrModeImm8s4OpValue(const MachineInstr &MI, unsigned Op)
215      const { return 0; }
216    unsigned getT2AddrModeImm0_1020s4OpValue(const MachineInstr &MI,unsigned Op)
217      const { return 0; }
218    unsigned getT2AddrModeImm8OffsetOpValue(const MachineInstr &MI, unsigned Op)
219      const { return 0; }
220    unsigned getT2AddrModeImm12OffsetOpValue(const MachineInstr &MI,unsigned Op)
221      const { return 0; }
222    unsigned getT2AddrModeSORegOpValue(const MachineInstr &MI, unsigned Op)
223      const { return 0; }
224    unsigned getT2SORegOpValue(const MachineInstr &MI, unsigned Op)
225      const { return 0; }
226    unsigned getT2AdrLabelOpValue(const MachineInstr &MI, unsigned Op)
227      const { return 0; }
228    unsigned getAddrMode6AddressOpValue(const MachineInstr &MI, unsigned Op)
229      const { return 0; }
230    unsigned getAddrMode6OneLane32AddressOpValue(const MachineInstr &MI,
231                                                 unsigned Op)
232      const { return 0; }
233    unsigned getAddrMode6DupAddressOpValue(const MachineInstr &MI, unsigned Op)
234      const { return 0; }
235    unsigned getAddrMode6OffsetOpValue(const MachineInstr &MI, unsigned Op)
236      const { return 0; }
237    unsigned getBitfieldInvertedMaskOpValue(const MachineInstr &MI,
238                                            unsigned Op) const { return 0; }
239    unsigned getSsatBitPosValue(const MachineInstr &MI,
240                                unsigned Op) const { return 0; }
241    uint32_t getLdStmModeOpValue(const MachineInstr &MI, unsigned OpIdx)
242      const {return 0; }
243    uint32_t getLdStSORegOpValue(const MachineInstr &MI, unsigned OpIdx)
244      const { return 0; }
245
246    unsigned getAddrModeImm12OpValue(const MachineInstr &MI, unsigned Op)
247      const {
248      // {17-13} = reg
249      // {12}    = (U)nsigned (add == '1', sub == '0')
250      // {11-0}  = imm12
251      const MachineOperand &MO  = MI.getOperand(Op);
252      const MachineOperand &MO1 = MI.getOperand(Op + 1);
253      if (!MO.isReg()) {
254        emitConstPoolAddress(MO.getIndex(), ARM::reloc_arm_cp_entry);
255        return 0;
256      }
257      unsigned Reg = II->getRegisterInfo().getEncodingValue(MO.getReg());
258      int32_t Imm12 = MO1.getImm();
259      uint32_t Binary;
260      Binary = Imm12 & 0xfff;
261      if (Imm12 >= 0)
262        Binary |= (1 << 12);
263      Binary |= (Reg << 13);
264      return Binary;
265    }
266
267    unsigned getHiLo16ImmOpValue(const MachineInstr &MI, unsigned Op) const {
268      return 0;
269    }
270
271    uint32_t getAddrMode2OpValue(const MachineInstr &MI, unsigned OpIdx)
272      const { return 0;}
273    uint32_t getAddrMode2OffsetOpValue(const MachineInstr &MI, unsigned OpIdx)
274      const { return 0;}
275    uint32_t getPostIdxRegOpValue(const MachineInstr &MI, unsigned OpIdx)
276      const { return 0;}
277    uint32_t getAddrMode3OffsetOpValue(const MachineInstr &MI, unsigned OpIdx)
278      const { return 0;}
279    uint32_t getAddrMode3OpValue(const MachineInstr &MI, unsigned Op)
280      const { return 0; }
281    uint32_t getAddrModeThumbSPOpValue(const MachineInstr &MI, unsigned Op)
282      const { return 0; }
283    uint32_t getAddrModeSOpValue(const MachineInstr &MI, unsigned Op)
284      const { return 0; }
285    uint32_t getAddrModeISOpValue(const MachineInstr &MI, unsigned Op)
286      const { return 0; }
287    uint32_t getAddrModePCOpValue(const MachineInstr &MI, unsigned Op)
288      const { return 0; }
289    uint32_t getAddrMode5OpValue(const MachineInstr &MI, unsigned Op) const {
290      // {17-13} = reg
291      // {12}    = (U)nsigned (add == '1', sub == '0')
292      // {11-0}  = imm12
293      const MachineOperand &MO  = MI.getOperand(Op);
294      const MachineOperand &MO1 = MI.getOperand(Op + 1);
295      if (!MO.isReg()) {
296        emitConstPoolAddress(MO.getIndex(), ARM::reloc_arm_cp_entry);
297        return 0;
298      }
299      unsigned Reg = II->getRegisterInfo().getEncodingValue(MO.getReg());
300      int32_t Imm12 = MO1.getImm();
301
302      // Special value for #-0
303      if (Imm12 == INT32_MIN)
304        Imm12 = 0;
305
306      // Immediate is always encoded as positive. The 'U' bit controls add vs
307      // sub.
308      bool isAdd = true;
309      if (Imm12 < 0) {
310        Imm12 = -Imm12;
311        isAdd = false;
312      }
313
314      uint32_t Binary = Imm12 & 0xfff;
315      if (isAdd)
316        Binary |= (1 << 12);
317      Binary |= (Reg << 13);
318      return Binary;
319    }
320    unsigned getNEONVcvtImm32OpValue(const MachineInstr &MI, unsigned Op)
321      const { return 0; }
322
323    unsigned getRegisterListOpValue(const MachineInstr &MI, unsigned Op)
324      const { return 0; }
325
326    unsigned getShiftRight8Imm(const MachineInstr &MI, unsigned Op)
327      const { return 0; }
328    unsigned getShiftRight16Imm(const MachineInstr &MI, unsigned Op)
329      const { return 0; }
330    unsigned getShiftRight32Imm(const MachineInstr &MI, unsigned Op)
331      const { return 0; }
332    unsigned getShiftRight64Imm(const MachineInstr &MI, unsigned Op)
333      const { return 0; }
334
335    /// getMovi32Value - Return binary encoding of operand for movw/movt. If the
336    /// machine operand requires relocation, record the relocation and return
337    /// zero.
338    unsigned getMovi32Value(const MachineInstr &MI,const MachineOperand &MO,
339                            unsigned Reloc);
340
341    /// getShiftOp - Return the shift opcode (bit[6:5]) of the immediate value.
342    ///
343    unsigned getShiftOp(unsigned Imm) const ;
344
345    /// Routines that handle operands which add machine relocations which are
346    /// fixed up by the relocation stage.
347    void emitGlobalAddress(const GlobalValue *GV, unsigned Reloc,
348                           bool MayNeedFarStub,  bool Indirect,
349                           intptr_t ACPV = 0) const;
350    void emitExternalSymbolAddress(const char *ES, unsigned Reloc) const;
351    void emitConstPoolAddress(unsigned CPI, unsigned Reloc) const;
352    void emitJumpTableAddress(unsigned JTIndex, unsigned Reloc) const;
353    void emitMachineBasicBlock(MachineBasicBlock *BB, unsigned Reloc,
354                               intptr_t JTBase = 0) const;
355    unsigned encodeVFPRd(const MachineInstr &MI, unsigned OpIdx) const;
356    unsigned encodeVFPRn(const MachineInstr &MI, unsigned OpIdx) const;
357    unsigned encodeVFPRm(const MachineInstr &MI, unsigned OpIdx) const;
358    unsigned encodeNEONRd(const MachineInstr &MI, unsigned OpIdx) const;
359    unsigned encodeNEONRn(const MachineInstr &MI, unsigned OpIdx) const;
360    unsigned encodeNEONRm(const MachineInstr &MI, unsigned OpIdx) const;
361  };
362}
363
364char ARMCodeEmitter::ID = 0;
365
366/// createARMJITCodeEmitterPass - Return a pass that emits the collected ARM
367/// code to the specified MCE object.
368FunctionPass *llvm::createARMJITCodeEmitterPass(ARMBaseTargetMachine &TM,
369                                                JITCodeEmitter &JCE) {
370  return new ARMCodeEmitter(TM, JCE);
371}
372
373bool ARMCodeEmitter::runOnMachineFunction(MachineFunction &MF) {
374  assert((MF.getTarget().getRelocationModel() != Reloc::Default ||
375          MF.getTarget().getRelocationModel() != Reloc::Static) &&
376         "JIT relocation model must be set to static or default!");
377  JTI = ((ARMBaseTargetMachine &)MF.getTarget()).getJITInfo();
378  II = (const ARMBaseInstrInfo *)MF.getTarget().getInstrInfo();
379  TD = MF.getTarget().getTargetData();
380  Subtarget = &TM.getSubtarget<ARMSubtarget>();
381  MCPEs = &MF.getConstantPool()->getConstants();
382  MJTEs = 0;
383  if (MF.getJumpTableInfo()) MJTEs = &MF.getJumpTableInfo()->getJumpTables();
384  IsPIC = TM.getRelocationModel() == Reloc::PIC_;
385  IsThumb = MF.getInfo<ARMFunctionInfo>()->isThumbFunction();
386  JTI->Initialize(MF, IsPIC);
387  MMI = &getAnalysis<MachineModuleInfo>();
388  MCE.setModuleInfo(MMI);
389
390  do {
391    DEBUG(errs() << "JITTing function '"
392          << MF.getFunction()->getName() << "'\n");
393    MCE.startFunction(MF);
394    for (MachineFunction::iterator MBB = MF.begin(), E = MF.end();
395         MBB != E; ++MBB) {
396      MCE.StartMachineBasicBlock(MBB);
397      for (MachineBasicBlock::iterator I = MBB->begin(), E = MBB->end();
398           I != E; ++I)
399        emitInstruction(*I);
400    }
401  } while (MCE.finishFunction(MF));
402
403  return false;
404}
405
406/// getShiftOp - Return the shift opcode (bit[6:5]) of the immediate value.
407///
408unsigned ARMCodeEmitter::getShiftOp(unsigned Imm) const {
409  switch (ARM_AM::getAM2ShiftOpc(Imm)) {
410  default: llvm_unreachable("Unknown shift opc!");
411  case ARM_AM::asr: return 2;
412  case ARM_AM::lsl: return 0;
413  case ARM_AM::lsr: return 1;
414  case ARM_AM::ror:
415  case ARM_AM::rrx: return 3;
416  }
417}
418
419/// getMovi32Value - Return binary encoding of operand for movw/movt. If the
420/// machine operand requires relocation, record the relocation and return zero.
421unsigned ARMCodeEmitter::getMovi32Value(const MachineInstr &MI,
422                                        const MachineOperand &MO,
423                                        unsigned Reloc) {
424  assert(((Reloc == ARM::reloc_arm_movt) || (Reloc == ARM::reloc_arm_movw))
425      && "Relocation to this function should be for movt or movw");
426
427  if (MO.isImm())
428    return static_cast<unsigned>(MO.getImm());
429  else if (MO.isGlobal())
430    emitGlobalAddress(MO.getGlobal(), Reloc, true, false);
431  else if (MO.isSymbol())
432    emitExternalSymbolAddress(MO.getSymbolName(), Reloc);
433  else if (MO.isMBB())
434    emitMachineBasicBlock(MO.getMBB(), Reloc);
435  else {
436#ifndef NDEBUG
437    errs() << MO;
438#endif
439    llvm_unreachable("Unsupported operand type for movw/movt");
440  }
441  return 0;
442}
443
444/// getMachineOpValue - Return binary encoding of operand. If the machine
445/// operand requires relocation, record the relocation and return zero.
446unsigned ARMCodeEmitter::getMachineOpValue(const MachineInstr &MI,
447                                           const MachineOperand &MO) const {
448  if (MO.isReg())
449    return II->getRegisterInfo().getEncodingValue(MO.getReg());
450  else if (MO.isImm())
451    return static_cast<unsigned>(MO.getImm());
452  else if (MO.isGlobal())
453    emitGlobalAddress(MO.getGlobal(), ARM::reloc_arm_branch, true, false);
454  else if (MO.isSymbol())
455    emitExternalSymbolAddress(MO.getSymbolName(), ARM::reloc_arm_branch);
456  else if (MO.isCPI()) {
457    const MCInstrDesc &MCID = MI.getDesc();
458    // For VFP load, the immediate offset is multiplied by 4.
459    unsigned Reloc =  ((MCID.TSFlags & ARMII::FormMask) == ARMII::VFPLdStFrm)
460      ? ARM::reloc_arm_vfp_cp_entry : ARM::reloc_arm_cp_entry;
461    emitConstPoolAddress(MO.getIndex(), Reloc);
462  } else if (MO.isJTI())
463    emitJumpTableAddress(MO.getIndex(), ARM::reloc_arm_relative);
464  else if (MO.isMBB())
465    emitMachineBasicBlock(MO.getMBB(), ARM::reloc_arm_branch);
466  else
467    llvm_unreachable("Unable to encode MachineOperand!");
468  return 0;
469}
470
471/// emitGlobalAddress - Emit the specified address to the code stream.
472///
473void ARMCodeEmitter::emitGlobalAddress(const GlobalValue *GV, unsigned Reloc,
474                                       bool MayNeedFarStub, bool Indirect,
475                                       intptr_t ACPV) const {
476  MachineRelocation MR = Indirect
477    ? MachineRelocation::getIndirectSymbol(MCE.getCurrentPCOffset(), Reloc,
478                                           const_cast<GlobalValue *>(GV),
479                                           ACPV, MayNeedFarStub)
480    : MachineRelocation::getGV(MCE.getCurrentPCOffset(), Reloc,
481                               const_cast<GlobalValue *>(GV), ACPV,
482                               MayNeedFarStub);
483  MCE.addRelocation(MR);
484}
485
486/// emitExternalSymbolAddress - Arrange for the address of an external symbol to
487/// be emitted to the current location in the function, and allow it to be PC
488/// relative.
489void ARMCodeEmitter::
490emitExternalSymbolAddress(const char *ES, unsigned Reloc) const {
491  MCE.addRelocation(MachineRelocation::getExtSym(MCE.getCurrentPCOffset(),
492                                                 Reloc, ES));
493}
494
495/// emitConstPoolAddress - Arrange for the address of an constant pool
496/// to be emitted to the current location in the function, and allow it to be PC
497/// relative.
498void ARMCodeEmitter::emitConstPoolAddress(unsigned CPI, unsigned Reloc) const {
499  // Tell JIT emitter we'll resolve the address.
500  MCE.addRelocation(MachineRelocation::getConstPool(MCE.getCurrentPCOffset(),
501                                                    Reloc, CPI, 0, true));
502}
503
504/// emitJumpTableAddress - Arrange for the address of a jump table to
505/// be emitted to the current location in the function, and allow it to be PC
506/// relative.
507void ARMCodeEmitter::
508emitJumpTableAddress(unsigned JTIndex, unsigned Reloc) const {
509  MCE.addRelocation(MachineRelocation::getJumpTable(MCE.getCurrentPCOffset(),
510                                                    Reloc, JTIndex, 0, true));
511}
512
513/// emitMachineBasicBlock - Emit the specified address basic block.
514void ARMCodeEmitter::emitMachineBasicBlock(MachineBasicBlock *BB,
515                                           unsigned Reloc,
516                                           intptr_t JTBase) const {
517  MCE.addRelocation(MachineRelocation::getBB(MCE.getCurrentPCOffset(),
518                                             Reloc, BB, JTBase));
519}
520
521void ARMCodeEmitter::emitWordLE(unsigned Binary) {
522  DEBUG(errs() << "  0x";
523        errs().write_hex(Binary) << "\n");
524  MCE.emitWordLE(Binary);
525}
526
527void ARMCodeEmitter::emitDWordLE(uint64_t Binary) {
528  DEBUG(errs() << "  0x";
529        errs().write_hex(Binary) << "\n");
530  MCE.emitDWordLE(Binary);
531}
532
533void ARMCodeEmitter::emitInstruction(const MachineInstr &MI) {
534  DEBUG(errs() << "JIT: " << (void*)MCE.getCurrentPCValue() << ":\t" << MI);
535
536  MCE.processDebugLoc(MI.getDebugLoc(), true);
537
538  ++NumEmitted;  // Keep track of the # of mi's emitted
539  switch (MI.getDesc().TSFlags & ARMII::FormMask) {
540  default: {
541    llvm_unreachable("Unhandled instruction encoding format!");
542  }
543  case ARMII::MiscFrm:
544    if (MI.getOpcode() == ARM::LEApcrelJT) {
545      // Materialize jumptable address.
546      emitLEApcrelJTInstruction(MI);
547      break;
548    }
549    llvm_unreachable("Unhandled instruction encoding!");
550  case ARMII::Pseudo:
551    emitPseudoInstruction(MI);
552    break;
553  case ARMII::DPFrm:
554  case ARMII::DPSoRegFrm:
555    emitDataProcessingInstruction(MI);
556    break;
557  case ARMII::LdFrm:
558  case ARMII::StFrm:
559    emitLoadStoreInstruction(MI);
560    break;
561  case ARMII::LdMiscFrm:
562  case ARMII::StMiscFrm:
563    emitMiscLoadStoreInstruction(MI);
564    break;
565  case ARMII::LdStMulFrm:
566    emitLoadStoreMultipleInstruction(MI);
567    break;
568  case ARMII::MulFrm:
569    emitMulFrmInstruction(MI);
570    break;
571  case ARMII::ExtFrm:
572    emitExtendInstruction(MI);
573    break;
574  case ARMII::ArithMiscFrm:
575    emitMiscArithInstruction(MI);
576    break;
577  case ARMII::SatFrm:
578    emitSaturateInstruction(MI);
579    break;
580  case ARMII::BrFrm:
581    emitBranchInstruction(MI);
582    break;
583  case ARMII::BrMiscFrm:
584    emitMiscBranchInstruction(MI);
585    break;
586  // VFP instructions.
587  case ARMII::VFPUnaryFrm:
588  case ARMII::VFPBinaryFrm:
589    emitVFPArithInstruction(MI);
590    break;
591  case ARMII::VFPConv1Frm:
592  case ARMII::VFPConv2Frm:
593  case ARMII::VFPConv3Frm:
594  case ARMII::VFPConv4Frm:
595  case ARMII::VFPConv5Frm:
596    emitVFPConversionInstruction(MI);
597    break;
598  case ARMII::VFPLdStFrm:
599    emitVFPLoadStoreInstruction(MI);
600    break;
601  case ARMII::VFPLdStMulFrm:
602    emitVFPLoadStoreMultipleInstruction(MI);
603    break;
604
605  // NEON instructions.
606  case ARMII::NGetLnFrm:
607  case ARMII::NSetLnFrm:
608    emitNEONLaneInstruction(MI);
609    break;
610  case ARMII::NDupFrm:
611    emitNEONDupInstruction(MI);
612    break;
613  case ARMII::N1RegModImmFrm:
614    emitNEON1RegModImmInstruction(MI);
615    break;
616  case ARMII::N2RegFrm:
617    emitNEON2RegInstruction(MI);
618    break;
619  case ARMII::N3RegFrm:
620    emitNEON3RegInstruction(MI);
621    break;
622  }
623  MCE.processDebugLoc(MI.getDebugLoc(), false);
624}
625
626void ARMCodeEmitter::emitConstPoolInstruction(const MachineInstr &MI) {
627  unsigned CPI = MI.getOperand(0).getImm();       // CP instruction index.
628  unsigned CPIndex = MI.getOperand(1).getIndex(); // Actual cp entry index.
629  const MachineConstantPoolEntry &MCPE = (*MCPEs)[CPIndex];
630
631  // Remember the CONSTPOOL_ENTRY address for later relocation.
632  JTI->addConstantPoolEntryAddr(CPI, MCE.getCurrentPCValue());
633
634  // Emit constpool island entry. In most cases, the actual values will be
635  // resolved and relocated after code emission.
636  if (MCPE.isMachineConstantPoolEntry()) {
637    ARMConstantPoolValue *ACPV =
638      static_cast<ARMConstantPoolValue*>(MCPE.Val.MachineCPVal);
639
640    DEBUG(errs() << "  ** ARM constant pool #" << CPI << " @ "
641          << (void*)MCE.getCurrentPCValue() << " " << *ACPV << '\n');
642
643    assert(ACPV->isGlobalValue() && "unsupported constant pool value");
644    const GlobalValue *GV = cast<ARMConstantPoolConstant>(ACPV)->getGV();
645    if (GV) {
646      Reloc::Model RelocM = TM.getRelocationModel();
647      emitGlobalAddress(GV, ARM::reloc_arm_machine_cp_entry,
648                        isa<Function>(GV),
649                        Subtarget->GVIsIndirectSymbol(GV, RelocM),
650                        (intptr_t)ACPV);
651    } else  {
652      const char *Sym = cast<ARMConstantPoolSymbol>(ACPV)->getSymbol();
653      emitExternalSymbolAddress(Sym, ARM::reloc_arm_absolute);
654    }
655    emitWordLE(0);
656  } else {
657    const Constant *CV = MCPE.Val.ConstVal;
658
659    DEBUG({
660        errs() << "  ** Constant pool #" << CPI << " @ "
661               << (void*)MCE.getCurrentPCValue() << " ";
662        if (const Function *F = dyn_cast<Function>(CV))
663          errs() << F->getName();
664        else
665          errs() << *CV;
666        errs() << '\n';
667      });
668
669    if (const GlobalValue *GV = dyn_cast<GlobalValue>(CV)) {
670      emitGlobalAddress(GV, ARM::reloc_arm_absolute, isa<Function>(GV), false);
671      emitWordLE(0);
672    } else if (const ConstantInt *CI = dyn_cast<ConstantInt>(CV)) {
673      uint32_t Val = uint32_t(*CI->getValue().getRawData());
674      emitWordLE(Val);
675    } else if (const ConstantFP *CFP = dyn_cast<ConstantFP>(CV)) {
676      if (CFP->getType()->isFloatTy())
677        emitWordLE(CFP->getValueAPF().bitcastToAPInt().getZExtValue());
678      else if (CFP->getType()->isDoubleTy())
679        emitDWordLE(CFP->getValueAPF().bitcastToAPInt().getZExtValue());
680      else {
681        llvm_unreachable("Unable to handle this constantpool entry!");
682      }
683    } else {
684      llvm_unreachable("Unable to handle this constantpool entry!");
685    }
686  }
687}
688
689void ARMCodeEmitter::emitMOVi32immInstruction(const MachineInstr &MI) {
690  const MachineOperand &MO0 = MI.getOperand(0);
691  const MachineOperand &MO1 = MI.getOperand(1);
692
693  // Emit the 'movw' instruction.
694  unsigned Binary = 0x30 << 20;  // mov: Insts{27-20} = 0b00110000
695
696  unsigned Lo16 = getMovi32Value(MI, MO1, ARM::reloc_arm_movw) & 0xFFFF;
697
698  // Set the conditional execution predicate.
699  Binary |= II->getPredicate(&MI) << ARMII::CondShift;
700
701  // Encode Rd.
702  Binary |= getMachineOpValue(MI, MO0) << ARMII::RegRdShift;
703
704  // Encode imm16 as imm4:imm12
705  Binary |= Lo16 & 0xFFF; // Insts{11-0} = imm12
706  Binary |= ((Lo16 >> 12) & 0xF) << 16; // Insts{19-16} = imm4
707  emitWordLE(Binary);
708
709  unsigned Hi16 = getMovi32Value(MI, MO1, ARM::reloc_arm_movt) >> 16;
710  // Emit the 'movt' instruction.
711  Binary = 0x34 << 20; // movt: Insts{27-20} = 0b00110100
712
713  // Set the conditional execution predicate.
714  Binary |= II->getPredicate(&MI) << ARMII::CondShift;
715
716  // Encode Rd.
717  Binary |= getMachineOpValue(MI, MO0) << ARMII::RegRdShift;
718
719  // Encode imm16 as imm4:imm1, same as movw above.
720  Binary |= Hi16 & 0xFFF;
721  Binary |= ((Hi16 >> 12) & 0xF) << 16;
722  emitWordLE(Binary);
723}
724
725void ARMCodeEmitter::emitMOVi2piecesInstruction(const MachineInstr &MI) {
726  const MachineOperand &MO0 = MI.getOperand(0);
727  const MachineOperand &MO1 = MI.getOperand(1);
728  assert(MO1.isImm() && ARM_AM::isSOImmTwoPartVal(MO1.getImm()) &&
729                                                  "Not a valid so_imm value!");
730  unsigned V1 = ARM_AM::getSOImmTwoPartFirst(MO1.getImm());
731  unsigned V2 = ARM_AM::getSOImmTwoPartSecond(MO1.getImm());
732
733  // Emit the 'mov' instruction.
734  unsigned Binary = 0xd << 21;  // mov: Insts{24-21} = 0b1101
735
736  // Set the conditional execution predicate.
737  Binary |= II->getPredicate(&MI) << ARMII::CondShift;
738
739  // Encode Rd.
740  Binary |= getMachineOpValue(MI, MO0) << ARMII::RegRdShift;
741
742  // Encode so_imm.
743  // Set bit I(25) to identify this is the immediate form of <shifter_op>
744  Binary |= 1 << ARMII::I_BitShift;
745  Binary |= getMachineSoImmOpValue(V1);
746  emitWordLE(Binary);
747
748  // Now the 'orr' instruction.
749  Binary = 0xc << 21;  // orr: Insts{24-21} = 0b1100
750
751  // Set the conditional execution predicate.
752  Binary |= II->getPredicate(&MI) << ARMII::CondShift;
753
754  // Encode Rd.
755  Binary |= getMachineOpValue(MI, MO0) << ARMII::RegRdShift;
756
757  // Encode Rn.
758  Binary |= getMachineOpValue(MI, MO0) << ARMII::RegRnShift;
759
760  // Encode so_imm.
761  // Set bit I(25) to identify this is the immediate form of <shifter_op>
762  Binary |= 1 << ARMII::I_BitShift;
763  Binary |= getMachineSoImmOpValue(V2);
764  emitWordLE(Binary);
765}
766
767void ARMCodeEmitter::emitLEApcrelJTInstruction(const MachineInstr &MI) {
768  // It's basically add r, pc, (LJTI - $+8)
769
770  const MCInstrDesc &MCID = MI.getDesc();
771
772  // Emit the 'add' instruction.
773  unsigned Binary = 0x4 << 21;  // add: Insts{24-21} = 0b0100
774
775  // Set the conditional execution predicate
776  Binary |= II->getPredicate(&MI) << ARMII::CondShift;
777
778  // Encode S bit if MI modifies CPSR.
779  Binary |= getAddrModeSBit(MI, MCID);
780
781  // Encode Rd.
782  Binary |= getMachineOpValue(MI, 0) << ARMII::RegRdShift;
783
784  // Encode Rn which is PC.
785  Binary |= II->getRegisterInfo().getEncodingValue(ARM::PC) << ARMII::RegRnShift;
786
787  // Encode the displacement.
788  Binary |= 1 << ARMII::I_BitShift;
789  emitJumpTableAddress(MI.getOperand(1).getIndex(), ARM::reloc_arm_jt_base);
790
791  emitWordLE(Binary);
792}
793
794void ARMCodeEmitter::emitPseudoMoveInstruction(const MachineInstr &MI) {
795  unsigned Opcode = MI.getDesc().Opcode;
796
797  // Part of binary is determined by TableGn.
798  unsigned Binary = getBinaryCodeForInstr(MI);
799
800  // Set the conditional execution predicate
801  Binary |= II->getPredicate(&MI) << ARMII::CondShift;
802
803  // Encode S bit if MI modifies CPSR.
804  if (Opcode == ARM::MOVsrl_flag || Opcode == ARM::MOVsra_flag)
805    Binary |= 1 << ARMII::S_BitShift;
806
807  // Encode register def if there is one.
808  Binary |= getMachineOpValue(MI, 0) << ARMII::RegRdShift;
809
810  // Encode the shift operation.
811  switch (Opcode) {
812  default: break;
813  case ARM::RRX:
814    // rrx
815    Binary |= 0x6 << 4;
816    break;
817  case ARM::MOVsrl_flag:
818    // lsr #1
819    Binary |= (0x2 << 4) | (1 << 7);
820    break;
821  case ARM::MOVsra_flag:
822    // asr #1
823    Binary |= (0x4 << 4) | (1 << 7);
824    break;
825  }
826
827  // Encode register Rm.
828  Binary |= getMachineOpValue(MI, 1);
829
830  emitWordLE(Binary);
831}
832
833void ARMCodeEmitter::addPCLabel(unsigned LabelID) {
834  DEBUG(errs() << "  ** LPC" << LabelID << " @ "
835        << (void*)MCE.getCurrentPCValue() << '\n');
836  JTI->addPCLabelAddr(LabelID, MCE.getCurrentPCValue());
837}
838
839void ARMCodeEmitter::emitPseudoInstruction(const MachineInstr &MI) {
840  unsigned Opcode = MI.getDesc().Opcode;
841  switch (Opcode) {
842  default:
843    llvm_unreachable("ARMCodeEmitter::emitPseudoInstruction");
844  case ARM::BX_CALL:
845  case ARM::BMOVPCRX_CALL: {
846    // First emit mov lr, pc
847    unsigned Binary = 0x01a0e00f;
848    Binary |= II->getPredicate(&MI) << ARMII::CondShift;
849    emitWordLE(Binary);
850
851    // and then emit the branch.
852    emitMiscBranchInstruction(MI);
853    break;
854  }
855  case TargetOpcode::INLINEASM: {
856    // We allow inline assembler nodes with empty bodies - they can
857    // implicitly define registers, which is ok for JIT.
858    if (MI.getOperand(0).getSymbolName()[0]) {
859      report_fatal_error("JIT does not support inline asm!");
860    }
861    break;
862  }
863  case TargetOpcode::PROLOG_LABEL:
864  case TargetOpcode::EH_LABEL:
865    MCE.emitLabel(MI.getOperand(0).getMCSymbol());
866    break;
867  case TargetOpcode::IMPLICIT_DEF:
868  case TargetOpcode::KILL:
869    // Do nothing.
870    break;
871  case ARM::CONSTPOOL_ENTRY:
872    emitConstPoolInstruction(MI);
873    break;
874  case ARM::PICADD: {
875    // Remember of the address of the PC label for relocation later.
876    addPCLabel(MI.getOperand(2).getImm());
877    // PICADD is just an add instruction that implicitly read pc.
878    emitDataProcessingInstruction(MI, 0, ARM::PC);
879    break;
880  }
881  case ARM::PICLDR:
882  case ARM::PICLDRB:
883  case ARM::PICSTR:
884  case ARM::PICSTRB: {
885    // Remember of the address of the PC label for relocation later.
886    addPCLabel(MI.getOperand(2).getImm());
887    // These are just load / store instructions that implicitly read pc.
888    emitLoadStoreInstruction(MI, 0, ARM::PC);
889    break;
890  }
891  case ARM::PICLDRH:
892  case ARM::PICLDRSH:
893  case ARM::PICLDRSB:
894  case ARM::PICSTRH: {
895    // Remember of the address of the PC label for relocation later.
896    addPCLabel(MI.getOperand(2).getImm());
897    // These are just load / store instructions that implicitly read pc.
898    emitMiscLoadStoreInstruction(MI, ARM::PC);
899    break;
900  }
901
902  case ARM::MOVi32imm:
903    // Two instructions to materialize a constant.
904    if (Subtarget->hasV6T2Ops())
905      emitMOVi32immInstruction(MI);
906    else
907      emitMOVi2piecesInstruction(MI);
908    break;
909
910  case ARM::LEApcrelJT:
911    // Materialize jumptable address.
912    emitLEApcrelJTInstruction(MI);
913    break;
914  case ARM::RRX:
915  case ARM::MOVsrl_flag:
916  case ARM::MOVsra_flag:
917    emitPseudoMoveInstruction(MI);
918    break;
919  }
920}
921
922unsigned ARMCodeEmitter::getMachineSoRegOpValue(const MachineInstr &MI,
923                                                const MCInstrDesc &MCID,
924                                                const MachineOperand &MO,
925                                                unsigned OpIdx) {
926  unsigned Binary = getMachineOpValue(MI, MO);
927
928  const MachineOperand &MO1 = MI.getOperand(OpIdx + 1);
929  const MachineOperand &MO2 = MI.getOperand(OpIdx + 2);
930  ARM_AM::ShiftOpc SOpc = ARM_AM::getSORegShOp(MO2.getImm());
931
932  // Encode the shift opcode.
933  unsigned SBits = 0;
934  unsigned Rs = MO1.getReg();
935  if (Rs) {
936    // Set shift operand (bit[7:4]).
937    // LSL - 0001
938    // LSR - 0011
939    // ASR - 0101
940    // ROR - 0111
941    // RRX - 0110 and bit[11:8] clear.
942    switch (SOpc) {
943    default: llvm_unreachable("Unknown shift opc!");
944    case ARM_AM::lsl: SBits = 0x1; break;
945    case ARM_AM::lsr: SBits = 0x3; break;
946    case ARM_AM::asr: SBits = 0x5; break;
947    case ARM_AM::ror: SBits = 0x7; break;
948    case ARM_AM::rrx: SBits = 0x6; break;
949    }
950  } else {
951    // Set shift operand (bit[6:4]).
952    // LSL - 000
953    // LSR - 010
954    // ASR - 100
955    // ROR - 110
956    switch (SOpc) {
957    default: llvm_unreachable("Unknown shift opc!");
958    case ARM_AM::lsl: SBits = 0x0; break;
959    case ARM_AM::lsr: SBits = 0x2; break;
960    case ARM_AM::asr: SBits = 0x4; break;
961    case ARM_AM::ror: SBits = 0x6; break;
962    }
963  }
964  Binary |= SBits << 4;
965  if (SOpc == ARM_AM::rrx)
966    return Binary;
967
968  // Encode the shift operation Rs or shift_imm (except rrx).
969  if (Rs) {
970    // Encode Rs bit[11:8].
971    assert(ARM_AM::getSORegOffset(MO2.getImm()) == 0);
972    return Binary | (II->getRegisterInfo().getEncodingValue(Rs) << ARMII::RegRsShift);
973  }
974
975  // Encode shift_imm bit[11:7].
976  return Binary | ARM_AM::getSORegOffset(MO2.getImm()) << 7;
977}
978
979unsigned ARMCodeEmitter::getMachineSoImmOpValue(unsigned SoImm) {
980  int SoImmVal = ARM_AM::getSOImmVal(SoImm);
981  assert(SoImmVal != -1 && "Not a valid so_imm value!");
982
983  // Encode rotate_imm.
984  unsigned Binary = (ARM_AM::getSOImmValRot((unsigned)SoImmVal) >> 1)
985    << ARMII::SoRotImmShift;
986
987  // Encode immed_8.
988  Binary |= ARM_AM::getSOImmValImm((unsigned)SoImmVal);
989  return Binary;
990}
991
992unsigned ARMCodeEmitter::getAddrModeSBit(const MachineInstr &MI,
993                                         const MCInstrDesc &MCID) const {
994  for (unsigned i = MI.getNumOperands(), e = MCID.getNumOperands(); i >= e;--i){
995    const MachineOperand &MO = MI.getOperand(i-1);
996    if (MO.isReg() && MO.isDef() && MO.getReg() == ARM::CPSR)
997      return 1 << ARMII::S_BitShift;
998  }
999  return 0;
1000}
1001
1002void ARMCodeEmitter::emitDataProcessingInstruction(const MachineInstr &MI,
1003                                                   unsigned ImplicitRd,
1004                                                   unsigned ImplicitRn) {
1005  const MCInstrDesc &MCID = MI.getDesc();
1006
1007  // Part of binary is determined by TableGn.
1008  unsigned Binary = getBinaryCodeForInstr(MI);
1009
1010  // Set the conditional execution predicate
1011  Binary |= II->getPredicate(&MI) << ARMII::CondShift;
1012
1013  // Encode S bit if MI modifies CPSR.
1014  Binary |= getAddrModeSBit(MI, MCID);
1015
1016  // Encode register def if there is one.
1017  unsigned NumDefs = MCID.getNumDefs();
1018  unsigned OpIdx = 0;
1019  if (NumDefs)
1020    Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRdShift;
1021  else if (ImplicitRd)
1022    // Special handling for implicit use (e.g. PC).
1023    Binary |= (II->getRegisterInfo().getEncodingValue(ImplicitRd) << ARMII::RegRdShift);
1024
1025  if (MCID.Opcode == ARM::MOVi16) {
1026      // Get immediate from MI.
1027      unsigned Lo16 = getMovi32Value(MI, MI.getOperand(OpIdx),
1028                      ARM::reloc_arm_movw);
1029      // Encode imm which is the same as in emitMOVi32immInstruction().
1030      Binary |= Lo16 & 0xFFF;
1031      Binary |= ((Lo16 >> 12) & 0xF) << 16;
1032      emitWordLE(Binary);
1033      return;
1034  } else if(MCID.Opcode == ARM::MOVTi16) {
1035      unsigned Hi16 = (getMovi32Value(MI, MI.getOperand(OpIdx),
1036                       ARM::reloc_arm_movt) >> 16);
1037      Binary |= Hi16 & 0xFFF;
1038      Binary |= ((Hi16 >> 12) & 0xF) << 16;
1039      emitWordLE(Binary);
1040      return;
1041  } else if ((MCID.Opcode == ARM::BFC) || (MCID.Opcode == ARM::BFI)) {
1042      uint32_t v = ~MI.getOperand(2).getImm();
1043      int32_t lsb = CountTrailingZeros_32(v);
1044      int32_t msb = (32 - CountLeadingZeros_32(v)) - 1;
1045      // Instr{20-16} = msb, Instr{11-7} = lsb
1046      Binary |= (msb & 0x1F) << 16;
1047      Binary |= (lsb & 0x1F) << 7;
1048      emitWordLE(Binary);
1049      return;
1050  } else if ((MCID.Opcode == ARM::UBFX) || (MCID.Opcode == ARM::SBFX)) {
1051      // Encode Rn in Instr{0-3}
1052      Binary |= getMachineOpValue(MI, OpIdx++);
1053
1054      uint32_t lsb = MI.getOperand(OpIdx++).getImm();
1055      uint32_t widthm1 = MI.getOperand(OpIdx++).getImm() - 1;
1056
1057      // Instr{20-16} = widthm1, Instr{11-7} = lsb
1058      Binary |= (widthm1 & 0x1F) << 16;
1059      Binary |= (lsb & 0x1F) << 7;
1060      emitWordLE(Binary);
1061      return;
1062  }
1063
1064  // If this is a two-address operand, skip it. e.g. MOVCCr operand 1.
1065  if (MCID.getOperandConstraint(OpIdx, MCOI::TIED_TO) != -1)
1066    ++OpIdx;
1067
1068  // Encode first non-shifter register operand if there is one.
1069  bool isUnary = MCID.TSFlags & ARMII::UnaryDP;
1070  if (!isUnary) {
1071    if (ImplicitRn)
1072      // Special handling for implicit use (e.g. PC).
1073      Binary |= (II->getRegisterInfo().getEncodingValue(ImplicitRn) << ARMII::RegRnShift);
1074    else {
1075      Binary |= getMachineOpValue(MI, OpIdx) << ARMII::RegRnShift;
1076      ++OpIdx;
1077    }
1078  }
1079
1080  // Encode shifter operand.
1081  const MachineOperand &MO = MI.getOperand(OpIdx);
1082  if ((MCID.TSFlags & ARMII::FormMask) == ARMII::DPSoRegFrm) {
1083    // Encode SoReg.
1084    emitWordLE(Binary | getMachineSoRegOpValue(MI, MCID, MO, OpIdx));
1085    return;
1086  }
1087
1088  if (MO.isReg()) {
1089    // Encode register Rm.
1090    emitWordLE(Binary | II->getRegisterInfo().getEncodingValue(MO.getReg()));
1091    return;
1092  }
1093
1094  // Encode so_imm.
1095  Binary |= getMachineSoImmOpValue((unsigned)MO.getImm());
1096
1097  emitWordLE(Binary);
1098}
1099
1100void ARMCodeEmitter::emitLoadStoreInstruction(const MachineInstr &MI,
1101                                              unsigned ImplicitRd,
1102                                              unsigned ImplicitRn) {
1103  const MCInstrDesc &MCID = MI.getDesc();
1104  unsigned Form = MCID.TSFlags & ARMII::FormMask;
1105  bool IsPrePost = (MCID.TSFlags & ARMII::IndexModeMask) != 0;
1106
1107  // Part of binary is determined by TableGn.
1108  unsigned Binary = getBinaryCodeForInstr(MI);
1109
1110  // If this is an LDRi12, STRi12 or LDRcp, nothing more needs be done.
1111  if (MI.getOpcode() == ARM::LDRi12 || MI.getOpcode() == ARM::LDRcp ||
1112      MI.getOpcode() == ARM::STRi12) {
1113    emitWordLE(Binary);
1114    return;
1115  }
1116
1117  // Set the conditional execution predicate
1118  Binary |= II->getPredicate(&MI) << ARMII::CondShift;
1119
1120  unsigned OpIdx = 0;
1121
1122  // Operand 0 of a pre- and post-indexed store is the address base
1123  // writeback. Skip it.
1124  bool Skipped = false;
1125  if (IsPrePost && Form == ARMII::StFrm) {
1126    ++OpIdx;
1127    Skipped = true;
1128  }
1129
1130  // Set first operand
1131  if (ImplicitRd)
1132    // Special handling for implicit use (e.g. PC).
1133    Binary |= (II->getRegisterInfo().getEncodingValue(ImplicitRd) << ARMII::RegRdShift);
1134  else
1135    Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRdShift;
1136
1137  // Set second operand
1138  if (ImplicitRn)
1139    // Special handling for implicit use (e.g. PC).
1140    Binary |= (II->getRegisterInfo().getEncodingValue(ImplicitRn) << ARMII::RegRnShift);
1141  else
1142    Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRnShift;
1143
1144  // If this is a two-address operand, skip it. e.g. LDR_PRE.
1145  if (!Skipped && MCID.getOperandConstraint(OpIdx, MCOI::TIED_TO) != -1)
1146    ++OpIdx;
1147
1148  const MachineOperand &MO2 = MI.getOperand(OpIdx);
1149  unsigned AM2Opc = (ImplicitRn == ARM::PC)
1150    ? 0 : MI.getOperand(OpIdx+1).getImm();
1151
1152  // Set bit U(23) according to sign of immed value (positive or negative).
1153  Binary |= ((ARM_AM::getAM2Op(AM2Opc) == ARM_AM::add ? 1 : 0) <<
1154             ARMII::U_BitShift);
1155  if (!MO2.getReg()) { // is immediate
1156    if (ARM_AM::getAM2Offset(AM2Opc))
1157      // Set the value of offset_12 field
1158      Binary |= ARM_AM::getAM2Offset(AM2Opc);
1159    emitWordLE(Binary);
1160    return;
1161  }
1162
1163  // Set bit I(25), because this is not in immediate encoding.
1164  Binary |= 1 << ARMII::I_BitShift;
1165  assert(TargetRegisterInfo::isPhysicalRegister(MO2.getReg()));
1166  // Set bit[3:0] to the corresponding Rm register
1167  Binary |= II->getRegisterInfo().getEncodingValue(MO2.getReg());
1168
1169  // If this instr is in scaled register offset/index instruction, set
1170  // shift_immed(bit[11:7]) and shift(bit[6:5]) fields.
1171  if (unsigned ShImm = ARM_AM::getAM2Offset(AM2Opc)) {
1172    Binary |= getShiftOp(AM2Opc) << ARMII::ShiftImmShift;  // shift
1173    Binary |= ShImm              << ARMII::ShiftShift;     // shift_immed
1174  }
1175
1176  emitWordLE(Binary);
1177}
1178
1179void ARMCodeEmitter::emitMiscLoadStoreInstruction(const MachineInstr &MI,
1180                                                  unsigned ImplicitRn) {
1181  const MCInstrDesc &MCID = MI.getDesc();
1182  unsigned Form = MCID.TSFlags & ARMII::FormMask;
1183  bool IsPrePost = (MCID.TSFlags & ARMII::IndexModeMask) != 0;
1184
1185  // Part of binary is determined by TableGn.
1186  unsigned Binary = getBinaryCodeForInstr(MI);
1187
1188  // Set the conditional execution predicate
1189  Binary |= II->getPredicate(&MI) << ARMII::CondShift;
1190
1191  unsigned OpIdx = 0;
1192
1193  // Operand 0 of a pre- and post-indexed store is the address base
1194  // writeback. Skip it.
1195  bool Skipped = false;
1196  if (IsPrePost && Form == ARMII::StMiscFrm) {
1197    ++OpIdx;
1198    Skipped = true;
1199  }
1200
1201  // Set first operand
1202  Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRdShift;
1203
1204  // Skip LDRD and STRD's second operand.
1205  if (MCID.Opcode == ARM::LDRD || MCID.Opcode == ARM::STRD)
1206    ++OpIdx;
1207
1208  // Set second operand
1209  if (ImplicitRn)
1210    // Special handling for implicit use (e.g. PC).
1211    Binary |= (II->getRegisterInfo().getEncodingValue(ImplicitRn) << ARMII::RegRnShift);
1212  else
1213    Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRnShift;
1214
1215  // If this is a two-address operand, skip it. e.g. LDRH_POST.
1216  if (!Skipped && MCID.getOperandConstraint(OpIdx, MCOI::TIED_TO) != -1)
1217    ++OpIdx;
1218
1219  const MachineOperand &MO2 = MI.getOperand(OpIdx);
1220  unsigned AM3Opc = (ImplicitRn == ARM::PC)
1221    ? 0 : MI.getOperand(OpIdx+1).getImm();
1222
1223  // Set bit U(23) according to sign of immed value (positive or negative)
1224  Binary |= ((ARM_AM::getAM3Op(AM3Opc) == ARM_AM::add ? 1 : 0) <<
1225             ARMII::U_BitShift);
1226
1227  // If this instr is in register offset/index encoding, set bit[3:0]
1228  // to the corresponding Rm register.
1229  if (MO2.getReg()) {
1230    Binary |= II->getRegisterInfo().getEncodingValue(MO2.getReg());
1231    emitWordLE(Binary);
1232    return;
1233  }
1234
1235  // This instr is in immediate offset/index encoding, set bit 22 to 1.
1236  Binary |= 1 << ARMII::AM3_I_BitShift;
1237  if (unsigned ImmOffs = ARM_AM::getAM3Offset(AM3Opc)) {
1238    // Set operands
1239    Binary |= (ImmOffs >> 4) << ARMII::ImmHiShift;  // immedH
1240    Binary |= (ImmOffs & 0xF);                      // immedL
1241  }
1242
1243  emitWordLE(Binary);
1244}
1245
1246static unsigned getAddrModeUPBits(unsigned Mode) {
1247  unsigned Binary = 0;
1248
1249  // Set addressing mode by modifying bits U(23) and P(24)
1250  // IA - Increment after  - bit U = 1 and bit P = 0
1251  // IB - Increment before - bit U = 1 and bit P = 1
1252  // DA - Decrement after  - bit U = 0 and bit P = 0
1253  // DB - Decrement before - bit U = 0 and bit P = 1
1254  switch (Mode) {
1255  default: llvm_unreachable("Unknown addressing sub-mode!");
1256  case ARM_AM::da:                                     break;
1257  case ARM_AM::db: Binary |= 0x1 << ARMII::P_BitShift; break;
1258  case ARM_AM::ia: Binary |= 0x1 << ARMII::U_BitShift; break;
1259  case ARM_AM::ib: Binary |= 0x3 << ARMII::U_BitShift; break;
1260  }
1261
1262  return Binary;
1263}
1264
1265void ARMCodeEmitter::emitLoadStoreMultipleInstruction(const MachineInstr &MI) {
1266  const MCInstrDesc &MCID = MI.getDesc();
1267  bool IsUpdating = (MCID.TSFlags & ARMII::IndexModeMask) != 0;
1268
1269  // Part of binary is determined by TableGn.
1270  unsigned Binary = getBinaryCodeForInstr(MI);
1271
1272  // Set the conditional execution predicate
1273  Binary |= II->getPredicate(&MI) << ARMII::CondShift;
1274
1275  // Skip operand 0 of an instruction with base register update.
1276  unsigned OpIdx = 0;
1277  if (IsUpdating)
1278    ++OpIdx;
1279
1280  // Set base address operand
1281  Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRnShift;
1282
1283  // Set addressing mode by modifying bits U(23) and P(24)
1284  ARM_AM::AMSubMode Mode = ARM_AM::getLoadStoreMultipleSubMode(MI.getOpcode());
1285  Binary |= getAddrModeUPBits(ARM_AM::getAM4SubMode(Mode));
1286
1287  // Set bit W(21)
1288  if (IsUpdating)
1289    Binary |= 0x1 << ARMII::W_BitShift;
1290
1291  // Set registers
1292  for (unsigned i = OpIdx+2, e = MI.getNumOperands(); i != e; ++i) {
1293    const MachineOperand &MO = MI.getOperand(i);
1294    if (!MO.isReg() || MO.isImplicit())
1295      break;
1296    unsigned RegNum = II->getRegisterInfo().getEncodingValue(MO.getReg());
1297    assert(TargetRegisterInfo::isPhysicalRegister(MO.getReg()) &&
1298           RegNum < 16);
1299    Binary |= 0x1 << RegNum;
1300  }
1301
1302  emitWordLE(Binary);
1303}
1304
1305void ARMCodeEmitter::emitMulFrmInstruction(const MachineInstr &MI) {
1306  const MCInstrDesc &MCID = MI.getDesc();
1307
1308  // Part of binary is determined by TableGn.
1309  unsigned Binary = getBinaryCodeForInstr(MI);
1310
1311  // Set the conditional execution predicate
1312  Binary |= II->getPredicate(&MI) << ARMII::CondShift;
1313
1314  // Encode S bit if MI modifies CPSR.
1315  Binary |= getAddrModeSBit(MI, MCID);
1316
1317  // 32x32->64bit operations have two destination registers. The number
1318  // of register definitions will tell us if that's what we're dealing with.
1319  unsigned OpIdx = 0;
1320  if (MCID.getNumDefs() == 2)
1321    Binary |= getMachineOpValue (MI, OpIdx++) << ARMII::RegRdLoShift;
1322
1323  // Encode Rd
1324  Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRdHiShift;
1325
1326  // Encode Rm
1327  Binary |= getMachineOpValue(MI, OpIdx++);
1328
1329  // Encode Rs
1330  Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRsShift;
1331
1332  // Many multiple instructions (e.g. MLA) have three src operands. Encode
1333  // it as Rn (for multiply, that's in the same offset as RdLo.
1334  if (MCID.getNumOperands() > OpIdx &&
1335      !MCID.OpInfo[OpIdx].isPredicate() &&
1336      !MCID.OpInfo[OpIdx].isOptionalDef())
1337    Binary |= getMachineOpValue(MI, OpIdx) << ARMII::RegRdLoShift;
1338
1339  emitWordLE(Binary);
1340}
1341
1342void ARMCodeEmitter::emitExtendInstruction(const MachineInstr &MI) {
1343  const MCInstrDesc &MCID = MI.getDesc();
1344
1345  // Part of binary is determined by TableGn.
1346  unsigned Binary = getBinaryCodeForInstr(MI);
1347
1348  // Set the conditional execution predicate
1349  Binary |= II->getPredicate(&MI) << ARMII::CondShift;
1350
1351  unsigned OpIdx = 0;
1352
1353  // Encode Rd
1354  Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRdShift;
1355
1356  const MachineOperand &MO1 = MI.getOperand(OpIdx++);
1357  const MachineOperand &MO2 = MI.getOperand(OpIdx);
1358  if (MO2.isReg()) {
1359    // Two register operand form.
1360    // Encode Rn.
1361    Binary |= getMachineOpValue(MI, MO1) << ARMII::RegRnShift;
1362
1363    // Encode Rm.
1364    Binary |= getMachineOpValue(MI, MO2);
1365    ++OpIdx;
1366  } else {
1367    Binary |= getMachineOpValue(MI, MO1);
1368  }
1369
1370  // Encode rot imm (0, 8, 16, or 24) if it has a rotate immediate operand.
1371  if (MI.getOperand(OpIdx).isImm() &&
1372      !MCID.OpInfo[OpIdx].isPredicate() &&
1373      !MCID.OpInfo[OpIdx].isOptionalDef())
1374    Binary |= (getMachineOpValue(MI, OpIdx) / 8) << ARMII::ExtRotImmShift;
1375
1376  emitWordLE(Binary);
1377}
1378
1379void ARMCodeEmitter::emitMiscArithInstruction(const MachineInstr &MI) {
1380  const MCInstrDesc &MCID = MI.getDesc();
1381
1382  // Part of binary is determined by TableGn.
1383  unsigned Binary = getBinaryCodeForInstr(MI);
1384
1385  // Set the conditional execution predicate
1386  Binary |= II->getPredicate(&MI) << ARMII::CondShift;
1387
1388  // PKH instructions are finished at this point
1389  if (MCID.Opcode == ARM::PKHBT || MCID.Opcode == ARM::PKHTB) {
1390    emitWordLE(Binary);
1391    return;
1392  }
1393
1394  unsigned OpIdx = 0;
1395
1396  // Encode Rd
1397  Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRdShift;
1398
1399  const MachineOperand &MO = MI.getOperand(OpIdx++);
1400  if (OpIdx == MCID.getNumOperands() ||
1401      MCID.OpInfo[OpIdx].isPredicate() ||
1402      MCID.OpInfo[OpIdx].isOptionalDef()) {
1403    // Encode Rm and it's done.
1404    Binary |= getMachineOpValue(MI, MO);
1405    emitWordLE(Binary);
1406    return;
1407  }
1408
1409  // Encode Rn.
1410  Binary |= getMachineOpValue(MI, MO) << ARMII::RegRnShift;
1411
1412  // Encode Rm.
1413  Binary |= getMachineOpValue(MI, OpIdx++);
1414
1415  // Encode shift_imm.
1416  unsigned ShiftAmt = MI.getOperand(OpIdx).getImm();
1417  if (MCID.Opcode == ARM::PKHTB) {
1418    assert(ShiftAmt != 0 && "PKHTB shift_imm is 0!");
1419    if (ShiftAmt == 32)
1420      ShiftAmt = 0;
1421  }
1422  assert(ShiftAmt < 32 && "shift_imm range is 0 to 31!");
1423  Binary |= ShiftAmt << ARMII::ShiftShift;
1424
1425  emitWordLE(Binary);
1426}
1427
1428void ARMCodeEmitter::emitSaturateInstruction(const MachineInstr &MI) {
1429  const MCInstrDesc &MCID = MI.getDesc();
1430
1431  // Part of binary is determined by TableGen.
1432  unsigned Binary = getBinaryCodeForInstr(MI);
1433
1434  // Set the conditional execution predicate
1435  Binary |= II->getPredicate(&MI) << ARMII::CondShift;
1436
1437  // Encode Rd
1438  Binary |= getMachineOpValue(MI, 0) << ARMII::RegRdShift;
1439
1440  // Encode saturate bit position.
1441  unsigned Pos = MI.getOperand(1).getImm();
1442  if (MCID.Opcode == ARM::SSAT || MCID.Opcode == ARM::SSAT16)
1443    Pos -= 1;
1444  assert((Pos < 16 || (Pos < 32 &&
1445                       MCID.Opcode != ARM::SSAT16 &&
1446                       MCID.Opcode != ARM::USAT16)) &&
1447         "saturate bit position out of range");
1448  Binary |= Pos << 16;
1449
1450  // Encode Rm
1451  Binary |= getMachineOpValue(MI, 2);
1452
1453  // Encode shift_imm.
1454  if (MCID.getNumOperands() == 4) {
1455    unsigned ShiftOp = MI.getOperand(3).getImm();
1456    ARM_AM::ShiftOpc Opc = ARM_AM::getSORegShOp(ShiftOp);
1457    if (Opc == ARM_AM::asr)
1458      Binary |= (1 << 6);
1459    unsigned ShiftAmt = MI.getOperand(3).getImm();
1460    if (ShiftAmt == 32 && Opc == ARM_AM::asr)
1461      ShiftAmt = 0;
1462    assert(ShiftAmt < 32 && "shift_imm range is 0 to 31!");
1463    Binary |= ShiftAmt << ARMII::ShiftShift;
1464  }
1465
1466  emitWordLE(Binary);
1467}
1468
1469void ARMCodeEmitter::emitBranchInstruction(const MachineInstr &MI) {
1470  const MCInstrDesc &MCID = MI.getDesc();
1471
1472  if (MCID.Opcode == ARM::TPsoft) {
1473    llvm_unreachable("ARM::TPsoft FIXME"); // FIXME
1474  }
1475
1476  // Part of binary is determined by TableGn.
1477  unsigned Binary = getBinaryCodeForInstr(MI);
1478
1479  // Set the conditional execution predicate
1480  Binary |= II->getPredicate(&MI) << ARMII::CondShift;
1481
1482  // Set signed_immed_24 field
1483  Binary |= getMachineOpValue(MI, 0);
1484
1485  emitWordLE(Binary);
1486}
1487
1488void ARMCodeEmitter::emitInlineJumpTable(unsigned JTIndex) {
1489  // Remember the base address of the inline jump table.
1490  uintptr_t JTBase = MCE.getCurrentPCValue();
1491  JTI->addJumpTableBaseAddr(JTIndex, JTBase);
1492  DEBUG(errs() << "  ** Jump Table #" << JTIndex << " @ " << (void*)JTBase
1493               << '\n');
1494
1495  // Now emit the jump table entries.
1496  const std::vector<MachineBasicBlock*> &MBBs = (*MJTEs)[JTIndex].MBBs;
1497  for (unsigned i = 0, e = MBBs.size(); i != e; ++i) {
1498    if (IsPIC)
1499      // DestBB address - JT base.
1500      emitMachineBasicBlock(MBBs[i], ARM::reloc_arm_pic_jt, JTBase);
1501    else
1502      // Absolute DestBB address.
1503      emitMachineBasicBlock(MBBs[i], ARM::reloc_arm_absolute);
1504    emitWordLE(0);
1505  }
1506}
1507
1508void ARMCodeEmitter::emitMiscBranchInstruction(const MachineInstr &MI) {
1509  const MCInstrDesc &MCID = MI.getDesc();
1510
1511  // Handle jump tables.
1512  if (MCID.Opcode == ARM::BR_JTr || MCID.Opcode == ARM::BR_JTadd) {
1513    // First emit a ldr pc, [] instruction.
1514    emitDataProcessingInstruction(MI, ARM::PC);
1515
1516    // Then emit the inline jump table.
1517    unsigned JTIndex =
1518      (MCID.Opcode == ARM::BR_JTr)
1519      ? MI.getOperand(1).getIndex() : MI.getOperand(2).getIndex();
1520    emitInlineJumpTable(JTIndex);
1521    return;
1522  } else if (MCID.Opcode == ARM::BR_JTm) {
1523    // First emit a ldr pc, [] instruction.
1524    emitLoadStoreInstruction(MI, ARM::PC);
1525
1526    // Then emit the inline jump table.
1527    emitInlineJumpTable(MI.getOperand(3).getIndex());
1528    return;
1529  }
1530
1531  // Part of binary is determined by TableGn.
1532  unsigned Binary = getBinaryCodeForInstr(MI);
1533
1534  // Set the conditional execution predicate
1535  Binary |= II->getPredicate(&MI) << ARMII::CondShift;
1536
1537  if (MCID.Opcode == ARM::BX_RET || MCID.Opcode == ARM::MOVPCLR)
1538    // The return register is LR.
1539    Binary |= II->getRegisterInfo().getEncodingValue(ARM::LR);
1540  else
1541    // otherwise, set the return register
1542    Binary |= getMachineOpValue(MI, 0);
1543
1544  emitWordLE(Binary);
1545}
1546
1547unsigned ARMCodeEmitter::encodeVFPRd(const MachineInstr &MI,
1548                                     unsigned OpIdx) const {
1549  unsigned RegD = MI.getOperand(OpIdx).getReg();
1550  unsigned Binary = 0;
1551  bool isSPVFP = ARM::SPRRegClass.contains(RegD);
1552  RegD = II->getRegisterInfo().getEncodingValue(RegD);
1553  if (!isSPVFP)
1554    Binary |=   RegD               << ARMII::RegRdShift;
1555  else {
1556    Binary |= ((RegD & 0x1E) >> 1) << ARMII::RegRdShift;
1557    Binary |=  (RegD & 0x01)       << ARMII::D_BitShift;
1558  }
1559  return Binary;
1560}
1561
1562unsigned ARMCodeEmitter::encodeVFPRn(const MachineInstr &MI,
1563                                     unsigned OpIdx) const {
1564  unsigned RegN = MI.getOperand(OpIdx).getReg();
1565  unsigned Binary = 0;
1566  bool isSPVFP = ARM::SPRRegClass.contains(RegN);
1567  RegN = II->getRegisterInfo().getEncodingValue(RegN);
1568  if (!isSPVFP)
1569    Binary |=   RegN               << ARMII::RegRnShift;
1570  else {
1571    Binary |= ((RegN & 0x1E) >> 1) << ARMII::RegRnShift;
1572    Binary |=  (RegN & 0x01)       << ARMII::N_BitShift;
1573  }
1574  return Binary;
1575}
1576
1577unsigned ARMCodeEmitter::encodeVFPRm(const MachineInstr &MI,
1578                                     unsigned OpIdx) const {
1579  unsigned RegM = MI.getOperand(OpIdx).getReg();
1580  unsigned Binary = 0;
1581  bool isSPVFP = ARM::SPRRegClass.contains(RegM);
1582  RegM = II->getRegisterInfo().getEncodingValue(RegM);
1583  if (!isSPVFP)
1584    Binary |=   RegM;
1585  else {
1586    Binary |= ((RegM & 0x1E) >> 1);
1587    Binary |=  (RegM & 0x01)       << ARMII::M_BitShift;
1588  }
1589  return Binary;
1590}
1591
1592void ARMCodeEmitter::emitVFPArithInstruction(const MachineInstr &MI) {
1593  const MCInstrDesc &MCID = MI.getDesc();
1594
1595  // Part of binary is determined by TableGn.
1596  unsigned Binary = getBinaryCodeForInstr(MI);
1597
1598  // Set the conditional execution predicate
1599  Binary |= II->getPredicate(&MI) << ARMII::CondShift;
1600
1601  unsigned OpIdx = 0;
1602  assert((Binary & ARMII::D_BitShift) == 0 &&
1603         (Binary & ARMII::N_BitShift) == 0 &&
1604         (Binary & ARMII::M_BitShift) == 0 && "VFP encoding bug!");
1605
1606  // Encode Dd / Sd.
1607  Binary |= encodeVFPRd(MI, OpIdx++);
1608
1609  // If this is a two-address operand, skip it, e.g. FMACD.
1610  if (MCID.getOperandConstraint(OpIdx, MCOI::TIED_TO) != -1)
1611    ++OpIdx;
1612
1613  // Encode Dn / Sn.
1614  if ((MCID.TSFlags & ARMII::FormMask) == ARMII::VFPBinaryFrm)
1615    Binary |= encodeVFPRn(MI, OpIdx++);
1616
1617  if (OpIdx == MCID.getNumOperands() ||
1618      MCID.OpInfo[OpIdx].isPredicate() ||
1619      MCID.OpInfo[OpIdx].isOptionalDef()) {
1620    // FCMPEZD etc. has only one operand.
1621    emitWordLE(Binary);
1622    return;
1623  }
1624
1625  // Encode Dm / Sm.
1626  Binary |= encodeVFPRm(MI, OpIdx);
1627
1628  emitWordLE(Binary);
1629}
1630
1631void ARMCodeEmitter::emitVFPConversionInstruction(const MachineInstr &MI) {
1632  const MCInstrDesc &MCID = MI.getDesc();
1633  unsigned Form = MCID.TSFlags & ARMII::FormMask;
1634
1635  // Part of binary is determined by TableGn.
1636  unsigned Binary = getBinaryCodeForInstr(MI);
1637
1638  // Set the conditional execution predicate
1639  Binary |= II->getPredicate(&MI) << ARMII::CondShift;
1640
1641  switch (Form) {
1642  default: break;
1643  case ARMII::VFPConv1Frm:
1644  case ARMII::VFPConv2Frm:
1645  case ARMII::VFPConv3Frm:
1646    // Encode Dd / Sd.
1647    Binary |= encodeVFPRd(MI, 0);
1648    break;
1649  case ARMII::VFPConv4Frm:
1650    // Encode Dn / Sn.
1651    Binary |= encodeVFPRn(MI, 0);
1652    break;
1653  case ARMII::VFPConv5Frm:
1654    // Encode Dm / Sm.
1655    Binary |= encodeVFPRm(MI, 0);
1656    break;
1657  }
1658
1659  switch (Form) {
1660  default: break;
1661  case ARMII::VFPConv1Frm:
1662    // Encode Dm / Sm.
1663    Binary |= encodeVFPRm(MI, 1);
1664    break;
1665  case ARMII::VFPConv2Frm:
1666  case ARMII::VFPConv3Frm:
1667    // Encode Dn / Sn.
1668    Binary |= encodeVFPRn(MI, 1);
1669    break;
1670  case ARMII::VFPConv4Frm:
1671  case ARMII::VFPConv5Frm:
1672    // Encode Dd / Sd.
1673    Binary |= encodeVFPRd(MI, 1);
1674    break;
1675  }
1676
1677  if (Form == ARMII::VFPConv5Frm)
1678    // Encode Dn / Sn.
1679    Binary |= encodeVFPRn(MI, 2);
1680  else if (Form == ARMII::VFPConv3Frm)
1681    // Encode Dm / Sm.
1682    Binary |= encodeVFPRm(MI, 2);
1683
1684  emitWordLE(Binary);
1685}
1686
1687void ARMCodeEmitter::emitVFPLoadStoreInstruction(const MachineInstr &MI) {
1688  // Part of binary is determined by TableGn.
1689  unsigned Binary = getBinaryCodeForInstr(MI);
1690
1691  // Set the conditional execution predicate
1692  Binary |= II->getPredicate(&MI) << ARMII::CondShift;
1693
1694  unsigned OpIdx = 0;
1695
1696  // Encode Dd / Sd.
1697  Binary |= encodeVFPRd(MI, OpIdx++);
1698
1699  // Encode address base.
1700  const MachineOperand &Base = MI.getOperand(OpIdx++);
1701  Binary |= getMachineOpValue(MI, Base) << ARMII::RegRnShift;
1702
1703  // If there is a non-zero immediate offset, encode it.
1704  if (Base.isReg()) {
1705    const MachineOperand &Offset = MI.getOperand(OpIdx);
1706    if (unsigned ImmOffs = ARM_AM::getAM5Offset(Offset.getImm())) {
1707      if (ARM_AM::getAM5Op(Offset.getImm()) == ARM_AM::add)
1708        Binary |= 1 << ARMII::U_BitShift;
1709      Binary |= ImmOffs;
1710      emitWordLE(Binary);
1711      return;
1712    }
1713  }
1714
1715  // If immediate offset is omitted, default to +0.
1716  Binary |= 1 << ARMII::U_BitShift;
1717
1718  emitWordLE(Binary);
1719}
1720
1721void
1722ARMCodeEmitter::emitVFPLoadStoreMultipleInstruction(const MachineInstr &MI) {
1723  const MCInstrDesc &MCID = MI.getDesc();
1724  bool IsUpdating = (MCID.TSFlags & ARMII::IndexModeMask) != 0;
1725
1726  // Part of binary is determined by TableGn.
1727  unsigned Binary = getBinaryCodeForInstr(MI);
1728
1729  // Set the conditional execution predicate
1730  Binary |= II->getPredicate(&MI) << ARMII::CondShift;
1731
1732  // Skip operand 0 of an instruction with base register update.
1733  unsigned OpIdx = 0;
1734  if (IsUpdating)
1735    ++OpIdx;
1736
1737  // Set base address operand
1738  Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRnShift;
1739
1740  // Set addressing mode by modifying bits U(23) and P(24)
1741  ARM_AM::AMSubMode Mode = ARM_AM::getLoadStoreMultipleSubMode(MI.getOpcode());
1742  Binary |= getAddrModeUPBits(ARM_AM::getAM4SubMode(Mode));
1743
1744  // Set bit W(21)
1745  if (IsUpdating)
1746    Binary |= 0x1 << ARMII::W_BitShift;
1747
1748  // First register is encoded in Dd.
1749  Binary |= encodeVFPRd(MI, OpIdx+2);
1750
1751  // Count the number of registers.
1752  unsigned NumRegs = 1;
1753  for (unsigned i = OpIdx+3, e = MI.getNumOperands(); i != e; ++i) {
1754    const MachineOperand &MO = MI.getOperand(i);
1755    if (!MO.isReg() || MO.isImplicit())
1756      break;
1757    ++NumRegs;
1758  }
1759  // Bit 8 will be set if <list> is consecutive 64-bit registers (e.g., D0)
1760  // Otherwise, it will be 0, in the case of 32-bit registers.
1761  if(Binary & 0x100)
1762    Binary |= NumRegs * 2;
1763  else
1764    Binary |= NumRegs;
1765
1766  emitWordLE(Binary);
1767}
1768
1769unsigned ARMCodeEmitter::encodeNEONRd(const MachineInstr &MI,
1770                                      unsigned OpIdx) const {
1771  unsigned RegD = MI.getOperand(OpIdx).getReg();
1772  unsigned Binary = 0;
1773  RegD = II->getRegisterInfo().getEncodingValue(RegD);
1774  Binary |= (RegD & 0xf) << ARMII::RegRdShift;
1775  Binary |= ((RegD >> 4) & 1) << ARMII::D_BitShift;
1776  return Binary;
1777}
1778
1779unsigned ARMCodeEmitter::encodeNEONRn(const MachineInstr &MI,
1780                                      unsigned OpIdx) const {
1781  unsigned RegN = MI.getOperand(OpIdx).getReg();
1782  unsigned Binary = 0;
1783  RegN = II->getRegisterInfo().getEncodingValue(RegN);
1784  Binary |= (RegN & 0xf) << ARMII::RegRnShift;
1785  Binary |= ((RegN >> 4) & 1) << ARMII::N_BitShift;
1786  return Binary;
1787}
1788
1789unsigned ARMCodeEmitter::encodeNEONRm(const MachineInstr &MI,
1790                                      unsigned OpIdx) const {
1791  unsigned RegM = MI.getOperand(OpIdx).getReg();
1792  unsigned Binary = 0;
1793  RegM = II->getRegisterInfo().getEncodingValue(RegM);
1794  Binary |= (RegM & 0xf);
1795  Binary |= ((RegM >> 4) & 1) << ARMII::M_BitShift;
1796  return Binary;
1797}
1798
1799/// convertNEONDataProcToThumb - Convert the ARM mode encoding for a NEON
1800/// data-processing instruction to the corresponding Thumb encoding.
1801static unsigned convertNEONDataProcToThumb(unsigned Binary) {
1802  assert((Binary & 0xfe000000) == 0xf2000000 &&
1803         "not an ARM NEON data-processing instruction");
1804  unsigned UBit = (Binary >> 24) & 1;
1805  return 0xef000000 | (UBit << 28) | (Binary & 0xffffff);
1806}
1807
1808void ARMCodeEmitter::emitNEONLaneInstruction(const MachineInstr &MI) {
1809  unsigned Binary = getBinaryCodeForInstr(MI);
1810
1811  unsigned RegTOpIdx, RegNOpIdx, LnOpIdx;
1812  const MCInstrDesc &MCID = MI.getDesc();
1813  if ((MCID.TSFlags & ARMII::FormMask) == ARMII::NGetLnFrm) {
1814    RegTOpIdx = 0;
1815    RegNOpIdx = 1;
1816    LnOpIdx = 2;
1817  } else { // ARMII::NSetLnFrm
1818    RegTOpIdx = 2;
1819    RegNOpIdx = 0;
1820    LnOpIdx = 3;
1821  }
1822
1823  // Set the conditional execution predicate
1824  Binary |= (IsThumb ? ARMCC::AL : II->getPredicate(&MI)) << ARMII::CondShift;
1825
1826  unsigned RegT = MI.getOperand(RegTOpIdx).getReg();
1827  RegT = II->getRegisterInfo().getEncodingValue(RegT);
1828  Binary |= (RegT << ARMII::RegRdShift);
1829  Binary |= encodeNEONRn(MI, RegNOpIdx);
1830
1831  unsigned LaneShift;
1832  if ((Binary & (1 << 22)) != 0)
1833    LaneShift = 0; // 8-bit elements
1834  else if ((Binary & (1 << 5)) != 0)
1835    LaneShift = 1; // 16-bit elements
1836  else
1837    LaneShift = 2; // 32-bit elements
1838
1839  unsigned Lane = MI.getOperand(LnOpIdx).getImm() << LaneShift;
1840  unsigned Opc1 = Lane >> 2;
1841  unsigned Opc2 = Lane & 3;
1842  assert((Opc1 & 3) == 0 && "out-of-range lane number operand");
1843  Binary |= (Opc1 << 21);
1844  Binary |= (Opc2 << 5);
1845
1846  emitWordLE(Binary);
1847}
1848
1849void ARMCodeEmitter::emitNEONDupInstruction(const MachineInstr &MI) {
1850  unsigned Binary = getBinaryCodeForInstr(MI);
1851
1852  // Set the conditional execution predicate
1853  Binary |= (IsThumb ? ARMCC::AL : II->getPredicate(&MI)) << ARMII::CondShift;
1854
1855  unsigned RegT = MI.getOperand(1).getReg();
1856  RegT = II->getRegisterInfo().getEncodingValue(RegT);
1857  Binary |= (RegT << ARMII::RegRdShift);
1858  Binary |= encodeNEONRn(MI, 0);
1859  emitWordLE(Binary);
1860}
1861
1862void ARMCodeEmitter::emitNEON1RegModImmInstruction(const MachineInstr &MI) {
1863  unsigned Binary = getBinaryCodeForInstr(MI);
1864  // Destination register is encoded in Dd.
1865  Binary |= encodeNEONRd(MI, 0);
1866  // Immediate fields: Op, Cmode, I, Imm3, Imm4
1867  unsigned Imm = MI.getOperand(1).getImm();
1868  unsigned Op = (Imm >> 12) & 1;
1869  unsigned Cmode = (Imm >> 8) & 0xf;
1870  unsigned I = (Imm >> 7) & 1;
1871  unsigned Imm3 = (Imm >> 4) & 0x7;
1872  unsigned Imm4 = Imm & 0xf;
1873  Binary |= (I << 24) | (Imm3 << 16) | (Cmode << 8) | (Op << 5) | Imm4;
1874  if (IsThumb)
1875    Binary = convertNEONDataProcToThumb(Binary);
1876  emitWordLE(Binary);
1877}
1878
1879void ARMCodeEmitter::emitNEON2RegInstruction(const MachineInstr &MI) {
1880  const MCInstrDesc &MCID = MI.getDesc();
1881  unsigned Binary = getBinaryCodeForInstr(MI);
1882  // Destination register is encoded in Dd; source register in Dm.
1883  unsigned OpIdx = 0;
1884  Binary |= encodeNEONRd(MI, OpIdx++);
1885  if (MCID.getOperandConstraint(OpIdx, MCOI::TIED_TO) != -1)
1886    ++OpIdx;
1887  Binary |= encodeNEONRm(MI, OpIdx);
1888  if (IsThumb)
1889    Binary = convertNEONDataProcToThumb(Binary);
1890  // FIXME: This does not handle VDUPfdf or VDUPfqf.
1891  emitWordLE(Binary);
1892}
1893
1894void ARMCodeEmitter::emitNEON3RegInstruction(const MachineInstr &MI) {
1895  const MCInstrDesc &MCID = MI.getDesc();
1896  unsigned Binary = getBinaryCodeForInstr(MI);
1897  // Destination register is encoded in Dd; source registers in Dn and Dm.
1898  unsigned OpIdx = 0;
1899  Binary |= encodeNEONRd(MI, OpIdx++);
1900  if (MCID.getOperandConstraint(OpIdx, MCOI::TIED_TO) != -1)
1901    ++OpIdx;
1902  Binary |= encodeNEONRn(MI, OpIdx++);
1903  if (MCID.getOperandConstraint(OpIdx, MCOI::TIED_TO) != -1)
1904    ++OpIdx;
1905  Binary |= encodeNEONRm(MI, OpIdx);
1906  if (IsThumb)
1907    Binary = convertNEONDataProcToThumb(Binary);
1908  // FIXME: This does not handle VMOVDneon or VMOVQ.
1909  emitWordLE(Binary);
1910}
1911
1912#include "ARMGenCodeEmitter.inc"
1913