ARMCodeEmitter.cpp revision e4e4ed3b56f63e9343e01bf0b2ecd7c1f45d296c 
1//===-- ARM/ARMCodeEmitter.cpp - Convert ARM code to machine code ---------===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file contains the pass that transforms the ARM machine instructions into
11// relocatable machine code.
12//
13//===----------------------------------------------------------------------===//
14
15#define DEBUG_TYPE "jit"
16#include "ARM.h"
17#include "ARMAddressingModes.h"
18#include "ARMConstantPoolValue.h"
19#include "ARMInstrInfo.h"
20#include "ARMRelocations.h"
21#include "ARMSubtarget.h"
22#include "ARMTargetMachine.h"
23#include "llvm/Constants.h"
24#include "llvm/DerivedTypes.h"
25#include "llvm/Function.h"
26#include "llvm/PassManager.h"
27#include "llvm/CodeGen/MachineCodeEmitter.h"
28#include "llvm/CodeGen/JITCodeEmitter.h"
29#include "llvm/CodeGen/ObjectCodeEmitter.h"
30#include "llvm/CodeGen/MachineConstantPool.h"
31#include "llvm/CodeGen/MachineFunctionPass.h"
32#include "llvm/CodeGen/MachineInstr.h"
33#include "llvm/CodeGen/MachineJumpTableInfo.h"
34#include "llvm/CodeGen/Passes.h"
35#include "llvm/ADT/Statistic.h"
36#include "llvm/Support/Compiler.h"
37#include "llvm/Support/Debug.h"
38#include "llvm/Support/ErrorHandling.h"
39#include "llvm/Support/raw_ostream.h"
40#ifndef NDEBUG
41#include <iomanip>
42#endif
43using namespace llvm;
44
45STATISTIC(NumEmitted, "Number of machine instructions emitted");
46
47namespace {
48
49  class ARMCodeEmitter {
50  public:
51    /// getBinaryCodeForInstr - This function, generated by the
52    /// CodeEmitterGenerator using TableGen, produces the binary encoding for
53    /// machine instructions.
54    unsigned getBinaryCodeForInstr(const MachineInstr &MI);
55  };
56
57  template<class CodeEmitter>
58  class VISIBILITY_HIDDEN Emitter : public MachineFunctionPass,
59                                    public ARMCodeEmitter {
60    ARMJITInfo                *JTI;
61    const ARMInstrInfo        *II;
62    const TargetData          *TD;
63    TargetMachine             &TM;
64    CodeEmitter               &MCE;
65    const std::vector<MachineConstantPoolEntry> *MCPEs;
66    const std::vector<MachineJumpTableEntry> *MJTEs;
67    bool IsPIC;
68
69  public:
70    static char ID;
71    explicit Emitter(TargetMachine &tm, CodeEmitter &mce)
72      : MachineFunctionPass(&ID), JTI(0), II(0), TD(0), TM(tm),
73      MCE(mce), MCPEs(0), MJTEs(0),
74      IsPIC(TM.getRelocationModel() == Reloc::PIC_) {}
75    Emitter(TargetMachine &tm, CodeEmitter &mce,
76            const ARMInstrInfo &ii, const TargetData &td)
77      : MachineFunctionPass(&ID), JTI(0), II(&ii), TD(&td), TM(tm),
78      MCE(mce), MCPEs(0), MJTEs(0),
79      IsPIC(TM.getRelocationModel() == Reloc::PIC_) {}
80
81    bool runOnMachineFunction(MachineFunction &MF);
82
83    virtual const char *getPassName() const {
84      return "ARM Machine Code Emitter";
85    }
86
87    void emitInstruction(const MachineInstr &MI);
88
89  private:
90
91    void emitWordLE(unsigned Binary);
92
93    void emitDWordLE(uint64_t Binary);
94
95    void emitConstPoolInstruction(const MachineInstr &MI);
96
97    void emitMOVi2piecesInstruction(const MachineInstr &MI);
98
99    void emitLEApcrelJTInstruction(const MachineInstr &MI);
100
101    void emitPseudoMoveInstruction(const MachineInstr &MI);
102
103    void addPCLabel(unsigned LabelID);
104
105    void emitPseudoInstruction(const MachineInstr &MI);
106
107    unsigned getMachineSoRegOpValue(const MachineInstr &MI,
108                                    const TargetInstrDesc &TID,
109                                    const MachineOperand &MO,
110                                    unsigned OpIdx);
111
112    unsigned getMachineSoImmOpValue(unsigned SoImm);
113
114    unsigned getAddrModeSBit(const MachineInstr &MI,
115                             const TargetInstrDesc &TID) const;
116
117    void emitDataProcessingInstruction(const MachineInstr &MI,
118                                       unsigned ImplicitRd = 0,
119                                       unsigned ImplicitRn = 0);
120
121    void emitLoadStoreInstruction(const MachineInstr &MI,
122                                  unsigned ImplicitRd = 0,
123                                  unsigned ImplicitRn = 0);
124
125    void emitMiscLoadStoreInstruction(const MachineInstr &MI,
126                                      unsigned ImplicitRn = 0);
127
128    void emitLoadStoreMultipleInstruction(const MachineInstr &MI);
129
130    void emitMulFrmInstruction(const MachineInstr &MI);
131
132    void emitExtendInstruction(const MachineInstr &MI);
133
134    void emitMiscArithInstruction(const MachineInstr &MI);
135
136    void emitBranchInstruction(const MachineInstr &MI);
137
138    void emitInlineJumpTable(unsigned JTIndex);
139
140    void emitMiscBranchInstruction(const MachineInstr &MI);
141
142    void emitVFPArithInstruction(const MachineInstr &MI);
143
144    void emitVFPConversionInstruction(const MachineInstr &MI);
145
146    void emitVFPLoadStoreInstruction(const MachineInstr &MI);
147
148    void emitVFPLoadStoreMultipleInstruction(const MachineInstr &MI);
149
150    void emitMiscInstruction(const MachineInstr &MI);
151
152    /// getMachineOpValue - Return binary encoding of operand. If the machine
153    /// operand requires relocation, record the relocation and return zero.
154    unsigned getMachineOpValue(const MachineInstr &MI,const MachineOperand &MO);
155    unsigned getMachineOpValue(const MachineInstr &MI, unsigned OpIdx) {
156      return getMachineOpValue(MI, MI.getOperand(OpIdx));
157    }
158
159    /// getShiftOp - Return the shift opcode (bit[6:5]) of the immediate value.
160    ///
161    unsigned getShiftOp(unsigned Imm) const ;
162
163    /// Routines that handle operands which add machine relocations which are
164    /// fixed up by the relocation stage.
165    void emitGlobalAddress(GlobalValue *GV, unsigned Reloc,
166                           bool NeedStub, intptr_t ACPV = 0);
167    void emitExternalSymbolAddress(const char *ES, unsigned Reloc);
168    void emitConstPoolAddress(unsigned CPI, unsigned Reloc);
169    void emitJumpTableAddress(unsigned JTIndex, unsigned Reloc);
170    void emitMachineBasicBlock(MachineBasicBlock *BB, unsigned Reloc,
171                               intptr_t JTBase = 0);
172  };
173  template <class CodeEmitter>
174  char Emitter<CodeEmitter>::ID = 0;
175}
176
177/// createARMCodeEmitterPass - Return a pass that emits the collected ARM code
178/// to the specified MCE object.
179
180FunctionPass *llvm::createARMCodeEmitterPass(ARMBaseTargetMachine &TM,
181                                             MachineCodeEmitter &MCE) {
182  return new Emitter<MachineCodeEmitter>(TM, MCE);
183}
184FunctionPass *llvm::createARMJITCodeEmitterPass(ARMBaseTargetMachine &TM,
185                                                JITCodeEmitter &JCE) {
186  return new Emitter<JITCodeEmitter>(TM, JCE);
187}
188FunctionPass *llvm::createARMObjectCodeEmitterPass(ARMBaseTargetMachine &TM,
189                                                   ObjectCodeEmitter &OCE) {
190  return new Emitter<ObjectCodeEmitter>(TM, OCE);
191}
192
193template<class CodeEmitter>
194bool Emitter<CodeEmitter>::runOnMachineFunction(MachineFunction &MF) {
195  assert((MF.getTarget().getRelocationModel() != Reloc::Default ||
196          MF.getTarget().getRelocationModel() != Reloc::Static) &&
197         "JIT relocation model must be set to static or default!");
198  II = ((ARMTargetMachine&)MF.getTarget()).getInstrInfo();
199  TD = ((ARMTargetMachine&)MF.getTarget()).getTargetData();
200  JTI = ((ARMTargetMachine&)MF.getTarget()).getJITInfo();
201  MCPEs = &MF.getConstantPool()->getConstants();
202  MJTEs = &MF.getJumpTableInfo()->getJumpTables();
203  IsPIC = TM.getRelocationModel() == Reloc::PIC_;
204  JTI->Initialize(MF, IsPIC);
205
206  do {
207    DEBUG(errs() << "JITTing function '"
208          << MF.getFunction()->getName() << "'\n");
209    MCE.startFunction(MF);
210    for (MachineFunction::iterator MBB = MF.begin(), E = MF.end();
211         MBB != E; ++MBB) {
212      MCE.StartMachineBasicBlock(MBB);
213      for (MachineBasicBlock::const_iterator I = MBB->begin(), E = MBB->end();
214           I != E; ++I)
215        emitInstruction(*I);
216    }
217  } while (MCE.finishFunction(MF));
218
219  return false;
220}
221
222/// getShiftOp - Return the shift opcode (bit[6:5]) of the immediate value.
223///
224template<class CodeEmitter>
225unsigned Emitter<CodeEmitter>::getShiftOp(unsigned Imm) const {
226  switch (ARM_AM::getAM2ShiftOpc(Imm)) {
227  default: llvm_unreachable("Unknown shift opc!");
228  case ARM_AM::asr: return 2;
229  case ARM_AM::lsl: return 0;
230  case ARM_AM::lsr: return 1;
231  case ARM_AM::ror:
232  case ARM_AM::rrx: return 3;
233  }
234  return 0;
235}
236
237/// getMachineOpValue - Return binary encoding of operand. If the machine
238/// operand requires relocation, record the relocation and return zero.
239template<class CodeEmitter>
240unsigned Emitter<CodeEmitter>::getMachineOpValue(const MachineInstr &MI,
241                                                 const MachineOperand &MO) {
242  if (MO.isReg())
243    return ARMRegisterInfo::getRegisterNumbering(MO.getReg());
244  else if (MO.isImm())
245    return static_cast<unsigned>(MO.getImm());
246  else if (MO.isGlobal())
247    emitGlobalAddress(MO.getGlobal(), ARM::reloc_arm_branch, true);
248  else if (MO.isSymbol())
249    emitExternalSymbolAddress(MO.getSymbolName(), ARM::reloc_arm_branch);
250  else if (MO.isCPI()) {
251    const TargetInstrDesc &TID = MI.getDesc();
252    // For VFP load, the immediate offset is multiplied by 4.
253    unsigned Reloc =  ((TID.TSFlags & ARMII::FormMask) == ARMII::VFPLdStFrm)
254      ? ARM::reloc_arm_vfp_cp_entry : ARM::reloc_arm_cp_entry;
255    emitConstPoolAddress(MO.getIndex(), Reloc);
256  } else if (MO.isJTI())
257    emitJumpTableAddress(MO.getIndex(), ARM::reloc_arm_relative);
258  else if (MO.isMBB())
259    emitMachineBasicBlock(MO.getMBB(), ARM::reloc_arm_branch);
260  else {
261#ifndef NDEBUG
262    errs() << MO;
263#endif
264    llvm_unreachable(0);
265  }
266  return 0;
267}
268
269/// emitGlobalAddress - Emit the specified address to the code stream.
270///
271template<class CodeEmitter>
272void Emitter<CodeEmitter>::emitGlobalAddress(GlobalValue *GV, unsigned Reloc,
273                                             bool NeedStub, intptr_t ACPV) {
274  MCE.addRelocation(MachineRelocation::getGV(MCE.getCurrentPCOffset(), Reloc,
275                                             GV, ACPV, NeedStub));
276}
277
278/// emitExternalSymbolAddress - Arrange for the address of an external symbol to
279/// be emitted to the current location in the function, and allow it to be PC
280/// relative.
281template<class CodeEmitter>
282void Emitter<CodeEmitter>::emitExternalSymbolAddress(const char *ES,
283                                                     unsigned Reloc) {
284  MCE.addRelocation(MachineRelocation::getExtSym(MCE.getCurrentPCOffset(),
285                                                 Reloc, ES));
286}
287
288/// emitConstPoolAddress - Arrange for the address of an constant pool
289/// to be emitted to the current location in the function, and allow it to be PC
290/// relative.
291template<class CodeEmitter>
292void Emitter<CodeEmitter>::emitConstPoolAddress(unsigned CPI,
293                                                unsigned Reloc) {
294  // Tell JIT emitter we'll resolve the address.
295  MCE.addRelocation(MachineRelocation::getConstPool(MCE.getCurrentPCOffset(),
296                                                    Reloc, CPI, 0, true));
297}
298
299/// emitJumpTableAddress - Arrange for the address of a jump table to
300/// be emitted to the current location in the function, and allow it to be PC
301/// relative.
302template<class CodeEmitter>
303void Emitter<CodeEmitter>::emitJumpTableAddress(unsigned JTIndex,
304                                                unsigned Reloc) {
305  MCE.addRelocation(MachineRelocation::getJumpTable(MCE.getCurrentPCOffset(),
306                                                    Reloc, JTIndex, 0, true));
307}
308
309/// emitMachineBasicBlock - Emit the specified address basic block.
310template<class CodeEmitter>
311void Emitter<CodeEmitter>::emitMachineBasicBlock(MachineBasicBlock *BB,
312                                              unsigned Reloc, intptr_t JTBase) {
313  MCE.addRelocation(MachineRelocation::getBB(MCE.getCurrentPCOffset(),
314                                             Reloc, BB, JTBase));
315}
316
317template<class CodeEmitter>
318void Emitter<CodeEmitter>::emitWordLE(unsigned Binary) {
319  DEBUG(errs() << "  0x";
320        errs().write_hex(Binary) << "\n");
321  MCE.emitWordLE(Binary);
322}
323
324template<class CodeEmitter>
325void Emitter<CodeEmitter>::emitDWordLE(uint64_t Binary) {
326  DEBUG(errs() << "  0x";
327        errs().write_hex(Binary) << "\n");
328  MCE.emitDWordLE(Binary);
329}
330
331template<class CodeEmitter>
332void Emitter<CodeEmitter>::emitInstruction(const MachineInstr &MI) {
333  DEBUG(errs() << "JIT: " << (void*)MCE.getCurrentPCValue() << ":\t" << MI);
334
335  MCE.processDebugLoc(MI.getDebugLoc());
336
337  NumEmitted++;  // Keep track of the # of mi's emitted
338  switch (MI.getDesc().TSFlags & ARMII::FormMask) {
339  default: {
340    llvm_unreachable("Unhandled instruction encoding format!");
341    break;
342  }
343  case ARMII::Pseudo:
344    emitPseudoInstruction(MI);
345    break;
346  case ARMII::DPFrm:
347  case ARMII::DPSoRegFrm:
348    emitDataProcessingInstruction(MI);
349    break;
350  case ARMII::LdFrm:
351  case ARMII::StFrm:
352    emitLoadStoreInstruction(MI);
353    break;
354  case ARMII::LdMiscFrm:
355  case ARMII::StMiscFrm:
356    emitMiscLoadStoreInstruction(MI);
357    break;
358  case ARMII::LdStMulFrm:
359    emitLoadStoreMultipleInstruction(MI);
360    break;
361  case ARMII::MulFrm:
362    emitMulFrmInstruction(MI);
363    break;
364  case ARMII::ExtFrm:
365    emitExtendInstruction(MI);
366    break;
367  case ARMII::ArithMiscFrm:
368    emitMiscArithInstruction(MI);
369    break;
370  case ARMII::BrFrm:
371    emitBranchInstruction(MI);
372    break;
373  case ARMII::BrMiscFrm:
374    emitMiscBranchInstruction(MI);
375    break;
376  // VFP instructions.
377  case ARMII::VFPUnaryFrm:
378  case ARMII::VFPBinaryFrm:
379    emitVFPArithInstruction(MI);
380    break;
381  case ARMII::VFPConv1Frm:
382  case ARMII::VFPConv2Frm:
383  case ARMII::VFPConv3Frm:
384  case ARMII::VFPConv4Frm:
385  case ARMII::VFPConv5Frm:
386    emitVFPConversionInstruction(MI);
387    break;
388  case ARMII::VFPLdStFrm:
389    emitVFPLoadStoreInstruction(MI);
390    break;
391  case ARMII::VFPLdStMulFrm:
392    emitVFPLoadStoreMultipleInstruction(MI);
393    break;
394  case ARMII::VFPMiscFrm:
395    emitMiscInstruction(MI);
396    break;
397  }
398}
399
400template<class CodeEmitter>
401void Emitter<CodeEmitter>::emitConstPoolInstruction(const MachineInstr &MI) {
402  unsigned CPI = MI.getOperand(0).getImm();       // CP instruction index.
403  unsigned CPIndex = MI.getOperand(1).getIndex(); // Actual cp entry index.
404  const MachineConstantPoolEntry &MCPE = (*MCPEs)[CPIndex];
405
406  // Remember the CONSTPOOL_ENTRY address for later relocation.
407  JTI->addConstantPoolEntryAddr(CPI, MCE.getCurrentPCValue());
408
409  // Emit constpool island entry. In most cases, the actual values will be
410  // resolved and relocated after code emission.
411  if (MCPE.isMachineConstantPoolEntry()) {
412    ARMConstantPoolValue *ACPV =
413      static_cast<ARMConstantPoolValue*>(MCPE.Val.MachineCPVal);
414
415    DEBUG(errs() << "  ** ARM constant pool #" << CPI << " @ "
416          << (void*)MCE.getCurrentPCValue() << " " << *ACPV << '\n');
417
418    GlobalValue *GV = ACPV->getGV();
419    if (GV) {
420      emitGlobalAddress(GV, ARM::reloc_arm_machine_cp_entry,
421                        isa<Function>(GV), (intptr_t)ACPV);
422     } else  {
423      emitExternalSymbolAddress(ACPV->getSymbol(), ARM::reloc_arm_absolute);
424    }
425    emitWordLE(0);
426  } else {
427    Constant *CV = MCPE.Val.ConstVal;
428
429    DEBUG({
430        errs() << "  ** Constant pool #" << CPI << " @ "
431               << (void*)MCE.getCurrentPCValue() << " ";
432        if (const Function *F = dyn_cast<Function>(CV))
433          errs() << F->getName();
434        else
435          errs() << *CV;
436        errs() << '\n';
437      });
438
439    if (GlobalValue *GV = dyn_cast<GlobalValue>(CV)) {
440      emitGlobalAddress(GV, ARM::reloc_arm_absolute, isa<Function>(GV));
441      emitWordLE(0);
442    } else if (const ConstantInt *CI = dyn_cast<ConstantInt>(CV)) {
443      uint32_t Val = *(uint32_t*)CI->getValue().getRawData();
444      emitWordLE(Val);
445    } else if (const ConstantFP *CFP = dyn_cast<ConstantFP>(CV)) {
446      if (CFP->getType() == Type::getFloatTy(CFP->getContext()))
447        emitWordLE(CFP->getValueAPF().bitcastToAPInt().getZExtValue());
448      else if (CFP->getType() == Type::getDoubleTy(CFP->getContext()))
449        emitDWordLE(CFP->getValueAPF().bitcastToAPInt().getZExtValue());
450      else {
451        llvm_unreachable("Unable to handle this constantpool entry!");
452      }
453    } else {
454      llvm_unreachable("Unable to handle this constantpool entry!");
455    }
456  }
457}
458
459template<class CodeEmitter>
460void Emitter<CodeEmitter>::emitMOVi2piecesInstruction(const MachineInstr &MI) {
461  const MachineOperand &MO0 = MI.getOperand(0);
462  const MachineOperand &MO1 = MI.getOperand(1);
463  assert(MO1.isImm() && ARM_AM::getSOImmVal(MO1.isImm()) != -1 &&
464                                            "Not a valid so_imm value!");
465  unsigned V1 = ARM_AM::getSOImmTwoPartFirst(MO1.getImm());
466  unsigned V2 = ARM_AM::getSOImmTwoPartSecond(MO1.getImm());
467
468  // Emit the 'mov' instruction.
469  unsigned Binary = 0xd << 21;  // mov: Insts{24-21} = 0b1101
470
471  // Set the conditional execution predicate.
472  Binary |= II->getPredicate(&MI) << ARMII::CondShift;
473
474  // Encode Rd.
475  Binary |= getMachineOpValue(MI, MO0) << ARMII::RegRdShift;
476
477  // Encode so_imm.
478  // Set bit I(25) to identify this is the immediate form of <shifter_op>
479  Binary |= 1 << ARMII::I_BitShift;
480  Binary |= getMachineSoImmOpValue(V1);
481  emitWordLE(Binary);
482
483  // Now the 'orr' instruction.
484  Binary = 0xc << 21;  // orr: Insts{24-21} = 0b1100
485
486  // Set the conditional execution predicate.
487  Binary |= II->getPredicate(&MI) << ARMII::CondShift;
488
489  // Encode Rd.
490  Binary |= getMachineOpValue(MI, MO0) << ARMII::RegRdShift;
491
492  // Encode Rn.
493  Binary |= getMachineOpValue(MI, MO0) << ARMII::RegRnShift;
494
495  // Encode so_imm.
496  // Set bit I(25) to identify this is the immediate form of <shifter_op>
497  Binary |= 1 << ARMII::I_BitShift;
498  Binary |= getMachineSoImmOpValue(V2);
499  emitWordLE(Binary);
500}
501
502template<class CodeEmitter>
503void Emitter<CodeEmitter>::emitLEApcrelJTInstruction(const MachineInstr &MI) {
504  // It's basically add r, pc, (LJTI - $+8)
505
506  const TargetInstrDesc &TID = MI.getDesc();
507
508  // Emit the 'add' instruction.
509  unsigned Binary = 0x4 << 21;  // add: Insts{24-31} = 0b0100
510
511  // Set the conditional execution predicate
512  Binary |= II->getPredicate(&MI) << ARMII::CondShift;
513
514  // Encode S bit if MI modifies CPSR.
515  Binary |= getAddrModeSBit(MI, TID);
516
517  // Encode Rd.
518  Binary |= getMachineOpValue(MI, 0) << ARMII::RegRdShift;
519
520  // Encode Rn which is PC.
521  Binary |= ARMRegisterInfo::getRegisterNumbering(ARM::PC) << ARMII::RegRnShift;
522
523  // Encode the displacement.
524  Binary |= 1 << ARMII::I_BitShift;
525  emitJumpTableAddress(MI.getOperand(1).getIndex(), ARM::reloc_arm_jt_base);
526
527  emitWordLE(Binary);
528}
529
530template<class CodeEmitter>
531void Emitter<CodeEmitter>::emitPseudoMoveInstruction(const MachineInstr &MI) {
532  unsigned Opcode = MI.getDesc().Opcode;
533
534  // Part of binary is determined by TableGn.
535  unsigned Binary = getBinaryCodeForInstr(MI);
536
537  // Set the conditional execution predicate
538  Binary |= II->getPredicate(&MI) << ARMII::CondShift;
539
540  // Encode S bit if MI modifies CPSR.
541  if (Opcode == ARM::MOVsrl_flag || Opcode == ARM::MOVsra_flag)
542    Binary |= 1 << ARMII::S_BitShift;
543
544  // Encode register def if there is one.
545  Binary |= getMachineOpValue(MI, 0) << ARMII::RegRdShift;
546
547  // Encode the shift operation.
548  switch (Opcode) {
549  default: break;
550  case ARM::MOVrx:
551    // rrx
552    Binary |= 0x6 << 4;
553    break;
554  case ARM::MOVsrl_flag:
555    // lsr #1
556    Binary |= (0x2 << 4) | (1 << 7);
557    break;
558  case ARM::MOVsra_flag:
559    // asr #1
560    Binary |= (0x4 << 4) | (1 << 7);
561    break;
562  }
563
564  // Encode register Rm.
565  Binary |= getMachineOpValue(MI, 1);
566
567  emitWordLE(Binary);
568}
569
570template<class CodeEmitter>
571void Emitter<CodeEmitter>::addPCLabel(unsigned LabelID) {
572  DEBUG(errs() << "  ** LPC" << LabelID << " @ "
573        << (void*)MCE.getCurrentPCValue() << '\n');
574  JTI->addPCLabelAddr(LabelID, MCE.getCurrentPCValue());
575}
576
577template<class CodeEmitter>
578void Emitter<CodeEmitter>::emitPseudoInstruction(const MachineInstr &MI) {
579  unsigned Opcode = MI.getDesc().Opcode;
580  switch (Opcode) {
581  default:
582    llvm_unreachable("ARMCodeEmitter::emitPseudoInstruction");//FIXME:
583  case TargetInstrInfo::INLINEASM: {
584    // We allow inline assembler nodes with empty bodies - they can
585    // implicitly define registers, which is ok for JIT.
586    if (MI.getOperand(0).getSymbolName()[0]) {
587      llvm_report_error("JIT does not support inline asm!");
588    }
589    break;
590  }
591  case TargetInstrInfo::DBG_LABEL:
592  case TargetInstrInfo::EH_LABEL:
593    MCE.emitLabel(MI.getOperand(0).getImm());
594    break;
595  case TargetInstrInfo::IMPLICIT_DEF:
596  case ARM::DWARF_LOC:
597    // Do nothing.
598    break;
599  case ARM::CONSTPOOL_ENTRY:
600    emitConstPoolInstruction(MI);
601    break;
602  case ARM::PICADD: {
603    // Remember of the address of the PC label for relocation later.
604    addPCLabel(MI.getOperand(2).getImm());
605    // PICADD is just an add instruction that implicitly read pc.
606    emitDataProcessingInstruction(MI, 0, ARM::PC);
607    break;
608  }
609  case ARM::PICLDR:
610  case ARM::PICLDRB:
611  case ARM::PICSTR:
612  case ARM::PICSTRB: {
613    // Remember of the address of the PC label for relocation later.
614    addPCLabel(MI.getOperand(2).getImm());
615    // These are just load / store instructions that implicitly read pc.
616    emitLoadStoreInstruction(MI, 0, ARM::PC);
617    break;
618  }
619  case ARM::PICLDRH:
620  case ARM::PICLDRSH:
621  case ARM::PICLDRSB:
622  case ARM::PICSTRH: {
623    // Remember of the address of the PC label for relocation later.
624    addPCLabel(MI.getOperand(2).getImm());
625    // These are just load / store instructions that implicitly read pc.
626    emitMiscLoadStoreInstruction(MI, ARM::PC);
627    break;
628  }
629  case ARM::MOVi2pieces:
630    // Two instructions to materialize a constant.
631    emitMOVi2piecesInstruction(MI);
632    break;
633  case ARM::LEApcrelJT:
634    // Materialize jumptable address.
635    emitLEApcrelJTInstruction(MI);
636    break;
637  case ARM::MOVrx:
638  case ARM::MOVsrl_flag:
639  case ARM::MOVsra_flag:
640    emitPseudoMoveInstruction(MI);
641    break;
642  }
643}
644
645template<class CodeEmitter>
646unsigned Emitter<CodeEmitter>::getMachineSoRegOpValue(
647                                                const MachineInstr &MI,
648                                                const TargetInstrDesc &TID,
649                                                const MachineOperand &MO,
650                                                unsigned OpIdx) {
651  unsigned Binary = getMachineOpValue(MI, MO);
652
653  const MachineOperand &MO1 = MI.getOperand(OpIdx + 1);
654  const MachineOperand &MO2 = MI.getOperand(OpIdx + 2);
655  ARM_AM::ShiftOpc SOpc = ARM_AM::getSORegShOp(MO2.getImm());
656
657  // Encode the shift opcode.
658  unsigned SBits = 0;
659  unsigned Rs = MO1.getReg();
660  if (Rs) {
661    // Set shift operand (bit[7:4]).
662    // LSL - 0001
663    // LSR - 0011
664    // ASR - 0101
665    // ROR - 0111
666    // RRX - 0110 and bit[11:8] clear.
667    switch (SOpc) {
668    default: llvm_unreachable("Unknown shift opc!");
669    case ARM_AM::lsl: SBits = 0x1; break;
670    case ARM_AM::lsr: SBits = 0x3; break;
671    case ARM_AM::asr: SBits = 0x5; break;
672    case ARM_AM::ror: SBits = 0x7; break;
673    case ARM_AM::rrx: SBits = 0x6; break;
674    }
675  } else {
676    // Set shift operand (bit[6:4]).
677    // LSL - 000
678    // LSR - 010
679    // ASR - 100
680    // ROR - 110
681    switch (SOpc) {
682    default: llvm_unreachable("Unknown shift opc!");
683    case ARM_AM::lsl: SBits = 0x0; break;
684    case ARM_AM::lsr: SBits = 0x2; break;
685    case ARM_AM::asr: SBits = 0x4; break;
686    case ARM_AM::ror: SBits = 0x6; break;
687    }
688  }
689  Binary |= SBits << 4;
690  if (SOpc == ARM_AM::rrx)
691    return Binary;
692
693  // Encode the shift operation Rs or shift_imm (except rrx).
694  if (Rs) {
695    // Encode Rs bit[11:8].
696    assert(ARM_AM::getSORegOffset(MO2.getImm()) == 0);
697    return Binary |
698      (ARMRegisterInfo::getRegisterNumbering(Rs) << ARMII::RegRsShift);
699  }
700
701  // Encode shift_imm bit[11:7].
702  return Binary | ARM_AM::getSORegOffset(MO2.getImm()) << 7;
703}
704
705template<class CodeEmitter>
706unsigned Emitter<CodeEmitter>::getMachineSoImmOpValue(unsigned SoImm) {
707  int SoImmVal = ARM_AM::getSOImmVal(SoImm);
708  assert(SoImmVal != -1 && "Not a valid so_imm value!");
709
710  // Encode rotate_imm.
711  unsigned Binary = (ARM_AM::getSOImmValRot((unsigned)SoImmVal) >> 1)
712    << ARMII::SoRotImmShift;
713
714  // Encode immed_8.
715  Binary |= ARM_AM::getSOImmValImm((unsigned)SoImmVal);
716  return Binary;
717}
718
719template<class CodeEmitter>
720unsigned Emitter<CodeEmitter>::getAddrModeSBit(const MachineInstr &MI,
721                                             const TargetInstrDesc &TID) const {
722  for (unsigned i = MI.getNumOperands(), e = TID.getNumOperands(); i != e; --i){
723    const MachineOperand &MO = MI.getOperand(i-1);
724    if (MO.isReg() && MO.isDef() && MO.getReg() == ARM::CPSR)
725      return 1 << ARMII::S_BitShift;
726  }
727  return 0;
728}
729
730template<class CodeEmitter>
731void Emitter<CodeEmitter>::emitDataProcessingInstruction(
732                                                   const MachineInstr &MI,
733                                                   unsigned ImplicitRd,
734                                                   unsigned ImplicitRn) {
735  const TargetInstrDesc &TID = MI.getDesc();
736
737  if (TID.Opcode == ARM::BFC) {
738    llvm_report_error("ARMv6t2 JIT is not yet supported.");
739  }
740
741  // Part of binary is determined by TableGn.
742  unsigned Binary = getBinaryCodeForInstr(MI);
743
744  // Set the conditional execution predicate
745  Binary |= II->getPredicate(&MI) << ARMII::CondShift;
746
747  // Encode S bit if MI modifies CPSR.
748  Binary |= getAddrModeSBit(MI, TID);
749
750  // Encode register def if there is one.
751  unsigned NumDefs = TID.getNumDefs();
752  unsigned OpIdx = 0;
753  if (NumDefs)
754    Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRdShift;
755  else if (ImplicitRd)
756    // Special handling for implicit use (e.g. PC).
757    Binary |= (ARMRegisterInfo::getRegisterNumbering(ImplicitRd)
758               << ARMII::RegRdShift);
759
760  // If this is a two-address operand, skip it. e.g. MOVCCr operand 1.
761  if (TID.getOperandConstraint(OpIdx, TOI::TIED_TO) != -1)
762    ++OpIdx;
763
764  // Encode first non-shifter register operand if there is one.
765  bool isUnary = TID.TSFlags & ARMII::UnaryDP;
766  if (!isUnary) {
767    if (ImplicitRn)
768      // Special handling for implicit use (e.g. PC).
769      Binary |= (ARMRegisterInfo::getRegisterNumbering(ImplicitRn)
770                 << ARMII::RegRnShift);
771    else {
772      Binary |= getMachineOpValue(MI, OpIdx) << ARMII::RegRnShift;
773      ++OpIdx;
774    }
775  }
776
777  // Encode shifter operand.
778  const MachineOperand &MO = MI.getOperand(OpIdx);
779  if ((TID.TSFlags & ARMII::FormMask) == ARMII::DPSoRegFrm) {
780    // Encode SoReg.
781    emitWordLE(Binary | getMachineSoRegOpValue(MI, TID, MO, OpIdx));
782    return;
783  }
784
785  if (MO.isReg()) {
786    // Encode register Rm.
787    emitWordLE(Binary | ARMRegisterInfo::getRegisterNumbering(MO.getReg()));
788    return;
789  }
790
791  // Encode so_imm.
792  Binary |= getMachineSoImmOpValue((unsigned)MO.getImm());
793
794  emitWordLE(Binary);
795}
796
797template<class CodeEmitter>
798void Emitter<CodeEmitter>::emitLoadStoreInstruction(
799                                              const MachineInstr &MI,
800                                              unsigned ImplicitRd,
801                                              unsigned ImplicitRn) {
802  const TargetInstrDesc &TID = MI.getDesc();
803  unsigned Form = TID.TSFlags & ARMII::FormMask;
804  bool IsPrePost = (TID.TSFlags & ARMII::IndexModeMask) != 0;
805
806  // Part of binary is determined by TableGn.
807  unsigned Binary = getBinaryCodeForInstr(MI);
808
809  // Set the conditional execution predicate
810  Binary |= II->getPredicate(&MI) << ARMII::CondShift;
811
812  unsigned OpIdx = 0;
813
814  // Operand 0 of a pre- and post-indexed store is the address base
815  // writeback. Skip it.
816  bool Skipped = false;
817  if (IsPrePost && Form == ARMII::StFrm) {
818    ++OpIdx;
819    Skipped = true;
820  }
821
822  // Set first operand
823  if (ImplicitRd)
824    // Special handling for implicit use (e.g. PC).
825    Binary |= (ARMRegisterInfo::getRegisterNumbering(ImplicitRd)
826               << ARMII::RegRdShift);
827  else
828    Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRdShift;
829
830  // Set second operand
831  if (ImplicitRn)
832    // Special handling for implicit use (e.g. PC).
833    Binary |= (ARMRegisterInfo::getRegisterNumbering(ImplicitRn)
834               << ARMII::RegRnShift);
835  else
836    Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRnShift;
837
838  // If this is a two-address operand, skip it. e.g. LDR_PRE.
839  if (!Skipped && TID.getOperandConstraint(OpIdx, TOI::TIED_TO) != -1)
840    ++OpIdx;
841
842  const MachineOperand &MO2 = MI.getOperand(OpIdx);
843  unsigned AM2Opc = (ImplicitRn == ARM::PC)
844    ? 0 : MI.getOperand(OpIdx+1).getImm();
845
846  // Set bit U(23) according to sign of immed value (positive or negative).
847  Binary |= ((ARM_AM::getAM2Op(AM2Opc) == ARM_AM::add ? 1 : 0) <<
848             ARMII::U_BitShift);
849  if (!MO2.getReg()) { // is immediate
850    if (ARM_AM::getAM2Offset(AM2Opc))
851      // Set the value of offset_12 field
852      Binary |= ARM_AM::getAM2Offset(AM2Opc);
853    emitWordLE(Binary);
854    return;
855  }
856
857  // Set bit I(25), because this is not in immediate enconding.
858  Binary |= 1 << ARMII::I_BitShift;
859  assert(TargetRegisterInfo::isPhysicalRegister(MO2.getReg()));
860  // Set bit[3:0] to the corresponding Rm register
861  Binary |= ARMRegisterInfo::getRegisterNumbering(MO2.getReg());
862
863  // If this instr is in scaled register offset/index instruction, set
864  // shift_immed(bit[11:7]) and shift(bit[6:5]) fields.
865  if (unsigned ShImm = ARM_AM::getAM2Offset(AM2Opc)) {
866    Binary |= getShiftOp(AM2Opc) << ARMII::ShiftImmShift;  // shift
867    Binary |= ShImm              << ARMII::ShiftShift;     // shift_immed
868  }
869
870  emitWordLE(Binary);
871}
872
873template<class CodeEmitter>
874void Emitter<CodeEmitter>::emitMiscLoadStoreInstruction(const MachineInstr &MI,
875                                                        unsigned ImplicitRn) {
876  const TargetInstrDesc &TID = MI.getDesc();
877  unsigned Form = TID.TSFlags & ARMII::FormMask;
878  bool IsPrePost = (TID.TSFlags & ARMII::IndexModeMask) != 0;
879
880  // Part of binary is determined by TableGn.
881  unsigned Binary = getBinaryCodeForInstr(MI);
882
883  // Set the conditional execution predicate
884  Binary |= II->getPredicate(&MI) << ARMII::CondShift;
885
886  unsigned OpIdx = 0;
887
888  // Operand 0 of a pre- and post-indexed store is the address base
889  // writeback. Skip it.
890  bool Skipped = false;
891  if (IsPrePost && Form == ARMII::StMiscFrm) {
892    ++OpIdx;
893    Skipped = true;
894  }
895
896  // Set first operand
897  Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRdShift;
898
899  // Skip LDRD and STRD's second operand.
900  if (TID.Opcode == ARM::LDRD || TID.Opcode == ARM::STRD)
901    ++OpIdx;
902
903  // Set second operand
904  if (ImplicitRn)
905    // Special handling for implicit use (e.g. PC).
906    Binary |= (ARMRegisterInfo::getRegisterNumbering(ImplicitRn)
907               << ARMII::RegRnShift);
908  else
909    Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRnShift;
910
911  // If this is a two-address operand, skip it. e.g. LDRH_POST.
912  if (!Skipped && TID.getOperandConstraint(OpIdx, TOI::TIED_TO) != -1)
913    ++OpIdx;
914
915  const MachineOperand &MO2 = MI.getOperand(OpIdx);
916  unsigned AM3Opc = (ImplicitRn == ARM::PC)
917    ? 0 : MI.getOperand(OpIdx+1).getImm();
918
919  // Set bit U(23) according to sign of immed value (positive or negative)
920  Binary |= ((ARM_AM::getAM3Op(AM3Opc) == ARM_AM::add ? 1 : 0) <<
921             ARMII::U_BitShift);
922
923  // If this instr is in register offset/index encoding, set bit[3:0]
924  // to the corresponding Rm register.
925  if (MO2.getReg()) {
926    Binary |= ARMRegisterInfo::getRegisterNumbering(MO2.getReg());
927    emitWordLE(Binary);
928    return;
929  }
930
931  // This instr is in immediate offset/index encoding, set bit 22 to 1.
932  Binary |= 1 << ARMII::AM3_I_BitShift;
933  if (unsigned ImmOffs = ARM_AM::getAM3Offset(AM3Opc)) {
934    // Set operands
935    Binary |= (ImmOffs >> 4) << ARMII::ImmHiShift;  // immedH
936    Binary |= (ImmOffs & 0xF);                      // immedL
937  }
938
939  emitWordLE(Binary);
940}
941
942static unsigned getAddrModeUPBits(unsigned Mode) {
943  unsigned Binary = 0;
944
945  // Set addressing mode by modifying bits U(23) and P(24)
946  // IA - Increment after  - bit U = 1 and bit P = 0
947  // IB - Increment before - bit U = 1 and bit P = 1
948  // DA - Decrement after  - bit U = 0 and bit P = 0
949  // DB - Decrement before - bit U = 0 and bit P = 1
950  switch (Mode) {
951  default: llvm_unreachable("Unknown addressing sub-mode!");
952  case ARM_AM::da:                      break;
953  case ARM_AM::db: Binary |= 0x1 << ARMII::P_BitShift; break;
954  case ARM_AM::ia: Binary |= 0x1 << ARMII::U_BitShift; break;
955  case ARM_AM::ib: Binary |= 0x3 << ARMII::U_BitShift; break;
956  }
957
958  return Binary;
959}
960
961template<class CodeEmitter>
962void Emitter<CodeEmitter>::emitLoadStoreMultipleInstruction(
963                                                       const MachineInstr &MI) {
964  // Part of binary is determined by TableGn.
965  unsigned Binary = getBinaryCodeForInstr(MI);
966
967  // Set the conditional execution predicate
968  Binary |= II->getPredicate(&MI) << ARMII::CondShift;
969
970  // Set base address operand
971  Binary |= getMachineOpValue(MI, 0) << ARMII::RegRnShift;
972
973  // Set addressing mode by modifying bits U(23) and P(24)
974  const MachineOperand &MO = MI.getOperand(1);
975  Binary |= getAddrModeUPBits(ARM_AM::getAM4SubMode(MO.getImm()));
976
977  // Set bit W(21)
978  if (ARM_AM::getAM4WBFlag(MO.getImm()))
979    Binary |= 0x1 << ARMII::W_BitShift;
980
981  // Set registers
982  for (unsigned i = 4, e = MI.getNumOperands(); i != e; ++i) {
983    const MachineOperand &MO = MI.getOperand(i);
984    if (!MO.isReg() || MO.isImplicit())
985      break;
986    unsigned RegNum = ARMRegisterInfo::getRegisterNumbering(MO.getReg());
987    assert(TargetRegisterInfo::isPhysicalRegister(MO.getReg()) &&
988           RegNum < 16);
989    Binary |= 0x1 << RegNum;
990  }
991
992  emitWordLE(Binary);
993}
994
995template<class CodeEmitter>
996void Emitter<CodeEmitter>::emitMulFrmInstruction(const MachineInstr &MI) {
997  const TargetInstrDesc &TID = MI.getDesc();
998
999  // Part of binary is determined by TableGn.
1000  unsigned Binary = getBinaryCodeForInstr(MI);
1001
1002  // Set the conditional execution predicate
1003  Binary |= II->getPredicate(&MI) << ARMII::CondShift;
1004
1005  // Encode S bit if MI modifies CPSR.
1006  Binary |= getAddrModeSBit(MI, TID);
1007
1008  // 32x32->64bit operations have two destination registers. The number
1009  // of register definitions will tell us if that's what we're dealing with.
1010  unsigned OpIdx = 0;
1011  if (TID.getNumDefs() == 2)
1012    Binary |= getMachineOpValue (MI, OpIdx++) << ARMII::RegRdLoShift;
1013
1014  // Encode Rd
1015  Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRdHiShift;
1016
1017  // Encode Rm
1018  Binary |= getMachineOpValue(MI, OpIdx++);
1019
1020  // Encode Rs
1021  Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRsShift;
1022
1023  // Many multiple instructions (e.g. MLA) have three src operands. Encode
1024  // it as Rn (for multiply, that's in the same offset as RdLo.
1025  if (TID.getNumOperands() > OpIdx &&
1026      !TID.OpInfo[OpIdx].isPredicate() &&
1027      !TID.OpInfo[OpIdx].isOptionalDef())
1028    Binary |= getMachineOpValue(MI, OpIdx) << ARMII::RegRdLoShift;
1029
1030  emitWordLE(Binary);
1031}
1032
1033template<class CodeEmitter>
1034void Emitter<CodeEmitter>::emitExtendInstruction(const MachineInstr &MI) {
1035  const TargetInstrDesc &TID = MI.getDesc();
1036
1037  // Part of binary is determined by TableGn.
1038  unsigned Binary = getBinaryCodeForInstr(MI);
1039
1040  // Set the conditional execution predicate
1041  Binary |= II->getPredicate(&MI) << ARMII::CondShift;
1042
1043  unsigned OpIdx = 0;
1044
1045  // Encode Rd
1046  Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRdShift;
1047
1048  const MachineOperand &MO1 = MI.getOperand(OpIdx++);
1049  const MachineOperand &MO2 = MI.getOperand(OpIdx);
1050  if (MO2.isReg()) {
1051    // Two register operand form.
1052    // Encode Rn.
1053    Binary |= getMachineOpValue(MI, MO1) << ARMII::RegRnShift;
1054
1055    // Encode Rm.
1056    Binary |= getMachineOpValue(MI, MO2);
1057    ++OpIdx;
1058  } else {
1059    Binary |= getMachineOpValue(MI, MO1);
1060  }
1061
1062  // Encode rot imm (0, 8, 16, or 24) if it has a rotate immediate operand.
1063  if (MI.getOperand(OpIdx).isImm() &&
1064      !TID.OpInfo[OpIdx].isPredicate() &&
1065      !TID.OpInfo[OpIdx].isOptionalDef())
1066    Binary |= (getMachineOpValue(MI, OpIdx) / 8) << ARMII::ExtRotImmShift;
1067
1068  emitWordLE(Binary);
1069}
1070
1071template<class CodeEmitter>
1072void Emitter<CodeEmitter>::emitMiscArithInstruction(const MachineInstr &MI) {
1073  const TargetInstrDesc &TID = MI.getDesc();
1074
1075  // Part of binary is determined by TableGn.
1076  unsigned Binary = getBinaryCodeForInstr(MI);
1077
1078  // Set the conditional execution predicate
1079  Binary |= II->getPredicate(&MI) << ARMII::CondShift;
1080
1081  unsigned OpIdx = 0;
1082
1083  // Encode Rd
1084  Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRdShift;
1085
1086  const MachineOperand &MO = MI.getOperand(OpIdx++);
1087  if (OpIdx == TID.getNumOperands() ||
1088      TID.OpInfo[OpIdx].isPredicate() ||
1089      TID.OpInfo[OpIdx].isOptionalDef()) {
1090    // Encode Rm and it's done.
1091    Binary |= getMachineOpValue(MI, MO);
1092    emitWordLE(Binary);
1093    return;
1094  }
1095
1096  // Encode Rn.
1097  Binary |= getMachineOpValue(MI, MO) << ARMII::RegRnShift;
1098
1099  // Encode Rm.
1100  Binary |= getMachineOpValue(MI, OpIdx++);
1101
1102  // Encode shift_imm.
1103  unsigned ShiftAmt = MI.getOperand(OpIdx).getImm();
1104  assert(ShiftAmt < 32 && "shift_imm range is 0 to 31!");
1105  Binary |= ShiftAmt << ARMII::ShiftShift;
1106
1107  emitWordLE(Binary);
1108}
1109
1110template<class CodeEmitter>
1111void Emitter<CodeEmitter>::emitBranchInstruction(const MachineInstr &MI) {
1112  const TargetInstrDesc &TID = MI.getDesc();
1113
1114  if (TID.Opcode == ARM::TPsoft) {
1115    llvm_unreachable("ARM::TPsoft FIXME"); // FIXME
1116  }
1117
1118  // Part of binary is determined by TableGn.
1119  unsigned Binary = getBinaryCodeForInstr(MI);
1120
1121  // Set the conditional execution predicate
1122  Binary |= II->getPredicate(&MI) << ARMII::CondShift;
1123
1124  // Set signed_immed_24 field
1125  Binary |= getMachineOpValue(MI, 0);
1126
1127  emitWordLE(Binary);
1128}
1129
1130template<class CodeEmitter>
1131void Emitter<CodeEmitter>::emitInlineJumpTable(unsigned JTIndex) {
1132  // Remember the base address of the inline jump table.
1133  uintptr_t JTBase = MCE.getCurrentPCValue();
1134  JTI->addJumpTableBaseAddr(JTIndex, JTBase);
1135  DEBUG(errs() << "  ** Jump Table #" << JTIndex << " @ " << (void*)JTBase
1136               << '\n');
1137
1138  // Now emit the jump table entries.
1139  const std::vector<MachineBasicBlock*> &MBBs = (*MJTEs)[JTIndex].MBBs;
1140  for (unsigned i = 0, e = MBBs.size(); i != e; ++i) {
1141    if (IsPIC)
1142      // DestBB address - JT base.
1143      emitMachineBasicBlock(MBBs[i], ARM::reloc_arm_pic_jt, JTBase);
1144    else
1145      // Absolute DestBB address.
1146      emitMachineBasicBlock(MBBs[i], ARM::reloc_arm_absolute);
1147    emitWordLE(0);
1148  }
1149}
1150
1151template<class CodeEmitter>
1152void Emitter<CodeEmitter>::emitMiscBranchInstruction(const MachineInstr &MI) {
1153  const TargetInstrDesc &TID = MI.getDesc();
1154
1155  // Handle jump tables.
1156  if (TID.Opcode == ARM::BR_JTr || TID.Opcode == ARM::BR_JTadd) {
1157    // First emit a ldr pc, [] instruction.
1158    emitDataProcessingInstruction(MI, ARM::PC);
1159
1160    // Then emit the inline jump table.
1161    unsigned JTIndex =
1162      (TID.Opcode == ARM::BR_JTr)
1163      ? MI.getOperand(1).getIndex() : MI.getOperand(2).getIndex();
1164    emitInlineJumpTable(JTIndex);
1165    return;
1166  } else if (TID.Opcode == ARM::BR_JTm) {
1167    // First emit a ldr pc, [] instruction.
1168    emitLoadStoreInstruction(MI, ARM::PC);
1169
1170    // Then emit the inline jump table.
1171    emitInlineJumpTable(MI.getOperand(3).getIndex());
1172    return;
1173  }
1174
1175  // Part of binary is determined by TableGn.
1176  unsigned Binary = getBinaryCodeForInstr(MI);
1177
1178  // Set the conditional execution predicate
1179  Binary |= II->getPredicate(&MI) << ARMII::CondShift;
1180
1181  if (TID.Opcode == ARM::BX_RET)
1182    // The return register is LR.
1183    Binary |= ARMRegisterInfo::getRegisterNumbering(ARM::LR);
1184  else
1185    // otherwise, set the return register
1186    Binary |= getMachineOpValue(MI, 0);
1187
1188  emitWordLE(Binary);
1189}
1190
1191static unsigned encodeVFPRd(const MachineInstr &MI, unsigned OpIdx) {
1192  unsigned RegD = MI.getOperand(OpIdx).getReg();
1193  unsigned Binary = 0;
1194  bool isSPVFP = false;
1195  RegD = ARMRegisterInfo::getRegisterNumbering(RegD, &isSPVFP);
1196  if (!isSPVFP)
1197    Binary |=   RegD               << ARMII::RegRdShift;
1198  else {
1199    Binary |= ((RegD & 0x1E) >> 1) << ARMII::RegRdShift;
1200    Binary |=  (RegD & 0x01)       << ARMII::D_BitShift;
1201  }
1202  return Binary;
1203}
1204
1205static unsigned encodeVFPRn(const MachineInstr &MI, unsigned OpIdx) {
1206  unsigned RegN = MI.getOperand(OpIdx).getReg();
1207  unsigned Binary = 0;
1208  bool isSPVFP = false;
1209  RegN = ARMRegisterInfo::getRegisterNumbering(RegN, &isSPVFP);
1210  if (!isSPVFP)
1211    Binary |=   RegN               << ARMII::RegRnShift;
1212  else {
1213    Binary |= ((RegN & 0x1E) >> 1) << ARMII::RegRnShift;
1214    Binary |=  (RegN & 0x01)       << ARMII::N_BitShift;
1215  }
1216  return Binary;
1217}
1218
1219static unsigned encodeVFPRm(const MachineInstr &MI, unsigned OpIdx) {
1220  unsigned RegM = MI.getOperand(OpIdx).getReg();
1221  unsigned Binary = 0;
1222  bool isSPVFP = false;
1223  RegM = ARMRegisterInfo::getRegisterNumbering(RegM, &isSPVFP);
1224  if (!isSPVFP)
1225    Binary |=   RegM;
1226  else {
1227    Binary |= ((RegM & 0x1E) >> 1);
1228    Binary |=  (RegM & 0x01)       << ARMII::M_BitShift;
1229  }
1230  return Binary;
1231}
1232
1233template<class CodeEmitter>
1234void Emitter<CodeEmitter>::emitVFPArithInstruction(const MachineInstr &MI) {
1235  const TargetInstrDesc &TID = MI.getDesc();
1236
1237  // Part of binary is determined by TableGn.
1238  unsigned Binary = getBinaryCodeForInstr(MI);
1239
1240  // Set the conditional execution predicate
1241  Binary |= II->getPredicate(&MI) << ARMII::CondShift;
1242
1243  unsigned OpIdx = 0;
1244  assert((Binary & ARMII::D_BitShift) == 0 &&
1245         (Binary & ARMII::N_BitShift) == 0 &&
1246         (Binary & ARMII::M_BitShift) == 0 && "VFP encoding bug!");
1247
1248  // Encode Dd / Sd.
1249  Binary |= encodeVFPRd(MI, OpIdx++);
1250
1251  // If this is a two-address operand, skip it, e.g. FMACD.
1252  if (TID.getOperandConstraint(OpIdx, TOI::TIED_TO) != -1)
1253    ++OpIdx;
1254
1255  // Encode Dn / Sn.
1256  if ((TID.TSFlags & ARMII::FormMask) == ARMII::VFPBinaryFrm)
1257    Binary |= encodeVFPRn(MI, OpIdx++);
1258
1259  if (OpIdx == TID.getNumOperands() ||
1260      TID.OpInfo[OpIdx].isPredicate() ||
1261      TID.OpInfo[OpIdx].isOptionalDef()) {
1262    // FCMPEZD etc. has only one operand.
1263    emitWordLE(Binary);
1264    return;
1265  }
1266
1267  // Encode Dm / Sm.
1268  Binary |= encodeVFPRm(MI, OpIdx);
1269
1270  emitWordLE(Binary);
1271}
1272
1273template<class CodeEmitter>
1274void Emitter<CodeEmitter>::emitVFPConversionInstruction(
1275      const MachineInstr &MI) {
1276  const TargetInstrDesc &TID = MI.getDesc();
1277  unsigned Form = TID.TSFlags & ARMII::FormMask;
1278
1279  // Part of binary is determined by TableGn.
1280  unsigned Binary = getBinaryCodeForInstr(MI);
1281
1282  // Set the conditional execution predicate
1283  Binary |= II->getPredicate(&MI) << ARMII::CondShift;
1284
1285  switch (Form) {
1286  default: break;
1287  case ARMII::VFPConv1Frm:
1288  case ARMII::VFPConv2Frm:
1289  case ARMII::VFPConv3Frm:
1290    // Encode Dd / Sd.
1291    Binary |= encodeVFPRd(MI, 0);
1292    break;
1293  case ARMII::VFPConv4Frm:
1294    // Encode Dn / Sn.
1295    Binary |= encodeVFPRn(MI, 0);
1296    break;
1297  case ARMII::VFPConv5Frm:
1298    // Encode Dm / Sm.
1299    Binary |= encodeVFPRm(MI, 0);
1300    break;
1301  }
1302
1303  switch (Form) {
1304  default: break;
1305  case ARMII::VFPConv1Frm:
1306    // Encode Dm / Sm.
1307    Binary |= encodeVFPRm(MI, 1);
1308    break;
1309  case ARMII::VFPConv2Frm:
1310  case ARMII::VFPConv3Frm:
1311    // Encode Dn / Sn.
1312    Binary |= encodeVFPRn(MI, 1);
1313    break;
1314  case ARMII::VFPConv4Frm:
1315  case ARMII::VFPConv5Frm:
1316    // Encode Dd / Sd.
1317    Binary |= encodeVFPRd(MI, 1);
1318    break;
1319  }
1320
1321  if (Form == ARMII::VFPConv5Frm)
1322    // Encode Dn / Sn.
1323    Binary |= encodeVFPRn(MI, 2);
1324  else if (Form == ARMII::VFPConv3Frm)
1325    // Encode Dm / Sm.
1326    Binary |= encodeVFPRm(MI, 2);
1327
1328  emitWordLE(Binary);
1329}
1330
1331template<class CodeEmitter>
1332void Emitter<CodeEmitter>::emitVFPLoadStoreInstruction(const MachineInstr &MI) {
1333  // Part of binary is determined by TableGn.
1334  unsigned Binary = getBinaryCodeForInstr(MI);
1335
1336  // Set the conditional execution predicate
1337  Binary |= II->getPredicate(&MI) << ARMII::CondShift;
1338
1339  unsigned OpIdx = 0;
1340
1341  // Encode Dd / Sd.
1342  Binary |= encodeVFPRd(MI, OpIdx++);
1343
1344  // Encode address base.
1345  const MachineOperand &Base = MI.getOperand(OpIdx++);
1346  Binary |= getMachineOpValue(MI, Base) << ARMII::RegRnShift;
1347
1348  // If there is a non-zero immediate offset, encode it.
1349  if (Base.isReg()) {
1350    const MachineOperand &Offset = MI.getOperand(OpIdx);
1351    if (unsigned ImmOffs = ARM_AM::getAM5Offset(Offset.getImm())) {
1352      if (ARM_AM::getAM5Op(Offset.getImm()) == ARM_AM::add)
1353        Binary |= 1 << ARMII::U_BitShift;
1354      Binary |= ImmOffs;
1355      emitWordLE(Binary);
1356      return;
1357    }
1358  }
1359
1360  // If immediate offset is omitted, default to +0.
1361  Binary |= 1 << ARMII::U_BitShift;
1362
1363  emitWordLE(Binary);
1364}
1365
1366template<class CodeEmitter>
1367void Emitter<CodeEmitter>::emitVFPLoadStoreMultipleInstruction(
1368                                                       const MachineInstr &MI) {
1369  // Part of binary is determined by TableGn.
1370  unsigned Binary = getBinaryCodeForInstr(MI);
1371
1372  // Set the conditional execution predicate
1373  Binary |= II->getPredicate(&MI) << ARMII::CondShift;
1374
1375  // Set base address operand
1376  Binary |= getMachineOpValue(MI, 0) << ARMII::RegRnShift;
1377
1378  // Set addressing mode by modifying bits U(23) and P(24)
1379  const MachineOperand &MO = MI.getOperand(1);
1380  Binary |= getAddrModeUPBits(ARM_AM::getAM5SubMode(MO.getImm()));
1381
1382  // Set bit W(21)
1383  if (ARM_AM::getAM5WBFlag(MO.getImm()))
1384    Binary |= 0x1 << ARMII::W_BitShift;
1385
1386  // First register is encoded in Dd.
1387  Binary |= encodeVFPRd(MI, 4);
1388
1389  // Number of registers are encoded in offset field.
1390  unsigned NumRegs = 1;
1391  for (unsigned i = 5, e = MI.getNumOperands(); i != e; ++i) {
1392    const MachineOperand &MO = MI.getOperand(i);
1393    if (!MO.isReg() || MO.isImplicit())
1394      break;
1395    ++NumRegs;
1396  }
1397  Binary |= NumRegs * 2;
1398
1399  emitWordLE(Binary);
1400}
1401
1402template<class CodeEmitter>
1403void Emitter<CodeEmitter>::emitMiscInstruction(const MachineInstr &MI) {
1404  // Part of binary is determined by TableGn.
1405  unsigned Binary = getBinaryCodeForInstr(MI);
1406
1407  // Set the conditional execution predicate
1408  Binary |= II->getPredicate(&MI) << ARMII::CondShift;
1409
1410  emitWordLE(Binary);
1411}
1412
1413#include "ARMGenCodeEmitter.inc"
1414