ARMCodeEmitter.cpp revision eaf1c98a7c38444d41d1c6dc2074736eec7d452f 
1//===-- ARM/ARMCodeEmitter.cpp - Convert ARM code to machine code ---------===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file contains the pass that transforms the ARM machine instructions into
11// relocatable machine code.
12//
13//===----------------------------------------------------------------------===//
14
15#define DEBUG_TYPE "jit"
16#include "ARM.h"
17#include "ARMAddressingModes.h"
18#include "ARMConstantPoolValue.h"
19#include "ARMInstrInfo.h"
20#include "ARMRelocations.h"
21#include "ARMSubtarget.h"
22#include "ARMTargetMachine.h"
23#include "llvm/Constants.h"
24#include "llvm/DerivedTypes.h"
25#include "llvm/Function.h"
26#include "llvm/PassManager.h"
27#include "llvm/CodeGen/JITCodeEmitter.h"
28#include "llvm/CodeGen/MachineConstantPool.h"
29#include "llvm/CodeGen/MachineFunctionPass.h"
30#include "llvm/CodeGen/MachineInstr.h"
31#include "llvm/CodeGen/MachineJumpTableInfo.h"
32#include "llvm/CodeGen/MachineModuleInfo.h"
33#include "llvm/CodeGen/Passes.h"
34#include "llvm/ADT/Statistic.h"
35#include "llvm/Support/Debug.h"
36#include "llvm/Support/ErrorHandling.h"
37#include "llvm/Support/raw_ostream.h"
38#ifndef NDEBUG
39#include <iomanip>
40#endif
41using namespace llvm;
42
43STATISTIC(NumEmitted, "Number of machine instructions emitted");
44
45namespace {
46
47  class ARMCodeEmitter : public MachineFunctionPass {
48    ARMJITInfo                *JTI;
49    const ARMInstrInfo        *II;
50    const TargetData          *TD;
51    const ARMSubtarget        *Subtarget;
52    TargetMachine             &TM;
53    JITCodeEmitter            &MCE;
54    MachineModuleInfo *MMI;
55    const std::vector<MachineConstantPoolEntry> *MCPEs;
56    const std::vector<MachineJumpTableEntry> *MJTEs;
57    bool IsPIC;
58    bool IsThumb;
59
60    void getAnalysisUsage(AnalysisUsage &AU) const {
61      AU.addRequired<MachineModuleInfo>();
62      MachineFunctionPass::getAnalysisUsage(AU);
63    }
64
65    static char ID;
66  public:
67    ARMCodeEmitter(TargetMachine &tm, JITCodeEmitter &mce)
68      : MachineFunctionPass(ID), JTI(0),
69        II((const ARMInstrInfo *)tm.getInstrInfo()),
70        TD(tm.getTargetData()), TM(tm),
71        MCE(mce), MCPEs(0), MJTEs(0),
72        IsPIC(TM.getRelocationModel() == Reloc::PIC_), IsThumb(false) {}
73
74    /// getBinaryCodeForInstr - This function, generated by the
75    /// CodeEmitterGenerator using TableGen, produces the binary encoding for
76    /// machine instructions.
77    unsigned getBinaryCodeForInstr(const MachineInstr &MI);
78
79    bool runOnMachineFunction(MachineFunction &MF);
80
81    virtual const char *getPassName() const {
82      return "ARM Machine Code Emitter";
83    }
84
85    void emitInstruction(const MachineInstr &MI);
86
87  private:
88
89    void emitWordLE(unsigned Binary);
90    void emitDWordLE(uint64_t Binary);
91    void emitConstPoolInstruction(const MachineInstr &MI);
92    void emitMOVi32immInstruction(const MachineInstr &MI);
93    void emitMOVi2piecesInstruction(const MachineInstr &MI);
94    void emitLEApcrelJTInstruction(const MachineInstr &MI);
95    void emitPseudoMoveInstruction(const MachineInstr &MI);
96    void addPCLabel(unsigned LabelID);
97    void emitPseudoInstruction(const MachineInstr &MI);
98    unsigned getMachineSoRegOpValue(const MachineInstr &MI,
99                                    const TargetInstrDesc &TID,
100                                    const MachineOperand &MO,
101                                    unsigned OpIdx);
102
103    unsigned getMachineSoImmOpValue(unsigned SoImm);
104
105    unsigned getAddrModeSBit(const MachineInstr &MI,
106                             const TargetInstrDesc &TID) const;
107
108    void emitDataProcessingInstruction(const MachineInstr &MI,
109                                       unsigned ImplicitRd = 0,
110                                       unsigned ImplicitRn = 0);
111
112    void emitLoadStoreInstruction(const MachineInstr &MI,
113                                  unsigned ImplicitRd = 0,
114                                  unsigned ImplicitRn = 0);
115
116    void emitMiscLoadStoreInstruction(const MachineInstr &MI,
117                                      unsigned ImplicitRn = 0);
118
119    void emitLoadStoreMultipleInstruction(const MachineInstr &MI);
120
121    void emitMulFrmInstruction(const MachineInstr &MI);
122
123    void emitExtendInstruction(const MachineInstr &MI);
124
125    void emitMiscArithInstruction(const MachineInstr &MI);
126
127    void emitSaturateInstruction(const MachineInstr &MI);
128
129    void emitBranchInstruction(const MachineInstr &MI);
130
131    void emitInlineJumpTable(unsigned JTIndex);
132
133    void emitMiscBranchInstruction(const MachineInstr &MI);
134
135    void emitVFPArithInstruction(const MachineInstr &MI);
136
137    void emitVFPConversionInstruction(const MachineInstr &MI);
138
139    void emitVFPLoadStoreInstruction(const MachineInstr &MI);
140
141    void emitVFPLoadStoreMultipleInstruction(const MachineInstr &MI);
142
143    void emitMiscInstruction(const MachineInstr &MI);
144
145    void emitNEONLaneInstruction(const MachineInstr &MI);
146    void emitNEONDupInstruction(const MachineInstr &MI);
147    void emitNEON1RegModImmInstruction(const MachineInstr &MI);
148    void emitNEON2RegInstruction(const MachineInstr &MI);
149    void emitNEON3RegInstruction(const MachineInstr &MI);
150
151    /// getMachineOpValue - Return binary encoding of operand. If the machine
152    /// operand requires relocation, record the relocation and return zero.
153    unsigned getMachineOpValue(const MachineInstr &MI,const MachineOperand &MO);
154    unsigned getMachineOpValue(const MachineInstr &MI, unsigned OpIdx) {
155      return getMachineOpValue(MI, MI.getOperand(OpIdx));
156    }
157
158    /// getMovi32Value - Return binary encoding of operand for movw/movt. If the
159    /// machine operand requires relocation, record the relocation and return
160    /// zero.
161    unsigned getMovi32Value(const MachineInstr &MI,const MachineOperand &MO,
162                            unsigned Reloc);
163    unsigned getMovi32Value(const MachineInstr &MI, unsigned OpIdx,
164                            unsigned Reloc) {
165      return getMovi32Value(MI, MI.getOperand(OpIdx), Reloc);
166    }
167
168    /// getShiftOp - Return the shift opcode (bit[6:5]) of the immediate value.
169    ///
170    unsigned getShiftOp(unsigned Imm) const ;
171
172    /// Routines that handle operands which add machine relocations which are
173    /// fixed up by the relocation stage.
174    void emitGlobalAddress(const GlobalValue *GV, unsigned Reloc,
175                           bool MayNeedFarStub,  bool Indirect,
176                           intptr_t ACPV = 0);
177    void emitExternalSymbolAddress(const char *ES, unsigned Reloc);
178    void emitConstPoolAddress(unsigned CPI, unsigned Reloc);
179    void emitJumpTableAddress(unsigned JTIndex, unsigned Reloc);
180    void emitMachineBasicBlock(MachineBasicBlock *BB, unsigned Reloc,
181                               intptr_t JTBase = 0);
182  };
183}
184
185char ARMCodeEmitter::ID = 0;
186
187/// createARMJITCodeEmitterPass - Return a pass that emits the collected ARM
188/// code to the specified MCE object.
189FunctionPass *llvm::createARMJITCodeEmitterPass(ARMBaseTargetMachine &TM,
190                                                JITCodeEmitter &JCE) {
191  return new ARMCodeEmitter(TM, JCE);
192}
193
194bool ARMCodeEmitter::runOnMachineFunction(MachineFunction &MF) {
195  assert((MF.getTarget().getRelocationModel() != Reloc::Default ||
196          MF.getTarget().getRelocationModel() != Reloc::Static) &&
197         "JIT relocation model must be set to static or default!");
198  JTI = ((ARMTargetMachine &)MF.getTarget()).getJITInfo();
199  II = ((const ARMTargetMachine &)MF.getTarget()).getInstrInfo();
200  TD = ((const ARMTargetMachine &)MF.getTarget()).getTargetData();
201  Subtarget = &TM.getSubtarget<ARMSubtarget>();
202  MCPEs = &MF.getConstantPool()->getConstants();
203  MJTEs = 0;
204  if (MF.getJumpTableInfo()) MJTEs = &MF.getJumpTableInfo()->getJumpTables();
205  IsPIC = TM.getRelocationModel() == Reloc::PIC_;
206  IsThumb = MF.getInfo<ARMFunctionInfo>()->isThumbFunction();
207  JTI->Initialize(MF, IsPIC);
208  MMI = &getAnalysis<MachineModuleInfo>();
209  MCE.setModuleInfo(MMI);
210
211  do {
212    DEBUG(errs() << "JITTing function '"
213          << MF.getFunction()->getName() << "'\n");
214    MCE.startFunction(MF);
215    for (MachineFunction::iterator MBB = MF.begin(), E = MF.end();
216         MBB != E; ++MBB) {
217      MCE.StartMachineBasicBlock(MBB);
218      for (MachineBasicBlock::const_iterator I = MBB->begin(), E = MBB->end();
219           I != E; ++I)
220        emitInstruction(*I);
221    }
222  } while (MCE.finishFunction(MF));
223
224  return false;
225}
226
227/// getShiftOp - Return the shift opcode (bit[6:5]) of the immediate value.
228///
229unsigned ARMCodeEmitter::getShiftOp(unsigned Imm) const {
230  switch (ARM_AM::getAM2ShiftOpc(Imm)) {
231  default: llvm_unreachable("Unknown shift opc!");
232  case ARM_AM::asr: return 2;
233  case ARM_AM::lsl: return 0;
234  case ARM_AM::lsr: return 1;
235  case ARM_AM::ror:
236  case ARM_AM::rrx: return 3;
237  }
238  return 0;
239}
240
241/// getMovi32Value - Return binary encoding of operand for movw/movt. If the
242/// machine operand requires relocation, record the relocation and return zero.
243unsigned ARMCodeEmitter::getMovi32Value(const MachineInstr &MI,
244                                        const MachineOperand &MO,
245                                        unsigned Reloc) {
246  assert(((Reloc == ARM::reloc_arm_movt) || (Reloc == ARM::reloc_arm_movw))
247      && "Relocation to this function should be for movt or movw");
248
249  if (MO.isImm())
250    return static_cast<unsigned>(MO.getImm());
251  else if (MO.isGlobal())
252    emitGlobalAddress(MO.getGlobal(), Reloc, true, false);
253  else if (MO.isSymbol())
254    emitExternalSymbolAddress(MO.getSymbolName(), Reloc);
255  else if (MO.isMBB())
256    emitMachineBasicBlock(MO.getMBB(), Reloc);
257  else {
258#ifndef NDEBUG
259    errs() << MO;
260#endif
261    llvm_unreachable("Unsupported operand type for movw/movt");
262  }
263  return 0;
264}
265
266/// getMachineOpValue - Return binary encoding of operand. If the machine
267/// operand requires relocation, record the relocation and return zero.
268unsigned ARMCodeEmitter::getMachineOpValue(const MachineInstr &MI,
269                                           const MachineOperand &MO) {
270  if (MO.isReg())
271    return ARMRegisterInfo::getRegisterNumbering(MO.getReg());
272  else if (MO.isImm())
273    return static_cast<unsigned>(MO.getImm());
274  else if (MO.isGlobal())
275    emitGlobalAddress(MO.getGlobal(), ARM::reloc_arm_branch, true, false);
276  else if (MO.isSymbol())
277    emitExternalSymbolAddress(MO.getSymbolName(), ARM::reloc_arm_branch);
278  else if (MO.isCPI()) {
279    const TargetInstrDesc &TID = MI.getDesc();
280    // For VFP load, the immediate offset is multiplied by 4.
281    unsigned Reloc =  ((TID.TSFlags & ARMII::FormMask) == ARMII::VFPLdStFrm)
282      ? ARM::reloc_arm_vfp_cp_entry : ARM::reloc_arm_cp_entry;
283    emitConstPoolAddress(MO.getIndex(), Reloc);
284  } else if (MO.isJTI())
285    emitJumpTableAddress(MO.getIndex(), ARM::reloc_arm_relative);
286  else if (MO.isMBB())
287    emitMachineBasicBlock(MO.getMBB(), ARM::reloc_arm_branch);
288  else {
289#ifndef NDEBUG
290    errs() << MO;
291#endif
292    llvm_unreachable(0);
293  }
294  return 0;
295}
296
297/// emitGlobalAddress - Emit the specified address to the code stream.
298///
299void ARMCodeEmitter::emitGlobalAddress(const GlobalValue *GV, unsigned Reloc,
300                                       bool MayNeedFarStub, bool Indirect,
301                                       intptr_t ACPV) {
302  MachineRelocation MR = Indirect
303    ? MachineRelocation::getIndirectSymbol(MCE.getCurrentPCOffset(), Reloc,
304                                           const_cast<GlobalValue *>(GV),
305                                           ACPV, MayNeedFarStub)
306    : MachineRelocation::getGV(MCE.getCurrentPCOffset(), Reloc,
307                               const_cast<GlobalValue *>(GV), ACPV,
308                               MayNeedFarStub);
309  MCE.addRelocation(MR);
310}
311
312/// emitExternalSymbolAddress - Arrange for the address of an external symbol to
313/// be emitted to the current location in the function, and allow it to be PC
314/// relative.
315void ARMCodeEmitter::emitExternalSymbolAddress(const char *ES, unsigned Reloc) {
316  MCE.addRelocation(MachineRelocation::getExtSym(MCE.getCurrentPCOffset(),
317                                                 Reloc, ES));
318}
319
320/// emitConstPoolAddress - Arrange for the address of an constant pool
321/// to be emitted to the current location in the function, and allow it to be PC
322/// relative.
323void ARMCodeEmitter::emitConstPoolAddress(unsigned CPI, unsigned Reloc) {
324  // Tell JIT emitter we'll resolve the address.
325  MCE.addRelocation(MachineRelocation::getConstPool(MCE.getCurrentPCOffset(),
326                                                    Reloc, CPI, 0, true));
327}
328
329/// emitJumpTableAddress - Arrange for the address of a jump table to
330/// be emitted to the current location in the function, and allow it to be PC
331/// relative.
332void ARMCodeEmitter::emitJumpTableAddress(unsigned JTIndex, unsigned Reloc) {
333  MCE.addRelocation(MachineRelocation::getJumpTable(MCE.getCurrentPCOffset(),
334                                                    Reloc, JTIndex, 0, true));
335}
336
337/// emitMachineBasicBlock - Emit the specified address basic block.
338void ARMCodeEmitter::emitMachineBasicBlock(MachineBasicBlock *BB,
339                                           unsigned Reloc, intptr_t JTBase) {
340  MCE.addRelocation(MachineRelocation::getBB(MCE.getCurrentPCOffset(),
341                                             Reloc, BB, JTBase));
342}
343
344void ARMCodeEmitter::emitWordLE(unsigned Binary) {
345  DEBUG(errs() << "  0x";
346        errs().write_hex(Binary) << "\n");
347  MCE.emitWordLE(Binary);
348}
349
350void ARMCodeEmitter::emitDWordLE(uint64_t Binary) {
351  DEBUG(errs() << "  0x";
352        errs().write_hex(Binary) << "\n");
353  MCE.emitDWordLE(Binary);
354}
355
356void ARMCodeEmitter::emitInstruction(const MachineInstr &MI) {
357  DEBUG(errs() << "JIT: " << (void*)MCE.getCurrentPCValue() << ":\t" << MI);
358
359  MCE.processDebugLoc(MI.getDebugLoc(), true);
360
361  ++NumEmitted;  // Keep track of the # of mi's emitted
362  switch (MI.getDesc().TSFlags & ARMII::FormMask) {
363  default: {
364    llvm_unreachable("Unhandled instruction encoding format!");
365    break;
366  }
367  case ARMII::Pseudo:
368    emitPseudoInstruction(MI);
369    break;
370  case ARMII::DPFrm:
371  case ARMII::DPSoRegFrm:
372    emitDataProcessingInstruction(MI);
373    break;
374  case ARMII::LdFrm:
375  case ARMII::StFrm:
376    emitLoadStoreInstruction(MI);
377    break;
378  case ARMII::LdMiscFrm:
379  case ARMII::StMiscFrm:
380    emitMiscLoadStoreInstruction(MI);
381    break;
382  case ARMII::LdStMulFrm:
383    emitLoadStoreMultipleInstruction(MI);
384    break;
385  case ARMII::MulFrm:
386    emitMulFrmInstruction(MI);
387    break;
388  case ARMII::ExtFrm:
389    emitExtendInstruction(MI);
390    break;
391  case ARMII::ArithMiscFrm:
392    emitMiscArithInstruction(MI);
393    break;
394  case ARMII::SatFrm:
395    emitSaturateInstruction(MI);
396    break;
397  case ARMII::BrFrm:
398    emitBranchInstruction(MI);
399    break;
400  case ARMII::BrMiscFrm:
401    emitMiscBranchInstruction(MI);
402    break;
403  // VFP instructions.
404  case ARMII::VFPUnaryFrm:
405  case ARMII::VFPBinaryFrm:
406    emitVFPArithInstruction(MI);
407    break;
408  case ARMII::VFPConv1Frm:
409  case ARMII::VFPConv2Frm:
410  case ARMII::VFPConv3Frm:
411  case ARMII::VFPConv4Frm:
412  case ARMII::VFPConv5Frm:
413    emitVFPConversionInstruction(MI);
414    break;
415  case ARMII::VFPLdStFrm:
416    emitVFPLoadStoreInstruction(MI);
417    break;
418  case ARMII::VFPLdStMulFrm:
419    emitVFPLoadStoreMultipleInstruction(MI);
420    break;
421  case ARMII::VFPMiscFrm:
422    emitMiscInstruction(MI);
423    break;
424  // NEON instructions.
425  case ARMII::NGetLnFrm:
426  case ARMII::NSetLnFrm:
427    emitNEONLaneInstruction(MI);
428    break;
429  case ARMII::NDupFrm:
430    emitNEONDupInstruction(MI);
431    break;
432  case ARMII::N1RegModImmFrm:
433    emitNEON1RegModImmInstruction(MI);
434    break;
435  case ARMII::N2RegFrm:
436    emitNEON2RegInstruction(MI);
437    break;
438  case ARMII::N3RegFrm:
439    emitNEON3RegInstruction(MI);
440    break;
441  }
442  MCE.processDebugLoc(MI.getDebugLoc(), false);
443}
444
445void ARMCodeEmitter::emitConstPoolInstruction(const MachineInstr &MI) {
446  unsigned CPI = MI.getOperand(0).getImm();       // CP instruction index.
447  unsigned CPIndex = MI.getOperand(1).getIndex(); // Actual cp entry index.
448  const MachineConstantPoolEntry &MCPE = (*MCPEs)[CPIndex];
449
450  // Remember the CONSTPOOL_ENTRY address for later relocation.
451  JTI->addConstantPoolEntryAddr(CPI, MCE.getCurrentPCValue());
452
453  // Emit constpool island entry. In most cases, the actual values will be
454  // resolved and relocated after code emission.
455  if (MCPE.isMachineConstantPoolEntry()) {
456    ARMConstantPoolValue *ACPV =
457      static_cast<ARMConstantPoolValue*>(MCPE.Val.MachineCPVal);
458
459    DEBUG(errs() << "  ** ARM constant pool #" << CPI << " @ "
460          << (void*)MCE.getCurrentPCValue() << " " << *ACPV << '\n');
461
462    assert(ACPV->isGlobalValue() && "unsupported constant pool value");
463    const GlobalValue *GV = ACPV->getGV();
464    if (GV) {
465      Reloc::Model RelocM = TM.getRelocationModel();
466      emitGlobalAddress(GV, ARM::reloc_arm_machine_cp_entry,
467                        isa<Function>(GV),
468                        Subtarget->GVIsIndirectSymbol(GV, RelocM),
469                        (intptr_t)ACPV);
470     } else  {
471      emitExternalSymbolAddress(ACPV->getSymbol(), ARM::reloc_arm_absolute);
472    }
473    emitWordLE(0);
474  } else {
475    const Constant *CV = MCPE.Val.ConstVal;
476
477    DEBUG({
478        errs() << "  ** Constant pool #" << CPI << " @ "
479               << (void*)MCE.getCurrentPCValue() << " ";
480        if (const Function *F = dyn_cast<Function>(CV))
481          errs() << F->getName();
482        else
483          errs() << *CV;
484        errs() << '\n';
485      });
486
487    if (const GlobalValue *GV = dyn_cast<GlobalValue>(CV)) {
488      emitGlobalAddress(GV, ARM::reloc_arm_absolute, isa<Function>(GV), false);
489      emitWordLE(0);
490    } else if (const ConstantInt *CI = dyn_cast<ConstantInt>(CV)) {
491      uint32_t Val = *(uint32_t*)CI->getValue().getRawData();
492      emitWordLE(Val);
493    } else if (const ConstantFP *CFP = dyn_cast<ConstantFP>(CV)) {
494      if (CFP->getType()->isFloatTy())
495        emitWordLE(CFP->getValueAPF().bitcastToAPInt().getZExtValue());
496      else if (CFP->getType()->isDoubleTy())
497        emitDWordLE(CFP->getValueAPF().bitcastToAPInt().getZExtValue());
498      else {
499        llvm_unreachable("Unable to handle this constantpool entry!");
500      }
501    } else {
502      llvm_unreachable("Unable to handle this constantpool entry!");
503    }
504  }
505}
506
507void ARMCodeEmitter::emitMOVi32immInstruction(const MachineInstr &MI) {
508  const MachineOperand &MO0 = MI.getOperand(0);
509  const MachineOperand &MO1 = MI.getOperand(1);
510
511  // Emit the 'movw' instruction.
512  unsigned Binary = 0x30 << 20;  // mov: Insts{27-20} = 0b00110000
513
514  unsigned Lo16 = getMovi32Value(MI, MO1, ARM::reloc_arm_movw) & 0xFFFF;
515
516  // Set the conditional execution predicate.
517  Binary |= II->getPredicate(&MI) << ARMII::CondShift;
518
519  // Encode Rd.
520  Binary |= getMachineOpValue(MI, MO0) << ARMII::RegRdShift;
521
522  // Encode imm16 as imm4:imm12
523  Binary |= Lo16 & 0xFFF; // Insts{11-0} = imm12
524  Binary |= ((Lo16 >> 12) & 0xF) << 16; // Insts{19-16} = imm4
525  emitWordLE(Binary);
526
527  unsigned Hi16 = getMovi32Value(MI, MO1, ARM::reloc_arm_movt) >> 16;
528  // Emit the 'movt' instruction.
529  Binary = 0x34 << 20; // movt: Insts{27-20} = 0b00110100
530
531  // Set the conditional execution predicate.
532  Binary |= II->getPredicate(&MI) << ARMII::CondShift;
533
534  // Encode Rd.
535  Binary |= getMachineOpValue(MI, MO0) << ARMII::RegRdShift;
536
537  // Encode imm16 as imm4:imm1, same as movw above.
538  Binary |= Hi16 & 0xFFF;
539  Binary |= ((Hi16 >> 12) & 0xF) << 16;
540  emitWordLE(Binary);
541}
542
543void ARMCodeEmitter::emitMOVi2piecesInstruction(const MachineInstr &MI) {
544  const MachineOperand &MO0 = MI.getOperand(0);
545  const MachineOperand &MO1 = MI.getOperand(1);
546  assert(MO1.isImm() && ARM_AM::isSOImmTwoPartVal(MO1.getImm()) &&
547                                                  "Not a valid so_imm value!");
548  unsigned V1 = ARM_AM::getSOImmTwoPartFirst(MO1.getImm());
549  unsigned V2 = ARM_AM::getSOImmTwoPartSecond(MO1.getImm());
550
551  // Emit the 'mov' instruction.
552  unsigned Binary = 0xd << 21;  // mov: Insts{24-21} = 0b1101
553
554  // Set the conditional execution predicate.
555  Binary |= II->getPredicate(&MI) << ARMII::CondShift;
556
557  // Encode Rd.
558  Binary |= getMachineOpValue(MI, MO0) << ARMII::RegRdShift;
559
560  // Encode so_imm.
561  // Set bit I(25) to identify this is the immediate form of <shifter_op>
562  Binary |= 1 << ARMII::I_BitShift;
563  Binary |= getMachineSoImmOpValue(V1);
564  emitWordLE(Binary);
565
566  // Now the 'orr' instruction.
567  Binary = 0xc << 21;  // orr: Insts{24-21} = 0b1100
568
569  // Set the conditional execution predicate.
570  Binary |= II->getPredicate(&MI) << ARMII::CondShift;
571
572  // Encode Rd.
573  Binary |= getMachineOpValue(MI, MO0) << ARMII::RegRdShift;
574
575  // Encode Rn.
576  Binary |= getMachineOpValue(MI, MO0) << ARMII::RegRnShift;
577
578  // Encode so_imm.
579  // Set bit I(25) to identify this is the immediate form of <shifter_op>
580  Binary |= 1 << ARMII::I_BitShift;
581  Binary |= getMachineSoImmOpValue(V2);
582  emitWordLE(Binary);
583}
584
585void ARMCodeEmitter::emitLEApcrelJTInstruction(const MachineInstr &MI) {
586  // It's basically add r, pc, (LJTI - $+8)
587
588  const TargetInstrDesc &TID = MI.getDesc();
589
590  // Emit the 'add' instruction.
591  unsigned Binary = 0x4 << 21;  // add: Insts{24-31} = 0b0100
592
593  // Set the conditional execution predicate
594  Binary |= II->getPredicate(&MI) << ARMII::CondShift;
595
596  // Encode S bit if MI modifies CPSR.
597  Binary |= getAddrModeSBit(MI, TID);
598
599  // Encode Rd.
600  Binary |= getMachineOpValue(MI, 0) << ARMII::RegRdShift;
601
602  // Encode Rn which is PC.
603  Binary |= ARMRegisterInfo::getRegisterNumbering(ARM::PC) << ARMII::RegRnShift;
604
605  // Encode the displacement.
606  Binary |= 1 << ARMII::I_BitShift;
607  emitJumpTableAddress(MI.getOperand(1).getIndex(), ARM::reloc_arm_jt_base);
608
609  emitWordLE(Binary);
610}
611
612void ARMCodeEmitter::emitPseudoMoveInstruction(const MachineInstr &MI) {
613  unsigned Opcode = MI.getDesc().Opcode;
614
615  // Part of binary is determined by TableGn.
616  unsigned Binary = getBinaryCodeForInstr(MI);
617
618  // Set the conditional execution predicate
619  Binary |= II->getPredicate(&MI) << ARMII::CondShift;
620
621  // Encode S bit if MI modifies CPSR.
622  if (Opcode == ARM::MOVsrl_flag || Opcode == ARM::MOVsra_flag)
623    Binary |= 1 << ARMII::S_BitShift;
624
625  // Encode register def if there is one.
626  Binary |= getMachineOpValue(MI, 0) << ARMII::RegRdShift;
627
628  // Encode the shift operation.
629  switch (Opcode) {
630  default: break;
631  case ARM::MOVrx:
632    // rrx
633    Binary |= 0x6 << 4;
634    break;
635  case ARM::MOVsrl_flag:
636    // lsr #1
637    Binary |= (0x2 << 4) | (1 << 7);
638    break;
639  case ARM::MOVsra_flag:
640    // asr #1
641    Binary |= (0x4 << 4) | (1 << 7);
642    break;
643  }
644
645  // Encode register Rm.
646  Binary |= getMachineOpValue(MI, 1);
647
648  emitWordLE(Binary);
649}
650
651void ARMCodeEmitter::addPCLabel(unsigned LabelID) {
652  DEBUG(errs() << "  ** LPC" << LabelID << " @ "
653        << (void*)MCE.getCurrentPCValue() << '\n');
654  JTI->addPCLabelAddr(LabelID, MCE.getCurrentPCValue());
655}
656
657void ARMCodeEmitter::emitPseudoInstruction(const MachineInstr &MI) {
658  unsigned Opcode = MI.getDesc().Opcode;
659  switch (Opcode) {
660  default:
661    llvm_unreachable("ARMCodeEmitter::emitPseudoInstruction");
662  case ARM::BX:
663  case ARM::BMOVPCRX:
664  case ARM::BXr9:
665  case ARM::BMOVPCRXr9: {
666    // First emit mov lr, pc
667    unsigned Binary = 0x01a0e00f;
668    Binary |= II->getPredicate(&MI) << ARMII::CondShift;
669    emitWordLE(Binary);
670
671    // and then emit the branch.
672    emitMiscBranchInstruction(MI);
673    break;
674  }
675  case TargetOpcode::INLINEASM: {
676    // We allow inline assembler nodes with empty bodies - they can
677    // implicitly define registers, which is ok for JIT.
678    if (MI.getOperand(0).getSymbolName()[0]) {
679      report_fatal_error("JIT does not support inline asm!");
680    }
681    break;
682  }
683  case TargetOpcode::PROLOG_LABEL:
684  case TargetOpcode::EH_LABEL:
685    MCE.emitLabel(MI.getOperand(0).getMCSymbol());
686    break;
687  case TargetOpcode::IMPLICIT_DEF:
688  case TargetOpcode::KILL:
689    // Do nothing.
690    break;
691  case ARM::CONSTPOOL_ENTRY:
692    emitConstPoolInstruction(MI);
693    break;
694  case ARM::PICADD: {
695    // Remember of the address of the PC label for relocation later.
696    addPCLabel(MI.getOperand(2).getImm());
697    // PICADD is just an add instruction that implicitly read pc.
698    emitDataProcessingInstruction(MI, 0, ARM::PC);
699    break;
700  }
701  case ARM::PICLDR:
702  case ARM::PICLDRB:
703  case ARM::PICSTR:
704  case ARM::PICSTRB: {
705    // Remember of the address of the PC label for relocation later.
706    addPCLabel(MI.getOperand(2).getImm());
707    // These are just load / store instructions that implicitly read pc.
708    emitLoadStoreInstruction(MI, 0, ARM::PC);
709    break;
710  }
711  case ARM::PICLDRH:
712  case ARM::PICLDRSH:
713  case ARM::PICLDRSB:
714  case ARM::PICSTRH: {
715    // Remember of the address of the PC label for relocation later.
716    addPCLabel(MI.getOperand(2).getImm());
717    // These are just load / store instructions that implicitly read pc.
718    emitMiscLoadStoreInstruction(MI, ARM::PC);
719    break;
720  }
721
722  case ARM::MOVi32imm:
723    emitMOVi32immInstruction(MI);
724    break;
725
726  case ARM::MOVi2pieces:
727    // Two instructions to materialize a constant.
728    emitMOVi2piecesInstruction(MI);
729    break;
730  case ARM::LEApcrelJT:
731    // Materialize jumptable address.
732    emitLEApcrelJTInstruction(MI);
733    break;
734  case ARM::MOVrx:
735  case ARM::MOVsrl_flag:
736  case ARM::MOVsra_flag:
737    emitPseudoMoveInstruction(MI);
738    break;
739  }
740}
741
742unsigned ARMCodeEmitter::getMachineSoRegOpValue(const MachineInstr &MI,
743                                                const TargetInstrDesc &TID,
744                                                const MachineOperand &MO,
745                                                unsigned OpIdx) {
746  unsigned Binary = getMachineOpValue(MI, MO);
747
748  const MachineOperand &MO1 = MI.getOperand(OpIdx + 1);
749  const MachineOperand &MO2 = MI.getOperand(OpIdx + 2);
750  ARM_AM::ShiftOpc SOpc = ARM_AM::getSORegShOp(MO2.getImm());
751
752  // Encode the shift opcode.
753  unsigned SBits = 0;
754  unsigned Rs = MO1.getReg();
755  if (Rs) {
756    // Set shift operand (bit[7:4]).
757    // LSL - 0001
758    // LSR - 0011
759    // ASR - 0101
760    // ROR - 0111
761    // RRX - 0110 and bit[11:8] clear.
762    switch (SOpc) {
763    default: llvm_unreachable("Unknown shift opc!");
764    case ARM_AM::lsl: SBits = 0x1; break;
765    case ARM_AM::lsr: SBits = 0x3; break;
766    case ARM_AM::asr: SBits = 0x5; break;
767    case ARM_AM::ror: SBits = 0x7; break;
768    case ARM_AM::rrx: SBits = 0x6; break;
769    }
770  } else {
771    // Set shift operand (bit[6:4]).
772    // LSL - 000
773    // LSR - 010
774    // ASR - 100
775    // ROR - 110
776    switch (SOpc) {
777    default: llvm_unreachable("Unknown shift opc!");
778    case ARM_AM::lsl: SBits = 0x0; break;
779    case ARM_AM::lsr: SBits = 0x2; break;
780    case ARM_AM::asr: SBits = 0x4; break;
781    case ARM_AM::ror: SBits = 0x6; break;
782    }
783  }
784  Binary |= SBits << 4;
785  if (SOpc == ARM_AM::rrx)
786    return Binary;
787
788  // Encode the shift operation Rs or shift_imm (except rrx).
789  if (Rs) {
790    // Encode Rs bit[11:8].
791    assert(ARM_AM::getSORegOffset(MO2.getImm()) == 0);
792    return Binary |
793      (ARMRegisterInfo::getRegisterNumbering(Rs) << ARMII::RegRsShift);
794  }
795
796  // Encode shift_imm bit[11:7].
797  return Binary | ARM_AM::getSORegOffset(MO2.getImm()) << 7;
798}
799
800unsigned ARMCodeEmitter::getMachineSoImmOpValue(unsigned SoImm) {
801  int SoImmVal = ARM_AM::getSOImmVal(SoImm);
802  assert(SoImmVal != -1 && "Not a valid so_imm value!");
803
804  // Encode rotate_imm.
805  unsigned Binary = (ARM_AM::getSOImmValRot((unsigned)SoImmVal) >> 1)
806    << ARMII::SoRotImmShift;
807
808  // Encode immed_8.
809  Binary |= ARM_AM::getSOImmValImm((unsigned)SoImmVal);
810  return Binary;
811}
812
813unsigned ARMCodeEmitter::getAddrModeSBit(const MachineInstr &MI,
814                                         const TargetInstrDesc &TID) const {
815  for (unsigned i = MI.getNumOperands(), e = TID.getNumOperands(); i != e; --i){
816    const MachineOperand &MO = MI.getOperand(i-1);
817    if (MO.isReg() && MO.isDef() && MO.getReg() == ARM::CPSR)
818      return 1 << ARMII::S_BitShift;
819  }
820  return 0;
821}
822
823void ARMCodeEmitter::emitDataProcessingInstruction(const MachineInstr &MI,
824                                                   unsigned ImplicitRd,
825                                                   unsigned ImplicitRn) {
826  const TargetInstrDesc &TID = MI.getDesc();
827
828  // Part of binary is determined by TableGn.
829  unsigned Binary = getBinaryCodeForInstr(MI);
830
831  // Set the conditional execution predicate
832  Binary |= II->getPredicate(&MI) << ARMII::CondShift;
833
834  // Encode S bit if MI modifies CPSR.
835  Binary |= getAddrModeSBit(MI, TID);
836
837  // Encode register def if there is one.
838  unsigned NumDefs = TID.getNumDefs();
839  unsigned OpIdx = 0;
840  if (NumDefs)
841    Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRdShift;
842  else if (ImplicitRd)
843    // Special handling for implicit use (e.g. PC).
844    Binary |= (ARMRegisterInfo::getRegisterNumbering(ImplicitRd)
845               << ARMII::RegRdShift);
846
847  if (TID.Opcode == ARM::MOVi16) {
848      // Get immediate from MI.
849      unsigned Lo16 = getMovi32Value(MI, MI.getOperand(OpIdx),
850                      ARM::reloc_arm_movw);
851      // Encode imm which is the same as in emitMOVi32immInstruction().
852      Binary |= Lo16 & 0xFFF;
853      Binary |= ((Lo16 >> 12) & 0xF) << 16;
854      emitWordLE(Binary);
855      return;
856  } else if(TID.Opcode == ARM::MOVTi16) {
857      unsigned Hi16 = (getMovi32Value(MI, MI.getOperand(OpIdx),
858                       ARM::reloc_arm_movt) >> 16);
859      Binary |= Hi16 & 0xFFF;
860      Binary |= ((Hi16 >> 12) & 0xF) << 16;
861      emitWordLE(Binary);
862      return;
863  } else if ((TID.Opcode == ARM::BFC) || (TID.Opcode == ARM::BFI)) {
864      uint32_t v = ~MI.getOperand(2).getImm();
865      int32_t lsb = CountTrailingZeros_32(v);
866      int32_t msb = (32 - CountLeadingZeros_32(v)) - 1;
867      // Instr{20-16} = msb, Instr{11-7} = lsb
868      Binary |= (msb & 0x1F) << 16;
869      Binary |= (lsb & 0x1F) << 7;
870      emitWordLE(Binary);
871      return;
872  } else if ((TID.Opcode == ARM::UBFX) || (TID.Opcode == ARM::SBFX)) {
873      // Encode Rn in Instr{0-3}
874      Binary |= getMachineOpValue(MI, OpIdx++);
875
876      uint32_t lsb = MI.getOperand(OpIdx++).getImm();
877      uint32_t widthm1 = MI.getOperand(OpIdx++).getImm() - 1;
878
879      // Instr{20-16} = widthm1, Instr{11-7} = lsb
880      Binary |= (widthm1 & 0x1F) << 16;
881      Binary |= (lsb & 0x1F) << 7;
882      emitWordLE(Binary);
883      return;
884  }
885
886  // If this is a two-address operand, skip it. e.g. MOVCCr operand 1.
887  if (TID.getOperandConstraint(OpIdx, TOI::TIED_TO) != -1)
888    ++OpIdx;
889
890  // Encode first non-shifter register operand if there is one.
891  bool isUnary = TID.TSFlags & ARMII::UnaryDP;
892  if (!isUnary) {
893    if (ImplicitRn)
894      // Special handling for implicit use (e.g. PC).
895      Binary |= (ARMRegisterInfo::getRegisterNumbering(ImplicitRn)
896                 << ARMII::RegRnShift);
897    else {
898      Binary |= getMachineOpValue(MI, OpIdx) << ARMII::RegRnShift;
899      ++OpIdx;
900    }
901  }
902
903  // Encode shifter operand.
904  const MachineOperand &MO = MI.getOperand(OpIdx);
905  if ((TID.TSFlags & ARMII::FormMask) == ARMII::DPSoRegFrm) {
906    // Encode SoReg.
907    emitWordLE(Binary | getMachineSoRegOpValue(MI, TID, MO, OpIdx));
908    return;
909  }
910
911  if (MO.isReg()) {
912    // Encode register Rm.
913    emitWordLE(Binary | ARMRegisterInfo::getRegisterNumbering(MO.getReg()));
914    return;
915  }
916
917  // Encode so_imm.
918  Binary |= getMachineSoImmOpValue((unsigned)MO.getImm());
919
920  emitWordLE(Binary);
921}
922
923void ARMCodeEmitter::emitLoadStoreInstruction(const MachineInstr &MI,
924                                              unsigned ImplicitRd,
925                                              unsigned ImplicitRn) {
926  const TargetInstrDesc &TID = MI.getDesc();
927  unsigned Form = TID.TSFlags & ARMII::FormMask;
928  bool IsPrePost = (TID.TSFlags & ARMII::IndexModeMask) != 0;
929
930  // Part of binary is determined by TableGn.
931  unsigned Binary = getBinaryCodeForInstr(MI);
932
933  // Set the conditional execution predicate
934  Binary |= II->getPredicate(&MI) << ARMII::CondShift;
935
936  unsigned OpIdx = 0;
937
938  // Operand 0 of a pre- and post-indexed store is the address base
939  // writeback. Skip it.
940  bool Skipped = false;
941  if (IsPrePost && Form == ARMII::StFrm) {
942    ++OpIdx;
943    Skipped = true;
944  }
945
946  // Set first operand
947  if (ImplicitRd)
948    // Special handling for implicit use (e.g. PC).
949    Binary |= (ARMRegisterInfo::getRegisterNumbering(ImplicitRd)
950               << ARMII::RegRdShift);
951  else
952    Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRdShift;
953
954  // Set second operand
955  if (ImplicitRn)
956    // Special handling for implicit use (e.g. PC).
957    Binary |= (ARMRegisterInfo::getRegisterNumbering(ImplicitRn)
958               << ARMII::RegRnShift);
959  else
960    Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRnShift;
961
962  // If this is a two-address operand, skip it. e.g. LDR_PRE.
963  if (!Skipped && TID.getOperandConstraint(OpIdx, TOI::TIED_TO) != -1)
964    ++OpIdx;
965
966  const MachineOperand &MO2 = MI.getOperand(OpIdx);
967  unsigned AM2Opc = (ImplicitRn == ARM::PC)
968    ? 0 : MI.getOperand(OpIdx+1).getImm();
969
970  // Set bit U(23) according to sign of immed value (positive or negative).
971  Binary |= ((ARM_AM::getAM2Op(AM2Opc) == ARM_AM::add ? 1 : 0) <<
972             ARMII::U_BitShift);
973  if (!MO2.getReg()) { // is immediate
974    if (ARM_AM::getAM2Offset(AM2Opc))
975      // Set the value of offset_12 field
976      Binary |= ARM_AM::getAM2Offset(AM2Opc);
977    emitWordLE(Binary);
978    return;
979  }
980
981  // Set bit I(25), because this is not in immediate enconding.
982  Binary |= 1 << ARMII::I_BitShift;
983  assert(TargetRegisterInfo::isPhysicalRegister(MO2.getReg()));
984  // Set bit[3:0] to the corresponding Rm register
985  Binary |= ARMRegisterInfo::getRegisterNumbering(MO2.getReg());
986
987  // If this instr is in scaled register offset/index instruction, set
988  // shift_immed(bit[11:7]) and shift(bit[6:5]) fields.
989  if (unsigned ShImm = ARM_AM::getAM2Offset(AM2Opc)) {
990    Binary |= getShiftOp(AM2Opc) << ARMII::ShiftImmShift;  // shift
991    Binary |= ShImm              << ARMII::ShiftShift;     // shift_immed
992  }
993
994  emitWordLE(Binary);
995}
996
997void ARMCodeEmitter::emitMiscLoadStoreInstruction(const MachineInstr &MI,
998                                                  unsigned ImplicitRn) {
999  const TargetInstrDesc &TID = MI.getDesc();
1000  unsigned Form = TID.TSFlags & ARMII::FormMask;
1001  bool IsPrePost = (TID.TSFlags & ARMII::IndexModeMask) != 0;
1002
1003  // Part of binary is determined by TableGn.
1004  unsigned Binary = getBinaryCodeForInstr(MI);
1005
1006  // Set the conditional execution predicate
1007  Binary |= II->getPredicate(&MI) << ARMII::CondShift;
1008
1009  unsigned OpIdx = 0;
1010
1011  // Operand 0 of a pre- and post-indexed store is the address base
1012  // writeback. Skip it.
1013  bool Skipped = false;
1014  if (IsPrePost && Form == ARMII::StMiscFrm) {
1015    ++OpIdx;
1016    Skipped = true;
1017  }
1018
1019  // Set first operand
1020  Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRdShift;
1021
1022  // Skip LDRD and STRD's second operand.
1023  if (TID.Opcode == ARM::LDRD || TID.Opcode == ARM::STRD)
1024    ++OpIdx;
1025
1026  // Set second operand
1027  if (ImplicitRn)
1028    // Special handling for implicit use (e.g. PC).
1029    Binary |= (ARMRegisterInfo::getRegisterNumbering(ImplicitRn)
1030               << ARMII::RegRnShift);
1031  else
1032    Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRnShift;
1033
1034  // If this is a two-address operand, skip it. e.g. LDRH_POST.
1035  if (!Skipped && TID.getOperandConstraint(OpIdx, TOI::TIED_TO) != -1)
1036    ++OpIdx;
1037
1038  const MachineOperand &MO2 = MI.getOperand(OpIdx);
1039  unsigned AM3Opc = (ImplicitRn == ARM::PC)
1040    ? 0 : MI.getOperand(OpIdx+1).getImm();
1041
1042  // Set bit U(23) according to sign of immed value (positive or negative)
1043  Binary |= ((ARM_AM::getAM3Op(AM3Opc) == ARM_AM::add ? 1 : 0) <<
1044             ARMII::U_BitShift);
1045
1046  // If this instr is in register offset/index encoding, set bit[3:0]
1047  // to the corresponding Rm register.
1048  if (MO2.getReg()) {
1049    Binary |= ARMRegisterInfo::getRegisterNumbering(MO2.getReg());
1050    emitWordLE(Binary);
1051    return;
1052  }
1053
1054  // This instr is in immediate offset/index encoding, set bit 22 to 1.
1055  Binary |= 1 << ARMII::AM3_I_BitShift;
1056  if (unsigned ImmOffs = ARM_AM::getAM3Offset(AM3Opc)) {
1057    // Set operands
1058    Binary |= (ImmOffs >> 4) << ARMII::ImmHiShift;  // immedH
1059    Binary |= (ImmOffs & 0xF);                      // immedL
1060  }
1061
1062  emitWordLE(Binary);
1063}
1064
1065static unsigned getAddrModeUPBits(unsigned Mode) {
1066  unsigned Binary = 0;
1067
1068  // Set addressing mode by modifying bits U(23) and P(24)
1069  // IA - Increment after  - bit U = 1 and bit P = 0
1070  // IB - Increment before - bit U = 1 and bit P = 1
1071  // DA - Decrement after  - bit U = 0 and bit P = 0
1072  // DB - Decrement before - bit U = 0 and bit P = 1
1073  switch (Mode) {
1074  default: llvm_unreachable("Unknown addressing sub-mode!");
1075  case ARM_AM::da:                                     break;
1076  case ARM_AM::db: Binary |= 0x1 << ARMII::P_BitShift; break;
1077  case ARM_AM::ia: Binary |= 0x1 << ARMII::U_BitShift; break;
1078  case ARM_AM::ib: Binary |= 0x3 << ARMII::U_BitShift; break;
1079  }
1080
1081  return Binary;
1082}
1083
1084void ARMCodeEmitter::emitLoadStoreMultipleInstruction(const MachineInstr &MI) {
1085  const TargetInstrDesc &TID = MI.getDesc();
1086  bool IsUpdating = (TID.TSFlags & ARMII::IndexModeMask) != 0;
1087
1088  // Part of binary is determined by TableGn.
1089  unsigned Binary = getBinaryCodeForInstr(MI);
1090
1091  // Set the conditional execution predicate
1092  Binary |= II->getPredicate(&MI) << ARMII::CondShift;
1093
1094  // Skip operand 0 of an instruction with base register update.
1095  unsigned OpIdx = 0;
1096  if (IsUpdating)
1097    ++OpIdx;
1098
1099  // Set base address operand
1100  Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRnShift;
1101
1102  // Set addressing mode by modifying bits U(23) and P(24)
1103  const MachineOperand &MO = MI.getOperand(OpIdx++);
1104  Binary |= getAddrModeUPBits(ARM_AM::getAM4SubMode(MO.getImm()));
1105
1106  // Set bit W(21)
1107  if (IsUpdating)
1108    Binary |= 0x1 << ARMII::W_BitShift;
1109
1110  // Set registers
1111  for (unsigned i = OpIdx+2, e = MI.getNumOperands(); i != e; ++i) {
1112    const MachineOperand &MO = MI.getOperand(i);
1113    if (!MO.isReg() || MO.isImplicit())
1114      break;
1115    unsigned RegNum = ARMRegisterInfo::getRegisterNumbering(MO.getReg());
1116    assert(TargetRegisterInfo::isPhysicalRegister(MO.getReg()) &&
1117           RegNum < 16);
1118    Binary |= 0x1 << RegNum;
1119  }
1120
1121  emitWordLE(Binary);
1122}
1123
1124void ARMCodeEmitter::emitMulFrmInstruction(const MachineInstr &MI) {
1125  const TargetInstrDesc &TID = MI.getDesc();
1126
1127  // Part of binary is determined by TableGn.
1128  unsigned Binary = getBinaryCodeForInstr(MI);
1129
1130  // Set the conditional execution predicate
1131  Binary |= II->getPredicate(&MI) << ARMII::CondShift;
1132
1133  // Encode S bit if MI modifies CPSR.
1134  Binary |= getAddrModeSBit(MI, TID);
1135
1136  // 32x32->64bit operations have two destination registers. The number
1137  // of register definitions will tell us if that's what we're dealing with.
1138  unsigned OpIdx = 0;
1139  if (TID.getNumDefs() == 2)
1140    Binary |= getMachineOpValue (MI, OpIdx++) << ARMII::RegRdLoShift;
1141
1142  // Encode Rd
1143  Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRdHiShift;
1144
1145  // Encode Rm
1146  Binary |= getMachineOpValue(MI, OpIdx++);
1147
1148  // Encode Rs
1149  Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRsShift;
1150
1151  // Many multiple instructions (e.g. MLA) have three src operands. Encode
1152  // it as Rn (for multiply, that's in the same offset as RdLo.
1153  if (TID.getNumOperands() > OpIdx &&
1154      !TID.OpInfo[OpIdx].isPredicate() &&
1155      !TID.OpInfo[OpIdx].isOptionalDef())
1156    Binary |= getMachineOpValue(MI, OpIdx) << ARMII::RegRdLoShift;
1157
1158  emitWordLE(Binary);
1159}
1160
1161void ARMCodeEmitter::emitExtendInstruction(const MachineInstr &MI) {
1162  const TargetInstrDesc &TID = MI.getDesc();
1163
1164  // Part of binary is determined by TableGn.
1165  unsigned Binary = getBinaryCodeForInstr(MI);
1166
1167  // Set the conditional execution predicate
1168  Binary |= II->getPredicate(&MI) << ARMII::CondShift;
1169
1170  unsigned OpIdx = 0;
1171
1172  // Encode Rd
1173  Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRdShift;
1174
1175  const MachineOperand &MO1 = MI.getOperand(OpIdx++);
1176  const MachineOperand &MO2 = MI.getOperand(OpIdx);
1177  if (MO2.isReg()) {
1178    // Two register operand form.
1179    // Encode Rn.
1180    Binary |= getMachineOpValue(MI, MO1) << ARMII::RegRnShift;
1181
1182    // Encode Rm.
1183    Binary |= getMachineOpValue(MI, MO2);
1184    ++OpIdx;
1185  } else {
1186    Binary |= getMachineOpValue(MI, MO1);
1187  }
1188
1189  // Encode rot imm (0, 8, 16, or 24) if it has a rotate immediate operand.
1190  if (MI.getOperand(OpIdx).isImm() &&
1191      !TID.OpInfo[OpIdx].isPredicate() &&
1192      !TID.OpInfo[OpIdx].isOptionalDef())
1193    Binary |= (getMachineOpValue(MI, OpIdx) / 8) << ARMII::ExtRotImmShift;
1194
1195  emitWordLE(Binary);
1196}
1197
1198void ARMCodeEmitter::emitMiscArithInstruction(const MachineInstr &MI) {
1199  const TargetInstrDesc &TID = MI.getDesc();
1200
1201  // Part of binary is determined by TableGn.
1202  unsigned Binary = getBinaryCodeForInstr(MI);
1203
1204  // Set the conditional execution predicate
1205  Binary |= II->getPredicate(&MI) << ARMII::CondShift;
1206
1207  unsigned OpIdx = 0;
1208
1209  // Encode Rd
1210  Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRdShift;
1211
1212  const MachineOperand &MO = MI.getOperand(OpIdx++);
1213  if (OpIdx == TID.getNumOperands() ||
1214      TID.OpInfo[OpIdx].isPredicate() ||
1215      TID.OpInfo[OpIdx].isOptionalDef()) {
1216    // Encode Rm and it's done.
1217    Binary |= getMachineOpValue(MI, MO);
1218    emitWordLE(Binary);
1219    return;
1220  }
1221
1222  // Encode Rn.
1223  Binary |= getMachineOpValue(MI, MO) << ARMII::RegRnShift;
1224
1225  // Encode Rm.
1226  Binary |= getMachineOpValue(MI, OpIdx++);
1227
1228  // Encode shift_imm.
1229  unsigned ShiftAmt = MI.getOperand(OpIdx).getImm();
1230  assert(ShiftAmt < 32 && "shift_imm range is 0 to 31!");
1231  Binary |= ShiftAmt << ARMII::ShiftShift;
1232
1233  emitWordLE(Binary);
1234}
1235
1236void ARMCodeEmitter::emitSaturateInstruction(const MachineInstr &MI) {
1237  const TargetInstrDesc &TID = MI.getDesc();
1238
1239  // Part of binary is determined by TableGen.
1240  unsigned Binary = getBinaryCodeForInstr(MI);
1241
1242  // Set the conditional execution predicate
1243  Binary |= II->getPredicate(&MI) << ARMII::CondShift;
1244
1245  // Encode Rd
1246  Binary |= getMachineOpValue(MI, 0) << ARMII::RegRdShift;
1247
1248  // Encode saturate bit position.
1249  unsigned Pos = MI.getOperand(1).getImm();
1250  if (TID.Opcode == ARM::SSAT || TID.Opcode == ARM::SSAT16)
1251    Pos -= 1;
1252  assert((Pos < 16 || (Pos < 32 &&
1253                       TID.Opcode != ARM::SSAT16 &&
1254                       TID.Opcode != ARM::USAT16)) &&
1255         "saturate bit position out of range");
1256  Binary |= Pos << 16;
1257
1258  // Encode Rm
1259  Binary |= getMachineOpValue(MI, 2);
1260
1261  // Encode shift_imm.
1262  if (TID.getNumOperands() == 4) {
1263    unsigned ShiftOp = MI.getOperand(3).getImm();
1264    ARM_AM::ShiftOpc Opc = ARM_AM::getSORegShOp(ShiftOp);
1265    if (Opc == ARM_AM::asr)
1266      Binary |= (1 << 6);
1267    unsigned ShiftAmt = MI.getOperand(3).getImm();
1268    if (ShiftAmt == 32 && Opc == ARM_AM::asr)
1269      ShiftAmt = 0;
1270    assert(ShiftAmt < 32 && "shift_imm range is 0 to 31!");
1271    Binary |= ShiftAmt << ARMII::ShiftShift;
1272  }
1273
1274  emitWordLE(Binary);
1275}
1276
1277void ARMCodeEmitter::emitBranchInstruction(const MachineInstr &MI) {
1278  const TargetInstrDesc &TID = MI.getDesc();
1279
1280  if (TID.Opcode == ARM::TPsoft) {
1281    llvm_unreachable("ARM::TPsoft FIXME"); // FIXME
1282  }
1283
1284  // Part of binary is determined by TableGn.
1285  unsigned Binary = getBinaryCodeForInstr(MI);
1286
1287  // Set the conditional execution predicate
1288  Binary |= II->getPredicate(&MI) << ARMII::CondShift;
1289
1290  // Set signed_immed_24 field
1291  Binary |= getMachineOpValue(MI, 0);
1292
1293  emitWordLE(Binary);
1294}
1295
1296void ARMCodeEmitter::emitInlineJumpTable(unsigned JTIndex) {
1297  // Remember the base address of the inline jump table.
1298  uintptr_t JTBase = MCE.getCurrentPCValue();
1299  JTI->addJumpTableBaseAddr(JTIndex, JTBase);
1300  DEBUG(errs() << "  ** Jump Table #" << JTIndex << " @ " << (void*)JTBase
1301               << '\n');
1302
1303  // Now emit the jump table entries.
1304  const std::vector<MachineBasicBlock*> &MBBs = (*MJTEs)[JTIndex].MBBs;
1305  for (unsigned i = 0, e = MBBs.size(); i != e; ++i) {
1306    if (IsPIC)
1307      // DestBB address - JT base.
1308      emitMachineBasicBlock(MBBs[i], ARM::reloc_arm_pic_jt, JTBase);
1309    else
1310      // Absolute DestBB address.
1311      emitMachineBasicBlock(MBBs[i], ARM::reloc_arm_absolute);
1312    emitWordLE(0);
1313  }
1314}
1315
1316void ARMCodeEmitter::emitMiscBranchInstruction(const MachineInstr &MI) {
1317  const TargetInstrDesc &TID = MI.getDesc();
1318
1319  // Handle jump tables.
1320  if (TID.Opcode == ARM::BR_JTr || TID.Opcode == ARM::BR_JTadd) {
1321    // First emit a ldr pc, [] instruction.
1322    emitDataProcessingInstruction(MI, ARM::PC);
1323
1324    // Then emit the inline jump table.
1325    unsigned JTIndex =
1326      (TID.Opcode == ARM::BR_JTr)
1327      ? MI.getOperand(1).getIndex() : MI.getOperand(2).getIndex();
1328    emitInlineJumpTable(JTIndex);
1329    return;
1330  } else if (TID.Opcode == ARM::BR_JTm) {
1331    // First emit a ldr pc, [] instruction.
1332    emitLoadStoreInstruction(MI, ARM::PC);
1333
1334    // Then emit the inline jump table.
1335    emitInlineJumpTable(MI.getOperand(3).getIndex());
1336    return;
1337  }
1338
1339  // Part of binary is determined by TableGn.
1340  unsigned Binary = getBinaryCodeForInstr(MI);
1341
1342  // Set the conditional execution predicate
1343  Binary |= II->getPredicate(&MI) << ARMII::CondShift;
1344
1345  if (TID.Opcode == ARM::BX_RET || TID.Opcode == ARM::MOVPCLR)
1346    // The return register is LR.
1347    Binary |= ARMRegisterInfo::getRegisterNumbering(ARM::LR);
1348  else
1349    // otherwise, set the return register
1350    Binary |= getMachineOpValue(MI, 0);
1351
1352  emitWordLE(Binary);
1353}
1354
1355static unsigned encodeVFPRd(const MachineInstr &MI, unsigned OpIdx) {
1356  unsigned RegD = MI.getOperand(OpIdx).getReg();
1357  unsigned Binary = 0;
1358  bool isSPVFP = false;
1359  RegD = ARMRegisterInfo::getRegisterNumbering(RegD, &isSPVFP);
1360  if (!isSPVFP)
1361    Binary |=   RegD               << ARMII::RegRdShift;
1362  else {
1363    Binary |= ((RegD & 0x1E) >> 1) << ARMII::RegRdShift;
1364    Binary |=  (RegD & 0x01)       << ARMII::D_BitShift;
1365  }
1366  return Binary;
1367}
1368
1369static unsigned encodeVFPRn(const MachineInstr &MI, unsigned OpIdx) {
1370  unsigned RegN = MI.getOperand(OpIdx).getReg();
1371  unsigned Binary = 0;
1372  bool isSPVFP = false;
1373  RegN = ARMRegisterInfo::getRegisterNumbering(RegN, &isSPVFP);
1374  if (!isSPVFP)
1375    Binary |=   RegN               << ARMII::RegRnShift;
1376  else {
1377    Binary |= ((RegN & 0x1E) >> 1) << ARMII::RegRnShift;
1378    Binary |=  (RegN & 0x01)       << ARMII::N_BitShift;
1379  }
1380  return Binary;
1381}
1382
1383static unsigned encodeVFPRm(const MachineInstr &MI, unsigned OpIdx) {
1384  unsigned RegM = MI.getOperand(OpIdx).getReg();
1385  unsigned Binary = 0;
1386  bool isSPVFP = false;
1387  RegM = ARMRegisterInfo::getRegisterNumbering(RegM, &isSPVFP);
1388  if (!isSPVFP)
1389    Binary |=   RegM;
1390  else {
1391    Binary |= ((RegM & 0x1E) >> 1);
1392    Binary |=  (RegM & 0x01)       << ARMII::M_BitShift;
1393  }
1394  return Binary;
1395}
1396
1397void ARMCodeEmitter::emitVFPArithInstruction(const MachineInstr &MI) {
1398  const TargetInstrDesc &TID = MI.getDesc();
1399
1400  // Part of binary is determined by TableGn.
1401  unsigned Binary = getBinaryCodeForInstr(MI);
1402
1403  // Set the conditional execution predicate
1404  Binary |= II->getPredicate(&MI) << ARMII::CondShift;
1405
1406  unsigned OpIdx = 0;
1407  assert((Binary & ARMII::D_BitShift) == 0 &&
1408         (Binary & ARMII::N_BitShift) == 0 &&
1409         (Binary & ARMII::M_BitShift) == 0 && "VFP encoding bug!");
1410
1411  // Encode Dd / Sd.
1412  Binary |= encodeVFPRd(MI, OpIdx++);
1413
1414  // If this is a two-address operand, skip it, e.g. FMACD.
1415  if (TID.getOperandConstraint(OpIdx, TOI::TIED_TO) != -1)
1416    ++OpIdx;
1417
1418  // Encode Dn / Sn.
1419  if ((TID.TSFlags & ARMII::FormMask) == ARMII::VFPBinaryFrm)
1420    Binary |= encodeVFPRn(MI, OpIdx++);
1421
1422  if (OpIdx == TID.getNumOperands() ||
1423      TID.OpInfo[OpIdx].isPredicate() ||
1424      TID.OpInfo[OpIdx].isOptionalDef()) {
1425    // FCMPEZD etc. has only one operand.
1426    emitWordLE(Binary);
1427    return;
1428  }
1429
1430  // Encode Dm / Sm.
1431  Binary |= encodeVFPRm(MI, OpIdx);
1432
1433  emitWordLE(Binary);
1434}
1435
1436void ARMCodeEmitter::emitVFPConversionInstruction(const MachineInstr &MI) {
1437  const TargetInstrDesc &TID = MI.getDesc();
1438  unsigned Form = TID.TSFlags & ARMII::FormMask;
1439
1440  // Part of binary is determined by TableGn.
1441  unsigned Binary = getBinaryCodeForInstr(MI);
1442
1443  // Set the conditional execution predicate
1444  Binary |= II->getPredicate(&MI) << ARMII::CondShift;
1445
1446  switch (Form) {
1447  default: break;
1448  case ARMII::VFPConv1Frm:
1449  case ARMII::VFPConv2Frm:
1450  case ARMII::VFPConv3Frm:
1451    // Encode Dd / Sd.
1452    Binary |= encodeVFPRd(MI, 0);
1453    break;
1454  case ARMII::VFPConv4Frm:
1455    // Encode Dn / Sn.
1456    Binary |= encodeVFPRn(MI, 0);
1457    break;
1458  case ARMII::VFPConv5Frm:
1459    // Encode Dm / Sm.
1460    Binary |= encodeVFPRm(MI, 0);
1461    break;
1462  }
1463
1464  switch (Form) {
1465  default: break;
1466  case ARMII::VFPConv1Frm:
1467    // Encode Dm / Sm.
1468    Binary |= encodeVFPRm(MI, 1);
1469    break;
1470  case ARMII::VFPConv2Frm:
1471  case ARMII::VFPConv3Frm:
1472    // Encode Dn / Sn.
1473    Binary |= encodeVFPRn(MI, 1);
1474    break;
1475  case ARMII::VFPConv4Frm:
1476  case ARMII::VFPConv5Frm:
1477    // Encode Dd / Sd.
1478    Binary |= encodeVFPRd(MI, 1);
1479    break;
1480  }
1481
1482  if (Form == ARMII::VFPConv5Frm)
1483    // Encode Dn / Sn.
1484    Binary |= encodeVFPRn(MI, 2);
1485  else if (Form == ARMII::VFPConv3Frm)
1486    // Encode Dm / Sm.
1487    Binary |= encodeVFPRm(MI, 2);
1488
1489  emitWordLE(Binary);
1490}
1491
1492void ARMCodeEmitter::emitVFPLoadStoreInstruction(const MachineInstr &MI) {
1493  // Part of binary is determined by TableGn.
1494  unsigned Binary = getBinaryCodeForInstr(MI);
1495
1496  // Set the conditional execution predicate
1497  Binary |= II->getPredicate(&MI) << ARMII::CondShift;
1498
1499  unsigned OpIdx = 0;
1500
1501  // Encode Dd / Sd.
1502  Binary |= encodeVFPRd(MI, OpIdx++);
1503
1504  // Encode address base.
1505  const MachineOperand &Base = MI.getOperand(OpIdx++);
1506  Binary |= getMachineOpValue(MI, Base) << ARMII::RegRnShift;
1507
1508  // If there is a non-zero immediate offset, encode it.
1509  if (Base.isReg()) {
1510    const MachineOperand &Offset = MI.getOperand(OpIdx);
1511    if (unsigned ImmOffs = ARM_AM::getAM5Offset(Offset.getImm())) {
1512      if (ARM_AM::getAM5Op(Offset.getImm()) == ARM_AM::add)
1513        Binary |= 1 << ARMII::U_BitShift;
1514      Binary |= ImmOffs;
1515      emitWordLE(Binary);
1516      return;
1517    }
1518  }
1519
1520  // If immediate offset is omitted, default to +0.
1521  Binary |= 1 << ARMII::U_BitShift;
1522
1523  emitWordLE(Binary);
1524}
1525
1526void
1527ARMCodeEmitter::emitVFPLoadStoreMultipleInstruction(const MachineInstr &MI) {
1528  const TargetInstrDesc &TID = MI.getDesc();
1529  bool IsUpdating = (TID.TSFlags & ARMII::IndexModeMask) != 0;
1530
1531  // Part of binary is determined by TableGn.
1532  unsigned Binary = getBinaryCodeForInstr(MI);
1533
1534  // Set the conditional execution predicate
1535  Binary |= II->getPredicate(&MI) << ARMII::CondShift;
1536
1537  // Skip operand 0 of an instruction with base register update.
1538  unsigned OpIdx = 0;
1539  if (IsUpdating)
1540    ++OpIdx;
1541
1542  // Set base address operand
1543  Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRnShift;
1544
1545  // Set addressing mode by modifying bits U(23) and P(24)
1546  const MachineOperand &MO = MI.getOperand(OpIdx++);
1547  Binary |= getAddrModeUPBits(ARM_AM::getAM5SubMode(MO.getImm()));
1548
1549  // Set bit W(21)
1550  if (IsUpdating)
1551    Binary |= 0x1 << ARMII::W_BitShift;
1552
1553  // First register is encoded in Dd.
1554  Binary |= encodeVFPRd(MI, OpIdx+2);
1555
1556  // Number of registers are encoded in offset field.
1557  unsigned NumRegs = 1;
1558  for (unsigned i = OpIdx+3, e = MI.getNumOperands(); i != e; ++i) {
1559    const MachineOperand &MO = MI.getOperand(i);
1560    if (!MO.isReg() || MO.isImplicit())
1561      break;
1562    ++NumRegs;
1563  }
1564  // Bit 8 will be set if <list> is consecutive 64-bit registers (e.g., D0)
1565  // Otherwise, it will be 0, in the case of 32-bit registers.
1566  if(Binary & 0x100)
1567    Binary |= NumRegs * 2;
1568  else
1569    Binary |= NumRegs;
1570
1571  emitWordLE(Binary);
1572}
1573
1574void ARMCodeEmitter::emitMiscInstruction(const MachineInstr &MI) {
1575  unsigned Opcode = MI.getDesc().Opcode;
1576  // Part of binary is determined by TableGn.
1577  unsigned Binary = getBinaryCodeForInstr(MI);
1578
1579  // Set the conditional execution predicate
1580  Binary |= II->getPredicate(&MI) << ARMII::CondShift;
1581
1582  switch(Opcode) {
1583  default:
1584    llvm_unreachable("ARMCodeEmitter::emitMiscInstruction");
1585
1586  case ARM::FMSTAT:
1587    // No further encoding needed.
1588    break;
1589
1590  case ARM::VMRS:
1591  case ARM::VMSR: {
1592    const MachineOperand &MO0 = MI.getOperand(0);
1593    // Encode Rt.
1594    Binary |= ARMRegisterInfo::getRegisterNumbering(MO0.getReg())
1595                << ARMII::RegRdShift;
1596    break;
1597  }
1598
1599  case ARM::FCONSTD:
1600  case ARM::FCONSTS: {
1601    // Encode Dd / Sd.
1602    Binary |= encodeVFPRd(MI, 0);
1603
1604    // Encode imm., Table A7-18 VFP modified immediate constants
1605    const MachineOperand &MO1 = MI.getOperand(1);
1606    unsigned Imm = static_cast<unsigned>(MO1.getFPImm()->getValueAPF()
1607                      .bitcastToAPInt().getHiBits(32).getLimitedValue());
1608    unsigned ModifiedImm;
1609
1610    if(Opcode == ARM::FCONSTS)
1611      ModifiedImm = (Imm & 0x80000000) >> 24 | // a
1612                    (Imm & 0x03F80000) >> 19;  // bcdefgh
1613    else // Opcode == ARM::FCONSTD
1614      ModifiedImm = (Imm & 0x80000000) >> 24 | // a
1615                    (Imm & 0x007F0000) >> 16;  // bcdefgh
1616
1617    // Insts{19-16} = abcd, Insts{3-0} = efgh
1618    Binary |= ((ModifiedImm & 0xF0) >> 4) << 16;
1619    Binary |= (ModifiedImm & 0xF);
1620    break;
1621  }
1622  }
1623
1624  emitWordLE(Binary);
1625}
1626
1627static unsigned encodeNEONRd(const MachineInstr &MI, unsigned OpIdx) {
1628  unsigned RegD = MI.getOperand(OpIdx).getReg();
1629  unsigned Binary = 0;
1630  RegD = ARMRegisterInfo::getRegisterNumbering(RegD);
1631  Binary |= (RegD & 0xf) << ARMII::RegRdShift;
1632  Binary |= ((RegD >> 4) & 1) << ARMII::D_BitShift;
1633  return Binary;
1634}
1635
1636static unsigned encodeNEONRn(const MachineInstr &MI, unsigned OpIdx) {
1637  unsigned RegN = MI.getOperand(OpIdx).getReg();
1638  unsigned Binary = 0;
1639  RegN = ARMRegisterInfo::getRegisterNumbering(RegN);
1640  Binary |= (RegN & 0xf) << ARMII::RegRnShift;
1641  Binary |= ((RegN >> 4) & 1) << ARMII::N_BitShift;
1642  return Binary;
1643}
1644
1645static unsigned encodeNEONRm(const MachineInstr &MI, unsigned OpIdx) {
1646  unsigned RegM = MI.getOperand(OpIdx).getReg();
1647  unsigned Binary = 0;
1648  RegM = ARMRegisterInfo::getRegisterNumbering(RegM);
1649  Binary |= (RegM & 0xf);
1650  Binary |= ((RegM >> 4) & 1) << ARMII::M_BitShift;
1651  return Binary;
1652}
1653
1654/// convertNEONDataProcToThumb - Convert the ARM mode encoding for a NEON
1655/// data-processing instruction to the corresponding Thumb encoding.
1656static unsigned convertNEONDataProcToThumb(unsigned Binary) {
1657  assert((Binary & 0xfe000000) == 0xf2000000 &&
1658         "not an ARM NEON data-processing instruction");
1659  unsigned UBit = (Binary >> 24) & 1;
1660  return 0xef000000 | (UBit << 28) | (Binary & 0xffffff);
1661}
1662
1663void ARMCodeEmitter::emitNEONLaneInstruction(const MachineInstr &MI) {
1664  unsigned Binary = getBinaryCodeForInstr(MI);
1665
1666  unsigned RegTOpIdx, RegNOpIdx, LnOpIdx;
1667  const TargetInstrDesc &TID = MI.getDesc();
1668  if ((TID.TSFlags & ARMII::FormMask) == ARMII::NGetLnFrm) {
1669    RegTOpIdx = 0;
1670    RegNOpIdx = 1;
1671    LnOpIdx = 2;
1672  } else { // ARMII::NSetLnFrm
1673    RegTOpIdx = 2;
1674    RegNOpIdx = 0;
1675    LnOpIdx = 3;
1676  }
1677
1678  // Set the conditional execution predicate
1679  Binary |= (IsThumb ? ARMCC::AL : II->getPredicate(&MI)) << ARMII::CondShift;
1680
1681  unsigned RegT = MI.getOperand(RegTOpIdx).getReg();
1682  RegT = ARMRegisterInfo::getRegisterNumbering(RegT);
1683  Binary |= (RegT << ARMII::RegRdShift);
1684  Binary |= encodeNEONRn(MI, RegNOpIdx);
1685
1686  unsigned LaneShift;
1687  if ((Binary & (1 << 22)) != 0)
1688    LaneShift = 0; // 8-bit elements
1689  else if ((Binary & (1 << 5)) != 0)
1690    LaneShift = 1; // 16-bit elements
1691  else
1692    LaneShift = 2; // 32-bit elements
1693
1694  unsigned Lane = MI.getOperand(LnOpIdx).getImm() << LaneShift;
1695  unsigned Opc1 = Lane >> 2;
1696  unsigned Opc2 = Lane & 3;
1697  assert((Opc1 & 3) == 0 && "out-of-range lane number operand");
1698  Binary |= (Opc1 << 21);
1699  Binary |= (Opc2 << 5);
1700
1701  emitWordLE(Binary);
1702}
1703
1704void ARMCodeEmitter::emitNEONDupInstruction(const MachineInstr &MI) {
1705  unsigned Binary = getBinaryCodeForInstr(MI);
1706
1707  // Set the conditional execution predicate
1708  Binary |= (IsThumb ? ARMCC::AL : II->getPredicate(&MI)) << ARMII::CondShift;
1709
1710  unsigned RegT = MI.getOperand(1).getReg();
1711  RegT = ARMRegisterInfo::getRegisterNumbering(RegT);
1712  Binary |= (RegT << ARMII::RegRdShift);
1713  Binary |= encodeNEONRn(MI, 0);
1714  emitWordLE(Binary);
1715}
1716
1717void ARMCodeEmitter::emitNEON1RegModImmInstruction(const MachineInstr &MI) {
1718  unsigned Binary = getBinaryCodeForInstr(MI);
1719  // Destination register is encoded in Dd.
1720  Binary |= encodeNEONRd(MI, 0);
1721  // Immediate fields: Op, Cmode, I, Imm3, Imm4
1722  unsigned Imm = MI.getOperand(1).getImm();
1723  unsigned Op = (Imm >> 12) & 1;
1724  unsigned Cmode = (Imm >> 8) & 0xf;
1725  unsigned I = (Imm >> 7) & 1;
1726  unsigned Imm3 = (Imm >> 4) & 0x7;
1727  unsigned Imm4 = Imm & 0xf;
1728  Binary |= (I << 24) | (Imm3 << 16) | (Cmode << 8) | (Op << 5) | Imm4;
1729  if (IsThumb)
1730    Binary = convertNEONDataProcToThumb(Binary);
1731  emitWordLE(Binary);
1732}
1733
1734void ARMCodeEmitter::emitNEON2RegInstruction(const MachineInstr &MI) {
1735  const TargetInstrDesc &TID = MI.getDesc();
1736  unsigned Binary = getBinaryCodeForInstr(MI);
1737  // Destination register is encoded in Dd; source register in Dm.
1738  unsigned OpIdx = 0;
1739  Binary |= encodeNEONRd(MI, OpIdx++);
1740  if (TID.getOperandConstraint(OpIdx, TOI::TIED_TO) != -1)
1741    ++OpIdx;
1742  Binary |= encodeNEONRm(MI, OpIdx);
1743  if (IsThumb)
1744    Binary = convertNEONDataProcToThumb(Binary);
1745  // FIXME: This does not handle VDUPfdf or VDUPfqf.
1746  emitWordLE(Binary);
1747}
1748
1749void ARMCodeEmitter::emitNEON3RegInstruction(const MachineInstr &MI) {
1750  const TargetInstrDesc &TID = MI.getDesc();
1751  unsigned Binary = getBinaryCodeForInstr(MI);
1752  // Destination register is encoded in Dd; source registers in Dn and Dm.
1753  unsigned OpIdx = 0;
1754  Binary |= encodeNEONRd(MI, OpIdx++);
1755  if (TID.getOperandConstraint(OpIdx, TOI::TIED_TO) != -1)
1756    ++OpIdx;
1757  Binary |= encodeNEONRn(MI, OpIdx++);
1758  if (TID.getOperandConstraint(OpIdx, TOI::TIED_TO) != -1)
1759    ++OpIdx;
1760  Binary |= encodeNEONRm(MI, OpIdx);
1761  if (IsThumb)
1762    Binary = convertNEONDataProcToThumb(Binary);
1763  // FIXME: This does not handle VMOVDneon or VMOVQ.
1764  emitWordLE(Binary);
1765}
1766
1767#include "ARMGenCodeEmitter.inc"
1768