ARMCodeEmitter.cpp revision efb9181429f459e5e04f1d79533bcdc3dbac2582 
1//===-- ARM/ARMCodeEmitter.cpp - Convert ARM code to machine code ---------===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file contains the pass that transforms the ARM machine instructions into
11// relocatable machine code.
12//
13//===----------------------------------------------------------------------===//
14
15#define DEBUG_TYPE "arm-emitter"
16#include "ARM.h"
17#include "ARMAddressingModes.h"
18#include "ARMInstrInfo.h"
19#include "ARMRelocations.h"
20#include "ARMSubtarget.h"
21#include "ARMTargetMachine.h"
22#include "llvm/Function.h"
23#include "llvm/PassManager.h"
24#include "llvm/CodeGen/MachineCodeEmitter.h"
25#include "llvm/CodeGen/MachineFunctionPass.h"
26#include "llvm/CodeGen/MachineInstr.h"
27#include "llvm/CodeGen/Passes.h"
28#include "llvm/ADT/Statistic.h"
29#include "llvm/Support/Compiler.h"
30#include "llvm/Support/Debug.h"
31using namespace llvm;
32
33STATISTIC(NumEmitted, "Number of machine instructions emitted");
34
35namespace {
36  class VISIBILITY_HIDDEN ARMCodeEmitter : public MachineFunctionPass {
37    const ARMInstrInfo  *II;
38    const TargetData    *TD;
39    TargetMachine       &TM;
40    MachineCodeEmitter  &MCE;
41  public:
42    static char ID;
43    explicit ARMCodeEmitter(TargetMachine &tm, MachineCodeEmitter &mce)
44      : MachineFunctionPass(&ID), II(0), TD(0), TM(tm),
45      MCE(mce) {}
46    ARMCodeEmitter(TargetMachine &tm, MachineCodeEmitter &mce,
47            const ARMInstrInfo &ii, const TargetData &td)
48      : MachineFunctionPass(&ID), II(&ii), TD(&td), TM(tm),
49      MCE(mce) {}
50
51    bool runOnMachineFunction(MachineFunction &MF);
52
53    virtual const char *getPassName() const {
54      return "ARM Machine Code Emitter";
55    }
56
57    void emitInstruction(const MachineInstr &MI);
58
59  private:
60    unsigned getAddrModeNoneInstrBinary(const MachineInstr &MI,
61                                        const TargetInstrDesc &TID,
62                                        unsigned Binary);
63
64    unsigned getMachineSoRegOpValue(const MachineInstr &MI,
65                                    const TargetInstrDesc &TID,
66                                    unsigned OpIdx);
67
68    unsigned getAddrMode1SBit(const MachineInstr &MI,
69                              const TargetInstrDesc &TID) const;
70
71    unsigned getAddrMode1InstrBinary(const MachineInstr &MI,
72                                     const TargetInstrDesc &TID,
73                                     unsigned Binary);
74    unsigned getAddrMode2InstrBinary(const MachineInstr &MI,
75                                     const TargetInstrDesc &TID,
76                                     unsigned Binary);
77    unsigned getAddrMode3InstrBinary(const MachineInstr &MI,
78                                     const TargetInstrDesc &TID,
79                                     unsigned Binary);
80    unsigned getAddrMode4InstrBinary(const MachineInstr &MI,
81                                     const TargetInstrDesc &TID,
82                                     unsigned Binary);
83
84    /// getInstrBinary - Return binary encoding for the specified
85    /// machine instruction.
86    unsigned getInstrBinary(const MachineInstr &MI);
87
88    /// getBinaryCodeForInstr - This function, generated by the
89    /// CodeEmitterGenerator using TableGen, produces the binary encoding for
90    /// machine instructions.
91    ///
92    unsigned getBinaryCodeForInstr(const MachineInstr &MI);
93
94    /// getMachineOpValue - Return binary encoding of operand. If the machine
95    /// operand requires relocation, record the relocation and return zero.
96    unsigned getMachineOpValue(const MachineInstr &MI, unsigned OpIdx) {
97      return getMachineOpValue(MI, MI.getOperand(OpIdx));
98    }
99    unsigned getMachineOpValue(const MachineInstr &MI,
100                               const MachineOperand &MO);
101
102    /// getBaseOpcodeFor - Return the opcode value.
103    ///
104    unsigned getBaseOpcodeFor(const TargetInstrDesc &TID) const {
105      return (TID.TSFlags & ARMII::OpcodeMask) >> ARMII::OpcodeShift;
106    }
107
108    /// getShiftOp - Return the shift opcode (bit[6:5]) of the machine operand.
109    ///
110    unsigned getShiftOp(const MachineOperand &MO) const ;
111
112    /// Routines that handle operands which add machine relocations which are
113    /// fixed up by the JIT fixup stage.
114    void emitGlobalAddressForCall(GlobalValue *GV, bool DoesntNeedStub);
115    void emitExternalSymbolAddress(const char *ES, unsigned Reloc);
116    void emitConstPoolAddress(unsigned CPI, unsigned Reloc,
117                              int Disp = 0, unsigned PCAdj = 0 );
118    void emitJumpTableAddress(unsigned JTI, unsigned Reloc,
119                              unsigned PCAdj = 0);
120    void emitGlobalConstant(const Constant *CV);
121    void emitMachineBasicBlock(MachineBasicBlock *BB);
122  };
123  char ARMCodeEmitter::ID = 0;
124}
125
126/// createARMCodeEmitterPass - Return a pass that emits the collected ARM code
127/// to the specified MCE object.
128FunctionPass *llvm::createARMCodeEmitterPass(ARMTargetMachine &TM,
129                                             MachineCodeEmitter &MCE) {
130  return new ARMCodeEmitter(TM, MCE);
131}
132
133bool ARMCodeEmitter::runOnMachineFunction(MachineFunction &MF) {
134  assert((MF.getTarget().getRelocationModel() != Reloc::Default ||
135          MF.getTarget().getRelocationModel() != Reloc::Static) &&
136         "JIT relocation model must be set to static or default!");
137  II = ((ARMTargetMachine&)MF.getTarget()).getInstrInfo();
138  TD = ((ARMTargetMachine&)MF.getTarget()).getTargetData();
139
140  do {
141    DOUT << "JITTing function '" << MF.getFunction()->getName() << "'\n";
142    MCE.startFunction(MF);
143    for (MachineFunction::iterator MBB = MF.begin(), E = MF.end();
144         MBB != E; ++MBB) {
145      MCE.StartMachineBasicBlock(MBB);
146      for (MachineBasicBlock::const_iterator I = MBB->begin(), E = MBB->end();
147           I != E; ++I)
148        emitInstruction(*I);
149    }
150  } while (MCE.finishFunction(MF));
151
152  return false;
153}
154
155/// getShiftOp - Return the shift opcode (bit[6:5]) of the machine operand.
156///
157unsigned ARMCodeEmitter::getShiftOp(const MachineOperand &MO) const {
158  switch (ARM_AM::getAM2ShiftOpc(MO.getImm())) {
159  default: assert(0 && "Unknown shift opc!");
160  case ARM_AM::asr: return 2;
161  case ARM_AM::lsl: return 0;
162  case ARM_AM::lsr: return 1;
163  case ARM_AM::ror:
164  case ARM_AM::rrx: return 3;
165  }
166  return 0;
167}
168
169/// getMachineOpValue - Return binary encoding of operand. If the machine
170/// operand requires relocation, record the relocation and return zero.
171unsigned ARMCodeEmitter::getMachineOpValue(const MachineInstr &MI,
172                                           const MachineOperand &MO) {
173  if (MO.isRegister())
174    return ARMRegisterInfo::getRegisterNumbering(MO.getReg());
175  else if (MO.isImmediate())
176    return static_cast<unsigned>(MO.getImm());
177  else if (MO.isGlobalAddress())
178    emitGlobalAddressForCall(MO.getGlobal(), false);
179  else if (MO.isExternalSymbol())
180    emitExternalSymbolAddress(MO.getSymbolName(), ARM::reloc_arm_relative);
181  else if (MO.isConstantPoolIndex())
182    emitConstPoolAddress(MO.getIndex(), ARM::reloc_arm_relative);
183  else if (MO.isJumpTableIndex())
184    emitJumpTableAddress(MO.getIndex(), ARM::reloc_arm_relative);
185  else if (MO.isMachineBasicBlock())
186    emitMachineBasicBlock(MO.getMBB());
187
188  abort();
189  return 0;
190}
191
192/// emitGlobalAddressForCall - Emit the specified address to the code stream
193/// assuming this is part of a function call, which is PC relative.
194///
195void ARMCodeEmitter::emitGlobalAddressForCall(GlobalValue *GV,
196                                              bool DoesntNeedStub) {
197  MCE.addRelocation(MachineRelocation::getGV(MCE.getCurrentPCOffset(),
198                                             ARM::reloc_arm_branch, GV, 0,
199                                             DoesntNeedStub));
200}
201
202/// emitExternalSymbolAddress - Arrange for the address of an external symbol to
203/// be emitted to the current location in the function, and allow it to be PC
204/// relative.
205void ARMCodeEmitter::emitExternalSymbolAddress(const char *ES, unsigned Reloc) {
206  MCE.addRelocation(MachineRelocation::getExtSym(MCE.getCurrentPCOffset(),
207                                                 Reloc, ES));
208}
209
210/// emitConstPoolAddress - Arrange for the address of an constant pool
211/// to be emitted to the current location in the function, and allow it to be PC
212/// relative.
213void ARMCodeEmitter::emitConstPoolAddress(unsigned CPI, unsigned Reloc,
214                                          int Disp /* = 0 */,
215                                          unsigned PCAdj /* = 0 */) {
216  MCE.addRelocation(MachineRelocation::getConstPool(MCE.getCurrentPCOffset(),
217                                                    Reloc, CPI, PCAdj));
218}
219
220/// emitJumpTableAddress - Arrange for the address of a jump table to
221/// be emitted to the current location in the function, and allow it to be PC
222/// relative.
223void ARMCodeEmitter::emitJumpTableAddress(unsigned JTI, unsigned Reloc,
224                                          unsigned PCAdj /* = 0 */) {
225  MCE.addRelocation(MachineRelocation::getJumpTable(MCE.getCurrentPCOffset(),
226                                                    Reloc, JTI, PCAdj));
227}
228
229/// emitMachineBasicBlock - Emit the specified address basic block.
230void ARMCodeEmitter::emitMachineBasicBlock(MachineBasicBlock *BB) {
231  MCE.addRelocation(MachineRelocation::getBB(MCE.getCurrentPCOffset(),
232                                             ARM::reloc_arm_branch, BB));
233}
234
235void ARMCodeEmitter::emitInstruction(const MachineInstr &MI) {
236  DOUT << MI;
237
238  NumEmitted++;  // Keep track of the # of mi's emitted
239  MCE.emitWordLE(getInstrBinary(MI));
240}
241
242unsigned ARMCodeEmitter::getAddrModeNoneInstrBinary(const MachineInstr &MI,
243                                                    const TargetInstrDesc &TID,
244                                                    unsigned Binary) {
245  switch (TID.TSFlags & ARMII::FormMask) {
246  default:
247    assert(0 && "Unknown instruction subtype!");
248    break;
249  case ARMII::Branch: {
250    // Set signed_immed_24 field
251    Binary |= getMachineOpValue(MI, 0);
252
253    // if it is a conditional branch, set cond field
254    if (TID.Opcode == ARM::Bcc) {
255      Binary &= 0x0FFFFFFF;                      // clear conditional field
256      Binary |= getMachineOpValue(MI, 1) << 28;  // set conditional field
257    }
258    break;
259  }
260  case ARMII::BranchMisc: {
261    // Set bit[19:8] to 0xFFF
262    Binary |= 0xfff << 8;
263    if (TID.Opcode == ARM::BX_RET)
264      Binary |= 0xe; // the return register is LR
265    else
266      // otherwise, set the return register
267      Binary |= getMachineOpValue(MI, 0);
268    break;
269  }
270  }
271
272  return Binary;
273}
274
275unsigned ARMCodeEmitter::getMachineSoRegOpValue(const MachineInstr &MI,
276                                                const TargetInstrDesc &TID,
277                                                unsigned OpIdx) {
278  // Set last operand (register Rm)
279  unsigned Binary = getMachineOpValue(MI, OpIdx);
280
281  const MachineOperand &MO1 = MI.getOperand(OpIdx + 1);
282  const MachineOperand &MO2 = MI.getOperand(OpIdx + 2);
283  ARM_AM::ShiftOpc SOpc = ARM_AM::getSORegShOp(MO2.getImm());
284
285  // Encode the shift opcode.
286  unsigned SBits = 0;
287  unsigned Rs = MO1.getReg();
288  if (Rs) {
289    // Set shift operand (bit[7:4]).
290    // LSL - 0001
291    // LSR - 0011
292    // ASR - 0101
293    // ROR - 0111
294    // RRX - 0110 and bit[11:8] clear.
295    switch (SOpc) {
296    default: assert(0 && "Unknown shift opc!");
297    case ARM_AM::lsl: SBits = 0x1; break;
298    case ARM_AM::lsr: SBits = 0x3; break;
299    case ARM_AM::asr: SBits = 0x5; break;
300    case ARM_AM::ror: SBits = 0x7; break;
301    case ARM_AM::rrx: SBits = 0x6; break;
302    }
303  } else {
304    // Set shift operand (bit[6:4]).
305    // LSL - 000
306    // LSR - 010
307    // ASR - 100
308    // ROR - 110
309    switch (SOpc) {
310    default: assert(0 && "Unknown shift opc!");
311    case ARM_AM::lsl: SBits = 0x0; break;
312    case ARM_AM::lsr: SBits = 0x2; break;
313    case ARM_AM::asr: SBits = 0x4; break;
314    case ARM_AM::ror: SBits = 0x6; break;
315    }
316  }
317  Binary |= SBits << 4;
318  if (SOpc == ARM_AM::rrx)
319    return Binary;
320
321  // Encode the shift operation Rs or shift_imm (except rrx).
322  if (Rs) {
323    // Encode Rs bit[11:8].
324    assert(ARM_AM::getSORegOffset(MO2.getImm()) == 0);
325    return Binary |
326      (ARMRegisterInfo::getRegisterNumbering(Rs) << ARMII::RegRsShift);
327  }
328
329  // Encode shift_imm bit[11:7].
330  return Binary | ARM_AM::getSORegOffset(MO2.getImm()) << 7;
331}
332
333unsigned ARMCodeEmitter::getAddrMode1SBit(const MachineInstr &MI,
334                                          const TargetInstrDesc &TID) const {
335  for (unsigned i = MI.getNumOperands(), e = TID.getNumOperands(); i != e; --i){
336    const MachineOperand &MO = MI.getOperand(i-1);
337    if (MO.isRegister() && MO.isDef() && MO.getReg() == ARM::CPSR)
338      return 1 << ARMII::S_BitShift;
339  }
340  return 0;
341}
342
343unsigned ARMCodeEmitter::getAddrMode1InstrBinary(const MachineInstr &MI,
344                                                 const TargetInstrDesc &TID,
345                                                 unsigned Binary) {
346  if ((TID.TSFlags & ARMII::FormMask) != ARMII::Pseudo)
347    abort(); // FIXME
348
349  // Encode S bit if MI modifies CPSR.
350  Binary |= getAddrMode1SBit(MI, TID);
351
352  // Encode register def if there is one.
353  unsigned NumDefs = TID.getNumDefs();
354  unsigned OpIdx = 0;
355  if (NumDefs) {
356    Binary |= getMachineOpValue(MI, OpIdx) << ARMII::RegRdShift;
357    ++OpIdx;
358  }
359
360  // Encode first non-shifter register operand if ther is one.
361  if ((TID.TSFlags & ARMII::FormMask) != ARMII::UnaryFrm) {
362    Binary |= getMachineOpValue(MI, OpIdx) << ARMII::RegRnShift;
363    ++OpIdx;
364  }
365
366  // Encode shifter operand.
367  if (TID.getNumOperands() - OpIdx > 1)
368    // Encode SoReg.
369    return Binary | getMachineSoRegOpValue(MI, TID, OpIdx);
370
371  const MachineOperand &MO = MI.getOperand(OpIdx);
372  if (MO.isRegister())
373    // Encode register Rm.
374    return Binary | getMachineOpValue(MI, NumDefs + 1);
375
376  // Encode so_imm.
377  // Set bit I(25) to identify this is the immediate form of <shifter_op>
378  Binary |= 1 << ARMII::I_BitShift;
379  unsigned SoImm = MO.getImm();
380  // Encode rotate_imm.
381  Binary |= ARM_AM::getSOImmValRot(SoImm) << ARMII::RotImmShift;
382  // Encode immed_8.
383  Binary |= ARM_AM::getSOImmVal(SoImm);
384  return Binary;
385}
386
387unsigned ARMCodeEmitter::getAddrMode2InstrBinary(const MachineInstr &MI,
388                                                 const TargetInstrDesc &TID,
389                                                 unsigned Binary) {
390  // Set first operand
391  Binary |= getMachineOpValue(MI, 0) << ARMII::RegRdShift;
392
393  // Set second operand
394  Binary |= getMachineOpValue(MI, 1) << ARMII::RegRnShift;
395
396  const MachineOperand &MO2 = MI.getOperand(2);
397  const MachineOperand &MO3 = MI.getOperand(3);
398
399  // Set bit U(23) according to signal of immed value (positive or negative).
400  Binary |= ((ARM_AM::getAM2Op(MO3.getImm()) == ARM_AM::add ? 1 : 0) <<
401            ARMII::U_BitShift);
402  if (!MO2.getReg()) { // is immediate
403    if (ARM_AM::getAM2Offset(MO3.getImm()))
404      // Set the value of offset_12 field
405      Binary |= ARM_AM::getAM2Offset(MO3.getImm());
406    return Binary;
407  }
408
409  // Set bit I(25), because this is not in immediate enconding.
410  Binary |= 1 << ARMII::I_BitShift;
411  assert(TargetRegisterInfo::isPhysicalRegister(MO2.getReg()));
412  // Set bit[3:0] to the corresponding Rm register
413  Binary |= ARMRegisterInfo::getRegisterNumbering(MO2.getReg());
414
415  // if this instr is in scaled register offset/index instruction, set
416  // shift_immed(bit[11:7]) and shift(bit[6:5]) fields.
417  if (unsigned ShImm = ARM_AM::getAM2Offset(MO3.getImm())) {
418    Binary |= getShiftOp(MO3) << 5;  // shift
419    Binary |= ShImm           << 7;  // shift_immed
420  }
421
422  return Binary;
423}
424
425unsigned ARMCodeEmitter::getAddrMode3InstrBinary(const MachineInstr &MI,
426                                                 const TargetInstrDesc &TID,
427                                                 unsigned Binary) {
428  // Set first operand
429  Binary |= getMachineOpValue(MI, 0) << ARMII::RegRdShift;
430
431  // Set second operand
432  Binary |= getMachineOpValue(MI, 1) << ARMII::RegRnShift;
433
434  const MachineOperand &MO2 = MI.getOperand(2);
435  const MachineOperand &MO3 = MI.getOperand(3);
436
437  // Set bit U(23) according to signal of immed value (positive or negative)
438  Binary |= ((ARM_AM::getAM2Op(MO3.getImm()) == ARM_AM::add ? 1 : 0) <<
439             ARMII::U_BitShift);
440
441  // If this instr is in register offset/index encoding, set bit[3:0]
442  // to the corresponding Rm register.
443  if (MO2.getReg()) {
444    Binary |= ARMRegisterInfo::getRegisterNumbering(MO2.getReg());
445    return Binary;
446  }
447
448  // if this instr is in immediate offset/index encoding, set bit 22 to 1
449  if (unsigned ImmOffs = ARM_AM::getAM3Offset(MO3.getImm())) {
450    Binary |= 1 << 22;
451    // Set operands
452    Binary |= (ImmOffs >> 4) << 8;  // immedH
453    Binary |= (ImmOffs & ~0xF);     // immedL
454  }
455
456  return Binary;
457}
458
459unsigned ARMCodeEmitter::getAddrMode4InstrBinary(const MachineInstr &MI,
460                                                 const TargetInstrDesc &TID,
461                                                 unsigned Binary) {
462  // Set first operand
463  Binary |= getMachineOpValue(MI, 0) << ARMII::RegRnShift;
464
465  // Set addressing mode by modifying bits U(23) and P(24)
466  // IA - Increment after  - bit U = 1 and bit P = 0
467  // IB - Increment before - bit U = 1 and bit P = 1
468  // DA - Decrement after  - bit U = 0 and bit P = 0
469  // DB - Decrement before - bit U = 0 and bit P = 1
470  const MachineOperand &MO = MI.getOperand(1);
471  ARM_AM::AMSubMode Mode = ARM_AM::getAM4SubMode(MO.getImm());
472  switch (Mode) {
473  default: assert(0 && "Unknown addressing sub-mode!");
474  case ARM_AM::da:                      break;
475  case ARM_AM::db: Binary |= 0x1 << 24; break;
476  case ARM_AM::ia: Binary |= 0x1 << 23; break;
477  case ARM_AM::ib: Binary |= 0x3 << 23; break;
478  }
479
480  // Set bit W(21)
481  if (ARM_AM::getAM4WBFlag(MO.getImm()))
482    Binary |= 0x1 << 21;
483
484  // Set registers
485  for (unsigned i = 4, e = MI.getNumOperands(); i != e; ++i) {
486    const MachineOperand &MO = MI.getOperand(i);
487    if (MO.isRegister() && MO.isImplicit())
488      continue;
489    unsigned RegNum = ARMRegisterInfo::getRegisterNumbering(MO.getReg());
490    assert(TargetRegisterInfo::isPhysicalRegister(MO.getReg()) &&
491           RegNum < 16);
492    Binary |= 0x1 << RegNum;
493  }
494
495  return Binary;
496}
497
498/// getInstrBinary - Return binary encoding for the specified
499/// machine instruction.
500unsigned ARMCodeEmitter::getInstrBinary(const MachineInstr &MI) {
501  // Part of binary is determined by TableGn.
502  unsigned Binary = getBinaryCodeForInstr(MI);
503
504  const TargetInstrDesc &TID = MI.getDesc();
505  switch (TID.TSFlags & ARMII::AddrModeMask) {
506  case ARMII::AddrModeNone:
507    return getAddrModeNoneInstrBinary(MI, TID, Binary);
508  case ARMII::AddrMode1:
509    return getAddrMode1InstrBinary(MI, TID, Binary);
510  case ARMII::AddrMode2:
511    return getAddrMode2InstrBinary(MI, TID, Binary);
512  case ARMII::AddrMode3:
513    return getAddrMode3InstrBinary(MI, TID, Binary);
514  case ARMII::AddrMode4:
515    return getAddrMode4InstrBinary(MI, TID, Binary);
516  }
517
518  abort();
519  return 0;
520}
521
522#include "ARMGenCodeEmitter.inc"
523