ARMCodeEmitter.cpp revision ffdc17bec626bae590717b8af59e4ba1de216bb4 
1//===-- ARM/ARMCodeEmitter.cpp - Convert ARM code to machine code ---------===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file contains the pass that transforms the ARM machine instructions into
11// relocatable machine code.
12//
13//===----------------------------------------------------------------------===//
14
15#define DEBUG_TYPE "jit"
16#include "ARM.h"
17#include "ARMAddressingModes.h"
18#include "ARMConstantPoolValue.h"
19#include "ARMInstrInfo.h"
20#include "ARMRelocations.h"
21#include "ARMSubtarget.h"
22#include "ARMTargetMachine.h"
23#include "llvm/Constants.h"
24#include "llvm/DerivedTypes.h"
25#include "llvm/Function.h"
26#include "llvm/PassManager.h"
27#include "llvm/CodeGen/JITCodeEmitter.h"
28#include "llvm/CodeGen/MachineConstantPool.h"
29#include "llvm/CodeGen/MachineFunctionPass.h"
30#include "llvm/CodeGen/MachineInstr.h"
31#include "llvm/CodeGen/MachineJumpTableInfo.h"
32#include "llvm/CodeGen/MachineModuleInfo.h"
33#include "llvm/CodeGen/Passes.h"
34#include "llvm/ADT/Statistic.h"
35#include "llvm/Support/Debug.h"
36#include "llvm/Support/ErrorHandling.h"
37#include "llvm/Support/raw_ostream.h"
38#ifndef NDEBUG
39#include <iomanip>
40#endif
41using namespace llvm;
42
43STATISTIC(NumEmitted, "Number of machine instructions emitted");
44
45namespace {
46
47  class ARMCodeEmitter : public MachineFunctionPass {
48    ARMJITInfo                *JTI;
49    const ARMInstrInfo        *II;
50    const TargetData          *TD;
51    const ARMSubtarget        *Subtarget;
52    TargetMachine             &TM;
53    JITCodeEmitter            &MCE;
54    MachineModuleInfo *MMI;
55    const std::vector<MachineConstantPoolEntry> *MCPEs;
56    const std::vector<MachineJumpTableEntry> *MJTEs;
57    bool IsPIC;
58    bool IsThumb;
59
60    void getAnalysisUsage(AnalysisUsage &AU) const {
61      AU.addRequired<MachineModuleInfo>();
62      MachineFunctionPass::getAnalysisUsage(AU);
63    }
64
65    static char ID;
66  public:
67    ARMCodeEmitter(TargetMachine &tm, JITCodeEmitter &mce)
68      : MachineFunctionPass(&ID), JTI(0),
69        II((const ARMInstrInfo *)tm.getInstrInfo()),
70        TD(tm.getTargetData()), TM(tm),
71        MCE(mce), MCPEs(0), MJTEs(0),
72        IsPIC(TM.getRelocationModel() == Reloc::PIC_), IsThumb(false) {}
73
74    /// getBinaryCodeForInstr - This function, generated by the
75    /// CodeEmitterGenerator using TableGen, produces the binary encoding for
76    /// machine instructions.
77    unsigned getBinaryCodeForInstr(const MachineInstr &MI);
78
79    bool runOnMachineFunction(MachineFunction &MF);
80
81    virtual const char *getPassName() const {
82      return "ARM Machine Code Emitter";
83    }
84
85    void emitInstruction(const MachineInstr &MI);
86
87  private:
88
89    void emitWordLE(unsigned Binary);
90    void emitDWordLE(uint64_t Binary);
91    void emitConstPoolInstruction(const MachineInstr &MI);
92    void emitMOVi32immInstruction(const MachineInstr &MI);
93    void emitMOVi2piecesInstruction(const MachineInstr &MI);
94    void emitLEApcrelJTInstruction(const MachineInstr &MI);
95    void emitPseudoMoveInstruction(const MachineInstr &MI);
96    void addPCLabel(unsigned LabelID);
97    void emitPseudoInstruction(const MachineInstr &MI);
98    unsigned getMachineSoRegOpValue(const MachineInstr &MI,
99                                    const TargetInstrDesc &TID,
100                                    const MachineOperand &MO,
101                                    unsigned OpIdx);
102
103    unsigned getMachineSoImmOpValue(unsigned SoImm);
104
105    unsigned getAddrModeSBit(const MachineInstr &MI,
106                             const TargetInstrDesc &TID) const;
107
108    void emitDataProcessingInstruction(const MachineInstr &MI,
109                                       unsigned ImplicitRd = 0,
110                                       unsigned ImplicitRn = 0);
111
112    void emitLoadStoreInstruction(const MachineInstr &MI,
113                                  unsigned ImplicitRd = 0,
114                                  unsigned ImplicitRn = 0);
115
116    void emitMiscLoadStoreInstruction(const MachineInstr &MI,
117                                      unsigned ImplicitRn = 0);
118
119    void emitLoadStoreMultipleInstruction(const MachineInstr &MI);
120
121    void emitMulFrmInstruction(const MachineInstr &MI);
122
123    void emitExtendInstruction(const MachineInstr &MI);
124
125    void emitMiscArithInstruction(const MachineInstr &MI);
126
127    void emitBranchInstruction(const MachineInstr &MI);
128
129    void emitInlineJumpTable(unsigned JTIndex);
130
131    void emitMiscBranchInstruction(const MachineInstr &MI);
132
133    void emitVFPArithInstruction(const MachineInstr &MI);
134
135    void emitVFPConversionInstruction(const MachineInstr &MI);
136
137    void emitVFPLoadStoreInstruction(const MachineInstr &MI);
138
139    void emitVFPLoadStoreMultipleInstruction(const MachineInstr &MI);
140
141    void emitMiscInstruction(const MachineInstr &MI);
142
143    void emitNEONLaneInstruction(const MachineInstr &MI);
144    void emitNEONDupInstruction(const MachineInstr &MI);
145    void emitNEON1RegModImmInstruction(const MachineInstr &MI);
146    void emitNEON2RegInstruction(const MachineInstr &MI);
147    void emitNEON3RegInstruction(const MachineInstr &MI);
148
149    /// getMachineOpValue - Return binary encoding of operand. If the machine
150    /// operand requires relocation, record the relocation and return zero.
151    unsigned getMachineOpValue(const MachineInstr &MI,const MachineOperand &MO);
152    unsigned getMachineOpValue(const MachineInstr &MI, unsigned OpIdx) {
153      return getMachineOpValue(MI, MI.getOperand(OpIdx));
154    }
155
156    /// getMovi32Value - Return binary encoding of operand for movw/movt. If the
157    /// machine operand requires relocation, record the relocation and return
158    /// zero.
159    unsigned getMovi32Value(const MachineInstr &MI,const MachineOperand &MO,
160                            unsigned Reloc);
161    unsigned getMovi32Value(const MachineInstr &MI, unsigned OpIdx,
162                            unsigned Reloc) {
163      return getMovi32Value(MI, MI.getOperand(OpIdx), Reloc);
164    }
165
166    /// getShiftOp - Return the shift opcode (bit[6:5]) of the immediate value.
167    ///
168    unsigned getShiftOp(unsigned Imm) const ;
169
170    /// Routines that handle operands which add machine relocations which are
171    /// fixed up by the relocation stage.
172    void emitGlobalAddress(const GlobalValue *GV, unsigned Reloc,
173                           bool MayNeedFarStub,  bool Indirect,
174                           intptr_t ACPV = 0);
175    void emitExternalSymbolAddress(const char *ES, unsigned Reloc);
176    void emitConstPoolAddress(unsigned CPI, unsigned Reloc);
177    void emitJumpTableAddress(unsigned JTIndex, unsigned Reloc);
178    void emitMachineBasicBlock(MachineBasicBlock *BB, unsigned Reloc,
179                               intptr_t JTBase = 0);
180  };
181}
182
183char ARMCodeEmitter::ID = 0;
184
185/// createARMJITCodeEmitterPass - Return a pass that emits the collected ARM
186/// code to the specified MCE object.
187FunctionPass *llvm::createARMJITCodeEmitterPass(ARMBaseTargetMachine &TM,
188                                                JITCodeEmitter &JCE) {
189  return new ARMCodeEmitter(TM, JCE);
190}
191
192bool ARMCodeEmitter::runOnMachineFunction(MachineFunction &MF) {
193  assert((MF.getTarget().getRelocationModel() != Reloc::Default ||
194          MF.getTarget().getRelocationModel() != Reloc::Static) &&
195         "JIT relocation model must be set to static or default!");
196  JTI = ((ARMTargetMachine &)MF.getTarget()).getJITInfo();
197  II = ((const ARMTargetMachine &)MF.getTarget()).getInstrInfo();
198  TD = ((const ARMTargetMachine &)MF.getTarget()).getTargetData();
199  Subtarget = &TM.getSubtarget<ARMSubtarget>();
200  MCPEs = &MF.getConstantPool()->getConstants();
201  MJTEs = 0;
202  if (MF.getJumpTableInfo()) MJTEs = &MF.getJumpTableInfo()->getJumpTables();
203  IsPIC = TM.getRelocationModel() == Reloc::PIC_;
204  IsThumb = MF.getInfo<ARMFunctionInfo>()->isThumbFunction();
205  JTI->Initialize(MF, IsPIC);
206  MMI = &getAnalysis<MachineModuleInfo>();
207  MCE.setModuleInfo(MMI);
208
209  do {
210    DEBUG(errs() << "JITTing function '"
211          << MF.getFunction()->getName() << "'\n");
212    MCE.startFunction(MF);
213    for (MachineFunction::iterator MBB = MF.begin(), E = MF.end();
214         MBB != E; ++MBB) {
215      MCE.StartMachineBasicBlock(MBB);
216      for (MachineBasicBlock::const_iterator I = MBB->begin(), E = MBB->end();
217           I != E; ++I)
218        emitInstruction(*I);
219    }
220  } while (MCE.finishFunction(MF));
221
222  return false;
223}
224
225/// getShiftOp - Return the shift opcode (bit[6:5]) of the immediate value.
226///
227unsigned ARMCodeEmitter::getShiftOp(unsigned Imm) const {
228  switch (ARM_AM::getAM2ShiftOpc(Imm)) {
229  default: llvm_unreachable("Unknown shift opc!");
230  case ARM_AM::asr: return 2;
231  case ARM_AM::lsl: return 0;
232  case ARM_AM::lsr: return 1;
233  case ARM_AM::ror:
234  case ARM_AM::rrx: return 3;
235  }
236  return 0;
237}
238
239/// getMovi32Value - Return binary encoding of operand for movw/movt. If the
240/// machine operand requires relocation, record the relocation and return zero.
241unsigned ARMCodeEmitter::getMovi32Value(const MachineInstr &MI,
242                                        const MachineOperand &MO,
243                                        unsigned Reloc) {
244  assert(((Reloc == ARM::reloc_arm_movt) || (Reloc == ARM::reloc_arm_movw))
245      && "Relocation to this function should be for movt or movw");
246
247  if (MO.isImm())
248    return static_cast<unsigned>(MO.getImm());
249  else if (MO.isGlobal())
250    emitGlobalAddress(MO.getGlobal(), Reloc, true, false);
251  else if (MO.isSymbol())
252    emitExternalSymbolAddress(MO.getSymbolName(), Reloc);
253  else if (MO.isMBB())
254    emitMachineBasicBlock(MO.getMBB(), Reloc);
255  else {
256#ifndef NDEBUG
257    errs() << MO;
258#endif
259    llvm_unreachable("Unsupported operand type for movw/movt");
260  }
261  return 0;
262}
263
264/// getMachineOpValue - Return binary encoding of operand. If the machine
265/// operand requires relocation, record the relocation and return zero.
266unsigned ARMCodeEmitter::getMachineOpValue(const MachineInstr &MI,
267                                           const MachineOperand &MO) {
268  if (MO.isReg())
269    return ARMRegisterInfo::getRegisterNumbering(MO.getReg());
270  else if (MO.isImm())
271    return static_cast<unsigned>(MO.getImm());
272  else if (MO.isGlobal())
273    emitGlobalAddress(MO.getGlobal(), ARM::reloc_arm_branch, true, false);
274  else if (MO.isSymbol())
275    emitExternalSymbolAddress(MO.getSymbolName(), ARM::reloc_arm_branch);
276  else if (MO.isCPI()) {
277    const TargetInstrDesc &TID = MI.getDesc();
278    // For VFP load, the immediate offset is multiplied by 4.
279    unsigned Reloc =  ((TID.TSFlags & ARMII::FormMask) == ARMII::VFPLdStFrm)
280      ? ARM::reloc_arm_vfp_cp_entry : ARM::reloc_arm_cp_entry;
281    emitConstPoolAddress(MO.getIndex(), Reloc);
282  } else if (MO.isJTI())
283    emitJumpTableAddress(MO.getIndex(), ARM::reloc_arm_relative);
284  else if (MO.isMBB())
285    emitMachineBasicBlock(MO.getMBB(), ARM::reloc_arm_branch);
286  else {
287#ifndef NDEBUG
288    errs() << MO;
289#endif
290    llvm_unreachable(0);
291  }
292  return 0;
293}
294
295/// emitGlobalAddress - Emit the specified address to the code stream.
296///
297void ARMCodeEmitter::emitGlobalAddress(const GlobalValue *GV, unsigned Reloc,
298                                       bool MayNeedFarStub, bool Indirect,
299                                       intptr_t ACPV) {
300  MachineRelocation MR = Indirect
301    ? MachineRelocation::getIndirectSymbol(MCE.getCurrentPCOffset(), Reloc,
302                                           const_cast<GlobalValue *>(GV),
303                                           ACPV, MayNeedFarStub)
304    : MachineRelocation::getGV(MCE.getCurrentPCOffset(), Reloc,
305                               const_cast<GlobalValue *>(GV), ACPV,
306                               MayNeedFarStub);
307  MCE.addRelocation(MR);
308}
309
310/// emitExternalSymbolAddress - Arrange for the address of an external symbol to
311/// be emitted to the current location in the function, and allow it to be PC
312/// relative.
313void ARMCodeEmitter::emitExternalSymbolAddress(const char *ES, unsigned Reloc) {
314  MCE.addRelocation(MachineRelocation::getExtSym(MCE.getCurrentPCOffset(),
315                                                 Reloc, ES));
316}
317
318/// emitConstPoolAddress - Arrange for the address of an constant pool
319/// to be emitted to the current location in the function, and allow it to be PC
320/// relative.
321void ARMCodeEmitter::emitConstPoolAddress(unsigned CPI, unsigned Reloc) {
322  // Tell JIT emitter we'll resolve the address.
323  MCE.addRelocation(MachineRelocation::getConstPool(MCE.getCurrentPCOffset(),
324                                                    Reloc, CPI, 0, true));
325}
326
327/// emitJumpTableAddress - Arrange for the address of a jump table to
328/// be emitted to the current location in the function, and allow it to be PC
329/// relative.
330void ARMCodeEmitter::emitJumpTableAddress(unsigned JTIndex, unsigned Reloc) {
331  MCE.addRelocation(MachineRelocation::getJumpTable(MCE.getCurrentPCOffset(),
332                                                    Reloc, JTIndex, 0, true));
333}
334
335/// emitMachineBasicBlock - Emit the specified address basic block.
336void ARMCodeEmitter::emitMachineBasicBlock(MachineBasicBlock *BB,
337                                           unsigned Reloc, intptr_t JTBase) {
338  MCE.addRelocation(MachineRelocation::getBB(MCE.getCurrentPCOffset(),
339                                             Reloc, BB, JTBase));
340}
341
342void ARMCodeEmitter::emitWordLE(unsigned Binary) {
343  DEBUG(errs() << "  0x";
344        errs().write_hex(Binary) << "\n");
345  MCE.emitWordLE(Binary);
346}
347
348void ARMCodeEmitter::emitDWordLE(uint64_t Binary) {
349  DEBUG(errs() << "  0x";
350        errs().write_hex(Binary) << "\n");
351  MCE.emitDWordLE(Binary);
352}
353
354void ARMCodeEmitter::emitInstruction(const MachineInstr &MI) {
355  DEBUG(errs() << "JIT: " << (void*)MCE.getCurrentPCValue() << ":\t" << MI);
356
357  MCE.processDebugLoc(MI.getDebugLoc(), true);
358
359  ++NumEmitted;  // Keep track of the # of mi's emitted
360  switch (MI.getDesc().TSFlags & ARMII::FormMask) {
361  default: {
362    llvm_unreachable("Unhandled instruction encoding format!");
363    break;
364  }
365  case ARMII::Pseudo:
366    emitPseudoInstruction(MI);
367    break;
368  case ARMII::DPFrm:
369  case ARMII::DPSoRegFrm:
370    emitDataProcessingInstruction(MI);
371    break;
372  case ARMII::LdFrm:
373  case ARMII::StFrm:
374    emitLoadStoreInstruction(MI);
375    break;
376  case ARMII::LdMiscFrm:
377  case ARMII::StMiscFrm:
378    emitMiscLoadStoreInstruction(MI);
379    break;
380  case ARMII::LdStMulFrm:
381    emitLoadStoreMultipleInstruction(MI);
382    break;
383  case ARMII::MulFrm:
384    emitMulFrmInstruction(MI);
385    break;
386  case ARMII::ExtFrm:
387    emitExtendInstruction(MI);
388    break;
389  case ARMII::ArithMiscFrm:
390    emitMiscArithInstruction(MI);
391    break;
392  case ARMII::BrFrm:
393    emitBranchInstruction(MI);
394    break;
395  case ARMII::BrMiscFrm:
396    emitMiscBranchInstruction(MI);
397    break;
398  // VFP instructions.
399  case ARMII::VFPUnaryFrm:
400  case ARMII::VFPBinaryFrm:
401    emitVFPArithInstruction(MI);
402    break;
403  case ARMII::VFPConv1Frm:
404  case ARMII::VFPConv2Frm:
405  case ARMII::VFPConv3Frm:
406  case ARMII::VFPConv4Frm:
407  case ARMII::VFPConv5Frm:
408    emitVFPConversionInstruction(MI);
409    break;
410  case ARMII::VFPLdStFrm:
411    emitVFPLoadStoreInstruction(MI);
412    break;
413  case ARMII::VFPLdStMulFrm:
414    emitVFPLoadStoreMultipleInstruction(MI);
415    break;
416  case ARMII::VFPMiscFrm:
417    emitMiscInstruction(MI);
418    break;
419  // NEON instructions.
420  case ARMII::NGetLnFrm:
421  case ARMII::NSetLnFrm:
422    emitNEONLaneInstruction(MI);
423    break;
424  case ARMII::NDupFrm:
425    emitNEONDupInstruction(MI);
426    break;
427  case ARMII::N1RegModImmFrm:
428    emitNEON1RegModImmInstruction(MI);
429    break;
430  case ARMII::N2RegFrm:
431    emitNEON2RegInstruction(MI);
432    break;
433  case ARMII::N3RegFrm:
434    emitNEON3RegInstruction(MI);
435    break;
436  }
437  MCE.processDebugLoc(MI.getDebugLoc(), false);
438}
439
440void ARMCodeEmitter::emitConstPoolInstruction(const MachineInstr &MI) {
441  unsigned CPI = MI.getOperand(0).getImm();       // CP instruction index.
442  unsigned CPIndex = MI.getOperand(1).getIndex(); // Actual cp entry index.
443  const MachineConstantPoolEntry &MCPE = (*MCPEs)[CPIndex];
444
445  // Remember the CONSTPOOL_ENTRY address for later relocation.
446  JTI->addConstantPoolEntryAddr(CPI, MCE.getCurrentPCValue());
447
448  // Emit constpool island entry. In most cases, the actual values will be
449  // resolved and relocated after code emission.
450  if (MCPE.isMachineConstantPoolEntry()) {
451    ARMConstantPoolValue *ACPV =
452      static_cast<ARMConstantPoolValue*>(MCPE.Val.MachineCPVal);
453
454    DEBUG(errs() << "  ** ARM constant pool #" << CPI << " @ "
455          << (void*)MCE.getCurrentPCValue() << " " << *ACPV << '\n');
456
457    assert(ACPV->isGlobalValue() && "unsupported constant pool value");
458    const GlobalValue *GV = ACPV->getGV();
459    if (GV) {
460      Reloc::Model RelocM = TM.getRelocationModel();
461      emitGlobalAddress(GV, ARM::reloc_arm_machine_cp_entry,
462                        isa<Function>(GV),
463                        Subtarget->GVIsIndirectSymbol(GV, RelocM),
464                        (intptr_t)ACPV);
465     } else  {
466      emitExternalSymbolAddress(ACPV->getSymbol(), ARM::reloc_arm_absolute);
467    }
468    emitWordLE(0);
469  } else {
470    const Constant *CV = MCPE.Val.ConstVal;
471
472    DEBUG({
473        errs() << "  ** Constant pool #" << CPI << " @ "
474               << (void*)MCE.getCurrentPCValue() << " ";
475        if (const Function *F = dyn_cast<Function>(CV))
476          errs() << F->getName();
477        else
478          errs() << *CV;
479        errs() << '\n';
480      });
481
482    if (const GlobalValue *GV = dyn_cast<GlobalValue>(CV)) {
483      emitGlobalAddress(GV, ARM::reloc_arm_absolute, isa<Function>(GV), false);
484      emitWordLE(0);
485    } else if (const ConstantInt *CI = dyn_cast<ConstantInt>(CV)) {
486      uint32_t Val = *(uint32_t*)CI->getValue().getRawData();
487      emitWordLE(Val);
488    } else if (const ConstantFP *CFP = dyn_cast<ConstantFP>(CV)) {
489      if (CFP->getType()->isFloatTy())
490        emitWordLE(CFP->getValueAPF().bitcastToAPInt().getZExtValue());
491      else if (CFP->getType()->isDoubleTy())
492        emitDWordLE(CFP->getValueAPF().bitcastToAPInt().getZExtValue());
493      else {
494        llvm_unreachable("Unable to handle this constantpool entry!");
495      }
496    } else {
497      llvm_unreachable("Unable to handle this constantpool entry!");
498    }
499  }
500}
501
502void ARMCodeEmitter::emitMOVi32immInstruction(const MachineInstr &MI) {
503  const MachineOperand &MO0 = MI.getOperand(0);
504  const MachineOperand &MO1 = MI.getOperand(1);
505
506  // Emit the 'movw' instruction.
507  unsigned Binary = 0x30 << 20;  // mov: Insts{27-20} = 0b00110000
508
509  unsigned Lo16 = getMovi32Value(MI, MO1, ARM::reloc_arm_movw) & 0xFFFF;
510
511  // Set the conditional execution predicate.
512  Binary |= II->getPredicate(&MI) << ARMII::CondShift;
513
514  // Encode Rd.
515  Binary |= getMachineOpValue(MI, MO0) << ARMII::RegRdShift;
516
517  // Encode imm16 as imm4:imm12
518  Binary |= Lo16 & 0xFFF; // Insts{11-0} = imm12
519  Binary |= ((Lo16 >> 12) & 0xF) << 16; // Insts{19-16} = imm4
520  emitWordLE(Binary);
521
522  unsigned Hi16 = getMovi32Value(MI, MO1, ARM::reloc_arm_movt) >> 16;
523  // Emit the 'movt' instruction.
524  Binary = 0x34 << 20; // movt: Insts{27-20} = 0b00110100
525
526  // Set the conditional execution predicate.
527  Binary |= II->getPredicate(&MI) << ARMII::CondShift;
528
529  // Encode Rd.
530  Binary |= getMachineOpValue(MI, MO0) << ARMII::RegRdShift;
531
532  // Encode imm16 as imm4:imm1, same as movw above.
533  Binary |= Hi16 & 0xFFF;
534  Binary |= ((Hi16 >> 12) & 0xF) << 16;
535  emitWordLE(Binary);
536}
537
538void ARMCodeEmitter::emitMOVi2piecesInstruction(const MachineInstr &MI) {
539  const MachineOperand &MO0 = MI.getOperand(0);
540  const MachineOperand &MO1 = MI.getOperand(1);
541  assert(MO1.isImm() && ARM_AM::isSOImmTwoPartVal(MO1.getImm()) &&
542                                                  "Not a valid so_imm value!");
543  unsigned V1 = ARM_AM::getSOImmTwoPartFirst(MO1.getImm());
544  unsigned V2 = ARM_AM::getSOImmTwoPartSecond(MO1.getImm());
545
546  // Emit the 'mov' instruction.
547  unsigned Binary = 0xd << 21;  // mov: Insts{24-21} = 0b1101
548
549  // Set the conditional execution predicate.
550  Binary |= II->getPredicate(&MI) << ARMII::CondShift;
551
552  // Encode Rd.
553  Binary |= getMachineOpValue(MI, MO0) << ARMII::RegRdShift;
554
555  // Encode so_imm.
556  // Set bit I(25) to identify this is the immediate form of <shifter_op>
557  Binary |= 1 << ARMII::I_BitShift;
558  Binary |= getMachineSoImmOpValue(V1);
559  emitWordLE(Binary);
560
561  // Now the 'orr' instruction.
562  Binary = 0xc << 21;  // orr: Insts{24-21} = 0b1100
563
564  // Set the conditional execution predicate.
565  Binary |= II->getPredicate(&MI) << ARMII::CondShift;
566
567  // Encode Rd.
568  Binary |= getMachineOpValue(MI, MO0) << ARMII::RegRdShift;
569
570  // Encode Rn.
571  Binary |= getMachineOpValue(MI, MO0) << ARMII::RegRnShift;
572
573  // Encode so_imm.
574  // Set bit I(25) to identify this is the immediate form of <shifter_op>
575  Binary |= 1 << ARMII::I_BitShift;
576  Binary |= getMachineSoImmOpValue(V2);
577  emitWordLE(Binary);
578}
579
580void ARMCodeEmitter::emitLEApcrelJTInstruction(const MachineInstr &MI) {
581  // It's basically add r, pc, (LJTI - $+8)
582
583  const TargetInstrDesc &TID = MI.getDesc();
584
585  // Emit the 'add' instruction.
586  unsigned Binary = 0x4 << 21;  // add: Insts{24-31} = 0b0100
587
588  // Set the conditional execution predicate
589  Binary |= II->getPredicate(&MI) << ARMII::CondShift;
590
591  // Encode S bit if MI modifies CPSR.
592  Binary |= getAddrModeSBit(MI, TID);
593
594  // Encode Rd.
595  Binary |= getMachineOpValue(MI, 0) << ARMII::RegRdShift;
596
597  // Encode Rn which is PC.
598  Binary |= ARMRegisterInfo::getRegisterNumbering(ARM::PC) << ARMII::RegRnShift;
599
600  // Encode the displacement.
601  Binary |= 1 << ARMII::I_BitShift;
602  emitJumpTableAddress(MI.getOperand(1).getIndex(), ARM::reloc_arm_jt_base);
603
604  emitWordLE(Binary);
605}
606
607void ARMCodeEmitter::emitPseudoMoveInstruction(const MachineInstr &MI) {
608  unsigned Opcode = MI.getDesc().Opcode;
609
610  // Part of binary is determined by TableGn.
611  unsigned Binary = getBinaryCodeForInstr(MI);
612
613  // Set the conditional execution predicate
614  Binary |= II->getPredicate(&MI) << ARMII::CondShift;
615
616  // Encode S bit if MI modifies CPSR.
617  if (Opcode == ARM::MOVsrl_flag || Opcode == ARM::MOVsra_flag)
618    Binary |= 1 << ARMII::S_BitShift;
619
620  // Encode register def if there is one.
621  Binary |= getMachineOpValue(MI, 0) << ARMII::RegRdShift;
622
623  // Encode the shift operation.
624  switch (Opcode) {
625  default: break;
626  case ARM::MOVrx:
627    // rrx
628    Binary |= 0x6 << 4;
629    break;
630  case ARM::MOVsrl_flag:
631    // lsr #1
632    Binary |= (0x2 << 4) | (1 << 7);
633    break;
634  case ARM::MOVsra_flag:
635    // asr #1
636    Binary |= (0x4 << 4) | (1 << 7);
637    break;
638  }
639
640  // Encode register Rm.
641  Binary |= getMachineOpValue(MI, 1);
642
643  emitWordLE(Binary);
644}
645
646void ARMCodeEmitter::addPCLabel(unsigned LabelID) {
647  DEBUG(errs() << "  ** LPC" << LabelID << " @ "
648        << (void*)MCE.getCurrentPCValue() << '\n');
649  JTI->addPCLabelAddr(LabelID, MCE.getCurrentPCValue());
650}
651
652void ARMCodeEmitter::emitPseudoInstruction(const MachineInstr &MI) {
653  unsigned Opcode = MI.getDesc().Opcode;
654  switch (Opcode) {
655  default:
656    llvm_unreachable("ARMCodeEmitter::emitPseudoInstruction");
657  case TargetOpcode::INLINEASM: {
658    // We allow inline assembler nodes with empty bodies - they can
659    // implicitly define registers, which is ok for JIT.
660    if (MI.getOperand(0).getSymbolName()[0]) {
661      report_fatal_error("JIT does not support inline asm!");
662    }
663    break;
664  }
665  case TargetOpcode::DBG_LABEL:
666  case TargetOpcode::EH_LABEL:
667    MCE.emitLabel(MI.getOperand(0).getMCSymbol());
668    break;
669  case TargetOpcode::IMPLICIT_DEF:
670  case TargetOpcode::KILL:
671    // Do nothing.
672    break;
673  case ARM::CONSTPOOL_ENTRY:
674    emitConstPoolInstruction(MI);
675    break;
676  case ARM::PICADD: {
677    // Remember of the address of the PC label for relocation later.
678    addPCLabel(MI.getOperand(2).getImm());
679    // PICADD is just an add instruction that implicitly read pc.
680    emitDataProcessingInstruction(MI, 0, ARM::PC);
681    break;
682  }
683  case ARM::PICLDR:
684  case ARM::PICLDRB:
685  case ARM::PICSTR:
686  case ARM::PICSTRB: {
687    // Remember of the address of the PC label for relocation later.
688    addPCLabel(MI.getOperand(2).getImm());
689    // These are just load / store instructions that implicitly read pc.
690    emitLoadStoreInstruction(MI, 0, ARM::PC);
691    break;
692  }
693  case ARM::PICLDRH:
694  case ARM::PICLDRSH:
695  case ARM::PICLDRSB:
696  case ARM::PICSTRH: {
697    // Remember of the address of the PC label for relocation later.
698    addPCLabel(MI.getOperand(2).getImm());
699    // These are just load / store instructions that implicitly read pc.
700    emitMiscLoadStoreInstruction(MI, ARM::PC);
701    break;
702  }
703
704  case ARM::MOVi32imm:
705    emitMOVi32immInstruction(MI);
706    break;
707
708  case ARM::MOVi2pieces:
709    // Two instructions to materialize a constant.
710    emitMOVi2piecesInstruction(MI);
711    break;
712  case ARM::LEApcrelJT:
713    // Materialize jumptable address.
714    emitLEApcrelJTInstruction(MI);
715    break;
716  case ARM::MOVrx:
717  case ARM::MOVsrl_flag:
718  case ARM::MOVsra_flag:
719    emitPseudoMoveInstruction(MI);
720    break;
721  }
722}
723
724unsigned ARMCodeEmitter::getMachineSoRegOpValue(const MachineInstr &MI,
725                                                const TargetInstrDesc &TID,
726                                                const MachineOperand &MO,
727                                                unsigned OpIdx) {
728  unsigned Binary = getMachineOpValue(MI, MO);
729
730  const MachineOperand &MO1 = MI.getOperand(OpIdx + 1);
731  const MachineOperand &MO2 = MI.getOperand(OpIdx + 2);
732  ARM_AM::ShiftOpc SOpc = ARM_AM::getSORegShOp(MO2.getImm());
733
734  // Encode the shift opcode.
735  unsigned SBits = 0;
736  unsigned Rs = MO1.getReg();
737  if (Rs) {
738    // Set shift operand (bit[7:4]).
739    // LSL - 0001
740    // LSR - 0011
741    // ASR - 0101
742    // ROR - 0111
743    // RRX - 0110 and bit[11:8] clear.
744    switch (SOpc) {
745    default: llvm_unreachable("Unknown shift opc!");
746    case ARM_AM::lsl: SBits = 0x1; break;
747    case ARM_AM::lsr: SBits = 0x3; break;
748    case ARM_AM::asr: SBits = 0x5; break;
749    case ARM_AM::ror: SBits = 0x7; break;
750    case ARM_AM::rrx: SBits = 0x6; break;
751    }
752  } else {
753    // Set shift operand (bit[6:4]).
754    // LSL - 000
755    // LSR - 010
756    // ASR - 100
757    // ROR - 110
758    switch (SOpc) {
759    default: llvm_unreachable("Unknown shift opc!");
760    case ARM_AM::lsl: SBits = 0x0; break;
761    case ARM_AM::lsr: SBits = 0x2; break;
762    case ARM_AM::asr: SBits = 0x4; break;
763    case ARM_AM::ror: SBits = 0x6; break;
764    }
765  }
766  Binary |= SBits << 4;
767  if (SOpc == ARM_AM::rrx)
768    return Binary;
769
770  // Encode the shift operation Rs or shift_imm (except rrx).
771  if (Rs) {
772    // Encode Rs bit[11:8].
773    assert(ARM_AM::getSORegOffset(MO2.getImm()) == 0);
774    return Binary |
775      (ARMRegisterInfo::getRegisterNumbering(Rs) << ARMII::RegRsShift);
776  }
777
778  // Encode shift_imm bit[11:7].
779  return Binary | ARM_AM::getSORegOffset(MO2.getImm()) << 7;
780}
781
782unsigned ARMCodeEmitter::getMachineSoImmOpValue(unsigned SoImm) {
783  int SoImmVal = ARM_AM::getSOImmVal(SoImm);
784  assert(SoImmVal != -1 && "Not a valid so_imm value!");
785
786  // Encode rotate_imm.
787  unsigned Binary = (ARM_AM::getSOImmValRot((unsigned)SoImmVal) >> 1)
788    << ARMII::SoRotImmShift;
789
790  // Encode immed_8.
791  Binary |= ARM_AM::getSOImmValImm((unsigned)SoImmVal);
792  return Binary;
793}
794
795unsigned ARMCodeEmitter::getAddrModeSBit(const MachineInstr &MI,
796                                         const TargetInstrDesc &TID) const {
797  for (unsigned i = MI.getNumOperands(), e = TID.getNumOperands(); i != e; --i){
798    const MachineOperand &MO = MI.getOperand(i-1);
799    if (MO.isReg() && MO.isDef() && MO.getReg() == ARM::CPSR)
800      return 1 << ARMII::S_BitShift;
801  }
802  return 0;
803}
804
805void ARMCodeEmitter::emitDataProcessingInstruction(const MachineInstr &MI,
806                                                   unsigned ImplicitRd,
807                                                   unsigned ImplicitRn) {
808  const TargetInstrDesc &TID = MI.getDesc();
809
810  // Part of binary is determined by TableGn.
811  unsigned Binary = getBinaryCodeForInstr(MI);
812
813  // Set the conditional execution predicate
814  Binary |= II->getPredicate(&MI) << ARMII::CondShift;
815
816  // Encode S bit if MI modifies CPSR.
817  Binary |= getAddrModeSBit(MI, TID);
818
819  // Encode register def if there is one.
820  unsigned NumDefs = TID.getNumDefs();
821  unsigned OpIdx = 0;
822  if (NumDefs)
823    Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRdShift;
824  else if (ImplicitRd)
825    // Special handling for implicit use (e.g. PC).
826    Binary |= (ARMRegisterInfo::getRegisterNumbering(ImplicitRd)
827               << ARMII::RegRdShift);
828
829  if (TID.Opcode == ARM::MOVi16) {
830      // Get immediate from MI.
831      unsigned Lo16 = getMovi32Value(MI, MI.getOperand(OpIdx),
832                      ARM::reloc_arm_movw);
833      // Encode imm which is the same as in emitMOVi32immInstruction().
834      Binary |= Lo16 & 0xFFF;
835      Binary |= ((Lo16 >> 12) & 0xF) << 16;
836      emitWordLE(Binary);
837      return;
838  } else if(TID.Opcode == ARM::MOVTi16) {
839      unsigned Hi16 = (getMovi32Value(MI, MI.getOperand(OpIdx),
840                       ARM::reloc_arm_movt) >> 16);
841      Binary |= Hi16 & 0xFFF;
842      Binary |= ((Hi16 >> 12) & 0xF) << 16;
843      emitWordLE(Binary);
844      return;
845  } else if ((TID.Opcode == ARM::BFC) || (TID.Opcode == ARM::BFI)) {
846      uint32_t v = ~MI.getOperand(2).getImm();
847      int32_t lsb = CountTrailingZeros_32(v);
848      int32_t msb = (32 - CountLeadingZeros_32(v)) - 1;
849      // Instr{20-16} = msb, Instr{11-7} = lsb
850      Binary |= (msb & 0x1F) << 16;
851      Binary |= (lsb & 0x1F) << 7;
852      emitWordLE(Binary);
853      return;
854  } else if ((TID.Opcode == ARM::UBFX) || (TID.Opcode == ARM::SBFX)) {
855      // Encode Rn in Instr{0-3}
856      Binary |= getMachineOpValue(MI, OpIdx++);
857
858      uint32_t lsb = MI.getOperand(OpIdx++).getImm();
859      uint32_t widthm1 = MI.getOperand(OpIdx++).getImm() - 1;
860
861      // Instr{20-16} = widthm1, Instr{11-7} = lsb
862      Binary |= (widthm1 & 0x1F) << 16;
863      Binary |= (lsb & 0x1F) << 7;
864      emitWordLE(Binary);
865      return;
866  }
867
868  // If this is a two-address operand, skip it. e.g. MOVCCr operand 1.
869  if (TID.getOperandConstraint(OpIdx, TOI::TIED_TO) != -1)
870    ++OpIdx;
871
872  // Encode first non-shifter register operand if there is one.
873  bool isUnary = TID.TSFlags & ARMII::UnaryDP;
874  if (!isUnary) {
875    if (ImplicitRn)
876      // Special handling for implicit use (e.g. PC).
877      Binary |= (ARMRegisterInfo::getRegisterNumbering(ImplicitRn)
878                 << ARMII::RegRnShift);
879    else {
880      Binary |= getMachineOpValue(MI, OpIdx) << ARMII::RegRnShift;
881      ++OpIdx;
882    }
883  }
884
885  // Encode shifter operand.
886  const MachineOperand &MO = MI.getOperand(OpIdx);
887  if ((TID.TSFlags & ARMII::FormMask) == ARMII::DPSoRegFrm) {
888    // Encode SoReg.
889    emitWordLE(Binary | getMachineSoRegOpValue(MI, TID, MO, OpIdx));
890    return;
891  }
892
893  if (MO.isReg()) {
894    // Encode register Rm.
895    emitWordLE(Binary | ARMRegisterInfo::getRegisterNumbering(MO.getReg()));
896    return;
897  }
898
899  // Encode so_imm.
900  Binary |= getMachineSoImmOpValue((unsigned)MO.getImm());
901
902  emitWordLE(Binary);
903}
904
905void ARMCodeEmitter::emitLoadStoreInstruction(const MachineInstr &MI,
906                                              unsigned ImplicitRd,
907                                              unsigned ImplicitRn) {
908  const TargetInstrDesc &TID = MI.getDesc();
909  unsigned Form = TID.TSFlags & ARMII::FormMask;
910  bool IsPrePost = (TID.TSFlags & ARMII::IndexModeMask) != 0;
911
912  // Part of binary is determined by TableGn.
913  unsigned Binary = getBinaryCodeForInstr(MI);
914
915  // Set the conditional execution predicate
916  Binary |= II->getPredicate(&MI) << ARMII::CondShift;
917
918  unsigned OpIdx = 0;
919
920  // Operand 0 of a pre- and post-indexed store is the address base
921  // writeback. Skip it.
922  bool Skipped = false;
923  if (IsPrePost && Form == ARMII::StFrm) {
924    ++OpIdx;
925    Skipped = true;
926  }
927
928  // Set first operand
929  if (ImplicitRd)
930    // Special handling for implicit use (e.g. PC).
931    Binary |= (ARMRegisterInfo::getRegisterNumbering(ImplicitRd)
932               << ARMII::RegRdShift);
933  else
934    Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRdShift;
935
936  // Set second operand
937  if (ImplicitRn)
938    // Special handling for implicit use (e.g. PC).
939    Binary |= (ARMRegisterInfo::getRegisterNumbering(ImplicitRn)
940               << ARMII::RegRnShift);
941  else
942    Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRnShift;
943
944  // If this is a two-address operand, skip it. e.g. LDR_PRE.
945  if (!Skipped && TID.getOperandConstraint(OpIdx, TOI::TIED_TO) != -1)
946    ++OpIdx;
947
948  const MachineOperand &MO2 = MI.getOperand(OpIdx);
949  unsigned AM2Opc = (ImplicitRn == ARM::PC)
950    ? 0 : MI.getOperand(OpIdx+1).getImm();
951
952  // Set bit U(23) according to sign of immed value (positive or negative).
953  Binary |= ((ARM_AM::getAM2Op(AM2Opc) == ARM_AM::add ? 1 : 0) <<
954             ARMII::U_BitShift);
955  if (!MO2.getReg()) { // is immediate
956    if (ARM_AM::getAM2Offset(AM2Opc))
957      // Set the value of offset_12 field
958      Binary |= ARM_AM::getAM2Offset(AM2Opc);
959    emitWordLE(Binary);
960    return;
961  }
962
963  // Set bit I(25), because this is not in immediate enconding.
964  Binary |= 1 << ARMII::I_BitShift;
965  assert(TargetRegisterInfo::isPhysicalRegister(MO2.getReg()));
966  // Set bit[3:0] to the corresponding Rm register
967  Binary |= ARMRegisterInfo::getRegisterNumbering(MO2.getReg());
968
969  // If this instr is in scaled register offset/index instruction, set
970  // shift_immed(bit[11:7]) and shift(bit[6:5]) fields.
971  if (unsigned ShImm = ARM_AM::getAM2Offset(AM2Opc)) {
972    Binary |= getShiftOp(AM2Opc) << ARMII::ShiftImmShift;  // shift
973    Binary |= ShImm              << ARMII::ShiftShift;     // shift_immed
974  }
975
976  emitWordLE(Binary);
977}
978
979void ARMCodeEmitter::emitMiscLoadStoreInstruction(const MachineInstr &MI,
980                                                  unsigned ImplicitRn) {
981  const TargetInstrDesc &TID = MI.getDesc();
982  unsigned Form = TID.TSFlags & ARMII::FormMask;
983  bool IsPrePost = (TID.TSFlags & ARMII::IndexModeMask) != 0;
984
985  // Part of binary is determined by TableGn.
986  unsigned Binary = getBinaryCodeForInstr(MI);
987
988  // Set the conditional execution predicate
989  Binary |= II->getPredicate(&MI) << ARMII::CondShift;
990
991  unsigned OpIdx = 0;
992
993  // Operand 0 of a pre- and post-indexed store is the address base
994  // writeback. Skip it.
995  bool Skipped = false;
996  if (IsPrePost && Form == ARMII::StMiscFrm) {
997    ++OpIdx;
998    Skipped = true;
999  }
1000
1001  // Set first operand
1002  Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRdShift;
1003
1004  // Skip LDRD and STRD's second operand.
1005  if (TID.Opcode == ARM::LDRD || TID.Opcode == ARM::STRD)
1006    ++OpIdx;
1007
1008  // Set second operand
1009  if (ImplicitRn)
1010    // Special handling for implicit use (e.g. PC).
1011    Binary |= (ARMRegisterInfo::getRegisterNumbering(ImplicitRn)
1012               << ARMII::RegRnShift);
1013  else
1014    Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRnShift;
1015
1016  // If this is a two-address operand, skip it. e.g. LDRH_POST.
1017  if (!Skipped && TID.getOperandConstraint(OpIdx, TOI::TIED_TO) != -1)
1018    ++OpIdx;
1019
1020  const MachineOperand &MO2 = MI.getOperand(OpIdx);
1021  unsigned AM3Opc = (ImplicitRn == ARM::PC)
1022    ? 0 : MI.getOperand(OpIdx+1).getImm();
1023
1024  // Set bit U(23) according to sign of immed value (positive or negative)
1025  Binary |= ((ARM_AM::getAM3Op(AM3Opc) == ARM_AM::add ? 1 : 0) <<
1026             ARMII::U_BitShift);
1027
1028  // If this instr is in register offset/index encoding, set bit[3:0]
1029  // to the corresponding Rm register.
1030  if (MO2.getReg()) {
1031    Binary |= ARMRegisterInfo::getRegisterNumbering(MO2.getReg());
1032    emitWordLE(Binary);
1033    return;
1034  }
1035
1036  // This instr is in immediate offset/index encoding, set bit 22 to 1.
1037  Binary |= 1 << ARMII::AM3_I_BitShift;
1038  if (unsigned ImmOffs = ARM_AM::getAM3Offset(AM3Opc)) {
1039    // Set operands
1040    Binary |= (ImmOffs >> 4) << ARMII::ImmHiShift;  // immedH
1041    Binary |= (ImmOffs & 0xF);                      // immedL
1042  }
1043
1044  emitWordLE(Binary);
1045}
1046
1047static unsigned getAddrModeUPBits(unsigned Mode) {
1048  unsigned Binary = 0;
1049
1050  // Set addressing mode by modifying bits U(23) and P(24)
1051  // IA - Increment after  - bit U = 1 and bit P = 0
1052  // IB - Increment before - bit U = 1 and bit P = 1
1053  // DA - Decrement after  - bit U = 0 and bit P = 0
1054  // DB - Decrement before - bit U = 0 and bit P = 1
1055  switch (Mode) {
1056  default: llvm_unreachable("Unknown addressing sub-mode!");
1057  case ARM_AM::da:                                     break;
1058  case ARM_AM::db: Binary |= 0x1 << ARMII::P_BitShift; break;
1059  case ARM_AM::ia: Binary |= 0x1 << ARMII::U_BitShift; break;
1060  case ARM_AM::ib: Binary |= 0x3 << ARMII::U_BitShift; break;
1061  }
1062
1063  return Binary;
1064}
1065
1066void ARMCodeEmitter::emitLoadStoreMultipleInstruction(const MachineInstr &MI) {
1067  const TargetInstrDesc &TID = MI.getDesc();
1068  bool IsUpdating = (TID.TSFlags & ARMII::IndexModeMask) != 0;
1069
1070  // Part of binary is determined by TableGn.
1071  unsigned Binary = getBinaryCodeForInstr(MI);
1072
1073  // Set the conditional execution predicate
1074  Binary |= II->getPredicate(&MI) << ARMII::CondShift;
1075
1076  // Skip operand 0 of an instruction with base register update.
1077  unsigned OpIdx = 0;
1078  if (IsUpdating)
1079    ++OpIdx;
1080
1081  // Set base address operand
1082  Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRnShift;
1083
1084  // Set addressing mode by modifying bits U(23) and P(24)
1085  const MachineOperand &MO = MI.getOperand(OpIdx++);
1086  Binary |= getAddrModeUPBits(ARM_AM::getAM4SubMode(MO.getImm()));
1087
1088  // Set bit W(21)
1089  if (IsUpdating)
1090    Binary |= 0x1 << ARMII::W_BitShift;
1091
1092  // Set registers
1093  for (unsigned i = OpIdx+2, e = MI.getNumOperands(); i != e; ++i) {
1094    const MachineOperand &MO = MI.getOperand(i);
1095    if (!MO.isReg() || MO.isImplicit())
1096      break;
1097    unsigned RegNum = ARMRegisterInfo::getRegisterNumbering(MO.getReg());
1098    assert(TargetRegisterInfo::isPhysicalRegister(MO.getReg()) &&
1099           RegNum < 16);
1100    Binary |= 0x1 << RegNum;
1101  }
1102
1103  emitWordLE(Binary);
1104}
1105
1106void ARMCodeEmitter::emitMulFrmInstruction(const MachineInstr &MI) {
1107  const TargetInstrDesc &TID = MI.getDesc();
1108
1109  // Part of binary is determined by TableGn.
1110  unsigned Binary = getBinaryCodeForInstr(MI);
1111
1112  // Set the conditional execution predicate
1113  Binary |= II->getPredicate(&MI) << ARMII::CondShift;
1114
1115  // Encode S bit if MI modifies CPSR.
1116  Binary |= getAddrModeSBit(MI, TID);
1117
1118  // 32x32->64bit operations have two destination registers. The number
1119  // of register definitions will tell us if that's what we're dealing with.
1120  unsigned OpIdx = 0;
1121  if (TID.getNumDefs() == 2)
1122    Binary |= getMachineOpValue (MI, OpIdx++) << ARMII::RegRdLoShift;
1123
1124  // Encode Rd
1125  Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRdHiShift;
1126
1127  // Encode Rm
1128  Binary |= getMachineOpValue(MI, OpIdx++);
1129
1130  // Encode Rs
1131  Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRsShift;
1132
1133  // Many multiple instructions (e.g. MLA) have three src operands. Encode
1134  // it as Rn (for multiply, that's in the same offset as RdLo.
1135  if (TID.getNumOperands() > OpIdx &&
1136      !TID.OpInfo[OpIdx].isPredicate() &&
1137      !TID.OpInfo[OpIdx].isOptionalDef())
1138    Binary |= getMachineOpValue(MI, OpIdx) << ARMII::RegRdLoShift;
1139
1140  emitWordLE(Binary);
1141}
1142
1143void ARMCodeEmitter::emitExtendInstruction(const MachineInstr &MI) {
1144  const TargetInstrDesc &TID = MI.getDesc();
1145
1146  // Part of binary is determined by TableGn.
1147  unsigned Binary = getBinaryCodeForInstr(MI);
1148
1149  // Set the conditional execution predicate
1150  Binary |= II->getPredicate(&MI) << ARMII::CondShift;
1151
1152  unsigned OpIdx = 0;
1153
1154  // Encode Rd
1155  Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRdShift;
1156
1157  const MachineOperand &MO1 = MI.getOperand(OpIdx++);
1158  const MachineOperand &MO2 = MI.getOperand(OpIdx);
1159  if (MO2.isReg()) {
1160    // Two register operand form.
1161    // Encode Rn.
1162    Binary |= getMachineOpValue(MI, MO1) << ARMII::RegRnShift;
1163
1164    // Encode Rm.
1165    Binary |= getMachineOpValue(MI, MO2);
1166    ++OpIdx;
1167  } else {
1168    Binary |= getMachineOpValue(MI, MO1);
1169  }
1170
1171  // Encode rot imm (0, 8, 16, or 24) if it has a rotate immediate operand.
1172  if (MI.getOperand(OpIdx).isImm() &&
1173      !TID.OpInfo[OpIdx].isPredicate() &&
1174      !TID.OpInfo[OpIdx].isOptionalDef())
1175    Binary |= (getMachineOpValue(MI, OpIdx) / 8) << ARMII::ExtRotImmShift;
1176
1177  emitWordLE(Binary);
1178}
1179
1180void ARMCodeEmitter::emitMiscArithInstruction(const MachineInstr &MI) {
1181  const TargetInstrDesc &TID = MI.getDesc();
1182
1183  // Part of binary is determined by TableGn.
1184  unsigned Binary = getBinaryCodeForInstr(MI);
1185
1186  // Set the conditional execution predicate
1187  Binary |= II->getPredicate(&MI) << ARMII::CondShift;
1188
1189  unsigned OpIdx = 0;
1190
1191  // Encode Rd
1192  Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRdShift;
1193
1194  const MachineOperand &MO = MI.getOperand(OpIdx++);
1195  if (OpIdx == TID.getNumOperands() ||
1196      TID.OpInfo[OpIdx].isPredicate() ||
1197      TID.OpInfo[OpIdx].isOptionalDef()) {
1198    // Encode Rm and it's done.
1199    Binary |= getMachineOpValue(MI, MO);
1200    emitWordLE(Binary);
1201    return;
1202  }
1203
1204  // Encode Rn.
1205  Binary |= getMachineOpValue(MI, MO) << ARMII::RegRnShift;
1206
1207  // Encode Rm.
1208  Binary |= getMachineOpValue(MI, OpIdx++);
1209
1210  // Encode shift_imm.
1211  unsigned ShiftAmt = MI.getOperand(OpIdx).getImm();
1212  assert(ShiftAmt < 32 && "shift_imm range is 0 to 31!");
1213  Binary |= ShiftAmt << ARMII::ShiftShift;
1214
1215  emitWordLE(Binary);
1216}
1217
1218void ARMCodeEmitter::emitBranchInstruction(const MachineInstr &MI) {
1219  const TargetInstrDesc &TID = MI.getDesc();
1220
1221  if (TID.Opcode == ARM::TPsoft) {
1222    llvm_unreachable("ARM::TPsoft FIXME"); // FIXME
1223  }
1224
1225  // Part of binary is determined by TableGn.
1226  unsigned Binary = getBinaryCodeForInstr(MI);
1227
1228  // Set the conditional execution predicate
1229  Binary |= II->getPredicate(&MI) << ARMII::CondShift;
1230
1231  // Set signed_immed_24 field
1232  Binary |= getMachineOpValue(MI, 0);
1233
1234  emitWordLE(Binary);
1235}
1236
1237void ARMCodeEmitter::emitInlineJumpTable(unsigned JTIndex) {
1238  // Remember the base address of the inline jump table.
1239  uintptr_t JTBase = MCE.getCurrentPCValue();
1240  JTI->addJumpTableBaseAddr(JTIndex, JTBase);
1241  DEBUG(errs() << "  ** Jump Table #" << JTIndex << " @ " << (void*)JTBase
1242               << '\n');
1243
1244  // Now emit the jump table entries.
1245  const std::vector<MachineBasicBlock*> &MBBs = (*MJTEs)[JTIndex].MBBs;
1246  for (unsigned i = 0, e = MBBs.size(); i != e; ++i) {
1247    if (IsPIC)
1248      // DestBB address - JT base.
1249      emitMachineBasicBlock(MBBs[i], ARM::reloc_arm_pic_jt, JTBase);
1250    else
1251      // Absolute DestBB address.
1252      emitMachineBasicBlock(MBBs[i], ARM::reloc_arm_absolute);
1253    emitWordLE(0);
1254  }
1255}
1256
1257void ARMCodeEmitter::emitMiscBranchInstruction(const MachineInstr &MI) {
1258  const TargetInstrDesc &TID = MI.getDesc();
1259
1260  // Handle jump tables.
1261  if (TID.Opcode == ARM::BR_JTr || TID.Opcode == ARM::BR_JTadd) {
1262    // First emit a ldr pc, [] instruction.
1263    emitDataProcessingInstruction(MI, ARM::PC);
1264
1265    // Then emit the inline jump table.
1266    unsigned JTIndex =
1267      (TID.Opcode == ARM::BR_JTr)
1268      ? MI.getOperand(1).getIndex() : MI.getOperand(2).getIndex();
1269    emitInlineJumpTable(JTIndex);
1270    return;
1271  } else if (TID.Opcode == ARM::BR_JTm) {
1272    // First emit a ldr pc, [] instruction.
1273    emitLoadStoreInstruction(MI, ARM::PC);
1274
1275    // Then emit the inline jump table.
1276    emitInlineJumpTable(MI.getOperand(3).getIndex());
1277    return;
1278  }
1279
1280  // Part of binary is determined by TableGn.
1281  unsigned Binary = getBinaryCodeForInstr(MI);
1282
1283  // Set the conditional execution predicate
1284  Binary |= II->getPredicate(&MI) << ARMII::CondShift;
1285
1286  if (TID.Opcode == ARM::BX_RET || TID.Opcode == ARM::MOVPCLR)
1287    // The return register is LR.
1288    Binary |= ARMRegisterInfo::getRegisterNumbering(ARM::LR);
1289  else
1290    // otherwise, set the return register
1291    Binary |= getMachineOpValue(MI, 0);
1292
1293  emitWordLE(Binary);
1294}
1295
1296static unsigned encodeVFPRd(const MachineInstr &MI, unsigned OpIdx) {
1297  unsigned RegD = MI.getOperand(OpIdx).getReg();
1298  unsigned Binary = 0;
1299  bool isSPVFP = false;
1300  RegD = ARMRegisterInfo::getRegisterNumbering(RegD, &isSPVFP);
1301  if (!isSPVFP)
1302    Binary |=   RegD               << ARMII::RegRdShift;
1303  else {
1304    Binary |= ((RegD & 0x1E) >> 1) << ARMII::RegRdShift;
1305    Binary |=  (RegD & 0x01)       << ARMII::D_BitShift;
1306  }
1307  return Binary;
1308}
1309
1310static unsigned encodeVFPRn(const MachineInstr &MI, unsigned OpIdx) {
1311  unsigned RegN = MI.getOperand(OpIdx).getReg();
1312  unsigned Binary = 0;
1313  bool isSPVFP = false;
1314  RegN = ARMRegisterInfo::getRegisterNumbering(RegN, &isSPVFP);
1315  if (!isSPVFP)
1316    Binary |=   RegN               << ARMII::RegRnShift;
1317  else {
1318    Binary |= ((RegN & 0x1E) >> 1) << ARMII::RegRnShift;
1319    Binary |=  (RegN & 0x01)       << ARMII::N_BitShift;
1320  }
1321  return Binary;
1322}
1323
1324static unsigned encodeVFPRm(const MachineInstr &MI, unsigned OpIdx) {
1325  unsigned RegM = MI.getOperand(OpIdx).getReg();
1326  unsigned Binary = 0;
1327  bool isSPVFP = false;
1328  RegM = ARMRegisterInfo::getRegisterNumbering(RegM, &isSPVFP);
1329  if (!isSPVFP)
1330    Binary |=   RegM;
1331  else {
1332    Binary |= ((RegM & 0x1E) >> 1);
1333    Binary |=  (RegM & 0x01)       << ARMII::M_BitShift;
1334  }
1335  return Binary;
1336}
1337
1338void ARMCodeEmitter::emitVFPArithInstruction(const MachineInstr &MI) {
1339  const TargetInstrDesc &TID = MI.getDesc();
1340
1341  // Part of binary is determined by TableGn.
1342  unsigned Binary = getBinaryCodeForInstr(MI);
1343
1344  // Set the conditional execution predicate
1345  Binary |= II->getPredicate(&MI) << ARMII::CondShift;
1346
1347  unsigned OpIdx = 0;
1348  assert((Binary & ARMII::D_BitShift) == 0 &&
1349         (Binary & ARMII::N_BitShift) == 0 &&
1350         (Binary & ARMII::M_BitShift) == 0 && "VFP encoding bug!");
1351
1352  // Encode Dd / Sd.
1353  Binary |= encodeVFPRd(MI, OpIdx++);
1354
1355  // If this is a two-address operand, skip it, e.g. FMACD.
1356  if (TID.getOperandConstraint(OpIdx, TOI::TIED_TO) != -1)
1357    ++OpIdx;
1358
1359  // Encode Dn / Sn.
1360  if ((TID.TSFlags & ARMII::FormMask) == ARMII::VFPBinaryFrm)
1361    Binary |= encodeVFPRn(MI, OpIdx++);
1362
1363  if (OpIdx == TID.getNumOperands() ||
1364      TID.OpInfo[OpIdx].isPredicate() ||
1365      TID.OpInfo[OpIdx].isOptionalDef()) {
1366    // FCMPEZD etc. has only one operand.
1367    emitWordLE(Binary);
1368    return;
1369  }
1370
1371  // Encode Dm / Sm.
1372  Binary |= encodeVFPRm(MI, OpIdx);
1373
1374  emitWordLE(Binary);
1375}
1376
1377void ARMCodeEmitter::emitVFPConversionInstruction(const MachineInstr &MI) {
1378  const TargetInstrDesc &TID = MI.getDesc();
1379  unsigned Form = TID.TSFlags & ARMII::FormMask;
1380
1381  // Part of binary is determined by TableGn.
1382  unsigned Binary = getBinaryCodeForInstr(MI);
1383
1384  // Set the conditional execution predicate
1385  Binary |= II->getPredicate(&MI) << ARMII::CondShift;
1386
1387  switch (Form) {
1388  default: break;
1389  case ARMII::VFPConv1Frm:
1390  case ARMII::VFPConv2Frm:
1391  case ARMII::VFPConv3Frm:
1392    // Encode Dd / Sd.
1393    Binary |= encodeVFPRd(MI, 0);
1394    break;
1395  case ARMII::VFPConv4Frm:
1396    // Encode Dn / Sn.
1397    Binary |= encodeVFPRn(MI, 0);
1398    break;
1399  case ARMII::VFPConv5Frm:
1400    // Encode Dm / Sm.
1401    Binary |= encodeVFPRm(MI, 0);
1402    break;
1403  }
1404
1405  switch (Form) {
1406  default: break;
1407  case ARMII::VFPConv1Frm:
1408    // Encode Dm / Sm.
1409    Binary |= encodeVFPRm(MI, 1);
1410    break;
1411  case ARMII::VFPConv2Frm:
1412  case ARMII::VFPConv3Frm:
1413    // Encode Dn / Sn.
1414    Binary |= encodeVFPRn(MI, 1);
1415    break;
1416  case ARMII::VFPConv4Frm:
1417  case ARMII::VFPConv5Frm:
1418    // Encode Dd / Sd.
1419    Binary |= encodeVFPRd(MI, 1);
1420    break;
1421  }
1422
1423  if (Form == ARMII::VFPConv5Frm)
1424    // Encode Dn / Sn.
1425    Binary |= encodeVFPRn(MI, 2);
1426  else if (Form == ARMII::VFPConv3Frm)
1427    // Encode Dm / Sm.
1428    Binary |= encodeVFPRm(MI, 2);
1429
1430  emitWordLE(Binary);
1431}
1432
1433void ARMCodeEmitter::emitVFPLoadStoreInstruction(const MachineInstr &MI) {
1434  // Part of binary is determined by TableGn.
1435  unsigned Binary = getBinaryCodeForInstr(MI);
1436
1437  // Set the conditional execution predicate
1438  Binary |= II->getPredicate(&MI) << ARMII::CondShift;
1439
1440  unsigned OpIdx = 0;
1441
1442  // Encode Dd / Sd.
1443  Binary |= encodeVFPRd(MI, OpIdx++);
1444
1445  // Encode address base.
1446  const MachineOperand &Base = MI.getOperand(OpIdx++);
1447  Binary |= getMachineOpValue(MI, Base) << ARMII::RegRnShift;
1448
1449  // If there is a non-zero immediate offset, encode it.
1450  if (Base.isReg()) {
1451    const MachineOperand &Offset = MI.getOperand(OpIdx);
1452    if (unsigned ImmOffs = ARM_AM::getAM5Offset(Offset.getImm())) {
1453      if (ARM_AM::getAM5Op(Offset.getImm()) == ARM_AM::add)
1454        Binary |= 1 << ARMII::U_BitShift;
1455      Binary |= ImmOffs;
1456      emitWordLE(Binary);
1457      return;
1458    }
1459  }
1460
1461  // If immediate offset is omitted, default to +0.
1462  Binary |= 1 << ARMII::U_BitShift;
1463
1464  emitWordLE(Binary);
1465}
1466
1467void
1468ARMCodeEmitter::emitVFPLoadStoreMultipleInstruction(const MachineInstr &MI) {
1469  const TargetInstrDesc &TID = MI.getDesc();
1470  bool IsUpdating = (TID.TSFlags & ARMII::IndexModeMask) != 0;
1471
1472  // Part of binary is determined by TableGn.
1473  unsigned Binary = getBinaryCodeForInstr(MI);
1474
1475  // Set the conditional execution predicate
1476  Binary |= II->getPredicate(&MI) << ARMII::CondShift;
1477
1478  // Skip operand 0 of an instruction with base register update.
1479  unsigned OpIdx = 0;
1480  if (IsUpdating)
1481    ++OpIdx;
1482
1483  // Set base address operand
1484  Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRnShift;
1485
1486  // Set addressing mode by modifying bits U(23) and P(24)
1487  const MachineOperand &MO = MI.getOperand(OpIdx++);
1488  Binary |= getAddrModeUPBits(ARM_AM::getAM5SubMode(MO.getImm()));
1489
1490  // Set bit W(21)
1491  if (IsUpdating)
1492    Binary |= 0x1 << ARMII::W_BitShift;
1493
1494  // First register is encoded in Dd.
1495  Binary |= encodeVFPRd(MI, OpIdx+2);
1496
1497  // Number of registers are encoded in offset field.
1498  unsigned NumRegs = 1;
1499  for (unsigned i = OpIdx+3, e = MI.getNumOperands(); i != e; ++i) {
1500    const MachineOperand &MO = MI.getOperand(i);
1501    if (!MO.isReg() || MO.isImplicit())
1502      break;
1503    ++NumRegs;
1504  }
1505  // Bit 8 will be set if <list> is consecutive 64-bit registers (e.g., D0)
1506  // Otherwise, it will be 0, in the case of 32-bit registers.
1507  if(Binary & 0x100)
1508    Binary |= NumRegs * 2;
1509  else
1510    Binary |= NumRegs;
1511
1512  emitWordLE(Binary);
1513}
1514
1515void ARMCodeEmitter::emitMiscInstruction(const MachineInstr &MI) {
1516  unsigned Opcode = MI.getDesc().Opcode;
1517  // Part of binary is determined by TableGn.
1518  unsigned Binary = getBinaryCodeForInstr(MI);
1519
1520  // Set the conditional execution predicate
1521  Binary |= II->getPredicate(&MI) << ARMII::CondShift;
1522
1523  switch(Opcode) {
1524  default:
1525    llvm_unreachable("ARMCodeEmitter::emitMiscInstruction");
1526
1527  case ARM::FMSTAT:
1528    // No further encoding needed.
1529    break;
1530
1531  case ARM::VMRS:
1532  case ARM::VMSR: {
1533    const MachineOperand &MO0 = MI.getOperand(0);
1534    // Encode Rt.
1535    Binary |= ARMRegisterInfo::getRegisterNumbering(MO0.getReg())
1536                << ARMII::RegRdShift;
1537    break;
1538  }
1539
1540  case ARM::FCONSTD:
1541  case ARM::FCONSTS: {
1542    // Encode Dd / Sd.
1543    Binary |= encodeVFPRd(MI, 0);
1544
1545    // Encode imm., Table A7-18 VFP modified immediate constants
1546    const MachineOperand &MO1 = MI.getOperand(1);
1547    unsigned Imm = static_cast<unsigned>(MO1.getFPImm()->getValueAPF()
1548                      .bitcastToAPInt().getHiBits(32).getLimitedValue());
1549    unsigned ModifiedImm;
1550
1551    if(Opcode == ARM::FCONSTS)
1552      ModifiedImm = (Imm & 0x80000000) >> 24 | // a
1553                    (Imm & 0x03F80000) >> 19;  // bcdefgh
1554    else // Opcode == ARM::FCONSTD
1555      ModifiedImm = (Imm & 0x80000000) >> 24 | // a
1556                    (Imm & 0x007F0000) >> 16;  // bcdefgh
1557
1558    // Insts{19-16} = abcd, Insts{3-0} = efgh
1559    Binary |= ((ModifiedImm & 0xF0) >> 4) << 16;
1560    Binary |= (ModifiedImm & 0xF);
1561    break;
1562  }
1563  }
1564
1565  emitWordLE(Binary);
1566}
1567
1568static unsigned encodeNEONRd(const MachineInstr &MI, unsigned OpIdx) {
1569  unsigned RegD = MI.getOperand(OpIdx).getReg();
1570  unsigned Binary = 0;
1571  RegD = ARMRegisterInfo::getRegisterNumbering(RegD);
1572  Binary |= (RegD & 0xf) << ARMII::RegRdShift;
1573  Binary |= ((RegD >> 4) & 1) << ARMII::D_BitShift;
1574  return Binary;
1575}
1576
1577static unsigned encodeNEONRn(const MachineInstr &MI, unsigned OpIdx) {
1578  unsigned RegN = MI.getOperand(OpIdx).getReg();
1579  unsigned Binary = 0;
1580  RegN = ARMRegisterInfo::getRegisterNumbering(RegN);
1581  Binary |= (RegN & 0xf) << ARMII::RegRnShift;
1582  Binary |= ((RegN >> 4) & 1) << ARMII::N_BitShift;
1583  return Binary;
1584}
1585
1586static unsigned encodeNEONRm(const MachineInstr &MI, unsigned OpIdx) {
1587  unsigned RegM = MI.getOperand(OpIdx).getReg();
1588  unsigned Binary = 0;
1589  RegM = ARMRegisterInfo::getRegisterNumbering(RegM);
1590  Binary |= (RegM & 0xf);
1591  Binary |= ((RegM >> 4) & 1) << ARMII::M_BitShift;
1592  return Binary;
1593}
1594
1595/// convertNEONDataProcToThumb - Convert the ARM mode encoding for a NEON
1596/// data-processing instruction to the corresponding Thumb encoding.
1597static unsigned convertNEONDataProcToThumb(unsigned Binary) {
1598  assert((Binary & 0xfe000000) == 0xf2000000 &&
1599         "not an ARM NEON data-processing instruction");
1600  unsigned UBit = (Binary >> 24) & 1;
1601  return 0xef000000 | (UBit << 28) | (Binary & 0xffffff);
1602}
1603
1604void ARMCodeEmitter::emitNEONLaneInstruction(const MachineInstr &MI) {
1605  unsigned Binary = getBinaryCodeForInstr(MI);
1606
1607  unsigned RegTOpIdx, RegNOpIdx, LnOpIdx;
1608  const TargetInstrDesc &TID = MI.getDesc();
1609  if ((TID.TSFlags & ARMII::FormMask) == ARMII::NGetLnFrm) {
1610    RegTOpIdx = 0;
1611    RegNOpIdx = 1;
1612    LnOpIdx = 2;
1613  } else { // ARMII::NSetLnFrm
1614    RegTOpIdx = 2;
1615    RegNOpIdx = 0;
1616    LnOpIdx = 3;
1617  }
1618
1619  // Set the conditional execution predicate
1620  Binary |= (IsThumb ? ARMCC::AL : II->getPredicate(&MI)) << ARMII::CondShift;
1621
1622  unsigned RegT = MI.getOperand(RegTOpIdx).getReg();
1623  RegT = ARMRegisterInfo::getRegisterNumbering(RegT);
1624  Binary |= (RegT << ARMII::RegRdShift);
1625  Binary |= encodeNEONRn(MI, RegNOpIdx);
1626
1627  unsigned LaneShift;
1628  if ((Binary & (1 << 22)) != 0)
1629    LaneShift = 0; // 8-bit elements
1630  else if ((Binary & (1 << 5)) != 0)
1631    LaneShift = 1; // 16-bit elements
1632  else
1633    LaneShift = 2; // 32-bit elements
1634
1635  unsigned Lane = MI.getOperand(LnOpIdx).getImm() << LaneShift;
1636  unsigned Opc1 = Lane >> 2;
1637  unsigned Opc2 = Lane & 3;
1638  assert((Opc1 & 3) == 0 && "out-of-range lane number operand");
1639  Binary |= (Opc1 << 21);
1640  Binary |= (Opc2 << 5);
1641
1642  emitWordLE(Binary);
1643}
1644
1645void ARMCodeEmitter::emitNEONDupInstruction(const MachineInstr &MI) {
1646  unsigned Binary = getBinaryCodeForInstr(MI);
1647
1648  // Set the conditional execution predicate
1649  Binary |= (IsThumb ? ARMCC::AL : II->getPredicate(&MI)) << ARMII::CondShift;
1650
1651  unsigned RegT = MI.getOperand(1).getReg();
1652  RegT = ARMRegisterInfo::getRegisterNumbering(RegT);
1653  Binary |= (RegT << ARMII::RegRdShift);
1654  Binary |= encodeNEONRn(MI, 0);
1655  emitWordLE(Binary);
1656}
1657
1658void ARMCodeEmitter::emitNEON1RegModImmInstruction(const MachineInstr &MI) {
1659  unsigned Binary = getBinaryCodeForInstr(MI);
1660  // Destination register is encoded in Dd.
1661  Binary |= encodeNEONRd(MI, 0);
1662  // Immediate fields: Op, Cmode, I, Imm3, Imm4
1663  unsigned Imm = MI.getOperand(1).getImm();
1664  unsigned Op = (Imm >> 12) & 1;
1665  unsigned Cmode = (Imm >> 8) & 0xf;
1666  unsigned I = (Imm >> 7) & 1;
1667  unsigned Imm3 = (Imm >> 4) & 0x7;
1668  unsigned Imm4 = Imm & 0xf;
1669  Binary |= (I << 24) | (Imm3 << 16) | (Cmode << 8) | (Op << 5) | Imm4;
1670  if (IsThumb)
1671    Binary = convertNEONDataProcToThumb(Binary);
1672  emitWordLE(Binary);
1673}
1674
1675void ARMCodeEmitter::emitNEON2RegInstruction(const MachineInstr &MI) {
1676  const TargetInstrDesc &TID = MI.getDesc();
1677  unsigned Binary = getBinaryCodeForInstr(MI);
1678  // Destination register is encoded in Dd; source register in Dm.
1679  unsigned OpIdx = 0;
1680  Binary |= encodeNEONRd(MI, OpIdx++);
1681  if (TID.getOperandConstraint(OpIdx, TOI::TIED_TO) != -1)
1682    ++OpIdx;
1683  Binary |= encodeNEONRm(MI, OpIdx);
1684  if (IsThumb)
1685    Binary = convertNEONDataProcToThumb(Binary);
1686  // FIXME: This does not handle VDUPfdf or VDUPfqf.
1687  emitWordLE(Binary);
1688}
1689
1690void ARMCodeEmitter::emitNEON3RegInstruction(const MachineInstr &MI) {
1691  const TargetInstrDesc &TID = MI.getDesc();
1692  unsigned Binary = getBinaryCodeForInstr(MI);
1693  // Destination register is encoded in Dd; source registers in Dn and Dm.
1694  unsigned OpIdx = 0;
1695  Binary |= encodeNEONRd(MI, OpIdx++);
1696  if (TID.getOperandConstraint(OpIdx, TOI::TIED_TO) != -1)
1697    ++OpIdx;
1698  Binary |= encodeNEONRn(MI, OpIdx++);
1699  if (TID.getOperandConstraint(OpIdx, TOI::TIED_TO) != -1)
1700    ++OpIdx;
1701  Binary |= encodeNEONRm(MI, OpIdx);
1702  if (IsThumb)
1703    Binary = convertNEONDataProcToThumb(Binary);
1704  // FIXME: This does not handle VMOVDneon or VMOVQ.
1705  emitWordLE(Binary);
1706}
1707
1708#include "ARMGenCodeEmitter.inc"
1709