131d157ae1ac2cd9c787dc3c1d28e64c682803844Jia Liu//===-- ARMExpandPseudoInsts.cpp - Expand pseudo instructions -------------===// 2b9803a8fa65f043c96612fa9c5aeeee12739db2bEvan Cheng// 3b9803a8fa65f043c96612fa9c5aeeee12739db2bEvan Cheng// The LLVM Compiler Infrastructure 4b9803a8fa65f043c96612fa9c5aeeee12739db2bEvan Cheng// 5b9803a8fa65f043c96612fa9c5aeeee12739db2bEvan Cheng// This file is distributed under the University of Illinois Open Source 6b9803a8fa65f043c96612fa9c5aeeee12739db2bEvan Cheng// License. See LICENSE.TXT for details. 7b9803a8fa65f043c96612fa9c5aeeee12739db2bEvan Cheng// 8b9803a8fa65f043c96612fa9c5aeeee12739db2bEvan Cheng//===----------------------------------------------------------------------===// 9b9803a8fa65f043c96612fa9c5aeeee12739db2bEvan Cheng// 10656edcf138563068a2e7d52fb35f8de1375bad9aBob Wilson// This file contains a pass that expands pseudo instructions into target 11b9803a8fa65f043c96612fa9c5aeeee12739db2bEvan Cheng// instructions to allow proper scheduling, if-conversion, and other late 12b9803a8fa65f043c96612fa9c5aeeee12739db2bEvan Cheng// optimizations. This pass should be run after register allocation but before 13656edcf138563068a2e7d52fb35f8de1375bad9aBob Wilson// the post-regalloc scheduling pass. 14b9803a8fa65f043c96612fa9c5aeeee12739db2bEvan Cheng// 15b9803a8fa65f043c96612fa9c5aeeee12739db2bEvan Cheng//===----------------------------------------------------------------------===// 16b9803a8fa65f043c96612fa9c5aeeee12739db2bEvan Cheng 17b9803a8fa65f043c96612fa9c5aeeee12739db2bEvan Cheng#include "ARM.h" 18b9803a8fa65f043c96612fa9c5aeeee12739db2bEvan Cheng#include "ARMBaseInstrInfo.h" 19e4ad387a5a88dae20f0f7578e55170bbc8eee2a9Jim Grosbach#include "ARMBaseRegisterInfo.h" 2036b56886974eae4f9c5ebc96befd3e7bfe5de338Stephen Hines#include "ARMConstantPoolValue.h" 21e4ad387a5a88dae20f0f7578e55170bbc8eee2a9Jim Grosbach#include "ARMMachineFunctionInfo.h" 22ee04a6d3a40c3017124e3fd89a0db473a2824498Evan Cheng#include "MCTargetDesc/ARMAddressingModes.h" 23e4ad387a5a88dae20f0f7578e55170bbc8eee2a9Jim Grosbach#include "llvm/CodeGen/MachineFrameInfo.h" 24b9803a8fa65f043c96612fa9c5aeeee12739db2bEvan Cheng#include "llvm/CodeGen/MachineFunctionPass.h" 25dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines#include "llvm/CodeGen/MachineInstrBundle.h" 26b9803a8fa65f043c96612fa9c5aeeee12739db2bEvan Cheng#include "llvm/CodeGen/MachineInstrBuilder.h" 2736b56886974eae4f9c5ebc96befd3e7bfe5de338Stephen Hines#include "llvm/IR/GlobalValue.h" 28e69438fb87623dd6fdeeb99b647a46e877eb6183Jakob Stoklund Olesen#include "llvm/Support/CommandLine.h" 29e4ad387a5a88dae20f0f7578e55170bbc8eee2a9Jim Grosbach#include "llvm/Support/raw_ostream.h" // FIXME: for debug only. remove! 30d04a8d4b33ff316ca4cf961e06c9e312eff8e64fChandler Carruth#include "llvm/Target/TargetFrameLowering.h" 31d04a8d4b33ff316ca4cf961e06c9e312eff8e64fChandler Carruth#include "llvm/Target/TargetRegisterInfo.h" 32b9803a8fa65f043c96612fa9c5aeeee12739db2bEvan Chengusing namespace llvm; 33b9803a8fa65f043c96612fa9c5aeeee12739db2bEvan Cheng 34dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines#define DEBUG_TYPE "arm-pseudo" 35dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines 36a67f14bf53737f9bb0afefa28e08c4aac6ec4804Benjamin Kramerstatic cl::opt<bool> 37e69438fb87623dd6fdeeb99b647a46e877eb6183Jakob Stoklund OlesenVerifyARMPseudo("verify-arm-pseudo-expand", cl::Hidden, 38e69438fb87623dd6fdeeb99b647a46e877eb6183Jakob Stoklund Olesen cl::desc("Verify machine code after expanding ARM pseudos")); 39e69438fb87623dd6fdeeb99b647a46e877eb6183Jakob Stoklund Olesen 40b9803a8fa65f043c96612fa9c5aeeee12739db2bEvan Chengnamespace { 41b9803a8fa65f043c96612fa9c5aeeee12739db2bEvan Cheng class ARMExpandPseudo : public MachineFunctionPass { 42b9803a8fa65f043c96612fa9c5aeeee12739db2bEvan Cheng public: 43b9803a8fa65f043c96612fa9c5aeeee12739db2bEvan Cheng static char ID; 4490c579de5a383cee278acc3f7e7b9d0a656e6a35Owen Anderson ARMExpandPseudo() : MachineFunctionPass(ID) {} 45b9803a8fa65f043c96612fa9c5aeeee12739db2bEvan Cheng 46e4ad387a5a88dae20f0f7578e55170bbc8eee2a9Jim Grosbach const ARMBaseInstrInfo *TII; 47d929f7773812535271ae6969331f8164c1f7f3b2Evan Cheng const TargetRegisterInfo *TRI; 48893d7fe2098cc81ba1b4ce0ed71f6f614843961fEvan Cheng const ARMSubtarget *STI; 499fe2009956fc40f3aea46fb3c38dcfb61c4aca46Evan Cheng ARMFunctionInfo *AFI; 50b9803a8fa65f043c96612fa9c5aeeee12739db2bEvan Cheng 5136b56886974eae4f9c5ebc96befd3e7bfe5de338Stephen Hines bool runOnMachineFunction(MachineFunction &Fn) override; 52b9803a8fa65f043c96612fa9c5aeeee12739db2bEvan Cheng 5336b56886974eae4f9c5ebc96befd3e7bfe5de338Stephen Hines const char *getPassName() const override { 54b9803a8fa65f043c96612fa9c5aeeee12739db2bEvan Cheng return "ARM pseudo instruction expansion pass"; 55b9803a8fa65f043c96612fa9c5aeeee12739db2bEvan Cheng } 56b9803a8fa65f043c96612fa9c5aeeee12739db2bEvan Cheng 57b9803a8fa65f043c96612fa9c5aeeee12739db2bEvan Cheng private: 58431300797b84600fc9b4eb8ca283277d3e0674ebEvan Cheng void TransferImpOps(MachineInstr &OldMI, 59431300797b84600fc9b4eb8ca283277d3e0674ebEvan Cheng MachineInstrBuilder &UseMI, MachineInstrBuilder &DefMI); 609fe2009956fc40f3aea46fb3c38dcfb61c4aca46Evan Cheng bool ExpandMI(MachineBasicBlock &MBB, 619fe2009956fc40f3aea46fb3c38dcfb61c4aca46Evan Cheng MachineBasicBlock::iterator MBBI); 62b9803a8fa65f043c96612fa9c5aeeee12739db2bEvan Cheng bool ExpandMBB(MachineBasicBlock &MBB); 638466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson void ExpandVLD(MachineBasicBlock::iterator &MBBI); 648466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson void ExpandVST(MachineBasicBlock::iterator &MBBI); 658466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson void ExpandLaneOp(MachineBasicBlock::iterator &MBBI); 66bd916c54b7989ddbab373c61eb1ed2556ca44d27Bob Wilson void ExpandVTBL(MachineBasicBlock::iterator &MBBI, 6760d99a5278e4a0e7116a05c01cececb07ca1362aJim Grosbach unsigned Opc, bool IsExt); 689fe2009956fc40f3aea46fb3c38dcfb61c4aca46Evan Cheng void ExpandMOV32BitImm(MachineBasicBlock &MBB, 699fe2009956fc40f3aea46fb3c38dcfb61c4aca46Evan Cheng MachineBasicBlock::iterator &MBBI); 70b9803a8fa65f043c96612fa9c5aeeee12739db2bEvan Cheng }; 71b9803a8fa65f043c96612fa9c5aeeee12739db2bEvan Cheng char ARMExpandPseudo::ID = 0; 72b9803a8fa65f043c96612fa9c5aeeee12739db2bEvan Cheng} 73b9803a8fa65f043c96612fa9c5aeeee12739db2bEvan Cheng 74431300797b84600fc9b4eb8ca283277d3e0674ebEvan Cheng/// TransferImpOps - Transfer implicit operands on the pseudo instruction to 75431300797b84600fc9b4eb8ca283277d3e0674ebEvan Cheng/// the instructions created from the expansion. 76431300797b84600fc9b4eb8ca283277d3e0674ebEvan Chengvoid ARMExpandPseudo::TransferImpOps(MachineInstr &OldMI, 77431300797b84600fc9b4eb8ca283277d3e0674ebEvan Cheng MachineInstrBuilder &UseMI, 78431300797b84600fc9b4eb8ca283277d3e0674ebEvan Cheng MachineInstrBuilder &DefMI) { 79e837dead3c8dc3445ef6a0e2322179c57e264a13Evan Cheng const MCInstrDesc &Desc = OldMI.getDesc(); 80431300797b84600fc9b4eb8ca283277d3e0674ebEvan Cheng for (unsigned i = Desc.getNumOperands(), e = OldMI.getNumOperands(); 81431300797b84600fc9b4eb8ca283277d3e0674ebEvan Cheng i != e; ++i) { 82431300797b84600fc9b4eb8ca283277d3e0674ebEvan Cheng const MachineOperand &MO = OldMI.getOperand(i); 83431300797b84600fc9b4eb8ca283277d3e0674ebEvan Cheng assert(MO.isReg() && MO.getReg()); 84431300797b84600fc9b4eb8ca283277d3e0674ebEvan Cheng if (MO.isUse()) 8563569c99ec944210d0edc687d7411b5c687e97a7Bob Wilson UseMI.addOperand(MO); 86431300797b84600fc9b4eb8ca283277d3e0674ebEvan Cheng else 8763569c99ec944210d0edc687d7411b5c687e97a7Bob Wilson DefMI.addOperand(MO); 88431300797b84600fc9b4eb8ca283277d3e0674ebEvan Cheng } 89431300797b84600fc9b4eb8ca283277d3e0674ebEvan Cheng} 90431300797b84600fc9b4eb8ca283277d3e0674ebEvan Cheng 918466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilsonnamespace { 928466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson // Constants for register spacing in NEON load/store instructions. 938466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson // For quad-register load-lane and store-lane pseudo instructors, the 948466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson // spacing is initially assumed to be EvenDblSpc, and that is changed to 958466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson // OddDblSpc depending on the lane number operand. 968466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson enum NEONRegSpacing { 978466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson SingleSpc, 988466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson EvenDblSpc, 998466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson OddDblSpc 1008466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson }; 1018466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson 1028466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson // Entries for NEON load/store information table. The table is sorted by 1038466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson // PseudoOpc for fast binary-search lookups. 1048466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson struct NEONLdStTableEntry { 105b78ca423844f19f4a838abb49b4b4fa7ae499707Craig Topper uint16_t PseudoOpc; 106b78ca423844f19f4a838abb49b4b4fa7ae499707Craig Topper uint16_t RealOpc; 1078466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson bool IsLoad; 108f9f5a765adf8465530fe1aced6455ca9438bb29aJim Grosbach bool isUpdating; 109f9f5a765adf8465530fe1aced6455ca9438bb29aJim Grosbach bool hasWritebackOperand; 110aa258442b9c9f764845660a8f3233c7887e7cf6fCraig Topper uint8_t RegSpacing; // One of type NEONRegSpacing 111aa258442b9c9f764845660a8f3233c7887e7cf6fCraig Topper uint8_t NumRegs; // D registers loaded or stored 112aa258442b9c9f764845660a8f3233c7887e7cf6fCraig Topper uint8_t RegElts; // elements per D register; used for lane ops 113280dfad48940a0a51726308dd3daa3b1b0d18705Jim Grosbach // FIXME: Temporary flag to denote whether the real instruction takes 114280dfad48940a0a51726308dd3daa3b1b0d18705Jim Grosbach // a single register (like the encoding) or all of the registers in 115280dfad48940a0a51726308dd3daa3b1b0d18705Jim Grosbach // the list (like the asm syntax and the isel DAG). When all definitions 116280dfad48940a0a51726308dd3daa3b1b0d18705Jim Grosbach // are converted to take only the single encoded register, this will 117280dfad48940a0a51726308dd3daa3b1b0d18705Jim Grosbach // go away. 118280dfad48940a0a51726308dd3daa3b1b0d18705Jim Grosbach bool copyAllListRegs; 1198466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson 1208466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson // Comparison methods for binary search of the table. 1218466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson bool operator<(const NEONLdStTableEntry &TE) const { 1228466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson return PseudoOpc < TE.PseudoOpc; 1238466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson } 1248466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson friend bool operator<(const NEONLdStTableEntry &TE, unsigned PseudoOpc) { 1258466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson return TE.PseudoOpc < PseudoOpc; 1268466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson } 127100c267249d1d03c4f96eede9877a4f9f54f2247Chandler Carruth friend bool LLVM_ATTRIBUTE_UNUSED operator<(unsigned PseudoOpc, 128100c267249d1d03c4f96eede9877a4f9f54f2247Chandler Carruth const NEONLdStTableEntry &TE) { 1298466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson return PseudoOpc < TE.PseudoOpc; 1308466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson } 1318466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson }; 1328466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson} 1338466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson 1348466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilsonstatic const NEONLdStTableEntry NEONLdStTable[] = { 135f9f5a765adf8465530fe1aced6455ca9438bb29aJim Grosbach{ ARM::VLD1LNq16Pseudo, ARM::VLD1LNd16, true, false, false, EvenDblSpc, 1, 4 ,true}, 136f9f5a765adf8465530fe1aced6455ca9438bb29aJim Grosbach{ ARM::VLD1LNq16Pseudo_UPD, ARM::VLD1LNd16_UPD, true, true, true, EvenDblSpc, 1, 4 ,true}, 137f9f5a765adf8465530fe1aced6455ca9438bb29aJim Grosbach{ ARM::VLD1LNq32Pseudo, ARM::VLD1LNd32, true, false, false, EvenDblSpc, 1, 2 ,true}, 138f9f5a765adf8465530fe1aced6455ca9438bb29aJim Grosbach{ ARM::VLD1LNq32Pseudo_UPD, ARM::VLD1LNd32_UPD, true, true, true, EvenDblSpc, 1, 2 ,true}, 139f9f5a765adf8465530fe1aced6455ca9438bb29aJim Grosbach{ ARM::VLD1LNq8Pseudo, ARM::VLD1LNd8, true, false, false, EvenDblSpc, 1, 8 ,true}, 140f9f5a765adf8465530fe1aced6455ca9438bb29aJim Grosbach{ ARM::VLD1LNq8Pseudo_UPD, ARM::VLD1LNd8_UPD, true, true, true, EvenDblSpc, 1, 8 ,true}, 141f9f5a765adf8465530fe1aced6455ca9438bb29aJim Grosbach 142f9f5a765adf8465530fe1aced6455ca9438bb29aJim Grosbach{ ARM::VLD1d64QPseudo, ARM::VLD1d64Q, true, false, false, SingleSpc, 4, 1 ,false}, 14336b56886974eae4f9c5ebc96befd3e7bfe5de338Stephen Hines{ ARM::VLD1d64QPseudoWB_fixed, ARM::VLD1d64Qwb_fixed, true, true, false, SingleSpc, 4, 1 ,false}, 144f9f5a765adf8465530fe1aced6455ca9438bb29aJim Grosbach{ ARM::VLD1d64TPseudo, ARM::VLD1d64T, true, false, false, SingleSpc, 3, 1 ,false}, 14536b56886974eae4f9c5ebc96befd3e7bfe5de338Stephen Hines{ ARM::VLD1d64TPseudoWB_fixed, ARM::VLD1d64Twb_fixed, true, true, false, SingleSpc, 3, 1 ,false}, 146f9f5a765adf8465530fe1aced6455ca9438bb29aJim Grosbach 147f9f5a765adf8465530fe1aced6455ca9438bb29aJim Grosbach{ ARM::VLD2LNd16Pseudo, ARM::VLD2LNd16, true, false, false, SingleSpc, 2, 4 ,true}, 148f9f5a765adf8465530fe1aced6455ca9438bb29aJim Grosbach{ ARM::VLD2LNd16Pseudo_UPD, ARM::VLD2LNd16_UPD, true, true, true, SingleSpc, 2, 4 ,true}, 149f9f5a765adf8465530fe1aced6455ca9438bb29aJim Grosbach{ ARM::VLD2LNd32Pseudo, ARM::VLD2LNd32, true, false, false, SingleSpc, 2, 2 ,true}, 150f9f5a765adf8465530fe1aced6455ca9438bb29aJim Grosbach{ ARM::VLD2LNd32Pseudo_UPD, ARM::VLD2LNd32_UPD, true, true, true, SingleSpc, 2, 2 ,true}, 151f9f5a765adf8465530fe1aced6455ca9438bb29aJim Grosbach{ ARM::VLD2LNd8Pseudo, ARM::VLD2LNd8, true, false, false, SingleSpc, 2, 8 ,true}, 152f9f5a765adf8465530fe1aced6455ca9438bb29aJim Grosbach{ ARM::VLD2LNd8Pseudo_UPD, ARM::VLD2LNd8_UPD, true, true, true, SingleSpc, 2, 8 ,true}, 153f9f5a765adf8465530fe1aced6455ca9438bb29aJim Grosbach{ ARM::VLD2LNq16Pseudo, ARM::VLD2LNq16, true, false, false, EvenDblSpc, 2, 4 ,true}, 154f9f5a765adf8465530fe1aced6455ca9438bb29aJim Grosbach{ ARM::VLD2LNq16Pseudo_UPD, ARM::VLD2LNq16_UPD, true, true, true, EvenDblSpc, 2, 4 ,true}, 155f9f5a765adf8465530fe1aced6455ca9438bb29aJim Grosbach{ ARM::VLD2LNq32Pseudo, ARM::VLD2LNq32, true, false, false, EvenDblSpc, 2, 2 ,true}, 156f9f5a765adf8465530fe1aced6455ca9438bb29aJim Grosbach{ ARM::VLD2LNq32Pseudo_UPD, ARM::VLD2LNq32_UPD, true, true, true, EvenDblSpc, 2, 2 ,true}, 157f9f5a765adf8465530fe1aced6455ca9438bb29aJim Grosbach 158f9f5a765adf8465530fe1aced6455ca9438bb29aJim Grosbach{ ARM::VLD2q16Pseudo, ARM::VLD2q16, true, false, false, SingleSpc, 4, 4 ,false}, 159a4e3c7fc4ba2d55695b0484480685698132eba20Jim Grosbach{ ARM::VLD2q16PseudoWB_fixed, ARM::VLD2q16wb_fixed, true, true, false, SingleSpc, 4, 4 ,false}, 160a4e3c7fc4ba2d55695b0484480685698132eba20Jim Grosbach{ ARM::VLD2q16PseudoWB_register, ARM::VLD2q16wb_register, true, true, true, SingleSpc, 4, 4 ,false}, 161f9f5a765adf8465530fe1aced6455ca9438bb29aJim Grosbach{ ARM::VLD2q32Pseudo, ARM::VLD2q32, true, false, false, SingleSpc, 4, 2 ,false}, 162a4e3c7fc4ba2d55695b0484480685698132eba20Jim Grosbach{ ARM::VLD2q32PseudoWB_fixed, ARM::VLD2q32wb_fixed, true, true, false, SingleSpc, 4, 2 ,false}, 163a4e3c7fc4ba2d55695b0484480685698132eba20Jim Grosbach{ ARM::VLD2q32PseudoWB_register, ARM::VLD2q32wb_register, true, true, true, SingleSpc, 4, 2 ,false}, 164f9f5a765adf8465530fe1aced6455ca9438bb29aJim Grosbach{ ARM::VLD2q8Pseudo, ARM::VLD2q8, true, false, false, SingleSpc, 4, 8 ,false}, 165a4e3c7fc4ba2d55695b0484480685698132eba20Jim Grosbach{ ARM::VLD2q8PseudoWB_fixed, ARM::VLD2q8wb_fixed, true, true, false, SingleSpc, 4, 8 ,false}, 166a4e3c7fc4ba2d55695b0484480685698132eba20Jim Grosbach{ ARM::VLD2q8PseudoWB_register, ARM::VLD2q8wb_register, true, true, true, SingleSpc, 4, 8 ,false}, 167f9f5a765adf8465530fe1aced6455ca9438bb29aJim Grosbach 168f9f5a765adf8465530fe1aced6455ca9438bb29aJim Grosbach{ ARM::VLD3DUPd16Pseudo, ARM::VLD3DUPd16, true, false, false, SingleSpc, 3, 4,true}, 169f9f5a765adf8465530fe1aced6455ca9438bb29aJim Grosbach{ ARM::VLD3DUPd16Pseudo_UPD, ARM::VLD3DUPd16_UPD, true, true, true, SingleSpc, 3, 4,true}, 170f9f5a765adf8465530fe1aced6455ca9438bb29aJim Grosbach{ ARM::VLD3DUPd32Pseudo, ARM::VLD3DUPd32, true, false, false, SingleSpc, 3, 2,true}, 171f9f5a765adf8465530fe1aced6455ca9438bb29aJim Grosbach{ ARM::VLD3DUPd32Pseudo_UPD, ARM::VLD3DUPd32_UPD, true, true, true, SingleSpc, 3, 2,true}, 172f9f5a765adf8465530fe1aced6455ca9438bb29aJim Grosbach{ ARM::VLD3DUPd8Pseudo, ARM::VLD3DUPd8, true, false, false, SingleSpc, 3, 8,true}, 173f9f5a765adf8465530fe1aced6455ca9438bb29aJim Grosbach{ ARM::VLD3DUPd8Pseudo_UPD, ARM::VLD3DUPd8_UPD, true, true, true, SingleSpc, 3, 8,true}, 174f9f5a765adf8465530fe1aced6455ca9438bb29aJim Grosbach 175f9f5a765adf8465530fe1aced6455ca9438bb29aJim Grosbach{ ARM::VLD3LNd16Pseudo, ARM::VLD3LNd16, true, false, false, SingleSpc, 3, 4 ,true}, 176f9f5a765adf8465530fe1aced6455ca9438bb29aJim Grosbach{ ARM::VLD3LNd16Pseudo_UPD, ARM::VLD3LNd16_UPD, true, true, true, SingleSpc, 3, 4 ,true}, 177f9f5a765adf8465530fe1aced6455ca9438bb29aJim Grosbach{ ARM::VLD3LNd32Pseudo, ARM::VLD3LNd32, true, false, false, SingleSpc, 3, 2 ,true}, 178f9f5a765adf8465530fe1aced6455ca9438bb29aJim Grosbach{ ARM::VLD3LNd32Pseudo_UPD, ARM::VLD3LNd32_UPD, true, true, true, SingleSpc, 3, 2 ,true}, 179f9f5a765adf8465530fe1aced6455ca9438bb29aJim Grosbach{ ARM::VLD3LNd8Pseudo, ARM::VLD3LNd8, true, false, false, SingleSpc, 3, 8 ,true}, 180f9f5a765adf8465530fe1aced6455ca9438bb29aJim Grosbach{ ARM::VLD3LNd8Pseudo_UPD, ARM::VLD3LNd8_UPD, true, true, true, SingleSpc, 3, 8 ,true}, 181f9f5a765adf8465530fe1aced6455ca9438bb29aJim Grosbach{ ARM::VLD3LNq16Pseudo, ARM::VLD3LNq16, true, false, false, EvenDblSpc, 3, 4 ,true}, 182f9f5a765adf8465530fe1aced6455ca9438bb29aJim Grosbach{ ARM::VLD3LNq16Pseudo_UPD, ARM::VLD3LNq16_UPD, true, true, true, EvenDblSpc, 3, 4 ,true}, 183f9f5a765adf8465530fe1aced6455ca9438bb29aJim Grosbach{ ARM::VLD3LNq32Pseudo, ARM::VLD3LNq32, true, false, false, EvenDblSpc, 3, 2 ,true}, 184f9f5a765adf8465530fe1aced6455ca9438bb29aJim Grosbach{ ARM::VLD3LNq32Pseudo_UPD, ARM::VLD3LNq32_UPD, true, true, true, EvenDblSpc, 3, 2 ,true}, 185f9f5a765adf8465530fe1aced6455ca9438bb29aJim Grosbach 186f9f5a765adf8465530fe1aced6455ca9438bb29aJim Grosbach{ ARM::VLD3d16Pseudo, ARM::VLD3d16, true, false, false, SingleSpc, 3, 4 ,true}, 187f9f5a765adf8465530fe1aced6455ca9438bb29aJim Grosbach{ ARM::VLD3d16Pseudo_UPD, ARM::VLD3d16_UPD, true, true, true, SingleSpc, 3, 4 ,true}, 188f9f5a765adf8465530fe1aced6455ca9438bb29aJim Grosbach{ ARM::VLD3d32Pseudo, ARM::VLD3d32, true, false, false, SingleSpc, 3, 2 ,true}, 189f9f5a765adf8465530fe1aced6455ca9438bb29aJim Grosbach{ ARM::VLD3d32Pseudo_UPD, ARM::VLD3d32_UPD, true, true, true, SingleSpc, 3, 2 ,true}, 190f9f5a765adf8465530fe1aced6455ca9438bb29aJim Grosbach{ ARM::VLD3d8Pseudo, ARM::VLD3d8, true, false, false, SingleSpc, 3, 8 ,true}, 191f9f5a765adf8465530fe1aced6455ca9438bb29aJim Grosbach{ ARM::VLD3d8Pseudo_UPD, ARM::VLD3d8_UPD, true, true, true, SingleSpc, 3, 8 ,true}, 192f9f5a765adf8465530fe1aced6455ca9438bb29aJim Grosbach 193f9f5a765adf8465530fe1aced6455ca9438bb29aJim Grosbach{ ARM::VLD3q16Pseudo_UPD, ARM::VLD3q16_UPD, true, true, true, EvenDblSpc, 3, 4 ,true}, 194f9f5a765adf8465530fe1aced6455ca9438bb29aJim Grosbach{ ARM::VLD3q16oddPseudo, ARM::VLD3q16, true, false, false, OddDblSpc, 3, 4 ,true}, 195f9f5a765adf8465530fe1aced6455ca9438bb29aJim Grosbach{ ARM::VLD3q16oddPseudo_UPD, ARM::VLD3q16_UPD, true, true, true, OddDblSpc, 3, 4 ,true}, 196f9f5a765adf8465530fe1aced6455ca9438bb29aJim Grosbach{ ARM::VLD3q32Pseudo_UPD, ARM::VLD3q32_UPD, true, true, true, EvenDblSpc, 3, 2 ,true}, 197f9f5a765adf8465530fe1aced6455ca9438bb29aJim Grosbach{ ARM::VLD3q32oddPseudo, ARM::VLD3q32, true, false, false, OddDblSpc, 3, 2 ,true}, 198f9f5a765adf8465530fe1aced6455ca9438bb29aJim Grosbach{ ARM::VLD3q32oddPseudo_UPD, ARM::VLD3q32_UPD, true, true, true, OddDblSpc, 3, 2 ,true}, 199f9f5a765adf8465530fe1aced6455ca9438bb29aJim Grosbach{ ARM::VLD3q8Pseudo_UPD, ARM::VLD3q8_UPD, true, true, true, EvenDblSpc, 3, 8 ,true}, 200f9f5a765adf8465530fe1aced6455ca9438bb29aJim Grosbach{ ARM::VLD3q8oddPseudo, ARM::VLD3q8, true, false, false, OddDblSpc, 3, 8 ,true}, 201f9f5a765adf8465530fe1aced6455ca9438bb29aJim Grosbach{ ARM::VLD3q8oddPseudo_UPD, ARM::VLD3q8_UPD, true, true, true, OddDblSpc, 3, 8 ,true}, 202f9f5a765adf8465530fe1aced6455ca9438bb29aJim Grosbach 203f9f5a765adf8465530fe1aced6455ca9438bb29aJim Grosbach{ ARM::VLD4DUPd16Pseudo, ARM::VLD4DUPd16, true, false, false, SingleSpc, 4, 4,true}, 204f9f5a765adf8465530fe1aced6455ca9438bb29aJim Grosbach{ ARM::VLD4DUPd16Pseudo_UPD, ARM::VLD4DUPd16_UPD, true, true, true, SingleSpc, 4, 4,true}, 205f9f5a765adf8465530fe1aced6455ca9438bb29aJim Grosbach{ ARM::VLD4DUPd32Pseudo, ARM::VLD4DUPd32, true, false, false, SingleSpc, 4, 2,true}, 206f9f5a765adf8465530fe1aced6455ca9438bb29aJim Grosbach{ ARM::VLD4DUPd32Pseudo_UPD, ARM::VLD4DUPd32_UPD, true, true, true, SingleSpc, 4, 2,true}, 207f9f5a765adf8465530fe1aced6455ca9438bb29aJim Grosbach{ ARM::VLD4DUPd8Pseudo, ARM::VLD4DUPd8, true, false, false, SingleSpc, 4, 8,true}, 208f9f5a765adf8465530fe1aced6455ca9438bb29aJim Grosbach{ ARM::VLD4DUPd8Pseudo_UPD, ARM::VLD4DUPd8_UPD, true, true, true, SingleSpc, 4, 8,true}, 209f9f5a765adf8465530fe1aced6455ca9438bb29aJim Grosbach 210f9f5a765adf8465530fe1aced6455ca9438bb29aJim Grosbach{ ARM::VLD4LNd16Pseudo, ARM::VLD4LNd16, true, false, false, SingleSpc, 4, 4 ,true}, 211f9f5a765adf8465530fe1aced6455ca9438bb29aJim Grosbach{ ARM::VLD4LNd16Pseudo_UPD, ARM::VLD4LNd16_UPD, true, true, true, SingleSpc, 4, 4 ,true}, 212f9f5a765adf8465530fe1aced6455ca9438bb29aJim Grosbach{ ARM::VLD4LNd32Pseudo, ARM::VLD4LNd32, true, false, false, SingleSpc, 4, 2 ,true}, 213f9f5a765adf8465530fe1aced6455ca9438bb29aJim Grosbach{ ARM::VLD4LNd32Pseudo_UPD, ARM::VLD4LNd32_UPD, true, true, true, SingleSpc, 4, 2 ,true}, 214f9f5a765adf8465530fe1aced6455ca9438bb29aJim Grosbach{ ARM::VLD4LNd8Pseudo, ARM::VLD4LNd8, true, false, false, SingleSpc, 4, 8 ,true}, 215f9f5a765adf8465530fe1aced6455ca9438bb29aJim Grosbach{ ARM::VLD4LNd8Pseudo_UPD, ARM::VLD4LNd8_UPD, true, true, true, SingleSpc, 4, 8 ,true}, 216f9f5a765adf8465530fe1aced6455ca9438bb29aJim Grosbach{ ARM::VLD4LNq16Pseudo, ARM::VLD4LNq16, true, false, false, EvenDblSpc, 4, 4 ,true}, 217f9f5a765adf8465530fe1aced6455ca9438bb29aJim Grosbach{ ARM::VLD4LNq16Pseudo_UPD, ARM::VLD4LNq16_UPD, true, true, true, EvenDblSpc, 4, 4 ,true}, 218f9f5a765adf8465530fe1aced6455ca9438bb29aJim Grosbach{ ARM::VLD4LNq32Pseudo, ARM::VLD4LNq32, true, false, false, EvenDblSpc, 4, 2 ,true}, 219f9f5a765adf8465530fe1aced6455ca9438bb29aJim Grosbach{ ARM::VLD4LNq32Pseudo_UPD, ARM::VLD4LNq32_UPD, true, true, true, EvenDblSpc, 4, 2 ,true}, 220f9f5a765adf8465530fe1aced6455ca9438bb29aJim Grosbach 221f9f5a765adf8465530fe1aced6455ca9438bb29aJim Grosbach{ ARM::VLD4d16Pseudo, ARM::VLD4d16, true, false, false, SingleSpc, 4, 4 ,true}, 222f9f5a765adf8465530fe1aced6455ca9438bb29aJim Grosbach{ ARM::VLD4d16Pseudo_UPD, ARM::VLD4d16_UPD, true, true, true, SingleSpc, 4, 4 ,true}, 223f9f5a765adf8465530fe1aced6455ca9438bb29aJim Grosbach{ ARM::VLD4d32Pseudo, ARM::VLD4d32, true, false, false, SingleSpc, 4, 2 ,true}, 224f9f5a765adf8465530fe1aced6455ca9438bb29aJim Grosbach{ ARM::VLD4d32Pseudo_UPD, ARM::VLD4d32_UPD, true, true, true, SingleSpc, 4, 2 ,true}, 225f9f5a765adf8465530fe1aced6455ca9438bb29aJim Grosbach{ ARM::VLD4d8Pseudo, ARM::VLD4d8, true, false, false, SingleSpc, 4, 8 ,true}, 226f9f5a765adf8465530fe1aced6455ca9438bb29aJim Grosbach{ ARM::VLD4d8Pseudo_UPD, ARM::VLD4d8_UPD, true, true, true, SingleSpc, 4, 8 ,true}, 227f9f5a765adf8465530fe1aced6455ca9438bb29aJim Grosbach 228f9f5a765adf8465530fe1aced6455ca9438bb29aJim Grosbach{ ARM::VLD4q16Pseudo_UPD, ARM::VLD4q16_UPD, true, true, true, EvenDblSpc, 4, 4 ,true}, 229f9f5a765adf8465530fe1aced6455ca9438bb29aJim Grosbach{ ARM::VLD4q16oddPseudo, ARM::VLD4q16, true, false, false, OddDblSpc, 4, 4 ,true}, 230f9f5a765adf8465530fe1aced6455ca9438bb29aJim Grosbach{ ARM::VLD4q16oddPseudo_UPD, ARM::VLD4q16_UPD, true, true, true, OddDblSpc, 4, 4 ,true}, 231f9f5a765adf8465530fe1aced6455ca9438bb29aJim Grosbach{ ARM::VLD4q32Pseudo_UPD, ARM::VLD4q32_UPD, true, true, true, EvenDblSpc, 4, 2 ,true}, 232f9f5a765adf8465530fe1aced6455ca9438bb29aJim Grosbach{ ARM::VLD4q32oddPseudo, ARM::VLD4q32, true, false, false, OddDblSpc, 4, 2 ,true}, 233f9f5a765adf8465530fe1aced6455ca9438bb29aJim Grosbach{ ARM::VLD4q32oddPseudo_UPD, ARM::VLD4q32_UPD, true, true, true, OddDblSpc, 4, 2 ,true}, 234f9f5a765adf8465530fe1aced6455ca9438bb29aJim Grosbach{ ARM::VLD4q8Pseudo_UPD, ARM::VLD4q8_UPD, true, true, true, EvenDblSpc, 4, 8 ,true}, 235f9f5a765adf8465530fe1aced6455ca9438bb29aJim Grosbach{ ARM::VLD4q8oddPseudo, ARM::VLD4q8, true, false, false, OddDblSpc, 4, 8 ,true}, 236f9f5a765adf8465530fe1aced6455ca9438bb29aJim Grosbach{ ARM::VLD4q8oddPseudo_UPD, ARM::VLD4q8_UPD, true, true, true, OddDblSpc, 4, 8 ,true}, 237f9f5a765adf8465530fe1aced6455ca9438bb29aJim Grosbach 238f9f5a765adf8465530fe1aced6455ca9438bb29aJim Grosbach{ ARM::VST1LNq16Pseudo, ARM::VST1LNd16, false, false, false, EvenDblSpc, 1, 4 ,true}, 239f9f5a765adf8465530fe1aced6455ca9438bb29aJim Grosbach{ ARM::VST1LNq16Pseudo_UPD, ARM::VST1LNd16_UPD, false, true, true, EvenDblSpc, 1, 4 ,true}, 240f9f5a765adf8465530fe1aced6455ca9438bb29aJim Grosbach{ ARM::VST1LNq32Pseudo, ARM::VST1LNd32, false, false, false, EvenDblSpc, 1, 2 ,true}, 241f9f5a765adf8465530fe1aced6455ca9438bb29aJim Grosbach{ ARM::VST1LNq32Pseudo_UPD, ARM::VST1LNd32_UPD, false, true, true, EvenDblSpc, 1, 2 ,true}, 242f9f5a765adf8465530fe1aced6455ca9438bb29aJim Grosbach{ ARM::VST1LNq8Pseudo, ARM::VST1LNd8, false, false, false, EvenDblSpc, 1, 8 ,true}, 243f9f5a765adf8465530fe1aced6455ca9438bb29aJim Grosbach{ ARM::VST1LNq8Pseudo_UPD, ARM::VST1LNd8_UPD, false, true, true, EvenDblSpc, 1, 8 ,true}, 244f9f5a765adf8465530fe1aced6455ca9438bb29aJim Grosbach 2454c7edb3ad8bd513c59190f6ebee9bee34af7d247Jim Grosbach{ ARM::VST1d64QPseudo, ARM::VST1d64Q, false, false, false, SingleSpc, 4, 1 ,false}, 2464c7edb3ad8bd513c59190f6ebee9bee34af7d247Jim Grosbach{ ARM::VST1d64QPseudoWB_fixed, ARM::VST1d64Qwb_fixed, false, true, false, SingleSpc, 4, 1 ,false}, 2474c7edb3ad8bd513c59190f6ebee9bee34af7d247Jim Grosbach{ ARM::VST1d64QPseudoWB_register, ARM::VST1d64Qwb_register, false, true, true, SingleSpc, 4, 1 ,false}, 248d5ca201891d238ca2185831524a1e3f2670224dfJim Grosbach{ ARM::VST1d64TPseudo, ARM::VST1d64T, false, false, false, SingleSpc, 3, 1 ,false}, 249d5ca201891d238ca2185831524a1e3f2670224dfJim Grosbach{ ARM::VST1d64TPseudoWB_fixed, ARM::VST1d64Twb_fixed, false, true, false, SingleSpc, 3, 1 ,false}, 250d5ca201891d238ca2185831524a1e3f2670224dfJim Grosbach{ ARM::VST1d64TPseudoWB_register, ARM::VST1d64Twb_register, false, true, true, SingleSpc, 3, 1 ,false}, 251f9f5a765adf8465530fe1aced6455ca9438bb29aJim Grosbach 252f9f5a765adf8465530fe1aced6455ca9438bb29aJim Grosbach{ ARM::VST2LNd16Pseudo, ARM::VST2LNd16, false, false, false, SingleSpc, 2, 4 ,true}, 253f9f5a765adf8465530fe1aced6455ca9438bb29aJim Grosbach{ ARM::VST2LNd16Pseudo_UPD, ARM::VST2LNd16_UPD, false, true, true, SingleSpc, 2, 4 ,true}, 254f9f5a765adf8465530fe1aced6455ca9438bb29aJim Grosbach{ ARM::VST2LNd32Pseudo, ARM::VST2LNd32, false, false, false, SingleSpc, 2, 2 ,true}, 255f9f5a765adf8465530fe1aced6455ca9438bb29aJim Grosbach{ ARM::VST2LNd32Pseudo_UPD, ARM::VST2LNd32_UPD, false, true, true, SingleSpc, 2, 2 ,true}, 256f9f5a765adf8465530fe1aced6455ca9438bb29aJim Grosbach{ ARM::VST2LNd8Pseudo, ARM::VST2LNd8, false, false, false, SingleSpc, 2, 8 ,true}, 257f9f5a765adf8465530fe1aced6455ca9438bb29aJim Grosbach{ ARM::VST2LNd8Pseudo_UPD, ARM::VST2LNd8_UPD, false, true, true, SingleSpc, 2, 8 ,true}, 258f9f5a765adf8465530fe1aced6455ca9438bb29aJim Grosbach{ ARM::VST2LNq16Pseudo, ARM::VST2LNq16, false, false, false, EvenDblSpc, 2, 4,true}, 259f9f5a765adf8465530fe1aced6455ca9438bb29aJim Grosbach{ ARM::VST2LNq16Pseudo_UPD, ARM::VST2LNq16_UPD, false, true, true, EvenDblSpc, 2, 4,true}, 260f9f5a765adf8465530fe1aced6455ca9438bb29aJim Grosbach{ ARM::VST2LNq32Pseudo, ARM::VST2LNq32, false, false, false, EvenDblSpc, 2, 2,true}, 261f9f5a765adf8465530fe1aced6455ca9438bb29aJim Grosbach{ ARM::VST2LNq32Pseudo_UPD, ARM::VST2LNq32_UPD, false, true, true, EvenDblSpc, 2, 2,true}, 262f9f5a765adf8465530fe1aced6455ca9438bb29aJim Grosbach 263e90ac9bce9aa6de288568df9bf6133c08534ae2fJim Grosbach{ ARM::VST2q16Pseudo, ARM::VST2q16, false, false, false, SingleSpc, 4, 4 ,false}, 264bb3a2e4d0defc6854d37384d80858037dbbc5f20Jim Grosbach{ ARM::VST2q16PseudoWB_fixed, ARM::VST2q16wb_fixed, false, true, false, SingleSpc, 4, 4 ,false}, 265bb3a2e4d0defc6854d37384d80858037dbbc5f20Jim Grosbach{ ARM::VST2q16PseudoWB_register, ARM::VST2q16wb_register, false, true, true, SingleSpc, 4, 4 ,false}, 266e90ac9bce9aa6de288568df9bf6133c08534ae2fJim Grosbach{ ARM::VST2q32Pseudo, ARM::VST2q32, false, false, false, SingleSpc, 4, 2 ,false}, 267bb3a2e4d0defc6854d37384d80858037dbbc5f20Jim Grosbach{ ARM::VST2q32PseudoWB_fixed, ARM::VST2q32wb_fixed, false, true, false, SingleSpc, 4, 2 ,false}, 268bb3a2e4d0defc6854d37384d80858037dbbc5f20Jim Grosbach{ ARM::VST2q32PseudoWB_register, ARM::VST2q32wb_register, false, true, true, SingleSpc, 4, 2 ,false}, 269e90ac9bce9aa6de288568df9bf6133c08534ae2fJim Grosbach{ ARM::VST2q8Pseudo, ARM::VST2q8, false, false, false, SingleSpc, 4, 8 ,false}, 270bb3a2e4d0defc6854d37384d80858037dbbc5f20Jim Grosbach{ ARM::VST2q8PseudoWB_fixed, ARM::VST2q8wb_fixed, false, true, false, SingleSpc, 4, 8 ,false}, 271bb3a2e4d0defc6854d37384d80858037dbbc5f20Jim Grosbach{ ARM::VST2q8PseudoWB_register, ARM::VST2q8wb_register, false, true, true, SingleSpc, 4, 8 ,false}, 272f9f5a765adf8465530fe1aced6455ca9438bb29aJim Grosbach 273f9f5a765adf8465530fe1aced6455ca9438bb29aJim Grosbach{ ARM::VST3LNd16Pseudo, ARM::VST3LNd16, false, false, false, SingleSpc, 3, 4 ,true}, 274f9f5a765adf8465530fe1aced6455ca9438bb29aJim Grosbach{ ARM::VST3LNd16Pseudo_UPD, ARM::VST3LNd16_UPD, false, true, true, SingleSpc, 3, 4 ,true}, 275f9f5a765adf8465530fe1aced6455ca9438bb29aJim Grosbach{ ARM::VST3LNd32Pseudo, ARM::VST3LNd32, false, false, false, SingleSpc, 3, 2 ,true}, 276f9f5a765adf8465530fe1aced6455ca9438bb29aJim Grosbach{ ARM::VST3LNd32Pseudo_UPD, ARM::VST3LNd32_UPD, false, true, true, SingleSpc, 3, 2 ,true}, 277f9f5a765adf8465530fe1aced6455ca9438bb29aJim Grosbach{ ARM::VST3LNd8Pseudo, ARM::VST3LNd8, false, false, false, SingleSpc, 3, 8 ,true}, 278f9f5a765adf8465530fe1aced6455ca9438bb29aJim Grosbach{ ARM::VST3LNd8Pseudo_UPD, ARM::VST3LNd8_UPD, false, true, true, SingleSpc, 3, 8 ,true}, 279f9f5a765adf8465530fe1aced6455ca9438bb29aJim Grosbach{ ARM::VST3LNq16Pseudo, ARM::VST3LNq16, false, false, false, EvenDblSpc, 3, 4,true}, 280f9f5a765adf8465530fe1aced6455ca9438bb29aJim Grosbach{ ARM::VST3LNq16Pseudo_UPD, ARM::VST3LNq16_UPD, false, true, true, EvenDblSpc, 3, 4,true}, 281f9f5a765adf8465530fe1aced6455ca9438bb29aJim Grosbach{ ARM::VST3LNq32Pseudo, ARM::VST3LNq32, false, false, false, EvenDblSpc, 3, 2,true}, 282f9f5a765adf8465530fe1aced6455ca9438bb29aJim Grosbach{ ARM::VST3LNq32Pseudo_UPD, ARM::VST3LNq32_UPD, false, true, true, EvenDblSpc, 3, 2,true}, 283f9f5a765adf8465530fe1aced6455ca9438bb29aJim Grosbach 284f9f5a765adf8465530fe1aced6455ca9438bb29aJim Grosbach{ ARM::VST3d16Pseudo, ARM::VST3d16, false, false, false, SingleSpc, 3, 4 ,true}, 285f9f5a765adf8465530fe1aced6455ca9438bb29aJim Grosbach{ ARM::VST3d16Pseudo_UPD, ARM::VST3d16_UPD, false, true, true, SingleSpc, 3, 4 ,true}, 286f9f5a765adf8465530fe1aced6455ca9438bb29aJim Grosbach{ ARM::VST3d32Pseudo, ARM::VST3d32, false, false, false, SingleSpc, 3, 2 ,true}, 287f9f5a765adf8465530fe1aced6455ca9438bb29aJim Grosbach{ ARM::VST3d32Pseudo_UPD, ARM::VST3d32_UPD, false, true, true, SingleSpc, 3, 2 ,true}, 288f9f5a765adf8465530fe1aced6455ca9438bb29aJim Grosbach{ ARM::VST3d8Pseudo, ARM::VST3d8, false, false, false, SingleSpc, 3, 8 ,true}, 289f9f5a765adf8465530fe1aced6455ca9438bb29aJim Grosbach{ ARM::VST3d8Pseudo_UPD, ARM::VST3d8_UPD, false, true, true, SingleSpc, 3, 8 ,true}, 290f9f5a765adf8465530fe1aced6455ca9438bb29aJim Grosbach 291f9f5a765adf8465530fe1aced6455ca9438bb29aJim Grosbach{ ARM::VST3q16Pseudo_UPD, ARM::VST3q16_UPD, false, true, true, EvenDblSpc, 3, 4 ,true}, 292f9f5a765adf8465530fe1aced6455ca9438bb29aJim Grosbach{ ARM::VST3q16oddPseudo, ARM::VST3q16, false, false, false, OddDblSpc, 3, 4 ,true}, 293f9f5a765adf8465530fe1aced6455ca9438bb29aJim Grosbach{ ARM::VST3q16oddPseudo_UPD, ARM::VST3q16_UPD, false, true, true, OddDblSpc, 3, 4 ,true}, 294f9f5a765adf8465530fe1aced6455ca9438bb29aJim Grosbach{ ARM::VST3q32Pseudo_UPD, ARM::VST3q32_UPD, false, true, true, EvenDblSpc, 3, 2 ,true}, 295f9f5a765adf8465530fe1aced6455ca9438bb29aJim Grosbach{ ARM::VST3q32oddPseudo, ARM::VST3q32, false, false, false, OddDblSpc, 3, 2 ,true}, 296f9f5a765adf8465530fe1aced6455ca9438bb29aJim Grosbach{ ARM::VST3q32oddPseudo_UPD, ARM::VST3q32_UPD, false, true, true, OddDblSpc, 3, 2 ,true}, 297f9f5a765adf8465530fe1aced6455ca9438bb29aJim Grosbach{ ARM::VST3q8Pseudo_UPD, ARM::VST3q8_UPD, false, true, true, EvenDblSpc, 3, 8 ,true}, 298f9f5a765adf8465530fe1aced6455ca9438bb29aJim Grosbach{ ARM::VST3q8oddPseudo, ARM::VST3q8, false, false, false, OddDblSpc, 3, 8 ,true}, 299f9f5a765adf8465530fe1aced6455ca9438bb29aJim Grosbach{ ARM::VST3q8oddPseudo_UPD, ARM::VST3q8_UPD, false, true, true, OddDblSpc, 3, 8 ,true}, 300f9f5a765adf8465530fe1aced6455ca9438bb29aJim Grosbach 301f9f5a765adf8465530fe1aced6455ca9438bb29aJim Grosbach{ ARM::VST4LNd16Pseudo, ARM::VST4LNd16, false, false, false, SingleSpc, 4, 4 ,true}, 302f9f5a765adf8465530fe1aced6455ca9438bb29aJim Grosbach{ ARM::VST4LNd16Pseudo_UPD, ARM::VST4LNd16_UPD, false, true, true, SingleSpc, 4, 4 ,true}, 303f9f5a765adf8465530fe1aced6455ca9438bb29aJim Grosbach{ ARM::VST4LNd32Pseudo, ARM::VST4LNd32, false, false, false, SingleSpc, 4, 2 ,true}, 304f9f5a765adf8465530fe1aced6455ca9438bb29aJim Grosbach{ ARM::VST4LNd32Pseudo_UPD, ARM::VST4LNd32_UPD, false, true, true, SingleSpc, 4, 2 ,true}, 305f9f5a765adf8465530fe1aced6455ca9438bb29aJim Grosbach{ ARM::VST4LNd8Pseudo, ARM::VST4LNd8, false, false, false, SingleSpc, 4, 8 ,true}, 306f9f5a765adf8465530fe1aced6455ca9438bb29aJim Grosbach{ ARM::VST4LNd8Pseudo_UPD, ARM::VST4LNd8_UPD, false, true, true, SingleSpc, 4, 8 ,true}, 307f9f5a765adf8465530fe1aced6455ca9438bb29aJim Grosbach{ ARM::VST4LNq16Pseudo, ARM::VST4LNq16, false, false, false, EvenDblSpc, 4, 4,true}, 308f9f5a765adf8465530fe1aced6455ca9438bb29aJim Grosbach{ ARM::VST4LNq16Pseudo_UPD, ARM::VST4LNq16_UPD, false, true, true, EvenDblSpc, 4, 4,true}, 309f9f5a765adf8465530fe1aced6455ca9438bb29aJim Grosbach{ ARM::VST4LNq32Pseudo, ARM::VST4LNq32, false, false, false, EvenDblSpc, 4, 2,true}, 310f9f5a765adf8465530fe1aced6455ca9438bb29aJim Grosbach{ ARM::VST4LNq32Pseudo_UPD, ARM::VST4LNq32_UPD, false, true, true, EvenDblSpc, 4, 2,true}, 311f9f5a765adf8465530fe1aced6455ca9438bb29aJim Grosbach 312f9f5a765adf8465530fe1aced6455ca9438bb29aJim Grosbach{ ARM::VST4d16Pseudo, ARM::VST4d16, false, false, false, SingleSpc, 4, 4 ,true}, 313f9f5a765adf8465530fe1aced6455ca9438bb29aJim Grosbach{ ARM::VST4d16Pseudo_UPD, ARM::VST4d16_UPD, false, true, true, SingleSpc, 4, 4 ,true}, 314f9f5a765adf8465530fe1aced6455ca9438bb29aJim Grosbach{ ARM::VST4d32Pseudo, ARM::VST4d32, false, false, false, SingleSpc, 4, 2 ,true}, 315f9f5a765adf8465530fe1aced6455ca9438bb29aJim Grosbach{ ARM::VST4d32Pseudo_UPD, ARM::VST4d32_UPD, false, true, true, SingleSpc, 4, 2 ,true}, 316f9f5a765adf8465530fe1aced6455ca9438bb29aJim Grosbach{ ARM::VST4d8Pseudo, ARM::VST4d8, false, false, false, SingleSpc, 4, 8 ,true}, 317f9f5a765adf8465530fe1aced6455ca9438bb29aJim Grosbach{ ARM::VST4d8Pseudo_UPD, ARM::VST4d8_UPD, false, true, true, SingleSpc, 4, 8 ,true}, 318f9f5a765adf8465530fe1aced6455ca9438bb29aJim Grosbach 319f9f5a765adf8465530fe1aced6455ca9438bb29aJim Grosbach{ ARM::VST4q16Pseudo_UPD, ARM::VST4q16_UPD, false, true, true, EvenDblSpc, 4, 4 ,true}, 320f9f5a765adf8465530fe1aced6455ca9438bb29aJim Grosbach{ ARM::VST4q16oddPseudo, ARM::VST4q16, false, false, false, OddDblSpc, 4, 4 ,true}, 321f9f5a765adf8465530fe1aced6455ca9438bb29aJim Grosbach{ ARM::VST4q16oddPseudo_UPD, ARM::VST4q16_UPD, false, true, true, OddDblSpc, 4, 4 ,true}, 322f9f5a765adf8465530fe1aced6455ca9438bb29aJim Grosbach{ ARM::VST4q32Pseudo_UPD, ARM::VST4q32_UPD, false, true, true, EvenDblSpc, 4, 2 ,true}, 323f9f5a765adf8465530fe1aced6455ca9438bb29aJim Grosbach{ ARM::VST4q32oddPseudo, ARM::VST4q32, false, false, false, OddDblSpc, 4, 2 ,true}, 324f9f5a765adf8465530fe1aced6455ca9438bb29aJim Grosbach{ ARM::VST4q32oddPseudo_UPD, ARM::VST4q32_UPD, false, true, true, OddDblSpc, 4, 2 ,true}, 325f9f5a765adf8465530fe1aced6455ca9438bb29aJim Grosbach{ ARM::VST4q8Pseudo_UPD, ARM::VST4q8_UPD, false, true, true, EvenDblSpc, 4, 8 ,true}, 326f9f5a765adf8465530fe1aced6455ca9438bb29aJim Grosbach{ ARM::VST4q8oddPseudo, ARM::VST4q8, false, false, false, OddDblSpc, 4, 8 ,true}, 327f9f5a765adf8465530fe1aced6455ca9438bb29aJim Grosbach{ ARM::VST4q8oddPseudo_UPD, ARM::VST4q8_UPD, false, true, true, OddDblSpc, 4, 8 ,true} 3288466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson}; 3298466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson 3308466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson/// LookupNEONLdSt - Search the NEONLdStTable for information about a NEON 3318466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson/// load or store pseudo instruction. 3328466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilsonstatic const NEONLdStTableEntry *LookupNEONLdSt(unsigned Opcode) { 333b78ca423844f19f4a838abb49b4b4fa7ae499707Craig Topper const unsigned NumEntries = array_lengthof(NEONLdStTable); 3348466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson 3358466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson#ifndef NDEBUG 3368466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson // Make sure the table is sorted. 3378466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson static bool TableChecked = false; 3388466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson if (!TableChecked) { 3398466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson for (unsigned i = 0; i != NumEntries-1; ++i) 3408466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson assert(NEONLdStTable[i] < NEONLdStTable[i+1] && 3418466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson "NEONLdStTable is not sorted!"); 3428466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson TableChecked = true; 3438466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson } 3448466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson#endif 3458466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson 3468466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson const NEONLdStTableEntry *I = 3478466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson std::lower_bound(NEONLdStTable, NEONLdStTable + NumEntries, Opcode); 3488466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson if (I != NEONLdStTable + NumEntries && I->PseudoOpc == Opcode) 3498466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson return I; 350dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines return nullptr; 3518466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson} 3528466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson 3538466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson/// GetDSubRegs - Get 4 D subregisters of a Q, QQ, or QQQQ register, 3548466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson/// corresponding to the specified register spacing. Not all of the results 3558466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson/// are necessarily valid, e.g., a Q register only has 2 D subregisters. 3568466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilsonstatic void GetDSubRegs(unsigned Reg, NEONRegSpacing RegSpc, 3578466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson const TargetRegisterInfo *TRI, unsigned &D0, 3588466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson unsigned &D1, unsigned &D2, unsigned &D3) { 3598466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson if (RegSpc == SingleSpc) { 3608466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson D0 = TRI->getSubReg(Reg, ARM::dsub_0); 3618466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson D1 = TRI->getSubReg(Reg, ARM::dsub_1); 3628466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson D2 = TRI->getSubReg(Reg, ARM::dsub_2); 3638466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson D3 = TRI->getSubReg(Reg, ARM::dsub_3); 3648466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson } else if (RegSpc == EvenDblSpc) { 3658466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson D0 = TRI->getSubReg(Reg, ARM::dsub_0); 3668466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson D1 = TRI->getSubReg(Reg, ARM::dsub_2); 3678466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson D2 = TRI->getSubReg(Reg, ARM::dsub_4); 3688466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson D3 = TRI->getSubReg(Reg, ARM::dsub_6); 3698466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson } else { 3708466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson assert(RegSpc == OddDblSpc && "unknown register spacing"); 3718466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson D0 = TRI->getSubReg(Reg, ARM::dsub_1); 3728466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson D1 = TRI->getSubReg(Reg, ARM::dsub_3); 3738466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson D2 = TRI->getSubReg(Reg, ARM::dsub_5); 3748466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson D3 = TRI->getSubReg(Reg, ARM::dsub_7); 375bd916c54b7989ddbab373c61eb1ed2556ca44d27Bob Wilson } 3768466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson} 3778466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson 37882a9c8480ecd41a1351274569f8d4e4de2723cf6Bob Wilson/// ExpandVLD - Translate VLD pseudo instructions with Q, QQ or QQQQ register 37982a9c8480ecd41a1351274569f8d4e4de2723cf6Bob Wilson/// operands to real VLD instructions with D register operands. 3808466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilsonvoid ARMExpandPseudo::ExpandVLD(MachineBasicBlock::iterator &MBBI) { 381ffde080ae615906545eb33dab30e7bc47c2ac838Bob Wilson MachineInstr &MI = *MBBI; 382ffde080ae615906545eb33dab30e7bc47c2ac838Bob Wilson MachineBasicBlock &MBB = *MI.getParent(); 383ffde080ae615906545eb33dab30e7bc47c2ac838Bob Wilson 3848466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson const NEONLdStTableEntry *TableEntry = LookupNEONLdSt(MI.getOpcode()); 3858466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson assert(TableEntry && TableEntry->IsLoad && "NEONLdStTable lookup failed"); 386aa258442b9c9f764845660a8f3233c7887e7cf6fCraig Topper NEONRegSpacing RegSpc = (NEONRegSpacing)TableEntry->RegSpacing; 3878466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson unsigned NumRegs = TableEntry->NumRegs; 3888466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson 3898466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson MachineInstrBuilder MIB = BuildMI(MBB, MBBI, MI.getDebugLoc(), 3908466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson TII->get(TableEntry->RealOpc)); 391ffde080ae615906545eb33dab30e7bc47c2ac838Bob Wilson unsigned OpIdx = 0; 392ffde080ae615906545eb33dab30e7bc47c2ac838Bob Wilson 393ffde080ae615906545eb33dab30e7bc47c2ac838Bob Wilson bool DstIsDead = MI.getOperand(OpIdx).isDead(); 394ffde080ae615906545eb33dab30e7bc47c2ac838Bob Wilson unsigned DstReg = MI.getOperand(OpIdx++).getReg(); 395ffde080ae615906545eb33dab30e7bc47c2ac838Bob Wilson unsigned D0, D1, D2, D3; 3968466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson GetDSubRegs(DstReg, RegSpc, TRI, D0, D1, D2, D3); 397280dfad48940a0a51726308dd3daa3b1b0d18705Jim Grosbach MIB.addReg(D0, RegState::Define | getDeadRegState(DstIsDead)); 398280dfad48940a0a51726308dd3daa3b1b0d18705Jim Grosbach if (NumRegs > 1 && TableEntry->copyAllListRegs) 399280dfad48940a0a51726308dd3daa3b1b0d18705Jim Grosbach MIB.addReg(D1, RegState::Define | getDeadRegState(DstIsDead)); 400280dfad48940a0a51726308dd3daa3b1b0d18705Jim Grosbach if (NumRegs > 2 && TableEntry->copyAllListRegs) 401f572191fe43025bd85ab5d398a5b53305fdc6b8bBob Wilson MIB.addReg(D2, RegState::Define | getDeadRegState(DstIsDead)); 402280dfad48940a0a51726308dd3daa3b1b0d18705Jim Grosbach if (NumRegs > 3 && TableEntry->copyAllListRegs) 403f572191fe43025bd85ab5d398a5b53305fdc6b8bBob Wilson MIB.addReg(D3, RegState::Define | getDeadRegState(DstIsDead)); 404ffde080ae615906545eb33dab30e7bc47c2ac838Bob Wilson 405f9f5a765adf8465530fe1aced6455ca9438bb29aJim Grosbach if (TableEntry->isUpdating) 40663569c99ec944210d0edc687d7411b5c687e97a7Bob Wilson MIB.addOperand(MI.getOperand(OpIdx++)); 40763569c99ec944210d0edc687d7411b5c687e97a7Bob Wilson 408ffde080ae615906545eb33dab30e7bc47c2ac838Bob Wilson // Copy the addrmode6 operands. 40963569c99ec944210d0edc687d7411b5c687e97a7Bob Wilson MIB.addOperand(MI.getOperand(OpIdx++)); 41063569c99ec944210d0edc687d7411b5c687e97a7Bob Wilson MIB.addOperand(MI.getOperand(OpIdx++)); 41163569c99ec944210d0edc687d7411b5c687e97a7Bob Wilson // Copy the am6offset operand. 412f9f5a765adf8465530fe1aced6455ca9438bb29aJim Grosbach if (TableEntry->hasWritebackOperand) 41363569c99ec944210d0edc687d7411b5c687e97a7Bob Wilson MIB.addOperand(MI.getOperand(OpIdx++)); 414ffde080ae615906545eb33dab30e7bc47c2ac838Bob Wilson 41519d644d5a9cd6699e5f9f1999deb3c77b2bbdca4Bob Wilson // For an instruction writing double-spaced subregs, the pseudo instruction 416823611bfba4fb2c1abbba2e59d68432c6d0a9e9aBob Wilson // has an extra operand that is a use of the super-register. Record the 417823611bfba4fb2c1abbba2e59d68432c6d0a9e9aBob Wilson // operand index and skip over it. 418823611bfba4fb2c1abbba2e59d68432c6d0a9e9aBob Wilson unsigned SrcOpIdx = 0; 419823611bfba4fb2c1abbba2e59d68432c6d0a9e9aBob Wilson if (RegSpc == EvenDblSpc || RegSpc == OddDblSpc) 420823611bfba4fb2c1abbba2e59d68432c6d0a9e9aBob Wilson SrcOpIdx = OpIdx++; 421823611bfba4fb2c1abbba2e59d68432c6d0a9e9aBob Wilson 422823611bfba4fb2c1abbba2e59d68432c6d0a9e9aBob Wilson // Copy the predicate operands. 423823611bfba4fb2c1abbba2e59d68432c6d0a9e9aBob Wilson MIB.addOperand(MI.getOperand(OpIdx++)); 424823611bfba4fb2c1abbba2e59d68432c6d0a9e9aBob Wilson MIB.addOperand(MI.getOperand(OpIdx++)); 425823611bfba4fb2c1abbba2e59d68432c6d0a9e9aBob Wilson 426823611bfba4fb2c1abbba2e59d68432c6d0a9e9aBob Wilson // Copy the super-register source operand used for double-spaced subregs over 42719d644d5a9cd6699e5f9f1999deb3c77b2bbdca4Bob Wilson // to the new instruction as an implicit operand. 428823611bfba4fb2c1abbba2e59d68432c6d0a9e9aBob Wilson if (SrcOpIdx != 0) { 429823611bfba4fb2c1abbba2e59d68432c6d0a9e9aBob Wilson MachineOperand MO = MI.getOperand(SrcOpIdx); 43019d644d5a9cd6699e5f9f1999deb3c77b2bbdca4Bob Wilson MO.setImplicit(true); 43119d644d5a9cd6699e5f9f1999deb3c77b2bbdca4Bob Wilson MIB.addOperand(MO); 43219d644d5a9cd6699e5f9f1999deb3c77b2bbdca4Bob Wilson } 433f572191fe43025bd85ab5d398a5b53305fdc6b8bBob Wilson // Add an implicit def for the super-register. 434f572191fe43025bd85ab5d398a5b53305fdc6b8bBob Wilson MIB.addReg(DstReg, RegState::ImplicitDefine | getDeadRegState(DstIsDead)); 43519d644d5a9cd6699e5f9f1999deb3c77b2bbdca4Bob Wilson TransferImpOps(MI, MIB, MIB); 436b58a340fa2affa0da27a46c94dd49ba079c9343cEvan Cheng 437b58a340fa2affa0da27a46c94dd49ba079c9343cEvan Cheng // Transfer memoperands. 438d7d030a44796adc73a6eaa939cd17e52047734c1Chris Lattner MIB->setMemRefs(MI.memoperands_begin(), MI.memoperands_end()); 439b58a340fa2affa0da27a46c94dd49ba079c9343cEvan Cheng 440ffde080ae615906545eb33dab30e7bc47c2ac838Bob Wilson MI.eraseFromParent(); 441ffde080ae615906545eb33dab30e7bc47c2ac838Bob Wilson} 442ffde080ae615906545eb33dab30e7bc47c2ac838Bob Wilson 44301ba461af7eafc9d181a5c349487691f2e801438Bob Wilson/// ExpandVST - Translate VST pseudo instructions with Q, QQ or QQQQ register 44401ba461af7eafc9d181a5c349487691f2e801438Bob Wilson/// operands to real VST instructions with D register operands. 4458466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilsonvoid ARMExpandPseudo::ExpandVST(MachineBasicBlock::iterator &MBBI) { 446709d59255a3100c7d440c93069efa1f726677a27Bob Wilson MachineInstr &MI = *MBBI; 447709d59255a3100c7d440c93069efa1f726677a27Bob Wilson MachineBasicBlock &MBB = *MI.getParent(); 448709d59255a3100c7d440c93069efa1f726677a27Bob Wilson 4498466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson const NEONLdStTableEntry *TableEntry = LookupNEONLdSt(MI.getOpcode()); 4508466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson assert(TableEntry && !TableEntry->IsLoad && "NEONLdStTable lookup failed"); 451aa258442b9c9f764845660a8f3233c7887e7cf6fCraig Topper NEONRegSpacing RegSpc = (NEONRegSpacing)TableEntry->RegSpacing; 4528466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson unsigned NumRegs = TableEntry->NumRegs; 4538466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson 4548466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson MachineInstrBuilder MIB = BuildMI(MBB, MBBI, MI.getDebugLoc(), 4558466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson TII->get(TableEntry->RealOpc)); 456709d59255a3100c7d440c93069efa1f726677a27Bob Wilson unsigned OpIdx = 0; 457f9f5a765adf8465530fe1aced6455ca9438bb29aJim Grosbach if (TableEntry->isUpdating) 45863569c99ec944210d0edc687d7411b5c687e97a7Bob Wilson MIB.addOperand(MI.getOperand(OpIdx++)); 45963569c99ec944210d0edc687d7411b5c687e97a7Bob Wilson 460709d59255a3100c7d440c93069efa1f726677a27Bob Wilson // Copy the addrmode6 operands. 46163569c99ec944210d0edc687d7411b5c687e97a7Bob Wilson MIB.addOperand(MI.getOperand(OpIdx++)); 46263569c99ec944210d0edc687d7411b5c687e97a7Bob Wilson MIB.addOperand(MI.getOperand(OpIdx++)); 46363569c99ec944210d0edc687d7411b5c687e97a7Bob Wilson // Copy the am6offset operand. 464f9f5a765adf8465530fe1aced6455ca9438bb29aJim Grosbach if (TableEntry->hasWritebackOperand) 46563569c99ec944210d0edc687d7411b5c687e97a7Bob Wilson MIB.addOperand(MI.getOperand(OpIdx++)); 466709d59255a3100c7d440c93069efa1f726677a27Bob Wilson 467709d59255a3100c7d440c93069efa1f726677a27Bob Wilson bool SrcIsKill = MI.getOperand(OpIdx).isKill(); 468d628a587b654ba737b570ee0611f70a1deb58bbcJakob Stoklund Olesen bool SrcIsUndef = MI.getOperand(OpIdx).isUndef(); 469823611bfba4fb2c1abbba2e59d68432c6d0a9e9aBob Wilson unsigned SrcReg = MI.getOperand(OpIdx++).getReg(); 470709d59255a3100c7d440c93069efa1f726677a27Bob Wilson unsigned D0, D1, D2, D3; 4718466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson GetDSubRegs(SrcReg, RegSpc, TRI, D0, D1, D2, D3); 472d628a587b654ba737b570ee0611f70a1deb58bbcJakob Stoklund Olesen MIB.addReg(D0, getUndefRegState(SrcIsUndef)); 4734334e032525d6c9038605f3871b945e8cbe6fab7Jim Grosbach if (NumRegs > 1 && TableEntry->copyAllListRegs) 474d628a587b654ba737b570ee0611f70a1deb58bbcJakob Stoklund Olesen MIB.addReg(D1, getUndefRegState(SrcIsUndef)); 4754334e032525d6c9038605f3871b945e8cbe6fab7Jim Grosbach if (NumRegs > 2 && TableEntry->copyAllListRegs) 476d628a587b654ba737b570ee0611f70a1deb58bbcJakob Stoklund Olesen MIB.addReg(D2, getUndefRegState(SrcIsUndef)); 4774334e032525d6c9038605f3871b945e8cbe6fab7Jim Grosbach if (NumRegs > 3 && TableEntry->copyAllListRegs) 478d628a587b654ba737b570ee0611f70a1deb58bbcJakob Stoklund Olesen MIB.addReg(D3, getUndefRegState(SrcIsUndef)); 479823611bfba4fb2c1abbba2e59d68432c6d0a9e9aBob Wilson 480823611bfba4fb2c1abbba2e59d68432c6d0a9e9aBob Wilson // Copy the predicate operands. 481823611bfba4fb2c1abbba2e59d68432c6d0a9e9aBob Wilson MIB.addOperand(MI.getOperand(OpIdx++)); 482823611bfba4fb2c1abbba2e59d68432c6d0a9e9aBob Wilson MIB.addOperand(MI.getOperand(OpIdx++)); 483823611bfba4fb2c1abbba2e59d68432c6d0a9e9aBob Wilson 484d628a587b654ba737b570ee0611f70a1deb58bbcJakob Stoklund Olesen if (SrcIsKill && !SrcIsUndef) // Add an implicit kill for the super-reg. 485d7d030a44796adc73a6eaa939cd17e52047734c1Chris Lattner MIB->addRegisterKilled(SrcReg, TRI, true); 48636b56886974eae4f9c5ebc96befd3e7bfe5de338Stephen Hines else if (!SrcIsUndef) 48736b56886974eae4f9c5ebc96befd3e7bfe5de338Stephen Hines MIB.addReg(SrcReg, RegState::Implicit); // Add implicit uses for src reg. 488bd916c54b7989ddbab373c61eb1ed2556ca44d27Bob Wilson TransferImpOps(MI, MIB, MIB); 489b58a340fa2affa0da27a46c94dd49ba079c9343cEvan Cheng 490b58a340fa2affa0da27a46c94dd49ba079c9343cEvan Cheng // Transfer memoperands. 491d7d030a44796adc73a6eaa939cd17e52047734c1Chris Lattner MIB->setMemRefs(MI.memoperands_begin(), MI.memoperands_end()); 492b58a340fa2affa0da27a46c94dd49ba079c9343cEvan Cheng 493709d59255a3100c7d440c93069efa1f726677a27Bob Wilson MI.eraseFromParent(); 494709d59255a3100c7d440c93069efa1f726677a27Bob Wilson} 495709d59255a3100c7d440c93069efa1f726677a27Bob Wilson 4968466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson/// ExpandLaneOp - Translate VLD*LN and VST*LN instructions with Q, QQ or QQQQ 4978466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson/// register operands to real instructions with D register operands. 4988466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilsonvoid ARMExpandPseudo::ExpandLaneOp(MachineBasicBlock::iterator &MBBI) { 4998466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson MachineInstr &MI = *MBBI; 5008466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson MachineBasicBlock &MBB = *MI.getParent(); 5018466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson 5028466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson const NEONLdStTableEntry *TableEntry = LookupNEONLdSt(MI.getOpcode()); 5038466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson assert(TableEntry && "NEONLdStTable lookup failed"); 504aa258442b9c9f764845660a8f3233c7887e7cf6fCraig Topper NEONRegSpacing RegSpc = (NEONRegSpacing)TableEntry->RegSpacing; 5058466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson unsigned NumRegs = TableEntry->NumRegs; 5068466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson unsigned RegElts = TableEntry->RegElts; 5078466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson 5088466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson MachineInstrBuilder MIB = BuildMI(MBB, MBBI, MI.getDebugLoc(), 5098466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson TII->get(TableEntry->RealOpc)); 5108466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson unsigned OpIdx = 0; 5118466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson // The lane operand is always the 3rd from last operand, before the 2 5128466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson // predicate operands. 5138466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson unsigned Lane = MI.getOperand(MI.getDesc().getNumOperands() - 3).getImm(); 5148466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson 5158466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson // Adjust the lane and spacing as needed for Q registers. 5168466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson assert(RegSpc != OddDblSpc && "unexpected register spacing for VLD/VST-lane"); 5178466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson if (RegSpc == EvenDblSpc && Lane >= RegElts) { 5188466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson RegSpc = OddDblSpc; 5198466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson Lane -= RegElts; 5208466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson } 5218466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson assert(Lane < RegElts && "out of range lane for VLD/VST-lane"); 5228466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson 523584520e8e2c1f8cc04bc8dd4dc4ea6c390627317Ted Kremenek unsigned D0 = 0, D1 = 0, D2 = 0, D3 = 0; 524fe3ac088ee0a536f60b3c30ad97703d5d6cd2167Bob Wilson unsigned DstReg = 0; 525fe3ac088ee0a536f60b3c30ad97703d5d6cd2167Bob Wilson bool DstIsDead = false; 5268466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson if (TableEntry->IsLoad) { 5278466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson DstIsDead = MI.getOperand(OpIdx).isDead(); 5288466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson DstReg = MI.getOperand(OpIdx++).getReg(); 5298466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson GetDSubRegs(DstReg, RegSpc, TRI, D0, D1, D2, D3); 530b796bbb6de19872c0c1921b8b3f05206dd33c97dBob Wilson MIB.addReg(D0, RegState::Define | getDeadRegState(DstIsDead)); 531b796bbb6de19872c0c1921b8b3f05206dd33c97dBob Wilson if (NumRegs > 1) 532b796bbb6de19872c0c1921b8b3f05206dd33c97dBob Wilson MIB.addReg(D1, RegState::Define | getDeadRegState(DstIsDead)); 5338466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson if (NumRegs > 2) 5348466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson MIB.addReg(D2, RegState::Define | getDeadRegState(DstIsDead)); 5358466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson if (NumRegs > 3) 5368466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson MIB.addReg(D3, RegState::Define | getDeadRegState(DstIsDead)); 5378466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson } 5388466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson 539f9f5a765adf8465530fe1aced6455ca9438bb29aJim Grosbach if (TableEntry->isUpdating) 5408466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson MIB.addOperand(MI.getOperand(OpIdx++)); 5418466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson 5428466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson // Copy the addrmode6 operands. 5438466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson MIB.addOperand(MI.getOperand(OpIdx++)); 5448466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson MIB.addOperand(MI.getOperand(OpIdx++)); 5458466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson // Copy the am6offset operand. 546f9f5a765adf8465530fe1aced6455ca9438bb29aJim Grosbach if (TableEntry->hasWritebackOperand) 5478466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson MIB.addOperand(MI.getOperand(OpIdx++)); 5488466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson 5498466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson // Grab the super-register source. 5508466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson MachineOperand MO = MI.getOperand(OpIdx++); 5518466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson if (!TableEntry->IsLoad) 5528466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson GetDSubRegs(MO.getReg(), RegSpc, TRI, D0, D1, D2, D3); 5538466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson 5548466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson // Add the subregs as sources of the new instruction. 5558466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson unsigned SrcFlags = (getUndefRegState(MO.isUndef()) | 5568466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson getKillRegState(MO.isKill())); 557b796bbb6de19872c0c1921b8b3f05206dd33c97dBob Wilson MIB.addReg(D0, SrcFlags); 558b796bbb6de19872c0c1921b8b3f05206dd33c97dBob Wilson if (NumRegs > 1) 559b796bbb6de19872c0c1921b8b3f05206dd33c97dBob Wilson MIB.addReg(D1, SrcFlags); 5608466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson if (NumRegs > 2) 5618466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson MIB.addReg(D2, SrcFlags); 5628466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson if (NumRegs > 3) 5638466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson MIB.addReg(D3, SrcFlags); 5648466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson 5658466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson // Add the lane number operand. 5668466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson MIB.addImm(Lane); 567823611bfba4fb2c1abbba2e59d68432c6d0a9e9aBob Wilson OpIdx += 1; 568823611bfba4fb2c1abbba2e59d68432c6d0a9e9aBob Wilson 569823611bfba4fb2c1abbba2e59d68432c6d0a9e9aBob Wilson // Copy the predicate operands. 570823611bfba4fb2c1abbba2e59d68432c6d0a9e9aBob Wilson MIB.addOperand(MI.getOperand(OpIdx++)); 571823611bfba4fb2c1abbba2e59d68432c6d0a9e9aBob Wilson MIB.addOperand(MI.getOperand(OpIdx++)); 5728466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson 5738466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson // Copy the super-register source to be an implicit source. 5748466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson MO.setImplicit(true); 5758466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson MIB.addOperand(MO); 5768466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson if (TableEntry->IsLoad) 5778466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson // Add an implicit def for the super-register. 5788466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson MIB.addReg(DstReg, RegState::ImplicitDefine | getDeadRegState(DstIsDead)); 5798466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson TransferImpOps(MI, MIB, MIB); 5802027379985f1cbb965be808adad5b819a66dd97fJakob Stoklund Olesen // Transfer memoperands. 5812027379985f1cbb965be808adad5b819a66dd97fJakob Stoklund Olesen MIB->setMemRefs(MI.memoperands_begin(), MI.memoperands_end()); 5828466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson MI.eraseFromParent(); 5838466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson} 5848466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson 585bd916c54b7989ddbab373c61eb1ed2556ca44d27Bob Wilson/// ExpandVTBL - Translate VTBL and VTBX pseudo instructions with Q or QQ 586bd916c54b7989ddbab373c61eb1ed2556ca44d27Bob Wilson/// register operands to real instructions with D register operands. 587bd916c54b7989ddbab373c61eb1ed2556ca44d27Bob Wilsonvoid ARMExpandPseudo::ExpandVTBL(MachineBasicBlock::iterator &MBBI, 58860d99a5278e4a0e7116a05c01cececb07ca1362aJim Grosbach unsigned Opc, bool IsExt) { 589bd916c54b7989ddbab373c61eb1ed2556ca44d27Bob Wilson MachineInstr &MI = *MBBI; 590bd916c54b7989ddbab373c61eb1ed2556ca44d27Bob Wilson MachineBasicBlock &MBB = *MI.getParent(); 591bd916c54b7989ddbab373c61eb1ed2556ca44d27Bob Wilson 592bd916c54b7989ddbab373c61eb1ed2556ca44d27Bob Wilson MachineInstrBuilder MIB = BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(Opc)); 593bd916c54b7989ddbab373c61eb1ed2556ca44d27Bob Wilson unsigned OpIdx = 0; 594bd916c54b7989ddbab373c61eb1ed2556ca44d27Bob Wilson 595bd916c54b7989ddbab373c61eb1ed2556ca44d27Bob Wilson // Transfer the destination register operand. 596bd916c54b7989ddbab373c61eb1ed2556ca44d27Bob Wilson MIB.addOperand(MI.getOperand(OpIdx++)); 597bd916c54b7989ddbab373c61eb1ed2556ca44d27Bob Wilson if (IsExt) 598bd916c54b7989ddbab373c61eb1ed2556ca44d27Bob Wilson MIB.addOperand(MI.getOperand(OpIdx++)); 599bd916c54b7989ddbab373c61eb1ed2556ca44d27Bob Wilson 600bd916c54b7989ddbab373c61eb1ed2556ca44d27Bob Wilson bool SrcIsKill = MI.getOperand(OpIdx).isKill(); 601bd916c54b7989ddbab373c61eb1ed2556ca44d27Bob Wilson unsigned SrcReg = MI.getOperand(OpIdx++).getReg(); 602bd916c54b7989ddbab373c61eb1ed2556ca44d27Bob Wilson unsigned D0, D1, D2, D3; 603bd916c54b7989ddbab373c61eb1ed2556ca44d27Bob Wilson GetDSubRegs(SrcReg, SingleSpc, TRI, D0, D1, D2, D3); 60460d99a5278e4a0e7116a05c01cececb07ca1362aJim Grosbach MIB.addReg(D0); 605bd916c54b7989ddbab373c61eb1ed2556ca44d27Bob Wilson 606bd916c54b7989ddbab373c61eb1ed2556ca44d27Bob Wilson // Copy the other source register operand. 607823611bfba4fb2c1abbba2e59d68432c6d0a9e9aBob Wilson MIB.addOperand(MI.getOperand(OpIdx++)); 608823611bfba4fb2c1abbba2e59d68432c6d0a9e9aBob Wilson 609823611bfba4fb2c1abbba2e59d68432c6d0a9e9aBob Wilson // Copy the predicate operands. 610823611bfba4fb2c1abbba2e59d68432c6d0a9e9aBob Wilson MIB.addOperand(MI.getOperand(OpIdx++)); 611823611bfba4fb2c1abbba2e59d68432c6d0a9e9aBob Wilson MIB.addOperand(MI.getOperand(OpIdx++)); 612bd916c54b7989ddbab373c61eb1ed2556ca44d27Bob Wilson 61336b56886974eae4f9c5ebc96befd3e7bfe5de338Stephen Hines // Add an implicit kill and use for the super-reg. 61436b56886974eae4f9c5ebc96befd3e7bfe5de338Stephen Hines MIB.addReg(SrcReg, RegState::Implicit | getKillRegState(SrcIsKill)); 615bd916c54b7989ddbab373c61eb1ed2556ca44d27Bob Wilson TransferImpOps(MI, MIB, MIB); 616bd916c54b7989ddbab373c61eb1ed2556ca44d27Bob Wilson MI.eraseFromParent(); 617bd916c54b7989ddbab373c61eb1ed2556ca44d27Bob Wilson} 618bd916c54b7989ddbab373c61eb1ed2556ca44d27Bob Wilson 619dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hinesstatic bool IsAnAddressOperand(const MachineOperand &MO) { 620dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines // This check is overly conservative. Unless we are certain that the machine 621dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines // operand is not a symbol reference, we return that it is a symbol reference. 622dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines // This is important as the load pair may not be split up Windows. 623dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines switch (MO.getType()) { 624dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines case MachineOperand::MO_Register: 625dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines case MachineOperand::MO_Immediate: 626dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines case MachineOperand::MO_CImmediate: 627dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines case MachineOperand::MO_FPImmediate: 628dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines return false; 629dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines case MachineOperand::MO_MachineBasicBlock: 630dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines return true; 631dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines case MachineOperand::MO_FrameIndex: 632dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines return false; 633dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines case MachineOperand::MO_ConstantPoolIndex: 634dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines case MachineOperand::MO_TargetIndex: 635dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines case MachineOperand::MO_JumpTableIndex: 636dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines case MachineOperand::MO_ExternalSymbol: 637dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines case MachineOperand::MO_GlobalAddress: 638dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines case MachineOperand::MO_BlockAddress: 639dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines return true; 640dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines case MachineOperand::MO_RegisterMask: 641dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines case MachineOperand::MO_RegisterLiveOut: 642dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines return false; 643dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines case MachineOperand::MO_Metadata: 644dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines case MachineOperand::MO_MCSymbol: 645dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines return true; 646dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines case MachineOperand::MO_CFIIndex: 647dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines return false; 648dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines } 649dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines llvm_unreachable("unhandled machine operand type"); 650dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines} 651dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines 6529fe2009956fc40f3aea46fb3c38dcfb61c4aca46Evan Chengvoid ARMExpandPseudo::ExpandMOV32BitImm(MachineBasicBlock &MBB, 6539fe2009956fc40f3aea46fb3c38dcfb61c4aca46Evan Cheng MachineBasicBlock::iterator &MBBI) { 6549fe2009956fc40f3aea46fb3c38dcfb61c4aca46Evan Cheng MachineInstr &MI = *MBBI; 6559fe2009956fc40f3aea46fb3c38dcfb61c4aca46Evan Cheng unsigned Opcode = MI.getOpcode(); 6569fe2009956fc40f3aea46fb3c38dcfb61c4aca46Evan Cheng unsigned PredReg = 0; 657c89c744b69cecac576317a98322fd295e36e9886Craig Topper ARMCC::CondCodes Pred = getInstrPredicate(&MI, PredReg); 6589fe2009956fc40f3aea46fb3c38dcfb61c4aca46Evan Cheng unsigned DstReg = MI.getOperand(0).getReg(); 6599fe2009956fc40f3aea46fb3c38dcfb61c4aca46Evan Cheng bool DstIsDead = MI.getOperand(0).isDead(); 6609fe2009956fc40f3aea46fb3c38dcfb61c4aca46Evan Cheng bool isCC = Opcode == ARM::MOVCCi32imm || Opcode == ARM::t2MOVCCi32imm; 6619fe2009956fc40f3aea46fb3c38dcfb61c4aca46Evan Cheng const MachineOperand &MO = MI.getOperand(isCC ? 2 : 1); 662dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines bool RequiresBundling = STI->isTargetWindows() && IsAnAddressOperand(MO); 6639fe2009956fc40f3aea46fb3c38dcfb61c4aca46Evan Cheng MachineInstrBuilder LO16, HI16; 6649fe2009956fc40f3aea46fb3c38dcfb61c4aca46Evan Cheng 6659fe2009956fc40f3aea46fb3c38dcfb61c4aca46Evan Cheng if (!STI->hasV6T2Ops() && 6669fe2009956fc40f3aea46fb3c38dcfb61c4aca46Evan Cheng (Opcode == ARM::MOVi32imm || Opcode == ARM::MOVCCi32imm)) { 667dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines // FIXME Windows CE supports older ARM CPUs 668dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines assert(!STI->isTargetWindows() && "Windows on ARM requires ARMv7+"); 669dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines 6709fe2009956fc40f3aea46fb3c38dcfb61c4aca46Evan Cheng // Expand into a movi + orr. 6719fe2009956fc40f3aea46fb3c38dcfb61c4aca46Evan Cheng LO16 = BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(ARM::MOVi), DstReg); 6729fe2009956fc40f3aea46fb3c38dcfb61c4aca46Evan Cheng HI16 = BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(ARM::ORRri)) 6739fe2009956fc40f3aea46fb3c38dcfb61c4aca46Evan Cheng .addReg(DstReg, RegState::Define | getDeadRegState(DstIsDead)) 6749fe2009956fc40f3aea46fb3c38dcfb61c4aca46Evan Cheng .addReg(DstReg); 6759fe2009956fc40f3aea46fb3c38dcfb61c4aca46Evan Cheng 6769fe2009956fc40f3aea46fb3c38dcfb61c4aca46Evan Cheng assert (MO.isImm() && "MOVi32imm w/ non-immediate source operand!"); 6779fe2009956fc40f3aea46fb3c38dcfb61c4aca46Evan Cheng unsigned ImmVal = (unsigned)MO.getImm(); 6789fe2009956fc40f3aea46fb3c38dcfb61c4aca46Evan Cheng unsigned SOImmValV1 = ARM_AM::getSOImmTwoPartFirst(ImmVal); 6799fe2009956fc40f3aea46fb3c38dcfb61c4aca46Evan Cheng unsigned SOImmValV2 = ARM_AM::getSOImmTwoPartSecond(ImmVal); 6809fe2009956fc40f3aea46fb3c38dcfb61c4aca46Evan Cheng LO16 = LO16.addImm(SOImmValV1); 6819fe2009956fc40f3aea46fb3c38dcfb61c4aca46Evan Cheng HI16 = HI16.addImm(SOImmValV2); 682d7d030a44796adc73a6eaa939cd17e52047734c1Chris Lattner LO16->setMemRefs(MI.memoperands_begin(), MI.memoperands_end()); 683d7d030a44796adc73a6eaa939cd17e52047734c1Chris Lattner HI16->setMemRefs(MI.memoperands_begin(), MI.memoperands_end()); 6849fe2009956fc40f3aea46fb3c38dcfb61c4aca46Evan Cheng LO16.addImm(Pred).addReg(PredReg).addReg(0); 6859fe2009956fc40f3aea46fb3c38dcfb61c4aca46Evan Cheng HI16.addImm(Pred).addReg(PredReg).addReg(0); 6869fe2009956fc40f3aea46fb3c38dcfb61c4aca46Evan Cheng TransferImpOps(MI, LO16, HI16); 6879fe2009956fc40f3aea46fb3c38dcfb61c4aca46Evan Cheng MI.eraseFromParent(); 6889fe2009956fc40f3aea46fb3c38dcfb61c4aca46Evan Cheng return; 6899fe2009956fc40f3aea46fb3c38dcfb61c4aca46Evan Cheng } 690b9803a8fa65f043c96612fa9c5aeeee12739db2bEvan Cheng 6919fe2009956fc40f3aea46fb3c38dcfb61c4aca46Evan Cheng unsigned LO16Opc = 0; 6929fe2009956fc40f3aea46fb3c38dcfb61c4aca46Evan Cheng unsigned HI16Opc = 0; 6939fe2009956fc40f3aea46fb3c38dcfb61c4aca46Evan Cheng if (Opcode == ARM::t2MOVi32imm || Opcode == ARM::t2MOVCCi32imm) { 6949fe2009956fc40f3aea46fb3c38dcfb61c4aca46Evan Cheng LO16Opc = ARM::t2MOVi16; 6959fe2009956fc40f3aea46fb3c38dcfb61c4aca46Evan Cheng HI16Opc = ARM::t2MOVTi16; 6969fe2009956fc40f3aea46fb3c38dcfb61c4aca46Evan Cheng } else { 6979fe2009956fc40f3aea46fb3c38dcfb61c4aca46Evan Cheng LO16Opc = ARM::MOVi16; 6989fe2009956fc40f3aea46fb3c38dcfb61c4aca46Evan Cheng HI16Opc = ARM::MOVTi16; 6999fe2009956fc40f3aea46fb3c38dcfb61c4aca46Evan Cheng } 700b9803a8fa65f043c96612fa9c5aeeee12739db2bEvan Cheng 7019fe2009956fc40f3aea46fb3c38dcfb61c4aca46Evan Cheng LO16 = BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(LO16Opc), DstReg); 7029fe2009956fc40f3aea46fb3c38dcfb61c4aca46Evan Cheng HI16 = BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(HI16Opc)) 7039fe2009956fc40f3aea46fb3c38dcfb61c4aca46Evan Cheng .addReg(DstReg, RegState::Define | getDeadRegState(DstIsDead)) 7049fe2009956fc40f3aea46fb3c38dcfb61c4aca46Evan Cheng .addReg(DstReg); 7059fe2009956fc40f3aea46fb3c38dcfb61c4aca46Evan Cheng 706dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines switch (MO.getType()) { 707dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines case MachineOperand::MO_Immediate: { 7089fe2009956fc40f3aea46fb3c38dcfb61c4aca46Evan Cheng unsigned Imm = MO.getImm(); 7099fe2009956fc40f3aea46fb3c38dcfb61c4aca46Evan Cheng unsigned Lo16 = Imm & 0xffff; 7109fe2009956fc40f3aea46fb3c38dcfb61c4aca46Evan Cheng unsigned Hi16 = (Imm >> 16) & 0xffff; 7119fe2009956fc40f3aea46fb3c38dcfb61c4aca46Evan Cheng LO16 = LO16.addImm(Lo16); 7129fe2009956fc40f3aea46fb3c38dcfb61c4aca46Evan Cheng HI16 = HI16.addImm(Hi16); 713dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines break; 714dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines } 715dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines case MachineOperand::MO_ExternalSymbol: { 716dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines const char *ES = MO.getSymbolName(); 717dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines unsigned TF = MO.getTargetFlags(); 718dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines LO16 = LO16.addExternalSymbol(ES, TF | ARMII::MO_LO16); 719dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines HI16 = HI16.addExternalSymbol(ES, TF | ARMII::MO_HI16); 720dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines break; 721dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines } 722dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines default: { 7239fe2009956fc40f3aea46fb3c38dcfb61c4aca46Evan Cheng const GlobalValue *GV = MO.getGlobal(); 7249fe2009956fc40f3aea46fb3c38dcfb61c4aca46Evan Cheng unsigned TF = MO.getTargetFlags(); 7259fe2009956fc40f3aea46fb3c38dcfb61c4aca46Evan Cheng LO16 = LO16.addGlobalAddress(GV, MO.getOffset(), TF | ARMII::MO_LO16); 7269fe2009956fc40f3aea46fb3c38dcfb61c4aca46Evan Cheng HI16 = HI16.addGlobalAddress(GV, MO.getOffset(), TF | ARMII::MO_HI16); 727dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines break; 728dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines } 7299fe2009956fc40f3aea46fb3c38dcfb61c4aca46Evan Cheng } 730709d59255a3100c7d440c93069efa1f726677a27Bob Wilson 731d7d030a44796adc73a6eaa939cd17e52047734c1Chris Lattner LO16->setMemRefs(MI.memoperands_begin(), MI.memoperands_end()); 732d7d030a44796adc73a6eaa939cd17e52047734c1Chris Lattner HI16->setMemRefs(MI.memoperands_begin(), MI.memoperands_end()); 7339fe2009956fc40f3aea46fb3c38dcfb61c4aca46Evan Cheng LO16.addImm(Pred).addReg(PredReg); 7349fe2009956fc40f3aea46fb3c38dcfb61c4aca46Evan Cheng HI16.addImm(Pred).addReg(PredReg); 7359fe2009956fc40f3aea46fb3c38dcfb61c4aca46Evan Cheng 736dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines if (RequiresBundling) 737dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines finalizeBundle(MBB, &*LO16, &*MBBI); 738dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines 7399fe2009956fc40f3aea46fb3c38dcfb61c4aca46Evan Cheng TransferImpOps(MI, LO16, HI16); 7409fe2009956fc40f3aea46fb3c38dcfb61c4aca46Evan Cheng MI.eraseFromParent(); 7419fe2009956fc40f3aea46fb3c38dcfb61c4aca46Evan Cheng} 7429fe2009956fc40f3aea46fb3c38dcfb61c4aca46Evan Cheng 7439fe2009956fc40f3aea46fb3c38dcfb61c4aca46Evan Chengbool ARMExpandPseudo::ExpandMI(MachineBasicBlock &MBB, 7449fe2009956fc40f3aea46fb3c38dcfb61c4aca46Evan Cheng MachineBasicBlock::iterator MBBI) { 7459fe2009956fc40f3aea46fb3c38dcfb61c4aca46Evan Cheng MachineInstr &MI = *MBBI; 7469fe2009956fc40f3aea46fb3c38dcfb61c4aca46Evan Cheng unsigned Opcode = MI.getOpcode(); 7479fe2009956fc40f3aea46fb3c38dcfb61c4aca46Evan Cheng switch (Opcode) { 7489fe2009956fc40f3aea46fb3c38dcfb61c4aca46Evan Cheng default: 7499fe2009956fc40f3aea46fb3c38dcfb61c4aca46Evan Cheng return false; 750f219f3135d0ec939acd42801766c17fad41c0173Jim Grosbach case ARM::VMOVScc: 751f219f3135d0ec939acd42801766c17fad41c0173Jim Grosbach case ARM::VMOVDcc: { 752f219f3135d0ec939acd42801766c17fad41c0173Jim Grosbach unsigned newOpc = Opcode == ARM::VMOVScc ? ARM::VMOVS : ARM::VMOVD; 753f219f3135d0ec939acd42801766c17fad41c0173Jim Grosbach BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(newOpc), 754f219f3135d0ec939acd42801766c17fad41c0173Jim Grosbach MI.getOperand(1).getReg()) 755e1bde51d63f888e0011dfd3b9cfd78b1736d0b5dMatthias Braun .addOperand(MI.getOperand(2)) 756f219f3135d0ec939acd42801766c17fad41c0173Jim Grosbach .addImm(MI.getOperand(3).getImm()) // 'pred' 757e1bde51d63f888e0011dfd3b9cfd78b1736d0b5dMatthias Braun .addOperand(MI.getOperand(4)); 758f219f3135d0ec939acd42801766c17fad41c0173Jim Grosbach 759f219f3135d0ec939acd42801766c17fad41c0173Jim Grosbach MI.eraseFromParent(); 760f219f3135d0ec939acd42801766c17fad41c0173Jim Grosbach return true; 761f219f3135d0ec939acd42801766c17fad41c0173Jim Grosbach } 762efeedceb41cc0c5ff7918cad870d5820de84b03dJim Grosbach case ARM::t2MOVCCr: 763d4a16ad85d991ff12487b40ef248833448047eadJim Grosbach case ARM::MOVCCr: { 764efeedceb41cc0c5ff7918cad870d5820de84b03dJim Grosbach unsigned Opc = AFI->isThumbFunction() ? ARM::t2MOVr : ARM::MOVr; 765efeedceb41cc0c5ff7918cad870d5820de84b03dJim Grosbach BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(Opc), 766d4a16ad85d991ff12487b40ef248833448047eadJim Grosbach MI.getOperand(1).getReg()) 767e1bde51d63f888e0011dfd3b9cfd78b1736d0b5dMatthias Braun .addOperand(MI.getOperand(2)) 768d4a16ad85d991ff12487b40ef248833448047eadJim Grosbach .addImm(MI.getOperand(3).getImm()) // 'pred' 769e1bde51d63f888e0011dfd3b9cfd78b1736d0b5dMatthias Braun .addOperand(MI.getOperand(4)) 770d4a16ad85d991ff12487b40ef248833448047eadJim Grosbach .addReg(0); // 's' bit 771d4a16ad85d991ff12487b40ef248833448047eadJim Grosbach 772d4a16ad85d991ff12487b40ef248833448047eadJim Grosbach MI.eraseFromParent(); 773d4a16ad85d991ff12487b40ef248833448047eadJim Grosbach return true; 774d4a16ad85d991ff12487b40ef248833448047eadJim Grosbach } 775152d4a4bb6b75de740b4b8a9f48abb9069d50c17Owen Anderson case ARM::MOVCCsi: { 776152d4a4bb6b75de740b4b8a9f48abb9069d50c17Owen Anderson BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(ARM::MOVsi), 777152d4a4bb6b75de740b4b8a9f48abb9069d50c17Owen Anderson (MI.getOperand(1).getReg())) 778e1bde51d63f888e0011dfd3b9cfd78b1736d0b5dMatthias Braun .addOperand(MI.getOperand(2)) 779152d4a4bb6b75de740b4b8a9f48abb9069d50c17Owen Anderson .addImm(MI.getOperand(3).getImm()) 780152d4a4bb6b75de740b4b8a9f48abb9069d50c17Owen Anderson .addImm(MI.getOperand(4).getImm()) // 'pred' 781e1bde51d63f888e0011dfd3b9cfd78b1736d0b5dMatthias Braun .addOperand(MI.getOperand(5)) 782152d4a4bb6b75de740b4b8a9f48abb9069d50c17Owen Anderson .addReg(0); // 's' bit 783152d4a4bb6b75de740b4b8a9f48abb9069d50c17Owen Anderson 784152d4a4bb6b75de740b4b8a9f48abb9069d50c17Owen Anderson MI.eraseFromParent(); 785152d4a4bb6b75de740b4b8a9f48abb9069d50c17Owen Anderson return true; 786152d4a4bb6b75de740b4b8a9f48abb9069d50c17Owen Anderson } 78792a202213bb4c20301abf6ab64e46df3695e60bfOwen Anderson case ARM::MOVCCsr: { 788152d4a4bb6b75de740b4b8a9f48abb9069d50c17Owen Anderson BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(ARM::MOVsr), 789d4a16ad85d991ff12487b40ef248833448047eadJim Grosbach (MI.getOperand(1).getReg())) 790e1bde51d63f888e0011dfd3b9cfd78b1736d0b5dMatthias Braun .addOperand(MI.getOperand(2)) 791e1bde51d63f888e0011dfd3b9cfd78b1736d0b5dMatthias Braun .addOperand(MI.getOperand(3)) 792d4a16ad85d991ff12487b40ef248833448047eadJim Grosbach .addImm(MI.getOperand(4).getImm()) 793d4a16ad85d991ff12487b40ef248833448047eadJim Grosbach .addImm(MI.getOperand(5).getImm()) // 'pred' 794e1bde51d63f888e0011dfd3b9cfd78b1736d0b5dMatthias Braun .addOperand(MI.getOperand(6)) 795d4a16ad85d991ff12487b40ef248833448047eadJim Grosbach .addReg(0); // 's' bit 7963906276a8d4b308a19675d5a67b2d6ab3e3b9b6fJim Grosbach 7973906276a8d4b308a19675d5a67b2d6ab3e3b9b6fJim Grosbach MI.eraseFromParent(); 7983906276a8d4b308a19675d5a67b2d6ab3e3b9b6fJim Grosbach return true; 7993906276a8d4b308a19675d5a67b2d6ab3e3b9b6fJim Grosbach } 800f7ab3a84b3e1b5a647ae9456a5edb99d86b35329Tim Northover case ARM::t2MOVCCi16: 8013906276a8d4b308a19675d5a67b2d6ab3e3b9b6fJim Grosbach case ARM::MOVCCi16: { 802f7ab3a84b3e1b5a647ae9456a5edb99d86b35329Tim Northover unsigned NewOpc = AFI->isThumbFunction() ? ARM::t2MOVi16 : ARM::MOVi16; 803f7ab3a84b3e1b5a647ae9456a5edb99d86b35329Tim Northover BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(NewOpc), 8043906276a8d4b308a19675d5a67b2d6ab3e3b9b6fJim Grosbach MI.getOperand(1).getReg()) 8053906276a8d4b308a19675d5a67b2d6ab3e3b9b6fJim Grosbach .addImm(MI.getOperand(2).getImm()) 8063906276a8d4b308a19675d5a67b2d6ab3e3b9b6fJim Grosbach .addImm(MI.getOperand(3).getImm()) // 'pred' 807e1bde51d63f888e0011dfd3b9cfd78b1736d0b5dMatthias Braun .addOperand(MI.getOperand(4)); 8083906276a8d4b308a19675d5a67b2d6ab3e3b9b6fJim Grosbach MI.eraseFromParent(); 8093906276a8d4b308a19675d5a67b2d6ab3e3b9b6fJim Grosbach return true; 8103906276a8d4b308a19675d5a67b2d6ab3e3b9b6fJim Grosbach } 811efeedceb41cc0c5ff7918cad870d5820de84b03dJim Grosbach case ARM::t2MOVCCi: 8123906276a8d4b308a19675d5a67b2d6ab3e3b9b6fJim Grosbach case ARM::MOVCCi: { 813efeedceb41cc0c5ff7918cad870d5820de84b03dJim Grosbach unsigned Opc = AFI->isThumbFunction() ? ARM::t2MOVi : ARM::MOVi; 814efeedceb41cc0c5ff7918cad870d5820de84b03dJim Grosbach BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(Opc), 8153906276a8d4b308a19675d5a67b2d6ab3e3b9b6fJim Grosbach MI.getOperand(1).getReg()) 8163906276a8d4b308a19675d5a67b2d6ab3e3b9b6fJim Grosbach .addImm(MI.getOperand(2).getImm()) 8173906276a8d4b308a19675d5a67b2d6ab3e3b9b6fJim Grosbach .addImm(MI.getOperand(3).getImm()) // 'pred' 818e1bde51d63f888e0011dfd3b9cfd78b1736d0b5dMatthias Braun .addOperand(MI.getOperand(4)) 8193906276a8d4b308a19675d5a67b2d6ab3e3b9b6fJim Grosbach .addReg(0); // 's' bit 820e672ff84308434ad5517a5c6fc36e691893fca96Jim Grosbach 821e672ff84308434ad5517a5c6fc36e691893fca96Jim Grosbach MI.eraseFromParent(); 822e672ff84308434ad5517a5c6fc36e691893fca96Jim Grosbach return true; 823e672ff84308434ad5517a5c6fc36e691893fca96Jim Grosbach } 824f7ab3a84b3e1b5a647ae9456a5edb99d86b35329Tim Northover case ARM::t2MVNCCi: 825e672ff84308434ad5517a5c6fc36e691893fca96Jim Grosbach case ARM::MVNCCi: { 826f7ab3a84b3e1b5a647ae9456a5edb99d86b35329Tim Northover unsigned Opc = AFI->isThumbFunction() ? ARM::t2MVNi : ARM::MVNi; 827f7ab3a84b3e1b5a647ae9456a5edb99d86b35329Tim Northover BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(Opc), 828e672ff84308434ad5517a5c6fc36e691893fca96Jim Grosbach MI.getOperand(1).getReg()) 829e672ff84308434ad5517a5c6fc36e691893fca96Jim Grosbach .addImm(MI.getOperand(2).getImm()) 830e672ff84308434ad5517a5c6fc36e691893fca96Jim Grosbach .addImm(MI.getOperand(3).getImm()) // 'pred' 831e1bde51d63f888e0011dfd3b9cfd78b1736d0b5dMatthias Braun .addOperand(MI.getOperand(4)) 832e672ff84308434ad5517a5c6fc36e691893fca96Jim Grosbach .addReg(0); // 's' bit 833d4a16ad85d991ff12487b40ef248833448047eadJim Grosbach 834d4a16ad85d991ff12487b40ef248833448047eadJim Grosbach MI.eraseFromParent(); 835d4a16ad85d991ff12487b40ef248833448047eadJim Grosbach return true; 836d4a16ad85d991ff12487b40ef248833448047eadJim Grosbach } 837f7ab3a84b3e1b5a647ae9456a5edb99d86b35329Tim Northover case ARM::t2MOVCClsl: 838f7ab3a84b3e1b5a647ae9456a5edb99d86b35329Tim Northover case ARM::t2MOVCClsr: 839f7ab3a84b3e1b5a647ae9456a5edb99d86b35329Tim Northover case ARM::t2MOVCCasr: 840f7ab3a84b3e1b5a647ae9456a5edb99d86b35329Tim Northover case ARM::t2MOVCCror: { 841f7ab3a84b3e1b5a647ae9456a5edb99d86b35329Tim Northover unsigned NewOpc; 842f7ab3a84b3e1b5a647ae9456a5edb99d86b35329Tim Northover switch (Opcode) { 843f7ab3a84b3e1b5a647ae9456a5edb99d86b35329Tim Northover case ARM::t2MOVCClsl: NewOpc = ARM::t2LSLri; break; 844f7ab3a84b3e1b5a647ae9456a5edb99d86b35329Tim Northover case ARM::t2MOVCClsr: NewOpc = ARM::t2LSRri; break; 845f7ab3a84b3e1b5a647ae9456a5edb99d86b35329Tim Northover case ARM::t2MOVCCasr: NewOpc = ARM::t2ASRri; break; 846f7ab3a84b3e1b5a647ae9456a5edb99d86b35329Tim Northover case ARM::t2MOVCCror: NewOpc = ARM::t2RORri; break; 847f7ab3a84b3e1b5a647ae9456a5edb99d86b35329Tim Northover default: llvm_unreachable("unexpeced conditional move"); 848f7ab3a84b3e1b5a647ae9456a5edb99d86b35329Tim Northover } 849f7ab3a84b3e1b5a647ae9456a5edb99d86b35329Tim Northover BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(NewOpc), 850f7ab3a84b3e1b5a647ae9456a5edb99d86b35329Tim Northover MI.getOperand(1).getReg()) 851e1bde51d63f888e0011dfd3b9cfd78b1736d0b5dMatthias Braun .addOperand(MI.getOperand(2)) 852f7ab3a84b3e1b5a647ae9456a5edb99d86b35329Tim Northover .addImm(MI.getOperand(3).getImm()) 853f7ab3a84b3e1b5a647ae9456a5edb99d86b35329Tim Northover .addImm(MI.getOperand(4).getImm()) // 'pred' 854e1bde51d63f888e0011dfd3b9cfd78b1736d0b5dMatthias Braun .addOperand(MI.getOperand(5)) 855f7ab3a84b3e1b5a647ae9456a5edb99d86b35329Tim Northover .addReg(0); // 's' bit 856f7ab3a84b3e1b5a647ae9456a5edb99d86b35329Tim Northover MI.eraseFromParent(); 857f7ab3a84b3e1b5a647ae9456a5edb99d86b35329Tim Northover return true; 858f7ab3a84b3e1b5a647ae9456a5edb99d86b35329Tim Northover } 859e7bd51980a1341fb60322e5922cfcc0c9b92b165Chad Rosier case ARM::Int_eh_sjlj_dispatchsetup: { 860e4ad387a5a88dae20f0f7578e55170bbc8eee2a9Jim Grosbach MachineFunction &MF = *MI.getParent()->getParent(); 861e4ad387a5a88dae20f0f7578e55170bbc8eee2a9Jim Grosbach const ARMBaseInstrInfo *AII = 862e4ad387a5a88dae20f0f7578e55170bbc8eee2a9Jim Grosbach static_cast<const ARMBaseInstrInfo*>(TII); 863e4ad387a5a88dae20f0f7578e55170bbc8eee2a9Jim Grosbach const ARMBaseRegisterInfo &RI = AII->getRegisterInfo(); 864e4ad387a5a88dae20f0f7578e55170bbc8eee2a9Jim Grosbach // For functions using a base pointer, we rematerialize it (via the frame 865e4ad387a5a88dae20f0f7578e55170bbc8eee2a9Jim Grosbach // pointer) here since eh.sjlj.setjmp and eh.sjlj.longjmp don't do it 866e4ad387a5a88dae20f0f7578e55170bbc8eee2a9Jim Grosbach // for us. Otherwise, expand to nothing. 867e4ad387a5a88dae20f0f7578e55170bbc8eee2a9Jim Grosbach if (RI.hasBasePointer(MF)) { 868e4ad387a5a88dae20f0f7578e55170bbc8eee2a9Jim Grosbach int32_t NumBytes = AFI->getFramePtrSpillOffset(); 869e4ad387a5a88dae20f0f7578e55170bbc8eee2a9Jim Grosbach unsigned FramePtr = RI.getFrameRegister(MF); 87016c29b5f285f375be53dabaa73e3e91107485fe4Anton Korobeynikov assert(MF.getTarget().getFrameLowering()->hasFP(MF) && 8717920d96964d707a3af85332c98d95b2fabc3d5c9Benjamin Kramer "base pointer without frame pointer?"); 872e4ad387a5a88dae20f0f7578e55170bbc8eee2a9Jim Grosbach 873e4ad387a5a88dae20f0f7578e55170bbc8eee2a9Jim Grosbach if (AFI->isThumb2Function()) { 874c89c744b69cecac576317a98322fd295e36e9886Craig Topper emitT2RegPlusImmediate(MBB, MBBI, MI.getDebugLoc(), ARM::R6, 875c89c744b69cecac576317a98322fd295e36e9886Craig Topper FramePtr, -NumBytes, ARMCC::AL, 0, *TII); 876e4ad387a5a88dae20f0f7578e55170bbc8eee2a9Jim Grosbach } else if (AFI->isThumbFunction()) { 877c89c744b69cecac576317a98322fd295e36e9886Craig Topper emitThumbRegPlusImmediate(MBB, MBBI, MI.getDebugLoc(), ARM::R6, 878c89c744b69cecac576317a98322fd295e36e9886Craig Topper FramePtr, -NumBytes, *TII, RI); 879e4ad387a5a88dae20f0f7578e55170bbc8eee2a9Jim Grosbach } else { 880c89c744b69cecac576317a98322fd295e36e9886Craig Topper emitARMRegPlusImmediate(MBB, MBBI, MI.getDebugLoc(), ARM::R6, 881c89c744b69cecac576317a98322fd295e36e9886Craig Topper FramePtr, -NumBytes, ARMCC::AL, 0, 882c89c744b69cecac576317a98322fd295e36e9886Craig Topper *TII); 883e4ad387a5a88dae20f0f7578e55170bbc8eee2a9Jim Grosbach } 8848b95c3ebfbd492c2ac863df93e40c11fc2e914fdJim Grosbach // If there's dynamic realignment, adjust for it. 885b8e67fc92b0a508e3782b782baa98a6d56d5d7eaJim Grosbach if (RI.needsStackRealignment(MF)) { 8868b95c3ebfbd492c2ac863df93e40c11fc2e914fdJim Grosbach MachineFrameInfo *MFI = MF.getFrameInfo(); 8878b95c3ebfbd492c2ac863df93e40c11fc2e914fdJim Grosbach unsigned MaxAlign = MFI->getMaxAlignment(); 8888b95c3ebfbd492c2ac863df93e40c11fc2e914fdJim Grosbach assert (!AFI->isThumb1OnlyFunction()); 8898b95c3ebfbd492c2ac863df93e40c11fc2e914fdJim Grosbach // Emit bic r6, r6, MaxAlign 8908b95c3ebfbd492c2ac863df93e40c11fc2e914fdJim Grosbach unsigned bicOpc = AFI->isThumbFunction() ? 8918b95c3ebfbd492c2ac863df93e40c11fc2e914fdJim Grosbach ARM::t2BICri : ARM::BICri; 8928b95c3ebfbd492c2ac863df93e40c11fc2e914fdJim Grosbach AddDefaultCC(AddDefaultPred(BuildMI(MBB, MBBI, MI.getDebugLoc(), 8938b95c3ebfbd492c2ac863df93e40c11fc2e914fdJim Grosbach TII->get(bicOpc), ARM::R6) 8948b95c3ebfbd492c2ac863df93e40c11fc2e914fdJim Grosbach .addReg(ARM::R6, RegState::Kill) 8958b95c3ebfbd492c2ac863df93e40c11fc2e914fdJim Grosbach .addImm(MaxAlign-1))); 8968b95c3ebfbd492c2ac863df93e40c11fc2e914fdJim Grosbach } 897e4ad387a5a88dae20f0f7578e55170bbc8eee2a9Jim Grosbach 898e4ad387a5a88dae20f0f7578e55170bbc8eee2a9Jim Grosbach } 899e4ad387a5a88dae20f0f7578e55170bbc8eee2a9Jim Grosbach MI.eraseFromParent(); 9009fe2009956fc40f3aea46fb3c38dcfb61c4aca46Evan Cheng return true; 901e4ad387a5a88dae20f0f7578e55170bbc8eee2a9Jim Grosbach } 902e4ad387a5a88dae20f0f7578e55170bbc8eee2a9Jim Grosbach 9037032f922b12746b73d6316578b0aea2d812b07b4Jim Grosbach case ARM::MOVsrl_flag: 9047032f922b12746b73d6316578b0aea2d812b07b4Jim Grosbach case ARM::MOVsra_flag: { 9053f4f420ab7acb10221ba971543a7eed5489fb626Robert Wilhelm // These are just fancy MOVs instructions. 906152d4a4bb6b75de740b4b8a9f48abb9069d50c17Owen Anderson AddDefaultPred(BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(ARM::MOVsi), 907dbbd99faf1d661f03a9dfc1551d7537c34d64beeDuncan Sands MI.getOperand(0).getReg()) 9089fe2009956fc40f3aea46fb3c38dcfb61c4aca46Evan Cheng .addOperand(MI.getOperand(1)) 909aa4cc1a6d75f621cbc5eb1db692068db072fbeccJim Grosbach .addImm(ARM_AM::getSORegOpc((Opcode == ARM::MOVsrl_flag ? 910aa4cc1a6d75f621cbc5eb1db692068db072fbeccJim Grosbach ARM_AM::lsr : ARM_AM::asr), 911aa4cc1a6d75f621cbc5eb1db692068db072fbeccJim Grosbach 1))) 9129fe2009956fc40f3aea46fb3c38dcfb61c4aca46Evan Cheng .addReg(ARM::CPSR, RegState::Define); 9137032f922b12746b73d6316578b0aea2d812b07b4Jim Grosbach MI.eraseFromParent(); 9149fe2009956fc40f3aea46fb3c38dcfb61c4aca46Evan Cheng return true; 9157032f922b12746b73d6316578b0aea2d812b07b4Jim Grosbach } 9167032f922b12746b73d6316578b0aea2d812b07b4Jim Grosbach case ARM::RRX: { 9177032f922b12746b73d6316578b0aea2d812b07b4Jim Grosbach // This encodes as "MOVs Rd, Rm, rrx 9187032f922b12746b73d6316578b0aea2d812b07b4Jim Grosbach MachineInstrBuilder MIB = 9198e0c7697fd9b9354856074efc06eea9f6d80015cJim Grosbach AddDefaultPred(BuildMI(MBB, MBBI, MI.getDebugLoc(),TII->get(ARM::MOVsi), 9207032f922b12746b73d6316578b0aea2d812b07b4Jim Grosbach MI.getOperand(0).getReg()) 9219fe2009956fc40f3aea46fb3c38dcfb61c4aca46Evan Cheng .addOperand(MI.getOperand(1)) 9229fe2009956fc40f3aea46fb3c38dcfb61c4aca46Evan Cheng .addImm(ARM_AM::getSORegOpc(ARM_AM::rrx, 0))) 9237032f922b12746b73d6316578b0aea2d812b07b4Jim Grosbach .addReg(0); 9247032f922b12746b73d6316578b0aea2d812b07b4Jim Grosbach TransferImpOps(MI, MIB, MIB); 9257032f922b12746b73d6316578b0aea2d812b07b4Jim Grosbach MI.eraseFromParent(); 9269fe2009956fc40f3aea46fb3c38dcfb61c4aca46Evan Cheng return true; 9277032f922b12746b73d6316578b0aea2d812b07b4Jim Grosbach } 928ff97eb0cf4394090570feaa327d1237ba4b935e2Jim Grosbach case ARM::tTPsoft: 929a0871e79270b2a05f93c9df73bbe24c587faa94eJason W Kim case ARM::TPsoft: { 930cd81d94322a39503e4a3e87b6ee03d4fcb3465fbStephen Hines MachineInstrBuilder MIB; 931cd81d94322a39503e4a3e87b6ee03d4fcb3465fbStephen Hines if (Opcode == ARM::tTPsoft) 932cd81d94322a39503e4a3e87b6ee03d4fcb3465fbStephen Hines MIB = BuildMI(MBB, MBBI, MI.getDebugLoc(), 933cd81d94322a39503e4a3e87b6ee03d4fcb3465fbStephen Hines TII->get( ARM::tBL)) 934cd81d94322a39503e4a3e87b6ee03d4fcb3465fbStephen Hines .addImm((unsigned)ARMCC::AL).addReg(0) 935cd81d94322a39503e4a3e87b6ee03d4fcb3465fbStephen Hines .addExternalSymbol("__aeabi_read_tp", 0); 936cd81d94322a39503e4a3e87b6ee03d4fcb3465fbStephen Hines else 937cd81d94322a39503e4a3e87b6ee03d4fcb3465fbStephen Hines MIB = BuildMI(MBB, MBBI, MI.getDebugLoc(), 938cd81d94322a39503e4a3e87b6ee03d4fcb3465fbStephen Hines TII->get( ARM::BL)) 939cd81d94322a39503e4a3e87b6ee03d4fcb3465fbStephen Hines .addExternalSymbol("__aeabi_read_tp", 0); 940a0871e79270b2a05f93c9df73bbe24c587faa94eJason W Kim 941d7d030a44796adc73a6eaa939cd17e52047734c1Chris Lattner MIB->setMemRefs(MI.memoperands_begin(), MI.memoperands_end()); 942a0871e79270b2a05f93c9df73bbe24c587faa94eJason W Kim TransferImpOps(MI, MIB, MIB); 943a0871e79270b2a05f93c9df73bbe24c587faa94eJason W Kim MI.eraseFromParent(); 9449fe2009956fc40f3aea46fb3c38dcfb61c4aca46Evan Cheng return true; 9452fe813af23e682b418ecd477144fe070be325419Bill Wendling } 946bd916c54b7989ddbab373c61eb1ed2556ca44d27Bob Wilson case ARM::tLDRpci_pic: 947b9803a8fa65f043c96612fa9c5aeeee12739db2bEvan Cheng case ARM::t2LDRpci_pic: { 948b9803a8fa65f043c96612fa9c5aeeee12739db2bEvan Cheng unsigned NewLdOpc = (Opcode == ARM::tLDRpci_pic) 949971b83b67a9812556cdb97bb58aa96fb37af458dOwen Anderson ? ARM::tLDRpci : ARM::t2LDRpci; 950b9803a8fa65f043c96612fa9c5aeeee12739db2bEvan Cheng unsigned DstReg = MI.getOperand(0).getReg(); 951431300797b84600fc9b4eb8ca283277d3e0674ebEvan Cheng bool DstIsDead = MI.getOperand(0).isDead(); 952431300797b84600fc9b4eb8ca283277d3e0674ebEvan Cheng MachineInstrBuilder MIB1 = 953971b83b67a9812556cdb97bb58aa96fb37af458dOwen Anderson AddDefaultPred(BuildMI(MBB, MBBI, MI.getDebugLoc(), 954971b83b67a9812556cdb97bb58aa96fb37af458dOwen Anderson TII->get(NewLdOpc), DstReg) 955971b83b67a9812556cdb97bb58aa96fb37af458dOwen Anderson .addOperand(MI.getOperand(1))); 956d7d030a44796adc73a6eaa939cd17e52047734c1Chris Lattner MIB1->setMemRefs(MI.memoperands_begin(), MI.memoperands_end()); 957431300797b84600fc9b4eb8ca283277d3e0674ebEvan Cheng MachineInstrBuilder MIB2 = BuildMI(MBB, MBBI, MI.getDebugLoc(), 958431300797b84600fc9b4eb8ca283277d3e0674ebEvan Cheng TII->get(ARM::tPICADD)) 95901b35c25deee3d4cab339e620c12c721e627d609Bob Wilson .addReg(DstReg, RegState::Define | getDeadRegState(DstIsDead)) 960431300797b84600fc9b4eb8ca283277d3e0674ebEvan Cheng .addReg(DstReg) 961431300797b84600fc9b4eb8ca283277d3e0674ebEvan Cheng .addOperand(MI.getOperand(2)); 962431300797b84600fc9b4eb8ca283277d3e0674ebEvan Cheng TransferImpOps(MI, MIB1, MIB2); 963b9803a8fa65f043c96612fa9c5aeeee12739db2bEvan Cheng MI.eraseFromParent(); 9649fe2009956fc40f3aea46fb3c38dcfb61c4aca46Evan Cheng return true; 965b9803a8fa65f043c96612fa9c5aeeee12739db2bEvan Cheng } 966431300797b84600fc9b4eb8ca283277d3e0674ebEvan Cheng 96736b56886974eae4f9c5ebc96befd3e7bfe5de338Stephen Hines case ARM::LDRLIT_ga_abs: 96836b56886974eae4f9c5ebc96befd3e7bfe5de338Stephen Hines case ARM::LDRLIT_ga_pcrel: 96936b56886974eae4f9c5ebc96befd3e7bfe5de338Stephen Hines case ARM::LDRLIT_ga_pcrel_ldr: 97036b56886974eae4f9c5ebc96befd3e7bfe5de338Stephen Hines case ARM::tLDRLIT_ga_abs: 97136b56886974eae4f9c5ebc96befd3e7bfe5de338Stephen Hines case ARM::tLDRLIT_ga_pcrel: { 97236b56886974eae4f9c5ebc96befd3e7bfe5de338Stephen Hines unsigned DstReg = MI.getOperand(0).getReg(); 97336b56886974eae4f9c5ebc96befd3e7bfe5de338Stephen Hines bool DstIsDead = MI.getOperand(0).isDead(); 97436b56886974eae4f9c5ebc96befd3e7bfe5de338Stephen Hines const MachineOperand &MO1 = MI.getOperand(1); 97536b56886974eae4f9c5ebc96befd3e7bfe5de338Stephen Hines const GlobalValue *GV = MO1.getGlobal(); 97636b56886974eae4f9c5ebc96befd3e7bfe5de338Stephen Hines bool IsARM = 97736b56886974eae4f9c5ebc96befd3e7bfe5de338Stephen Hines Opcode != ARM::tLDRLIT_ga_pcrel && Opcode != ARM::tLDRLIT_ga_abs; 97836b56886974eae4f9c5ebc96befd3e7bfe5de338Stephen Hines bool IsPIC = 97936b56886974eae4f9c5ebc96befd3e7bfe5de338Stephen Hines Opcode != ARM::LDRLIT_ga_abs && Opcode != ARM::tLDRLIT_ga_abs; 98036b56886974eae4f9c5ebc96befd3e7bfe5de338Stephen Hines unsigned LDRLITOpc = IsARM ? ARM::LDRi12 : ARM::tLDRpci; 98136b56886974eae4f9c5ebc96befd3e7bfe5de338Stephen Hines unsigned PICAddOpc = 98236b56886974eae4f9c5ebc96befd3e7bfe5de338Stephen Hines IsARM 98336b56886974eae4f9c5ebc96befd3e7bfe5de338Stephen Hines ? (Opcode == ARM::LDRLIT_ga_pcrel_ldr ? ARM::PICADD : ARM::PICLDR) 98436b56886974eae4f9c5ebc96befd3e7bfe5de338Stephen Hines : ARM::tPICADD; 98536b56886974eae4f9c5ebc96befd3e7bfe5de338Stephen Hines 98636b56886974eae4f9c5ebc96befd3e7bfe5de338Stephen Hines // We need a new const-pool entry to load from. 98736b56886974eae4f9c5ebc96befd3e7bfe5de338Stephen Hines MachineConstantPool *MCP = MBB.getParent()->getConstantPool(); 98836b56886974eae4f9c5ebc96befd3e7bfe5de338Stephen Hines unsigned ARMPCLabelIndex = 0; 98936b56886974eae4f9c5ebc96befd3e7bfe5de338Stephen Hines MachineConstantPoolValue *CPV; 99036b56886974eae4f9c5ebc96befd3e7bfe5de338Stephen Hines 99136b56886974eae4f9c5ebc96befd3e7bfe5de338Stephen Hines if (IsPIC) { 99236b56886974eae4f9c5ebc96befd3e7bfe5de338Stephen Hines unsigned PCAdj = IsARM ? 8 : 4; 99336b56886974eae4f9c5ebc96befd3e7bfe5de338Stephen Hines ARMPCLabelIndex = AFI->createPICLabelUId(); 99436b56886974eae4f9c5ebc96befd3e7bfe5de338Stephen Hines CPV = ARMConstantPoolConstant::Create(GV, ARMPCLabelIndex, 99536b56886974eae4f9c5ebc96befd3e7bfe5de338Stephen Hines ARMCP::CPValue, PCAdj); 99636b56886974eae4f9c5ebc96befd3e7bfe5de338Stephen Hines } else 99736b56886974eae4f9c5ebc96befd3e7bfe5de338Stephen Hines CPV = ARMConstantPoolConstant::Create(GV, ARMCP::no_modifier); 99836b56886974eae4f9c5ebc96befd3e7bfe5de338Stephen Hines 99936b56886974eae4f9c5ebc96befd3e7bfe5de338Stephen Hines MachineInstrBuilder MIB = 100036b56886974eae4f9c5ebc96befd3e7bfe5de338Stephen Hines BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(LDRLITOpc), DstReg) 100136b56886974eae4f9c5ebc96befd3e7bfe5de338Stephen Hines .addConstantPoolIndex(MCP->getConstantPoolIndex(CPV, 4)); 100236b56886974eae4f9c5ebc96befd3e7bfe5de338Stephen Hines if (IsARM) 100336b56886974eae4f9c5ebc96befd3e7bfe5de338Stephen Hines MIB.addImm(0); 100436b56886974eae4f9c5ebc96befd3e7bfe5de338Stephen Hines AddDefaultPred(MIB); 100536b56886974eae4f9c5ebc96befd3e7bfe5de338Stephen Hines 100636b56886974eae4f9c5ebc96befd3e7bfe5de338Stephen Hines if (IsPIC) { 100736b56886974eae4f9c5ebc96befd3e7bfe5de338Stephen Hines MachineInstrBuilder MIB = 100836b56886974eae4f9c5ebc96befd3e7bfe5de338Stephen Hines BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(PICAddOpc)) 100936b56886974eae4f9c5ebc96befd3e7bfe5de338Stephen Hines .addReg(DstReg, RegState::Define | getDeadRegState(DstIsDead)) 101036b56886974eae4f9c5ebc96befd3e7bfe5de338Stephen Hines .addReg(DstReg) 101136b56886974eae4f9c5ebc96befd3e7bfe5de338Stephen Hines .addImm(ARMPCLabelIndex); 101236b56886974eae4f9c5ebc96befd3e7bfe5de338Stephen Hines 101336b56886974eae4f9c5ebc96befd3e7bfe5de338Stephen Hines if (IsARM) 101436b56886974eae4f9c5ebc96befd3e7bfe5de338Stephen Hines AddDefaultPred(MIB); 101536b56886974eae4f9c5ebc96befd3e7bfe5de338Stephen Hines } 101636b56886974eae4f9c5ebc96befd3e7bfe5de338Stephen Hines 101736b56886974eae4f9c5ebc96befd3e7bfe5de338Stephen Hines MI.eraseFromParent(); 101836b56886974eae4f9c5ebc96befd3e7bfe5de338Stephen Hines return true; 101936b56886974eae4f9c5ebc96befd3e7bfe5de338Stephen Hines } 102053519f015e3e84e9f57b677cc8724805a6009b73Evan Cheng case ARM::MOV_ga_pcrel: 102153519f015e3e84e9f57b677cc8724805a6009b73Evan Cheng case ARM::MOV_ga_pcrel_ldr: 102253519f015e3e84e9f57b677cc8724805a6009b73Evan Cheng case ARM::t2MOV_ga_pcrel: { 102353519f015e3e84e9f57b677cc8724805a6009b73Evan Cheng // Expand into movw + movw. Also "add pc" / ldr [pc] in PIC mode. 10249fe2009956fc40f3aea46fb3c38dcfb61c4aca46Evan Cheng unsigned LabelId = AFI->createPICLabelUId(); 1025b9803a8fa65f043c96612fa9c5aeeee12739db2bEvan Cheng unsigned DstReg = MI.getOperand(0).getReg(); 1026431300797b84600fc9b4eb8ca283277d3e0674ebEvan Cheng bool DstIsDead = MI.getOperand(0).isDead(); 10279fe2009956fc40f3aea46fb3c38dcfb61c4aca46Evan Cheng const MachineOperand &MO1 = MI.getOperand(1); 10289fe2009956fc40f3aea46fb3c38dcfb61c4aca46Evan Cheng const GlobalValue *GV = MO1.getGlobal(); 10299fe2009956fc40f3aea46fb3c38dcfb61c4aca46Evan Cheng unsigned TF = MO1.getTargetFlags(); 103036b56886974eae4f9c5ebc96befd3e7bfe5de338Stephen Hines bool isARM = Opcode != ARM::t2MOV_ga_pcrel; 103153519f015e3e84e9f57b677cc8724805a6009b73Evan Cheng unsigned LO16Opc = isARM ? ARM::MOVi16_ga_pcrel : ARM::t2MOVi16_ga_pcrel; 1032aa4cc1a6d75f621cbc5eb1db692068db072fbeccJim Grosbach unsigned HI16Opc = isARM ? ARM::MOVTi16_ga_pcrel :ARM::t2MOVTi16_ga_pcrel; 103336b56886974eae4f9c5ebc96befd3e7bfe5de338Stephen Hines unsigned LO16TF = TF | ARMII::MO_LO16; 103436b56886974eae4f9c5ebc96befd3e7bfe5de338Stephen Hines unsigned HI16TF = TF | ARMII::MO_HI16; 10359fe2009956fc40f3aea46fb3c38dcfb61c4aca46Evan Cheng unsigned PICAddOpc = isARM 103653519f015e3e84e9f57b677cc8724805a6009b73Evan Cheng ? (Opcode == ARM::MOV_ga_pcrel_ldr ? ARM::PICLDR : ARM::PICADD) 10379fe2009956fc40f3aea46fb3c38dcfb61c4aca46Evan Cheng : ARM::tPICADD; 10389fe2009956fc40f3aea46fb3c38dcfb61c4aca46Evan Cheng MachineInstrBuilder MIB1 = BuildMI(MBB, MBBI, MI.getDebugLoc(), 10399fe2009956fc40f3aea46fb3c38dcfb61c4aca46Evan Cheng TII->get(LO16Opc), DstReg) 104053519f015e3e84e9f57b677cc8724805a6009b73Evan Cheng .addGlobalAddress(GV, MO1.getOffset(), TF | LO16TF) 10419fe2009956fc40f3aea46fb3c38dcfb61c4aca46Evan Cheng .addImm(LabelId); 104236b56886974eae4f9c5ebc96befd3e7bfe5de338Stephen Hines 104336b56886974eae4f9c5ebc96befd3e7bfe5de338Stephen Hines BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(HI16Opc), DstReg) 10449fe2009956fc40f3aea46fb3c38dcfb61c4aca46Evan Cheng .addReg(DstReg) 104553519f015e3e84e9f57b677cc8724805a6009b73Evan Cheng .addGlobalAddress(GV, MO1.getOffset(), TF | HI16TF) 10469fe2009956fc40f3aea46fb3c38dcfb61c4aca46Evan Cheng .addImm(LabelId); 104753519f015e3e84e9f57b677cc8724805a6009b73Evan Cheng 104853519f015e3e84e9f57b677cc8724805a6009b73Evan Cheng MachineInstrBuilder MIB3 = BuildMI(MBB, MBBI, MI.getDebugLoc(), 10499fe2009956fc40f3aea46fb3c38dcfb61c4aca46Evan Cheng TII->get(PICAddOpc)) 105001b35c25deee3d4cab339e620c12c721e627d609Bob Wilson .addReg(DstReg, RegState::Define | getDeadRegState(DstIsDead)) 10519fe2009956fc40f3aea46fb3c38dcfb61c4aca46Evan Cheng .addReg(DstReg).addImm(LabelId); 10529fe2009956fc40f3aea46fb3c38dcfb61c4aca46Evan Cheng if (isARM) { 105353519f015e3e84e9f57b677cc8724805a6009b73Evan Cheng AddDefaultPred(MIB3); 105453519f015e3e84e9f57b677cc8724805a6009b73Evan Cheng if (Opcode == ARM::MOV_ga_pcrel_ldr) 10556e6269a976baee45717265dbd12996367df6a201Jakob Stoklund Olesen MIB3->setMemRefs(MI.memoperands_begin(), MI.memoperands_end()); 10565de5d4b6d0eb3fd379fa571d82f6fa764460b3b8Evan Cheng } 105753519f015e3e84e9f57b677cc8724805a6009b73Evan Cheng TransferImpOps(MI, MIB1, MIB3); 1058b9803a8fa65f043c96612fa9c5aeeee12739db2bEvan Cheng MI.eraseFromParent(); 10599fe2009956fc40f3aea46fb3c38dcfb61c4aca46Evan Cheng return true; 1060d929f7773812535271ae6969331f8164c1f7f3b2Evan Cheng } 1061d929f7773812535271ae6969331f8164c1f7f3b2Evan Cheng 10629fe2009956fc40f3aea46fb3c38dcfb61c4aca46Evan Cheng case ARM::MOVi32imm: 10639fe2009956fc40f3aea46fb3c38dcfb61c4aca46Evan Cheng case ARM::MOVCCi32imm: 10649fe2009956fc40f3aea46fb3c38dcfb61c4aca46Evan Cheng case ARM::t2MOVi32imm: 10659fe2009956fc40f3aea46fb3c38dcfb61c4aca46Evan Cheng case ARM::t2MOVCCi32imm: 10669fe2009956fc40f3aea46fb3c38dcfb61c4aca46Evan Cheng ExpandMOV32BitImm(MBB, MBBI); 10679fe2009956fc40f3aea46fb3c38dcfb61c4aca46Evan Cheng return true; 10689fe2009956fc40f3aea46fb3c38dcfb61c4aca46Evan Cheng 1069bba9390fc6c0d536172c6bb4a9c93db557c1aff4Tim Northover case ARM::SUBS_PC_LR: { 1070bba9390fc6c0d536172c6bb4a9c93db557c1aff4Tim Northover MachineInstrBuilder MIB = 1071bba9390fc6c0d536172c6bb4a9c93db557c1aff4Tim Northover BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(ARM::SUBri), ARM::PC) 1072bba9390fc6c0d536172c6bb4a9c93db557c1aff4Tim Northover .addReg(ARM::LR) 1073bba9390fc6c0d536172c6bb4a9c93db557c1aff4Tim Northover .addOperand(MI.getOperand(0)) 1074bba9390fc6c0d536172c6bb4a9c93db557c1aff4Tim Northover .addOperand(MI.getOperand(1)) 1075bba9390fc6c0d536172c6bb4a9c93db557c1aff4Tim Northover .addOperand(MI.getOperand(2)) 1076bba9390fc6c0d536172c6bb4a9c93db557c1aff4Tim Northover .addReg(ARM::CPSR, RegState::Undef); 1077bba9390fc6c0d536172c6bb4a9c93db557c1aff4Tim Northover TransferImpOps(MI, MIB, MIB); 1078bba9390fc6c0d536172c6bb4a9c93db557c1aff4Tim Northover MI.eraseFromParent(); 1079bba9390fc6c0d536172c6bb4a9c93db557c1aff4Tim Northover return true; 1080bba9390fc6c0d536172c6bb4a9c93db557c1aff4Tim Northover } 1081848b0c39b11801614c47e460248b60e8d40eb257Owen Anderson case ARM::VLDMQIA: { 1082848b0c39b11801614c47e460248b60e8d40eb257Owen Anderson unsigned NewOpc = ARM::VLDMDIA; 10839d4ebc0eb80c770aab5b51ca459748a6ac8f1699Bob Wilson MachineInstrBuilder MIB = 108473fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(NewOpc)); 10859d4ebc0eb80c770aab5b51ca459748a6ac8f1699Bob Wilson unsigned OpIdx = 0; 108673fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling 10879d4ebc0eb80c770aab5b51ca459748a6ac8f1699Bob Wilson // Grab the Q register destination. 10889d4ebc0eb80c770aab5b51ca459748a6ac8f1699Bob Wilson bool DstIsDead = MI.getOperand(OpIdx).isDead(); 10899d4ebc0eb80c770aab5b51ca459748a6ac8f1699Bob Wilson unsigned DstReg = MI.getOperand(OpIdx++).getReg(); 109073fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling 109173fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling // Copy the source register. 10929d4ebc0eb80c770aab5b51ca459748a6ac8f1699Bob Wilson MIB.addOperand(MI.getOperand(OpIdx++)); 109373fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling 10949d4ebc0eb80c770aab5b51ca459748a6ac8f1699Bob Wilson // Copy the predicate operands. 10959d4ebc0eb80c770aab5b51ca459748a6ac8f1699Bob Wilson MIB.addOperand(MI.getOperand(OpIdx++)); 10969d4ebc0eb80c770aab5b51ca459748a6ac8f1699Bob Wilson MIB.addOperand(MI.getOperand(OpIdx++)); 109773fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling 10989d4ebc0eb80c770aab5b51ca459748a6ac8f1699Bob Wilson // Add the destination operands (D subregs). 10999d4ebc0eb80c770aab5b51ca459748a6ac8f1699Bob Wilson unsigned D0 = TRI->getSubReg(DstReg, ARM::dsub_0); 11009d4ebc0eb80c770aab5b51ca459748a6ac8f1699Bob Wilson unsigned D1 = TRI->getSubReg(DstReg, ARM::dsub_1); 11019d4ebc0eb80c770aab5b51ca459748a6ac8f1699Bob Wilson MIB.addReg(D0, RegState::Define | getDeadRegState(DstIsDead)) 11029d4ebc0eb80c770aab5b51ca459748a6ac8f1699Bob Wilson .addReg(D1, RegState::Define | getDeadRegState(DstIsDead)); 110373fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling 11049d4ebc0eb80c770aab5b51ca459748a6ac8f1699Bob Wilson // Add an implicit def for the super-register. 11059d4ebc0eb80c770aab5b51ca459748a6ac8f1699Bob Wilson MIB.addReg(DstReg, RegState::ImplicitDefine | getDeadRegState(DstIsDead)); 11069d4ebc0eb80c770aab5b51ca459748a6ac8f1699Bob Wilson TransferImpOps(MI, MIB, MIB); 11072027379985f1cbb965be808adad5b819a66dd97fJakob Stoklund Olesen MIB.setMemRefs(MI.memoperands_begin(), MI.memoperands_end()); 11089d4ebc0eb80c770aab5b51ca459748a6ac8f1699Bob Wilson MI.eraseFromParent(); 11099fe2009956fc40f3aea46fb3c38dcfb61c4aca46Evan Cheng return true; 11109d4ebc0eb80c770aab5b51ca459748a6ac8f1699Bob Wilson } 11119d4ebc0eb80c770aab5b51ca459748a6ac8f1699Bob Wilson 1112848b0c39b11801614c47e460248b60e8d40eb257Owen Anderson case ARM::VSTMQIA: { 1113848b0c39b11801614c47e460248b60e8d40eb257Owen Anderson unsigned NewOpc = ARM::VSTMDIA; 11149d4ebc0eb80c770aab5b51ca459748a6ac8f1699Bob Wilson MachineInstrBuilder MIB = 111573fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(NewOpc)); 11169d4ebc0eb80c770aab5b51ca459748a6ac8f1699Bob Wilson unsigned OpIdx = 0; 111773fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling 11189d4ebc0eb80c770aab5b51ca459748a6ac8f1699Bob Wilson // Grab the Q register source. 11199d4ebc0eb80c770aab5b51ca459748a6ac8f1699Bob Wilson bool SrcIsKill = MI.getOperand(OpIdx).isKill(); 11209d4ebc0eb80c770aab5b51ca459748a6ac8f1699Bob Wilson unsigned SrcReg = MI.getOperand(OpIdx++).getReg(); 112173fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling 112273fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling // Copy the destination register. 11239d4ebc0eb80c770aab5b51ca459748a6ac8f1699Bob Wilson MIB.addOperand(MI.getOperand(OpIdx++)); 112473fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling 11259d4ebc0eb80c770aab5b51ca459748a6ac8f1699Bob Wilson // Copy the predicate operands. 11269d4ebc0eb80c770aab5b51ca459748a6ac8f1699Bob Wilson MIB.addOperand(MI.getOperand(OpIdx++)); 11279d4ebc0eb80c770aab5b51ca459748a6ac8f1699Bob Wilson MIB.addOperand(MI.getOperand(OpIdx++)); 112873fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling 11299d4ebc0eb80c770aab5b51ca459748a6ac8f1699Bob Wilson // Add the source operands (D subregs). 11309d4ebc0eb80c770aab5b51ca459748a6ac8f1699Bob Wilson unsigned D0 = TRI->getSubReg(SrcReg, ARM::dsub_0); 11319d4ebc0eb80c770aab5b51ca459748a6ac8f1699Bob Wilson unsigned D1 = TRI->getSubReg(SrcReg, ARM::dsub_1); 11329d4ebc0eb80c770aab5b51ca459748a6ac8f1699Bob Wilson MIB.addReg(D0).addReg(D1); 113373fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling 1134d7d030a44796adc73a6eaa939cd17e52047734c1Chris Lattner if (SrcIsKill) // Add an implicit kill for the Q register. 1135d7d030a44796adc73a6eaa939cd17e52047734c1Chris Lattner MIB->addRegisterKilled(SrcReg, TRI, true); 113673fe34a3ee866867d5028f4a9afa2c3b8efebcbaBill Wendling 11379d4ebc0eb80c770aab5b51ca459748a6ac8f1699Bob Wilson TransferImpOps(MI, MIB, MIB); 11382027379985f1cbb965be808adad5b819a66dd97fJakob Stoklund Olesen MIB.setMemRefs(MI.memoperands_begin(), MI.memoperands_end()); 11399d4ebc0eb80c770aab5b51ca459748a6ac8f1699Bob Wilson MI.eraseFromParent(); 11409fe2009956fc40f3aea46fb3c38dcfb61c4aca46Evan Cheng return true; 11419d4ebc0eb80c770aab5b51ca459748a6ac8f1699Bob Wilson } 11429d4ebc0eb80c770aab5b51ca459748a6ac8f1699Bob Wilson 1143ffde080ae615906545eb33dab30e7bc47c2ac838Bob Wilson case ARM::VLD2q8Pseudo: 1144ffde080ae615906545eb33dab30e7bc47c2ac838Bob Wilson case ARM::VLD2q16Pseudo: 1145ffde080ae615906545eb33dab30e7bc47c2ac838Bob Wilson case ARM::VLD2q32Pseudo: 1146a4e3c7fc4ba2d55695b0484480685698132eba20Jim Grosbach case ARM::VLD2q8PseudoWB_fixed: 1147a4e3c7fc4ba2d55695b0484480685698132eba20Jim Grosbach case ARM::VLD2q16PseudoWB_fixed: 1148a4e3c7fc4ba2d55695b0484480685698132eba20Jim Grosbach case ARM::VLD2q32PseudoWB_fixed: 1149a4e3c7fc4ba2d55695b0484480685698132eba20Jim Grosbach case ARM::VLD2q8PseudoWB_register: 1150a4e3c7fc4ba2d55695b0484480685698132eba20Jim Grosbach case ARM::VLD2q16PseudoWB_register: 1151a4e3c7fc4ba2d55695b0484480685698132eba20Jim Grosbach case ARM::VLD2q32PseudoWB_register: 1152f572191fe43025bd85ab5d398a5b53305fdc6b8bBob Wilson case ARM::VLD3d8Pseudo: 1153f572191fe43025bd85ab5d398a5b53305fdc6b8bBob Wilson case ARM::VLD3d16Pseudo: 1154f572191fe43025bd85ab5d398a5b53305fdc6b8bBob Wilson case ARM::VLD3d32Pseudo: 1155ffde080ae615906545eb33dab30e7bc47c2ac838Bob Wilson case ARM::VLD1d64TPseudo: 115636b56886974eae4f9c5ebc96befd3e7bfe5de338Stephen Hines case ARM::VLD1d64TPseudoWB_fixed: 1157f572191fe43025bd85ab5d398a5b53305fdc6b8bBob Wilson case ARM::VLD3d8Pseudo_UPD: 1158f572191fe43025bd85ab5d398a5b53305fdc6b8bBob Wilson case ARM::VLD3d16Pseudo_UPD: 1159f572191fe43025bd85ab5d398a5b53305fdc6b8bBob Wilson case ARM::VLD3d32Pseudo_UPD: 1160f572191fe43025bd85ab5d398a5b53305fdc6b8bBob Wilson case ARM::VLD3q8Pseudo_UPD: 1161f572191fe43025bd85ab5d398a5b53305fdc6b8bBob Wilson case ARM::VLD3q16Pseudo_UPD: 1162f572191fe43025bd85ab5d398a5b53305fdc6b8bBob Wilson case ARM::VLD3q32Pseudo_UPD: 11637de6814405ab02591235f0826b8e6d98fd76c8baBob Wilson case ARM::VLD3q8oddPseudo: 11647de6814405ab02591235f0826b8e6d98fd76c8baBob Wilson case ARM::VLD3q16oddPseudo: 11657de6814405ab02591235f0826b8e6d98fd76c8baBob Wilson case ARM::VLD3q32oddPseudo: 1166f572191fe43025bd85ab5d398a5b53305fdc6b8bBob Wilson case ARM::VLD3q8oddPseudo_UPD: 1167f572191fe43025bd85ab5d398a5b53305fdc6b8bBob Wilson case ARM::VLD3q16oddPseudo_UPD: 1168f572191fe43025bd85ab5d398a5b53305fdc6b8bBob Wilson case ARM::VLD3q32oddPseudo_UPD: 1169f572191fe43025bd85ab5d398a5b53305fdc6b8bBob Wilson case ARM::VLD4d8Pseudo: 1170f572191fe43025bd85ab5d398a5b53305fdc6b8bBob Wilson case ARM::VLD4d16Pseudo: 1171f572191fe43025bd85ab5d398a5b53305fdc6b8bBob Wilson case ARM::VLD4d32Pseudo: 1172ffde080ae615906545eb33dab30e7bc47c2ac838Bob Wilson case ARM::VLD1d64QPseudo: 117336b56886974eae4f9c5ebc96befd3e7bfe5de338Stephen Hines case ARM::VLD1d64QPseudoWB_fixed: 1174f572191fe43025bd85ab5d398a5b53305fdc6b8bBob Wilson case ARM::VLD4d8Pseudo_UPD: 1175f572191fe43025bd85ab5d398a5b53305fdc6b8bBob Wilson case ARM::VLD4d16Pseudo_UPD: 1176f572191fe43025bd85ab5d398a5b53305fdc6b8bBob Wilson case ARM::VLD4d32Pseudo_UPD: 1177f572191fe43025bd85ab5d398a5b53305fdc6b8bBob Wilson case ARM::VLD4q8Pseudo_UPD: 1178f572191fe43025bd85ab5d398a5b53305fdc6b8bBob Wilson case ARM::VLD4q16Pseudo_UPD: 1179f572191fe43025bd85ab5d398a5b53305fdc6b8bBob Wilson case ARM::VLD4q32Pseudo_UPD: 11807de6814405ab02591235f0826b8e6d98fd76c8baBob Wilson case ARM::VLD4q8oddPseudo: 11817de6814405ab02591235f0826b8e6d98fd76c8baBob Wilson case ARM::VLD4q16oddPseudo: 11827de6814405ab02591235f0826b8e6d98fd76c8baBob Wilson case ARM::VLD4q32oddPseudo: 1183f572191fe43025bd85ab5d398a5b53305fdc6b8bBob Wilson case ARM::VLD4q8oddPseudo_UPD: 1184f572191fe43025bd85ab5d398a5b53305fdc6b8bBob Wilson case ARM::VLD4q16oddPseudo_UPD: 1185f572191fe43025bd85ab5d398a5b53305fdc6b8bBob Wilson case ARM::VLD4q32oddPseudo_UPD: 118686c6d80a7a20fa7decc3e914be5d1cb0f7f29a6fBob Wilson case ARM::VLD3DUPd8Pseudo: 118786c6d80a7a20fa7decc3e914be5d1cb0f7f29a6fBob Wilson case ARM::VLD3DUPd16Pseudo: 118886c6d80a7a20fa7decc3e914be5d1cb0f7f29a6fBob Wilson case ARM::VLD3DUPd32Pseudo: 118986c6d80a7a20fa7decc3e914be5d1cb0f7f29a6fBob Wilson case ARM::VLD3DUPd8Pseudo_UPD: 119086c6d80a7a20fa7decc3e914be5d1cb0f7f29a6fBob Wilson case ARM::VLD3DUPd16Pseudo_UPD: 119186c6d80a7a20fa7decc3e914be5d1cb0f7f29a6fBob Wilson case ARM::VLD3DUPd32Pseudo_UPD: 11926c4c982f83eea655e0f14610d2689fad722aeb7dBob Wilson case ARM::VLD4DUPd8Pseudo: 11936c4c982f83eea655e0f14610d2689fad722aeb7dBob Wilson case ARM::VLD4DUPd16Pseudo: 11946c4c982f83eea655e0f14610d2689fad722aeb7dBob Wilson case ARM::VLD4DUPd32Pseudo: 11956c4c982f83eea655e0f14610d2689fad722aeb7dBob Wilson case ARM::VLD4DUPd8Pseudo_UPD: 11966c4c982f83eea655e0f14610d2689fad722aeb7dBob Wilson case ARM::VLD4DUPd16Pseudo_UPD: 11976c4c982f83eea655e0f14610d2689fad722aeb7dBob Wilson case ARM::VLD4DUPd32Pseudo_UPD: 11988466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson ExpandVLD(MBBI); 11999fe2009956fc40f3aea46fb3c38dcfb61c4aca46Evan Cheng return true; 1200ffde080ae615906545eb33dab30e7bc47c2ac838Bob Wilson 1201e5ce4f68c786696a96acf1f1aa5431652abb6ce7Bob Wilson case ARM::VST2q8Pseudo: 1202e5ce4f68c786696a96acf1f1aa5431652abb6ce7Bob Wilson case ARM::VST2q16Pseudo: 1203e5ce4f68c786696a96acf1f1aa5431652abb6ce7Bob Wilson case ARM::VST2q32Pseudo: 1204bb3a2e4d0defc6854d37384d80858037dbbc5f20Jim Grosbach case ARM::VST2q8PseudoWB_fixed: 1205bb3a2e4d0defc6854d37384d80858037dbbc5f20Jim Grosbach case ARM::VST2q16PseudoWB_fixed: 1206bb3a2e4d0defc6854d37384d80858037dbbc5f20Jim Grosbach case ARM::VST2q32PseudoWB_fixed: 1207bb3a2e4d0defc6854d37384d80858037dbbc5f20Jim Grosbach case ARM::VST2q8PseudoWB_register: 1208bb3a2e4d0defc6854d37384d80858037dbbc5f20Jim Grosbach case ARM::VST2q16PseudoWB_register: 1209bb3a2e4d0defc6854d37384d80858037dbbc5f20Jim Grosbach case ARM::VST2q32PseudoWB_register: 121001ba461af7eafc9d181a5c349487691f2e801438Bob Wilson case ARM::VST3d8Pseudo: 121101ba461af7eafc9d181a5c349487691f2e801438Bob Wilson case ARM::VST3d16Pseudo: 121201ba461af7eafc9d181a5c349487691f2e801438Bob Wilson case ARM::VST3d32Pseudo: 121301ba461af7eafc9d181a5c349487691f2e801438Bob Wilson case ARM::VST1d64TPseudo: 121401ba461af7eafc9d181a5c349487691f2e801438Bob Wilson case ARM::VST3d8Pseudo_UPD: 121501ba461af7eafc9d181a5c349487691f2e801438Bob Wilson case ARM::VST3d16Pseudo_UPD: 121601ba461af7eafc9d181a5c349487691f2e801438Bob Wilson case ARM::VST3d32Pseudo_UPD: 1217d5ca201891d238ca2185831524a1e3f2670224dfJim Grosbach case ARM::VST1d64TPseudoWB_fixed: 1218d5ca201891d238ca2185831524a1e3f2670224dfJim Grosbach case ARM::VST1d64TPseudoWB_register: 121901ba461af7eafc9d181a5c349487691f2e801438Bob Wilson case ARM::VST3q8Pseudo_UPD: 122001ba461af7eafc9d181a5c349487691f2e801438Bob Wilson case ARM::VST3q16Pseudo_UPD: 122101ba461af7eafc9d181a5c349487691f2e801438Bob Wilson case ARM::VST3q32Pseudo_UPD: 12227de6814405ab02591235f0826b8e6d98fd76c8baBob Wilson case ARM::VST3q8oddPseudo: 12237de6814405ab02591235f0826b8e6d98fd76c8baBob Wilson case ARM::VST3q16oddPseudo: 12247de6814405ab02591235f0826b8e6d98fd76c8baBob Wilson case ARM::VST3q32oddPseudo: 122501ba461af7eafc9d181a5c349487691f2e801438Bob Wilson case ARM::VST3q8oddPseudo_UPD: 122601ba461af7eafc9d181a5c349487691f2e801438Bob Wilson case ARM::VST3q16oddPseudo_UPD: 122701ba461af7eafc9d181a5c349487691f2e801438Bob Wilson case ARM::VST3q32oddPseudo_UPD: 1228709d59255a3100c7d440c93069efa1f726677a27Bob Wilson case ARM::VST4d8Pseudo: 1229709d59255a3100c7d440c93069efa1f726677a27Bob Wilson case ARM::VST4d16Pseudo: 1230709d59255a3100c7d440c93069efa1f726677a27Bob Wilson case ARM::VST4d32Pseudo: 123170e48b23a3455e4689ee24cec4eb153d67223e86Bob Wilson case ARM::VST1d64QPseudo: 1232709d59255a3100c7d440c93069efa1f726677a27Bob Wilson case ARM::VST4d8Pseudo_UPD: 1233709d59255a3100c7d440c93069efa1f726677a27Bob Wilson case ARM::VST4d16Pseudo_UPD: 1234709d59255a3100c7d440c93069efa1f726677a27Bob Wilson case ARM::VST4d32Pseudo_UPD: 12354c7edb3ad8bd513c59190f6ebee9bee34af7d247Jim Grosbach case ARM::VST1d64QPseudoWB_fixed: 12364c7edb3ad8bd513c59190f6ebee9bee34af7d247Jim Grosbach case ARM::VST1d64QPseudoWB_register: 1237709d59255a3100c7d440c93069efa1f726677a27Bob Wilson case ARM::VST4q8Pseudo_UPD: 1238709d59255a3100c7d440c93069efa1f726677a27Bob Wilson case ARM::VST4q16Pseudo_UPD: 1239709d59255a3100c7d440c93069efa1f726677a27Bob Wilson case ARM::VST4q32Pseudo_UPD: 12407de6814405ab02591235f0826b8e6d98fd76c8baBob Wilson case ARM::VST4q8oddPseudo: 12417de6814405ab02591235f0826b8e6d98fd76c8baBob Wilson case ARM::VST4q16oddPseudo: 12427de6814405ab02591235f0826b8e6d98fd76c8baBob Wilson case ARM::VST4q32oddPseudo: 1243709d59255a3100c7d440c93069efa1f726677a27Bob Wilson case ARM::VST4q8oddPseudo_UPD: 1244709d59255a3100c7d440c93069efa1f726677a27Bob Wilson case ARM::VST4q16oddPseudo_UPD: 1245709d59255a3100c7d440c93069efa1f726677a27Bob Wilson case ARM::VST4q32oddPseudo_UPD: 12468466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson ExpandVST(MBBI); 12479fe2009956fc40f3aea46fb3c38dcfb61c4aca46Evan Cheng return true; 12488466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson 1249b796bbb6de19872c0c1921b8b3f05206dd33c97dBob Wilson case ARM::VLD1LNq8Pseudo: 1250b796bbb6de19872c0c1921b8b3f05206dd33c97dBob Wilson case ARM::VLD1LNq16Pseudo: 1251b796bbb6de19872c0c1921b8b3f05206dd33c97dBob Wilson case ARM::VLD1LNq32Pseudo: 1252b796bbb6de19872c0c1921b8b3f05206dd33c97dBob Wilson case ARM::VLD1LNq8Pseudo_UPD: 1253b796bbb6de19872c0c1921b8b3f05206dd33c97dBob Wilson case ARM::VLD1LNq16Pseudo_UPD: 1254b796bbb6de19872c0c1921b8b3f05206dd33c97dBob Wilson case ARM::VLD1LNq32Pseudo_UPD: 12558466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson case ARM::VLD2LNd8Pseudo: 12568466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson case ARM::VLD2LNd16Pseudo: 12578466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson case ARM::VLD2LNd32Pseudo: 12588466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson case ARM::VLD2LNq16Pseudo: 12598466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson case ARM::VLD2LNq32Pseudo: 12608466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson case ARM::VLD2LNd8Pseudo_UPD: 12618466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson case ARM::VLD2LNd16Pseudo_UPD: 12628466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson case ARM::VLD2LNd32Pseudo_UPD: 12638466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson case ARM::VLD2LNq16Pseudo_UPD: 12648466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson case ARM::VLD2LNq32Pseudo_UPD: 12658466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson case ARM::VLD3LNd8Pseudo: 12668466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson case ARM::VLD3LNd16Pseudo: 12678466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson case ARM::VLD3LNd32Pseudo: 12688466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson case ARM::VLD3LNq16Pseudo: 12698466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson case ARM::VLD3LNq32Pseudo: 12708466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson case ARM::VLD3LNd8Pseudo_UPD: 12718466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson case ARM::VLD3LNd16Pseudo_UPD: 12728466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson case ARM::VLD3LNd32Pseudo_UPD: 12738466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson case ARM::VLD3LNq16Pseudo_UPD: 12748466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson case ARM::VLD3LNq32Pseudo_UPD: 12758466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson case ARM::VLD4LNd8Pseudo: 12768466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson case ARM::VLD4LNd16Pseudo: 12778466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson case ARM::VLD4LNd32Pseudo: 12788466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson case ARM::VLD4LNq16Pseudo: 12798466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson case ARM::VLD4LNq32Pseudo: 12808466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson case ARM::VLD4LNd8Pseudo_UPD: 12818466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson case ARM::VLD4LNd16Pseudo_UPD: 12828466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson case ARM::VLD4LNd32Pseudo_UPD: 12838466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson case ARM::VLD4LNq16Pseudo_UPD: 12848466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson case ARM::VLD4LNq32Pseudo_UPD: 1285d0c6bc220433fab06bc1507f963ea5883fdc4f69Bob Wilson case ARM::VST1LNq8Pseudo: 1286d0c6bc220433fab06bc1507f963ea5883fdc4f69Bob Wilson case ARM::VST1LNq16Pseudo: 1287d0c6bc220433fab06bc1507f963ea5883fdc4f69Bob Wilson case ARM::VST1LNq32Pseudo: 1288d0c6bc220433fab06bc1507f963ea5883fdc4f69Bob Wilson case ARM::VST1LNq8Pseudo_UPD: 1289d0c6bc220433fab06bc1507f963ea5883fdc4f69Bob Wilson case ARM::VST1LNq16Pseudo_UPD: 1290d0c6bc220433fab06bc1507f963ea5883fdc4f69Bob Wilson case ARM::VST1LNq32Pseudo_UPD: 12918466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson case ARM::VST2LNd8Pseudo: 12928466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson case ARM::VST2LNd16Pseudo: 12938466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson case ARM::VST2LNd32Pseudo: 12948466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson case ARM::VST2LNq16Pseudo: 12958466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson case ARM::VST2LNq32Pseudo: 12968466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson case ARM::VST2LNd8Pseudo_UPD: 12978466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson case ARM::VST2LNd16Pseudo_UPD: 12988466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson case ARM::VST2LNd32Pseudo_UPD: 12998466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson case ARM::VST2LNq16Pseudo_UPD: 13008466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson case ARM::VST2LNq32Pseudo_UPD: 13018466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson case ARM::VST3LNd8Pseudo: 13028466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson case ARM::VST3LNd16Pseudo: 13038466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson case ARM::VST3LNd32Pseudo: 13048466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson case ARM::VST3LNq16Pseudo: 13058466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson case ARM::VST3LNq32Pseudo: 13068466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson case ARM::VST3LNd8Pseudo_UPD: 13078466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson case ARM::VST3LNd16Pseudo_UPD: 13088466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson case ARM::VST3LNd32Pseudo_UPD: 13098466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson case ARM::VST3LNq16Pseudo_UPD: 13108466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson case ARM::VST3LNq32Pseudo_UPD: 13118466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson case ARM::VST4LNd8Pseudo: 13128466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson case ARM::VST4LNd16Pseudo: 13138466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson case ARM::VST4LNd32Pseudo: 13148466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson case ARM::VST4LNq16Pseudo: 13158466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson case ARM::VST4LNq32Pseudo: 13168466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson case ARM::VST4LNd8Pseudo_UPD: 13178466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson case ARM::VST4LNd16Pseudo_UPD: 13188466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson case ARM::VST4LNd32Pseudo_UPD: 13198466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson case ARM::VST4LNq16Pseudo_UPD: 13208466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson case ARM::VST4LNq32Pseudo_UPD: 13218466fa1842ad4f2d6fadcf5c23c15319ae96b972Bob Wilson ExpandLaneOp(MBBI); 13229fe2009956fc40f3aea46fb3c38dcfb61c4aca46Evan Cheng return true; 13239fe2009956fc40f3aea46fb3c38dcfb61c4aca46Evan Cheng 132460d99a5278e4a0e7116a05c01cececb07ca1362aJim Grosbach case ARM::VTBL3Pseudo: ExpandVTBL(MBBI, ARM::VTBL3, false); return true; 132560d99a5278e4a0e7116a05c01cececb07ca1362aJim Grosbach case ARM::VTBL4Pseudo: ExpandVTBL(MBBI, ARM::VTBL4, false); return true; 132660d99a5278e4a0e7116a05c01cececb07ca1362aJim Grosbach case ARM::VTBX3Pseudo: ExpandVTBL(MBBI, ARM::VTBX3, true); return true; 132760d99a5278e4a0e7116a05c01cececb07ca1362aJim Grosbach case ARM::VTBX4Pseudo: ExpandVTBL(MBBI, ARM::VTBX4, true); return true; 13289fe2009956fc40f3aea46fb3c38dcfb61c4aca46Evan Cheng } 13299fe2009956fc40f3aea46fb3c38dcfb61c4aca46Evan Cheng} 1330709d59255a3100c7d440c93069efa1f726677a27Bob Wilson 13319fe2009956fc40f3aea46fb3c38dcfb61c4aca46Evan Chengbool ARMExpandPseudo::ExpandMBB(MachineBasicBlock &MBB) { 13329fe2009956fc40f3aea46fb3c38dcfb61c4aca46Evan Cheng bool Modified = false; 13339fe2009956fc40f3aea46fb3c38dcfb61c4aca46Evan Cheng 13349fe2009956fc40f3aea46fb3c38dcfb61c4aca46Evan Cheng MachineBasicBlock::iterator MBBI = MBB.begin(), E = MBB.end(); 13359fe2009956fc40f3aea46fb3c38dcfb61c4aca46Evan Cheng while (MBBI != E) { 133636b56886974eae4f9c5ebc96befd3e7bfe5de338Stephen Hines MachineBasicBlock::iterator NMBBI = std::next(MBBI); 13379fe2009956fc40f3aea46fb3c38dcfb61c4aca46Evan Cheng Modified |= ExpandMI(MBB, MBBI); 1338b9803a8fa65f043c96612fa9c5aeeee12739db2bEvan Cheng MBBI = NMBBI; 1339b9803a8fa65f043c96612fa9c5aeeee12739db2bEvan Cheng } 1340b9803a8fa65f043c96612fa9c5aeeee12739db2bEvan Cheng 1341b9803a8fa65f043c96612fa9c5aeeee12739db2bEvan Cheng return Modified; 1342b9803a8fa65f043c96612fa9c5aeeee12739db2bEvan Cheng} 1343b9803a8fa65f043c96612fa9c5aeeee12739db2bEvan Cheng 1344b9803a8fa65f043c96612fa9c5aeeee12739db2bEvan Chengbool ARMExpandPseudo::runOnMachineFunction(MachineFunction &MF) { 134553519f015e3e84e9f57b677cc8724805a6009b73Evan Cheng const TargetMachine &TM = MF.getTarget(); 134653519f015e3e84e9f57b677cc8724805a6009b73Evan Cheng TII = static_cast<const ARMBaseInstrInfo*>(TM.getInstrInfo()); 134753519f015e3e84e9f57b677cc8724805a6009b73Evan Cheng TRI = TM.getRegisterInfo(); 134853519f015e3e84e9f57b677cc8724805a6009b73Evan Cheng STI = &TM.getSubtarget<ARMSubtarget>(); 13499fe2009956fc40f3aea46fb3c38dcfb61c4aca46Evan Cheng AFI = MF.getInfo<ARMFunctionInfo>(); 1350b9803a8fa65f043c96612fa9c5aeeee12739db2bEvan Cheng 1351b9803a8fa65f043c96612fa9c5aeeee12739db2bEvan Cheng bool Modified = false; 1352b9803a8fa65f043c96612fa9c5aeeee12739db2bEvan Cheng for (MachineFunction::iterator MFI = MF.begin(), E = MF.end(); MFI != E; 1353b9803a8fa65f043c96612fa9c5aeeee12739db2bEvan Cheng ++MFI) 1354b9803a8fa65f043c96612fa9c5aeeee12739db2bEvan Cheng Modified |= ExpandMBB(*MFI); 1355e69438fb87623dd6fdeeb99b647a46e877eb6183Jakob Stoklund Olesen if (VerifyARMPseudo) 1356e69438fb87623dd6fdeeb99b647a46e877eb6183Jakob Stoklund Olesen MF.verify(this, "After expanding ARM pseudo instructions."); 1357b9803a8fa65f043c96612fa9c5aeeee12739db2bEvan Cheng return Modified; 1358b9803a8fa65f043c96612fa9c5aeeee12739db2bEvan Cheng} 1359b9803a8fa65f043c96612fa9c5aeeee12739db2bEvan Cheng 1360b9803a8fa65f043c96612fa9c5aeeee12739db2bEvan Cheng/// createARMExpandPseudoPass - returns an instance of the pseudo instruction 1361b9803a8fa65f043c96612fa9c5aeeee12739db2bEvan Cheng/// expansion pass. 1362b9803a8fa65f043c96612fa9c5aeeee12739db2bEvan ChengFunctionPass *llvm::createARMExpandPseudoPass() { 1363b9803a8fa65f043c96612fa9c5aeeee12739db2bEvan Cheng return new ARMExpandPseudo(); 1364b9803a8fa65f043c96612fa9c5aeeee12739db2bEvan Cheng} 1365