ARMFastISel.cpp revision 98d3af863f5d21f782bc8518d4a59137ba46e315 
1//===-- ARMFastISel.cpp - ARM FastISel implementation ---------------------===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file defines the ARM-specific support for the FastISel class. Some
11// of the target-specific code is generated by tablegen in the file
12// ARMGenFastISel.inc, which is #included here.
13//
14//===----------------------------------------------------------------------===//
15
16#include "ARM.h"
17#include "ARMBaseInstrInfo.h"
18#include "ARMCallingConv.h"
19#include "ARMRegisterInfo.h"
20#include "ARMTargetMachine.h"
21#include "ARMSubtarget.h"
22#include "llvm/CallingConv.h"
23#include "llvm/DerivedTypes.h"
24#include "llvm/GlobalVariable.h"
25#include "llvm/Instructions.h"
26#include "llvm/IntrinsicInst.h"
27#include "llvm/Module.h"
28#include "llvm/CodeGen/Analysis.h"
29#include "llvm/CodeGen/FastISel.h"
30#include "llvm/CodeGen/FunctionLoweringInfo.h"
31#include "llvm/CodeGen/MachineInstrBuilder.h"
32#include "llvm/CodeGen/MachineModuleInfo.h"
33#include "llvm/CodeGen/MachineConstantPool.h"
34#include "llvm/CodeGen/MachineFrameInfo.h"
35#include "llvm/CodeGen/MachineRegisterInfo.h"
36#include "llvm/Support/CallSite.h"
37#include "llvm/Support/CommandLine.h"
38#include "llvm/Support/ErrorHandling.h"
39#include "llvm/Support/GetElementPtrTypeIterator.h"
40#include "llvm/Target/TargetData.h"
41#include "llvm/Target/TargetInstrInfo.h"
42#include "llvm/Target/TargetLowering.h"
43#include "llvm/Target/TargetMachine.h"
44#include "llvm/Target/TargetOptions.h"
45using namespace llvm;
46
47static cl::opt<bool>
48EnableARMFastISel("arm-fast-isel",
49                  cl::desc("Turn on experimental ARM fast-isel support"),
50                  cl::init(false), cl::Hidden);
51
52namespace {
53
54class ARMFastISel : public FastISel {
55
56  /// Subtarget - Keep a pointer to the ARMSubtarget around so that we can
57  /// make the right decision when generating code for different targets.
58  const ARMSubtarget *Subtarget;
59  const TargetMachine &TM;
60  const TargetInstrInfo &TII;
61  const TargetLowering &TLI;
62  const ARMFunctionInfo *AFI;
63
64  // Convenience variable to avoid checking all the time.
65  bool isThumb;
66
67  public:
68    explicit ARMFastISel(FunctionLoweringInfo &funcInfo)
69    : FastISel(funcInfo),
70      TM(funcInfo.MF->getTarget()),
71      TII(*TM.getInstrInfo()),
72      TLI(*TM.getTargetLowering()) {
73      Subtarget = &TM.getSubtarget<ARMSubtarget>();
74      AFI = funcInfo.MF->getInfo<ARMFunctionInfo>();
75      isThumb = AFI->isThumbFunction();
76    }
77
78    // Code from FastISel.cpp.
79    virtual unsigned FastEmitInst_(unsigned MachineInstOpcode,
80                                   const TargetRegisterClass *RC);
81    virtual unsigned FastEmitInst_r(unsigned MachineInstOpcode,
82                                    const TargetRegisterClass *RC,
83                                    unsigned Op0, bool Op0IsKill);
84    virtual unsigned FastEmitInst_rr(unsigned MachineInstOpcode,
85                                     const TargetRegisterClass *RC,
86                                     unsigned Op0, bool Op0IsKill,
87                                     unsigned Op1, bool Op1IsKill);
88    virtual unsigned FastEmitInst_ri(unsigned MachineInstOpcode,
89                                     const TargetRegisterClass *RC,
90                                     unsigned Op0, bool Op0IsKill,
91                                     uint64_t Imm);
92    virtual unsigned FastEmitInst_rf(unsigned MachineInstOpcode,
93                                     const TargetRegisterClass *RC,
94                                     unsigned Op0, bool Op0IsKill,
95                                     const ConstantFP *FPImm);
96    virtual unsigned FastEmitInst_i(unsigned MachineInstOpcode,
97                                    const TargetRegisterClass *RC,
98                                    uint64_t Imm);
99    virtual unsigned FastEmitInst_rri(unsigned MachineInstOpcode,
100                                      const TargetRegisterClass *RC,
101                                      unsigned Op0, bool Op0IsKill,
102                                      unsigned Op1, bool Op1IsKill,
103                                      uint64_t Imm);
104    virtual unsigned FastEmitInst_extractsubreg(MVT RetVT,
105                                                unsigned Op0, bool Op0IsKill,
106                                                uint32_t Idx);
107
108    // Backend specific FastISel code.
109    virtual bool TargetSelectInstruction(const Instruction *I);
110    virtual unsigned TargetMaterializeConstant(const Constant *C);
111
112  #include "ARMGenFastISel.inc"
113
114    // Instruction selection routines.
115  private:
116    virtual bool SelectLoad(const Instruction *I);
117    virtual bool SelectStore(const Instruction *I);
118    virtual bool SelectBranch(const Instruction *I);
119    virtual bool SelectCmp(const Instruction *I);
120    virtual bool SelectFPExt(const Instruction *I);
121    virtual bool SelectFPTrunc(const Instruction *I);
122    virtual bool SelectBinaryOp(const Instruction *I, unsigned ISDOpcode);
123    virtual bool SelectSIToFP(const Instruction *I);
124    virtual bool SelectFPToSI(const Instruction *I);
125    virtual bool SelectSDiv(const Instruction *I);
126
127    // Utility routines.
128  private:
129    bool isTypeLegal(const Type *Ty, EVT &VT);
130    bool isLoadTypeLegal(const Type *Ty, EVT &VT);
131    bool ARMEmitLoad(EVT VT, unsigned &ResultReg, unsigned Reg, int Offset);
132    bool ARMEmitStore(EVT VT, unsigned SrcReg, unsigned Reg, int Offset);
133    bool ARMLoadAlloca(const Instruction *I, EVT VT);
134    bool ARMStoreAlloca(const Instruction *I, unsigned SrcReg, EVT VT);
135    bool ARMComputeRegOffset(const Value *Obj, unsigned &Reg, int &Offset);
136    unsigned ARMMaterializeFP(const ConstantFP *CFP, EVT VT);
137    unsigned ARMMaterializeInt(const Constant *C, EVT VT);
138    unsigned ARMMoveToFPReg(EVT VT, unsigned SrcReg);
139    unsigned ARMMoveToIntReg(EVT VT, unsigned SrcReg);
140
141    // Call handling routines.
142  private:
143    CCAssignFn *CCAssignFnForCall(CallingConv::ID CC, bool Return);
144    bool ARMEmitLibcall(const Instruction *I, RTLIB::Libcall Call);
145
146    // OptionalDef handling routines.
147  private:
148    bool DefinesOptionalPredicate(MachineInstr *MI, bool *CPSR);
149    const MachineInstrBuilder &AddOptionalDefs(const MachineInstrBuilder &MIB);
150};
151
152} // end anonymous namespace
153
154#include "ARMGenCallingConv.inc"
155
156// DefinesOptionalPredicate - This is different from DefinesPredicate in that
157// we don't care about implicit defs here, just places we'll need to add a
158// default CCReg argument. Sets CPSR if we're setting CPSR instead of CCR.
159bool ARMFastISel::DefinesOptionalPredicate(MachineInstr *MI, bool *CPSR) {
160  const TargetInstrDesc &TID = MI->getDesc();
161  if (!TID.hasOptionalDef())
162    return false;
163
164  // Look to see if our OptionalDef is defining CPSR or CCR.
165  for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
166    const MachineOperand &MO = MI->getOperand(i);
167    if (!MO.isReg() || !MO.isDef()) continue;
168    if (MO.getReg() == ARM::CPSR)
169      *CPSR = true;
170  }
171  return true;
172}
173
174// If the machine is predicable go ahead and add the predicate operands, if
175// it needs default CC operands add those.
176const MachineInstrBuilder &
177ARMFastISel::AddOptionalDefs(const MachineInstrBuilder &MIB) {
178  MachineInstr *MI = &*MIB;
179
180  // Do we use a predicate?
181  if (TII.isPredicable(MI))
182    AddDefaultPred(MIB);
183
184  // Do we optionally set a predicate?  Preds is size > 0 iff the predicate
185  // defines CPSR. All other OptionalDefines in ARM are the CCR register.
186  bool CPSR = false;
187  if (DefinesOptionalPredicate(MI, &CPSR)) {
188    if (CPSR)
189      AddDefaultT1CC(MIB);
190    else
191      AddDefaultCC(MIB);
192  }
193  return MIB;
194}
195
196unsigned ARMFastISel::FastEmitInst_(unsigned MachineInstOpcode,
197                                    const TargetRegisterClass* RC) {
198  unsigned ResultReg = createResultReg(RC);
199  const TargetInstrDesc &II = TII.get(MachineInstOpcode);
200
201  AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II, ResultReg));
202  return ResultReg;
203}
204
205unsigned ARMFastISel::FastEmitInst_r(unsigned MachineInstOpcode,
206                                     const TargetRegisterClass *RC,
207                                     unsigned Op0, bool Op0IsKill) {
208  unsigned ResultReg = createResultReg(RC);
209  const TargetInstrDesc &II = TII.get(MachineInstOpcode);
210
211  if (II.getNumDefs() >= 1)
212    AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II, ResultReg)
213                   .addReg(Op0, Op0IsKill * RegState::Kill));
214  else {
215    AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II)
216                   .addReg(Op0, Op0IsKill * RegState::Kill));
217    AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
218                   TII.get(TargetOpcode::COPY), ResultReg)
219                   .addReg(II.ImplicitDefs[0]));
220  }
221  return ResultReg;
222}
223
224unsigned ARMFastISel::FastEmitInst_rr(unsigned MachineInstOpcode,
225                                      const TargetRegisterClass *RC,
226                                      unsigned Op0, bool Op0IsKill,
227                                      unsigned Op1, bool Op1IsKill) {
228  unsigned ResultReg = createResultReg(RC);
229  const TargetInstrDesc &II = TII.get(MachineInstOpcode);
230
231  if (II.getNumDefs() >= 1)
232    AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II, ResultReg)
233                   .addReg(Op0, Op0IsKill * RegState::Kill)
234                   .addReg(Op1, Op1IsKill * RegState::Kill));
235  else {
236    AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II)
237                   .addReg(Op0, Op0IsKill * RegState::Kill)
238                   .addReg(Op1, Op1IsKill * RegState::Kill));
239    AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
240                           TII.get(TargetOpcode::COPY), ResultReg)
241                   .addReg(II.ImplicitDefs[0]));
242  }
243  return ResultReg;
244}
245
246unsigned ARMFastISel::FastEmitInst_ri(unsigned MachineInstOpcode,
247                                      const TargetRegisterClass *RC,
248                                      unsigned Op0, bool Op0IsKill,
249                                      uint64_t Imm) {
250  unsigned ResultReg = createResultReg(RC);
251  const TargetInstrDesc &II = TII.get(MachineInstOpcode);
252
253  if (II.getNumDefs() >= 1)
254    AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II, ResultReg)
255                   .addReg(Op0, Op0IsKill * RegState::Kill)
256                   .addImm(Imm));
257  else {
258    AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II)
259                   .addReg(Op0, Op0IsKill * RegState::Kill)
260                   .addImm(Imm));
261    AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
262                           TII.get(TargetOpcode::COPY), ResultReg)
263                   .addReg(II.ImplicitDefs[0]));
264  }
265  return ResultReg;
266}
267
268unsigned ARMFastISel::FastEmitInst_rf(unsigned MachineInstOpcode,
269                                      const TargetRegisterClass *RC,
270                                      unsigned Op0, bool Op0IsKill,
271                                      const ConstantFP *FPImm) {
272  unsigned ResultReg = createResultReg(RC);
273  const TargetInstrDesc &II = TII.get(MachineInstOpcode);
274
275  if (II.getNumDefs() >= 1)
276    AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II, ResultReg)
277                   .addReg(Op0, Op0IsKill * RegState::Kill)
278                   .addFPImm(FPImm));
279  else {
280    AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II)
281                   .addReg(Op0, Op0IsKill * RegState::Kill)
282                   .addFPImm(FPImm));
283    AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
284                           TII.get(TargetOpcode::COPY), ResultReg)
285                   .addReg(II.ImplicitDefs[0]));
286  }
287  return ResultReg;
288}
289
290unsigned ARMFastISel::FastEmitInst_rri(unsigned MachineInstOpcode,
291                                       const TargetRegisterClass *RC,
292                                       unsigned Op0, bool Op0IsKill,
293                                       unsigned Op1, bool Op1IsKill,
294                                       uint64_t Imm) {
295  unsigned ResultReg = createResultReg(RC);
296  const TargetInstrDesc &II = TII.get(MachineInstOpcode);
297
298  if (II.getNumDefs() >= 1)
299    AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II, ResultReg)
300                   .addReg(Op0, Op0IsKill * RegState::Kill)
301                   .addReg(Op1, Op1IsKill * RegState::Kill)
302                   .addImm(Imm));
303  else {
304    AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II)
305                   .addReg(Op0, Op0IsKill * RegState::Kill)
306                   .addReg(Op1, Op1IsKill * RegState::Kill)
307                   .addImm(Imm));
308    AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
309                           TII.get(TargetOpcode::COPY), ResultReg)
310                   .addReg(II.ImplicitDefs[0]));
311  }
312  return ResultReg;
313}
314
315unsigned ARMFastISel::FastEmitInst_i(unsigned MachineInstOpcode,
316                                     const TargetRegisterClass *RC,
317                                     uint64_t Imm) {
318  unsigned ResultReg = createResultReg(RC);
319  const TargetInstrDesc &II = TII.get(MachineInstOpcode);
320
321  if (II.getNumDefs() >= 1)
322    AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II, ResultReg)
323                   .addImm(Imm));
324  else {
325    AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II)
326                   .addImm(Imm));
327    AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
328                           TII.get(TargetOpcode::COPY), ResultReg)
329                   .addReg(II.ImplicitDefs[0]));
330  }
331  return ResultReg;
332}
333
334unsigned ARMFastISel::FastEmitInst_extractsubreg(MVT RetVT,
335                                                 unsigned Op0, bool Op0IsKill,
336                                                 uint32_t Idx) {
337  unsigned ResultReg = createResultReg(TLI.getRegClassFor(RetVT));
338  assert(TargetRegisterInfo::isVirtualRegister(Op0) &&
339         "Cannot yet extract from physregs");
340  AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt,
341                         DL, TII.get(TargetOpcode::COPY), ResultReg)
342                 .addReg(Op0, getKillRegState(Op0IsKill), Idx));
343  return ResultReg;
344}
345
346// TODO: Don't worry about 64-bit now, but when this is fixed remove the
347// checks from the various callers.
348unsigned ARMFastISel::ARMMoveToFPReg(EVT VT, unsigned SrcReg) {
349  if (VT.getSimpleVT().SimpleTy == MVT::f64) return 0;
350
351  unsigned MoveReg = createResultReg(TLI.getRegClassFor(VT));
352  AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
353                          TII.get(ARM::VMOVRS), MoveReg)
354                  .addReg(SrcReg));
355  return MoveReg;
356}
357
358unsigned ARMFastISel::ARMMoveToIntReg(EVT VT, unsigned SrcReg) {
359  if (VT.getSimpleVT().SimpleTy == MVT::i64) return 0;
360
361  unsigned MoveReg = createResultReg(TLI.getRegClassFor(VT));
362  AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
363                          TII.get(ARM::VMOVSR), MoveReg)
364                  .addReg(SrcReg));
365  return MoveReg;
366}
367
368// For double width floating point we need to materialize two constants
369// (the high and the low) into integer registers then use a move to get
370// the combined constant into an FP reg.
371unsigned ARMFastISel::ARMMaterializeFP(const ConstantFP *CFP, EVT VT) {
372  const APFloat Val = CFP->getValueAPF();
373  bool is64bit = VT.getSimpleVT().SimpleTy == MVT::f64;
374
375  // This checks to see if we can use VFP3 instructions to materialize
376  // a constant, otherwise we have to go through the constant pool.
377  if (TLI.isFPImmLegal(Val, VT)) {
378    unsigned Opc = is64bit ? ARM::FCONSTD : ARM::FCONSTS;
379    unsigned DestReg = createResultReg(TLI.getRegClassFor(VT));
380    AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(Opc),
381                            DestReg)
382                    .addFPImm(CFP));
383    return DestReg;
384  }
385
386  // Require VFP2 for loading fp constants.
387  if (!Subtarget->hasVFP2()) return false;
388
389  // MachineConstantPool wants an explicit alignment.
390  unsigned Align = TD.getPrefTypeAlignment(CFP->getType());
391  if (Align == 0) {
392    // TODO: Figure out if this is correct.
393    Align = TD.getTypeAllocSize(CFP->getType());
394  }
395  unsigned Idx = MCP.getConstantPoolIndex(cast<Constant>(CFP), Align);
396  unsigned DestReg = createResultReg(TLI.getRegClassFor(VT));
397  unsigned Opc = is64bit ? ARM::VLDRD : ARM::VLDRS;
398
399  // The extra reg is for addrmode5.
400  AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(Opc),
401                          DestReg)
402                  .addConstantPoolIndex(Idx)
403                  .addReg(0));
404  return DestReg;
405}
406
407unsigned ARMFastISel::ARMMaterializeInt(const Constant *C, EVT VT) {
408
409  // For now 32-bit only.
410  if (VT.getSimpleVT().SimpleTy != MVT::i32) return false;
411
412  // MachineConstantPool wants an explicit alignment.
413  unsigned Align = TD.getPrefTypeAlignment(C->getType());
414  if (Align == 0) {
415    // TODO: Figure out if this is correct.
416    Align = TD.getTypeAllocSize(C->getType());
417  }
418  unsigned Idx = MCP.getConstantPoolIndex(C, Align);
419  unsigned DestReg = createResultReg(TLI.getRegClassFor(VT));
420
421  if (isThumb)
422    AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
423                            TII.get(ARM::t2LDRpci), DestReg)
424                    .addConstantPoolIndex(Idx));
425  else
426    // The extra reg and immediate are for addrmode2.
427    AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
428                            TII.get(ARM::LDRcp), DestReg)
429                    .addConstantPoolIndex(Idx)
430                    .addReg(0).addImm(0));
431
432  return DestReg;
433}
434
435unsigned ARMFastISel::TargetMaterializeConstant(const Constant *C) {
436  EVT VT = TLI.getValueType(C->getType(), true);
437
438  // Only handle simple types.
439  if (!VT.isSimple()) return 0;
440
441  if (const ConstantFP *CFP = dyn_cast<ConstantFP>(C))
442    return ARMMaterializeFP(CFP, VT);
443  return ARMMaterializeInt(C, VT);
444}
445
446bool ARMFastISel::isTypeLegal(const Type *Ty, EVT &VT) {
447  VT = TLI.getValueType(Ty, true);
448
449  // Only handle simple types.
450  if (VT == MVT::Other || !VT.isSimple()) return false;
451
452  // Handle all legal types, i.e. a register that will directly hold this
453  // value.
454  return TLI.isTypeLegal(VT);
455}
456
457bool ARMFastISel::isLoadTypeLegal(const Type *Ty, EVT &VT) {
458  if (isTypeLegal(Ty, VT)) return true;
459
460  // If this is a type than can be sign or zero-extended to a basic operation
461  // go ahead and accept it now.
462  if (VT == MVT::i8 || VT == MVT::i16)
463    return true;
464
465  return false;
466}
467
468// Computes the Reg+Offset to get to an object.
469bool ARMFastISel::ARMComputeRegOffset(const Value *Obj, unsigned &Reg,
470                                      int &Offset) {
471  // Some boilerplate from the X86 FastISel.
472  const User *U = NULL;
473  unsigned Opcode = Instruction::UserOp1;
474  if (const Instruction *I = dyn_cast<Instruction>(Obj)) {
475    // Don't walk into other basic blocks; it's possible we haven't
476    // visited them yet, so the instructions may not yet be assigned
477    // virtual registers.
478    if (FuncInfo.MBBMap[I->getParent()] != FuncInfo.MBB)
479      return false;
480    Opcode = I->getOpcode();
481    U = I;
482  } else if (const ConstantExpr *C = dyn_cast<ConstantExpr>(Obj)) {
483    Opcode = C->getOpcode();
484    U = C;
485  }
486
487  if (const PointerType *Ty = dyn_cast<PointerType>(Obj->getType()))
488    if (Ty->getAddressSpace() > 255)
489      // Fast instruction selection doesn't support the special
490      // address spaces.
491      return false;
492
493  switch (Opcode) {
494    default:
495    break;
496    case Instruction::Alloca: {
497      assert(false && "Alloca should have been handled earlier!");
498      return false;
499    }
500  }
501
502  // FIXME: Handle global variables.
503  if (const GlobalValue *GV = dyn_cast<GlobalValue>(Obj)) {
504    (void)GV;
505    return false;
506  }
507
508  // Try to get this in a register if nothing else has worked.
509  Reg = getRegForValue(Obj);
510  if (Reg == 0) return false;
511
512  // Since the offset may be too large for the load instruction
513  // get the reg+offset into a register.
514  // TODO: Verify the additions work, otherwise we'll need to add the
515  // offset instead of 0 to the instructions and do all sorts of operand
516  // munging.
517  // TODO: Optimize this somewhat.
518  if (Offset != 0) {
519    ARMCC::CondCodes Pred = ARMCC::AL;
520    unsigned PredReg = 0;
521
522    if (!isThumb)
523      emitARMRegPlusImmediate(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
524                              Reg, Reg, Offset, Pred, PredReg,
525                              static_cast<const ARMBaseInstrInfo&>(TII));
526    else {
527      assert(AFI->isThumb2Function());
528      emitT2RegPlusImmediate(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
529                             Reg, Reg, Offset, Pred, PredReg,
530                             static_cast<const ARMBaseInstrInfo&>(TII));
531    }
532  }
533  return true;
534}
535
536bool ARMFastISel::ARMLoadAlloca(const Instruction *I, EVT VT) {
537  Value *Op0 = I->getOperand(0);
538
539  // Verify it's an alloca.
540  if (const AllocaInst *AI = dyn_cast<AllocaInst>(Op0)) {
541    DenseMap<const AllocaInst*, int>::iterator SI =
542      FuncInfo.StaticAllocaMap.find(AI);
543
544    if (SI != FuncInfo.StaticAllocaMap.end()) {
545      TargetRegisterClass* RC = TLI.getRegClassFor(VT);
546      unsigned ResultReg = createResultReg(RC);
547      TII.loadRegFromStackSlot(*FuncInfo.MBB, *FuncInfo.InsertPt,
548                               ResultReg, SI->second, RC,
549                               TM.getRegisterInfo());
550      UpdateValueMap(I, ResultReg);
551      return true;
552    }
553  }
554  return false;
555}
556
557bool ARMFastISel::ARMEmitLoad(EVT VT, unsigned &ResultReg,
558                              unsigned Reg, int Offset) {
559
560  assert(VT.isSimple() && "Non-simple types are invalid here!");
561  unsigned Opc;
562  bool isFloat = false;
563  switch (VT.getSimpleVT().SimpleTy) {
564    default:
565      // This is mostly going to be Neon/vector support.
566      return false;
567    case MVT::i16:
568      Opc = isThumb ? ARM::tLDRH : ARM::LDRH;
569      VT = MVT::i32;
570      break;
571    case MVT::i8:
572      Opc = isThumb ? ARM::tLDRB : ARM::LDRB;
573      VT = MVT::i32;
574      break;
575    case MVT::i32:
576      Opc = isThumb ? ARM::tLDR : ARM::LDR;
577      break;
578    case MVT::f32:
579      Opc = ARM::VLDRS;
580      isFloat = true;
581      break;
582    case MVT::f64:
583      Opc = ARM::VLDRD;
584      isFloat = true;
585      break;
586  }
587
588  ResultReg = createResultReg(TLI.getRegClassFor(VT));
589
590  // TODO: Fix the Addressing modes so that these can share some code.
591  // Since this is a Thumb1 load this will work in Thumb1 or 2 mode.
592  // The thumb addressing mode has operands swapped from the arm addressing
593  // mode, the floating point one only has two operands.
594  if (isFloat)
595    AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
596                            TII.get(Opc), ResultReg)
597                    .addReg(Reg).addImm(Offset));
598  else if (isThumb)
599    AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
600                            TII.get(Opc), ResultReg)
601                    .addReg(Reg).addImm(Offset).addReg(0));
602  else
603    AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
604                            TII.get(Opc), ResultReg)
605                    .addReg(Reg).addReg(0).addImm(Offset));
606  return true;
607}
608
609bool ARMFastISel::SelectLoad(const Instruction *I) {
610  // Verify we have a legal type before going any further.
611  EVT VT;
612  if (!isLoadTypeLegal(I->getType(), VT))
613    return false;
614
615  // If we're an alloca we know we have a frame index and can emit the load
616  // directly in short order.
617  if (ARMLoadAlloca(I, VT))
618    return true;
619
620  // Our register and offset with innocuous defaults.
621  unsigned Reg = 0;
622  int Offset = 0;
623
624  // See if we can handle this as Reg + Offset
625  if (!ARMComputeRegOffset(I->getOperand(0), Reg, Offset))
626    return false;
627
628  unsigned ResultReg;
629  if (!ARMEmitLoad(VT, ResultReg, Reg, Offset /* 0 */)) return false;
630
631  UpdateValueMap(I, ResultReg);
632  return true;
633}
634
635bool ARMFastISel::ARMStoreAlloca(const Instruction *I, unsigned SrcReg, EVT VT){
636  Value *Op1 = I->getOperand(1);
637
638  // Verify it's an alloca.
639  if (const AllocaInst *AI = dyn_cast<AllocaInst>(Op1)) {
640    DenseMap<const AllocaInst*, int>::iterator SI =
641      FuncInfo.StaticAllocaMap.find(AI);
642
643    if (SI != FuncInfo.StaticAllocaMap.end()) {
644      TargetRegisterClass* RC = TLI.getRegClassFor(VT);
645      assert(SrcReg != 0 && "Nothing to store!");
646      TII.storeRegToStackSlot(*FuncInfo.MBB, *FuncInfo.InsertPt,
647                              SrcReg, true /*isKill*/, SI->second, RC,
648                              TM.getRegisterInfo());
649      return true;
650    }
651  }
652  return false;
653}
654
655bool ARMFastISel::ARMEmitStore(EVT VT, unsigned SrcReg,
656                               unsigned DstReg, int Offset) {
657  unsigned StrOpc;
658  bool isFloat = false;
659  switch (VT.getSimpleVT().SimpleTy) {
660    default: return false;
661    case MVT::i1:
662    case MVT::i8: StrOpc = isThumb ? ARM::tSTRB : ARM::STRB; break;
663    case MVT::i16: StrOpc = isThumb ? ARM::tSTRH : ARM::STRH; break;
664    case MVT::i32: StrOpc = isThumb ? ARM::tSTR : ARM::STR; break;
665    case MVT::f32:
666      if (!Subtarget->hasVFP2()) return false;
667      StrOpc = ARM::VSTRS;
668      isFloat = true;
669      break;
670    case MVT::f64:
671      if (!Subtarget->hasVFP2()) return false;
672      StrOpc = ARM::VSTRD;
673      isFloat = true;
674      break;
675  }
676
677  // The thumb addressing mode has operands swapped from the arm addressing
678  // mode, the floating point one only has two operands.
679  if (isFloat)
680    AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
681                            TII.get(StrOpc), SrcReg)
682                    .addReg(DstReg).addImm(Offset));
683  else if (isThumb)
684    AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
685                            TII.get(StrOpc), SrcReg)
686                    .addReg(DstReg).addImm(Offset).addReg(0));
687
688  else
689    AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
690                            TII.get(StrOpc), SrcReg)
691                    .addReg(DstReg).addReg(0).addImm(Offset));
692
693  return true;
694}
695
696bool ARMFastISel::SelectStore(const Instruction *I) {
697  Value *Op0 = I->getOperand(0);
698  unsigned SrcReg = 0;
699
700  // Yay type legalization
701  EVT VT;
702  if (!isLoadTypeLegal(I->getOperand(0)->getType(), VT))
703    return false;
704
705  // Get the value to be stored into a register.
706  SrcReg = getRegForValue(Op0);
707  if (SrcReg == 0)
708    return false;
709
710  // If we're an alloca we know we have a frame index and can emit the store
711  // quickly.
712  if (ARMStoreAlloca(I, SrcReg, VT))
713    return true;
714
715  // Our register and offset with innocuous defaults.
716  unsigned Reg = 0;
717  int Offset = 0;
718
719  // See if we can handle this as Reg + Offset
720  if (!ARMComputeRegOffset(I->getOperand(1), Reg, Offset))
721    return false;
722
723  if (!ARMEmitStore(VT, SrcReg, Reg, Offset /* 0 */)) return false;
724
725  return true;
726}
727
728static ARMCC::CondCodes getComparePred(CmpInst::Predicate Pred) {
729  switch (Pred) {
730    // Needs two compares...
731    case CmpInst::FCMP_ONE:
732    case CmpInst::FCMP_UEQ:
733    default:
734      assert(false && "Unhandled CmpInst::Predicate!");
735      return ARMCC::AL;
736    case CmpInst::ICMP_EQ:
737    case CmpInst::FCMP_OEQ:
738      return ARMCC::EQ;
739    case CmpInst::ICMP_SGT:
740    case CmpInst::FCMP_OGT:
741      return ARMCC::GT;
742    case CmpInst::ICMP_SGE:
743    case CmpInst::FCMP_OGE:
744      return ARMCC::GE;
745    case CmpInst::ICMP_UGT:
746    case CmpInst::FCMP_UGT:
747      return ARMCC::HI;
748    case CmpInst::FCMP_OLT:
749      return ARMCC::MI;
750    case CmpInst::ICMP_ULE:
751    case CmpInst::FCMP_OLE:
752      return ARMCC::LS;
753    case CmpInst::FCMP_ORD:
754      return ARMCC::VC;
755    case CmpInst::FCMP_UNO:
756      return ARMCC::VS;
757    case CmpInst::FCMP_UGE:
758      return ARMCC::PL;
759    case CmpInst::ICMP_SLT:
760    case CmpInst::FCMP_ULT:
761      return ARMCC::LT;
762    case CmpInst::ICMP_SLE:
763    case CmpInst::FCMP_ULE:
764      return ARMCC::LE;
765    case CmpInst::FCMP_UNE:
766    case CmpInst::ICMP_NE:
767      return ARMCC::NE;
768    case CmpInst::ICMP_UGE:
769      return ARMCC::HS;
770    case CmpInst::ICMP_ULT:
771      return ARMCC::LO;
772  }
773}
774
775bool ARMFastISel::SelectBranch(const Instruction *I) {
776  const BranchInst *BI = cast<BranchInst>(I);
777  MachineBasicBlock *TBB = FuncInfo.MBBMap[BI->getSuccessor(0)];
778  MachineBasicBlock *FBB = FuncInfo.MBBMap[BI->getSuccessor(1)];
779
780  // Simple branch support.
781  // TODO: Hopefully we've already handled the condition since we won't
782  // have left an update in the value map. See the TODO below in SelectCMP.
783  Value *Cond = BI->getCondition();
784  unsigned CondReg = getRegForValue(Cond);
785  if (CondReg == 0) return false;
786
787  ARMCC::CondCodes ARMPred = ARMCC::NE;
788  CmpInst *CI = dyn_cast<CmpInst>(Cond);
789  if (!CI) return false;
790
791  // Get the compare predicate.
792  ARMPred = getComparePred(CI->getPredicate());
793
794  // We may not handle every CC for now.
795  if (ARMPred == ARMCC::AL) return false;
796
797  unsigned BrOpc = isThumb ? ARM::t2Bcc : ARM::Bcc;
798  BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(BrOpc))
799                  .addMBB(TBB).addImm(ARMPred).addReg(CondReg);
800  FastEmitBranch(FBB, DL);
801  FuncInfo.MBB->addSuccessor(TBB);
802  return true;
803}
804
805bool ARMFastISel::SelectCmp(const Instruction *I) {
806  const CmpInst *CI = cast<CmpInst>(I);
807
808  EVT VT;
809  const Type *Ty = CI->getOperand(0)->getType();
810  if (!isTypeLegal(Ty, VT))
811    return false;
812
813  bool isFloat = (Ty->isDoubleTy() || Ty->isFloatTy());
814  if (isFloat && !Subtarget->hasVFP2())
815    return false;
816
817  unsigned CmpOpc;
818  unsigned DestReg;
819  switch (VT.getSimpleVT().SimpleTy) {
820    default: return false;
821    // TODO: Verify compares.
822    case MVT::f32:
823      CmpOpc = ARM::VCMPES;
824      DestReg = ARM::FPSCR;
825      break;
826    case MVT::f64:
827      CmpOpc = ARM::VCMPED;
828      DestReg = ARM::FPSCR;
829      break;
830    case MVT::i32:
831      CmpOpc = isThumb ? ARM::t2CMPrr : ARM::CMPrr;
832      DestReg = ARM::CPSR;
833      break;
834  }
835
836  unsigned Arg1 = getRegForValue(CI->getOperand(0));
837  if (Arg1 == 0) return false;
838
839  unsigned Arg2 = getRegForValue(CI->getOperand(1));
840  if (Arg2 == 0) return false;
841
842  AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(CmpOpc))
843                  .addReg(Arg1).addReg(Arg2));
844
845  // For floating point we need to move the result to a comparison register
846  // that we can then use for branches.
847  if (isFloat)
848    AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
849                            TII.get(ARM::FMSTAT)));
850
851  // Update the value to the implicit def reg.
852  UpdateValueMap(I, DestReg);
853  return true;
854}
855
856bool ARMFastISel::SelectFPExt(const Instruction *I) {
857  // Make sure we have VFP and that we're extending float to double.
858  if (!Subtarget->hasVFP2()) return false;
859
860  Value *V = I->getOperand(0);
861  if (!I->getType()->isDoubleTy() ||
862      !V->getType()->isFloatTy()) return false;
863
864  unsigned Op = getRegForValue(V);
865  if (Op == 0) return false;
866
867  unsigned Result = createResultReg(ARM::DPRRegisterClass);
868  AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
869                          TII.get(ARM::VCVTDS), Result)
870                  .addReg(Op));
871  UpdateValueMap(I, Result);
872  return true;
873}
874
875bool ARMFastISel::SelectFPTrunc(const Instruction *I) {
876  // Make sure we have VFP and that we're truncating double to float.
877  if (!Subtarget->hasVFP2()) return false;
878
879  Value *V = I->getOperand(0);
880  if (!I->getType()->isFloatTy() ||
881      !V->getType()->isDoubleTy()) return false;
882
883  unsigned Op = getRegForValue(V);
884  if (Op == 0) return false;
885
886  unsigned Result = createResultReg(ARM::SPRRegisterClass);
887  AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
888                          TII.get(ARM::VCVTSD), Result)
889                  .addReg(Op));
890  UpdateValueMap(I, Result);
891  return true;
892}
893
894bool ARMFastISel::SelectSIToFP(const Instruction *I) {
895  // Make sure we have VFP.
896  if (!Subtarget->hasVFP2()) return false;
897
898  EVT DstVT;
899  const Type *Ty = I->getType();
900  if (!isTypeLegal(Ty, DstVT))
901    return false;
902
903  unsigned Op = getRegForValue(I->getOperand(0));
904  if (Op == 0) return false;
905
906  // The conversion routine works on fp-reg to fp-reg and the operand above
907  // was an integer, move it to the fp registers if possible.
908  unsigned FP = ARMMoveToFPReg(DstVT, Op);
909  if (FP == 0) return false;
910
911  unsigned Opc;
912  if (Ty->isFloatTy()) Opc = ARM::VSITOS;
913  else if (Ty->isDoubleTy()) Opc = ARM::VSITOD;
914  else return 0;
915
916  unsigned ResultReg = createResultReg(TLI.getRegClassFor(DstVT));
917  AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(Opc),
918                          ResultReg)
919                  .addReg(FP));
920  UpdateValueMap(I, ResultReg);
921  return true;
922}
923
924bool ARMFastISel::SelectFPToSI(const Instruction *I) {
925  // Make sure we have VFP.
926  if (!Subtarget->hasVFP2()) return false;
927
928  EVT DstVT;
929  const Type *RetTy = I->getType();
930  if (!isTypeLegal(RetTy, DstVT))
931    return false;
932
933  unsigned Op = getRegForValue(I->getOperand(0));
934  if (Op == 0) return false;
935
936  unsigned Opc;
937  const Type *OpTy = I->getOperand(0)->getType();
938  if (OpTy->isFloatTy()) Opc = ARM::VTOSIZS;
939  else if (OpTy->isDoubleTy()) Opc = ARM::VTOSIZD;
940  else return 0;
941  EVT OpVT = TLI.getValueType(OpTy, true);
942
943  unsigned ResultReg = createResultReg(TLI.getRegClassFor(OpVT));
944  AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(Opc),
945                          ResultReg)
946                  .addReg(Op));
947
948  // This result needs to be in an integer register, but the conversion only
949  // takes place in fp-regs.
950  unsigned IntReg = ARMMoveToIntReg(DstVT, ResultReg);
951  if (IntReg == 0) return false;
952
953  UpdateValueMap(I, IntReg);
954  return true;
955}
956
957bool ARMFastISel::SelectBinaryOp(const Instruction *I, unsigned ISDOpcode) {
958  EVT VT  = TLI.getValueType(I->getType(), true);
959
960  // We can get here in the case when we want to use NEON for our fp
961  // operations, but can't figure out how to. Just use the vfp instructions
962  // if we have them.
963  // FIXME: It'd be nice to use NEON instructions.
964  const Type *Ty = I->getType();
965  bool isFloat = (Ty->isDoubleTy() || Ty->isFloatTy());
966  if (isFloat && !Subtarget->hasVFP2())
967    return false;
968
969  unsigned Op1 = getRegForValue(I->getOperand(0));
970  if (Op1 == 0) return false;
971
972  unsigned Op2 = getRegForValue(I->getOperand(1));
973  if (Op2 == 0) return false;
974
975  unsigned Opc;
976  bool is64bit = VT.getSimpleVT().SimpleTy == MVT::f64 ||
977                 VT.getSimpleVT().SimpleTy == MVT::i64;
978  switch (ISDOpcode) {
979    default: return false;
980    case ISD::FADD:
981      Opc = is64bit ? ARM::VADDD : ARM::VADDS;
982      break;
983    case ISD::FSUB:
984      Opc = is64bit ? ARM::VSUBD : ARM::VSUBS;
985      break;
986    case ISD::FMUL:
987      Opc = is64bit ? ARM::VMULD : ARM::VMULS;
988      break;
989  }
990  unsigned ResultReg = createResultReg(TLI.getRegClassFor(VT));
991  AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
992                          TII.get(Opc), ResultReg)
993                  .addReg(Op1).addReg(Op2));
994  UpdateValueMap(I, ResultReg);
995  return true;
996}
997
998// Call Handling Code
999
1000// This is largely taken directly from CCAssignFnForNode - we don't support
1001// varargs in FastISel so that part has been removed.
1002// TODO: We may not support all of this.
1003CCAssignFn *ARMFastISel::CCAssignFnForCall(CallingConv::ID CC, bool Return) {
1004  switch (CC) {
1005  default:
1006    llvm_unreachable("Unsupported calling convention");
1007  case CallingConv::C:
1008  case CallingConv::Fast:
1009    // Use target triple & subtarget features to do actual dispatch.
1010    if (Subtarget->isAAPCS_ABI()) {
1011      if (Subtarget->hasVFP2() &&
1012          FloatABIType == FloatABI::Hard)
1013        return (Return ? RetCC_ARM_AAPCS_VFP: CC_ARM_AAPCS_VFP);
1014      else
1015        return (Return ? RetCC_ARM_AAPCS: CC_ARM_AAPCS);
1016    } else
1017        return (Return ? RetCC_ARM_APCS: CC_ARM_APCS);
1018  case CallingConv::ARM_AAPCS_VFP:
1019    return (Return ? RetCC_ARM_AAPCS_VFP: CC_ARM_AAPCS_VFP);
1020  case CallingConv::ARM_AAPCS:
1021    return (Return ? RetCC_ARM_AAPCS: CC_ARM_AAPCS);
1022  case CallingConv::ARM_APCS:
1023    return (Return ? RetCC_ARM_APCS: CC_ARM_APCS);
1024  }
1025}
1026
1027// A quick function that will emit a call for a named libcall in F with the
1028// vector of passed arguments for the Instruction in I. We can assume that we
1029// can emit a call for any libcall we can produce. This is an abridged version
1030// of the full call infrastructure since we won't need to worry about things
1031// like computed function pointers or strange arguments at call sites.
1032// TODO: Try to unify this and the normal call bits for ARM, then try to unify
1033// with X86.
1034bool ARMFastISel::ARMEmitLibcall(const Instruction *I, RTLIB::Libcall Call) {
1035  CallingConv::ID CC = TLI.getLibcallCallingConv(Call);
1036
1037  // Handle *simple* calls for now.
1038  const Type *RetTy = I->getType();
1039  EVT RetVT;
1040  if (RetTy->isVoidTy())
1041    RetVT = MVT::isVoid;
1042  else if (!isTypeLegal(RetTy, RetVT))
1043    return false;
1044
1045  // For now we're using BLX etc on the assumption that we have v5t ops.
1046  if (!Subtarget->hasV5TOps()) return false;
1047
1048  // Abridged from the X86 FastISel call selection mechanism
1049  SmallVector<Value*, 8> Args;
1050  SmallVector<unsigned, 8> ArgRegs;
1051  SmallVector<EVT, 8> ArgVTs;
1052  SmallVector<ISD::ArgFlagsTy, 8> ArgFlags;
1053  Args.reserve(I->getNumOperands());
1054  ArgRegs.reserve(I->getNumOperands());
1055  ArgVTs.reserve(I->getNumOperands());
1056  ArgFlags.reserve(I->getNumOperands());
1057  for (unsigned i = 0; i < I->getNumOperands(); ++i) {
1058    Value *Op = I->getOperand(i);
1059    unsigned Arg = getRegForValue(Op);
1060    if (Arg == 0) return false;
1061
1062    const Type *ArgTy = Op->getType();
1063    EVT ArgVT;
1064    if (!isTypeLegal(ArgTy, ArgVT)) return false;
1065
1066    ISD::ArgFlagsTy Flags;
1067    unsigned OriginalAlignment = TD.getABITypeAlignment(ArgTy);
1068    Flags.setOrigAlign(OriginalAlignment);
1069
1070    Args.push_back(Op);
1071    ArgRegs.push_back(Arg);
1072    ArgVTs.push_back(ArgVT);
1073    ArgFlags.push_back(Flags);
1074  }
1075
1076  SmallVector<CCValAssign, 16> ArgLocs;
1077  CCState CCInfo(CC, false, TM, ArgLocs,
1078                 I->getParent()->getParent()->getContext());
1079  CCInfo.AnalyzeCallOperands(ArgVTs, ArgFlags, CCAssignFnForCall(CC, false));
1080
1081  // Get a count of how many bytes are to be pushed on the stack.
1082  unsigned NumBytes = CCInfo.getNextStackOffset();
1083
1084  // Issue CALLSEQ_START
1085  unsigned AdjStackDown = TM.getRegisterInfo()->getCallFrameSetupOpcode();
1086  BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(AdjStackDown))
1087    .addImm(NumBytes);
1088
1089  // Process the args.
1090  SmallVector<unsigned, 4> RegArgs;
1091  for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
1092    CCValAssign &VA = ArgLocs[i];
1093    unsigned Arg = ArgRegs[VA.getValNo()];
1094    EVT ArgVT = ArgVTs[VA.getValNo()];
1095
1096    // Should we ever have to promote?
1097    switch (VA.getLocInfo()) {
1098      case CCValAssign::Full: break;
1099      default:
1100        assert(false && "Handle arg promotion for libcalls?");
1101        return false;
1102    }
1103
1104    // Now copy/store arg to correct locations.
1105    if (VA.isRegLoc()) {
1106      BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(TargetOpcode::COPY),
1107              VA.getLocReg())
1108      .addReg(Arg);
1109      RegArgs.push_back(VA.getLocReg());
1110    } else {
1111      // Need to store
1112      return false;
1113    }
1114  }
1115
1116  // Issue the call, BLXr9 for darwin, BLX otherwise. This uses V5 ops.
1117  // TODO: Turn this into the table of arm call ops.
1118  MachineInstrBuilder MIB;
1119  unsigned CallOpc;
1120  if(isThumb)
1121    CallOpc = Subtarget->isTargetDarwin() ? ARM::tBLXi_r9 : ARM::tBLXi;
1122  else
1123    CallOpc = Subtarget->isTargetDarwin() ? ARM::BLr9 : ARM::BL;
1124  MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(CallOpc))
1125        .addExternalSymbol(TLI.getLibcallName(Call));
1126
1127  // Add implicit physical register uses to the call.
1128  for (unsigned i = 0, e = RegArgs.size(); i != e; ++i)
1129    MIB.addReg(RegArgs[i]);
1130
1131  // Issue CALLSEQ_END
1132  unsigned AdjStackUp = TM.getRegisterInfo()->getCallFrameDestroyOpcode();
1133  BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(AdjStackUp))
1134    .addImm(NumBytes).addImm(0);
1135
1136  // Now the return value.
1137  SmallVector<unsigned, 4> UsedRegs;
1138  if (RetVT.getSimpleVT().SimpleTy != MVT::isVoid) {
1139    SmallVector<CCValAssign, 16> RVLocs;
1140    CCState CCInfo(CC, false, TM, RVLocs,
1141                   I->getParent()->getParent()->getContext());
1142    CCInfo.AnalyzeCallResult(RetVT, CCAssignFnForCall(CC, true));
1143
1144    // Copy all of the result registers out of their specified physreg.
1145    assert(RVLocs.size() == 1 && "Can't handle multi-value calls!");
1146    EVT CopyVT = RVLocs[0].getValVT();
1147    TargetRegisterClass* DstRC = TLI.getRegClassFor(CopyVT);
1148
1149    unsigned ResultReg = createResultReg(DstRC);
1150    BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(TargetOpcode::COPY),
1151            ResultReg).addReg(RVLocs[0].getLocReg());
1152    UsedRegs.push_back(RVLocs[0].getLocReg());
1153
1154    // Finally update the result.
1155    UpdateValueMap(I, ResultReg);
1156  }
1157
1158  // Set all unused physreg defs as dead.
1159  static_cast<MachineInstr *>(MIB)->setPhysRegsDeadExcept(UsedRegs, TRI);
1160  return true;
1161}
1162
1163bool ARMFastISel::SelectSDiv(const Instruction *I) {
1164  EVT VT;
1165  const Type *Ty = I->getType();
1166  if (!isTypeLegal(Ty, VT))
1167    return false;
1168
1169  // If we have integer div support we should have selected this automagically.
1170  // In case we have a real miss go ahead and return false and we'll pick
1171  // it up later.
1172  if (Subtarget->hasDivide()) return false;
1173
1174  // Otherwise emit a libcall.
1175  RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
1176  if (VT == MVT::i16)
1177    LC = RTLIB::SDIV_I16;
1178  else if (VT == MVT::i32)
1179    LC = RTLIB::SDIV_I32;
1180  else if (VT == MVT::i64)
1181    LC = RTLIB::SDIV_I64;
1182  else if (VT == MVT::i128)
1183    LC = RTLIB::SDIV_I128;
1184  assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unsupported SDIV!");
1185
1186  return ARMEmitLibcall(I, LC);
1187}
1188
1189// TODO: SoftFP support.
1190bool ARMFastISel::TargetSelectInstruction(const Instruction *I) {
1191  // No Thumb-1 for now.
1192  if (isThumb && !AFI->isThumb2Function()) return false;
1193
1194  switch (I->getOpcode()) {
1195    case Instruction::Load:
1196      return SelectLoad(I);
1197    case Instruction::Store:
1198      return SelectStore(I);
1199    case Instruction::Br:
1200      return SelectBranch(I);
1201    case Instruction::ICmp:
1202    case Instruction::FCmp:
1203      return SelectCmp(I);
1204    case Instruction::FPExt:
1205      return SelectFPExt(I);
1206    case Instruction::FPTrunc:
1207      return SelectFPTrunc(I);
1208    case Instruction::SIToFP:
1209      return SelectSIToFP(I);
1210    case Instruction::FPToSI:
1211      return SelectFPToSI(I);
1212    case Instruction::FAdd:
1213      return SelectBinaryOp(I, ISD::FADD);
1214    case Instruction::FSub:
1215      return SelectBinaryOp(I, ISD::FSUB);
1216    case Instruction::FMul:
1217      return SelectBinaryOp(I, ISD::FMUL);
1218    case Instruction::SDiv:
1219      return SelectSDiv(I);
1220    default: break;
1221  }
1222  return false;
1223}
1224
1225namespace llvm {
1226  llvm::FastISel *ARM::createFastISel(FunctionLoweringInfo &funcInfo) {
1227    if (EnableARMFastISel) return new ARMFastISel(funcInfo);
1228    return 0;
1229  }
1230}
1231