ARMFastISel.cpp revision d04f6a581ce06ef1cd5fe376088347ad0246e07d 
1//===-- ARMFastISel.cpp - ARM FastISel implementation ---------------------===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file defines the ARM-specific support for the FastISel class. Some
11// of the target-specific code is generated by tablegen in the file
12// ARMGenFastISel.inc, which is #included here.
13//
14//===----------------------------------------------------------------------===//
15
16#include "ARM.h"
17#include "ARMBaseInstrInfo.h"
18#include "ARMCallingConv.h"
19#include "ARMRegisterInfo.h"
20#include "ARMTargetMachine.h"
21#include "ARMSubtarget.h"
22#include "ARMConstantPoolValue.h"
23#include "MCTargetDesc/ARMAddressingModes.h"
24#include "llvm/CallingConv.h"
25#include "llvm/DerivedTypes.h"
26#include "llvm/GlobalVariable.h"
27#include "llvm/Instructions.h"
28#include "llvm/IntrinsicInst.h"
29#include "llvm/Module.h"
30#include "llvm/Operator.h"
31#include "llvm/CodeGen/Analysis.h"
32#include "llvm/CodeGen/FastISel.h"
33#include "llvm/CodeGen/FunctionLoweringInfo.h"
34#include "llvm/CodeGen/MachineInstrBuilder.h"
35#include "llvm/CodeGen/MachineModuleInfo.h"
36#include "llvm/CodeGen/MachineConstantPool.h"
37#include "llvm/CodeGen/MachineFrameInfo.h"
38#include "llvm/CodeGen/MachineMemOperand.h"
39#include "llvm/CodeGen/MachineRegisterInfo.h"
40#include "llvm/CodeGen/PseudoSourceValue.h"
41#include "llvm/Support/CallSite.h"
42#include "llvm/Support/CommandLine.h"
43#include "llvm/Support/ErrorHandling.h"
44#include "llvm/Support/GetElementPtrTypeIterator.h"
45#include "llvm/Target/TargetData.h"
46#include "llvm/Target/TargetInstrInfo.h"
47#include "llvm/Target/TargetLowering.h"
48#include "llvm/Target/TargetMachine.h"
49#include "llvm/Target/TargetOptions.h"
50using namespace llvm;
51
52static cl::opt<bool>
53DisableARMFastISel("disable-arm-fast-isel",
54                    cl::desc("Turn off experimental ARM fast-isel support"),
55                    cl::init(false), cl::Hidden);
56
57extern cl::opt<bool> EnableARMLongCalls;
58
59namespace {
60
61  // All possible address modes, plus some.
62  typedef struct Address {
63    enum {
64      RegBase,
65      FrameIndexBase
66    } BaseType;
67
68    union {
69      unsigned Reg;
70      int FI;
71    } Base;
72
73    int Offset;
74
75    // Innocuous defaults for our address.
76    Address()
77     : BaseType(RegBase), Offset(0) {
78       Base.Reg = 0;
79     }
80  } Address;
81
82class ARMFastISel : public FastISel {
83
84  /// Subtarget - Keep a pointer to the ARMSubtarget around so that we can
85  /// make the right decision when generating code for different targets.
86  const ARMSubtarget *Subtarget;
87  const TargetMachine &TM;
88  const TargetInstrInfo &TII;
89  const TargetLowering &TLI;
90  ARMFunctionInfo *AFI;
91
92  // Convenience variables to avoid some queries.
93  bool isThumb;
94  LLVMContext *Context;
95
96  public:
97    explicit ARMFastISel(FunctionLoweringInfo &funcInfo)
98    : FastISel(funcInfo),
99      TM(funcInfo.MF->getTarget()),
100      TII(*TM.getInstrInfo()),
101      TLI(*TM.getTargetLowering()) {
102      Subtarget = &TM.getSubtarget<ARMSubtarget>();
103      AFI = funcInfo.MF->getInfo<ARMFunctionInfo>();
104      isThumb = AFI->isThumbFunction();
105      Context = &funcInfo.Fn->getContext();
106    }
107
108    // Code from FastISel.cpp.
109    virtual unsigned FastEmitInst_(unsigned MachineInstOpcode,
110                                   const TargetRegisterClass *RC);
111    virtual unsigned FastEmitInst_r(unsigned MachineInstOpcode,
112                                    const TargetRegisterClass *RC,
113                                    unsigned Op0, bool Op0IsKill);
114    virtual unsigned FastEmitInst_rr(unsigned MachineInstOpcode,
115                                     const TargetRegisterClass *RC,
116                                     unsigned Op0, bool Op0IsKill,
117                                     unsigned Op1, bool Op1IsKill);
118    virtual unsigned FastEmitInst_rrr(unsigned MachineInstOpcode,
119                                      const TargetRegisterClass *RC,
120                                      unsigned Op0, bool Op0IsKill,
121                                      unsigned Op1, bool Op1IsKill,
122                                      unsigned Op2, bool Op2IsKill);
123    virtual unsigned FastEmitInst_ri(unsigned MachineInstOpcode,
124                                     const TargetRegisterClass *RC,
125                                     unsigned Op0, bool Op0IsKill,
126                                     uint64_t Imm);
127    virtual unsigned FastEmitInst_rf(unsigned MachineInstOpcode,
128                                     const TargetRegisterClass *RC,
129                                     unsigned Op0, bool Op0IsKill,
130                                     const ConstantFP *FPImm);
131    virtual unsigned FastEmitInst_rri(unsigned MachineInstOpcode,
132                                      const TargetRegisterClass *RC,
133                                      unsigned Op0, bool Op0IsKill,
134                                      unsigned Op1, bool Op1IsKill,
135                                      uint64_t Imm);
136    virtual unsigned FastEmitInst_i(unsigned MachineInstOpcode,
137                                    const TargetRegisterClass *RC,
138                                    uint64_t Imm);
139    virtual unsigned FastEmitInst_ii(unsigned MachineInstOpcode,
140                                     const TargetRegisterClass *RC,
141                                     uint64_t Imm1, uint64_t Imm2);
142
143    virtual unsigned FastEmitInst_extractsubreg(MVT RetVT,
144                                                unsigned Op0, bool Op0IsKill,
145                                                uint32_t Idx);
146
147    // Backend specific FastISel code.
148    virtual bool TargetSelectInstruction(const Instruction *I);
149    virtual unsigned TargetMaterializeConstant(const Constant *C);
150    virtual unsigned TargetMaterializeAlloca(const AllocaInst *AI);
151
152  #include "ARMGenFastISel.inc"
153
154    // Instruction selection routines.
155  private:
156    bool SelectLoad(const Instruction *I);
157    bool SelectStore(const Instruction *I);
158    bool SelectBranch(const Instruction *I);
159    bool SelectCmp(const Instruction *I);
160    bool SelectFPExt(const Instruction *I);
161    bool SelectFPTrunc(const Instruction *I);
162    bool SelectBinaryOp(const Instruction *I, unsigned ISDOpcode);
163    bool SelectSIToFP(const Instruction *I);
164    bool SelectFPToSI(const Instruction *I);
165    bool SelectSDiv(const Instruction *I);
166    bool SelectSRem(const Instruction *I);
167    bool SelectCall(const Instruction *I);
168    bool SelectSelect(const Instruction *I);
169    bool SelectRet(const Instruction *I);
170    bool SelectIntCast(const Instruction *I);
171
172    // Utility routines.
173  private:
174    bool isTypeLegal(Type *Ty, MVT &VT);
175    bool isLoadTypeLegal(Type *Ty, MVT &VT);
176    bool ARMEmitLoad(EVT VT, unsigned &ResultReg, Address &Addr);
177    bool ARMEmitStore(EVT VT, unsigned SrcReg, Address &Addr);
178    bool ARMComputeAddress(const Value *Obj, Address &Addr);
179    void ARMSimplifyAddress(Address &Addr, EVT VT);
180    unsigned ARMMaterializeFP(const ConstantFP *CFP, EVT VT);
181    unsigned ARMMaterializeInt(const Constant *C, EVT VT);
182    unsigned ARMMaterializeGV(const GlobalValue *GV, EVT VT);
183    unsigned ARMMoveToFPReg(EVT VT, unsigned SrcReg);
184    unsigned ARMMoveToIntReg(EVT VT, unsigned SrcReg);
185    unsigned ARMSelectCallOp(const GlobalValue *GV);
186
187    // Call handling routines.
188  private:
189    bool FastEmitExtend(ISD::NodeType Opc, EVT DstVT, unsigned Src, EVT SrcVT,
190                        unsigned &ResultReg);
191    CCAssignFn *CCAssignFnForCall(CallingConv::ID CC, bool Return);
192    bool ProcessCallArgs(SmallVectorImpl<Value*> &Args,
193                         SmallVectorImpl<unsigned> &ArgRegs,
194                         SmallVectorImpl<MVT> &ArgVTs,
195                         SmallVectorImpl<ISD::ArgFlagsTy> &ArgFlags,
196                         SmallVectorImpl<unsigned> &RegArgs,
197                         CallingConv::ID CC,
198                         unsigned &NumBytes);
199    bool FinishCall(MVT RetVT, SmallVectorImpl<unsigned> &UsedRegs,
200                    const Instruction *I, CallingConv::ID CC,
201                    unsigned &NumBytes);
202    bool ARMEmitLibcall(const Instruction *I, RTLIB::Libcall Call);
203
204    // OptionalDef handling routines.
205  private:
206    bool isARMNEONPred(const MachineInstr *MI);
207    bool DefinesOptionalPredicate(MachineInstr *MI, bool *CPSR);
208    const MachineInstrBuilder &AddOptionalDefs(const MachineInstrBuilder &MIB);
209    void AddLoadStoreOperands(EVT VT, Address &Addr,
210                              const MachineInstrBuilder &MIB,
211                              unsigned Flags);
212};
213
214} // end anonymous namespace
215
216#include "ARMGenCallingConv.inc"
217
218// DefinesOptionalPredicate - This is different from DefinesPredicate in that
219// we don't care about implicit defs here, just places we'll need to add a
220// default CCReg argument. Sets CPSR if we're setting CPSR instead of CCR.
221bool ARMFastISel::DefinesOptionalPredicate(MachineInstr *MI, bool *CPSR) {
222  const MCInstrDesc &MCID = MI->getDesc();
223  if (!MCID.hasOptionalDef())
224    return false;
225
226  // Look to see if our OptionalDef is defining CPSR or CCR.
227  for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
228    const MachineOperand &MO = MI->getOperand(i);
229    if (!MO.isReg() || !MO.isDef()) continue;
230    if (MO.getReg() == ARM::CPSR)
231      *CPSR = true;
232  }
233  return true;
234}
235
236bool ARMFastISel::isARMNEONPred(const MachineInstr *MI) {
237  const MCInstrDesc &MCID = MI->getDesc();
238
239  // If we're a thumb2 or not NEON function we were handled via isPredicable.
240  if ((MCID.TSFlags & ARMII::DomainMask) != ARMII::DomainNEON ||
241       AFI->isThumb2Function())
242    return false;
243
244  for (unsigned i = 0, e = MCID.getNumOperands(); i != e; ++i)
245    if (MCID.OpInfo[i].isPredicate())
246      return true;
247
248  return false;
249}
250
251// If the machine is predicable go ahead and add the predicate operands, if
252// it needs default CC operands add those.
253// TODO: If we want to support thumb1 then we'll need to deal with optional
254// CPSR defs that need to be added before the remaining operands. See s_cc_out
255// for descriptions why.
256const MachineInstrBuilder &
257ARMFastISel::AddOptionalDefs(const MachineInstrBuilder &MIB) {
258  MachineInstr *MI = &*MIB;
259
260  // Do we use a predicate? or...
261  // Are we NEON in ARM mode and have a predicate operand? If so, I know
262  // we're not predicable but add it anyways.
263  if (TII.isPredicable(MI) || isARMNEONPred(MI))
264    AddDefaultPred(MIB);
265
266  // Do we optionally set a predicate?  Preds is size > 0 iff the predicate
267  // defines CPSR. All other OptionalDefines in ARM are the CCR register.
268  bool CPSR = false;
269  if (DefinesOptionalPredicate(MI, &CPSR)) {
270    if (CPSR)
271      AddDefaultT1CC(MIB);
272    else
273      AddDefaultCC(MIB);
274  }
275  return MIB;
276}
277
278unsigned ARMFastISel::FastEmitInst_(unsigned MachineInstOpcode,
279                                    const TargetRegisterClass* RC) {
280  unsigned ResultReg = createResultReg(RC);
281  const MCInstrDesc &II = TII.get(MachineInstOpcode);
282
283  AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II, ResultReg));
284  return ResultReg;
285}
286
287unsigned ARMFastISel::FastEmitInst_r(unsigned MachineInstOpcode,
288                                     const TargetRegisterClass *RC,
289                                     unsigned Op0, bool Op0IsKill) {
290  unsigned ResultReg = createResultReg(RC);
291  const MCInstrDesc &II = TII.get(MachineInstOpcode);
292
293  if (II.getNumDefs() >= 1)
294    AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II, ResultReg)
295                   .addReg(Op0, Op0IsKill * RegState::Kill));
296  else {
297    AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II)
298                   .addReg(Op0, Op0IsKill * RegState::Kill));
299    AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
300                   TII.get(TargetOpcode::COPY), ResultReg)
301                   .addReg(II.ImplicitDefs[0]));
302  }
303  return ResultReg;
304}
305
306unsigned ARMFastISel::FastEmitInst_rr(unsigned MachineInstOpcode,
307                                      const TargetRegisterClass *RC,
308                                      unsigned Op0, bool Op0IsKill,
309                                      unsigned Op1, bool Op1IsKill) {
310  unsigned ResultReg = createResultReg(RC);
311  const MCInstrDesc &II = TII.get(MachineInstOpcode);
312
313  if (II.getNumDefs() >= 1)
314    AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II, ResultReg)
315                   .addReg(Op0, Op0IsKill * RegState::Kill)
316                   .addReg(Op1, Op1IsKill * RegState::Kill));
317  else {
318    AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II)
319                   .addReg(Op0, Op0IsKill * RegState::Kill)
320                   .addReg(Op1, Op1IsKill * RegState::Kill));
321    AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
322                           TII.get(TargetOpcode::COPY), ResultReg)
323                   .addReg(II.ImplicitDefs[0]));
324  }
325  return ResultReg;
326}
327
328unsigned ARMFastISel::FastEmitInst_rrr(unsigned MachineInstOpcode,
329                                       const TargetRegisterClass *RC,
330                                       unsigned Op0, bool Op0IsKill,
331                                       unsigned Op1, bool Op1IsKill,
332                                       unsigned Op2, bool Op2IsKill) {
333  unsigned ResultReg = createResultReg(RC);
334  const MCInstrDesc &II = TII.get(MachineInstOpcode);
335
336  if (II.getNumDefs() >= 1)
337    AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II, ResultReg)
338                   .addReg(Op0, Op0IsKill * RegState::Kill)
339                   .addReg(Op1, Op1IsKill * RegState::Kill)
340                   .addReg(Op2, Op2IsKill * RegState::Kill));
341  else {
342    AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II)
343                   .addReg(Op0, Op0IsKill * RegState::Kill)
344                   .addReg(Op1, Op1IsKill * RegState::Kill)
345                   .addReg(Op2, Op2IsKill * RegState::Kill));
346    AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
347                           TII.get(TargetOpcode::COPY), ResultReg)
348                   .addReg(II.ImplicitDefs[0]));
349  }
350  return ResultReg;
351}
352
353unsigned ARMFastISel::FastEmitInst_ri(unsigned MachineInstOpcode,
354                                      const TargetRegisterClass *RC,
355                                      unsigned Op0, bool Op0IsKill,
356                                      uint64_t Imm) {
357  unsigned ResultReg = createResultReg(RC);
358  const MCInstrDesc &II = TII.get(MachineInstOpcode);
359
360  if (II.getNumDefs() >= 1)
361    AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II, ResultReg)
362                   .addReg(Op0, Op0IsKill * RegState::Kill)
363                   .addImm(Imm));
364  else {
365    AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II)
366                   .addReg(Op0, Op0IsKill * RegState::Kill)
367                   .addImm(Imm));
368    AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
369                           TII.get(TargetOpcode::COPY), ResultReg)
370                   .addReg(II.ImplicitDefs[0]));
371  }
372  return ResultReg;
373}
374
375unsigned ARMFastISel::FastEmitInst_rf(unsigned MachineInstOpcode,
376                                      const TargetRegisterClass *RC,
377                                      unsigned Op0, bool Op0IsKill,
378                                      const ConstantFP *FPImm) {
379  unsigned ResultReg = createResultReg(RC);
380  const MCInstrDesc &II = TII.get(MachineInstOpcode);
381
382  if (II.getNumDefs() >= 1)
383    AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II, ResultReg)
384                   .addReg(Op0, Op0IsKill * RegState::Kill)
385                   .addFPImm(FPImm));
386  else {
387    AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II)
388                   .addReg(Op0, Op0IsKill * RegState::Kill)
389                   .addFPImm(FPImm));
390    AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
391                           TII.get(TargetOpcode::COPY), ResultReg)
392                   .addReg(II.ImplicitDefs[0]));
393  }
394  return ResultReg;
395}
396
397unsigned ARMFastISel::FastEmitInst_rri(unsigned MachineInstOpcode,
398                                       const TargetRegisterClass *RC,
399                                       unsigned Op0, bool Op0IsKill,
400                                       unsigned Op1, bool Op1IsKill,
401                                       uint64_t Imm) {
402  unsigned ResultReg = createResultReg(RC);
403  const MCInstrDesc &II = TII.get(MachineInstOpcode);
404
405  if (II.getNumDefs() >= 1)
406    AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II, ResultReg)
407                   .addReg(Op0, Op0IsKill * RegState::Kill)
408                   .addReg(Op1, Op1IsKill * RegState::Kill)
409                   .addImm(Imm));
410  else {
411    AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II)
412                   .addReg(Op0, Op0IsKill * RegState::Kill)
413                   .addReg(Op1, Op1IsKill * RegState::Kill)
414                   .addImm(Imm));
415    AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
416                           TII.get(TargetOpcode::COPY), ResultReg)
417                   .addReg(II.ImplicitDefs[0]));
418  }
419  return ResultReg;
420}
421
422unsigned ARMFastISel::FastEmitInst_i(unsigned MachineInstOpcode,
423                                     const TargetRegisterClass *RC,
424                                     uint64_t Imm) {
425  unsigned ResultReg = createResultReg(RC);
426  const MCInstrDesc &II = TII.get(MachineInstOpcode);
427
428  if (II.getNumDefs() >= 1)
429    AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II, ResultReg)
430                   .addImm(Imm));
431  else {
432    AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II)
433                   .addImm(Imm));
434    AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
435                           TII.get(TargetOpcode::COPY), ResultReg)
436                   .addReg(II.ImplicitDefs[0]));
437  }
438  return ResultReg;
439}
440
441unsigned ARMFastISel::FastEmitInst_ii(unsigned MachineInstOpcode,
442                                      const TargetRegisterClass *RC,
443                                      uint64_t Imm1, uint64_t Imm2) {
444  unsigned ResultReg = createResultReg(RC);
445  const MCInstrDesc &II = TII.get(MachineInstOpcode);
446
447  if (II.getNumDefs() >= 1)
448    AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II, ResultReg)
449                    .addImm(Imm1).addImm(Imm2));
450  else {
451    AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II)
452                    .addImm(Imm1).addImm(Imm2));
453    AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
454                            TII.get(TargetOpcode::COPY),
455                            ResultReg)
456                    .addReg(II.ImplicitDefs[0]));
457  }
458  return ResultReg;
459}
460
461unsigned ARMFastISel::FastEmitInst_extractsubreg(MVT RetVT,
462                                                 unsigned Op0, bool Op0IsKill,
463                                                 uint32_t Idx) {
464  unsigned ResultReg = createResultReg(TLI.getRegClassFor(RetVT));
465  assert(TargetRegisterInfo::isVirtualRegister(Op0) &&
466         "Cannot yet extract from physregs");
467  AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt,
468                         DL, TII.get(TargetOpcode::COPY), ResultReg)
469                 .addReg(Op0, getKillRegState(Op0IsKill), Idx));
470  return ResultReg;
471}
472
473// TODO: Don't worry about 64-bit now, but when this is fixed remove the
474// checks from the various callers.
475unsigned ARMFastISel::ARMMoveToFPReg(EVT VT, unsigned SrcReg) {
476  if (VT == MVT::f64) return 0;
477
478  unsigned MoveReg = createResultReg(TLI.getRegClassFor(VT));
479  AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
480                          TII.get(ARM::VMOVRS), MoveReg)
481                  .addReg(SrcReg));
482  return MoveReg;
483}
484
485unsigned ARMFastISel::ARMMoveToIntReg(EVT VT, unsigned SrcReg) {
486  if (VT == MVT::i64) return 0;
487
488  unsigned MoveReg = createResultReg(TLI.getRegClassFor(VT));
489  AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
490                          TII.get(ARM::VMOVSR), MoveReg)
491                  .addReg(SrcReg));
492  return MoveReg;
493}
494
495// For double width floating point we need to materialize two constants
496// (the high and the low) into integer registers then use a move to get
497// the combined constant into an FP reg.
498unsigned ARMFastISel::ARMMaterializeFP(const ConstantFP *CFP, EVT VT) {
499  const APFloat Val = CFP->getValueAPF();
500  bool is64bit = VT == MVT::f64;
501
502  // This checks to see if we can use VFP3 instructions to materialize
503  // a constant, otherwise we have to go through the constant pool.
504  if (TLI.isFPImmLegal(Val, VT)) {
505    unsigned Opc = is64bit ? ARM::FCONSTD : ARM::FCONSTS;
506    unsigned DestReg = createResultReg(TLI.getRegClassFor(VT));
507    AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(Opc),
508                            DestReg)
509                    .addFPImm(CFP));
510    return DestReg;
511  }
512
513  // Require VFP2 for loading fp constants.
514  if (!Subtarget->hasVFP2()) return false;
515
516  // MachineConstantPool wants an explicit alignment.
517  unsigned Align = TD.getPrefTypeAlignment(CFP->getType());
518  if (Align == 0) {
519    // TODO: Figure out if this is correct.
520    Align = TD.getTypeAllocSize(CFP->getType());
521  }
522  unsigned Idx = MCP.getConstantPoolIndex(cast<Constant>(CFP), Align);
523  unsigned DestReg = createResultReg(TLI.getRegClassFor(VT));
524  unsigned Opc = is64bit ? ARM::VLDRD : ARM::VLDRS;
525
526  // The extra reg is for addrmode5.
527  AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(Opc),
528                          DestReg)
529                  .addConstantPoolIndex(Idx)
530                  .addReg(0));
531  return DestReg;
532}
533
534unsigned ARMFastISel::ARMMaterializeInt(const Constant *C, EVT VT) {
535
536  // For now 32-bit only.
537  if (VT != MVT::i32) return false;
538
539  unsigned DestReg = createResultReg(TLI.getRegClassFor(VT));
540
541  // If we can do this in a single instruction without a constant pool entry
542  // do so now.
543  const ConstantInt *CI = cast<ConstantInt>(C);
544  if (Subtarget->hasV6T2Ops() && isUInt<16>(CI->getSExtValue())) {
545    unsigned Opc = isThumb ? ARM::t2MOVi16 : ARM::MOVi16;
546    AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
547                            TII.get(Opc), DestReg)
548                    .addImm(CI->getSExtValue()));
549    return DestReg;
550  }
551
552  // MachineConstantPool wants an explicit alignment.
553  unsigned Align = TD.getPrefTypeAlignment(C->getType());
554  if (Align == 0) {
555    // TODO: Figure out if this is correct.
556    Align = TD.getTypeAllocSize(C->getType());
557  }
558  unsigned Idx = MCP.getConstantPoolIndex(C, Align);
559
560  if (isThumb)
561    AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
562                            TII.get(ARM::t2LDRpci), DestReg)
563                    .addConstantPoolIndex(Idx));
564  else
565    // The extra immediate is for addrmode2.
566    AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
567                            TII.get(ARM::LDRcp), DestReg)
568                    .addConstantPoolIndex(Idx)
569                    .addImm(0));
570
571  return DestReg;
572}
573
574unsigned ARMFastISel::ARMMaterializeGV(const GlobalValue *GV, EVT VT) {
575  // For now 32-bit only.
576  if (VT != MVT::i32) return 0;
577
578  Reloc::Model RelocM = TM.getRelocationModel();
579
580  // TODO: Need more magic for ARM PIC.
581  if (!isThumb && (RelocM == Reloc::PIC_)) return 0;
582
583  // MachineConstantPool wants an explicit alignment.
584  unsigned Align = TD.getPrefTypeAlignment(GV->getType());
585  if (Align == 0) {
586    // TODO: Figure out if this is correct.
587    Align = TD.getTypeAllocSize(GV->getType());
588  }
589
590  // Grab index.
591  unsigned PCAdj = (RelocM != Reloc::PIC_) ? 0 : (Subtarget->isThumb() ? 4 : 8);
592  unsigned Id = AFI->createPICLabelUId();
593  ARMConstantPoolValue *CPV = new ARMConstantPoolValue(GV, Id,
594                                                       ARMCP::CPValue, PCAdj);
595  unsigned Idx = MCP.getConstantPoolIndex(CPV, Align);
596
597  // Load value.
598  MachineInstrBuilder MIB;
599  unsigned DestReg = createResultReg(TLI.getRegClassFor(VT));
600  if (isThumb) {
601    unsigned Opc = (RelocM != Reloc::PIC_) ? ARM::t2LDRpci : ARM::t2LDRpci_pic;
602    MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(Opc), DestReg)
603          .addConstantPoolIndex(Idx);
604    if (RelocM == Reloc::PIC_)
605      MIB.addImm(Id);
606  } else {
607    // The extra immediate is for addrmode2.
608    MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(ARM::LDRcp),
609                  DestReg)
610          .addConstantPoolIndex(Idx)
611          .addImm(0);
612  }
613  AddOptionalDefs(MIB);
614
615  if (Subtarget->GVIsIndirectSymbol(GV, RelocM)) {
616    unsigned NewDestReg = createResultReg(TLI.getRegClassFor(VT));
617    if (isThumb)
618      MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(ARM::t2LDRi12),
619                    NewDestReg)
620            .addReg(DestReg)
621            .addImm(0);
622    else
623      MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(ARM::LDRi12),
624                    NewDestReg)
625            .addReg(DestReg)
626            .addImm(0);
627    DestReg = NewDestReg;
628    AddOptionalDefs(MIB);
629  }
630
631  return DestReg;
632}
633
634unsigned ARMFastISel::TargetMaterializeConstant(const Constant *C) {
635  EVT VT = TLI.getValueType(C->getType(), true);
636
637  // Only handle simple types.
638  if (!VT.isSimple()) return 0;
639
640  if (const ConstantFP *CFP = dyn_cast<ConstantFP>(C))
641    return ARMMaterializeFP(CFP, VT);
642  else if (const GlobalValue *GV = dyn_cast<GlobalValue>(C))
643    return ARMMaterializeGV(GV, VT);
644  else if (isa<ConstantInt>(C))
645    return ARMMaterializeInt(C, VT);
646
647  return 0;
648}
649
650unsigned ARMFastISel::TargetMaterializeAlloca(const AllocaInst *AI) {
651  // Don't handle dynamic allocas.
652  if (!FuncInfo.StaticAllocaMap.count(AI)) return 0;
653
654  MVT VT;
655  if (!isLoadTypeLegal(AI->getType(), VT)) return false;
656
657  DenseMap<const AllocaInst*, int>::iterator SI =
658    FuncInfo.StaticAllocaMap.find(AI);
659
660  // This will get lowered later into the correct offsets and registers
661  // via rewriteXFrameIndex.
662  if (SI != FuncInfo.StaticAllocaMap.end()) {
663    TargetRegisterClass* RC = TLI.getRegClassFor(VT);
664    unsigned ResultReg = createResultReg(RC);
665    unsigned Opc = isThumb ? ARM::t2ADDri : ARM::ADDri;
666    AddOptionalDefs(BuildMI(*FuncInfo.MBB, *FuncInfo.InsertPt, DL,
667                            TII.get(Opc), ResultReg)
668                            .addFrameIndex(SI->second)
669                            .addImm(0));
670    return ResultReg;
671  }
672
673  return 0;
674}
675
676bool ARMFastISel::isTypeLegal(Type *Ty, MVT &VT) {
677  EVT evt = TLI.getValueType(Ty, true);
678
679  // Only handle simple types.
680  if (evt == MVT::Other || !evt.isSimple()) return false;
681  VT = evt.getSimpleVT();
682
683  // Handle all legal types, i.e. a register that will directly hold this
684  // value.
685  return TLI.isTypeLegal(VT);
686}
687
688bool ARMFastISel::isLoadTypeLegal(Type *Ty, MVT &VT) {
689  if (isTypeLegal(Ty, VT)) return true;
690
691  // If this is a type than can be sign or zero-extended to a basic operation
692  // go ahead and accept it now.
693  if (VT == MVT::i8 || VT == MVT::i16)
694    return true;
695
696  return false;
697}
698
699// Computes the address to get to an object.
700bool ARMFastISel::ARMComputeAddress(const Value *Obj, Address &Addr) {
701  // Some boilerplate from the X86 FastISel.
702  const User *U = NULL;
703  unsigned Opcode = Instruction::UserOp1;
704  if (const Instruction *I = dyn_cast<Instruction>(Obj)) {
705    // Don't walk into other basic blocks unless the object is an alloca from
706    // another block, otherwise it may not have a virtual register assigned.
707    if (FuncInfo.StaticAllocaMap.count(static_cast<const AllocaInst *>(Obj)) ||
708        FuncInfo.MBBMap[I->getParent()] == FuncInfo.MBB) {
709      Opcode = I->getOpcode();
710      U = I;
711    }
712  } else if (const ConstantExpr *C = dyn_cast<ConstantExpr>(Obj)) {
713    Opcode = C->getOpcode();
714    U = C;
715  }
716
717  if (PointerType *Ty = dyn_cast<PointerType>(Obj->getType()))
718    if (Ty->getAddressSpace() > 255)
719      // Fast instruction selection doesn't support the special
720      // address spaces.
721      return false;
722
723  switch (Opcode) {
724    default:
725    break;
726    case Instruction::BitCast: {
727      // Look through bitcasts.
728      return ARMComputeAddress(U->getOperand(0), Addr);
729    }
730    case Instruction::IntToPtr: {
731      // Look past no-op inttoptrs.
732      if (TLI.getValueType(U->getOperand(0)->getType()) == TLI.getPointerTy())
733        return ARMComputeAddress(U->getOperand(0), Addr);
734      break;
735    }
736    case Instruction::PtrToInt: {
737      // Look past no-op ptrtoints.
738      if (TLI.getValueType(U->getType()) == TLI.getPointerTy())
739        return ARMComputeAddress(U->getOperand(0), Addr);
740      break;
741    }
742    case Instruction::GetElementPtr: {
743      Address SavedAddr = Addr;
744      int TmpOffset = Addr.Offset;
745
746      // Iterate through the GEP folding the constants into offsets where
747      // we can.
748      gep_type_iterator GTI = gep_type_begin(U);
749      for (User::const_op_iterator i = U->op_begin() + 1, e = U->op_end();
750           i != e; ++i, ++GTI) {
751        const Value *Op = *i;
752        if (StructType *STy = dyn_cast<StructType>(*GTI)) {
753          const StructLayout *SL = TD.getStructLayout(STy);
754          unsigned Idx = cast<ConstantInt>(Op)->getZExtValue();
755          TmpOffset += SL->getElementOffset(Idx);
756        } else {
757          uint64_t S = TD.getTypeAllocSize(GTI.getIndexedType());
758          for (;;) {
759            if (const ConstantInt *CI = dyn_cast<ConstantInt>(Op)) {
760              // Constant-offset addressing.
761              TmpOffset += CI->getSExtValue() * S;
762              break;
763            }
764            if (isa<AddOperator>(Op) &&
765                (!isa<Instruction>(Op) ||
766                 FuncInfo.MBBMap[cast<Instruction>(Op)->getParent()]
767                 == FuncInfo.MBB) &&
768                isa<ConstantInt>(cast<AddOperator>(Op)->getOperand(1))) {
769              // An add (in the same block) with a constant operand. Fold the
770              // constant.
771              ConstantInt *CI =
772              cast<ConstantInt>(cast<AddOperator>(Op)->getOperand(1));
773              TmpOffset += CI->getSExtValue() * S;
774              // Iterate on the other operand.
775              Op = cast<AddOperator>(Op)->getOperand(0);
776              continue;
777            }
778            // Unsupported
779            goto unsupported_gep;
780          }
781        }
782      }
783
784      // Try to grab the base operand now.
785      Addr.Offset = TmpOffset;
786      if (ARMComputeAddress(U->getOperand(0), Addr)) return true;
787
788      // We failed, restore everything and try the other options.
789      Addr = SavedAddr;
790
791      unsupported_gep:
792      break;
793    }
794    case Instruction::Alloca: {
795      const AllocaInst *AI = cast<AllocaInst>(Obj);
796      DenseMap<const AllocaInst*, int>::iterator SI =
797        FuncInfo.StaticAllocaMap.find(AI);
798      if (SI != FuncInfo.StaticAllocaMap.end()) {
799        Addr.BaseType = Address::FrameIndexBase;
800        Addr.Base.FI = SI->second;
801        return true;
802      }
803      break;
804    }
805  }
806
807  // Materialize the global variable's address into a reg which can
808  // then be used later to load the variable.
809  if (const GlobalValue *GV = dyn_cast<GlobalValue>(Obj)) {
810    unsigned Tmp = ARMMaterializeGV(GV, TLI.getValueType(Obj->getType()));
811    if (Tmp == 0) return false;
812
813    Addr.Base.Reg = Tmp;
814    return true;
815  }
816
817  // Try to get this in a register if nothing else has worked.
818  if (Addr.Base.Reg == 0) Addr.Base.Reg = getRegForValue(Obj);
819  return Addr.Base.Reg != 0;
820}
821
822void ARMFastISel::ARMSimplifyAddress(Address &Addr, EVT VT) {
823
824  assert(VT.isSimple() && "Non-simple types are invalid here!");
825
826  bool needsLowering = false;
827  switch (VT.getSimpleVT().SimpleTy) {
828    default:
829      assert(false && "Unhandled load/store type!");
830    case MVT::i1:
831    case MVT::i8:
832    case MVT::i16:
833    case MVT::i32:
834      // Integer loads/stores handle 12-bit offsets.
835      needsLowering = ((Addr.Offset & 0xfff) != Addr.Offset);
836      break;
837    case MVT::f32:
838    case MVT::f64:
839      // Floating point operands handle 8-bit offsets.
840      needsLowering = ((Addr.Offset & 0xff) != Addr.Offset);
841      break;
842  }
843
844  // If this is a stack pointer and the offset needs to be simplified then
845  // put the alloca address into a register, set the base type back to
846  // register and continue. This should almost never happen.
847  if (needsLowering && Addr.BaseType == Address::FrameIndexBase) {
848    TargetRegisterClass *RC = isThumb ? ARM::tGPRRegisterClass :
849                              ARM::GPRRegisterClass;
850    unsigned ResultReg = createResultReg(RC);
851    unsigned Opc = isThumb ? ARM::t2ADDri : ARM::ADDri;
852    AddOptionalDefs(BuildMI(*FuncInfo.MBB, *FuncInfo.InsertPt, DL,
853                            TII.get(Opc), ResultReg)
854                            .addFrameIndex(Addr.Base.FI)
855                            .addImm(0));
856    Addr.Base.Reg = ResultReg;
857    Addr.BaseType = Address::RegBase;
858  }
859
860  // Since the offset is too large for the load/store instruction
861  // get the reg+offset into a register.
862  if (needsLowering) {
863    Addr.Base.Reg = FastEmit_ri_(MVT::i32, ISD::ADD, Addr.Base.Reg,
864                                 /*Op0IsKill*/false, Addr.Offset, MVT::i32);
865    Addr.Offset = 0;
866  }
867}
868
869void ARMFastISel::AddLoadStoreOperands(EVT VT, Address &Addr,
870                                       const MachineInstrBuilder &MIB,
871                                       unsigned Flags) {
872  // addrmode5 output depends on the selection dag addressing dividing the
873  // offset by 4 that it then later multiplies. Do this here as well.
874  if (VT.getSimpleVT().SimpleTy == MVT::f32 ||
875      VT.getSimpleVT().SimpleTy == MVT::f64)
876    Addr.Offset /= 4;
877
878  // Frame base works a bit differently. Handle it separately.
879  if (Addr.BaseType == Address::FrameIndexBase) {
880    int FI = Addr.Base.FI;
881    int Offset = Addr.Offset;
882    MachineMemOperand *MMO =
883          FuncInfo.MF->getMachineMemOperand(
884                                  MachinePointerInfo::getFixedStack(FI, Offset),
885                                  Flags,
886                                  MFI.getObjectSize(FI),
887                                  MFI.getObjectAlignment(FI));
888    // Now add the rest of the operands.
889    MIB.addFrameIndex(FI);
890
891    // ARM halfword load/stores need an additional operand.
892    if (!isThumb && VT.getSimpleVT().SimpleTy == MVT::i16) MIB.addReg(0);
893
894    MIB.addImm(Addr.Offset);
895    MIB.addMemOperand(MMO);
896  } else {
897    // Now add the rest of the operands.
898    MIB.addReg(Addr.Base.Reg);
899
900    // ARM halfword load/stores need an additional operand.
901    if (!isThumb && VT.getSimpleVT().SimpleTy == MVT::i16) MIB.addReg(0);
902
903    MIB.addImm(Addr.Offset);
904  }
905  AddOptionalDefs(MIB);
906}
907
908bool ARMFastISel::ARMEmitLoad(EVT VT, unsigned &ResultReg, Address &Addr) {
909
910  assert(VT.isSimple() && "Non-simple types are invalid here!");
911  unsigned Opc;
912  TargetRegisterClass *RC;
913  switch (VT.getSimpleVT().SimpleTy) {
914    // This is mostly going to be Neon/vector support.
915    default: return false;
916    case MVT::i16:
917      Opc = isThumb ? ARM::t2LDRHi12 : ARM::LDRH;
918      RC = ARM::GPRRegisterClass;
919      break;
920    case MVT::i8:
921      Opc = isThumb ? ARM::t2LDRBi12 : ARM::LDRBi12;
922      RC = ARM::GPRRegisterClass;
923      break;
924    case MVT::i32:
925      Opc = isThumb ? ARM::t2LDRi12 : ARM::LDRi12;
926      RC = ARM::GPRRegisterClass;
927      break;
928    case MVT::f32:
929      Opc = ARM::VLDRS;
930      RC = TLI.getRegClassFor(VT);
931      break;
932    case MVT::f64:
933      Opc = ARM::VLDRD;
934      RC = TLI.getRegClassFor(VT);
935      break;
936  }
937  // Simplify this down to something we can handle.
938  ARMSimplifyAddress(Addr, VT);
939
940  // Create the base instruction, then add the operands.
941  ResultReg = createResultReg(RC);
942  MachineInstrBuilder MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
943                                    TII.get(Opc), ResultReg);
944  AddLoadStoreOperands(VT, Addr, MIB, MachineMemOperand::MOLoad);
945  return true;
946}
947
948bool ARMFastISel::SelectLoad(const Instruction *I) {
949  // Verify we have a legal type before going any further.
950  MVT VT;
951  if (!isLoadTypeLegal(I->getType(), VT))
952    return false;
953
954  // See if we can handle this address.
955  Address Addr;
956  if (!ARMComputeAddress(I->getOperand(0), Addr)) return false;
957
958  unsigned ResultReg;
959  if (!ARMEmitLoad(VT, ResultReg, Addr)) return false;
960  UpdateValueMap(I, ResultReg);
961  return true;
962}
963
964bool ARMFastISel::ARMEmitStore(EVT VT, unsigned SrcReg, Address &Addr) {
965  unsigned StrOpc;
966  switch (VT.getSimpleVT().SimpleTy) {
967    // This is mostly going to be Neon/vector support.
968    default: return false;
969    case MVT::i1: {
970      unsigned Res = createResultReg(isThumb ? ARM::tGPRRegisterClass :
971                                               ARM::GPRRegisterClass);
972      unsigned Opc = isThumb ? ARM::t2ANDri : ARM::ANDri;
973      AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
974                              TII.get(Opc), Res)
975                      .addReg(SrcReg).addImm(1));
976      SrcReg = Res;
977    } // Fallthrough here.
978    case MVT::i8:
979      StrOpc = isThumb ? ARM::t2STRBi12 : ARM::STRBi12;
980      break;
981    case MVT::i16:
982      StrOpc = isThumb ? ARM::t2STRHi12 : ARM::STRH;
983      break;
984    case MVT::i32:
985      StrOpc = isThumb ? ARM::t2STRi12 : ARM::STRi12;
986      break;
987    case MVT::f32:
988      if (!Subtarget->hasVFP2()) return false;
989      StrOpc = ARM::VSTRS;
990      break;
991    case MVT::f64:
992      if (!Subtarget->hasVFP2()) return false;
993      StrOpc = ARM::VSTRD;
994      break;
995  }
996  // Simplify this down to something we can handle.
997  ARMSimplifyAddress(Addr, VT);
998
999  // Create the base instruction, then add the operands.
1000  MachineInstrBuilder MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
1001                                    TII.get(StrOpc))
1002                            .addReg(SrcReg, getKillRegState(true));
1003  AddLoadStoreOperands(VT, Addr, MIB, MachineMemOperand::MOStore);
1004  return true;
1005}
1006
1007bool ARMFastISel::SelectStore(const Instruction *I) {
1008  Value *Op0 = I->getOperand(0);
1009  unsigned SrcReg = 0;
1010
1011  // Verify we have a legal type before going any further.
1012  MVT VT;
1013  if (!isLoadTypeLegal(I->getOperand(0)->getType(), VT))
1014    return false;
1015
1016  // Get the value to be stored into a register.
1017  SrcReg = getRegForValue(Op0);
1018  if (SrcReg == 0) return false;
1019
1020  // See if we can handle this address.
1021  Address Addr;
1022  if (!ARMComputeAddress(I->getOperand(1), Addr))
1023    return false;
1024
1025  if (!ARMEmitStore(VT, SrcReg, Addr)) return false;
1026  return true;
1027}
1028
1029static ARMCC::CondCodes getComparePred(CmpInst::Predicate Pred) {
1030  switch (Pred) {
1031    // Needs two compares...
1032    case CmpInst::FCMP_ONE:
1033    case CmpInst::FCMP_UEQ:
1034    default:
1035      // AL is our "false" for now. The other two need more compares.
1036      return ARMCC::AL;
1037    case CmpInst::ICMP_EQ:
1038    case CmpInst::FCMP_OEQ:
1039      return ARMCC::EQ;
1040    case CmpInst::ICMP_SGT:
1041    case CmpInst::FCMP_OGT:
1042      return ARMCC::GT;
1043    case CmpInst::ICMP_SGE:
1044    case CmpInst::FCMP_OGE:
1045      return ARMCC::GE;
1046    case CmpInst::ICMP_UGT:
1047    case CmpInst::FCMP_UGT:
1048      return ARMCC::HI;
1049    case CmpInst::FCMP_OLT:
1050      return ARMCC::MI;
1051    case CmpInst::ICMP_ULE:
1052    case CmpInst::FCMP_OLE:
1053      return ARMCC::LS;
1054    case CmpInst::FCMP_ORD:
1055      return ARMCC::VC;
1056    case CmpInst::FCMP_UNO:
1057      return ARMCC::VS;
1058    case CmpInst::FCMP_UGE:
1059      return ARMCC::PL;
1060    case CmpInst::ICMP_SLT:
1061    case CmpInst::FCMP_ULT:
1062      return ARMCC::LT;
1063    case CmpInst::ICMP_SLE:
1064    case CmpInst::FCMP_ULE:
1065      return ARMCC::LE;
1066    case CmpInst::FCMP_UNE:
1067    case CmpInst::ICMP_NE:
1068      return ARMCC::NE;
1069    case CmpInst::ICMP_UGE:
1070      return ARMCC::HS;
1071    case CmpInst::ICMP_ULT:
1072      return ARMCC::LO;
1073  }
1074}
1075
1076bool ARMFastISel::SelectBranch(const Instruction *I) {
1077  const BranchInst *BI = cast<BranchInst>(I);
1078  MachineBasicBlock *TBB = FuncInfo.MBBMap[BI->getSuccessor(0)];
1079  MachineBasicBlock *FBB = FuncInfo.MBBMap[BI->getSuccessor(1)];
1080
1081  // Simple branch support.
1082
1083  // If we can, avoid recomputing the compare - redoing it could lead to wonky
1084  // behavior.
1085  // TODO: Factor this out.
1086  if (const CmpInst *CI = dyn_cast<CmpInst>(BI->getCondition())) {
1087    MVT SourceVT;
1088    Type *Ty = CI->getOperand(0)->getType();
1089    if (CI->hasOneUse() && (CI->getParent() == I->getParent())
1090        && isTypeLegal(Ty, SourceVT)) {
1091      bool isFloat = (Ty->isDoubleTy() || Ty->isFloatTy());
1092      if (isFloat && !Subtarget->hasVFP2())
1093        return false;
1094
1095      unsigned CmpOpc;
1096      switch (SourceVT.SimpleTy) {
1097        default: return false;
1098        // TODO: Verify compares.
1099        case MVT::f32:
1100          CmpOpc = ARM::VCMPES;
1101          break;
1102        case MVT::f64:
1103          CmpOpc = ARM::VCMPED;
1104          break;
1105        case MVT::i32:
1106          CmpOpc = isThumb ? ARM::t2CMPrr : ARM::CMPrr;
1107          break;
1108      }
1109
1110      // Get the compare predicate.
1111      // Try to take advantage of fallthrough opportunities.
1112      CmpInst::Predicate Predicate = CI->getPredicate();
1113      if (FuncInfo.MBB->isLayoutSuccessor(TBB)) {
1114        std::swap(TBB, FBB);
1115        Predicate = CmpInst::getInversePredicate(Predicate);
1116      }
1117
1118      ARMCC::CondCodes ARMPred = getComparePred(Predicate);
1119
1120      // We may not handle every CC for now.
1121      if (ARMPred == ARMCC::AL) return false;
1122
1123      unsigned Arg1 = getRegForValue(CI->getOperand(0));
1124      if (Arg1 == 0) return false;
1125
1126      unsigned Arg2 = getRegForValue(CI->getOperand(1));
1127      if (Arg2 == 0) return false;
1128
1129      AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
1130                              TII.get(CmpOpc))
1131                      .addReg(Arg1).addReg(Arg2));
1132
1133      // For floating point we need to move the result to a comparison register
1134      // that we can then use for branches.
1135      if (isFloat)
1136        AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
1137                                TII.get(ARM::FMSTAT)));
1138
1139      unsigned BrOpc = isThumb ? ARM::t2Bcc : ARM::Bcc;
1140      BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(BrOpc))
1141      .addMBB(TBB).addImm(ARMPred).addReg(ARM::CPSR);
1142      FastEmitBranch(FBB, DL);
1143      FuncInfo.MBB->addSuccessor(TBB);
1144      return true;
1145    }
1146  } else if (TruncInst *TI = dyn_cast<TruncInst>(BI->getCondition())) {
1147    MVT SourceVT;
1148    if (TI->hasOneUse() && TI->getParent() == I->getParent() &&
1149        (isLoadTypeLegal(TI->getOperand(0)->getType(), SourceVT))) {
1150      unsigned TstOpc = isThumb ? ARM::t2TSTri : ARM::TSTri;
1151      unsigned OpReg = getRegForValue(TI->getOperand(0));
1152      AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
1153                              TII.get(TstOpc))
1154                      .addReg(OpReg).addImm(1));
1155
1156      unsigned CCMode = ARMCC::NE;
1157      if (FuncInfo.MBB->isLayoutSuccessor(TBB)) {
1158        std::swap(TBB, FBB);
1159        CCMode = ARMCC::EQ;
1160      }
1161
1162      unsigned BrOpc = isThumb ? ARM::t2Bcc : ARM::Bcc;
1163      BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(BrOpc))
1164      .addMBB(TBB).addImm(CCMode).addReg(ARM::CPSR);
1165
1166      FastEmitBranch(FBB, DL);
1167      FuncInfo.MBB->addSuccessor(TBB);
1168      return true;
1169    }
1170  }
1171
1172  unsigned CmpReg = getRegForValue(BI->getCondition());
1173  if (CmpReg == 0) return false;
1174
1175  // We've been divorced from our compare!  Our block was split, and
1176  // now our compare lives in a predecessor block.  We musn't
1177  // re-compare here, as the children of the compare aren't guaranteed
1178  // live across the block boundary (we *could* check for this).
1179  // Regardless, the compare has been done in the predecessor block,
1180  // and it left a value for us in a virtual register.  Ergo, we test
1181  // the one-bit value left in the virtual register.
1182  unsigned TstOpc = isThumb ? ARM::t2TSTri : ARM::TSTri;
1183  AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(TstOpc))
1184                  .addReg(CmpReg).addImm(1));
1185
1186  unsigned CCMode = ARMCC::NE;
1187  if (FuncInfo.MBB->isLayoutSuccessor(TBB)) {
1188    std::swap(TBB, FBB);
1189    CCMode = ARMCC::EQ;
1190  }
1191
1192  unsigned BrOpc = isThumb ? ARM::t2Bcc : ARM::Bcc;
1193  BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(BrOpc))
1194                  .addMBB(TBB).addImm(CCMode).addReg(ARM::CPSR);
1195  FastEmitBranch(FBB, DL);
1196  FuncInfo.MBB->addSuccessor(TBB);
1197  return true;
1198}
1199
1200bool ARMFastISel::SelectCmp(const Instruction *I) {
1201  const CmpInst *CI = cast<CmpInst>(I);
1202
1203  MVT VT;
1204  Type *Ty = CI->getOperand(0)->getType();
1205  if (!isTypeLegal(Ty, VT))
1206    return false;
1207
1208  bool isFloat = (Ty->isDoubleTy() || Ty->isFloatTy());
1209  if (isFloat && !Subtarget->hasVFP2())
1210    return false;
1211
1212  unsigned CmpOpc;
1213  unsigned CondReg;
1214  switch (VT.SimpleTy) {
1215    default: return false;
1216    // TODO: Verify compares.
1217    case MVT::f32:
1218      CmpOpc = ARM::VCMPES;
1219      CondReg = ARM::FPSCR;
1220      break;
1221    case MVT::f64:
1222      CmpOpc = ARM::VCMPED;
1223      CondReg = ARM::FPSCR;
1224      break;
1225    case MVT::i32:
1226      CmpOpc = isThumb ? ARM::t2CMPrr : ARM::CMPrr;
1227      CondReg = ARM::CPSR;
1228      break;
1229  }
1230
1231  // Get the compare predicate.
1232  ARMCC::CondCodes ARMPred = getComparePred(CI->getPredicate());
1233
1234  // We may not handle every CC for now.
1235  if (ARMPred == ARMCC::AL) return false;
1236
1237  unsigned Arg1 = getRegForValue(CI->getOperand(0));
1238  if (Arg1 == 0) return false;
1239
1240  unsigned Arg2 = getRegForValue(CI->getOperand(1));
1241  if (Arg2 == 0) return false;
1242
1243  AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(CmpOpc))
1244                  .addReg(Arg1).addReg(Arg2));
1245
1246  // For floating point we need to move the result to a comparison register
1247  // that we can then use for branches.
1248  if (isFloat)
1249    AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
1250                            TII.get(ARM::FMSTAT)));
1251
1252  // Now set a register based on the comparison. Explicitly set the predicates
1253  // here.
1254  unsigned MovCCOpc = isThumb ? ARM::t2MOVCCi : ARM::MOVCCi;
1255  TargetRegisterClass *RC = isThumb ? ARM::rGPRRegisterClass
1256                                    : ARM::GPRRegisterClass;
1257  unsigned DestReg = createResultReg(RC);
1258  Constant *Zero
1259    = ConstantInt::get(Type::getInt32Ty(*Context), 0);
1260  unsigned ZeroReg = TargetMaterializeConstant(Zero);
1261  BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(MovCCOpc), DestReg)
1262          .addReg(ZeroReg).addImm(1)
1263          .addImm(ARMPred).addReg(CondReg);
1264
1265  UpdateValueMap(I, DestReg);
1266  return true;
1267}
1268
1269bool ARMFastISel::SelectFPExt(const Instruction *I) {
1270  // Make sure we have VFP and that we're extending float to double.
1271  if (!Subtarget->hasVFP2()) return false;
1272
1273  Value *V = I->getOperand(0);
1274  if (!I->getType()->isDoubleTy() ||
1275      !V->getType()->isFloatTy()) return false;
1276
1277  unsigned Op = getRegForValue(V);
1278  if (Op == 0) return false;
1279
1280  unsigned Result = createResultReg(ARM::DPRRegisterClass);
1281  AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
1282                          TII.get(ARM::VCVTDS), Result)
1283                  .addReg(Op));
1284  UpdateValueMap(I, Result);
1285  return true;
1286}
1287
1288bool ARMFastISel::SelectFPTrunc(const Instruction *I) {
1289  // Make sure we have VFP and that we're truncating double to float.
1290  if (!Subtarget->hasVFP2()) return false;
1291
1292  Value *V = I->getOperand(0);
1293  if (!(I->getType()->isFloatTy() &&
1294        V->getType()->isDoubleTy())) return false;
1295
1296  unsigned Op = getRegForValue(V);
1297  if (Op == 0) return false;
1298
1299  unsigned Result = createResultReg(ARM::SPRRegisterClass);
1300  AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
1301                          TII.get(ARM::VCVTSD), Result)
1302                  .addReg(Op));
1303  UpdateValueMap(I, Result);
1304  return true;
1305}
1306
1307bool ARMFastISel::SelectSIToFP(const Instruction *I) {
1308  // Make sure we have VFP.
1309  if (!Subtarget->hasVFP2()) return false;
1310
1311  MVT DstVT;
1312  Type *Ty = I->getType();
1313  if (!isTypeLegal(Ty, DstVT))
1314    return false;
1315
1316  // FIXME: Handle sign-extension where necessary.
1317  if (!I->getOperand(0)->getType()->isIntegerTy(32))
1318    return false;
1319
1320  unsigned Op = getRegForValue(I->getOperand(0));
1321  if (Op == 0) return false;
1322
1323  // The conversion routine works on fp-reg to fp-reg and the operand above
1324  // was an integer, move it to the fp registers if possible.
1325  unsigned FP = ARMMoveToFPReg(MVT::f32, Op);
1326  if (FP == 0) return false;
1327
1328  unsigned Opc;
1329  if (Ty->isFloatTy()) Opc = ARM::VSITOS;
1330  else if (Ty->isDoubleTy()) Opc = ARM::VSITOD;
1331  else return 0;
1332
1333  unsigned ResultReg = createResultReg(TLI.getRegClassFor(DstVT));
1334  AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(Opc),
1335                          ResultReg)
1336                  .addReg(FP));
1337  UpdateValueMap(I, ResultReg);
1338  return true;
1339}
1340
1341bool ARMFastISel::SelectFPToSI(const Instruction *I) {
1342  // Make sure we have VFP.
1343  if (!Subtarget->hasVFP2()) return false;
1344
1345  MVT DstVT;
1346  Type *RetTy = I->getType();
1347  if (!isTypeLegal(RetTy, DstVT))
1348    return false;
1349
1350  unsigned Op = getRegForValue(I->getOperand(0));
1351  if (Op == 0) return false;
1352
1353  unsigned Opc;
1354  Type *OpTy = I->getOperand(0)->getType();
1355  if (OpTy->isFloatTy()) Opc = ARM::VTOSIZS;
1356  else if (OpTy->isDoubleTy()) Opc = ARM::VTOSIZD;
1357  else return 0;
1358
1359  // f64->s32 or f32->s32 both need an intermediate f32 reg.
1360  unsigned ResultReg = createResultReg(TLI.getRegClassFor(MVT::f32));
1361  AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(Opc),
1362                          ResultReg)
1363                  .addReg(Op));
1364
1365  // This result needs to be in an integer register, but the conversion only
1366  // takes place in fp-regs.
1367  unsigned IntReg = ARMMoveToIntReg(DstVT, ResultReg);
1368  if (IntReg == 0) return false;
1369
1370  UpdateValueMap(I, IntReg);
1371  return true;
1372}
1373
1374bool ARMFastISel::SelectSelect(const Instruction *I) {
1375  MVT VT;
1376  if (!isTypeLegal(I->getType(), VT))
1377    return false;
1378
1379  // Things need to be register sized for register moves.
1380  if (VT != MVT::i32) return false;
1381  const TargetRegisterClass *RC = TLI.getRegClassFor(VT);
1382
1383  unsigned CondReg = getRegForValue(I->getOperand(0));
1384  if (CondReg == 0) return false;
1385  unsigned Op1Reg = getRegForValue(I->getOperand(1));
1386  if (Op1Reg == 0) return false;
1387  unsigned Op2Reg = getRegForValue(I->getOperand(2));
1388  if (Op2Reg == 0) return false;
1389
1390  unsigned CmpOpc = isThumb ? ARM::t2TSTri : ARM::TSTri;
1391  AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(CmpOpc))
1392                  .addReg(CondReg).addImm(1));
1393  unsigned ResultReg = createResultReg(RC);
1394  unsigned MovCCOpc = isThumb ? ARM::t2MOVCCr : ARM::MOVCCr;
1395  BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(MovCCOpc), ResultReg)
1396    .addReg(Op1Reg).addReg(Op2Reg)
1397    .addImm(ARMCC::EQ).addReg(ARM::CPSR);
1398  UpdateValueMap(I, ResultReg);
1399  return true;
1400}
1401
1402bool ARMFastISel::SelectSDiv(const Instruction *I) {
1403  MVT VT;
1404  Type *Ty = I->getType();
1405  if (!isTypeLegal(Ty, VT))
1406    return false;
1407
1408  // If we have integer div support we should have selected this automagically.
1409  // In case we have a real miss go ahead and return false and we'll pick
1410  // it up later.
1411  if (Subtarget->hasDivide()) return false;
1412
1413  // Otherwise emit a libcall.
1414  RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
1415  if (VT == MVT::i8)
1416    LC = RTLIB::SDIV_I8;
1417  else if (VT == MVT::i16)
1418    LC = RTLIB::SDIV_I16;
1419  else if (VT == MVT::i32)
1420    LC = RTLIB::SDIV_I32;
1421  else if (VT == MVT::i64)
1422    LC = RTLIB::SDIV_I64;
1423  else if (VT == MVT::i128)
1424    LC = RTLIB::SDIV_I128;
1425  assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unsupported SDIV!");
1426
1427  return ARMEmitLibcall(I, LC);
1428}
1429
1430bool ARMFastISel::SelectSRem(const Instruction *I) {
1431  MVT VT;
1432  Type *Ty = I->getType();
1433  if (!isTypeLegal(Ty, VT))
1434    return false;
1435
1436  RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
1437  if (VT == MVT::i8)
1438    LC = RTLIB::SREM_I8;
1439  else if (VT == MVT::i16)
1440    LC = RTLIB::SREM_I16;
1441  else if (VT == MVT::i32)
1442    LC = RTLIB::SREM_I32;
1443  else if (VT == MVT::i64)
1444    LC = RTLIB::SREM_I64;
1445  else if (VT == MVT::i128)
1446    LC = RTLIB::SREM_I128;
1447  assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unsupported SREM!");
1448
1449  return ARMEmitLibcall(I, LC);
1450}
1451
1452bool ARMFastISel::SelectBinaryOp(const Instruction *I, unsigned ISDOpcode) {
1453  EVT VT  = TLI.getValueType(I->getType(), true);
1454
1455  // We can get here in the case when we want to use NEON for our fp
1456  // operations, but can't figure out how to. Just use the vfp instructions
1457  // if we have them.
1458  // FIXME: It'd be nice to use NEON instructions.
1459  Type *Ty = I->getType();
1460  bool isFloat = (Ty->isDoubleTy() || Ty->isFloatTy());
1461  if (isFloat && !Subtarget->hasVFP2())
1462    return false;
1463
1464  unsigned Op1 = getRegForValue(I->getOperand(0));
1465  if (Op1 == 0) return false;
1466
1467  unsigned Op2 = getRegForValue(I->getOperand(1));
1468  if (Op2 == 0) return false;
1469
1470  unsigned Opc;
1471  bool is64bit = VT == MVT::f64 || VT == MVT::i64;
1472  switch (ISDOpcode) {
1473    default: return false;
1474    case ISD::FADD:
1475      Opc = is64bit ? ARM::VADDD : ARM::VADDS;
1476      break;
1477    case ISD::FSUB:
1478      Opc = is64bit ? ARM::VSUBD : ARM::VSUBS;
1479      break;
1480    case ISD::FMUL:
1481      Opc = is64bit ? ARM::VMULD : ARM::VMULS;
1482      break;
1483  }
1484  unsigned ResultReg = createResultReg(TLI.getRegClassFor(VT));
1485  AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
1486                          TII.get(Opc), ResultReg)
1487                  .addReg(Op1).addReg(Op2));
1488  UpdateValueMap(I, ResultReg);
1489  return true;
1490}
1491
1492// Call Handling Code
1493
1494bool ARMFastISel::FastEmitExtend(ISD::NodeType Opc, EVT DstVT, unsigned Src,
1495                                 EVT SrcVT, unsigned &ResultReg) {
1496  unsigned RR = FastEmit_r(SrcVT.getSimpleVT(), DstVT.getSimpleVT(), Opc,
1497                           Src, /*TODO: Kill=*/false);
1498
1499  if (RR != 0) {
1500    ResultReg = RR;
1501    return true;
1502  } else
1503    return false;
1504}
1505
1506// This is largely taken directly from CCAssignFnForNode - we don't support
1507// varargs in FastISel so that part has been removed.
1508// TODO: We may not support all of this.
1509CCAssignFn *ARMFastISel::CCAssignFnForCall(CallingConv::ID CC, bool Return) {
1510  switch (CC) {
1511  default:
1512    llvm_unreachable("Unsupported calling convention");
1513  case CallingConv::Fast:
1514    // Ignore fastcc. Silence compiler warnings.
1515    (void)RetFastCC_ARM_APCS;
1516    (void)FastCC_ARM_APCS;
1517    // Fallthrough
1518  case CallingConv::C:
1519    // Use target triple & subtarget features to do actual dispatch.
1520    if (Subtarget->isAAPCS_ABI()) {
1521      if (Subtarget->hasVFP2() &&
1522          FloatABIType == FloatABI::Hard)
1523        return (Return ? RetCC_ARM_AAPCS_VFP: CC_ARM_AAPCS_VFP);
1524      else
1525        return (Return ? RetCC_ARM_AAPCS: CC_ARM_AAPCS);
1526    } else
1527        return (Return ? RetCC_ARM_APCS: CC_ARM_APCS);
1528  case CallingConv::ARM_AAPCS_VFP:
1529    return (Return ? RetCC_ARM_AAPCS_VFP: CC_ARM_AAPCS_VFP);
1530  case CallingConv::ARM_AAPCS:
1531    return (Return ? RetCC_ARM_AAPCS: CC_ARM_AAPCS);
1532  case CallingConv::ARM_APCS:
1533    return (Return ? RetCC_ARM_APCS: CC_ARM_APCS);
1534  }
1535}
1536
1537bool ARMFastISel::ProcessCallArgs(SmallVectorImpl<Value*> &Args,
1538                                  SmallVectorImpl<unsigned> &ArgRegs,
1539                                  SmallVectorImpl<MVT> &ArgVTs,
1540                                  SmallVectorImpl<ISD::ArgFlagsTy> &ArgFlags,
1541                                  SmallVectorImpl<unsigned> &RegArgs,
1542                                  CallingConv::ID CC,
1543                                  unsigned &NumBytes) {
1544  SmallVector<CCValAssign, 16> ArgLocs;
1545  CCState CCInfo(CC, false, *FuncInfo.MF, TM, ArgLocs, *Context);
1546  CCInfo.AnalyzeCallOperands(ArgVTs, ArgFlags, CCAssignFnForCall(CC, false));
1547
1548  // Get a count of how many bytes are to be pushed on the stack.
1549  NumBytes = CCInfo.getNextStackOffset();
1550
1551  // Issue CALLSEQ_START
1552  unsigned AdjStackDown = TII.getCallFrameSetupOpcode();
1553  AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
1554                          TII.get(AdjStackDown))
1555                  .addImm(NumBytes));
1556
1557  // Process the args.
1558  for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
1559    CCValAssign &VA = ArgLocs[i];
1560    unsigned Arg = ArgRegs[VA.getValNo()];
1561    MVT ArgVT = ArgVTs[VA.getValNo()];
1562
1563    // We don't handle NEON/vector parameters yet.
1564    if (ArgVT.isVector() || ArgVT.getSizeInBits() > 64)
1565      return false;
1566
1567    // Handle arg promotion, etc.
1568    switch (VA.getLocInfo()) {
1569      case CCValAssign::Full: break;
1570      case CCValAssign::SExt: {
1571        bool Emitted = FastEmitExtend(ISD::SIGN_EXTEND, VA.getLocVT(),
1572                                         Arg, ArgVT, Arg);
1573        assert(Emitted && "Failed to emit a sext!"); (void)Emitted;
1574        Emitted = true;
1575        ArgVT = VA.getLocVT();
1576        break;
1577      }
1578      case CCValAssign::ZExt: {
1579        bool Emitted = FastEmitExtend(ISD::ZERO_EXTEND, VA.getLocVT(),
1580                                         Arg, ArgVT, Arg);
1581        assert(Emitted && "Failed to emit a zext!"); (void)Emitted;
1582        Emitted = true;
1583        ArgVT = VA.getLocVT();
1584        break;
1585      }
1586      case CCValAssign::AExt: {
1587        bool Emitted = FastEmitExtend(ISD::ANY_EXTEND, VA.getLocVT(),
1588                                         Arg, ArgVT, Arg);
1589        if (!Emitted)
1590          Emitted = FastEmitExtend(ISD::ZERO_EXTEND, VA.getLocVT(),
1591                                      Arg, ArgVT, Arg);
1592        if (!Emitted)
1593          Emitted = FastEmitExtend(ISD::SIGN_EXTEND, VA.getLocVT(),
1594                                      Arg, ArgVT, Arg);
1595
1596        assert(Emitted && "Failed to emit a aext!"); (void)Emitted;
1597        ArgVT = VA.getLocVT();
1598        break;
1599      }
1600      case CCValAssign::BCvt: {
1601        unsigned BC = FastEmit_r(ArgVT, VA.getLocVT(), ISD::BITCAST, Arg,
1602                                 /*TODO: Kill=*/false);
1603        assert(BC != 0 && "Failed to emit a bitcast!");
1604        Arg = BC;
1605        ArgVT = VA.getLocVT();
1606        break;
1607      }
1608      default: llvm_unreachable("Unknown arg promotion!");
1609    }
1610
1611    // Now copy/store arg to correct locations.
1612    if (VA.isRegLoc() && !VA.needsCustom()) {
1613      BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(TargetOpcode::COPY),
1614              VA.getLocReg())
1615      .addReg(Arg);
1616      RegArgs.push_back(VA.getLocReg());
1617    } else if (VA.needsCustom()) {
1618      // TODO: We need custom lowering for vector (v2f64) args.
1619      if (VA.getLocVT() != MVT::f64) return false;
1620
1621      CCValAssign &NextVA = ArgLocs[++i];
1622
1623      // TODO: Only handle register args for now.
1624      if(!(VA.isRegLoc() && NextVA.isRegLoc())) return false;
1625
1626      AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
1627                              TII.get(ARM::VMOVRRD), VA.getLocReg())
1628                      .addReg(NextVA.getLocReg(), RegState::Define)
1629                      .addReg(Arg));
1630      RegArgs.push_back(VA.getLocReg());
1631      RegArgs.push_back(NextVA.getLocReg());
1632    } else {
1633      assert(VA.isMemLoc());
1634      // Need to store on the stack.
1635      Address Addr;
1636      Addr.BaseType = Address::RegBase;
1637      Addr.Base.Reg = ARM::SP;
1638      Addr.Offset = VA.getLocMemOffset();
1639
1640      if (!ARMEmitStore(ArgVT, Arg, Addr)) return false;
1641    }
1642  }
1643  return true;
1644}
1645
1646bool ARMFastISel::FinishCall(MVT RetVT, SmallVectorImpl<unsigned> &UsedRegs,
1647                             const Instruction *I, CallingConv::ID CC,
1648                             unsigned &NumBytes) {
1649  // Issue CALLSEQ_END
1650  unsigned AdjStackUp = TII.getCallFrameDestroyOpcode();
1651  AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
1652                          TII.get(AdjStackUp))
1653                  .addImm(NumBytes).addImm(0));
1654
1655  // Now the return value.
1656  if (RetVT != MVT::isVoid) {
1657    SmallVector<CCValAssign, 16> RVLocs;
1658    CCState CCInfo(CC, false, *FuncInfo.MF, TM, RVLocs, *Context);
1659    CCInfo.AnalyzeCallResult(RetVT, CCAssignFnForCall(CC, true));
1660
1661    // Copy all of the result registers out of their specified physreg.
1662    if (RVLocs.size() == 2 && RetVT == MVT::f64) {
1663      // For this move we copy into two registers and then move into the
1664      // double fp reg we want.
1665      EVT DestVT = RVLocs[0].getValVT();
1666      TargetRegisterClass* DstRC = TLI.getRegClassFor(DestVT);
1667      unsigned ResultReg = createResultReg(DstRC);
1668      AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
1669                              TII.get(ARM::VMOVDRR), ResultReg)
1670                      .addReg(RVLocs[0].getLocReg())
1671                      .addReg(RVLocs[1].getLocReg()));
1672
1673      UsedRegs.push_back(RVLocs[0].getLocReg());
1674      UsedRegs.push_back(RVLocs[1].getLocReg());
1675
1676      // Finally update the result.
1677      UpdateValueMap(I, ResultReg);
1678    } else {
1679      assert(RVLocs.size() == 1 &&"Can't handle non-double multi-reg retvals!");
1680      EVT CopyVT = RVLocs[0].getValVT();
1681      TargetRegisterClass* DstRC = TLI.getRegClassFor(CopyVT);
1682
1683      unsigned ResultReg = createResultReg(DstRC);
1684      BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(TargetOpcode::COPY),
1685              ResultReg).addReg(RVLocs[0].getLocReg());
1686      UsedRegs.push_back(RVLocs[0].getLocReg());
1687
1688      // Finally update the result.
1689      UpdateValueMap(I, ResultReg);
1690    }
1691  }
1692
1693  return true;
1694}
1695
1696bool ARMFastISel::SelectRet(const Instruction *I) {
1697  const ReturnInst *Ret = cast<ReturnInst>(I);
1698  const Function &F = *I->getParent()->getParent();
1699
1700  if (!FuncInfo.CanLowerReturn)
1701    return false;
1702
1703  if (F.isVarArg())
1704    return false;
1705
1706  CallingConv::ID CC = F.getCallingConv();
1707  if (Ret->getNumOperands() > 0) {
1708    SmallVector<ISD::OutputArg, 4> Outs;
1709    GetReturnInfo(F.getReturnType(), F.getAttributes().getRetAttributes(),
1710                  Outs, TLI);
1711
1712    // Analyze operands of the call, assigning locations to each operand.
1713    SmallVector<CCValAssign, 16> ValLocs;
1714    CCState CCInfo(CC, F.isVarArg(), *FuncInfo.MF, TM, ValLocs, I->getContext());
1715    CCInfo.AnalyzeReturn(Outs, CCAssignFnForCall(CC, true /* is Ret */));
1716
1717    const Value *RV = Ret->getOperand(0);
1718    unsigned Reg = getRegForValue(RV);
1719    if (Reg == 0)
1720      return false;
1721
1722    // Only handle a single return value for now.
1723    if (ValLocs.size() != 1)
1724      return false;
1725
1726    CCValAssign &VA = ValLocs[0];
1727
1728    // Don't bother handling odd stuff for now.
1729    if (VA.getLocInfo() != CCValAssign::Full)
1730      return false;
1731    // Only handle register returns for now.
1732    if (!VA.isRegLoc())
1733      return false;
1734    // TODO: For now, don't try to handle cases where getLocInfo()
1735    // says Full but the types don't match.
1736    if (TLI.getValueType(RV->getType()) != VA.getValVT())
1737      return false;
1738
1739    // Make the copy.
1740    unsigned SrcReg = Reg + VA.getValNo();
1741    unsigned DstReg = VA.getLocReg();
1742    const TargetRegisterClass* SrcRC = MRI.getRegClass(SrcReg);
1743    // Avoid a cross-class copy. This is very unlikely.
1744    if (!SrcRC->contains(DstReg))
1745      return false;
1746    BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(TargetOpcode::COPY),
1747            DstReg).addReg(SrcReg);
1748
1749    // Mark the register as live out of the function.
1750    MRI.addLiveOut(VA.getLocReg());
1751  }
1752
1753  unsigned RetOpc = isThumb ? ARM::tBX_RET : ARM::BX_RET;
1754  AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
1755                          TII.get(RetOpc)));
1756  return true;
1757}
1758
1759unsigned ARMFastISel::ARMSelectCallOp(const GlobalValue *GV) {
1760
1761  // Darwin needs the r9 versions of the opcodes.
1762  bool isDarwin = Subtarget->isTargetDarwin();
1763  if (isThumb) {
1764    return isDarwin ? ARM::tBLr9 : ARM::tBL;
1765  } else  {
1766    return isDarwin ? ARM::BLr9 : ARM::BL;
1767  }
1768}
1769
1770// A quick function that will emit a call for a named libcall in F with the
1771// vector of passed arguments for the Instruction in I. We can assume that we
1772// can emit a call for any libcall we can produce. This is an abridged version
1773// of the full call infrastructure since we won't need to worry about things
1774// like computed function pointers or strange arguments at call sites.
1775// TODO: Try to unify this and the normal call bits for ARM, then try to unify
1776// with X86.
1777bool ARMFastISel::ARMEmitLibcall(const Instruction *I, RTLIB::Libcall Call) {
1778  CallingConv::ID CC = TLI.getLibcallCallingConv(Call);
1779
1780  // Handle *simple* calls for now.
1781  Type *RetTy = I->getType();
1782  MVT RetVT;
1783  if (RetTy->isVoidTy())
1784    RetVT = MVT::isVoid;
1785  else if (!isTypeLegal(RetTy, RetVT))
1786    return false;
1787
1788  // TODO: For now if we have long calls specified we don't handle the call.
1789  if (EnableARMLongCalls) return false;
1790
1791  // Set up the argument vectors.
1792  SmallVector<Value*, 8> Args;
1793  SmallVector<unsigned, 8> ArgRegs;
1794  SmallVector<MVT, 8> ArgVTs;
1795  SmallVector<ISD::ArgFlagsTy, 8> ArgFlags;
1796  Args.reserve(I->getNumOperands());
1797  ArgRegs.reserve(I->getNumOperands());
1798  ArgVTs.reserve(I->getNumOperands());
1799  ArgFlags.reserve(I->getNumOperands());
1800  for (unsigned i = 0; i < I->getNumOperands(); ++i) {
1801    Value *Op = I->getOperand(i);
1802    unsigned Arg = getRegForValue(Op);
1803    if (Arg == 0) return false;
1804
1805    Type *ArgTy = Op->getType();
1806    MVT ArgVT;
1807    if (!isTypeLegal(ArgTy, ArgVT)) return false;
1808
1809    ISD::ArgFlagsTy Flags;
1810    unsigned OriginalAlignment = TD.getABITypeAlignment(ArgTy);
1811    Flags.setOrigAlign(OriginalAlignment);
1812
1813    Args.push_back(Op);
1814    ArgRegs.push_back(Arg);
1815    ArgVTs.push_back(ArgVT);
1816    ArgFlags.push_back(Flags);
1817  }
1818
1819  // Handle the arguments now that we've gotten them.
1820  SmallVector<unsigned, 4> RegArgs;
1821  unsigned NumBytes;
1822  if (!ProcessCallArgs(Args, ArgRegs, ArgVTs, ArgFlags, RegArgs, CC, NumBytes))
1823    return false;
1824
1825  // Issue the call, BLr9 for darwin, BL otherwise.
1826  // TODO: Turn this into the table of arm call ops.
1827  MachineInstrBuilder MIB;
1828  unsigned CallOpc = ARMSelectCallOp(NULL);
1829  if(isThumb)
1830    // Explicitly adding the predicate here.
1831    MIB = AddDefaultPred(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
1832                         TII.get(CallOpc)))
1833                         .addExternalSymbol(TLI.getLibcallName(Call));
1834  else
1835    // Explicitly adding the predicate here.
1836    MIB = AddDefaultPred(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
1837                         TII.get(CallOpc))
1838          .addExternalSymbol(TLI.getLibcallName(Call)));
1839
1840  // Add implicit physical register uses to the call.
1841  for (unsigned i = 0, e = RegArgs.size(); i != e; ++i)
1842    MIB.addReg(RegArgs[i]);
1843
1844  // Finish off the call including any return values.
1845  SmallVector<unsigned, 4> UsedRegs;
1846  if (!FinishCall(RetVT, UsedRegs, I, CC, NumBytes)) return false;
1847
1848  // Set all unused physreg defs as dead.
1849  static_cast<MachineInstr *>(MIB)->setPhysRegsDeadExcept(UsedRegs, TRI);
1850
1851  return true;
1852}
1853
1854bool ARMFastISel::SelectCall(const Instruction *I) {
1855  const CallInst *CI = cast<CallInst>(I);
1856  const Value *Callee = CI->getCalledValue();
1857
1858  // Can't handle inline asm or worry about intrinsics yet.
1859  if (isa<InlineAsm>(Callee) || isa<IntrinsicInst>(CI)) return false;
1860
1861  // Only handle global variable Callees.
1862  const GlobalValue *GV = dyn_cast<GlobalValue>(Callee);
1863  if (!GV)
1864    return false;
1865
1866  // Check the calling convention.
1867  ImmutableCallSite CS(CI);
1868  CallingConv::ID CC = CS.getCallingConv();
1869
1870  // TODO: Avoid some calling conventions?
1871
1872  // Let SDISel handle vararg functions.
1873  PointerType *PT = cast<PointerType>(CS.getCalledValue()->getType());
1874  FunctionType *FTy = cast<FunctionType>(PT->getElementType());
1875  if (FTy->isVarArg())
1876    return false;
1877
1878  // Handle *simple* calls for now.
1879  Type *RetTy = I->getType();
1880  MVT RetVT;
1881  if (RetTy->isVoidTy())
1882    RetVT = MVT::isVoid;
1883  else if (!isTypeLegal(RetTy, RetVT))
1884    return false;
1885
1886  // TODO: For now if we have long calls specified we don't handle the call.
1887  if (EnableARMLongCalls) return false;
1888
1889  // Set up the argument vectors.
1890  SmallVector<Value*, 8> Args;
1891  SmallVector<unsigned, 8> ArgRegs;
1892  SmallVector<MVT, 8> ArgVTs;
1893  SmallVector<ISD::ArgFlagsTy, 8> ArgFlags;
1894  Args.reserve(CS.arg_size());
1895  ArgRegs.reserve(CS.arg_size());
1896  ArgVTs.reserve(CS.arg_size());
1897  ArgFlags.reserve(CS.arg_size());
1898  for (ImmutableCallSite::arg_iterator i = CS.arg_begin(), e = CS.arg_end();
1899       i != e; ++i) {
1900    unsigned Arg = getRegForValue(*i);
1901
1902    if (Arg == 0)
1903      return false;
1904    ISD::ArgFlagsTy Flags;
1905    unsigned AttrInd = i - CS.arg_begin() + 1;
1906    if (CS.paramHasAttr(AttrInd, Attribute::SExt))
1907      Flags.setSExt();
1908    if (CS.paramHasAttr(AttrInd, Attribute::ZExt))
1909      Flags.setZExt();
1910
1911         // FIXME: Only handle *easy* calls for now.
1912    if (CS.paramHasAttr(AttrInd, Attribute::InReg) ||
1913        CS.paramHasAttr(AttrInd, Attribute::StructRet) ||
1914        CS.paramHasAttr(AttrInd, Attribute::Nest) ||
1915        CS.paramHasAttr(AttrInd, Attribute::ByVal))
1916      return false;
1917
1918    Type *ArgTy = (*i)->getType();
1919    MVT ArgVT;
1920    if (!isTypeLegal(ArgTy, ArgVT))
1921      return false;
1922    unsigned OriginalAlignment = TD.getABITypeAlignment(ArgTy);
1923    Flags.setOrigAlign(OriginalAlignment);
1924
1925    Args.push_back(*i);
1926    ArgRegs.push_back(Arg);
1927    ArgVTs.push_back(ArgVT);
1928    ArgFlags.push_back(Flags);
1929  }
1930
1931  // Handle the arguments now that we've gotten them.
1932  SmallVector<unsigned, 4> RegArgs;
1933  unsigned NumBytes;
1934  if (!ProcessCallArgs(Args, ArgRegs, ArgVTs, ArgFlags, RegArgs, CC, NumBytes))
1935    return false;
1936
1937  // Issue the call, BLr9 for darwin, BL otherwise.
1938  // TODO: Turn this into the table of arm call ops.
1939  MachineInstrBuilder MIB;
1940  unsigned CallOpc = ARMSelectCallOp(GV);
1941  // Explicitly adding the predicate here.
1942  if(isThumb)
1943    // Explicitly adding the predicate here.
1944    MIB = AddDefaultPred(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
1945                         TII.get(CallOpc)))
1946          .addGlobalAddress(GV, 0, 0);
1947  else
1948    // Explicitly adding the predicate here.
1949    MIB = AddDefaultPred(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
1950                         TII.get(CallOpc))
1951          .addGlobalAddress(GV, 0, 0));
1952
1953  // Add implicit physical register uses to the call.
1954  for (unsigned i = 0, e = RegArgs.size(); i != e; ++i)
1955    MIB.addReg(RegArgs[i]);
1956
1957  // Finish off the call including any return values.
1958  SmallVector<unsigned, 4> UsedRegs;
1959  if (!FinishCall(RetVT, UsedRegs, I, CC, NumBytes)) return false;
1960
1961  // Set all unused physreg defs as dead.
1962  static_cast<MachineInstr *>(MIB)->setPhysRegsDeadExcept(UsedRegs, TRI);
1963
1964  return true;
1965
1966}
1967
1968bool ARMFastISel::SelectIntCast(const Instruction *I) {
1969  // On ARM, in general, integer casts don't involve legal types; this code
1970  // handles promotable integers.  The high bits for a type smaller than
1971  // the register size are assumed to be undefined.
1972  Type *DestTy = I->getType();
1973  Value *Op = I->getOperand(0);
1974  Type *SrcTy = Op->getType();
1975
1976  EVT SrcVT, DestVT;
1977  SrcVT = TLI.getValueType(SrcTy, true);
1978  DestVT = TLI.getValueType(DestTy, true);
1979
1980  if (isa<TruncInst>(I)) {
1981    if (SrcVT != MVT::i32 && SrcVT != MVT::i16 && SrcVT != MVT::i8)
1982      return false;
1983    if (DestVT != MVT::i16 && DestVT != MVT::i8 && DestVT != MVT::i1)
1984      return false;
1985
1986    unsigned SrcReg = getRegForValue(Op);
1987    if (!SrcReg) return false;
1988
1989    // Because the high bits are undefined, a truncate doesn't generate
1990    // any code.
1991    UpdateValueMap(I, SrcReg);
1992    return true;
1993  }
1994  if (DestVT != MVT::i32 && DestVT != MVT::i16 && DestVT != MVT::i8)
1995    return false;
1996
1997  unsigned Opc;
1998  bool isZext = isa<ZExtInst>(I);
1999  bool isBoolZext = false;
2000  if (!SrcVT.isSimple())
2001    return false;
2002  switch (SrcVT.getSimpleVT().SimpleTy) {
2003  default: return false;
2004  case MVT::i16:
2005    if (!Subtarget->hasV6Ops()) return false;
2006    if (isZext)
2007      Opc = isThumb ? ARM::t2UXTH : ARM::UXTH;
2008    else
2009      Opc = isThumb ? ARM::t2SXTH : ARM::SXTH;
2010    break;
2011  case MVT::i8:
2012    if (!Subtarget->hasV6Ops()) return false;
2013    if (isZext)
2014      Opc = isThumb ? ARM::t2UXTB : ARM::UXTB;
2015    else
2016      Opc = isThumb ? ARM::t2SXTB : ARM::SXTB;
2017    break;
2018  case MVT::i1:
2019    if (isZext) {
2020      Opc = isThumb ? ARM::t2ANDri : ARM::ANDri;
2021      isBoolZext = true;
2022      break;
2023    }
2024    return false;
2025  }
2026
2027  // FIXME: We could save an instruction in many cases by special-casing
2028  // load instructions.
2029  unsigned SrcReg = getRegForValue(Op);
2030  if (!SrcReg) return false;
2031
2032  unsigned DestReg = createResultReg(TLI.getRegClassFor(MVT::i32));
2033  MachineInstrBuilder MIB;
2034  MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(Opc), DestReg)
2035        .addReg(SrcReg);
2036  if (isBoolZext)
2037    MIB.addImm(1);
2038  else
2039    MIB.addImm(0);
2040  AddOptionalDefs(MIB);
2041  UpdateValueMap(I, DestReg);
2042  return true;
2043}
2044
2045// TODO: SoftFP support.
2046bool ARMFastISel::TargetSelectInstruction(const Instruction *I) {
2047
2048  switch (I->getOpcode()) {
2049    case Instruction::Load:
2050      return SelectLoad(I);
2051    case Instruction::Store:
2052      return SelectStore(I);
2053    case Instruction::Br:
2054      return SelectBranch(I);
2055    case Instruction::ICmp:
2056    case Instruction::FCmp:
2057      return SelectCmp(I);
2058    case Instruction::FPExt:
2059      return SelectFPExt(I);
2060    case Instruction::FPTrunc:
2061      return SelectFPTrunc(I);
2062    case Instruction::SIToFP:
2063      return SelectSIToFP(I);
2064    case Instruction::FPToSI:
2065      return SelectFPToSI(I);
2066    case Instruction::FAdd:
2067      return SelectBinaryOp(I, ISD::FADD);
2068    case Instruction::FSub:
2069      return SelectBinaryOp(I, ISD::FSUB);
2070    case Instruction::FMul:
2071      return SelectBinaryOp(I, ISD::FMUL);
2072    case Instruction::SDiv:
2073      return SelectSDiv(I);
2074    case Instruction::SRem:
2075      return SelectSRem(I);
2076    case Instruction::Call:
2077      return SelectCall(I);
2078    case Instruction::Select:
2079      return SelectSelect(I);
2080    case Instruction::Ret:
2081      return SelectRet(I);
2082    case Instruction::Trunc:
2083    case Instruction::ZExt:
2084    case Instruction::SExt:
2085      return SelectIntCast(I);
2086    default: break;
2087  }
2088  return false;
2089}
2090
2091namespace llvm {
2092  llvm::FastISel *ARM::createFastISel(FunctionLoweringInfo &funcInfo) {
2093    // Completely untested on non-darwin.
2094    const TargetMachine &TM = funcInfo.MF->getTarget();
2095
2096    // Darwin and thumb1 only for now.
2097    const ARMSubtarget *Subtarget = &TM.getSubtarget<ARMSubtarget>();
2098    if (Subtarget->isTargetDarwin() && !Subtarget->isThumb1Only() &&
2099        !DisableARMFastISel)
2100      return new ARMFastISel(funcInfo);
2101    return 0;
2102  }
2103}
2104