ARMFastISel.cpp revision e07cd5e40ac06fabfb9d33ea7c79542f138f45ce 
1//===-- ARMFastISel.cpp - ARM FastISel implementation ---------------------===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file defines the ARM-specific support for the FastISel class. Some
11// of the target-specific code is generated by tablegen in the file
12// ARMGenFastISel.inc, which is #included here.
13//
14//===----------------------------------------------------------------------===//
15
16#include "ARM.h"
17#include "ARMBaseInstrInfo.h"
18#include "ARMCallingConv.h"
19#include "ARMRegisterInfo.h"
20#include "ARMTargetMachine.h"
21#include "ARMSubtarget.h"
22#include "ARMConstantPoolValue.h"
23#include "MCTargetDesc/ARMAddressingModes.h"
24#include "llvm/CallingConv.h"
25#include "llvm/DerivedTypes.h"
26#include "llvm/GlobalVariable.h"
27#include "llvm/Instructions.h"
28#include "llvm/IntrinsicInst.h"
29#include "llvm/Module.h"
30#include "llvm/Operator.h"
31#include "llvm/CodeGen/Analysis.h"
32#include "llvm/CodeGen/FastISel.h"
33#include "llvm/CodeGen/FunctionLoweringInfo.h"
34#include "llvm/CodeGen/MachineInstrBuilder.h"
35#include "llvm/CodeGen/MachineModuleInfo.h"
36#include "llvm/CodeGen/MachineConstantPool.h"
37#include "llvm/CodeGen/MachineFrameInfo.h"
38#include "llvm/CodeGen/MachineMemOperand.h"
39#include "llvm/CodeGen/MachineRegisterInfo.h"
40#include "llvm/CodeGen/PseudoSourceValue.h"
41#include "llvm/Support/CallSite.h"
42#include "llvm/Support/CommandLine.h"
43#include "llvm/Support/ErrorHandling.h"
44#include "llvm/Support/GetElementPtrTypeIterator.h"
45#include "llvm/Target/TargetData.h"
46#include "llvm/Target/TargetInstrInfo.h"
47#include "llvm/Target/TargetLowering.h"
48#include "llvm/Target/TargetMachine.h"
49#include "llvm/Target/TargetOptions.h"
50using namespace llvm;
51
52static cl::opt<bool>
53DisableARMFastISel("disable-arm-fast-isel",
54                    cl::desc("Turn off experimental ARM fast-isel support"),
55                    cl::init(false), cl::Hidden);
56
57extern cl::opt<bool> EnableARMLongCalls;
58
59namespace {
60
61  // All possible address modes, plus some.
62  typedef struct Address {
63    enum {
64      RegBase,
65      FrameIndexBase
66    } BaseType;
67
68    union {
69      unsigned Reg;
70      int FI;
71    } Base;
72
73    int Offset;
74
75    // Innocuous defaults for our address.
76    Address()
77     : BaseType(RegBase), Offset(0) {
78       Base.Reg = 0;
79     }
80  } Address;
81
82class ARMFastISel : public FastISel {
83
84  /// Subtarget - Keep a pointer to the ARMSubtarget around so that we can
85  /// make the right decision when generating code for different targets.
86  const ARMSubtarget *Subtarget;
87  const TargetMachine &TM;
88  const TargetInstrInfo &TII;
89  const TargetLowering &TLI;
90  ARMFunctionInfo *AFI;
91
92  // Convenience variables to avoid some queries.
93  bool isThumb;
94  LLVMContext *Context;
95
96  public:
97    explicit ARMFastISel(FunctionLoweringInfo &funcInfo)
98    : FastISel(funcInfo),
99      TM(funcInfo.MF->getTarget()),
100      TII(*TM.getInstrInfo()),
101      TLI(*TM.getTargetLowering()) {
102      Subtarget = &TM.getSubtarget<ARMSubtarget>();
103      AFI = funcInfo.MF->getInfo<ARMFunctionInfo>();
104      isThumb = AFI->isThumbFunction();
105      Context = &funcInfo.Fn->getContext();
106    }
107
108    // Code from FastISel.cpp.
109    virtual unsigned FastEmitInst_(unsigned MachineInstOpcode,
110                                   const TargetRegisterClass *RC);
111    virtual unsigned FastEmitInst_r(unsigned MachineInstOpcode,
112                                    const TargetRegisterClass *RC,
113                                    unsigned Op0, bool Op0IsKill);
114    virtual unsigned FastEmitInst_rr(unsigned MachineInstOpcode,
115                                     const TargetRegisterClass *RC,
116                                     unsigned Op0, bool Op0IsKill,
117                                     unsigned Op1, bool Op1IsKill);
118    virtual unsigned FastEmitInst_rrr(unsigned MachineInstOpcode,
119                                      const TargetRegisterClass *RC,
120                                      unsigned Op0, bool Op0IsKill,
121                                      unsigned Op1, bool Op1IsKill,
122                                      unsigned Op2, bool Op2IsKill);
123    virtual unsigned FastEmitInst_ri(unsigned MachineInstOpcode,
124                                     const TargetRegisterClass *RC,
125                                     unsigned Op0, bool Op0IsKill,
126                                     uint64_t Imm);
127    virtual unsigned FastEmitInst_rf(unsigned MachineInstOpcode,
128                                     const TargetRegisterClass *RC,
129                                     unsigned Op0, bool Op0IsKill,
130                                     const ConstantFP *FPImm);
131    virtual unsigned FastEmitInst_rri(unsigned MachineInstOpcode,
132                                      const TargetRegisterClass *RC,
133                                      unsigned Op0, bool Op0IsKill,
134                                      unsigned Op1, bool Op1IsKill,
135                                      uint64_t Imm);
136    virtual unsigned FastEmitInst_i(unsigned MachineInstOpcode,
137                                    const TargetRegisterClass *RC,
138                                    uint64_t Imm);
139    virtual unsigned FastEmitInst_ii(unsigned MachineInstOpcode,
140                                     const TargetRegisterClass *RC,
141                                     uint64_t Imm1, uint64_t Imm2);
142
143    virtual unsigned FastEmitInst_extractsubreg(MVT RetVT,
144                                                unsigned Op0, bool Op0IsKill,
145                                                uint32_t Idx);
146
147    // Backend specific FastISel code.
148    virtual bool TargetSelectInstruction(const Instruction *I);
149    virtual unsigned TargetMaterializeConstant(const Constant *C);
150    virtual unsigned TargetMaterializeAlloca(const AllocaInst *AI);
151
152  #include "ARMGenFastISel.inc"
153
154    // Instruction selection routines.
155  private:
156    bool SelectLoad(const Instruction *I);
157    bool SelectStore(const Instruction *I);
158    bool SelectBranch(const Instruction *I);
159    bool SelectCmp(const Instruction *I);
160    bool SelectFPExt(const Instruction *I);
161    bool SelectFPTrunc(const Instruction *I);
162    bool SelectBinaryOp(const Instruction *I, unsigned ISDOpcode);
163    bool SelectSIToFP(const Instruction *I);
164    bool SelectFPToSI(const Instruction *I);
165    bool SelectSDiv(const Instruction *I);
166    bool SelectSRem(const Instruction *I);
167    bool SelectCall(const Instruction *I);
168    bool SelectSelect(const Instruction *I);
169    bool SelectRet(const Instruction *I);
170    bool SelectTrunc(const Instruction *I);
171    bool SelectIntExt(const Instruction *I);
172
173    // Utility routines.
174  private:
175    bool isTypeLegal(Type *Ty, MVT &VT);
176    bool isLoadTypeLegal(Type *Ty, MVT &VT);
177    bool ARMEmitCmp(const Value *Src1Value, const Value *Src2Value,
178                    bool isZExt);
179    bool ARMEmitLoad(EVT VT, unsigned &ResultReg, Address &Addr);
180    bool ARMEmitStore(EVT VT, unsigned SrcReg, Address &Addr);
181    bool ARMComputeAddress(const Value *Obj, Address &Addr);
182    void ARMSimplifyAddress(Address &Addr, EVT VT);
183    unsigned ARMEmitIntExt(EVT SrcVT, unsigned SrcReg, EVT DestVT, bool isZExt);
184    unsigned ARMMaterializeFP(const ConstantFP *CFP, EVT VT);
185    unsigned ARMMaterializeInt(const Constant *C, EVT VT);
186    unsigned ARMMaterializeGV(const GlobalValue *GV, EVT VT);
187    unsigned ARMMoveToFPReg(EVT VT, unsigned SrcReg);
188    unsigned ARMMoveToIntReg(EVT VT, unsigned SrcReg);
189    unsigned ARMSelectCallOp(const GlobalValue *GV);
190
191    // Call handling routines.
192  private:
193    bool FastEmitExtend(ISD::NodeType Opc, EVT DstVT, unsigned Src, EVT SrcVT,
194                        unsigned &ResultReg);
195    CCAssignFn *CCAssignFnForCall(CallingConv::ID CC, bool Return);
196    bool ProcessCallArgs(SmallVectorImpl<Value*> &Args,
197                         SmallVectorImpl<unsigned> &ArgRegs,
198                         SmallVectorImpl<MVT> &ArgVTs,
199                         SmallVectorImpl<ISD::ArgFlagsTy> &ArgFlags,
200                         SmallVectorImpl<unsigned> &RegArgs,
201                         CallingConv::ID CC,
202                         unsigned &NumBytes);
203    bool FinishCall(MVT RetVT, SmallVectorImpl<unsigned> &UsedRegs,
204                    const Instruction *I, CallingConv::ID CC,
205                    unsigned &NumBytes);
206    bool ARMEmitLibcall(const Instruction *I, RTLIB::Libcall Call);
207
208    // OptionalDef handling routines.
209  private:
210    bool isARMNEONPred(const MachineInstr *MI);
211    bool DefinesOptionalPredicate(MachineInstr *MI, bool *CPSR);
212    const MachineInstrBuilder &AddOptionalDefs(const MachineInstrBuilder &MIB);
213    void AddLoadStoreOperands(EVT VT, Address &Addr,
214                              const MachineInstrBuilder &MIB,
215                              unsigned Flags);
216};
217
218} // end anonymous namespace
219
220#include "ARMGenCallingConv.inc"
221
222// DefinesOptionalPredicate - This is different from DefinesPredicate in that
223// we don't care about implicit defs here, just places we'll need to add a
224// default CCReg argument. Sets CPSR if we're setting CPSR instead of CCR.
225bool ARMFastISel::DefinesOptionalPredicate(MachineInstr *MI, bool *CPSR) {
226  const MCInstrDesc &MCID = MI->getDesc();
227  if (!MCID.hasOptionalDef())
228    return false;
229
230  // Look to see if our OptionalDef is defining CPSR or CCR.
231  for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
232    const MachineOperand &MO = MI->getOperand(i);
233    if (!MO.isReg() || !MO.isDef()) continue;
234    if (MO.getReg() == ARM::CPSR)
235      *CPSR = true;
236  }
237  return true;
238}
239
240bool ARMFastISel::isARMNEONPred(const MachineInstr *MI) {
241  const MCInstrDesc &MCID = MI->getDesc();
242
243  // If we're a thumb2 or not NEON function we were handled via isPredicable.
244  if ((MCID.TSFlags & ARMII::DomainMask) != ARMII::DomainNEON ||
245       AFI->isThumb2Function())
246    return false;
247
248  for (unsigned i = 0, e = MCID.getNumOperands(); i != e; ++i)
249    if (MCID.OpInfo[i].isPredicate())
250      return true;
251
252  return false;
253}
254
255// If the machine is predicable go ahead and add the predicate operands, if
256// it needs default CC operands add those.
257// TODO: If we want to support thumb1 then we'll need to deal with optional
258// CPSR defs that need to be added before the remaining operands. See s_cc_out
259// for descriptions why.
260const MachineInstrBuilder &
261ARMFastISel::AddOptionalDefs(const MachineInstrBuilder &MIB) {
262  MachineInstr *MI = &*MIB;
263
264  // Do we use a predicate? or...
265  // Are we NEON in ARM mode and have a predicate operand? If so, I know
266  // we're not predicable but add it anyways.
267  if (TII.isPredicable(MI) || isARMNEONPred(MI))
268    AddDefaultPred(MIB);
269
270  // Do we optionally set a predicate?  Preds is size > 0 iff the predicate
271  // defines CPSR. All other OptionalDefines in ARM are the CCR register.
272  bool CPSR = false;
273  if (DefinesOptionalPredicate(MI, &CPSR)) {
274    if (CPSR)
275      AddDefaultT1CC(MIB);
276    else
277      AddDefaultCC(MIB);
278  }
279  return MIB;
280}
281
282unsigned ARMFastISel::FastEmitInst_(unsigned MachineInstOpcode,
283                                    const TargetRegisterClass* RC) {
284  unsigned ResultReg = createResultReg(RC);
285  const MCInstrDesc &II = TII.get(MachineInstOpcode);
286
287  AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II, ResultReg));
288  return ResultReg;
289}
290
291unsigned ARMFastISel::FastEmitInst_r(unsigned MachineInstOpcode,
292                                     const TargetRegisterClass *RC,
293                                     unsigned Op0, bool Op0IsKill) {
294  unsigned ResultReg = createResultReg(RC);
295  const MCInstrDesc &II = TII.get(MachineInstOpcode);
296
297  if (II.getNumDefs() >= 1)
298    AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II, ResultReg)
299                   .addReg(Op0, Op0IsKill * RegState::Kill));
300  else {
301    AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II)
302                   .addReg(Op0, Op0IsKill * RegState::Kill));
303    AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
304                   TII.get(TargetOpcode::COPY), ResultReg)
305                   .addReg(II.ImplicitDefs[0]));
306  }
307  return ResultReg;
308}
309
310unsigned ARMFastISel::FastEmitInst_rr(unsigned MachineInstOpcode,
311                                      const TargetRegisterClass *RC,
312                                      unsigned Op0, bool Op0IsKill,
313                                      unsigned Op1, bool Op1IsKill) {
314  unsigned ResultReg = createResultReg(RC);
315  const MCInstrDesc &II = TII.get(MachineInstOpcode);
316
317  if (II.getNumDefs() >= 1)
318    AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II, ResultReg)
319                   .addReg(Op0, Op0IsKill * RegState::Kill)
320                   .addReg(Op1, Op1IsKill * RegState::Kill));
321  else {
322    AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II)
323                   .addReg(Op0, Op0IsKill * RegState::Kill)
324                   .addReg(Op1, Op1IsKill * RegState::Kill));
325    AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
326                           TII.get(TargetOpcode::COPY), ResultReg)
327                   .addReg(II.ImplicitDefs[0]));
328  }
329  return ResultReg;
330}
331
332unsigned ARMFastISel::FastEmitInst_rrr(unsigned MachineInstOpcode,
333                                       const TargetRegisterClass *RC,
334                                       unsigned Op0, bool Op0IsKill,
335                                       unsigned Op1, bool Op1IsKill,
336                                       unsigned Op2, bool Op2IsKill) {
337  unsigned ResultReg = createResultReg(RC);
338  const MCInstrDesc &II = TII.get(MachineInstOpcode);
339
340  if (II.getNumDefs() >= 1)
341    AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II, ResultReg)
342                   .addReg(Op0, Op0IsKill * RegState::Kill)
343                   .addReg(Op1, Op1IsKill * RegState::Kill)
344                   .addReg(Op2, Op2IsKill * RegState::Kill));
345  else {
346    AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II)
347                   .addReg(Op0, Op0IsKill * RegState::Kill)
348                   .addReg(Op1, Op1IsKill * RegState::Kill)
349                   .addReg(Op2, Op2IsKill * RegState::Kill));
350    AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
351                           TII.get(TargetOpcode::COPY), ResultReg)
352                   .addReg(II.ImplicitDefs[0]));
353  }
354  return ResultReg;
355}
356
357unsigned ARMFastISel::FastEmitInst_ri(unsigned MachineInstOpcode,
358                                      const TargetRegisterClass *RC,
359                                      unsigned Op0, bool Op0IsKill,
360                                      uint64_t Imm) {
361  unsigned ResultReg = createResultReg(RC);
362  const MCInstrDesc &II = TII.get(MachineInstOpcode);
363
364  if (II.getNumDefs() >= 1)
365    AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II, ResultReg)
366                   .addReg(Op0, Op0IsKill * RegState::Kill)
367                   .addImm(Imm));
368  else {
369    AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II)
370                   .addReg(Op0, Op0IsKill * RegState::Kill)
371                   .addImm(Imm));
372    AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
373                           TII.get(TargetOpcode::COPY), ResultReg)
374                   .addReg(II.ImplicitDefs[0]));
375  }
376  return ResultReg;
377}
378
379unsigned ARMFastISel::FastEmitInst_rf(unsigned MachineInstOpcode,
380                                      const TargetRegisterClass *RC,
381                                      unsigned Op0, bool Op0IsKill,
382                                      const ConstantFP *FPImm) {
383  unsigned ResultReg = createResultReg(RC);
384  const MCInstrDesc &II = TII.get(MachineInstOpcode);
385
386  if (II.getNumDefs() >= 1)
387    AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II, ResultReg)
388                   .addReg(Op0, Op0IsKill * RegState::Kill)
389                   .addFPImm(FPImm));
390  else {
391    AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II)
392                   .addReg(Op0, Op0IsKill * RegState::Kill)
393                   .addFPImm(FPImm));
394    AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
395                           TII.get(TargetOpcode::COPY), ResultReg)
396                   .addReg(II.ImplicitDefs[0]));
397  }
398  return ResultReg;
399}
400
401unsigned ARMFastISel::FastEmitInst_rri(unsigned MachineInstOpcode,
402                                       const TargetRegisterClass *RC,
403                                       unsigned Op0, bool Op0IsKill,
404                                       unsigned Op1, bool Op1IsKill,
405                                       uint64_t Imm) {
406  unsigned ResultReg = createResultReg(RC);
407  const MCInstrDesc &II = TII.get(MachineInstOpcode);
408
409  if (II.getNumDefs() >= 1)
410    AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II, ResultReg)
411                   .addReg(Op0, Op0IsKill * RegState::Kill)
412                   .addReg(Op1, Op1IsKill * RegState::Kill)
413                   .addImm(Imm));
414  else {
415    AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II)
416                   .addReg(Op0, Op0IsKill * RegState::Kill)
417                   .addReg(Op1, Op1IsKill * RegState::Kill)
418                   .addImm(Imm));
419    AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
420                           TII.get(TargetOpcode::COPY), ResultReg)
421                   .addReg(II.ImplicitDefs[0]));
422  }
423  return ResultReg;
424}
425
426unsigned ARMFastISel::FastEmitInst_i(unsigned MachineInstOpcode,
427                                     const TargetRegisterClass *RC,
428                                     uint64_t Imm) {
429  unsigned ResultReg = createResultReg(RC);
430  const MCInstrDesc &II = TII.get(MachineInstOpcode);
431
432  if (II.getNumDefs() >= 1)
433    AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II, ResultReg)
434                   .addImm(Imm));
435  else {
436    AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II)
437                   .addImm(Imm));
438    AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
439                           TII.get(TargetOpcode::COPY), ResultReg)
440                   .addReg(II.ImplicitDefs[0]));
441  }
442  return ResultReg;
443}
444
445unsigned ARMFastISel::FastEmitInst_ii(unsigned MachineInstOpcode,
446                                      const TargetRegisterClass *RC,
447                                      uint64_t Imm1, uint64_t Imm2) {
448  unsigned ResultReg = createResultReg(RC);
449  const MCInstrDesc &II = TII.get(MachineInstOpcode);
450
451  if (II.getNumDefs() >= 1)
452    AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II, ResultReg)
453                    .addImm(Imm1).addImm(Imm2));
454  else {
455    AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II)
456                    .addImm(Imm1).addImm(Imm2));
457    AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
458                            TII.get(TargetOpcode::COPY),
459                            ResultReg)
460                    .addReg(II.ImplicitDefs[0]));
461  }
462  return ResultReg;
463}
464
465unsigned ARMFastISel::FastEmitInst_extractsubreg(MVT RetVT,
466                                                 unsigned Op0, bool Op0IsKill,
467                                                 uint32_t Idx) {
468  unsigned ResultReg = createResultReg(TLI.getRegClassFor(RetVT));
469  assert(TargetRegisterInfo::isVirtualRegister(Op0) &&
470         "Cannot yet extract from physregs");
471  AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt,
472                         DL, TII.get(TargetOpcode::COPY), ResultReg)
473                 .addReg(Op0, getKillRegState(Op0IsKill), Idx));
474  return ResultReg;
475}
476
477// TODO: Don't worry about 64-bit now, but when this is fixed remove the
478// checks from the various callers.
479unsigned ARMFastISel::ARMMoveToFPReg(EVT VT, unsigned SrcReg) {
480  if (VT == MVT::f64) return 0;
481
482  unsigned MoveReg = createResultReg(TLI.getRegClassFor(VT));
483  AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
484                          TII.get(ARM::VMOVRS), MoveReg)
485                  .addReg(SrcReg));
486  return MoveReg;
487}
488
489unsigned ARMFastISel::ARMMoveToIntReg(EVT VT, unsigned SrcReg) {
490  if (VT == MVT::i64) return 0;
491
492  unsigned MoveReg = createResultReg(TLI.getRegClassFor(VT));
493  AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
494                          TII.get(ARM::VMOVSR), MoveReg)
495                  .addReg(SrcReg));
496  return MoveReg;
497}
498
499// For double width floating point we need to materialize two constants
500// (the high and the low) into integer registers then use a move to get
501// the combined constant into an FP reg.
502unsigned ARMFastISel::ARMMaterializeFP(const ConstantFP *CFP, EVT VT) {
503  const APFloat Val = CFP->getValueAPF();
504  bool is64bit = VT == MVT::f64;
505
506  // This checks to see if we can use VFP3 instructions to materialize
507  // a constant, otherwise we have to go through the constant pool.
508  if (TLI.isFPImmLegal(Val, VT)) {
509    int Imm;
510    unsigned Opc;
511    if (is64bit) {
512      Imm = ARM_AM::getFP64Imm(Val);
513      Opc = ARM::FCONSTD;
514    } else {
515      Imm = ARM_AM::getFP32Imm(Val);
516      Opc = ARM::FCONSTS;
517    }
518    unsigned DestReg = createResultReg(TLI.getRegClassFor(VT));
519    AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(Opc),
520                            DestReg)
521                    .addImm(Imm));
522    return DestReg;
523  }
524
525  // Require VFP2 for loading fp constants.
526  if (!Subtarget->hasVFP2()) return false;
527
528  // MachineConstantPool wants an explicit alignment.
529  unsigned Align = TD.getPrefTypeAlignment(CFP->getType());
530  if (Align == 0) {
531    // TODO: Figure out if this is correct.
532    Align = TD.getTypeAllocSize(CFP->getType());
533  }
534  unsigned Idx = MCP.getConstantPoolIndex(cast<Constant>(CFP), Align);
535  unsigned DestReg = createResultReg(TLI.getRegClassFor(VT));
536  unsigned Opc = is64bit ? ARM::VLDRD : ARM::VLDRS;
537
538  // The extra reg is for addrmode5.
539  AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(Opc),
540                          DestReg)
541                  .addConstantPoolIndex(Idx)
542                  .addReg(0));
543  return DestReg;
544}
545
546unsigned ARMFastISel::ARMMaterializeInt(const Constant *C, EVT VT) {
547
548  // For now 32-bit only.
549  if (VT != MVT::i32) return false;
550
551  unsigned DestReg = createResultReg(TLI.getRegClassFor(VT));
552
553  // If we can do this in a single instruction without a constant pool entry
554  // do so now.
555  const ConstantInt *CI = cast<ConstantInt>(C);
556  if (Subtarget->hasV6T2Ops() && isUInt<16>(CI->getSExtValue())) {
557    unsigned Opc = isThumb ? ARM::t2MOVi16 : ARM::MOVi16;
558    AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
559                            TII.get(Opc), DestReg)
560                    .addImm(CI->getSExtValue()));
561    return DestReg;
562  }
563
564  // MachineConstantPool wants an explicit alignment.
565  unsigned Align = TD.getPrefTypeAlignment(C->getType());
566  if (Align == 0) {
567    // TODO: Figure out if this is correct.
568    Align = TD.getTypeAllocSize(C->getType());
569  }
570  unsigned Idx = MCP.getConstantPoolIndex(C, Align);
571
572  if (isThumb)
573    AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
574                            TII.get(ARM::t2LDRpci), DestReg)
575                    .addConstantPoolIndex(Idx));
576  else
577    // The extra immediate is for addrmode2.
578    AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
579                            TII.get(ARM::LDRcp), DestReg)
580                    .addConstantPoolIndex(Idx)
581                    .addImm(0));
582
583  return DestReg;
584}
585
586unsigned ARMFastISel::ARMMaterializeGV(const GlobalValue *GV, EVT VT) {
587  // For now 32-bit only.
588  if (VT != MVT::i32) return 0;
589
590  Reloc::Model RelocM = TM.getRelocationModel();
591
592  // TODO: Need more magic for ARM PIC.
593  if (!isThumb && (RelocM == Reloc::PIC_)) return 0;
594
595  // MachineConstantPool wants an explicit alignment.
596  unsigned Align = TD.getPrefTypeAlignment(GV->getType());
597  if (Align == 0) {
598    // TODO: Figure out if this is correct.
599    Align = TD.getTypeAllocSize(GV->getType());
600  }
601
602  // Grab index.
603  unsigned PCAdj = (RelocM != Reloc::PIC_) ? 0 : (Subtarget->isThumb() ? 4 : 8);
604  unsigned Id = AFI->createPICLabelUId();
605  ARMConstantPoolValue *CPV = ARMConstantPoolConstant::Create(GV, Id,
606                                                              ARMCP::CPValue,
607                                                              PCAdj);
608  unsigned Idx = MCP.getConstantPoolIndex(CPV, Align);
609
610  // Load value.
611  MachineInstrBuilder MIB;
612  unsigned DestReg = createResultReg(TLI.getRegClassFor(VT));
613  if (isThumb) {
614    unsigned Opc = (RelocM != Reloc::PIC_) ? ARM::t2LDRpci : ARM::t2LDRpci_pic;
615    MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(Opc), DestReg)
616          .addConstantPoolIndex(Idx);
617    if (RelocM == Reloc::PIC_)
618      MIB.addImm(Id);
619  } else {
620    // The extra immediate is for addrmode2.
621    MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(ARM::LDRcp),
622                  DestReg)
623          .addConstantPoolIndex(Idx)
624          .addImm(0);
625  }
626  AddOptionalDefs(MIB);
627
628  if (Subtarget->GVIsIndirectSymbol(GV, RelocM)) {
629    unsigned NewDestReg = createResultReg(TLI.getRegClassFor(VT));
630    if (isThumb)
631      MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
632                    TII.get(ARM::t2LDRi12), NewDestReg)
633            .addReg(DestReg)
634            .addImm(0);
635    else
636      MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(ARM::LDRi12),
637                    NewDestReg)
638            .addReg(DestReg)
639            .addImm(0);
640    DestReg = NewDestReg;
641    AddOptionalDefs(MIB);
642  }
643
644  return DestReg;
645}
646
647unsigned ARMFastISel::TargetMaterializeConstant(const Constant *C) {
648  EVT VT = TLI.getValueType(C->getType(), true);
649
650  // Only handle simple types.
651  if (!VT.isSimple()) return 0;
652
653  if (const ConstantFP *CFP = dyn_cast<ConstantFP>(C))
654    return ARMMaterializeFP(CFP, VT);
655  else if (const GlobalValue *GV = dyn_cast<GlobalValue>(C))
656    return ARMMaterializeGV(GV, VT);
657  else if (isa<ConstantInt>(C))
658    return ARMMaterializeInt(C, VT);
659
660  return 0;
661}
662
663unsigned ARMFastISel::TargetMaterializeAlloca(const AllocaInst *AI) {
664  // Don't handle dynamic allocas.
665  if (!FuncInfo.StaticAllocaMap.count(AI)) return 0;
666
667  MVT VT;
668  if (!isLoadTypeLegal(AI->getType(), VT)) return false;
669
670  DenseMap<const AllocaInst*, int>::iterator SI =
671    FuncInfo.StaticAllocaMap.find(AI);
672
673  // This will get lowered later into the correct offsets and registers
674  // via rewriteXFrameIndex.
675  if (SI != FuncInfo.StaticAllocaMap.end()) {
676    TargetRegisterClass* RC = TLI.getRegClassFor(VT);
677    unsigned ResultReg = createResultReg(RC);
678    unsigned Opc = isThumb ? ARM::t2ADDri : ARM::ADDri;
679    AddOptionalDefs(BuildMI(*FuncInfo.MBB, *FuncInfo.InsertPt, DL,
680                            TII.get(Opc), ResultReg)
681                            .addFrameIndex(SI->second)
682                            .addImm(0));
683    return ResultReg;
684  }
685
686  return 0;
687}
688
689bool ARMFastISel::isTypeLegal(Type *Ty, MVT &VT) {
690  EVT evt = TLI.getValueType(Ty, true);
691
692  // Only handle simple types.
693  if (evt == MVT::Other || !evt.isSimple()) return false;
694  VT = evt.getSimpleVT();
695
696  // Handle all legal types, i.e. a register that will directly hold this
697  // value.
698  return TLI.isTypeLegal(VT);
699}
700
701bool ARMFastISel::isLoadTypeLegal(Type *Ty, MVT &VT) {
702  if (isTypeLegal(Ty, VT)) return true;
703
704  // If this is a type than can be sign or zero-extended to a basic operation
705  // go ahead and accept it now.
706  if (VT == MVT::i8 || VT == MVT::i16)
707    return true;
708
709  return false;
710}
711
712// Computes the address to get to an object.
713bool ARMFastISel::ARMComputeAddress(const Value *Obj, Address &Addr) {
714  // Some boilerplate from the X86 FastISel.
715  const User *U = NULL;
716  unsigned Opcode = Instruction::UserOp1;
717  if (const Instruction *I = dyn_cast<Instruction>(Obj)) {
718    // Don't walk into other basic blocks unless the object is an alloca from
719    // another block, otherwise it may not have a virtual register assigned.
720    if (FuncInfo.StaticAllocaMap.count(static_cast<const AllocaInst *>(Obj)) ||
721        FuncInfo.MBBMap[I->getParent()] == FuncInfo.MBB) {
722      Opcode = I->getOpcode();
723      U = I;
724    }
725  } else if (const ConstantExpr *C = dyn_cast<ConstantExpr>(Obj)) {
726    Opcode = C->getOpcode();
727    U = C;
728  }
729
730  if (PointerType *Ty = dyn_cast<PointerType>(Obj->getType()))
731    if (Ty->getAddressSpace() > 255)
732      // Fast instruction selection doesn't support the special
733      // address spaces.
734      return false;
735
736  switch (Opcode) {
737    default:
738    break;
739    case Instruction::BitCast: {
740      // Look through bitcasts.
741      return ARMComputeAddress(U->getOperand(0), Addr);
742    }
743    case Instruction::IntToPtr: {
744      // Look past no-op inttoptrs.
745      if (TLI.getValueType(U->getOperand(0)->getType()) == TLI.getPointerTy())
746        return ARMComputeAddress(U->getOperand(0), Addr);
747      break;
748    }
749    case Instruction::PtrToInt: {
750      // Look past no-op ptrtoints.
751      if (TLI.getValueType(U->getType()) == TLI.getPointerTy())
752        return ARMComputeAddress(U->getOperand(0), Addr);
753      break;
754    }
755    case Instruction::GetElementPtr: {
756      Address SavedAddr = Addr;
757      int TmpOffset = Addr.Offset;
758
759      // Iterate through the GEP folding the constants into offsets where
760      // we can.
761      gep_type_iterator GTI = gep_type_begin(U);
762      for (User::const_op_iterator i = U->op_begin() + 1, e = U->op_end();
763           i != e; ++i, ++GTI) {
764        const Value *Op = *i;
765        if (StructType *STy = dyn_cast<StructType>(*GTI)) {
766          const StructLayout *SL = TD.getStructLayout(STy);
767          unsigned Idx = cast<ConstantInt>(Op)->getZExtValue();
768          TmpOffset += SL->getElementOffset(Idx);
769        } else {
770          uint64_t S = TD.getTypeAllocSize(GTI.getIndexedType());
771          for (;;) {
772            if (const ConstantInt *CI = dyn_cast<ConstantInt>(Op)) {
773              // Constant-offset addressing.
774              TmpOffset += CI->getSExtValue() * S;
775              break;
776            }
777            if (isa<AddOperator>(Op) &&
778                (!isa<Instruction>(Op) ||
779                 FuncInfo.MBBMap[cast<Instruction>(Op)->getParent()]
780                 == FuncInfo.MBB) &&
781                isa<ConstantInt>(cast<AddOperator>(Op)->getOperand(1))) {
782              // An add (in the same block) with a constant operand. Fold the
783              // constant.
784              ConstantInt *CI =
785              cast<ConstantInt>(cast<AddOperator>(Op)->getOperand(1));
786              TmpOffset += CI->getSExtValue() * S;
787              // Iterate on the other operand.
788              Op = cast<AddOperator>(Op)->getOperand(0);
789              continue;
790            }
791            // Unsupported
792            goto unsupported_gep;
793          }
794        }
795      }
796
797      // Try to grab the base operand now.
798      Addr.Offset = TmpOffset;
799      if (ARMComputeAddress(U->getOperand(0), Addr)) return true;
800
801      // We failed, restore everything and try the other options.
802      Addr = SavedAddr;
803
804      unsupported_gep:
805      break;
806    }
807    case Instruction::Alloca: {
808      const AllocaInst *AI = cast<AllocaInst>(Obj);
809      DenseMap<const AllocaInst*, int>::iterator SI =
810        FuncInfo.StaticAllocaMap.find(AI);
811      if (SI != FuncInfo.StaticAllocaMap.end()) {
812        Addr.BaseType = Address::FrameIndexBase;
813        Addr.Base.FI = SI->second;
814        return true;
815      }
816      break;
817    }
818  }
819
820  // Materialize the global variable's address into a reg which can
821  // then be used later to load the variable.
822  if (const GlobalValue *GV = dyn_cast<GlobalValue>(Obj)) {
823    unsigned Tmp = ARMMaterializeGV(GV, TLI.getValueType(Obj->getType()));
824    if (Tmp == 0) return false;
825
826    Addr.Base.Reg = Tmp;
827    return true;
828  }
829
830  // Try to get this in a register if nothing else has worked.
831  if (Addr.Base.Reg == 0) Addr.Base.Reg = getRegForValue(Obj);
832  return Addr.Base.Reg != 0;
833}
834
835void ARMFastISel::ARMSimplifyAddress(Address &Addr, EVT VT) {
836
837  assert(VT.isSimple() && "Non-simple types are invalid here!");
838
839  bool needsLowering = false;
840  switch (VT.getSimpleVT().SimpleTy) {
841    default:
842      assert(false && "Unhandled load/store type!");
843    case MVT::i1:
844    case MVT::i8:
845    case MVT::i16:
846    case MVT::i32:
847      // Integer loads/stores handle 12-bit offsets.
848      needsLowering = ((Addr.Offset & 0xfff) != Addr.Offset);
849      break;
850    case MVT::f32:
851    case MVT::f64:
852      // Floating point operands handle 8-bit offsets.
853      needsLowering = ((Addr.Offset & 0xff) != Addr.Offset);
854      break;
855  }
856
857  // If this is a stack pointer and the offset needs to be simplified then
858  // put the alloca address into a register, set the base type back to
859  // register and continue. This should almost never happen.
860  if (needsLowering && Addr.BaseType == Address::FrameIndexBase) {
861    TargetRegisterClass *RC = isThumb ? ARM::tGPRRegisterClass :
862                              ARM::GPRRegisterClass;
863    unsigned ResultReg = createResultReg(RC);
864    unsigned Opc = isThumb ? ARM::t2ADDri : ARM::ADDri;
865    AddOptionalDefs(BuildMI(*FuncInfo.MBB, *FuncInfo.InsertPt, DL,
866                            TII.get(Opc), ResultReg)
867                            .addFrameIndex(Addr.Base.FI)
868                            .addImm(0));
869    Addr.Base.Reg = ResultReg;
870    Addr.BaseType = Address::RegBase;
871  }
872
873  // Since the offset is too large for the load/store instruction
874  // get the reg+offset into a register.
875  if (needsLowering) {
876    Addr.Base.Reg = FastEmit_ri_(MVT::i32, ISD::ADD, Addr.Base.Reg,
877                                 /*Op0IsKill*/false, Addr.Offset, MVT::i32);
878    Addr.Offset = 0;
879  }
880}
881
882void ARMFastISel::AddLoadStoreOperands(EVT VT, Address &Addr,
883                                       const MachineInstrBuilder &MIB,
884                                       unsigned Flags) {
885  // addrmode5 output depends on the selection dag addressing dividing the
886  // offset by 4 that it then later multiplies. Do this here as well.
887  if (VT.getSimpleVT().SimpleTy == MVT::f32 ||
888      VT.getSimpleVT().SimpleTy == MVT::f64)
889    Addr.Offset /= 4;
890
891  // Frame base works a bit differently. Handle it separately.
892  if (Addr.BaseType == Address::FrameIndexBase) {
893    int FI = Addr.Base.FI;
894    int Offset = Addr.Offset;
895    MachineMemOperand *MMO =
896          FuncInfo.MF->getMachineMemOperand(
897                                  MachinePointerInfo::getFixedStack(FI, Offset),
898                                  Flags,
899                                  MFI.getObjectSize(FI),
900                                  MFI.getObjectAlignment(FI));
901    // Now add the rest of the operands.
902    MIB.addFrameIndex(FI);
903
904    // ARM halfword load/stores need an additional operand.
905    if (!isThumb && VT.getSimpleVT().SimpleTy == MVT::i16) MIB.addReg(0);
906
907    MIB.addImm(Addr.Offset);
908    MIB.addMemOperand(MMO);
909  } else {
910    // Now add the rest of the operands.
911    MIB.addReg(Addr.Base.Reg);
912
913    // ARM halfword load/stores need an additional operand.
914    if (!isThumb && VT.getSimpleVT().SimpleTy == MVT::i16) MIB.addReg(0);
915
916    MIB.addImm(Addr.Offset);
917  }
918  AddOptionalDefs(MIB);
919}
920
921bool ARMFastISel::ARMEmitLoad(EVT VT, unsigned &ResultReg, Address &Addr) {
922
923  assert(VT.isSimple() && "Non-simple types are invalid here!");
924  unsigned Opc;
925  TargetRegisterClass *RC;
926  switch (VT.getSimpleVT().SimpleTy) {
927    // This is mostly going to be Neon/vector support.
928    default: return false;
929    case MVT::i16:
930      Opc = isThumb ? ARM::t2LDRHi12 : ARM::LDRH;
931      RC = ARM::GPRRegisterClass;
932      break;
933    case MVT::i8:
934      Opc = isThumb ? ARM::t2LDRBi12 : ARM::LDRBi12;
935      RC = ARM::GPRRegisterClass;
936      break;
937    case MVT::i32:
938      Opc = isThumb ? ARM::t2LDRi12 : ARM::LDRi12;
939      RC = ARM::GPRRegisterClass;
940      break;
941    case MVT::f32:
942      Opc = ARM::VLDRS;
943      RC = TLI.getRegClassFor(VT);
944      break;
945    case MVT::f64:
946      Opc = ARM::VLDRD;
947      RC = TLI.getRegClassFor(VT);
948      break;
949  }
950  // Simplify this down to something we can handle.
951  ARMSimplifyAddress(Addr, VT);
952
953  // Create the base instruction, then add the operands.
954  ResultReg = createResultReg(RC);
955  MachineInstrBuilder MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
956                                    TII.get(Opc), ResultReg);
957  AddLoadStoreOperands(VT, Addr, MIB, MachineMemOperand::MOLoad);
958  return true;
959}
960
961bool ARMFastISel::SelectLoad(const Instruction *I) {
962  // Atomic loads need special handling.
963  if (cast<LoadInst>(I)->isAtomic())
964    return false;
965
966  // Verify we have a legal type before going any further.
967  MVT VT;
968  if (!isLoadTypeLegal(I->getType(), VT))
969    return false;
970
971  // See if we can handle this address.
972  Address Addr;
973  if (!ARMComputeAddress(I->getOperand(0), Addr)) return false;
974
975  unsigned ResultReg;
976  if (!ARMEmitLoad(VT, ResultReg, Addr)) return false;
977  UpdateValueMap(I, ResultReg);
978  return true;
979}
980
981bool ARMFastISel::ARMEmitStore(EVT VT, unsigned SrcReg, Address &Addr) {
982  unsigned StrOpc;
983  switch (VT.getSimpleVT().SimpleTy) {
984    // This is mostly going to be Neon/vector support.
985    default: return false;
986    case MVT::i1: {
987      unsigned Res = createResultReg(isThumb ? ARM::tGPRRegisterClass :
988                                               ARM::GPRRegisterClass);
989      unsigned Opc = isThumb ? ARM::t2ANDri : ARM::ANDri;
990      AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
991                              TII.get(Opc), Res)
992                      .addReg(SrcReg).addImm(1));
993      SrcReg = Res;
994    } // Fallthrough here.
995    case MVT::i8:
996      StrOpc = isThumb ? ARM::t2STRBi12 : ARM::STRBi12;
997      break;
998    case MVT::i16:
999      StrOpc = isThumb ? ARM::t2STRHi12 : ARM::STRH;
1000      break;
1001    case MVT::i32:
1002      StrOpc = isThumb ? ARM::t2STRi12 : ARM::STRi12;
1003      break;
1004    case MVT::f32:
1005      if (!Subtarget->hasVFP2()) return false;
1006      StrOpc = ARM::VSTRS;
1007      break;
1008    case MVT::f64:
1009      if (!Subtarget->hasVFP2()) return false;
1010      StrOpc = ARM::VSTRD;
1011      break;
1012  }
1013  // Simplify this down to something we can handle.
1014  ARMSimplifyAddress(Addr, VT);
1015
1016  // Create the base instruction, then add the operands.
1017  MachineInstrBuilder MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
1018                                    TII.get(StrOpc))
1019                            .addReg(SrcReg, getKillRegState(true));
1020  AddLoadStoreOperands(VT, Addr, MIB, MachineMemOperand::MOStore);
1021  return true;
1022}
1023
1024bool ARMFastISel::SelectStore(const Instruction *I) {
1025  Value *Op0 = I->getOperand(0);
1026  unsigned SrcReg = 0;
1027
1028  // Atomic stores need special handling.
1029  if (cast<StoreInst>(I)->isAtomic())
1030    return false;
1031
1032  // Verify we have a legal type before going any further.
1033  MVT VT;
1034  if (!isLoadTypeLegal(I->getOperand(0)->getType(), VT))
1035    return false;
1036
1037  // Get the value to be stored into a register.
1038  SrcReg = getRegForValue(Op0);
1039  if (SrcReg == 0) return false;
1040
1041  // See if we can handle this address.
1042  Address Addr;
1043  if (!ARMComputeAddress(I->getOperand(1), Addr))
1044    return false;
1045
1046  if (!ARMEmitStore(VT, SrcReg, Addr)) return false;
1047  return true;
1048}
1049
1050static ARMCC::CondCodes getComparePred(CmpInst::Predicate Pred) {
1051  switch (Pred) {
1052    // Needs two compares...
1053    case CmpInst::FCMP_ONE:
1054    case CmpInst::FCMP_UEQ:
1055    default:
1056      // AL is our "false" for now. The other two need more compares.
1057      return ARMCC::AL;
1058    case CmpInst::ICMP_EQ:
1059    case CmpInst::FCMP_OEQ:
1060      return ARMCC::EQ;
1061    case CmpInst::ICMP_SGT:
1062    case CmpInst::FCMP_OGT:
1063      return ARMCC::GT;
1064    case CmpInst::ICMP_SGE:
1065    case CmpInst::FCMP_OGE:
1066      return ARMCC::GE;
1067    case CmpInst::ICMP_UGT:
1068    case CmpInst::FCMP_UGT:
1069      return ARMCC::HI;
1070    case CmpInst::FCMP_OLT:
1071      return ARMCC::MI;
1072    case CmpInst::ICMP_ULE:
1073    case CmpInst::FCMP_OLE:
1074      return ARMCC::LS;
1075    case CmpInst::FCMP_ORD:
1076      return ARMCC::VC;
1077    case CmpInst::FCMP_UNO:
1078      return ARMCC::VS;
1079    case CmpInst::FCMP_UGE:
1080      return ARMCC::PL;
1081    case CmpInst::ICMP_SLT:
1082    case CmpInst::FCMP_ULT:
1083      return ARMCC::LT;
1084    case CmpInst::ICMP_SLE:
1085    case CmpInst::FCMP_ULE:
1086      return ARMCC::LE;
1087    case CmpInst::FCMP_UNE:
1088    case CmpInst::ICMP_NE:
1089      return ARMCC::NE;
1090    case CmpInst::ICMP_UGE:
1091      return ARMCC::HS;
1092    case CmpInst::ICMP_ULT:
1093      return ARMCC::LO;
1094  }
1095}
1096
1097bool ARMFastISel::SelectBranch(const Instruction *I) {
1098  const BranchInst *BI = cast<BranchInst>(I);
1099  MachineBasicBlock *TBB = FuncInfo.MBBMap[BI->getSuccessor(0)];
1100  MachineBasicBlock *FBB = FuncInfo.MBBMap[BI->getSuccessor(1)];
1101
1102  // Simple branch support.
1103
1104  // If we can, avoid recomputing the compare - redoing it could lead to wonky
1105  // behavior.
1106  if (const CmpInst *CI = dyn_cast<CmpInst>(BI->getCondition())) {
1107    if (CI->hasOneUse() && (CI->getParent() == I->getParent())) {
1108
1109      // Get the compare predicate.
1110      // Try to take advantage of fallthrough opportunities.
1111      CmpInst::Predicate Predicate = CI->getPredicate();
1112      if (FuncInfo.MBB->isLayoutSuccessor(TBB)) {
1113        std::swap(TBB, FBB);
1114        Predicate = CmpInst::getInversePredicate(Predicate);
1115      }
1116
1117      ARMCC::CondCodes ARMPred = getComparePred(Predicate);
1118
1119      // We may not handle every CC for now.
1120      if (ARMPred == ARMCC::AL) return false;
1121
1122      // Emit the compare.
1123      if (!ARMEmitCmp(CI->getOperand(0), CI->getOperand(1), CI->isUnsigned()))
1124        return false;
1125
1126      unsigned BrOpc = isThumb ? ARM::t2Bcc : ARM::Bcc;
1127      BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(BrOpc))
1128      .addMBB(TBB).addImm(ARMPred).addReg(ARM::CPSR);
1129      FastEmitBranch(FBB, DL);
1130      FuncInfo.MBB->addSuccessor(TBB);
1131      return true;
1132    }
1133  } else if (TruncInst *TI = dyn_cast<TruncInst>(BI->getCondition())) {
1134    MVT SourceVT;
1135    if (TI->hasOneUse() && TI->getParent() == I->getParent() &&
1136        (isLoadTypeLegal(TI->getOperand(0)->getType(), SourceVT))) {
1137      unsigned TstOpc = isThumb ? ARM::t2TSTri : ARM::TSTri;
1138      unsigned OpReg = getRegForValue(TI->getOperand(0));
1139      AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
1140                              TII.get(TstOpc))
1141                      .addReg(OpReg).addImm(1));
1142
1143      unsigned CCMode = ARMCC::NE;
1144      if (FuncInfo.MBB->isLayoutSuccessor(TBB)) {
1145        std::swap(TBB, FBB);
1146        CCMode = ARMCC::EQ;
1147      }
1148
1149      unsigned BrOpc = isThumb ? ARM::t2Bcc : ARM::Bcc;
1150      BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(BrOpc))
1151      .addMBB(TBB).addImm(CCMode).addReg(ARM::CPSR);
1152
1153      FastEmitBranch(FBB, DL);
1154      FuncInfo.MBB->addSuccessor(TBB);
1155      return true;
1156    }
1157  } else if (const ConstantInt *CI =
1158             dyn_cast<ConstantInt>(BI->getCondition())) {
1159    uint64_t Imm = CI->getZExtValue();
1160    MachineBasicBlock *Target = (Imm == 0) ? FBB : TBB;
1161    FastEmitBranch(Target, DL);
1162    return true;
1163  }
1164
1165  unsigned CmpReg = getRegForValue(BI->getCondition());
1166  if (CmpReg == 0) return false;
1167
1168  // We've been divorced from our compare!  Our block was split, and
1169  // now our compare lives in a predecessor block.  We musn't
1170  // re-compare here, as the children of the compare aren't guaranteed
1171  // live across the block boundary (we *could* check for this).
1172  // Regardless, the compare has been done in the predecessor block,
1173  // and it left a value for us in a virtual register.  Ergo, we test
1174  // the one-bit value left in the virtual register.
1175  unsigned TstOpc = isThumb ? ARM::t2TSTri : ARM::TSTri;
1176  AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(TstOpc))
1177                  .addReg(CmpReg).addImm(1));
1178
1179  unsigned CCMode = ARMCC::NE;
1180  if (FuncInfo.MBB->isLayoutSuccessor(TBB)) {
1181    std::swap(TBB, FBB);
1182    CCMode = ARMCC::EQ;
1183  }
1184
1185  unsigned BrOpc = isThumb ? ARM::t2Bcc : ARM::Bcc;
1186  BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(BrOpc))
1187                  .addMBB(TBB).addImm(CCMode).addReg(ARM::CPSR);
1188  FastEmitBranch(FBB, DL);
1189  FuncInfo.MBB->addSuccessor(TBB);
1190  return true;
1191}
1192
1193bool ARMFastISel::ARMEmitCmp(const Value *Src1Value, const Value *Src2Value,
1194                             bool isZExt) {
1195  Type *Ty = Src1Value->getType();
1196  EVT SrcVT = TLI.getValueType(Ty, true);
1197  if (!SrcVT.isSimple()) return false;
1198
1199  bool isFloat = (Ty->isFloatTy() || Ty->isDoubleTy());
1200  if (isFloat && !Subtarget->hasVFP2())
1201    return false;
1202
1203  unsigned CmpOpc;
1204  bool needsExt = false;
1205  switch (SrcVT.getSimpleVT().SimpleTy) {
1206    default: return false;
1207    // TODO: Verify compares.
1208    case MVT::f32:
1209      CmpOpc = ARM::VCMPES;
1210      break;
1211    case MVT::f64:
1212      CmpOpc = ARM::VCMPED;
1213      break;
1214    case MVT::i1:
1215    case MVT::i8:
1216    case MVT::i16:
1217      needsExt = true;
1218    // Intentional fall-through.
1219    case MVT::i32:
1220      CmpOpc = isThumb ? ARM::t2CMPrr : ARM::CMPrr;
1221      break;
1222  }
1223
1224  unsigned SrcReg1 = getRegForValue(Src1Value);
1225  if (SrcReg1 == 0) return false;
1226
1227  unsigned SrcReg2 = getRegForValue(Src2Value);
1228  if (SrcReg2 == 0) return false;
1229
1230  // We have i1, i8, or i16, we need to either zero extend or sign extend.
1231  if (needsExt) {
1232    unsigned ResultReg;
1233    EVT DestVT = MVT::i32;
1234    ResultReg = ARMEmitIntExt(SrcVT, SrcReg1, DestVT, isZExt);
1235    if (ResultReg == 0) return false;
1236    SrcReg1 = ResultReg;
1237    ResultReg = ARMEmitIntExt(SrcVT, SrcReg2, DestVT, isZExt);
1238    if (ResultReg == 0) return false;
1239    SrcReg2 = ResultReg;
1240  }
1241
1242  AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(CmpOpc))
1243                  .addReg(SrcReg1).addReg(SrcReg2));
1244
1245  // For floating point we need to move the result to a comparison register
1246  // that we can then use for branches.
1247  if (Ty->isFloatTy() || Ty->isDoubleTy())
1248    AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
1249                            TII.get(ARM::FMSTAT)));
1250  return true;
1251}
1252
1253bool ARMFastISel::SelectCmp(const Instruction *I) {
1254  const CmpInst *CI = cast<CmpInst>(I);
1255  Type *Ty = CI->getOperand(0)->getType();
1256
1257  // Get the compare predicate.
1258  ARMCC::CondCodes ARMPred = getComparePred(CI->getPredicate());
1259
1260  // We may not handle every CC for now.
1261  if (ARMPred == ARMCC::AL) return false;
1262
1263  // Emit the compare.
1264  if (!ARMEmitCmp(CI->getOperand(0), CI->getOperand(1), CI->isUnsigned()))
1265    return false;
1266
1267  // Now set a register based on the comparison. Explicitly set the predicates
1268  // here.
1269  unsigned MovCCOpc = isThumb ? ARM::t2MOVCCi : ARM::MOVCCi;
1270  TargetRegisterClass *RC = isThumb ? ARM::rGPRRegisterClass
1271                                    : ARM::GPRRegisterClass;
1272  unsigned DestReg = createResultReg(RC);
1273  Constant *Zero = ConstantInt::get(Type::getInt32Ty(*Context), 0);
1274  unsigned ZeroReg = TargetMaterializeConstant(Zero);
1275  bool isFloat = (Ty->isFloatTy() || Ty->isDoubleTy());
1276  unsigned CondReg = isFloat ? ARM::FPSCR : ARM::CPSR;
1277  BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(MovCCOpc), DestReg)
1278          .addReg(ZeroReg).addImm(1)
1279          .addImm(ARMPred).addReg(CondReg);
1280
1281  UpdateValueMap(I, DestReg);
1282  return true;
1283}
1284
1285bool ARMFastISel::SelectFPExt(const Instruction *I) {
1286  // Make sure we have VFP and that we're extending float to double.
1287  if (!Subtarget->hasVFP2()) return false;
1288
1289  Value *V = I->getOperand(0);
1290  if (!I->getType()->isDoubleTy() ||
1291      !V->getType()->isFloatTy()) return false;
1292
1293  unsigned Op = getRegForValue(V);
1294  if (Op == 0) return false;
1295
1296  unsigned Result = createResultReg(ARM::DPRRegisterClass);
1297  AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
1298                          TII.get(ARM::VCVTDS), Result)
1299                  .addReg(Op));
1300  UpdateValueMap(I, Result);
1301  return true;
1302}
1303
1304bool ARMFastISel::SelectFPTrunc(const Instruction *I) {
1305  // Make sure we have VFP and that we're truncating double to float.
1306  if (!Subtarget->hasVFP2()) return false;
1307
1308  Value *V = I->getOperand(0);
1309  if (!(I->getType()->isFloatTy() &&
1310        V->getType()->isDoubleTy())) return false;
1311
1312  unsigned Op = getRegForValue(V);
1313  if (Op == 0) return false;
1314
1315  unsigned Result = createResultReg(ARM::SPRRegisterClass);
1316  AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
1317                          TII.get(ARM::VCVTSD), Result)
1318                  .addReg(Op));
1319  UpdateValueMap(I, Result);
1320  return true;
1321}
1322
1323bool ARMFastISel::SelectSIToFP(const Instruction *I) {
1324  // Make sure we have VFP.
1325  if (!Subtarget->hasVFP2()) return false;
1326
1327  MVT DstVT;
1328  Type *Ty = I->getType();
1329  if (!isTypeLegal(Ty, DstVT))
1330    return false;
1331
1332  // FIXME: Handle sign-extension where necessary.
1333  if (!I->getOperand(0)->getType()->isIntegerTy(32))
1334    return false;
1335
1336  unsigned Op = getRegForValue(I->getOperand(0));
1337  if (Op == 0) return false;
1338
1339  // The conversion routine works on fp-reg to fp-reg and the operand above
1340  // was an integer, move it to the fp registers if possible.
1341  unsigned FP = ARMMoveToFPReg(MVT::f32, Op);
1342  if (FP == 0) return false;
1343
1344  unsigned Opc;
1345  if (Ty->isFloatTy()) Opc = ARM::VSITOS;
1346  else if (Ty->isDoubleTy()) Opc = ARM::VSITOD;
1347  else return false;
1348
1349  unsigned ResultReg = createResultReg(TLI.getRegClassFor(DstVT));
1350  AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(Opc),
1351                          ResultReg)
1352                  .addReg(FP));
1353  UpdateValueMap(I, ResultReg);
1354  return true;
1355}
1356
1357bool ARMFastISel::SelectFPToSI(const Instruction *I) {
1358  // Make sure we have VFP.
1359  if (!Subtarget->hasVFP2()) return false;
1360
1361  MVT DstVT;
1362  Type *RetTy = I->getType();
1363  if (!isTypeLegal(RetTy, DstVT))
1364    return false;
1365
1366  unsigned Op = getRegForValue(I->getOperand(0));
1367  if (Op == 0) return false;
1368
1369  unsigned Opc;
1370  Type *OpTy = I->getOperand(0)->getType();
1371  if (OpTy->isFloatTy()) Opc = ARM::VTOSIZS;
1372  else if (OpTy->isDoubleTy()) Opc = ARM::VTOSIZD;
1373  else return false;
1374
1375  // f64->s32 or f32->s32 both need an intermediate f32 reg.
1376  unsigned ResultReg = createResultReg(TLI.getRegClassFor(MVT::f32));
1377  AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(Opc),
1378                          ResultReg)
1379                  .addReg(Op));
1380
1381  // This result needs to be in an integer register, but the conversion only
1382  // takes place in fp-regs.
1383  unsigned IntReg = ARMMoveToIntReg(DstVT, ResultReg);
1384  if (IntReg == 0) return false;
1385
1386  UpdateValueMap(I, IntReg);
1387  return true;
1388}
1389
1390bool ARMFastISel::SelectSelect(const Instruction *I) {
1391  MVT VT;
1392  if (!isTypeLegal(I->getType(), VT))
1393    return false;
1394
1395  // Things need to be register sized for register moves.
1396  if (VT != MVT::i32) return false;
1397  const TargetRegisterClass *RC = TLI.getRegClassFor(VT);
1398
1399  unsigned CondReg = getRegForValue(I->getOperand(0));
1400  if (CondReg == 0) return false;
1401  unsigned Op1Reg = getRegForValue(I->getOperand(1));
1402  if (Op1Reg == 0) return false;
1403  unsigned Op2Reg = getRegForValue(I->getOperand(2));
1404  if (Op2Reg == 0) return false;
1405
1406  unsigned CmpOpc = isThumb ? ARM::t2TSTri : ARM::TSTri;
1407  AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(CmpOpc))
1408                  .addReg(CondReg).addImm(1));
1409  unsigned ResultReg = createResultReg(RC);
1410  unsigned MovCCOpc = isThumb ? ARM::t2MOVCCr : ARM::MOVCCr;
1411  BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(MovCCOpc), ResultReg)
1412    .addReg(Op1Reg).addReg(Op2Reg)
1413    .addImm(ARMCC::EQ).addReg(ARM::CPSR);
1414  UpdateValueMap(I, ResultReg);
1415  return true;
1416}
1417
1418bool ARMFastISel::SelectSDiv(const Instruction *I) {
1419  MVT VT;
1420  Type *Ty = I->getType();
1421  if (!isTypeLegal(Ty, VT))
1422    return false;
1423
1424  // If we have integer div support we should have selected this automagically.
1425  // In case we have a real miss go ahead and return false and we'll pick
1426  // it up later.
1427  if (Subtarget->hasDivide()) return false;
1428
1429  // Otherwise emit a libcall.
1430  RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
1431  if (VT == MVT::i8)
1432    LC = RTLIB::SDIV_I8;
1433  else if (VT == MVT::i16)
1434    LC = RTLIB::SDIV_I16;
1435  else if (VT == MVT::i32)
1436    LC = RTLIB::SDIV_I32;
1437  else if (VT == MVT::i64)
1438    LC = RTLIB::SDIV_I64;
1439  else if (VT == MVT::i128)
1440    LC = RTLIB::SDIV_I128;
1441  assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unsupported SDIV!");
1442
1443  return ARMEmitLibcall(I, LC);
1444}
1445
1446bool ARMFastISel::SelectSRem(const Instruction *I) {
1447  MVT VT;
1448  Type *Ty = I->getType();
1449  if (!isTypeLegal(Ty, VT))
1450    return false;
1451
1452  RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
1453  if (VT == MVT::i8)
1454    LC = RTLIB::SREM_I8;
1455  else if (VT == MVT::i16)
1456    LC = RTLIB::SREM_I16;
1457  else if (VT == MVT::i32)
1458    LC = RTLIB::SREM_I32;
1459  else if (VT == MVT::i64)
1460    LC = RTLIB::SREM_I64;
1461  else if (VT == MVT::i128)
1462    LC = RTLIB::SREM_I128;
1463  assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unsupported SREM!");
1464
1465  return ARMEmitLibcall(I, LC);
1466}
1467
1468bool ARMFastISel::SelectBinaryOp(const Instruction *I, unsigned ISDOpcode) {
1469  EVT VT  = TLI.getValueType(I->getType(), true);
1470
1471  // We can get here in the case when we want to use NEON for our fp
1472  // operations, but can't figure out how to. Just use the vfp instructions
1473  // if we have them.
1474  // FIXME: It'd be nice to use NEON instructions.
1475  Type *Ty = I->getType();
1476  bool isFloat = (Ty->isDoubleTy() || Ty->isFloatTy());
1477  if (isFloat && !Subtarget->hasVFP2())
1478    return false;
1479
1480  unsigned Op1 = getRegForValue(I->getOperand(0));
1481  if (Op1 == 0) return false;
1482
1483  unsigned Op2 = getRegForValue(I->getOperand(1));
1484  if (Op2 == 0) return false;
1485
1486  unsigned Opc;
1487  bool is64bit = VT == MVT::f64 || VT == MVT::i64;
1488  switch (ISDOpcode) {
1489    default: return false;
1490    case ISD::FADD:
1491      Opc = is64bit ? ARM::VADDD : ARM::VADDS;
1492      break;
1493    case ISD::FSUB:
1494      Opc = is64bit ? ARM::VSUBD : ARM::VSUBS;
1495      break;
1496    case ISD::FMUL:
1497      Opc = is64bit ? ARM::VMULD : ARM::VMULS;
1498      break;
1499  }
1500  unsigned ResultReg = createResultReg(TLI.getRegClassFor(VT));
1501  AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
1502                          TII.get(Opc), ResultReg)
1503                  .addReg(Op1).addReg(Op2));
1504  UpdateValueMap(I, ResultReg);
1505  return true;
1506}
1507
1508// Call Handling Code
1509
1510bool ARMFastISel::FastEmitExtend(ISD::NodeType Opc, EVT DstVT, unsigned Src,
1511                                 EVT SrcVT, unsigned &ResultReg) {
1512  unsigned RR = FastEmit_r(SrcVT.getSimpleVT(), DstVT.getSimpleVT(), Opc,
1513                           Src, /*TODO: Kill=*/false);
1514
1515  if (RR != 0) {
1516    ResultReg = RR;
1517    return true;
1518  } else
1519    return false;
1520}
1521
1522// This is largely taken directly from CCAssignFnForNode - we don't support
1523// varargs in FastISel so that part has been removed.
1524// TODO: We may not support all of this.
1525CCAssignFn *ARMFastISel::CCAssignFnForCall(CallingConv::ID CC, bool Return) {
1526  switch (CC) {
1527  default:
1528    llvm_unreachable("Unsupported calling convention");
1529  case CallingConv::Fast:
1530    // Ignore fastcc. Silence compiler warnings.
1531    (void)RetFastCC_ARM_APCS;
1532    (void)FastCC_ARM_APCS;
1533    // Fallthrough
1534  case CallingConv::C:
1535    // Use target triple & subtarget features to do actual dispatch.
1536    if (Subtarget->isAAPCS_ABI()) {
1537      if (Subtarget->hasVFP2() &&
1538          FloatABIType == FloatABI::Hard)
1539        return (Return ? RetCC_ARM_AAPCS_VFP: CC_ARM_AAPCS_VFP);
1540      else
1541        return (Return ? RetCC_ARM_AAPCS: CC_ARM_AAPCS);
1542    } else
1543        return (Return ? RetCC_ARM_APCS: CC_ARM_APCS);
1544  case CallingConv::ARM_AAPCS_VFP:
1545    return (Return ? RetCC_ARM_AAPCS_VFP: CC_ARM_AAPCS_VFP);
1546  case CallingConv::ARM_AAPCS:
1547    return (Return ? RetCC_ARM_AAPCS: CC_ARM_AAPCS);
1548  case CallingConv::ARM_APCS:
1549    return (Return ? RetCC_ARM_APCS: CC_ARM_APCS);
1550  }
1551}
1552
1553bool ARMFastISel::ProcessCallArgs(SmallVectorImpl<Value*> &Args,
1554                                  SmallVectorImpl<unsigned> &ArgRegs,
1555                                  SmallVectorImpl<MVT> &ArgVTs,
1556                                  SmallVectorImpl<ISD::ArgFlagsTy> &ArgFlags,
1557                                  SmallVectorImpl<unsigned> &RegArgs,
1558                                  CallingConv::ID CC,
1559                                  unsigned &NumBytes) {
1560  SmallVector<CCValAssign, 16> ArgLocs;
1561  CCState CCInfo(CC, false, *FuncInfo.MF, TM, ArgLocs, *Context);
1562  CCInfo.AnalyzeCallOperands(ArgVTs, ArgFlags, CCAssignFnForCall(CC, false));
1563
1564  // Get a count of how many bytes are to be pushed on the stack.
1565  NumBytes = CCInfo.getNextStackOffset();
1566
1567  // Issue CALLSEQ_START
1568  unsigned AdjStackDown = TII.getCallFrameSetupOpcode();
1569  AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
1570                          TII.get(AdjStackDown))
1571                  .addImm(NumBytes));
1572
1573  // Process the args.
1574  for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
1575    CCValAssign &VA = ArgLocs[i];
1576    unsigned Arg = ArgRegs[VA.getValNo()];
1577    MVT ArgVT = ArgVTs[VA.getValNo()];
1578
1579    // We don't handle NEON/vector parameters yet.
1580    if (ArgVT.isVector() || ArgVT.getSizeInBits() > 64)
1581      return false;
1582
1583    // Handle arg promotion, etc.
1584    switch (VA.getLocInfo()) {
1585      case CCValAssign::Full: break;
1586      case CCValAssign::SExt: {
1587        bool Emitted = FastEmitExtend(ISD::SIGN_EXTEND, VA.getLocVT(),
1588                                         Arg, ArgVT, Arg);
1589        assert(Emitted && "Failed to emit a sext!"); (void)Emitted;
1590        Emitted = true;
1591        ArgVT = VA.getLocVT();
1592        break;
1593      }
1594      case CCValAssign::ZExt: {
1595        bool Emitted = FastEmitExtend(ISD::ZERO_EXTEND, VA.getLocVT(),
1596                                         Arg, ArgVT, Arg);
1597        assert(Emitted && "Failed to emit a zext!"); (void)Emitted;
1598        Emitted = true;
1599        ArgVT = VA.getLocVT();
1600        break;
1601      }
1602      case CCValAssign::AExt: {
1603        bool Emitted = FastEmitExtend(ISD::ANY_EXTEND, VA.getLocVT(),
1604                                         Arg, ArgVT, Arg);
1605        if (!Emitted)
1606          Emitted = FastEmitExtend(ISD::ZERO_EXTEND, VA.getLocVT(),
1607                                      Arg, ArgVT, Arg);
1608        if (!Emitted)
1609          Emitted = FastEmitExtend(ISD::SIGN_EXTEND, VA.getLocVT(),
1610                                      Arg, ArgVT, Arg);
1611
1612        assert(Emitted && "Failed to emit a aext!"); (void)Emitted;
1613        ArgVT = VA.getLocVT();
1614        break;
1615      }
1616      case CCValAssign::BCvt: {
1617        unsigned BC = FastEmit_r(ArgVT, VA.getLocVT(), ISD::BITCAST, Arg,
1618                                 /*TODO: Kill=*/false);
1619        assert(BC != 0 && "Failed to emit a bitcast!");
1620        Arg = BC;
1621        ArgVT = VA.getLocVT();
1622        break;
1623      }
1624      default: llvm_unreachable("Unknown arg promotion!");
1625    }
1626
1627    // Now copy/store arg to correct locations.
1628    if (VA.isRegLoc() && !VA.needsCustom()) {
1629      BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(TargetOpcode::COPY),
1630              VA.getLocReg())
1631      .addReg(Arg);
1632      RegArgs.push_back(VA.getLocReg());
1633    } else if (VA.needsCustom()) {
1634      // TODO: We need custom lowering for vector (v2f64) args.
1635      if (VA.getLocVT() != MVT::f64) return false;
1636
1637      CCValAssign &NextVA = ArgLocs[++i];
1638
1639      // TODO: Only handle register args for now.
1640      if(!(VA.isRegLoc() && NextVA.isRegLoc())) return false;
1641
1642      AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
1643                              TII.get(ARM::VMOVRRD), VA.getLocReg())
1644                      .addReg(NextVA.getLocReg(), RegState::Define)
1645                      .addReg(Arg));
1646      RegArgs.push_back(VA.getLocReg());
1647      RegArgs.push_back(NextVA.getLocReg());
1648    } else {
1649      assert(VA.isMemLoc());
1650      // Need to store on the stack.
1651      Address Addr;
1652      Addr.BaseType = Address::RegBase;
1653      Addr.Base.Reg = ARM::SP;
1654      Addr.Offset = VA.getLocMemOffset();
1655
1656      if (!ARMEmitStore(ArgVT, Arg, Addr)) return false;
1657    }
1658  }
1659  return true;
1660}
1661
1662bool ARMFastISel::FinishCall(MVT RetVT, SmallVectorImpl<unsigned> &UsedRegs,
1663                             const Instruction *I, CallingConv::ID CC,
1664                             unsigned &NumBytes) {
1665  // Issue CALLSEQ_END
1666  unsigned AdjStackUp = TII.getCallFrameDestroyOpcode();
1667  AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
1668                          TII.get(AdjStackUp))
1669                  .addImm(NumBytes).addImm(0));
1670
1671  // Now the return value.
1672  if (RetVT != MVT::isVoid) {
1673    SmallVector<CCValAssign, 16> RVLocs;
1674    CCState CCInfo(CC, false, *FuncInfo.MF, TM, RVLocs, *Context);
1675    CCInfo.AnalyzeCallResult(RetVT, CCAssignFnForCall(CC, true));
1676
1677    // Copy all of the result registers out of their specified physreg.
1678    if (RVLocs.size() == 2 && RetVT == MVT::f64) {
1679      // For this move we copy into two registers and then move into the
1680      // double fp reg we want.
1681      EVT DestVT = RVLocs[0].getValVT();
1682      TargetRegisterClass* DstRC = TLI.getRegClassFor(DestVT);
1683      unsigned ResultReg = createResultReg(DstRC);
1684      AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
1685                              TII.get(ARM::VMOVDRR), ResultReg)
1686                      .addReg(RVLocs[0].getLocReg())
1687                      .addReg(RVLocs[1].getLocReg()));
1688
1689      UsedRegs.push_back(RVLocs[0].getLocReg());
1690      UsedRegs.push_back(RVLocs[1].getLocReg());
1691
1692      // Finally update the result.
1693      UpdateValueMap(I, ResultReg);
1694    } else {
1695      assert(RVLocs.size() == 1 &&"Can't handle non-double multi-reg retvals!");
1696      EVT CopyVT = RVLocs[0].getValVT();
1697      TargetRegisterClass* DstRC = TLI.getRegClassFor(CopyVT);
1698
1699      unsigned ResultReg = createResultReg(DstRC);
1700      BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(TargetOpcode::COPY),
1701              ResultReg).addReg(RVLocs[0].getLocReg());
1702      UsedRegs.push_back(RVLocs[0].getLocReg());
1703
1704      // Finally update the result.
1705      UpdateValueMap(I, ResultReg);
1706    }
1707  }
1708
1709  return true;
1710}
1711
1712bool ARMFastISel::SelectRet(const Instruction *I) {
1713  const ReturnInst *Ret = cast<ReturnInst>(I);
1714  const Function &F = *I->getParent()->getParent();
1715
1716  if (!FuncInfo.CanLowerReturn)
1717    return false;
1718
1719  if (F.isVarArg())
1720    return false;
1721
1722  CallingConv::ID CC = F.getCallingConv();
1723  if (Ret->getNumOperands() > 0) {
1724    SmallVector<ISD::OutputArg, 4> Outs;
1725    GetReturnInfo(F.getReturnType(), F.getAttributes().getRetAttributes(),
1726                  Outs, TLI);
1727
1728    // Analyze operands of the call, assigning locations to each operand.
1729    SmallVector<CCValAssign, 16> ValLocs;
1730    CCState CCInfo(CC, F.isVarArg(), *FuncInfo.MF, TM, ValLocs,I->getContext());
1731    CCInfo.AnalyzeReturn(Outs, CCAssignFnForCall(CC, true /* is Ret */));
1732
1733    const Value *RV = Ret->getOperand(0);
1734    unsigned Reg = getRegForValue(RV);
1735    if (Reg == 0)
1736      return false;
1737
1738    // Only handle a single return value for now.
1739    if (ValLocs.size() != 1)
1740      return false;
1741
1742    CCValAssign &VA = ValLocs[0];
1743
1744    // Don't bother handling odd stuff for now.
1745    // FIXME: Should be able to handle i1, i8, and/or i16 return types.
1746    if (VA.getLocInfo() != CCValAssign::Full)
1747      return false;
1748    // Only handle register returns for now.
1749    if (!VA.isRegLoc())
1750      return false;
1751    // TODO: For now, don't try to handle cases where getLocInfo()
1752    // says Full but the types don't match.
1753    if (TLI.getValueType(RV->getType()) != VA.getValVT())
1754      return false;
1755
1756    // Make the copy.
1757    unsigned SrcReg = Reg + VA.getValNo();
1758    unsigned DstReg = VA.getLocReg();
1759    const TargetRegisterClass* SrcRC = MRI.getRegClass(SrcReg);
1760    // Avoid a cross-class copy. This is very unlikely.
1761    if (!SrcRC->contains(DstReg))
1762      return false;
1763    BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(TargetOpcode::COPY),
1764            DstReg).addReg(SrcReg);
1765
1766    // Mark the register as live out of the function.
1767    MRI.addLiveOut(VA.getLocReg());
1768  }
1769
1770  unsigned RetOpc = isThumb ? ARM::tBX_RET : ARM::BX_RET;
1771  AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
1772                          TII.get(RetOpc)));
1773  return true;
1774}
1775
1776unsigned ARMFastISel::ARMSelectCallOp(const GlobalValue *GV) {
1777
1778  // Darwin needs the r9 versions of the opcodes.
1779  bool isDarwin = Subtarget->isTargetDarwin();
1780  if (isThumb) {
1781    return isDarwin ? ARM::tBLr9 : ARM::tBL;
1782  } else  {
1783    return isDarwin ? ARM::BLr9 : ARM::BL;
1784  }
1785}
1786
1787// A quick function that will emit a call for a named libcall in F with the
1788// vector of passed arguments for the Instruction in I. We can assume that we
1789// can emit a call for any libcall we can produce. This is an abridged version
1790// of the full call infrastructure since we won't need to worry about things
1791// like computed function pointers or strange arguments at call sites.
1792// TODO: Try to unify this and the normal call bits for ARM, then try to unify
1793// with X86.
1794bool ARMFastISel::ARMEmitLibcall(const Instruction *I, RTLIB::Libcall Call) {
1795  CallingConv::ID CC = TLI.getLibcallCallingConv(Call);
1796
1797  // Handle *simple* calls for now.
1798  Type *RetTy = I->getType();
1799  MVT RetVT;
1800  if (RetTy->isVoidTy())
1801    RetVT = MVT::isVoid;
1802  else if (!isTypeLegal(RetTy, RetVT))
1803    return false;
1804
1805  // TODO: For now if we have long calls specified we don't handle the call.
1806  if (EnableARMLongCalls) return false;
1807
1808  // Set up the argument vectors.
1809  SmallVector<Value*, 8> Args;
1810  SmallVector<unsigned, 8> ArgRegs;
1811  SmallVector<MVT, 8> ArgVTs;
1812  SmallVector<ISD::ArgFlagsTy, 8> ArgFlags;
1813  Args.reserve(I->getNumOperands());
1814  ArgRegs.reserve(I->getNumOperands());
1815  ArgVTs.reserve(I->getNumOperands());
1816  ArgFlags.reserve(I->getNumOperands());
1817  for (unsigned i = 0; i < I->getNumOperands(); ++i) {
1818    Value *Op = I->getOperand(i);
1819    unsigned Arg = getRegForValue(Op);
1820    if (Arg == 0) return false;
1821
1822    Type *ArgTy = Op->getType();
1823    MVT ArgVT;
1824    if (!isTypeLegal(ArgTy, ArgVT)) return false;
1825
1826    ISD::ArgFlagsTy Flags;
1827    unsigned OriginalAlignment = TD.getABITypeAlignment(ArgTy);
1828    Flags.setOrigAlign(OriginalAlignment);
1829
1830    Args.push_back(Op);
1831    ArgRegs.push_back(Arg);
1832    ArgVTs.push_back(ArgVT);
1833    ArgFlags.push_back(Flags);
1834  }
1835
1836  // Handle the arguments now that we've gotten them.
1837  SmallVector<unsigned, 4> RegArgs;
1838  unsigned NumBytes;
1839  if (!ProcessCallArgs(Args, ArgRegs, ArgVTs, ArgFlags, RegArgs, CC, NumBytes))
1840    return false;
1841
1842  // Issue the call, BLr9 for darwin, BL otherwise.
1843  // TODO: Turn this into the table of arm call ops.
1844  MachineInstrBuilder MIB;
1845  unsigned CallOpc = ARMSelectCallOp(NULL);
1846  if(isThumb)
1847    // Explicitly adding the predicate here.
1848    MIB = AddDefaultPred(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
1849                         TII.get(CallOpc)))
1850                         .addExternalSymbol(TLI.getLibcallName(Call));
1851  else
1852    // Explicitly adding the predicate here.
1853    MIB = AddDefaultPred(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
1854                         TII.get(CallOpc))
1855          .addExternalSymbol(TLI.getLibcallName(Call)));
1856
1857  // Add implicit physical register uses to the call.
1858  for (unsigned i = 0, e = RegArgs.size(); i != e; ++i)
1859    MIB.addReg(RegArgs[i]);
1860
1861  // Finish off the call including any return values.
1862  SmallVector<unsigned, 4> UsedRegs;
1863  if (!FinishCall(RetVT, UsedRegs, I, CC, NumBytes)) return false;
1864
1865  // Set all unused physreg defs as dead.
1866  static_cast<MachineInstr *>(MIB)->setPhysRegsDeadExcept(UsedRegs, TRI);
1867
1868  return true;
1869}
1870
1871bool ARMFastISel::SelectCall(const Instruction *I) {
1872  const CallInst *CI = cast<CallInst>(I);
1873  const Value *Callee = CI->getCalledValue();
1874
1875  // Can't handle inline asm or worry about intrinsics yet.
1876  if (isa<InlineAsm>(Callee) || isa<IntrinsicInst>(CI)) return false;
1877
1878  // Only handle global variable Callees.
1879  const GlobalValue *GV = dyn_cast<GlobalValue>(Callee);
1880  if (!GV)
1881    return false;
1882
1883  // Check the calling convention.
1884  ImmutableCallSite CS(CI);
1885  CallingConv::ID CC = CS.getCallingConv();
1886
1887  // TODO: Avoid some calling conventions?
1888
1889  // Let SDISel handle vararg functions.
1890  PointerType *PT = cast<PointerType>(CS.getCalledValue()->getType());
1891  FunctionType *FTy = cast<FunctionType>(PT->getElementType());
1892  if (FTy->isVarArg())
1893    return false;
1894
1895  // Handle *simple* calls for now.
1896  Type *RetTy = I->getType();
1897  MVT RetVT;
1898  if (RetTy->isVoidTy())
1899    RetVT = MVT::isVoid;
1900  else if (!isTypeLegal(RetTy, RetVT))
1901    return false;
1902
1903  // TODO: For now if we have long calls specified we don't handle the call.
1904  if (EnableARMLongCalls) return false;
1905
1906  // Set up the argument vectors.
1907  SmallVector<Value*, 8> Args;
1908  SmallVector<unsigned, 8> ArgRegs;
1909  SmallVector<MVT, 8> ArgVTs;
1910  SmallVector<ISD::ArgFlagsTy, 8> ArgFlags;
1911  Args.reserve(CS.arg_size());
1912  ArgRegs.reserve(CS.arg_size());
1913  ArgVTs.reserve(CS.arg_size());
1914  ArgFlags.reserve(CS.arg_size());
1915  for (ImmutableCallSite::arg_iterator i = CS.arg_begin(), e = CS.arg_end();
1916       i != e; ++i) {
1917    unsigned Arg = getRegForValue(*i);
1918
1919    if (Arg == 0)
1920      return false;
1921    ISD::ArgFlagsTy Flags;
1922    unsigned AttrInd = i - CS.arg_begin() + 1;
1923    if (CS.paramHasAttr(AttrInd, Attribute::SExt))
1924      Flags.setSExt();
1925    if (CS.paramHasAttr(AttrInd, Attribute::ZExt))
1926      Flags.setZExt();
1927
1928         // FIXME: Only handle *easy* calls for now.
1929    if (CS.paramHasAttr(AttrInd, Attribute::InReg) ||
1930        CS.paramHasAttr(AttrInd, Attribute::StructRet) ||
1931        CS.paramHasAttr(AttrInd, Attribute::Nest) ||
1932        CS.paramHasAttr(AttrInd, Attribute::ByVal))
1933      return false;
1934
1935    Type *ArgTy = (*i)->getType();
1936    MVT ArgVT;
1937    // FIXME: Should be able to handle i1, i8, and/or i16 parameters.
1938    if (!isTypeLegal(ArgTy, ArgVT))
1939      return false;
1940    unsigned OriginalAlignment = TD.getABITypeAlignment(ArgTy);
1941    Flags.setOrigAlign(OriginalAlignment);
1942
1943    Args.push_back(*i);
1944    ArgRegs.push_back(Arg);
1945    ArgVTs.push_back(ArgVT);
1946    ArgFlags.push_back(Flags);
1947  }
1948
1949  // Handle the arguments now that we've gotten them.
1950  SmallVector<unsigned, 4> RegArgs;
1951  unsigned NumBytes;
1952  if (!ProcessCallArgs(Args, ArgRegs, ArgVTs, ArgFlags, RegArgs, CC, NumBytes))
1953    return false;
1954
1955  // Issue the call, BLr9 for darwin, BL otherwise.
1956  // TODO: Turn this into the table of arm call ops.
1957  MachineInstrBuilder MIB;
1958  unsigned CallOpc = ARMSelectCallOp(GV);
1959  // Explicitly adding the predicate here.
1960  if(isThumb)
1961    // Explicitly adding the predicate here.
1962    MIB = AddDefaultPred(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
1963                         TII.get(CallOpc)))
1964          .addGlobalAddress(GV, 0, 0);
1965  else
1966    // Explicitly adding the predicate here.
1967    MIB = AddDefaultPred(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
1968                         TII.get(CallOpc))
1969          .addGlobalAddress(GV, 0, 0));
1970
1971  // Add implicit physical register uses to the call.
1972  for (unsigned i = 0, e = RegArgs.size(); i != e; ++i)
1973    MIB.addReg(RegArgs[i]);
1974
1975  // Finish off the call including any return values.
1976  SmallVector<unsigned, 4> UsedRegs;
1977  if (!FinishCall(RetVT, UsedRegs, I, CC, NumBytes)) return false;
1978
1979  // Set all unused physreg defs as dead.
1980  static_cast<MachineInstr *>(MIB)->setPhysRegsDeadExcept(UsedRegs, TRI);
1981
1982  return true;
1983}
1984
1985bool ARMFastISel::SelectTrunc(const Instruction *I) {
1986  // The high bits for a type smaller than the register size are assumed to be
1987  // undefined.
1988  Value *Op = I->getOperand(0);
1989
1990  EVT SrcVT, DestVT;
1991  SrcVT = TLI.getValueType(Op->getType(), true);
1992  DestVT = TLI.getValueType(I->getType(), true);
1993
1994  if (SrcVT != MVT::i32 && SrcVT != MVT::i16 && SrcVT != MVT::i8)
1995    return false;
1996  if (DestVT != MVT::i16 && DestVT != MVT::i8 && DestVT != MVT::i1)
1997    return false;
1998
1999  unsigned SrcReg = getRegForValue(Op);
2000  if (!SrcReg) return false;
2001
2002  // Because the high bits are undefined, a truncate doesn't generate
2003  // any code.
2004  UpdateValueMap(I, SrcReg);
2005  return true;
2006}
2007
2008unsigned ARMFastISel::ARMEmitIntExt(EVT SrcVT, unsigned SrcReg, EVT DestVT,
2009                                    bool isZExt) {
2010  if (DestVT != MVT::i32 && DestVT != MVT::i16 && DestVT != MVT::i8)
2011    return 0;
2012
2013  unsigned Opc;
2014  bool isBoolZext = false;
2015  if (!SrcVT.isSimple()) return 0;
2016  switch (SrcVT.getSimpleVT().SimpleTy) {
2017  default: return 0;
2018  case MVT::i16:
2019    if (!Subtarget->hasV6Ops()) return 0;
2020    if (isZExt)
2021      Opc = isThumb ? ARM::t2UXTH : ARM::UXTH;
2022    else
2023      Opc = isThumb ? ARM::t2SXTH : ARM::SXTH;
2024    break;
2025  case MVT::i8:
2026    if (!Subtarget->hasV6Ops()) return 0;
2027    if (isZExt)
2028      Opc = isThumb ? ARM::t2UXTB : ARM::UXTB;
2029    else
2030      Opc = isThumb ? ARM::t2SXTB : ARM::SXTB;
2031    break;
2032  case MVT::i1:
2033    if (isZExt) {
2034      Opc = isThumb ? ARM::t2ANDri : ARM::ANDri;
2035      isBoolZext = true;
2036      break;
2037    }
2038    return 0;
2039  }
2040
2041  unsigned ResultReg = createResultReg(TLI.getRegClassFor(MVT::i32));
2042  MachineInstrBuilder MIB;
2043  MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(Opc), ResultReg)
2044        .addReg(SrcReg);
2045  if (isBoolZext)
2046    MIB.addImm(1);
2047  else
2048    MIB.addImm(0);
2049  AddOptionalDefs(MIB);
2050  return ResultReg;
2051}
2052
2053bool ARMFastISel::SelectIntExt(const Instruction *I) {
2054  // On ARM, in general, integer casts don't involve legal types; this code
2055  // handles promotable integers.
2056  // FIXME: We could save an instruction in many cases by special-casing
2057  // load instructions.
2058  Type *DestTy = I->getType();
2059  Value *Src = I->getOperand(0);
2060  Type *SrcTy = Src->getType();
2061
2062  EVT SrcVT, DestVT;
2063  SrcVT = TLI.getValueType(SrcTy, true);
2064  DestVT = TLI.getValueType(DestTy, true);
2065
2066  bool isZExt = isa<ZExtInst>(I);
2067  unsigned SrcReg = getRegForValue(Src);
2068  if (!SrcReg) return false;
2069
2070  unsigned ResultReg = ARMEmitIntExt(SrcVT, SrcReg, DestVT, isZExt);
2071  if (ResultReg == 0) return false;
2072  UpdateValueMap(I, ResultReg);
2073  return true;
2074}
2075
2076// TODO: SoftFP support.
2077bool ARMFastISel::TargetSelectInstruction(const Instruction *I) {
2078
2079  switch (I->getOpcode()) {
2080    case Instruction::Load:
2081      return SelectLoad(I);
2082    case Instruction::Store:
2083      return SelectStore(I);
2084    case Instruction::Br:
2085      return SelectBranch(I);
2086    case Instruction::ICmp:
2087    case Instruction::FCmp:
2088      return SelectCmp(I);
2089    case Instruction::FPExt:
2090      return SelectFPExt(I);
2091    case Instruction::FPTrunc:
2092      return SelectFPTrunc(I);
2093    case Instruction::SIToFP:
2094      return SelectSIToFP(I);
2095    case Instruction::FPToSI:
2096      return SelectFPToSI(I);
2097    case Instruction::FAdd:
2098      return SelectBinaryOp(I, ISD::FADD);
2099    case Instruction::FSub:
2100      return SelectBinaryOp(I, ISD::FSUB);
2101    case Instruction::FMul:
2102      return SelectBinaryOp(I, ISD::FMUL);
2103    case Instruction::SDiv:
2104      return SelectSDiv(I);
2105    case Instruction::SRem:
2106      return SelectSRem(I);
2107    case Instruction::Call:
2108      return SelectCall(I);
2109    case Instruction::Select:
2110      return SelectSelect(I);
2111    case Instruction::Ret:
2112      return SelectRet(I);
2113    case Instruction::Trunc:
2114      return SelectTrunc(I);
2115    case Instruction::ZExt:
2116    case Instruction::SExt:
2117      return SelectIntExt(I);
2118    default: break;
2119  }
2120  return false;
2121}
2122
2123namespace llvm {
2124  llvm::FastISel *ARM::createFastISel(FunctionLoweringInfo &funcInfo) {
2125    // Completely untested on non-darwin.
2126    const TargetMachine &TM = funcInfo.MF->getTarget();
2127
2128    // Darwin and thumb1 only for now.
2129    const ARMSubtarget *Subtarget = &TM.getSubtarget<ARMSubtarget>();
2130    if (Subtarget->isTargetDarwin() && !Subtarget->isThumb1Only() &&
2131        !DisableARMFastISel)
2132      return new ARMFastISel(funcInfo);
2133    return 0;
2134  }
2135}
2136