ARMFastISel.cpp revision e3dad19e0de5c639886055c09da1f4faaa8556f9 
1//===-- ARMFastISel.cpp - ARM FastISel implementation ---------------------===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file defines the ARM-specific support for the FastISel class. Some
11// of the target-specific code is generated by tablegen in the file
12// ARMGenFastISel.inc, which is #included here.
13//
14//===----------------------------------------------------------------------===//
15
16#include "ARM.h"
17#include "ARMBaseInstrInfo.h"
18#include "ARMCallingConv.h"
19#include "ARMConstantPoolValue.h"
20#include "ARMSubtarget.h"
21#include "ARMTargetMachine.h"
22#include "MCTargetDesc/ARMAddressingModes.h"
23#include "llvm/ADT/STLExtras.h"
24#include "llvm/CodeGen/Analysis.h"
25#include "llvm/CodeGen/FastISel.h"
26#include "llvm/CodeGen/FunctionLoweringInfo.h"
27#include "llvm/CodeGen/MachineConstantPool.h"
28#include "llvm/CodeGen/MachineFrameInfo.h"
29#include "llvm/CodeGen/MachineInstrBuilder.h"
30#include "llvm/CodeGen/MachineMemOperand.h"
31#include "llvm/CodeGen/MachineModuleInfo.h"
32#include "llvm/CodeGen/MachineRegisterInfo.h"
33#include "llvm/IR/CallingConv.h"
34#include "llvm/IR/DataLayout.h"
35#include "llvm/IR/DerivedTypes.h"
36#include "llvm/IR/GlobalVariable.h"
37#include "llvm/IR/Instructions.h"
38#include "llvm/IR/IntrinsicInst.h"
39#include "llvm/IR/Module.h"
40#include "llvm/IR/Operator.h"
41#include "llvm/Support/CallSite.h"
42#include "llvm/Support/CommandLine.h"
43#include "llvm/Support/ErrorHandling.h"
44#include "llvm/Support/GetElementPtrTypeIterator.h"
45#include "llvm/Target/TargetInstrInfo.h"
46#include "llvm/Target/TargetLowering.h"
47#include "llvm/Target/TargetMachine.h"
48#include "llvm/Target/TargetOptions.h"
49using namespace llvm;
50
51extern cl::opt<bool> EnableARMLongCalls;
52
53namespace {
54
55  // All possible address modes, plus some.
56  typedef struct Address {
57    enum {
58      RegBase,
59      FrameIndexBase
60    } BaseType;
61
62    union {
63      unsigned Reg;
64      int FI;
65    } Base;
66
67    int Offset;
68
69    // Innocuous defaults for our address.
70    Address()
71     : BaseType(RegBase), Offset(0) {
72       Base.Reg = 0;
73     }
74  } Address;
75
76class ARMFastISel : public FastISel {
77
78  /// Subtarget - Keep a pointer to the ARMSubtarget around so that we can
79  /// make the right decision when generating code for different targets.
80  const ARMSubtarget *Subtarget;
81  const TargetMachine &TM;
82  const TargetInstrInfo &TII;
83  const TargetLowering &TLI;
84  ARMFunctionInfo *AFI;
85
86  // Convenience variables to avoid some queries.
87  bool isThumb2;
88  LLVMContext *Context;
89
90  public:
91    explicit ARMFastISel(FunctionLoweringInfo &funcInfo,
92                         const TargetLibraryInfo *libInfo)
93    : FastISel(funcInfo, libInfo),
94      TM(funcInfo.MF->getTarget()),
95      TII(*TM.getInstrInfo()),
96      TLI(*TM.getTargetLowering()) {
97      Subtarget = &TM.getSubtarget<ARMSubtarget>();
98      AFI = funcInfo.MF->getInfo<ARMFunctionInfo>();
99      isThumb2 = AFI->isThumbFunction();
100      Context = &funcInfo.Fn->getContext();
101    }
102
103    // Code from FastISel.cpp.
104  private:
105    unsigned FastEmitInst_(unsigned MachineInstOpcode,
106                           const TargetRegisterClass *RC);
107    unsigned FastEmitInst_r(unsigned MachineInstOpcode,
108                            const TargetRegisterClass *RC,
109                            unsigned Op0, bool Op0IsKill);
110    unsigned FastEmitInst_rr(unsigned MachineInstOpcode,
111                             const TargetRegisterClass *RC,
112                             unsigned Op0, bool Op0IsKill,
113                             unsigned Op1, bool Op1IsKill);
114    unsigned FastEmitInst_rrr(unsigned MachineInstOpcode,
115                              const TargetRegisterClass *RC,
116                              unsigned Op0, bool Op0IsKill,
117                              unsigned Op1, bool Op1IsKill,
118                              unsigned Op2, bool Op2IsKill);
119    unsigned FastEmitInst_ri(unsigned MachineInstOpcode,
120                             const TargetRegisterClass *RC,
121                             unsigned Op0, bool Op0IsKill,
122                             uint64_t Imm);
123    unsigned FastEmitInst_rf(unsigned MachineInstOpcode,
124                             const TargetRegisterClass *RC,
125                             unsigned Op0, bool Op0IsKill,
126                             const ConstantFP *FPImm);
127    unsigned FastEmitInst_rri(unsigned MachineInstOpcode,
128                              const TargetRegisterClass *RC,
129                              unsigned Op0, bool Op0IsKill,
130                              unsigned Op1, bool Op1IsKill,
131                              uint64_t Imm);
132    unsigned FastEmitInst_i(unsigned MachineInstOpcode,
133                            const TargetRegisterClass *RC,
134                            uint64_t Imm);
135    unsigned FastEmitInst_ii(unsigned MachineInstOpcode,
136                             const TargetRegisterClass *RC,
137                             uint64_t Imm1, uint64_t Imm2);
138
139    unsigned FastEmitInst_extractsubreg(MVT RetVT,
140                                        unsigned Op0, bool Op0IsKill,
141                                        uint32_t Idx);
142
143    // Backend specific FastISel code.
144  private:
145    virtual bool TargetSelectInstruction(const Instruction *I);
146    virtual unsigned TargetMaterializeConstant(const Constant *C);
147    virtual unsigned TargetMaterializeAlloca(const AllocaInst *AI);
148    virtual bool tryToFoldLoadIntoMI(MachineInstr *MI, unsigned OpNo,
149                                     const LoadInst *LI);
150    virtual bool FastLowerArguments();
151  private:
152  #include "ARMGenFastISel.inc"
153
154    // Instruction selection routines.
155  private:
156    bool SelectLoad(const Instruction *I);
157    bool SelectStore(const Instruction *I);
158    bool SelectBranch(const Instruction *I);
159    bool SelectIndirectBr(const Instruction *I);
160    bool SelectCmp(const Instruction *I);
161    bool SelectFPExt(const Instruction *I);
162    bool SelectFPTrunc(const Instruction *I);
163    bool SelectBinaryIntOp(const Instruction *I, unsigned ISDOpcode);
164    bool SelectBinaryFPOp(const Instruction *I, unsigned ISDOpcode);
165    bool SelectIToFP(const Instruction *I, bool isSigned);
166    bool SelectFPToI(const Instruction *I, bool isSigned);
167    bool SelectDiv(const Instruction *I, bool isSigned);
168    bool SelectRem(const Instruction *I, bool isSigned);
169    bool SelectCall(const Instruction *I, const char *IntrMemName);
170    bool SelectIntrinsicCall(const IntrinsicInst &I);
171    bool SelectSelect(const Instruction *I);
172    bool SelectRet(const Instruction *I);
173    bool SelectTrunc(const Instruction *I);
174    bool SelectIntExt(const Instruction *I);
175    bool SelectShift(const Instruction *I, ARM_AM::ShiftOpc ShiftTy);
176
177    // Utility routines.
178  private:
179    unsigned constrainOperandRegClass(const MCInstrDesc &II, unsigned OpNum,
180                                      unsigned Op);
181    bool isTypeLegal(Type *Ty, MVT &VT);
182    bool isLoadTypeLegal(Type *Ty, MVT &VT);
183    bool ARMEmitCmp(const Value *Src1Value, const Value *Src2Value,
184                    bool isZExt);
185    bool ARMEmitLoad(MVT VT, unsigned &ResultReg, Address &Addr,
186                     unsigned Alignment = 0, bool isZExt = true,
187                     bool allocReg = true);
188    bool ARMEmitStore(MVT VT, unsigned SrcReg, Address &Addr,
189                      unsigned Alignment = 0);
190    bool ARMComputeAddress(const Value *Obj, Address &Addr);
191    void ARMSimplifyAddress(Address &Addr, MVT VT, bool useAM3);
192    bool ARMIsMemCpySmall(uint64_t Len);
193    bool ARMTryEmitSmallMemCpy(Address Dest, Address Src, uint64_t Len,
194                               unsigned Alignment);
195    unsigned ARMEmitIntExt(MVT SrcVT, unsigned SrcReg, MVT DestVT, bool isZExt);
196    unsigned ARMMaterializeFP(const ConstantFP *CFP, MVT VT);
197    unsigned ARMMaterializeInt(const Constant *C, MVT VT);
198    unsigned ARMMaterializeGV(const GlobalValue *GV, MVT VT);
199    unsigned ARMMoveToFPReg(MVT VT, unsigned SrcReg);
200    unsigned ARMMoveToIntReg(MVT VT, unsigned SrcReg);
201    unsigned ARMSelectCallOp(bool UseReg);
202    unsigned ARMLowerPICELF(const GlobalValue *GV, unsigned Align, MVT VT);
203
204    // Call handling routines.
205  private:
206    CCAssignFn *CCAssignFnForCall(CallingConv::ID CC,
207                                  bool Return,
208                                  bool isVarArg);
209    bool ProcessCallArgs(SmallVectorImpl<Value*> &Args,
210                         SmallVectorImpl<unsigned> &ArgRegs,
211                         SmallVectorImpl<MVT> &ArgVTs,
212                         SmallVectorImpl<ISD::ArgFlagsTy> &ArgFlags,
213                         SmallVectorImpl<unsigned> &RegArgs,
214                         CallingConv::ID CC,
215                         unsigned &NumBytes,
216                         bool isVarArg);
217    unsigned getLibcallReg(const Twine &Name);
218    bool FinishCall(MVT RetVT, SmallVectorImpl<unsigned> &UsedRegs,
219                    const Instruction *I, CallingConv::ID CC,
220                    unsigned &NumBytes, bool isVarArg);
221    bool ARMEmitLibcall(const Instruction *I, RTLIB::Libcall Call);
222
223    // OptionalDef handling routines.
224  private:
225    bool isARMNEONPred(const MachineInstr *MI);
226    bool DefinesOptionalPredicate(MachineInstr *MI, bool *CPSR);
227    const MachineInstrBuilder &AddOptionalDefs(const MachineInstrBuilder &MIB);
228    void AddLoadStoreOperands(MVT VT, Address &Addr,
229                              const MachineInstrBuilder &MIB,
230                              unsigned Flags, bool useAM3);
231};
232
233} // end anonymous namespace
234
235#include "ARMGenCallingConv.inc"
236
237// DefinesOptionalPredicate - This is different from DefinesPredicate in that
238// we don't care about implicit defs here, just places we'll need to add a
239// default CCReg argument. Sets CPSR if we're setting CPSR instead of CCR.
240bool ARMFastISel::DefinesOptionalPredicate(MachineInstr *MI, bool *CPSR) {
241  if (!MI->hasOptionalDef())
242    return false;
243
244  // Look to see if our OptionalDef is defining CPSR or CCR.
245  for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
246    const MachineOperand &MO = MI->getOperand(i);
247    if (!MO.isReg() || !MO.isDef()) continue;
248    if (MO.getReg() == ARM::CPSR)
249      *CPSR = true;
250  }
251  return true;
252}
253
254bool ARMFastISel::isARMNEONPred(const MachineInstr *MI) {
255  const MCInstrDesc &MCID = MI->getDesc();
256
257  // If we're a thumb2 or not NEON function we were handled via isPredicable.
258  if ((MCID.TSFlags & ARMII::DomainMask) != ARMII::DomainNEON ||
259       AFI->isThumb2Function())
260    return false;
261
262  for (unsigned i = 0, e = MCID.getNumOperands(); i != e; ++i)
263    if (MCID.OpInfo[i].isPredicate())
264      return true;
265
266  return false;
267}
268
269// If the machine is predicable go ahead and add the predicate operands, if
270// it needs default CC operands add those.
271// TODO: If we want to support thumb1 then we'll need to deal with optional
272// CPSR defs that need to be added before the remaining operands. See s_cc_out
273// for descriptions why.
274const MachineInstrBuilder &
275ARMFastISel::AddOptionalDefs(const MachineInstrBuilder &MIB) {
276  MachineInstr *MI = &*MIB;
277
278  // Do we use a predicate? or...
279  // Are we NEON in ARM mode and have a predicate operand? If so, I know
280  // we're not predicable but add it anyways.
281  if (TII.isPredicable(MI) || isARMNEONPred(MI))
282    AddDefaultPred(MIB);
283
284  // Do we optionally set a predicate?  Preds is size > 0 iff the predicate
285  // defines CPSR. All other OptionalDefines in ARM are the CCR register.
286  bool CPSR = false;
287  if (DefinesOptionalPredicate(MI, &CPSR)) {
288    if (CPSR)
289      AddDefaultT1CC(MIB);
290    else
291      AddDefaultCC(MIB);
292  }
293  return MIB;
294}
295
296unsigned ARMFastISel::constrainOperandRegClass(const MCInstrDesc &II,
297                                               unsigned Op, unsigned OpNum) {
298  if (TargetRegisterInfo::isVirtualRegister(Op)) {
299    const TargetRegisterClass *RegClass =
300        TII.getRegClass(II, OpNum, &TRI, *FuncInfo.MF);
301    if (!MRI.constrainRegClass(Op, RegClass)) {
302      // If it's not legal to COPY between the register classes, something
303      // has gone very wrong before we got here.
304      unsigned NewOp = createResultReg(RegClass);
305      AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
306                              TII.get(TargetOpcode::COPY), NewOp).addReg(Op));
307      return NewOp;
308    }
309  }
310  return Op;
311}
312
313unsigned ARMFastISel::FastEmitInst_(unsigned MachineInstOpcode,
314                                    const TargetRegisterClass* RC) {
315  unsigned ResultReg = createResultReg(RC);
316  const MCInstrDesc &II = TII.get(MachineInstOpcode);
317
318  AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II, ResultReg));
319  return ResultReg;
320}
321
322unsigned ARMFastISel::FastEmitInst_r(unsigned MachineInstOpcode,
323                                     const TargetRegisterClass *RC,
324                                     unsigned Op0, bool Op0IsKill) {
325  unsigned ResultReg = createResultReg(RC);
326  const MCInstrDesc &II = TII.get(MachineInstOpcode);
327
328  // Make sure the input operand is sufficiently constrained to be legal
329  // for this instruction.
330  Op0 = constrainOperandRegClass(II, Op0, 1);
331  if (II.getNumDefs() >= 1) {
332    AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II, ResultReg)
333                   .addReg(Op0, Op0IsKill * RegState::Kill));
334  } else {
335    AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II)
336                   .addReg(Op0, Op0IsKill * RegState::Kill));
337    AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
338                   TII.get(TargetOpcode::COPY), ResultReg)
339                   .addReg(II.ImplicitDefs[0]));
340  }
341  return ResultReg;
342}
343
344unsigned ARMFastISel::FastEmitInst_rr(unsigned MachineInstOpcode,
345                                      const TargetRegisterClass *RC,
346                                      unsigned Op0, bool Op0IsKill,
347                                      unsigned Op1, bool Op1IsKill) {
348  unsigned ResultReg = createResultReg(RC);
349  const MCInstrDesc &II = TII.get(MachineInstOpcode);
350
351  // Make sure the input operands are sufficiently constrained to be legal
352  // for this instruction.
353  Op0 = constrainOperandRegClass(II, Op0, 1);
354  Op1 = constrainOperandRegClass(II, Op1, 2);
355
356  if (II.getNumDefs() >= 1) {
357    AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II, ResultReg)
358                   .addReg(Op0, Op0IsKill * RegState::Kill)
359                   .addReg(Op1, Op1IsKill * RegState::Kill));
360  } else {
361    AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II)
362                   .addReg(Op0, Op0IsKill * RegState::Kill)
363                   .addReg(Op1, Op1IsKill * RegState::Kill));
364    AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
365                           TII.get(TargetOpcode::COPY), ResultReg)
366                   .addReg(II.ImplicitDefs[0]));
367  }
368  return ResultReg;
369}
370
371unsigned ARMFastISel::FastEmitInst_rrr(unsigned MachineInstOpcode,
372                                       const TargetRegisterClass *RC,
373                                       unsigned Op0, bool Op0IsKill,
374                                       unsigned Op1, bool Op1IsKill,
375                                       unsigned Op2, bool Op2IsKill) {
376  unsigned ResultReg = createResultReg(RC);
377  const MCInstrDesc &II = TII.get(MachineInstOpcode);
378
379  // Make sure the input operands are sufficiently constrained to be legal
380  // for this instruction.
381  Op0 = constrainOperandRegClass(II, Op0, 1);
382  Op1 = constrainOperandRegClass(II, Op1, 2);
383  Op2 = constrainOperandRegClass(II, Op1, 3);
384
385  if (II.getNumDefs() >= 1) {
386    AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II, ResultReg)
387                   .addReg(Op0, Op0IsKill * RegState::Kill)
388                   .addReg(Op1, Op1IsKill * RegState::Kill)
389                   .addReg(Op2, Op2IsKill * RegState::Kill));
390  } else {
391    AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II)
392                   .addReg(Op0, Op0IsKill * RegState::Kill)
393                   .addReg(Op1, Op1IsKill * RegState::Kill)
394                   .addReg(Op2, Op2IsKill * RegState::Kill));
395    AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
396                           TII.get(TargetOpcode::COPY), ResultReg)
397                   .addReg(II.ImplicitDefs[0]));
398  }
399  return ResultReg;
400}
401
402unsigned ARMFastISel::FastEmitInst_ri(unsigned MachineInstOpcode,
403                                      const TargetRegisterClass *RC,
404                                      unsigned Op0, bool Op0IsKill,
405                                      uint64_t Imm) {
406  unsigned ResultReg = createResultReg(RC);
407  const MCInstrDesc &II = TII.get(MachineInstOpcode);
408
409  // Make sure the input operand is sufficiently constrained to be legal
410  // for this instruction.
411  Op0 = constrainOperandRegClass(II, Op0, 1);
412  if (II.getNumDefs() >= 1) {
413    AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II, ResultReg)
414                   .addReg(Op0, Op0IsKill * RegState::Kill)
415                   .addImm(Imm));
416  } else {
417    AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II)
418                   .addReg(Op0, Op0IsKill * RegState::Kill)
419                   .addImm(Imm));
420    AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
421                           TII.get(TargetOpcode::COPY), ResultReg)
422                   .addReg(II.ImplicitDefs[0]));
423  }
424  return ResultReg;
425}
426
427unsigned ARMFastISel::FastEmitInst_rf(unsigned MachineInstOpcode,
428                                      const TargetRegisterClass *RC,
429                                      unsigned Op0, bool Op0IsKill,
430                                      const ConstantFP *FPImm) {
431  unsigned ResultReg = createResultReg(RC);
432  const MCInstrDesc &II = TII.get(MachineInstOpcode);
433
434  // Make sure the input operand is sufficiently constrained to be legal
435  // for this instruction.
436  Op0 = constrainOperandRegClass(II, Op0, 1);
437  if (II.getNumDefs() >= 1) {
438    AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II, ResultReg)
439                   .addReg(Op0, Op0IsKill * RegState::Kill)
440                   .addFPImm(FPImm));
441  } else {
442    AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II)
443                   .addReg(Op0, Op0IsKill * RegState::Kill)
444                   .addFPImm(FPImm));
445    AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
446                           TII.get(TargetOpcode::COPY), ResultReg)
447                   .addReg(II.ImplicitDefs[0]));
448  }
449  return ResultReg;
450}
451
452unsigned ARMFastISel::FastEmitInst_rri(unsigned MachineInstOpcode,
453                                       const TargetRegisterClass *RC,
454                                       unsigned Op0, bool Op0IsKill,
455                                       unsigned Op1, bool Op1IsKill,
456                                       uint64_t Imm) {
457  unsigned ResultReg = createResultReg(RC);
458  const MCInstrDesc &II = TII.get(MachineInstOpcode);
459
460  // Make sure the input operands are sufficiently constrained to be legal
461  // for this instruction.
462  Op0 = constrainOperandRegClass(II, Op0, 1);
463  Op1 = constrainOperandRegClass(II, Op1, 2);
464  if (II.getNumDefs() >= 1) {
465    AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II, ResultReg)
466                   .addReg(Op0, Op0IsKill * RegState::Kill)
467                   .addReg(Op1, Op1IsKill * RegState::Kill)
468                   .addImm(Imm));
469  } else {
470    AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II)
471                   .addReg(Op0, Op0IsKill * RegState::Kill)
472                   .addReg(Op1, Op1IsKill * RegState::Kill)
473                   .addImm(Imm));
474    AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
475                           TII.get(TargetOpcode::COPY), ResultReg)
476                   .addReg(II.ImplicitDefs[0]));
477  }
478  return ResultReg;
479}
480
481unsigned ARMFastISel::FastEmitInst_i(unsigned MachineInstOpcode,
482                                     const TargetRegisterClass *RC,
483                                     uint64_t Imm) {
484  unsigned ResultReg = createResultReg(RC);
485  const MCInstrDesc &II = TII.get(MachineInstOpcode);
486
487  if (II.getNumDefs() >= 1) {
488    AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II, ResultReg)
489                   .addImm(Imm));
490  } else {
491    AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II)
492                   .addImm(Imm));
493    AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
494                           TII.get(TargetOpcode::COPY), ResultReg)
495                   .addReg(II.ImplicitDefs[0]));
496  }
497  return ResultReg;
498}
499
500unsigned ARMFastISel::FastEmitInst_ii(unsigned MachineInstOpcode,
501                                      const TargetRegisterClass *RC,
502                                      uint64_t Imm1, uint64_t Imm2) {
503  unsigned ResultReg = createResultReg(RC);
504  const MCInstrDesc &II = TII.get(MachineInstOpcode);
505
506  if (II.getNumDefs() >= 1) {
507    AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II, ResultReg)
508                    .addImm(Imm1).addImm(Imm2));
509  } else {
510    AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II)
511                    .addImm(Imm1).addImm(Imm2));
512    AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
513                            TII.get(TargetOpcode::COPY),
514                            ResultReg)
515                    .addReg(II.ImplicitDefs[0]));
516  }
517  return ResultReg;
518}
519
520unsigned ARMFastISel::FastEmitInst_extractsubreg(MVT RetVT,
521                                                 unsigned Op0, bool Op0IsKill,
522                                                 uint32_t Idx) {
523  unsigned ResultReg = createResultReg(TLI.getRegClassFor(RetVT));
524  assert(TargetRegisterInfo::isVirtualRegister(Op0) &&
525         "Cannot yet extract from physregs");
526
527  AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt,
528                          DL, TII.get(TargetOpcode::COPY), ResultReg)
529                  .addReg(Op0, getKillRegState(Op0IsKill), Idx));
530  return ResultReg;
531}
532
533// TODO: Don't worry about 64-bit now, but when this is fixed remove the
534// checks from the various callers.
535unsigned ARMFastISel::ARMMoveToFPReg(MVT VT, unsigned SrcReg) {
536  if (VT == MVT::f64) return 0;
537
538  unsigned MoveReg = createResultReg(TLI.getRegClassFor(VT));
539  AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
540                          TII.get(ARM::VMOVSR), MoveReg)
541                  .addReg(SrcReg));
542  return MoveReg;
543}
544
545unsigned ARMFastISel::ARMMoveToIntReg(MVT VT, unsigned SrcReg) {
546  if (VT == MVT::i64) return 0;
547
548  unsigned MoveReg = createResultReg(TLI.getRegClassFor(VT));
549  AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
550                          TII.get(ARM::VMOVRS), MoveReg)
551                  .addReg(SrcReg));
552  return MoveReg;
553}
554
555// For double width floating point we need to materialize two constants
556// (the high and the low) into integer registers then use a move to get
557// the combined constant into an FP reg.
558unsigned ARMFastISel::ARMMaterializeFP(const ConstantFP *CFP, MVT VT) {
559  const APFloat Val = CFP->getValueAPF();
560  bool is64bit = VT == MVT::f64;
561
562  // This checks to see if we can use VFP3 instructions to materialize
563  // a constant, otherwise we have to go through the constant pool.
564  if (TLI.isFPImmLegal(Val, VT)) {
565    int Imm;
566    unsigned Opc;
567    if (is64bit) {
568      Imm = ARM_AM::getFP64Imm(Val);
569      Opc = ARM::FCONSTD;
570    } else {
571      Imm = ARM_AM::getFP32Imm(Val);
572      Opc = ARM::FCONSTS;
573    }
574    unsigned DestReg = createResultReg(TLI.getRegClassFor(VT));
575    AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(Opc),
576                            DestReg)
577                    .addImm(Imm));
578    return DestReg;
579  }
580
581  // Require VFP2 for loading fp constants.
582  if (!Subtarget->hasVFP2()) return false;
583
584  // MachineConstantPool wants an explicit alignment.
585  unsigned Align = TD.getPrefTypeAlignment(CFP->getType());
586  if (Align == 0) {
587    // TODO: Figure out if this is correct.
588    Align = TD.getTypeAllocSize(CFP->getType());
589  }
590  unsigned Idx = MCP.getConstantPoolIndex(cast<Constant>(CFP), Align);
591  unsigned DestReg = createResultReg(TLI.getRegClassFor(VT));
592  unsigned Opc = is64bit ? ARM::VLDRD : ARM::VLDRS;
593
594  // The extra reg is for addrmode5.
595  AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(Opc),
596                          DestReg)
597                  .addConstantPoolIndex(Idx)
598                  .addReg(0));
599  return DestReg;
600}
601
602unsigned ARMFastISel::ARMMaterializeInt(const Constant *C, MVT VT) {
603
604  if (VT != MVT::i32 && VT != MVT::i16 && VT != MVT::i8 && VT != MVT::i1)
605    return false;
606
607  // If we can do this in a single instruction without a constant pool entry
608  // do so now.
609  const ConstantInt *CI = cast<ConstantInt>(C);
610  if (Subtarget->hasV6T2Ops() && isUInt<16>(CI->getZExtValue())) {
611    unsigned Opc = isThumb2 ? ARM::t2MOVi16 : ARM::MOVi16;
612    const TargetRegisterClass *RC = isThumb2 ? &ARM::rGPRRegClass :
613      &ARM::GPRRegClass;
614    unsigned ImmReg = createResultReg(RC);
615    AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
616                            TII.get(Opc), ImmReg)
617                    .addImm(CI->getZExtValue()));
618    return ImmReg;
619  }
620
621  // Use MVN to emit negative constants.
622  if (VT == MVT::i32 && Subtarget->hasV6T2Ops() && CI->isNegative()) {
623    unsigned Imm = (unsigned)~(CI->getSExtValue());
624    bool UseImm = isThumb2 ? (ARM_AM::getT2SOImmVal(Imm) != -1) :
625      (ARM_AM::getSOImmVal(Imm) != -1);
626    if (UseImm) {
627      unsigned Opc = isThumb2 ? ARM::t2MVNi : ARM::MVNi;
628      unsigned ImmReg = createResultReg(TLI.getRegClassFor(MVT::i32));
629      AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
630                              TII.get(Opc), ImmReg)
631                      .addImm(Imm));
632      return ImmReg;
633    }
634  }
635
636  // Load from constant pool.  For now 32-bit only.
637  if (VT != MVT::i32)
638    return false;
639
640  unsigned DestReg = createResultReg(TLI.getRegClassFor(VT));
641
642  // MachineConstantPool wants an explicit alignment.
643  unsigned Align = TD.getPrefTypeAlignment(C->getType());
644  if (Align == 0) {
645    // TODO: Figure out if this is correct.
646    Align = TD.getTypeAllocSize(C->getType());
647  }
648  unsigned Idx = MCP.getConstantPoolIndex(C, Align);
649
650  if (isThumb2)
651    AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
652                            TII.get(ARM::t2LDRpci), DestReg)
653                    .addConstantPoolIndex(Idx));
654  else
655    // The extra immediate is for addrmode2.
656    DestReg = constrainOperandRegClass(TII.get(ARM::LDRcp), DestReg, 0);
657    AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
658                            TII.get(ARM::LDRcp), DestReg)
659                    .addConstantPoolIndex(Idx)
660                    .addImm(0));
661
662  return DestReg;
663}
664
665unsigned ARMFastISel::ARMMaterializeGV(const GlobalValue *GV, MVT VT) {
666  // For now 32-bit only.
667  if (VT != MVT::i32) return 0;
668
669  Reloc::Model RelocM = TM.getRelocationModel();
670  bool IsIndirect = Subtarget->GVIsIndirectSymbol(GV, RelocM);
671  const TargetRegisterClass *RC = isThumb2 ?
672    (const TargetRegisterClass*)&ARM::rGPRRegClass :
673    (const TargetRegisterClass*)&ARM::GPRRegClass;
674  unsigned DestReg = createResultReg(RC);
675
676  // FastISel TLS support on non-Darwin is broken, punt to SelectionDAG.
677  const GlobalVariable *GVar = dyn_cast<GlobalVariable>(GV);
678  bool IsThreadLocal = GVar && GVar->isThreadLocal();
679  if (!Subtarget->isTargetDarwin() && IsThreadLocal) return 0;
680
681  // Use movw+movt when possible, it avoids constant pool entries.
682  // Darwin targets don't support movt with Reloc::Static, see
683  // ARMTargetLowering::LowerGlobalAddressDarwin.  Other targets only support
684  // static movt relocations.
685  if (Subtarget->useMovt() &&
686      Subtarget->isTargetDarwin() == (RelocM != Reloc::Static)) {
687    unsigned Opc;
688    switch (RelocM) {
689    case Reloc::PIC_:
690      Opc = isThumb2 ? ARM::t2MOV_ga_pcrel : ARM::MOV_ga_pcrel;
691      break;
692    case Reloc::DynamicNoPIC:
693      Opc = isThumb2 ? ARM::t2MOV_ga_dyn : ARM::MOV_ga_dyn;
694      break;
695    default:
696      Opc = isThumb2 ? ARM::t2MOVi32imm : ARM::MOVi32imm;
697      break;
698    }
699    AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(Opc),
700                            DestReg).addGlobalAddress(GV));
701  } else {
702    // MachineConstantPool wants an explicit alignment.
703    unsigned Align = TD.getPrefTypeAlignment(GV->getType());
704    if (Align == 0) {
705      // TODO: Figure out if this is correct.
706      Align = TD.getTypeAllocSize(GV->getType());
707    }
708
709    if (Subtarget->isTargetELF() && RelocM == Reloc::PIC_)
710      return ARMLowerPICELF(GV, Align, VT);
711
712    // Grab index.
713    unsigned PCAdj = (RelocM != Reloc::PIC_) ? 0 :
714      (Subtarget->isThumb() ? 4 : 8);
715    unsigned Id = AFI->createPICLabelUId();
716    ARMConstantPoolValue *CPV = ARMConstantPoolConstant::Create(GV, Id,
717                                                                ARMCP::CPValue,
718                                                                PCAdj);
719    unsigned Idx = MCP.getConstantPoolIndex(CPV, Align);
720
721    // Load value.
722    MachineInstrBuilder MIB;
723    if (isThumb2) {
724      unsigned Opc = (RelocM!=Reloc::PIC_) ? ARM::t2LDRpci : ARM::t2LDRpci_pic;
725      MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(Opc), DestReg)
726        .addConstantPoolIndex(Idx);
727      if (RelocM == Reloc::PIC_)
728        MIB.addImm(Id);
729      AddOptionalDefs(MIB);
730    } else {
731      // The extra immediate is for addrmode2.
732      DestReg = constrainOperandRegClass(TII.get(ARM::LDRcp), DestReg, 0);
733      MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(ARM::LDRcp),
734                    DestReg)
735        .addConstantPoolIndex(Idx)
736        .addImm(0);
737      AddOptionalDefs(MIB);
738
739      if (RelocM == Reloc::PIC_) {
740        unsigned Opc = IsIndirect ? ARM::PICLDR : ARM::PICADD;
741        unsigned NewDestReg = createResultReg(TLI.getRegClassFor(VT));
742
743        MachineInstrBuilder MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt,
744                                          DL, TII.get(Opc), NewDestReg)
745                                  .addReg(DestReg)
746                                  .addImm(Id);
747        AddOptionalDefs(MIB);
748        return NewDestReg;
749      }
750    }
751  }
752
753  if (IsIndirect) {
754    MachineInstrBuilder MIB;
755    unsigned NewDestReg = createResultReg(TLI.getRegClassFor(VT));
756    if (isThumb2)
757      MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
758                    TII.get(ARM::t2LDRi12), NewDestReg)
759            .addReg(DestReg)
760            .addImm(0);
761    else
762      MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(ARM::LDRi12),
763                    NewDestReg)
764            .addReg(DestReg)
765            .addImm(0);
766    DestReg = NewDestReg;
767    AddOptionalDefs(MIB);
768  }
769
770  return DestReg;
771}
772
773unsigned ARMFastISel::TargetMaterializeConstant(const Constant *C) {
774  EVT CEVT = TLI.getValueType(C->getType(), true);
775
776  // Only handle simple types.
777  if (!CEVT.isSimple()) return 0;
778  MVT VT = CEVT.getSimpleVT();
779
780  if (const ConstantFP *CFP = dyn_cast<ConstantFP>(C))
781    return ARMMaterializeFP(CFP, VT);
782  else if (const GlobalValue *GV = dyn_cast<GlobalValue>(C))
783    return ARMMaterializeGV(GV, VT);
784  else if (isa<ConstantInt>(C))
785    return ARMMaterializeInt(C, VT);
786
787  return 0;
788}
789
790// TODO: unsigned ARMFastISel::TargetMaterializeFloatZero(const ConstantFP *CF);
791
792unsigned ARMFastISel::TargetMaterializeAlloca(const AllocaInst *AI) {
793  // Don't handle dynamic allocas.
794  if (!FuncInfo.StaticAllocaMap.count(AI)) return 0;
795
796  MVT VT;
797  if (!isLoadTypeLegal(AI->getType(), VT)) return 0;
798
799  DenseMap<const AllocaInst*, int>::iterator SI =
800    FuncInfo.StaticAllocaMap.find(AI);
801
802  // This will get lowered later into the correct offsets and registers
803  // via rewriteXFrameIndex.
804  if (SI != FuncInfo.StaticAllocaMap.end()) {
805    const TargetRegisterClass* RC = TLI.getRegClassFor(VT);
806    unsigned ResultReg = createResultReg(RC);
807    unsigned Opc = isThumb2 ? ARM::t2ADDri : ARM::ADDri;
808    AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
809                            TII.get(Opc), ResultReg)
810                            .addFrameIndex(SI->second)
811                            .addImm(0));
812    return ResultReg;
813  }
814
815  return 0;
816}
817
818bool ARMFastISel::isTypeLegal(Type *Ty, MVT &VT) {
819  EVT evt = TLI.getValueType(Ty, true);
820
821  // Only handle simple types.
822  if (evt == MVT::Other || !evt.isSimple()) return false;
823  VT = evt.getSimpleVT();
824
825  // Handle all legal types, i.e. a register that will directly hold this
826  // value.
827  return TLI.isTypeLegal(VT);
828}
829
830bool ARMFastISel::isLoadTypeLegal(Type *Ty, MVT &VT) {
831  if (isTypeLegal(Ty, VT)) return true;
832
833  // If this is a type than can be sign or zero-extended to a basic operation
834  // go ahead and accept it now.
835  if (VT == MVT::i1 || VT == MVT::i8 || VT == MVT::i16)
836    return true;
837
838  return false;
839}
840
841// Computes the address to get to an object.
842bool ARMFastISel::ARMComputeAddress(const Value *Obj, Address &Addr) {
843  // Some boilerplate from the X86 FastISel.
844  const User *U = NULL;
845  unsigned Opcode = Instruction::UserOp1;
846  if (const Instruction *I = dyn_cast<Instruction>(Obj)) {
847    // Don't walk into other basic blocks unless the object is an alloca from
848    // another block, otherwise it may not have a virtual register assigned.
849    if (FuncInfo.StaticAllocaMap.count(static_cast<const AllocaInst *>(Obj)) ||
850        FuncInfo.MBBMap[I->getParent()] == FuncInfo.MBB) {
851      Opcode = I->getOpcode();
852      U = I;
853    }
854  } else if (const ConstantExpr *C = dyn_cast<ConstantExpr>(Obj)) {
855    Opcode = C->getOpcode();
856    U = C;
857  }
858
859  if (PointerType *Ty = dyn_cast<PointerType>(Obj->getType()))
860    if (Ty->getAddressSpace() > 255)
861      // Fast instruction selection doesn't support the special
862      // address spaces.
863      return false;
864
865  switch (Opcode) {
866    default:
867    break;
868    case Instruction::BitCast:
869      // Look through bitcasts.
870      return ARMComputeAddress(U->getOperand(0), Addr);
871    case Instruction::IntToPtr:
872      // Look past no-op inttoptrs.
873      if (TLI.getValueType(U->getOperand(0)->getType()) == TLI.getPointerTy())
874        return ARMComputeAddress(U->getOperand(0), Addr);
875      break;
876    case Instruction::PtrToInt:
877      // Look past no-op ptrtoints.
878      if (TLI.getValueType(U->getType()) == TLI.getPointerTy())
879        return ARMComputeAddress(U->getOperand(0), Addr);
880      break;
881    case Instruction::GetElementPtr: {
882      Address SavedAddr = Addr;
883      int TmpOffset = Addr.Offset;
884
885      // Iterate through the GEP folding the constants into offsets where
886      // we can.
887      gep_type_iterator GTI = gep_type_begin(U);
888      for (User::const_op_iterator i = U->op_begin() + 1, e = U->op_end();
889           i != e; ++i, ++GTI) {
890        const Value *Op = *i;
891        if (StructType *STy = dyn_cast<StructType>(*GTI)) {
892          const StructLayout *SL = TD.getStructLayout(STy);
893          unsigned Idx = cast<ConstantInt>(Op)->getZExtValue();
894          TmpOffset += SL->getElementOffset(Idx);
895        } else {
896          uint64_t S = TD.getTypeAllocSize(GTI.getIndexedType());
897          for (;;) {
898            if (const ConstantInt *CI = dyn_cast<ConstantInt>(Op)) {
899              // Constant-offset addressing.
900              TmpOffset += CI->getSExtValue() * S;
901              break;
902            }
903            if (isa<AddOperator>(Op) &&
904                (!isa<Instruction>(Op) ||
905                 FuncInfo.MBBMap[cast<Instruction>(Op)->getParent()]
906                 == FuncInfo.MBB) &&
907                isa<ConstantInt>(cast<AddOperator>(Op)->getOperand(1))) {
908              // An add (in the same block) with a constant operand. Fold the
909              // constant.
910              ConstantInt *CI =
911              cast<ConstantInt>(cast<AddOperator>(Op)->getOperand(1));
912              TmpOffset += CI->getSExtValue() * S;
913              // Iterate on the other operand.
914              Op = cast<AddOperator>(Op)->getOperand(0);
915              continue;
916            }
917            // Unsupported
918            goto unsupported_gep;
919          }
920        }
921      }
922
923      // Try to grab the base operand now.
924      Addr.Offset = TmpOffset;
925      if (ARMComputeAddress(U->getOperand(0), Addr)) return true;
926
927      // We failed, restore everything and try the other options.
928      Addr = SavedAddr;
929
930      unsupported_gep:
931      break;
932    }
933    case Instruction::Alloca: {
934      const AllocaInst *AI = cast<AllocaInst>(Obj);
935      DenseMap<const AllocaInst*, int>::iterator SI =
936        FuncInfo.StaticAllocaMap.find(AI);
937      if (SI != FuncInfo.StaticAllocaMap.end()) {
938        Addr.BaseType = Address::FrameIndexBase;
939        Addr.Base.FI = SI->second;
940        return true;
941      }
942      break;
943    }
944  }
945
946  // Try to get this in a register if nothing else has worked.
947  if (Addr.Base.Reg == 0) Addr.Base.Reg = getRegForValue(Obj);
948  return Addr.Base.Reg != 0;
949}
950
951void ARMFastISel::ARMSimplifyAddress(Address &Addr, MVT VT, bool useAM3) {
952  bool needsLowering = false;
953  switch (VT.SimpleTy) {
954    default: llvm_unreachable("Unhandled load/store type!");
955    case MVT::i1:
956    case MVT::i8:
957    case MVT::i16:
958    case MVT::i32:
959      if (!useAM3) {
960        // Integer loads/stores handle 12-bit offsets.
961        needsLowering = ((Addr.Offset & 0xfff) != Addr.Offset);
962        // Handle negative offsets.
963        if (needsLowering && isThumb2)
964          needsLowering = !(Subtarget->hasV6T2Ops() && Addr.Offset < 0 &&
965                            Addr.Offset > -256);
966      } else {
967        // ARM halfword load/stores and signed byte loads use +/-imm8 offsets.
968        needsLowering = (Addr.Offset > 255 || Addr.Offset < -255);
969      }
970      break;
971    case MVT::f32:
972    case MVT::f64:
973      // Floating point operands handle 8-bit offsets.
974      needsLowering = ((Addr.Offset & 0xff) != Addr.Offset);
975      break;
976  }
977
978  // If this is a stack pointer and the offset needs to be simplified then
979  // put the alloca address into a register, set the base type back to
980  // register and continue. This should almost never happen.
981  if (needsLowering && Addr.BaseType == Address::FrameIndexBase) {
982    const TargetRegisterClass *RC = isThumb2 ?
983      (const TargetRegisterClass*)&ARM::tGPRRegClass :
984      (const TargetRegisterClass*)&ARM::GPRRegClass;
985    unsigned ResultReg = createResultReg(RC);
986    unsigned Opc = isThumb2 ? ARM::t2ADDri : ARM::ADDri;
987    AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
988                            TII.get(Opc), ResultReg)
989                            .addFrameIndex(Addr.Base.FI)
990                            .addImm(0));
991    Addr.Base.Reg = ResultReg;
992    Addr.BaseType = Address::RegBase;
993  }
994
995  // Since the offset is too large for the load/store instruction
996  // get the reg+offset into a register.
997  if (needsLowering) {
998    Addr.Base.Reg = FastEmit_ri_(MVT::i32, ISD::ADD, Addr.Base.Reg,
999                                 /*Op0IsKill*/false, Addr.Offset, MVT::i32);
1000    Addr.Offset = 0;
1001  }
1002}
1003
1004void ARMFastISel::AddLoadStoreOperands(MVT VT, Address &Addr,
1005                                       const MachineInstrBuilder &MIB,
1006                                       unsigned Flags, bool useAM3) {
1007  // addrmode5 output depends on the selection dag addressing dividing the
1008  // offset by 4 that it then later multiplies. Do this here as well.
1009  if (VT.SimpleTy == MVT::f32 || VT.SimpleTy == MVT::f64)
1010    Addr.Offset /= 4;
1011
1012  // Frame base works a bit differently. Handle it separately.
1013  if (Addr.BaseType == Address::FrameIndexBase) {
1014    int FI = Addr.Base.FI;
1015    int Offset = Addr.Offset;
1016    MachineMemOperand *MMO =
1017          FuncInfo.MF->getMachineMemOperand(
1018                                  MachinePointerInfo::getFixedStack(FI, Offset),
1019                                  Flags,
1020                                  MFI.getObjectSize(FI),
1021                                  MFI.getObjectAlignment(FI));
1022    // Now add the rest of the operands.
1023    MIB.addFrameIndex(FI);
1024
1025    // ARM halfword load/stores and signed byte loads need an additional
1026    // operand.
1027    if (useAM3) {
1028      signed Imm = (Addr.Offset < 0) ? (0x100 | -Addr.Offset) : Addr.Offset;
1029      MIB.addReg(0);
1030      MIB.addImm(Imm);
1031    } else {
1032      MIB.addImm(Addr.Offset);
1033    }
1034    MIB.addMemOperand(MMO);
1035  } else {
1036    // Now add the rest of the operands.
1037    MIB.addReg(Addr.Base.Reg);
1038
1039    // ARM halfword load/stores and signed byte loads need an additional
1040    // operand.
1041    if (useAM3) {
1042      signed Imm = (Addr.Offset < 0) ? (0x100 | -Addr.Offset) : Addr.Offset;
1043      MIB.addReg(0);
1044      MIB.addImm(Imm);
1045    } else {
1046      MIB.addImm(Addr.Offset);
1047    }
1048  }
1049  AddOptionalDefs(MIB);
1050}
1051
1052bool ARMFastISel::ARMEmitLoad(MVT VT, unsigned &ResultReg, Address &Addr,
1053                              unsigned Alignment, bool isZExt, bool allocReg) {
1054  unsigned Opc;
1055  bool useAM3 = false;
1056  bool needVMOV = false;
1057  const TargetRegisterClass *RC;
1058  switch (VT.SimpleTy) {
1059    // This is mostly going to be Neon/vector support.
1060    default: return false;
1061    case MVT::i1:
1062    case MVT::i8:
1063      if (isThumb2) {
1064        if (Addr.Offset < 0 && Addr.Offset > -256 && Subtarget->hasV6T2Ops())
1065          Opc = isZExt ? ARM::t2LDRBi8 : ARM::t2LDRSBi8;
1066        else
1067          Opc = isZExt ? ARM::t2LDRBi12 : ARM::t2LDRSBi12;
1068      } else {
1069        if (isZExt) {
1070          Opc = ARM::LDRBi12;
1071        } else {
1072          Opc = ARM::LDRSB;
1073          useAM3 = true;
1074        }
1075      }
1076      RC = isThumb2 ? &ARM::rGPRRegClass : &ARM::GPRnopcRegClass;
1077      break;
1078    case MVT::i16:
1079      if (Alignment && Alignment < 2 && !Subtarget->allowsUnalignedMem())
1080        return false;
1081
1082      if (isThumb2) {
1083        if (Addr.Offset < 0 && Addr.Offset > -256 && Subtarget->hasV6T2Ops())
1084          Opc = isZExt ? ARM::t2LDRHi8 : ARM::t2LDRSHi8;
1085        else
1086          Opc = isZExt ? ARM::t2LDRHi12 : ARM::t2LDRSHi12;
1087      } else {
1088        Opc = isZExt ? ARM::LDRH : ARM::LDRSH;
1089        useAM3 = true;
1090      }
1091      RC = isThumb2 ? &ARM::rGPRRegClass : &ARM::GPRnopcRegClass;
1092      break;
1093    case MVT::i32:
1094      if (Alignment && Alignment < 4 && !Subtarget->allowsUnalignedMem())
1095        return false;
1096
1097      if (isThumb2) {
1098        if (Addr.Offset < 0 && Addr.Offset > -256 && Subtarget->hasV6T2Ops())
1099          Opc = ARM::t2LDRi8;
1100        else
1101          Opc = ARM::t2LDRi12;
1102      } else {
1103        Opc = ARM::LDRi12;
1104      }
1105      RC = isThumb2 ? &ARM::rGPRRegClass : &ARM::GPRnopcRegClass;
1106      break;
1107    case MVT::f32:
1108      if (!Subtarget->hasVFP2()) return false;
1109      // Unaligned loads need special handling. Floats require word-alignment.
1110      if (Alignment && Alignment < 4) {
1111        needVMOV = true;
1112        VT = MVT::i32;
1113        Opc = isThumb2 ? ARM::t2LDRi12 : ARM::LDRi12;
1114        RC = isThumb2 ? &ARM::rGPRRegClass : &ARM::GPRnopcRegClass;
1115      } else {
1116        Opc = ARM::VLDRS;
1117        RC = TLI.getRegClassFor(VT);
1118      }
1119      break;
1120    case MVT::f64:
1121      if (!Subtarget->hasVFP2()) return false;
1122      // FIXME: Unaligned loads need special handling.  Doublewords require
1123      // word-alignment.
1124      if (Alignment && Alignment < 4)
1125        return false;
1126
1127      Opc = ARM::VLDRD;
1128      RC = TLI.getRegClassFor(VT);
1129      break;
1130  }
1131  // Simplify this down to something we can handle.
1132  ARMSimplifyAddress(Addr, VT, useAM3);
1133
1134  // Create the base instruction, then add the operands.
1135  if (allocReg)
1136    ResultReg = createResultReg(RC);
1137  assert (ResultReg > 255 && "Expected an allocated virtual register.");
1138  MachineInstrBuilder MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
1139                                    TII.get(Opc), ResultReg);
1140  AddLoadStoreOperands(VT, Addr, MIB, MachineMemOperand::MOLoad, useAM3);
1141
1142  // If we had an unaligned load of a float we've converted it to an regular
1143  // load.  Now we must move from the GRP to the FP register.
1144  if (needVMOV) {
1145    unsigned MoveReg = createResultReg(TLI.getRegClassFor(MVT::f32));
1146    AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
1147                            TII.get(ARM::VMOVSR), MoveReg)
1148                    .addReg(ResultReg));
1149    ResultReg = MoveReg;
1150  }
1151  return true;
1152}
1153
1154bool ARMFastISel::SelectLoad(const Instruction *I) {
1155  // Atomic loads need special handling.
1156  if (cast<LoadInst>(I)->isAtomic())
1157    return false;
1158
1159  // Verify we have a legal type before going any further.
1160  MVT VT;
1161  if (!isLoadTypeLegal(I->getType(), VT))
1162    return false;
1163
1164  // See if we can handle this address.
1165  Address Addr;
1166  if (!ARMComputeAddress(I->getOperand(0), Addr)) return false;
1167
1168  unsigned ResultReg;
1169  if (!ARMEmitLoad(VT, ResultReg, Addr, cast<LoadInst>(I)->getAlignment()))
1170    return false;
1171  UpdateValueMap(I, ResultReg);
1172  return true;
1173}
1174
1175bool ARMFastISel::ARMEmitStore(MVT VT, unsigned SrcReg, Address &Addr,
1176                               unsigned Alignment) {
1177  unsigned StrOpc;
1178  bool useAM3 = false;
1179  switch (VT.SimpleTy) {
1180    // This is mostly going to be Neon/vector support.
1181    default: return false;
1182    case MVT::i1: {
1183      unsigned Res = createResultReg(isThumb2 ?
1184        (const TargetRegisterClass*)&ARM::tGPRRegClass :
1185        (const TargetRegisterClass*)&ARM::GPRRegClass);
1186      unsigned Opc = isThumb2 ? ARM::t2ANDri : ARM::ANDri;
1187      SrcReg = constrainOperandRegClass(TII.get(Opc), SrcReg, 1);
1188      AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
1189                              TII.get(Opc), Res)
1190                      .addReg(SrcReg).addImm(1));
1191      SrcReg = Res;
1192    } // Fallthrough here.
1193    case MVT::i8:
1194      if (isThumb2) {
1195        if (Addr.Offset < 0 && Addr.Offset > -256 && Subtarget->hasV6T2Ops())
1196          StrOpc = ARM::t2STRBi8;
1197        else
1198          StrOpc = ARM::t2STRBi12;
1199      } else {
1200        StrOpc = ARM::STRBi12;
1201      }
1202      break;
1203    case MVT::i16:
1204      if (Alignment && Alignment < 2 && !Subtarget->allowsUnalignedMem())
1205        return false;
1206
1207      if (isThumb2) {
1208        if (Addr.Offset < 0 && Addr.Offset > -256 && Subtarget->hasV6T2Ops())
1209          StrOpc = ARM::t2STRHi8;
1210        else
1211          StrOpc = ARM::t2STRHi12;
1212      } else {
1213        StrOpc = ARM::STRH;
1214        useAM3 = true;
1215      }
1216      break;
1217    case MVT::i32:
1218      if (Alignment && Alignment < 4 && !Subtarget->allowsUnalignedMem())
1219        return false;
1220
1221      if (isThumb2) {
1222        if (Addr.Offset < 0 && Addr.Offset > -256 && Subtarget->hasV6T2Ops())
1223          StrOpc = ARM::t2STRi8;
1224        else
1225          StrOpc = ARM::t2STRi12;
1226      } else {
1227        StrOpc = ARM::STRi12;
1228      }
1229      break;
1230    case MVT::f32:
1231      if (!Subtarget->hasVFP2()) return false;
1232      // Unaligned stores need special handling. Floats require word-alignment.
1233      if (Alignment && Alignment < 4) {
1234        unsigned MoveReg = createResultReg(TLI.getRegClassFor(MVT::i32));
1235        AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
1236                                TII.get(ARM::VMOVRS), MoveReg)
1237                        .addReg(SrcReg));
1238        SrcReg = MoveReg;
1239        VT = MVT::i32;
1240        StrOpc = isThumb2 ? ARM::t2STRi12 : ARM::STRi12;
1241      } else {
1242        StrOpc = ARM::VSTRS;
1243      }
1244      break;
1245    case MVT::f64:
1246      if (!Subtarget->hasVFP2()) return false;
1247      // FIXME: Unaligned stores need special handling.  Doublewords require
1248      // word-alignment.
1249      if (Alignment && Alignment < 4)
1250          return false;
1251
1252      StrOpc = ARM::VSTRD;
1253      break;
1254  }
1255  // Simplify this down to something we can handle.
1256  ARMSimplifyAddress(Addr, VT, useAM3);
1257
1258  // Create the base instruction, then add the operands.
1259  SrcReg = constrainOperandRegClass(TII.get(StrOpc), SrcReg, 0);
1260  MachineInstrBuilder MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
1261                                    TII.get(StrOpc))
1262                            .addReg(SrcReg);
1263  AddLoadStoreOperands(VT, Addr, MIB, MachineMemOperand::MOStore, useAM3);
1264  return true;
1265}
1266
1267bool ARMFastISel::SelectStore(const Instruction *I) {
1268  Value *Op0 = I->getOperand(0);
1269  unsigned SrcReg = 0;
1270
1271  // Atomic stores need special handling.
1272  if (cast<StoreInst>(I)->isAtomic())
1273    return false;
1274
1275  // Verify we have a legal type before going any further.
1276  MVT VT;
1277  if (!isLoadTypeLegal(I->getOperand(0)->getType(), VT))
1278    return false;
1279
1280  // Get the value to be stored into a register.
1281  SrcReg = getRegForValue(Op0);
1282  if (SrcReg == 0) return false;
1283
1284  // See if we can handle this address.
1285  Address Addr;
1286  if (!ARMComputeAddress(I->getOperand(1), Addr))
1287    return false;
1288
1289  if (!ARMEmitStore(VT, SrcReg, Addr, cast<StoreInst>(I)->getAlignment()))
1290    return false;
1291  return true;
1292}
1293
1294static ARMCC::CondCodes getComparePred(CmpInst::Predicate Pred) {
1295  switch (Pred) {
1296    // Needs two compares...
1297    case CmpInst::FCMP_ONE:
1298    case CmpInst::FCMP_UEQ:
1299    default:
1300      // AL is our "false" for now. The other two need more compares.
1301      return ARMCC::AL;
1302    case CmpInst::ICMP_EQ:
1303    case CmpInst::FCMP_OEQ:
1304      return ARMCC::EQ;
1305    case CmpInst::ICMP_SGT:
1306    case CmpInst::FCMP_OGT:
1307      return ARMCC::GT;
1308    case CmpInst::ICMP_SGE:
1309    case CmpInst::FCMP_OGE:
1310      return ARMCC::GE;
1311    case CmpInst::ICMP_UGT:
1312    case CmpInst::FCMP_UGT:
1313      return ARMCC::HI;
1314    case CmpInst::FCMP_OLT:
1315      return ARMCC::MI;
1316    case CmpInst::ICMP_ULE:
1317    case CmpInst::FCMP_OLE:
1318      return ARMCC::LS;
1319    case CmpInst::FCMP_ORD:
1320      return ARMCC::VC;
1321    case CmpInst::FCMP_UNO:
1322      return ARMCC::VS;
1323    case CmpInst::FCMP_UGE:
1324      return ARMCC::PL;
1325    case CmpInst::ICMP_SLT:
1326    case CmpInst::FCMP_ULT:
1327      return ARMCC::LT;
1328    case CmpInst::ICMP_SLE:
1329    case CmpInst::FCMP_ULE:
1330      return ARMCC::LE;
1331    case CmpInst::FCMP_UNE:
1332    case CmpInst::ICMP_NE:
1333      return ARMCC::NE;
1334    case CmpInst::ICMP_UGE:
1335      return ARMCC::HS;
1336    case CmpInst::ICMP_ULT:
1337      return ARMCC::LO;
1338  }
1339}
1340
1341bool ARMFastISel::SelectBranch(const Instruction *I) {
1342  const BranchInst *BI = cast<BranchInst>(I);
1343  MachineBasicBlock *TBB = FuncInfo.MBBMap[BI->getSuccessor(0)];
1344  MachineBasicBlock *FBB = FuncInfo.MBBMap[BI->getSuccessor(1)];
1345
1346  // Simple branch support.
1347
1348  // If we can, avoid recomputing the compare - redoing it could lead to wonky
1349  // behavior.
1350  if (const CmpInst *CI = dyn_cast<CmpInst>(BI->getCondition())) {
1351    if (CI->hasOneUse() && (CI->getParent() == I->getParent())) {
1352
1353      // Get the compare predicate.
1354      // Try to take advantage of fallthrough opportunities.
1355      CmpInst::Predicate Predicate = CI->getPredicate();
1356      if (FuncInfo.MBB->isLayoutSuccessor(TBB)) {
1357        std::swap(TBB, FBB);
1358        Predicate = CmpInst::getInversePredicate(Predicate);
1359      }
1360
1361      ARMCC::CondCodes ARMPred = getComparePred(Predicate);
1362
1363      // We may not handle every CC for now.
1364      if (ARMPred == ARMCC::AL) return false;
1365
1366      // Emit the compare.
1367      if (!ARMEmitCmp(CI->getOperand(0), CI->getOperand(1), CI->isUnsigned()))
1368        return false;
1369
1370      unsigned BrOpc = isThumb2 ? ARM::t2Bcc : ARM::Bcc;
1371      BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(BrOpc))
1372      .addMBB(TBB).addImm(ARMPred).addReg(ARM::CPSR);
1373      FastEmitBranch(FBB, DL);
1374      FuncInfo.MBB->addSuccessor(TBB);
1375      return true;
1376    }
1377  } else if (TruncInst *TI = dyn_cast<TruncInst>(BI->getCondition())) {
1378    MVT SourceVT;
1379    if (TI->hasOneUse() && TI->getParent() == I->getParent() &&
1380        (isLoadTypeLegal(TI->getOperand(0)->getType(), SourceVT))) {
1381      unsigned TstOpc = isThumb2 ? ARM::t2TSTri : ARM::TSTri;
1382      unsigned OpReg = getRegForValue(TI->getOperand(0));
1383      AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
1384                              TII.get(TstOpc))
1385                      .addReg(OpReg).addImm(1));
1386
1387      unsigned CCMode = ARMCC::NE;
1388      if (FuncInfo.MBB->isLayoutSuccessor(TBB)) {
1389        std::swap(TBB, FBB);
1390        CCMode = ARMCC::EQ;
1391      }
1392
1393      unsigned BrOpc = isThumb2 ? ARM::t2Bcc : ARM::Bcc;
1394      BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(BrOpc))
1395      .addMBB(TBB).addImm(CCMode).addReg(ARM::CPSR);
1396
1397      FastEmitBranch(FBB, DL);
1398      FuncInfo.MBB->addSuccessor(TBB);
1399      return true;
1400    }
1401  } else if (const ConstantInt *CI =
1402             dyn_cast<ConstantInt>(BI->getCondition())) {
1403    uint64_t Imm = CI->getZExtValue();
1404    MachineBasicBlock *Target = (Imm == 0) ? FBB : TBB;
1405    FastEmitBranch(Target, DL);
1406    return true;
1407  }
1408
1409  unsigned CmpReg = getRegForValue(BI->getCondition());
1410  if (CmpReg == 0) return false;
1411
1412  // We've been divorced from our compare!  Our block was split, and
1413  // now our compare lives in a predecessor block.  We musn't
1414  // re-compare here, as the children of the compare aren't guaranteed
1415  // live across the block boundary (we *could* check for this).
1416  // Regardless, the compare has been done in the predecessor block,
1417  // and it left a value for us in a virtual register.  Ergo, we test
1418  // the one-bit value left in the virtual register.
1419  unsigned TstOpc = isThumb2 ? ARM::t2TSTri : ARM::TSTri;
1420  AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(TstOpc))
1421                  .addReg(CmpReg).addImm(1));
1422
1423  unsigned CCMode = ARMCC::NE;
1424  if (FuncInfo.MBB->isLayoutSuccessor(TBB)) {
1425    std::swap(TBB, FBB);
1426    CCMode = ARMCC::EQ;
1427  }
1428
1429  unsigned BrOpc = isThumb2 ? ARM::t2Bcc : ARM::Bcc;
1430  BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(BrOpc))
1431                  .addMBB(TBB).addImm(CCMode).addReg(ARM::CPSR);
1432  FastEmitBranch(FBB, DL);
1433  FuncInfo.MBB->addSuccessor(TBB);
1434  return true;
1435}
1436
1437bool ARMFastISel::SelectIndirectBr(const Instruction *I) {
1438  unsigned AddrReg = getRegForValue(I->getOperand(0));
1439  if (AddrReg == 0) return false;
1440
1441  unsigned Opc = isThumb2 ? ARM::tBRIND : ARM::BX;
1442  AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(Opc))
1443                  .addReg(AddrReg));
1444
1445  const IndirectBrInst *IB = cast<IndirectBrInst>(I);
1446  for (unsigned i = 0, e = IB->getNumSuccessors(); i != e; ++i)
1447    FuncInfo.MBB->addSuccessor(FuncInfo.MBBMap[IB->getSuccessor(i)]);
1448
1449  return true;
1450}
1451
1452bool ARMFastISel::ARMEmitCmp(const Value *Src1Value, const Value *Src2Value,
1453                             bool isZExt) {
1454  Type *Ty = Src1Value->getType();
1455  EVT SrcEVT = TLI.getValueType(Ty, true);
1456  if (!SrcEVT.isSimple()) return false;
1457  MVT SrcVT = SrcEVT.getSimpleVT();
1458
1459  bool isFloat = (Ty->isFloatTy() || Ty->isDoubleTy());
1460  if (isFloat && !Subtarget->hasVFP2())
1461    return false;
1462
1463  // Check to see if the 2nd operand is a constant that we can encode directly
1464  // in the compare.
1465  int Imm = 0;
1466  bool UseImm = false;
1467  bool isNegativeImm = false;
1468  // FIXME: At -O0 we don't have anything that canonicalizes operand order.
1469  // Thus, Src1Value may be a ConstantInt, but we're missing it.
1470  if (const ConstantInt *ConstInt = dyn_cast<ConstantInt>(Src2Value)) {
1471    if (SrcVT == MVT::i32 || SrcVT == MVT::i16 || SrcVT == MVT::i8 ||
1472        SrcVT == MVT::i1) {
1473      const APInt &CIVal = ConstInt->getValue();
1474      Imm = (isZExt) ? (int)CIVal.getZExtValue() : (int)CIVal.getSExtValue();
1475      // For INT_MIN/LONG_MIN (i.e., 0x80000000) we need to use a cmp, rather
1476      // then a cmn, because there is no way to represent 2147483648 as a
1477      // signed 32-bit int.
1478      if (Imm < 0 && Imm != (int)0x80000000) {
1479        isNegativeImm = true;
1480        Imm = -Imm;
1481      }
1482      UseImm = isThumb2 ? (ARM_AM::getT2SOImmVal(Imm) != -1) :
1483        (ARM_AM::getSOImmVal(Imm) != -1);
1484    }
1485  } else if (const ConstantFP *ConstFP = dyn_cast<ConstantFP>(Src2Value)) {
1486    if (SrcVT == MVT::f32 || SrcVT == MVT::f64)
1487      if (ConstFP->isZero() && !ConstFP->isNegative())
1488        UseImm = true;
1489  }
1490
1491  unsigned CmpOpc;
1492  bool isICmp = true;
1493  bool needsExt = false;
1494  switch (SrcVT.SimpleTy) {
1495    default: return false;
1496    // TODO: Verify compares.
1497    case MVT::f32:
1498      isICmp = false;
1499      CmpOpc = UseImm ? ARM::VCMPEZS : ARM::VCMPES;
1500      break;
1501    case MVT::f64:
1502      isICmp = false;
1503      CmpOpc = UseImm ? ARM::VCMPEZD : ARM::VCMPED;
1504      break;
1505    case MVT::i1:
1506    case MVT::i8:
1507    case MVT::i16:
1508      needsExt = true;
1509    // Intentional fall-through.
1510    case MVT::i32:
1511      if (isThumb2) {
1512        if (!UseImm)
1513          CmpOpc = ARM::t2CMPrr;
1514        else
1515          CmpOpc = isNegativeImm ? ARM::t2CMNri : ARM::t2CMPri;
1516      } else {
1517        if (!UseImm)
1518          CmpOpc = ARM::CMPrr;
1519        else
1520          CmpOpc = isNegativeImm ? ARM::CMNri : ARM::CMPri;
1521      }
1522      break;
1523  }
1524
1525  unsigned SrcReg1 = getRegForValue(Src1Value);
1526  if (SrcReg1 == 0) return false;
1527
1528  unsigned SrcReg2 = 0;
1529  if (!UseImm) {
1530    SrcReg2 = getRegForValue(Src2Value);
1531    if (SrcReg2 == 0) return false;
1532  }
1533
1534  // We have i1, i8, or i16, we need to either zero extend or sign extend.
1535  if (needsExt) {
1536    SrcReg1 = ARMEmitIntExt(SrcVT, SrcReg1, MVT::i32, isZExt);
1537    if (SrcReg1 == 0) return false;
1538    if (!UseImm) {
1539      SrcReg2 = ARMEmitIntExt(SrcVT, SrcReg2, MVT::i32, isZExt);
1540      if (SrcReg2 == 0) return false;
1541    }
1542  }
1543
1544  const MCInstrDesc &II = TII.get(CmpOpc);
1545  SrcReg1 = constrainOperandRegClass(II, SrcReg1, 0);
1546  if (!UseImm) {
1547    SrcReg2 = constrainOperandRegClass(II, SrcReg2, 1);
1548    AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II)
1549                    .addReg(SrcReg1).addReg(SrcReg2));
1550  } else {
1551    MachineInstrBuilder MIB;
1552    MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II)
1553      .addReg(SrcReg1);
1554
1555    // Only add immediate for icmp as the immediate for fcmp is an implicit 0.0.
1556    if (isICmp)
1557      MIB.addImm(Imm);
1558    AddOptionalDefs(MIB);
1559  }
1560
1561  // For floating point we need to move the result to a comparison register
1562  // that we can then use for branches.
1563  if (Ty->isFloatTy() || Ty->isDoubleTy())
1564    AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
1565                            TII.get(ARM::FMSTAT)));
1566  return true;
1567}
1568
1569bool ARMFastISel::SelectCmp(const Instruction *I) {
1570  const CmpInst *CI = cast<CmpInst>(I);
1571
1572  // Get the compare predicate.
1573  ARMCC::CondCodes ARMPred = getComparePred(CI->getPredicate());
1574
1575  // We may not handle every CC for now.
1576  if (ARMPred == ARMCC::AL) return false;
1577
1578  // Emit the compare.
1579  if (!ARMEmitCmp(CI->getOperand(0), CI->getOperand(1), CI->isUnsigned()))
1580    return false;
1581
1582  // Now set a register based on the comparison. Explicitly set the predicates
1583  // here.
1584  unsigned MovCCOpc = isThumb2 ? ARM::t2MOVCCi : ARM::MOVCCi;
1585  const TargetRegisterClass *RC = isThumb2 ?
1586    (const TargetRegisterClass*)&ARM::rGPRRegClass :
1587    (const TargetRegisterClass*)&ARM::GPRRegClass;
1588  unsigned DestReg = createResultReg(RC);
1589  Constant *Zero = ConstantInt::get(Type::getInt32Ty(*Context), 0);
1590  unsigned ZeroReg = TargetMaterializeConstant(Zero);
1591  // ARMEmitCmp emits a FMSTAT when necessary, so it's always safe to use CPSR.
1592  BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(MovCCOpc), DestReg)
1593          .addReg(ZeroReg).addImm(1)
1594          .addImm(ARMPred).addReg(ARM::CPSR);
1595
1596  UpdateValueMap(I, DestReg);
1597  return true;
1598}
1599
1600bool ARMFastISel::SelectFPExt(const Instruction *I) {
1601  // Make sure we have VFP and that we're extending float to double.
1602  if (!Subtarget->hasVFP2()) return false;
1603
1604  Value *V = I->getOperand(0);
1605  if (!I->getType()->isDoubleTy() ||
1606      !V->getType()->isFloatTy()) return false;
1607
1608  unsigned Op = getRegForValue(V);
1609  if (Op == 0) return false;
1610
1611  unsigned Result = createResultReg(&ARM::DPRRegClass);
1612  AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
1613                          TII.get(ARM::VCVTDS), Result)
1614                  .addReg(Op));
1615  UpdateValueMap(I, Result);
1616  return true;
1617}
1618
1619bool ARMFastISel::SelectFPTrunc(const Instruction *I) {
1620  // Make sure we have VFP and that we're truncating double to float.
1621  if (!Subtarget->hasVFP2()) return false;
1622
1623  Value *V = I->getOperand(0);
1624  if (!(I->getType()->isFloatTy() &&
1625        V->getType()->isDoubleTy())) return false;
1626
1627  unsigned Op = getRegForValue(V);
1628  if (Op == 0) return false;
1629
1630  unsigned Result = createResultReg(&ARM::SPRRegClass);
1631  AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
1632                          TII.get(ARM::VCVTSD), Result)
1633                  .addReg(Op));
1634  UpdateValueMap(I, Result);
1635  return true;
1636}
1637
1638bool ARMFastISel::SelectIToFP(const Instruction *I, bool isSigned) {
1639  // Make sure we have VFP.
1640  if (!Subtarget->hasVFP2()) return false;
1641
1642  MVT DstVT;
1643  Type *Ty = I->getType();
1644  if (!isTypeLegal(Ty, DstVT))
1645    return false;
1646
1647  Value *Src = I->getOperand(0);
1648  EVT SrcEVT = TLI.getValueType(Src->getType(), true);
1649  if (!SrcEVT.isSimple())
1650    return false;
1651  MVT SrcVT = SrcEVT.getSimpleVT();
1652  if (SrcVT != MVT::i32 && SrcVT != MVT::i16 && SrcVT != MVT::i8)
1653    return false;
1654
1655  unsigned SrcReg = getRegForValue(Src);
1656  if (SrcReg == 0) return false;
1657
1658  // Handle sign-extension.
1659  if (SrcVT == MVT::i16 || SrcVT == MVT::i8) {
1660    SrcReg = ARMEmitIntExt(SrcVT, SrcReg, MVT::i32,
1661                                       /*isZExt*/!isSigned);
1662    if (SrcReg == 0) return false;
1663  }
1664
1665  // The conversion routine works on fp-reg to fp-reg and the operand above
1666  // was an integer, move it to the fp registers if possible.
1667  unsigned FP = ARMMoveToFPReg(MVT::f32, SrcReg);
1668  if (FP == 0) return false;
1669
1670  unsigned Opc;
1671  if (Ty->isFloatTy()) Opc = isSigned ? ARM::VSITOS : ARM::VUITOS;
1672  else if (Ty->isDoubleTy()) Opc = isSigned ? ARM::VSITOD : ARM::VUITOD;
1673  else return false;
1674
1675  unsigned ResultReg = createResultReg(TLI.getRegClassFor(DstVT));
1676  AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(Opc),
1677                          ResultReg)
1678                  .addReg(FP));
1679  UpdateValueMap(I, ResultReg);
1680  return true;
1681}
1682
1683bool ARMFastISel::SelectFPToI(const Instruction *I, bool isSigned) {
1684  // Make sure we have VFP.
1685  if (!Subtarget->hasVFP2()) return false;
1686
1687  MVT DstVT;
1688  Type *RetTy = I->getType();
1689  if (!isTypeLegal(RetTy, DstVT))
1690    return false;
1691
1692  unsigned Op = getRegForValue(I->getOperand(0));
1693  if (Op == 0) return false;
1694
1695  unsigned Opc;
1696  Type *OpTy = I->getOperand(0)->getType();
1697  if (OpTy->isFloatTy()) Opc = isSigned ? ARM::VTOSIZS : ARM::VTOUIZS;
1698  else if (OpTy->isDoubleTy()) Opc = isSigned ? ARM::VTOSIZD : ARM::VTOUIZD;
1699  else return false;
1700
1701  // f64->s32/u32 or f32->s32/u32 both need an intermediate f32 reg.
1702  unsigned ResultReg = createResultReg(TLI.getRegClassFor(MVT::f32));
1703  AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(Opc),
1704                          ResultReg)
1705                  .addReg(Op));
1706
1707  // This result needs to be in an integer register, but the conversion only
1708  // takes place in fp-regs.
1709  unsigned IntReg = ARMMoveToIntReg(DstVT, ResultReg);
1710  if (IntReg == 0) return false;
1711
1712  UpdateValueMap(I, IntReg);
1713  return true;
1714}
1715
1716bool ARMFastISel::SelectSelect(const Instruction *I) {
1717  MVT VT;
1718  if (!isTypeLegal(I->getType(), VT))
1719    return false;
1720
1721  // Things need to be register sized for register moves.
1722  if (VT != MVT::i32) return false;
1723
1724  unsigned CondReg = getRegForValue(I->getOperand(0));
1725  if (CondReg == 0) return false;
1726  unsigned Op1Reg = getRegForValue(I->getOperand(1));
1727  if (Op1Reg == 0) return false;
1728
1729  // Check to see if we can use an immediate in the conditional move.
1730  int Imm = 0;
1731  bool UseImm = false;
1732  bool isNegativeImm = false;
1733  if (const ConstantInt *ConstInt = dyn_cast<ConstantInt>(I->getOperand(2))) {
1734    assert (VT == MVT::i32 && "Expecting an i32.");
1735    Imm = (int)ConstInt->getValue().getZExtValue();
1736    if (Imm < 0) {
1737      isNegativeImm = true;
1738      Imm = ~Imm;
1739    }
1740    UseImm = isThumb2 ? (ARM_AM::getT2SOImmVal(Imm) != -1) :
1741      (ARM_AM::getSOImmVal(Imm) != -1);
1742  }
1743
1744  unsigned Op2Reg = 0;
1745  if (!UseImm) {
1746    Op2Reg = getRegForValue(I->getOperand(2));
1747    if (Op2Reg == 0) return false;
1748  }
1749
1750  unsigned CmpOpc = isThumb2 ? ARM::t2CMPri : ARM::CMPri;
1751  CondReg = constrainOperandRegClass(TII.get(CmpOpc), CondReg, 0);
1752  AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(CmpOpc))
1753                  .addReg(CondReg).addImm(0));
1754
1755  unsigned MovCCOpc;
1756  const TargetRegisterClass *RC;
1757  if (!UseImm) {
1758    RC = isThumb2 ? &ARM::tGPRRegClass : &ARM::GPRRegClass;
1759    MovCCOpc = isThumb2 ? ARM::t2MOVCCr : ARM::MOVCCr;
1760  } else {
1761    RC = isThumb2 ? &ARM::rGPRRegClass : &ARM::GPRRegClass;
1762    if (!isNegativeImm)
1763      MovCCOpc = isThumb2 ? ARM::t2MOVCCi : ARM::MOVCCi;
1764    else
1765      MovCCOpc = isThumb2 ? ARM::t2MVNCCi : ARM::MVNCCi;
1766  }
1767  unsigned ResultReg = createResultReg(RC);
1768  if (!UseImm) {
1769    Op2Reg = constrainOperandRegClass(TII.get(MovCCOpc), Op2Reg, 1);
1770    Op1Reg = constrainOperandRegClass(TII.get(MovCCOpc), Op1Reg, 2);
1771    BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(MovCCOpc), ResultReg)
1772    .addReg(Op2Reg).addReg(Op1Reg).addImm(ARMCC::NE).addReg(ARM::CPSR);
1773  } else {
1774    Op1Reg = constrainOperandRegClass(TII.get(MovCCOpc), Op1Reg, 1);
1775    BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(MovCCOpc), ResultReg)
1776    .addReg(Op1Reg).addImm(Imm).addImm(ARMCC::EQ).addReg(ARM::CPSR);
1777  }
1778  UpdateValueMap(I, ResultReg);
1779  return true;
1780}
1781
1782bool ARMFastISel::SelectDiv(const Instruction *I, bool isSigned) {
1783  MVT VT;
1784  Type *Ty = I->getType();
1785  if (!isTypeLegal(Ty, VT))
1786    return false;
1787
1788  // If we have integer div support we should have selected this automagically.
1789  // In case we have a real miss go ahead and return false and we'll pick
1790  // it up later.
1791  if (Subtarget->hasDivide()) return false;
1792
1793  // Otherwise emit a libcall.
1794  RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
1795  if (VT == MVT::i8)
1796    LC = isSigned ? RTLIB::SDIV_I8 : RTLIB::UDIV_I8;
1797  else if (VT == MVT::i16)
1798    LC = isSigned ? RTLIB::SDIV_I16 : RTLIB::UDIV_I16;
1799  else if (VT == MVT::i32)
1800    LC = isSigned ? RTLIB::SDIV_I32 : RTLIB::UDIV_I32;
1801  else if (VT == MVT::i64)
1802    LC = isSigned ? RTLIB::SDIV_I64 : RTLIB::UDIV_I64;
1803  else if (VT == MVT::i128)
1804    LC = isSigned ? RTLIB::SDIV_I128 : RTLIB::UDIV_I128;
1805  assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unsupported SDIV!");
1806
1807  return ARMEmitLibcall(I, LC);
1808}
1809
1810bool ARMFastISel::SelectRem(const Instruction *I, bool isSigned) {
1811  MVT VT;
1812  Type *Ty = I->getType();
1813  if (!isTypeLegal(Ty, VT))
1814    return false;
1815
1816  RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
1817  if (VT == MVT::i8)
1818    LC = isSigned ? RTLIB::SREM_I8 : RTLIB::UREM_I8;
1819  else if (VT == MVT::i16)
1820    LC = isSigned ? RTLIB::SREM_I16 : RTLIB::UREM_I16;
1821  else if (VT == MVT::i32)
1822    LC = isSigned ? RTLIB::SREM_I32 : RTLIB::UREM_I32;
1823  else if (VT == MVT::i64)
1824    LC = isSigned ? RTLIB::SREM_I64 : RTLIB::UREM_I64;
1825  else if (VT == MVT::i128)
1826    LC = isSigned ? RTLIB::SREM_I128 : RTLIB::UREM_I128;
1827  assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unsupported SREM!");
1828
1829  return ARMEmitLibcall(I, LC);
1830}
1831
1832bool ARMFastISel::SelectBinaryIntOp(const Instruction *I, unsigned ISDOpcode) {
1833  EVT DestVT  = TLI.getValueType(I->getType(), true);
1834
1835  // We can get here in the case when we have a binary operation on a non-legal
1836  // type and the target independent selector doesn't know how to handle it.
1837  if (DestVT != MVT::i16 && DestVT != MVT::i8 && DestVT != MVT::i1)
1838    return false;
1839
1840  unsigned Opc;
1841  switch (ISDOpcode) {
1842    default: return false;
1843    case ISD::ADD:
1844      Opc = isThumb2 ? ARM::t2ADDrr : ARM::ADDrr;
1845      break;
1846    case ISD::OR:
1847      Opc = isThumb2 ? ARM::t2ORRrr : ARM::ORRrr;
1848      break;
1849    case ISD::SUB:
1850      Opc = isThumb2 ? ARM::t2SUBrr : ARM::SUBrr;
1851      break;
1852  }
1853
1854  unsigned SrcReg1 = getRegForValue(I->getOperand(0));
1855  if (SrcReg1 == 0) return false;
1856
1857  // TODO: Often the 2nd operand is an immediate, which can be encoded directly
1858  // in the instruction, rather then materializing the value in a register.
1859  unsigned SrcReg2 = getRegForValue(I->getOperand(1));
1860  if (SrcReg2 == 0) return false;
1861
1862  unsigned ResultReg = createResultReg(&ARM::GPRnopcRegClass);
1863  SrcReg1 = constrainOperandRegClass(TII.get(Opc), SrcReg1, 1);
1864  SrcReg2 = constrainOperandRegClass(TII.get(Opc), SrcReg2, 2);
1865  AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
1866                          TII.get(Opc), ResultReg)
1867                  .addReg(SrcReg1).addReg(SrcReg2));
1868  UpdateValueMap(I, ResultReg);
1869  return true;
1870}
1871
1872bool ARMFastISel::SelectBinaryFPOp(const Instruction *I, unsigned ISDOpcode) {
1873  EVT FPVT = TLI.getValueType(I->getType(), true);
1874  if (!FPVT.isSimple()) return false;
1875  MVT VT = FPVT.getSimpleVT();
1876
1877  // We can get here in the case when we want to use NEON for our fp
1878  // operations, but can't figure out how to. Just use the vfp instructions
1879  // if we have them.
1880  // FIXME: It'd be nice to use NEON instructions.
1881  Type *Ty = I->getType();
1882  bool isFloat = (Ty->isDoubleTy() || Ty->isFloatTy());
1883  if (isFloat && !Subtarget->hasVFP2())
1884    return false;
1885
1886  unsigned Opc;
1887  bool is64bit = VT == MVT::f64 || VT == MVT::i64;
1888  switch (ISDOpcode) {
1889    default: return false;
1890    case ISD::FADD:
1891      Opc = is64bit ? ARM::VADDD : ARM::VADDS;
1892      break;
1893    case ISD::FSUB:
1894      Opc = is64bit ? ARM::VSUBD : ARM::VSUBS;
1895      break;
1896    case ISD::FMUL:
1897      Opc = is64bit ? ARM::VMULD : ARM::VMULS;
1898      break;
1899  }
1900  unsigned Op1 = getRegForValue(I->getOperand(0));
1901  if (Op1 == 0) return false;
1902
1903  unsigned Op2 = getRegForValue(I->getOperand(1));
1904  if (Op2 == 0) return false;
1905
1906  unsigned ResultReg = createResultReg(TLI.getRegClassFor(VT.SimpleTy));
1907  AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
1908                          TII.get(Opc), ResultReg)
1909                  .addReg(Op1).addReg(Op2));
1910  UpdateValueMap(I, ResultReg);
1911  return true;
1912}
1913
1914// Call Handling Code
1915
1916// This is largely taken directly from CCAssignFnForNode
1917// TODO: We may not support all of this.
1918CCAssignFn *ARMFastISel::CCAssignFnForCall(CallingConv::ID CC,
1919                                           bool Return,
1920                                           bool isVarArg) {
1921  switch (CC) {
1922  default:
1923    llvm_unreachable("Unsupported calling convention");
1924  case CallingConv::Fast:
1925    if (Subtarget->hasVFP2() && !isVarArg) {
1926      if (!Subtarget->isAAPCS_ABI())
1927        return (Return ? RetFastCC_ARM_APCS : FastCC_ARM_APCS);
1928      // For AAPCS ABI targets, just use VFP variant of the calling convention.
1929      return (Return ? RetCC_ARM_AAPCS_VFP : CC_ARM_AAPCS_VFP);
1930    }
1931    // Fallthrough
1932  case CallingConv::C:
1933    // Use target triple & subtarget features to do actual dispatch.
1934    if (Subtarget->isAAPCS_ABI()) {
1935      if (Subtarget->hasVFP2() &&
1936          TM.Options.FloatABIType == FloatABI::Hard && !isVarArg)
1937        return (Return ? RetCC_ARM_AAPCS_VFP: CC_ARM_AAPCS_VFP);
1938      else
1939        return (Return ? RetCC_ARM_AAPCS: CC_ARM_AAPCS);
1940    } else
1941        return (Return ? RetCC_ARM_APCS: CC_ARM_APCS);
1942  case CallingConv::ARM_AAPCS_VFP:
1943    if (!isVarArg)
1944      return (Return ? RetCC_ARM_AAPCS_VFP: CC_ARM_AAPCS_VFP);
1945    // Fall through to soft float variant, variadic functions don't
1946    // use hard floating point ABI.
1947  case CallingConv::ARM_AAPCS:
1948    return (Return ? RetCC_ARM_AAPCS: CC_ARM_AAPCS);
1949  case CallingConv::ARM_APCS:
1950    return (Return ? RetCC_ARM_APCS: CC_ARM_APCS);
1951  case CallingConv::GHC:
1952    if (Return)
1953      llvm_unreachable("Can't return in GHC call convention");
1954    else
1955      return CC_ARM_APCS_GHC;
1956  }
1957}
1958
1959bool ARMFastISel::ProcessCallArgs(SmallVectorImpl<Value*> &Args,
1960                                  SmallVectorImpl<unsigned> &ArgRegs,
1961                                  SmallVectorImpl<MVT> &ArgVTs,
1962                                  SmallVectorImpl<ISD::ArgFlagsTy> &ArgFlags,
1963                                  SmallVectorImpl<unsigned> &RegArgs,
1964                                  CallingConv::ID CC,
1965                                  unsigned &NumBytes,
1966                                  bool isVarArg) {
1967  SmallVector<CCValAssign, 16> ArgLocs;
1968  CCState CCInfo(CC, isVarArg, *FuncInfo.MF, TM, ArgLocs, *Context);
1969  CCInfo.AnalyzeCallOperands(ArgVTs, ArgFlags,
1970                             CCAssignFnForCall(CC, false, isVarArg));
1971
1972  // Check that we can handle all of the arguments. If we can't, then bail out
1973  // now before we add code to the MBB.
1974  for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
1975    CCValAssign &VA = ArgLocs[i];
1976    MVT ArgVT = ArgVTs[VA.getValNo()];
1977
1978    // We don't handle NEON/vector parameters yet.
1979    if (ArgVT.isVector() || ArgVT.getSizeInBits() > 64)
1980      return false;
1981
1982    // Now copy/store arg to correct locations.
1983    if (VA.isRegLoc() && !VA.needsCustom()) {
1984      continue;
1985    } else if (VA.needsCustom()) {
1986      // TODO: We need custom lowering for vector (v2f64) args.
1987      if (VA.getLocVT() != MVT::f64 ||
1988          // TODO: Only handle register args for now.
1989          !VA.isRegLoc() || !ArgLocs[++i].isRegLoc())
1990        return false;
1991    } else {
1992      switch (ArgVT.SimpleTy) {
1993      default:
1994        return false;
1995      case MVT::i1:
1996      case MVT::i8:
1997      case MVT::i16:
1998      case MVT::i32:
1999        break;
2000      case MVT::f32:
2001        if (!Subtarget->hasVFP2())
2002          return false;
2003        break;
2004      case MVT::f64:
2005        if (!Subtarget->hasVFP2())
2006          return false;
2007        break;
2008      }
2009    }
2010  }
2011
2012  // At the point, we are able to handle the call's arguments in fast isel.
2013
2014  // Get a count of how many bytes are to be pushed on the stack.
2015  NumBytes = CCInfo.getNextStackOffset();
2016
2017  // Issue CALLSEQ_START
2018  unsigned AdjStackDown = TII.getCallFrameSetupOpcode();
2019  AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
2020                          TII.get(AdjStackDown))
2021                  .addImm(NumBytes));
2022
2023  // Process the args.
2024  for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2025    CCValAssign &VA = ArgLocs[i];
2026    unsigned Arg = ArgRegs[VA.getValNo()];
2027    MVT ArgVT = ArgVTs[VA.getValNo()];
2028
2029    assert((!ArgVT.isVector() && ArgVT.getSizeInBits() <= 64) &&
2030           "We don't handle NEON/vector parameters yet.");
2031
2032    // Handle arg promotion, etc.
2033    switch (VA.getLocInfo()) {
2034      case CCValAssign::Full: break;
2035      case CCValAssign::SExt: {
2036        MVT DestVT = VA.getLocVT();
2037        Arg = ARMEmitIntExt(ArgVT, Arg, DestVT, /*isZExt*/false);
2038        assert (Arg != 0 && "Failed to emit a sext");
2039        ArgVT = DestVT;
2040        break;
2041      }
2042      case CCValAssign::AExt:
2043        // Intentional fall-through.  Handle AExt and ZExt.
2044      case CCValAssign::ZExt: {
2045        MVT DestVT = VA.getLocVT();
2046        Arg = ARMEmitIntExt(ArgVT, Arg, DestVT, /*isZExt*/true);
2047        assert (Arg != 0 && "Failed to emit a zext");
2048        ArgVT = DestVT;
2049        break;
2050      }
2051      case CCValAssign::BCvt: {
2052        unsigned BC = FastEmit_r(ArgVT, VA.getLocVT(), ISD::BITCAST, Arg,
2053                                 /*TODO: Kill=*/false);
2054        assert(BC != 0 && "Failed to emit a bitcast!");
2055        Arg = BC;
2056        ArgVT = VA.getLocVT();
2057        break;
2058      }
2059      default: llvm_unreachable("Unknown arg promotion!");
2060    }
2061
2062    // Now copy/store arg to correct locations.
2063    if (VA.isRegLoc() && !VA.needsCustom()) {
2064      BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(TargetOpcode::COPY),
2065              VA.getLocReg())
2066        .addReg(Arg);
2067      RegArgs.push_back(VA.getLocReg());
2068    } else if (VA.needsCustom()) {
2069      // TODO: We need custom lowering for vector (v2f64) args.
2070      assert(VA.getLocVT() == MVT::f64 &&
2071             "Custom lowering for v2f64 args not available");
2072
2073      CCValAssign &NextVA = ArgLocs[++i];
2074
2075      assert(VA.isRegLoc() && NextVA.isRegLoc() &&
2076             "We only handle register args!");
2077
2078      AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
2079                              TII.get(ARM::VMOVRRD), VA.getLocReg())
2080                      .addReg(NextVA.getLocReg(), RegState::Define)
2081                      .addReg(Arg));
2082      RegArgs.push_back(VA.getLocReg());
2083      RegArgs.push_back(NextVA.getLocReg());
2084    } else {
2085      assert(VA.isMemLoc());
2086      // Need to store on the stack.
2087      Address Addr;
2088      Addr.BaseType = Address::RegBase;
2089      Addr.Base.Reg = ARM::SP;
2090      Addr.Offset = VA.getLocMemOffset();
2091
2092      bool EmitRet = ARMEmitStore(ArgVT, Arg, Addr); (void)EmitRet;
2093      assert(EmitRet && "Could not emit a store for argument!");
2094    }
2095  }
2096
2097  return true;
2098}
2099
2100bool ARMFastISel::FinishCall(MVT RetVT, SmallVectorImpl<unsigned> &UsedRegs,
2101                             const Instruction *I, CallingConv::ID CC,
2102                             unsigned &NumBytes, bool isVarArg) {
2103  // Issue CALLSEQ_END
2104  unsigned AdjStackUp = TII.getCallFrameDestroyOpcode();
2105  AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
2106                          TII.get(AdjStackUp))
2107                  .addImm(NumBytes).addImm(0));
2108
2109  // Now the return value.
2110  if (RetVT != MVT::isVoid) {
2111    SmallVector<CCValAssign, 16> RVLocs;
2112    CCState CCInfo(CC, isVarArg, *FuncInfo.MF, TM, RVLocs, *Context);
2113    CCInfo.AnalyzeCallResult(RetVT, CCAssignFnForCall(CC, true, isVarArg));
2114
2115    // Copy all of the result registers out of their specified physreg.
2116    if (RVLocs.size() == 2 && RetVT == MVT::f64) {
2117      // For this move we copy into two registers and then move into the
2118      // double fp reg we want.
2119      MVT DestVT = RVLocs[0].getValVT();
2120      const TargetRegisterClass* DstRC = TLI.getRegClassFor(DestVT);
2121      unsigned ResultReg = createResultReg(DstRC);
2122      AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
2123                              TII.get(ARM::VMOVDRR), ResultReg)
2124                      .addReg(RVLocs[0].getLocReg())
2125                      .addReg(RVLocs[1].getLocReg()));
2126
2127      UsedRegs.push_back(RVLocs[0].getLocReg());
2128      UsedRegs.push_back(RVLocs[1].getLocReg());
2129
2130      // Finally update the result.
2131      UpdateValueMap(I, ResultReg);
2132    } else {
2133      assert(RVLocs.size() == 1 &&"Can't handle non-double multi-reg retvals!");
2134      MVT CopyVT = RVLocs[0].getValVT();
2135
2136      // Special handling for extended integers.
2137      if (RetVT == MVT::i1 || RetVT == MVT::i8 || RetVT == MVT::i16)
2138        CopyVT = MVT::i32;
2139
2140      const TargetRegisterClass* DstRC = TLI.getRegClassFor(CopyVT);
2141
2142      unsigned ResultReg = createResultReg(DstRC);
2143      BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(TargetOpcode::COPY),
2144              ResultReg).addReg(RVLocs[0].getLocReg());
2145      UsedRegs.push_back(RVLocs[0].getLocReg());
2146
2147      // Finally update the result.
2148      UpdateValueMap(I, ResultReg);
2149    }
2150  }
2151
2152  return true;
2153}
2154
2155bool ARMFastISel::SelectRet(const Instruction *I) {
2156  const ReturnInst *Ret = cast<ReturnInst>(I);
2157  const Function &F = *I->getParent()->getParent();
2158
2159  if (!FuncInfo.CanLowerReturn)
2160    return false;
2161
2162  // Build a list of return value registers.
2163  SmallVector<unsigned, 4> RetRegs;
2164
2165  CallingConv::ID CC = F.getCallingConv();
2166  if (Ret->getNumOperands() > 0) {
2167    SmallVector<ISD::OutputArg, 4> Outs;
2168    GetReturnInfo(F.getReturnType(), F.getAttributes(), Outs, TLI);
2169
2170    // Analyze operands of the call, assigning locations to each operand.
2171    SmallVector<CCValAssign, 16> ValLocs;
2172    CCState CCInfo(CC, F.isVarArg(), *FuncInfo.MF, TM, ValLocs,I->getContext());
2173    CCInfo.AnalyzeReturn(Outs, CCAssignFnForCall(CC, true /* is Ret */,
2174                                                 F.isVarArg()));
2175
2176    const Value *RV = Ret->getOperand(0);
2177    unsigned Reg = getRegForValue(RV);
2178    if (Reg == 0)
2179      return false;
2180
2181    // Only handle a single return value for now.
2182    if (ValLocs.size() != 1)
2183      return false;
2184
2185    CCValAssign &VA = ValLocs[0];
2186
2187    // Don't bother handling odd stuff for now.
2188    if (VA.getLocInfo() != CCValAssign::Full)
2189      return false;
2190    // Only handle register returns for now.
2191    if (!VA.isRegLoc())
2192      return false;
2193
2194    unsigned SrcReg = Reg + VA.getValNo();
2195    EVT RVEVT = TLI.getValueType(RV->getType());
2196    if (!RVEVT.isSimple()) return false;
2197    MVT RVVT = RVEVT.getSimpleVT();
2198    MVT DestVT = VA.getValVT();
2199    // Special handling for extended integers.
2200    if (RVVT != DestVT) {
2201      if (RVVT != MVT::i1 && RVVT != MVT::i8 && RVVT != MVT::i16)
2202        return false;
2203
2204      assert(DestVT == MVT::i32 && "ARM should always ext to i32");
2205
2206      // Perform extension if flagged as either zext or sext.  Otherwise, do
2207      // nothing.
2208      if (Outs[0].Flags.isZExt() || Outs[0].Flags.isSExt()) {
2209        SrcReg = ARMEmitIntExt(RVVT, SrcReg, DestVT, Outs[0].Flags.isZExt());
2210        if (SrcReg == 0) return false;
2211      }
2212    }
2213
2214    // Make the copy.
2215    unsigned DstReg = VA.getLocReg();
2216    const TargetRegisterClass* SrcRC = MRI.getRegClass(SrcReg);
2217    // Avoid a cross-class copy. This is very unlikely.
2218    if (!SrcRC->contains(DstReg))
2219      return false;
2220    BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(TargetOpcode::COPY),
2221            DstReg).addReg(SrcReg);
2222
2223    // Add register to return instruction.
2224    RetRegs.push_back(VA.getLocReg());
2225  }
2226
2227  unsigned RetOpc = isThumb2 ? ARM::tBX_RET : ARM::BX_RET;
2228  MachineInstrBuilder MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
2229                                    TII.get(RetOpc));
2230  AddOptionalDefs(MIB);
2231  for (unsigned i = 0, e = RetRegs.size(); i != e; ++i)
2232    MIB.addReg(RetRegs[i], RegState::Implicit);
2233  return true;
2234}
2235
2236unsigned ARMFastISel::ARMSelectCallOp(bool UseReg) {
2237  if (UseReg)
2238    return isThumb2 ? ARM::tBLXr : ARM::BLX;
2239  else
2240    return isThumb2 ? ARM::tBL : ARM::BL;
2241}
2242
2243unsigned ARMFastISel::getLibcallReg(const Twine &Name) {
2244  // Manually compute the global's type to avoid building it when unnecessary.
2245  Type *GVTy = Type::getInt32PtrTy(*Context, /*AS=*/0);
2246  EVT LCREVT = TLI.getValueType(GVTy);
2247  if (!LCREVT.isSimple()) return 0;
2248
2249  GlobalValue *GV = new GlobalVariable(Type::getInt32Ty(*Context), false,
2250                                       GlobalValue::ExternalLinkage, 0, Name);
2251  assert(GV->getType() == GVTy && "We miscomputed the type for the global!");
2252  return ARMMaterializeGV(GV, LCREVT.getSimpleVT());
2253}
2254
2255// A quick function that will emit a call for a named libcall in F with the
2256// vector of passed arguments for the Instruction in I. We can assume that we
2257// can emit a call for any libcall we can produce. This is an abridged version
2258// of the full call infrastructure since we won't need to worry about things
2259// like computed function pointers or strange arguments at call sites.
2260// TODO: Try to unify this and the normal call bits for ARM, then try to unify
2261// with X86.
2262bool ARMFastISel::ARMEmitLibcall(const Instruction *I, RTLIB::Libcall Call) {
2263  CallingConv::ID CC = TLI.getLibcallCallingConv(Call);
2264
2265  // Handle *simple* calls for now.
2266  Type *RetTy = I->getType();
2267  MVT RetVT;
2268  if (RetTy->isVoidTy())
2269    RetVT = MVT::isVoid;
2270  else if (!isTypeLegal(RetTy, RetVT))
2271    return false;
2272
2273  // Can't handle non-double multi-reg retvals.
2274  if (RetVT != MVT::isVoid && RetVT != MVT::i32) {
2275    SmallVector<CCValAssign, 16> RVLocs;
2276    CCState CCInfo(CC, false, *FuncInfo.MF, TM, RVLocs, *Context);
2277    CCInfo.AnalyzeCallResult(RetVT, CCAssignFnForCall(CC, true, false));
2278    if (RVLocs.size() >= 2 && RetVT != MVT::f64)
2279      return false;
2280  }
2281
2282  // Set up the argument vectors.
2283  SmallVector<Value*, 8> Args;
2284  SmallVector<unsigned, 8> ArgRegs;
2285  SmallVector<MVT, 8> ArgVTs;
2286  SmallVector<ISD::ArgFlagsTy, 8> ArgFlags;
2287  Args.reserve(I->getNumOperands());
2288  ArgRegs.reserve(I->getNumOperands());
2289  ArgVTs.reserve(I->getNumOperands());
2290  ArgFlags.reserve(I->getNumOperands());
2291  for (unsigned i = 0; i < I->getNumOperands(); ++i) {
2292    Value *Op = I->getOperand(i);
2293    unsigned Arg = getRegForValue(Op);
2294    if (Arg == 0) return false;
2295
2296    Type *ArgTy = Op->getType();
2297    MVT ArgVT;
2298    if (!isTypeLegal(ArgTy, ArgVT)) return false;
2299
2300    ISD::ArgFlagsTy Flags;
2301    unsigned OriginalAlignment = TD.getABITypeAlignment(ArgTy);
2302    Flags.setOrigAlign(OriginalAlignment);
2303
2304    Args.push_back(Op);
2305    ArgRegs.push_back(Arg);
2306    ArgVTs.push_back(ArgVT);
2307    ArgFlags.push_back(Flags);
2308  }
2309
2310  // Handle the arguments now that we've gotten them.
2311  SmallVector<unsigned, 4> RegArgs;
2312  unsigned NumBytes;
2313  if (!ProcessCallArgs(Args, ArgRegs, ArgVTs, ArgFlags,
2314                       RegArgs, CC, NumBytes, false))
2315    return false;
2316
2317  unsigned CalleeReg = 0;
2318  if (EnableARMLongCalls) {
2319    CalleeReg = getLibcallReg(TLI.getLibcallName(Call));
2320    if (CalleeReg == 0) return false;
2321  }
2322
2323  // Issue the call.
2324  unsigned CallOpc = ARMSelectCallOp(EnableARMLongCalls);
2325  MachineInstrBuilder MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt,
2326                                    DL, TII.get(CallOpc));
2327  // BL / BLX don't take a predicate, but tBL / tBLX do.
2328  if (isThumb2)
2329    AddDefaultPred(MIB);
2330  if (EnableARMLongCalls)
2331    MIB.addReg(CalleeReg);
2332  else
2333    MIB.addExternalSymbol(TLI.getLibcallName(Call));
2334
2335  // Add implicit physical register uses to the call.
2336  for (unsigned i = 0, e = RegArgs.size(); i != e; ++i)
2337    MIB.addReg(RegArgs[i], RegState::Implicit);
2338
2339  // Add a register mask with the call-preserved registers.
2340  // Proper defs for return values will be added by setPhysRegsDeadExcept().
2341  MIB.addRegMask(TRI.getCallPreservedMask(CC));
2342
2343  // Finish off the call including any return values.
2344  SmallVector<unsigned, 4> UsedRegs;
2345  if (!FinishCall(RetVT, UsedRegs, I, CC, NumBytes, false)) return false;
2346
2347  // Set all unused physreg defs as dead.
2348  static_cast<MachineInstr *>(MIB)->setPhysRegsDeadExcept(UsedRegs, TRI);
2349
2350  return true;
2351}
2352
2353bool ARMFastISel::SelectCall(const Instruction *I,
2354                             const char *IntrMemName = 0) {
2355  const CallInst *CI = cast<CallInst>(I);
2356  const Value *Callee = CI->getCalledValue();
2357
2358  // Can't handle inline asm.
2359  if (isa<InlineAsm>(Callee)) return false;
2360
2361  // Allow SelectionDAG isel to handle tail calls.
2362  if (CI->isTailCall()) return false;
2363
2364  // Check the calling convention.
2365  ImmutableCallSite CS(CI);
2366  CallingConv::ID CC = CS.getCallingConv();
2367
2368  // TODO: Avoid some calling conventions?
2369
2370  PointerType *PT = cast<PointerType>(CS.getCalledValue()->getType());
2371  FunctionType *FTy = cast<FunctionType>(PT->getElementType());
2372  bool isVarArg = FTy->isVarArg();
2373
2374  // Handle *simple* calls for now.
2375  Type *RetTy = I->getType();
2376  MVT RetVT;
2377  if (RetTy->isVoidTy())
2378    RetVT = MVT::isVoid;
2379  else if (!isTypeLegal(RetTy, RetVT) && RetVT != MVT::i16 &&
2380           RetVT != MVT::i8  && RetVT != MVT::i1)
2381    return false;
2382
2383  // Can't handle non-double multi-reg retvals.
2384  if (RetVT != MVT::isVoid && RetVT != MVT::i1 && RetVT != MVT::i8 &&
2385      RetVT != MVT::i16 && RetVT != MVT::i32) {
2386    SmallVector<CCValAssign, 16> RVLocs;
2387    CCState CCInfo(CC, isVarArg, *FuncInfo.MF, TM, RVLocs, *Context);
2388    CCInfo.AnalyzeCallResult(RetVT, CCAssignFnForCall(CC, true, isVarArg));
2389    if (RVLocs.size() >= 2 && RetVT != MVT::f64)
2390      return false;
2391  }
2392
2393  // Set up the argument vectors.
2394  SmallVector<Value*, 8> Args;
2395  SmallVector<unsigned, 8> ArgRegs;
2396  SmallVector<MVT, 8> ArgVTs;
2397  SmallVector<ISD::ArgFlagsTy, 8> ArgFlags;
2398  unsigned arg_size = CS.arg_size();
2399  Args.reserve(arg_size);
2400  ArgRegs.reserve(arg_size);
2401  ArgVTs.reserve(arg_size);
2402  ArgFlags.reserve(arg_size);
2403  for (ImmutableCallSite::arg_iterator i = CS.arg_begin(), e = CS.arg_end();
2404       i != e; ++i) {
2405    // If we're lowering a memory intrinsic instead of a regular call, skip the
2406    // last two arguments, which shouldn't be passed to the underlying function.
2407    if (IntrMemName && e-i <= 2)
2408      break;
2409
2410    ISD::ArgFlagsTy Flags;
2411    unsigned AttrInd = i - CS.arg_begin() + 1;
2412    if (CS.paramHasAttr(AttrInd, Attribute::SExt))
2413      Flags.setSExt();
2414    if (CS.paramHasAttr(AttrInd, Attribute::ZExt))
2415      Flags.setZExt();
2416
2417    // FIXME: Only handle *easy* calls for now.
2418    if (CS.paramHasAttr(AttrInd, Attribute::InReg) ||
2419        CS.paramHasAttr(AttrInd, Attribute::StructRet) ||
2420        CS.paramHasAttr(AttrInd, Attribute::Nest) ||
2421        CS.paramHasAttr(AttrInd, Attribute::ByVal))
2422      return false;
2423
2424    Type *ArgTy = (*i)->getType();
2425    MVT ArgVT;
2426    if (!isTypeLegal(ArgTy, ArgVT) && ArgVT != MVT::i16 && ArgVT != MVT::i8 &&
2427        ArgVT != MVT::i1)
2428      return false;
2429
2430    unsigned Arg = getRegForValue(*i);
2431    if (Arg == 0)
2432      return false;
2433
2434    unsigned OriginalAlignment = TD.getABITypeAlignment(ArgTy);
2435    Flags.setOrigAlign(OriginalAlignment);
2436
2437    Args.push_back(*i);
2438    ArgRegs.push_back(Arg);
2439    ArgVTs.push_back(ArgVT);
2440    ArgFlags.push_back(Flags);
2441  }
2442
2443  // Handle the arguments now that we've gotten them.
2444  SmallVector<unsigned, 4> RegArgs;
2445  unsigned NumBytes;
2446  if (!ProcessCallArgs(Args, ArgRegs, ArgVTs, ArgFlags,
2447                       RegArgs, CC, NumBytes, isVarArg))
2448    return false;
2449
2450  bool UseReg = false;
2451  const GlobalValue *GV = dyn_cast<GlobalValue>(Callee);
2452  if (!GV || EnableARMLongCalls) UseReg = true;
2453
2454  unsigned CalleeReg = 0;
2455  if (UseReg) {
2456    if (IntrMemName)
2457      CalleeReg = getLibcallReg(IntrMemName);
2458    else
2459      CalleeReg = getRegForValue(Callee);
2460
2461    if (CalleeReg == 0) return false;
2462  }
2463
2464  // Issue the call.
2465  unsigned CallOpc = ARMSelectCallOp(UseReg);
2466  MachineInstrBuilder MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt,
2467                                    DL, TII.get(CallOpc));
2468
2469  unsigned char OpFlags = 0;
2470
2471  // Add MO_PLT for global address or external symbol in the PIC relocation
2472  // model.
2473  if (Subtarget->isTargetELF() && TM.getRelocationModel() == Reloc::PIC_)
2474    OpFlags = ARMII::MO_PLT;
2475
2476  // ARM calls don't take a predicate, but tBL / tBLX do.
2477  if(isThumb2)
2478    AddDefaultPred(MIB);
2479  if (UseReg)
2480    MIB.addReg(CalleeReg);
2481  else if (!IntrMemName)
2482    MIB.addGlobalAddress(GV, 0, OpFlags);
2483  else
2484    MIB.addExternalSymbol(IntrMemName, OpFlags);
2485
2486  // Add implicit physical register uses to the call.
2487  for (unsigned i = 0, e = RegArgs.size(); i != e; ++i)
2488    MIB.addReg(RegArgs[i], RegState::Implicit);
2489
2490  // Add a register mask with the call-preserved registers.
2491  // Proper defs for return values will be added by setPhysRegsDeadExcept().
2492  MIB.addRegMask(TRI.getCallPreservedMask(CC));
2493
2494  // Finish off the call including any return values.
2495  SmallVector<unsigned, 4> UsedRegs;
2496  if (!FinishCall(RetVT, UsedRegs, I, CC, NumBytes, isVarArg))
2497    return false;
2498
2499  // Set all unused physreg defs as dead.
2500  static_cast<MachineInstr *>(MIB)->setPhysRegsDeadExcept(UsedRegs, TRI);
2501
2502  return true;
2503}
2504
2505bool ARMFastISel::ARMIsMemCpySmall(uint64_t Len) {
2506  return Len <= 16;
2507}
2508
2509bool ARMFastISel::ARMTryEmitSmallMemCpy(Address Dest, Address Src,
2510                                        uint64_t Len, unsigned Alignment) {
2511  // Make sure we don't bloat code by inlining very large memcpy's.
2512  if (!ARMIsMemCpySmall(Len))
2513    return false;
2514
2515  while (Len) {
2516    MVT VT;
2517    if (!Alignment || Alignment >= 4) {
2518      if (Len >= 4)
2519        VT = MVT::i32;
2520      else if (Len >= 2)
2521        VT = MVT::i16;
2522      else {
2523        assert (Len == 1 && "Expected a length of 1!");
2524        VT = MVT::i8;
2525      }
2526    } else {
2527      // Bound based on alignment.
2528      if (Len >= 2 && Alignment == 2)
2529        VT = MVT::i16;
2530      else {
2531        VT = MVT::i8;
2532      }
2533    }
2534
2535    bool RV;
2536    unsigned ResultReg;
2537    RV = ARMEmitLoad(VT, ResultReg, Src);
2538    assert (RV == true && "Should be able to handle this load.");
2539    RV = ARMEmitStore(VT, ResultReg, Dest);
2540    assert (RV == true && "Should be able to handle this store.");
2541    (void)RV;
2542
2543    unsigned Size = VT.getSizeInBits()/8;
2544    Len -= Size;
2545    Dest.Offset += Size;
2546    Src.Offset += Size;
2547  }
2548
2549  return true;
2550}
2551
2552bool ARMFastISel::SelectIntrinsicCall(const IntrinsicInst &I) {
2553  // FIXME: Handle more intrinsics.
2554  switch (I.getIntrinsicID()) {
2555  default: return false;
2556  case Intrinsic::frameaddress: {
2557    MachineFrameInfo *MFI = FuncInfo.MF->getFrameInfo();
2558    MFI->setFrameAddressIsTaken(true);
2559
2560    unsigned LdrOpc;
2561    const TargetRegisterClass *RC;
2562    if (isThumb2) {
2563      LdrOpc =  ARM::t2LDRi12;
2564      RC = (const TargetRegisterClass*)&ARM::tGPRRegClass;
2565    } else {
2566      LdrOpc =  ARM::LDRi12;
2567      RC = (const TargetRegisterClass*)&ARM::GPRRegClass;
2568    }
2569
2570    const ARMBaseRegisterInfo *RegInfo =
2571          static_cast<const ARMBaseRegisterInfo*>(TM.getRegisterInfo());
2572    unsigned FramePtr = RegInfo->getFrameRegister(*(FuncInfo.MF));
2573    unsigned SrcReg = FramePtr;
2574
2575    // Recursively load frame address
2576    // ldr r0 [fp]
2577    // ldr r0 [r0]
2578    // ldr r0 [r0]
2579    // ...
2580    unsigned DestReg;
2581    unsigned Depth = cast<ConstantInt>(I.getOperand(0))->getZExtValue();
2582    while (Depth--) {
2583      DestReg = createResultReg(RC);
2584      AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
2585                              TII.get(LdrOpc), DestReg)
2586                      .addReg(SrcReg).addImm(0));
2587      SrcReg = DestReg;
2588    }
2589    UpdateValueMap(&I, SrcReg);
2590    return true;
2591  }
2592  case Intrinsic::memcpy:
2593  case Intrinsic::memmove: {
2594    const MemTransferInst &MTI = cast<MemTransferInst>(I);
2595    // Don't handle volatile.
2596    if (MTI.isVolatile())
2597      return false;
2598
2599    // Disable inlining for memmove before calls to ComputeAddress.  Otherwise,
2600    // we would emit dead code because we don't currently handle memmoves.
2601    bool isMemCpy = (I.getIntrinsicID() == Intrinsic::memcpy);
2602    if (isa<ConstantInt>(MTI.getLength()) && isMemCpy) {
2603      // Small memcpy's are common enough that we want to do them without a call
2604      // if possible.
2605      uint64_t Len = cast<ConstantInt>(MTI.getLength())->getZExtValue();
2606      if (ARMIsMemCpySmall(Len)) {
2607        Address Dest, Src;
2608        if (!ARMComputeAddress(MTI.getRawDest(), Dest) ||
2609            !ARMComputeAddress(MTI.getRawSource(), Src))
2610          return false;
2611        unsigned Alignment = MTI.getAlignment();
2612        if (ARMTryEmitSmallMemCpy(Dest, Src, Len, Alignment))
2613          return true;
2614      }
2615    }
2616
2617    if (!MTI.getLength()->getType()->isIntegerTy(32))
2618      return false;
2619
2620    if (MTI.getSourceAddressSpace() > 255 || MTI.getDestAddressSpace() > 255)
2621      return false;
2622
2623    const char *IntrMemName = isa<MemCpyInst>(I) ? "memcpy" : "memmove";
2624    return SelectCall(&I, IntrMemName);
2625  }
2626  case Intrinsic::memset: {
2627    const MemSetInst &MSI = cast<MemSetInst>(I);
2628    // Don't handle volatile.
2629    if (MSI.isVolatile())
2630      return false;
2631
2632    if (!MSI.getLength()->getType()->isIntegerTy(32))
2633      return false;
2634
2635    if (MSI.getDestAddressSpace() > 255)
2636      return false;
2637
2638    return SelectCall(&I, "memset");
2639  }
2640  case Intrinsic::trap: {
2641    BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(
2642      Subtarget->useNaClTrap() ? ARM::TRAPNaCl : ARM::TRAP));
2643    return true;
2644  }
2645  }
2646}
2647
2648bool ARMFastISel::SelectTrunc(const Instruction *I) {
2649  // The high bits for a type smaller than the register size are assumed to be
2650  // undefined.
2651  Value *Op = I->getOperand(0);
2652
2653  EVT SrcVT, DestVT;
2654  SrcVT = TLI.getValueType(Op->getType(), true);
2655  DestVT = TLI.getValueType(I->getType(), true);
2656
2657  if (SrcVT != MVT::i32 && SrcVT != MVT::i16 && SrcVT != MVT::i8)
2658    return false;
2659  if (DestVT != MVT::i16 && DestVT != MVT::i8 && DestVT != MVT::i1)
2660    return false;
2661
2662  unsigned SrcReg = getRegForValue(Op);
2663  if (!SrcReg) return false;
2664
2665  // Because the high bits are undefined, a truncate doesn't generate
2666  // any code.
2667  UpdateValueMap(I, SrcReg);
2668  return true;
2669}
2670
2671unsigned ARMFastISel::ARMEmitIntExt(MVT SrcVT, unsigned SrcReg, MVT DestVT,
2672                                    bool isZExt) {
2673  if (DestVT != MVT::i32 && DestVT != MVT::i16 && DestVT != MVT::i8)
2674    return 0;
2675  if (SrcVT != MVT::i16 && SrcVT != MVT::i8 && SrcVT != MVT::i1)
2676    return 0;
2677
2678  // Table of which combinations can be emitted as a single instruction,
2679  // and which will require two.
2680  static const uint8_t isSingleInstrTbl[3][2][2][2] = {
2681    //            ARM                     Thumb
2682    //           !hasV6Ops  hasV6Ops     !hasV6Ops  hasV6Ops
2683    //    ext:     s  z      s  z          s  z      s  z
2684    /*  1 */ { { { 0, 1 }, { 0, 1 } }, { { 0, 0 }, { 0, 1 } } },
2685    /*  8 */ { { { 0, 1 }, { 1, 1 } }, { { 0, 0 }, { 1, 1 } } },
2686    /* 16 */ { { { 0, 0 }, { 1, 1 } }, { { 0, 0 }, { 1, 1 } } }
2687  };
2688
2689  // Target registers for:
2690  //  - For ARM can never be PC.
2691  //  - For 16-bit Thumb are restricted to lower 8 registers.
2692  //  - For 32-bit Thumb are restricted to non-SP and non-PC.
2693  static const TargetRegisterClass *RCTbl[2][2] = {
2694    // Instructions: Two                     Single
2695    /* ARM      */ { &ARM::GPRnopcRegClass, &ARM::GPRnopcRegClass },
2696    /* Thumb    */ { &ARM::tGPRRegClass,    &ARM::rGPRRegClass    }
2697  };
2698
2699  // Table governing the instruction(s) to be emitted.
2700  static const struct InstructionTable {
2701    uint32_t Opc   : 16;
2702    uint32_t hasS  :  1; // Some instructions have an S bit, always set it to 0.
2703    uint32_t Shift :  7; // For shift operand addressing mode, used by MOVsi.
2704    uint32_t Imm   :  8; // All instructions have either a shift or a mask.
2705  } IT[2][2][3][2] = {
2706    { // Two instructions (first is left shift, second is in this table).
2707      { // ARM                Opc           S  Shift             Imm
2708        /*  1 bit sext */ { { ARM::MOVsi  , 1, ARM_AM::asr     ,  31 },
2709        /*  1 bit zext */   { ARM::MOVsi  , 1, ARM_AM::lsr     ,  31 } },
2710        /*  8 bit sext */ { { ARM::MOVsi  , 1, ARM_AM::asr     ,  24 },
2711        /*  8 bit zext */   { ARM::MOVsi  , 1, ARM_AM::lsr     ,  24 } },
2712        /* 16 bit sext */ { { ARM::MOVsi  , 1, ARM_AM::asr     ,  16 },
2713        /* 16 bit zext */   { ARM::MOVsi  , 1, ARM_AM::lsr     ,  16 } }
2714      },
2715      { // Thumb              Opc           S  Shift             Imm
2716        /*  1 bit sext */ { { ARM::tASRri , 0, ARM_AM::no_shift,  31 },
2717        /*  1 bit zext */   { ARM::tLSRri , 0, ARM_AM::no_shift,  31 } },
2718        /*  8 bit sext */ { { ARM::tASRri , 0, ARM_AM::no_shift,  24 },
2719        /*  8 bit zext */   { ARM::tLSRri , 0, ARM_AM::no_shift,  24 } },
2720        /* 16 bit sext */ { { ARM::tASRri , 0, ARM_AM::no_shift,  16 },
2721        /* 16 bit zext */   { ARM::tLSRri , 0, ARM_AM::no_shift,  16 } }
2722      }
2723    },
2724    { // Single instruction.
2725      { // ARM                Opc           S  Shift             Imm
2726        /*  1 bit sext */ { { ARM::KILL   , 0, ARM_AM::no_shift,   0 },
2727        /*  1 bit zext */   { ARM::ANDri  , 1, ARM_AM::no_shift,   1 } },
2728        /*  8 bit sext */ { { ARM::SXTB   , 0, ARM_AM::no_shift,   0 },
2729        /*  8 bit zext */   { ARM::ANDri  , 1, ARM_AM::no_shift, 255 } },
2730        /* 16 bit sext */ { { ARM::SXTH   , 0, ARM_AM::no_shift,   0 },
2731        /* 16 bit zext */   { ARM::UXTH   , 0, ARM_AM::no_shift,   0 } }
2732      },
2733      { // Thumb              Opc           S  Shift             Imm
2734        /*  1 bit sext */ { { ARM::KILL   , 0, ARM_AM::no_shift,   0 },
2735        /*  1 bit zext */   { ARM::t2ANDri, 1, ARM_AM::no_shift,   1 } },
2736        /*  8 bit sext */ { { ARM::t2SXTB , 0, ARM_AM::no_shift,   0 },
2737        /*  8 bit zext */   { ARM::t2ANDri, 1, ARM_AM::no_shift, 255 } },
2738        /* 16 bit sext */ { { ARM::t2SXTH , 0, ARM_AM::no_shift,   0 },
2739        /* 16 bit zext */   { ARM::t2UXTH , 0, ARM_AM::no_shift,   0 } }
2740      }
2741    }
2742  };
2743
2744  unsigned SrcBits = SrcVT.getSizeInBits();
2745  unsigned DestBits = DestVT.getSizeInBits();
2746  (void) DestBits;
2747  assert((SrcBits < DestBits) && "can only extend to larger types");
2748  assert((DestBits == 32 || DestBits == 16 || DestBits == 8) &&
2749         "other sizes unimplemented");
2750  assert((SrcBits == 16 || SrcBits == 8 || SrcBits == 1) &&
2751         "other sizes unimplemented");
2752
2753  bool hasV6Ops = Subtarget->hasV6Ops();
2754  unsigned Bitness = SrcBits / 8;  // {1,8,16}=>{0,1,2}
2755  assert((Bitness < 3) && "sanity-check table bounds");
2756
2757  bool isSingleInstr = isSingleInstrTbl[Bitness][isThumb2][hasV6Ops][isZExt];
2758  const TargetRegisterClass *RC = RCTbl[isThumb2][isSingleInstr];
2759  const InstructionTable *ITP = &IT[isSingleInstr][isThumb2][Bitness][isZExt];
2760  unsigned Opc = ITP->Opc;
2761  assert(ARM::KILL != Opc && "Invalid table entry");
2762  unsigned hasS = ITP->hasS;
2763  ARM_AM::ShiftOpc Shift = (ARM_AM::ShiftOpc) ITP->Shift;
2764  assert(((Shift == ARM_AM::no_shift) == (Opc != ARM::MOVsi)) &&
2765         "only MOVsi has shift operand addressing mode");
2766  unsigned Imm = ITP->Imm;
2767
2768  // 16-bit Thumb instructions always set CPSR (unless they're in an IT block).
2769  bool setsCPSR = &ARM::tGPRRegClass == RC;
2770  unsigned LSLOpc = isThumb2 ? ARM::tLSLri : ARM::MOVsi;
2771  unsigned ResultReg;
2772  // MOVsi encodes shift and immediate in shift operand addressing mode.
2773  // The following condition has the same value when emitting two
2774  // instruction sequences: both are shifts.
2775  bool ImmIsSO = (Shift != ARM_AM::no_shift);
2776
2777  // Either one or two instructions are emitted.
2778  // They're always of the form:
2779  //   dst = in OP imm
2780  // CPSR is set only by 16-bit Thumb instructions.
2781  // Predicate, if any, is AL.
2782  // S bit, if available, is always 0.
2783  // When two are emitted the first's result will feed as the second's input,
2784  // that value is then dead.
2785  unsigned NumInstrsEmitted = isSingleInstr ? 1 : 2;
2786  for (unsigned Instr = 0; Instr != NumInstrsEmitted; ++Instr) {
2787    ResultReg = createResultReg(RC);
2788    bool isLsl = (0 == Instr) && !isSingleInstr;
2789    unsigned Opcode = isLsl ? LSLOpc : Opc;
2790    ARM_AM::ShiftOpc ShiftAM = isLsl ? ARM_AM::lsl : Shift;
2791    unsigned ImmEnc = ImmIsSO ? ARM_AM::getSORegOpc(ShiftAM, Imm) : Imm;
2792    bool isKill = 1 == Instr;
2793    MachineInstrBuilder MIB = BuildMI(
2794        *FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(Opcode), ResultReg);
2795    if (setsCPSR)
2796      MIB.addReg(ARM::CPSR, RegState::Define);
2797    SrcReg = constrainOperandRegClass(TII.get(Opcode), SrcReg, 1 + setsCPSR);
2798    AddDefaultPred(MIB.addReg(SrcReg, isKill * RegState::Kill).addImm(ImmEnc));
2799    if (hasS)
2800      AddDefaultCC(MIB);
2801    // Second instruction consumes the first's result.
2802    SrcReg = ResultReg;
2803  }
2804
2805  return ResultReg;
2806}
2807
2808bool ARMFastISel::SelectIntExt(const Instruction *I) {
2809  // On ARM, in general, integer casts don't involve legal types; this code
2810  // handles promotable integers.
2811  Type *DestTy = I->getType();
2812  Value *Src = I->getOperand(0);
2813  Type *SrcTy = Src->getType();
2814
2815  bool isZExt = isa<ZExtInst>(I);
2816  unsigned SrcReg = getRegForValue(Src);
2817  if (!SrcReg) return false;
2818
2819  EVT SrcEVT, DestEVT;
2820  SrcEVT = TLI.getValueType(SrcTy, true);
2821  DestEVT = TLI.getValueType(DestTy, true);
2822  if (!SrcEVT.isSimple()) return false;
2823  if (!DestEVT.isSimple()) return false;
2824
2825  MVT SrcVT = SrcEVT.getSimpleVT();
2826  MVT DestVT = DestEVT.getSimpleVT();
2827  unsigned ResultReg = ARMEmitIntExt(SrcVT, SrcReg, DestVT, isZExt);
2828  if (ResultReg == 0) return false;
2829  UpdateValueMap(I, ResultReg);
2830  return true;
2831}
2832
2833bool ARMFastISel::SelectShift(const Instruction *I,
2834                              ARM_AM::ShiftOpc ShiftTy) {
2835  // We handle thumb2 mode by target independent selector
2836  // or SelectionDAG ISel.
2837  if (isThumb2)
2838    return false;
2839
2840  // Only handle i32 now.
2841  EVT DestVT = TLI.getValueType(I->getType(), true);
2842  if (DestVT != MVT::i32)
2843    return false;
2844
2845  unsigned Opc = ARM::MOVsr;
2846  unsigned ShiftImm;
2847  Value *Src2Value = I->getOperand(1);
2848  if (const ConstantInt *CI = dyn_cast<ConstantInt>(Src2Value)) {
2849    ShiftImm = CI->getZExtValue();
2850
2851    // Fall back to selection DAG isel if the shift amount
2852    // is zero or greater than the width of the value type.
2853    if (ShiftImm == 0 || ShiftImm >=32)
2854      return false;
2855
2856    Opc = ARM::MOVsi;
2857  }
2858
2859  Value *Src1Value = I->getOperand(0);
2860  unsigned Reg1 = getRegForValue(Src1Value);
2861  if (Reg1 == 0) return false;
2862
2863  unsigned Reg2 = 0;
2864  if (Opc == ARM::MOVsr) {
2865    Reg2 = getRegForValue(Src2Value);
2866    if (Reg2 == 0) return false;
2867  }
2868
2869  unsigned ResultReg = createResultReg(&ARM::GPRnopcRegClass);
2870  if(ResultReg == 0) return false;
2871
2872  MachineInstrBuilder MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
2873                                    TII.get(Opc), ResultReg)
2874                            .addReg(Reg1);
2875
2876  if (Opc == ARM::MOVsi)
2877    MIB.addImm(ARM_AM::getSORegOpc(ShiftTy, ShiftImm));
2878  else if (Opc == ARM::MOVsr) {
2879    MIB.addReg(Reg2);
2880    MIB.addImm(ARM_AM::getSORegOpc(ShiftTy, 0));
2881  }
2882
2883  AddOptionalDefs(MIB);
2884  UpdateValueMap(I, ResultReg);
2885  return true;
2886}
2887
2888// TODO: SoftFP support.
2889bool ARMFastISel::TargetSelectInstruction(const Instruction *I) {
2890
2891  switch (I->getOpcode()) {
2892    case Instruction::Load:
2893      return SelectLoad(I);
2894    case Instruction::Store:
2895      return SelectStore(I);
2896    case Instruction::Br:
2897      return SelectBranch(I);
2898    case Instruction::IndirectBr:
2899      return SelectIndirectBr(I);
2900    case Instruction::ICmp:
2901    case Instruction::FCmp:
2902      return SelectCmp(I);
2903    case Instruction::FPExt:
2904      return SelectFPExt(I);
2905    case Instruction::FPTrunc:
2906      return SelectFPTrunc(I);
2907    case Instruction::SIToFP:
2908      return SelectIToFP(I, /*isSigned*/ true);
2909    case Instruction::UIToFP:
2910      return SelectIToFP(I, /*isSigned*/ false);
2911    case Instruction::FPToSI:
2912      return SelectFPToI(I, /*isSigned*/ true);
2913    case Instruction::FPToUI:
2914      return SelectFPToI(I, /*isSigned*/ false);
2915    case Instruction::Add:
2916      return SelectBinaryIntOp(I, ISD::ADD);
2917    case Instruction::Or:
2918      return SelectBinaryIntOp(I, ISD::OR);
2919    case Instruction::Sub:
2920      return SelectBinaryIntOp(I, ISD::SUB);
2921    case Instruction::FAdd:
2922      return SelectBinaryFPOp(I, ISD::FADD);
2923    case Instruction::FSub:
2924      return SelectBinaryFPOp(I, ISD::FSUB);
2925    case Instruction::FMul:
2926      return SelectBinaryFPOp(I, ISD::FMUL);
2927    case Instruction::SDiv:
2928      return SelectDiv(I, /*isSigned*/ true);
2929    case Instruction::UDiv:
2930      return SelectDiv(I, /*isSigned*/ false);
2931    case Instruction::SRem:
2932      return SelectRem(I, /*isSigned*/ true);
2933    case Instruction::URem:
2934      return SelectRem(I, /*isSigned*/ false);
2935    case Instruction::Call:
2936      if (const IntrinsicInst *II = dyn_cast<IntrinsicInst>(I))
2937        return SelectIntrinsicCall(*II);
2938      return SelectCall(I);
2939    case Instruction::Select:
2940      return SelectSelect(I);
2941    case Instruction::Ret:
2942      return SelectRet(I);
2943    case Instruction::Trunc:
2944      return SelectTrunc(I);
2945    case Instruction::ZExt:
2946    case Instruction::SExt:
2947      return SelectIntExt(I);
2948    case Instruction::Shl:
2949      return SelectShift(I, ARM_AM::lsl);
2950    case Instruction::LShr:
2951      return SelectShift(I, ARM_AM::lsr);
2952    case Instruction::AShr:
2953      return SelectShift(I, ARM_AM::asr);
2954    default: break;
2955  }
2956  return false;
2957}
2958
2959namespace {
2960// This table describes sign- and zero-extend instructions which can be
2961// folded into a preceding load. All of these extends have an immediate
2962// (sometimes a mask and sometimes a shift) that's applied after
2963// extension.
2964const struct FoldableLoadExtendsStruct {
2965  uint16_t Opc[2];  // ARM, Thumb.
2966  uint8_t ExpectedImm;
2967  uint8_t isZExt     : 1;
2968  uint8_t ExpectedVT : 7;
2969} FoldableLoadExtends[] = {
2970  { { ARM::SXTH,  ARM::t2SXTH  },   0, 0, MVT::i16 },
2971  { { ARM::UXTH,  ARM::t2UXTH  },   0, 1, MVT::i16 },
2972  { { ARM::ANDri, ARM::t2ANDri }, 255, 1, MVT::i8  },
2973  { { ARM::SXTB,  ARM::t2SXTB  },   0, 0, MVT::i8  },
2974  { { ARM::UXTB,  ARM::t2UXTB  },   0, 1, MVT::i8  }
2975};
2976}
2977
2978/// \brief The specified machine instr operand is a vreg, and that
2979/// vreg is being provided by the specified load instruction.  If possible,
2980/// try to fold the load as an operand to the instruction, returning true if
2981/// successful.
2982bool ARMFastISel::tryToFoldLoadIntoMI(MachineInstr *MI, unsigned OpNo,
2983                                      const LoadInst *LI) {
2984  // Verify we have a legal type before going any further.
2985  MVT VT;
2986  if (!isLoadTypeLegal(LI->getType(), VT))
2987    return false;
2988
2989  // Combine load followed by zero- or sign-extend.
2990  // ldrb r1, [r0]       ldrb r1, [r0]
2991  // uxtb r2, r1     =>
2992  // mov  r3, r2         mov  r3, r1
2993  if (MI->getNumOperands() < 3 || !MI->getOperand(2).isImm())
2994    return false;
2995  const uint64_t Imm = MI->getOperand(2).getImm();
2996
2997  bool Found = false;
2998  bool isZExt;
2999  for (unsigned i = 0, e = array_lengthof(FoldableLoadExtends);
3000       i != e; ++i) {
3001    if (FoldableLoadExtends[i].Opc[isThumb2] == MI->getOpcode() &&
3002        (uint64_t)FoldableLoadExtends[i].ExpectedImm == Imm &&
3003        MVT((MVT::SimpleValueType)FoldableLoadExtends[i].ExpectedVT) == VT) {
3004      Found = true;
3005      isZExt = FoldableLoadExtends[i].isZExt;
3006    }
3007  }
3008  if (!Found) return false;
3009
3010  // See if we can handle this address.
3011  Address Addr;
3012  if (!ARMComputeAddress(LI->getOperand(0), Addr)) return false;
3013
3014  unsigned ResultReg = MI->getOperand(0).getReg();
3015  if (!ARMEmitLoad(VT, ResultReg, Addr, LI->getAlignment(), isZExt, false))
3016    return false;
3017  MI->eraseFromParent();
3018  return true;
3019}
3020
3021unsigned ARMFastISel::ARMLowerPICELF(const GlobalValue *GV,
3022                                     unsigned Align, MVT VT) {
3023  bool UseGOTOFF = GV->hasLocalLinkage() || GV->hasHiddenVisibility();
3024  ARMConstantPoolConstant *CPV =
3025    ARMConstantPoolConstant::Create(GV, UseGOTOFF ? ARMCP::GOTOFF : ARMCP::GOT);
3026  unsigned Idx = MCP.getConstantPoolIndex(CPV, Align);
3027
3028  unsigned Opc;
3029  unsigned DestReg1 = createResultReg(TLI.getRegClassFor(VT));
3030  // Load value.
3031  if (isThumb2) {
3032    DestReg1 = constrainOperandRegClass(TII.get(ARM::t2LDRpci), DestReg1, 0);
3033    AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
3034                            TII.get(ARM::t2LDRpci), DestReg1)
3035                    .addConstantPoolIndex(Idx));
3036    Opc = UseGOTOFF ? ARM::t2ADDrr : ARM::t2LDRs;
3037  } else {
3038    // The extra immediate is for addrmode2.
3039    DestReg1 = constrainOperandRegClass(TII.get(ARM::LDRcp), DestReg1, 0);
3040    AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt,
3041                            DL, TII.get(ARM::LDRcp), DestReg1)
3042                    .addConstantPoolIndex(Idx).addImm(0));
3043    Opc = UseGOTOFF ? ARM::ADDrr : ARM::LDRrs;
3044  }
3045
3046  unsigned GlobalBaseReg = AFI->getGlobalBaseReg();
3047  if (GlobalBaseReg == 0) {
3048    GlobalBaseReg = MRI.createVirtualRegister(TLI.getRegClassFor(VT));
3049    AFI->setGlobalBaseReg(GlobalBaseReg);
3050  }
3051
3052  unsigned DestReg2 = createResultReg(TLI.getRegClassFor(VT));
3053  DestReg2 = constrainOperandRegClass(TII.get(Opc), DestReg2, 0);
3054  DestReg1 = constrainOperandRegClass(TII.get(Opc), DestReg1, 1);
3055  GlobalBaseReg = constrainOperandRegClass(TII.get(Opc), GlobalBaseReg, 2);
3056  MachineInstrBuilder MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt,
3057                                    DL, TII.get(Opc), DestReg2)
3058                            .addReg(DestReg1)
3059                            .addReg(GlobalBaseReg);
3060  if (!UseGOTOFF)
3061    MIB.addImm(0);
3062  AddOptionalDefs(MIB);
3063
3064  return DestReg2;
3065}
3066
3067bool ARMFastISel::FastLowerArguments() {
3068  if (!FuncInfo.CanLowerReturn)
3069    return false;
3070
3071  const Function *F = FuncInfo.Fn;
3072  if (F->isVarArg())
3073    return false;
3074
3075  CallingConv::ID CC = F->getCallingConv();
3076  switch (CC) {
3077  default:
3078    return false;
3079  case CallingConv::Fast:
3080  case CallingConv::C:
3081  case CallingConv::ARM_AAPCS_VFP:
3082  case CallingConv::ARM_AAPCS:
3083  case CallingConv::ARM_APCS:
3084    break;
3085  }
3086
3087  // Only handle simple cases. i.e. Up to 4 i8/i16/i32 scalar arguments
3088  // which are passed in r0 - r3.
3089  unsigned Idx = 1;
3090  for (Function::const_arg_iterator I = F->arg_begin(), E = F->arg_end();
3091       I != E; ++I, ++Idx) {
3092    if (Idx > 4)
3093      return false;
3094
3095    if (F->getAttributes().hasAttribute(Idx, Attribute::InReg) ||
3096        F->getAttributes().hasAttribute(Idx, Attribute::StructRet) ||
3097        F->getAttributes().hasAttribute(Idx, Attribute::ByVal))
3098      return false;
3099
3100    Type *ArgTy = I->getType();
3101    if (ArgTy->isStructTy() || ArgTy->isArrayTy() || ArgTy->isVectorTy())
3102      return false;
3103
3104    EVT ArgVT = TLI.getValueType(ArgTy);
3105    if (!ArgVT.isSimple()) return false;
3106    switch (ArgVT.getSimpleVT().SimpleTy) {
3107    case MVT::i8:
3108    case MVT::i16:
3109    case MVT::i32:
3110      break;
3111    default:
3112      return false;
3113    }
3114  }
3115
3116
3117  static const uint16_t GPRArgRegs[] = {
3118    ARM::R0, ARM::R1, ARM::R2, ARM::R3
3119  };
3120
3121  const TargetRegisterClass *RC = &ARM::rGPRRegClass;
3122  Idx = 0;
3123  for (Function::const_arg_iterator I = F->arg_begin(), E = F->arg_end();
3124       I != E; ++I, ++Idx) {
3125    unsigned SrcReg = GPRArgRegs[Idx];
3126    unsigned DstReg = FuncInfo.MF->addLiveIn(SrcReg, RC);
3127    // FIXME: Unfortunately it's necessary to emit a copy from the livein copy.
3128    // Without this, EmitLiveInCopies may eliminate the livein if its only
3129    // use is a bitcast (which isn't turned into an instruction).
3130    unsigned ResultReg = createResultReg(RC);
3131    BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(TargetOpcode::COPY),
3132            ResultReg).addReg(DstReg, getKillRegState(true));
3133    UpdateValueMap(I, ResultReg);
3134  }
3135
3136  return true;
3137}
3138
3139namespace llvm {
3140  FastISel *ARM::createFastISel(FunctionLoweringInfo &funcInfo,
3141                                const TargetLibraryInfo *libInfo) {
3142    const TargetMachine &TM = funcInfo.MF->getTarget();
3143
3144    const ARMSubtarget *Subtarget = &TM.getSubtarget<ARMSubtarget>();
3145    // Thumb2 support on iOS; ARM support on iOS, Linux and NaCl.
3146    bool UseFastISel = false;
3147    UseFastISel |= Subtarget->isTargetIOS() && !Subtarget->isThumb1Only();
3148    UseFastISel |= Subtarget->isTargetLinux() && !Subtarget->isThumb();
3149    UseFastISel |= Subtarget->isTargetNaCl() && !Subtarget->isThumb();
3150
3151    if (UseFastISel) {
3152      // iOS always has a FP for backtracking, force other targets
3153      // to keep their FP when doing FastISel. The emitted code is
3154      // currently superior, and in cases like test-suite's lencod
3155      // FastISel isn't quite correct when FP is eliminated.
3156      TM.Options.NoFramePointerElim = true;
3157      return new ARMFastISel(funcInfo, libInfo);
3158    }
3159    return 0;
3160  }
3161}
3162