ARMFastISel.cpp revision f7a1d96e192555ed915694011cf3aedf9ea28009 
1//===-- ARMFastISel.cpp - ARM FastISel implementation ---------------------===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file defines the ARM-specific support for the FastISel class. Some
11// of the target-specific code is generated by tablegen in the file
12// ARMGenFastISel.inc, which is #included here.
13//
14//===----------------------------------------------------------------------===//
15
16#include "ARM.h"
17#include "ARMBaseInstrInfo.h"
18#include "ARMCallingConv.h"
19#include "ARMRegisterInfo.h"
20#include "ARMTargetMachine.h"
21#include "ARMSubtarget.h"
22#include "ARMConstantPoolValue.h"
23#include "llvm/CallingConv.h"
24#include "llvm/DerivedTypes.h"
25#include "llvm/GlobalVariable.h"
26#include "llvm/Instructions.h"
27#include "llvm/IntrinsicInst.h"
28#include "llvm/Module.h"
29#include "llvm/CodeGen/Analysis.h"
30#include "llvm/CodeGen/FastISel.h"
31#include "llvm/CodeGen/FunctionLoweringInfo.h"
32#include "llvm/CodeGen/MachineInstrBuilder.h"
33#include "llvm/CodeGen/MachineModuleInfo.h"
34#include "llvm/CodeGen/MachineConstantPool.h"
35#include "llvm/CodeGen/MachineFrameInfo.h"
36#include "llvm/CodeGen/MachineMemOperand.h"
37#include "llvm/CodeGen/MachineRegisterInfo.h"
38#include "llvm/CodeGen/PseudoSourceValue.h"
39#include "llvm/Support/CallSite.h"
40#include "llvm/Support/CommandLine.h"
41#include "llvm/Support/ErrorHandling.h"
42#include "llvm/Support/GetElementPtrTypeIterator.h"
43#include "llvm/Target/TargetData.h"
44#include "llvm/Target/TargetInstrInfo.h"
45#include "llvm/Target/TargetLowering.h"
46#include "llvm/Target/TargetMachine.h"
47#include "llvm/Target/TargetOptions.h"
48using namespace llvm;
49
50static cl::opt<bool>
51DisableARMFastISel("disable-arm-fast-isel",
52                    cl::desc("Turn off experimental ARM fast-isel support"),
53                    cl::init(false), cl::Hidden);
54
55namespace {
56
57class ARMFastISel : public FastISel {
58
59  /// Subtarget - Keep a pointer to the ARMSubtarget around so that we can
60  /// make the right decision when generating code for different targets.
61  const ARMSubtarget *Subtarget;
62  const TargetMachine &TM;
63  const TargetInstrInfo &TII;
64  const TargetLowering &TLI;
65  ARMFunctionInfo *AFI;
66
67  // Convenience variables to avoid some queries.
68  bool isThumb;
69  LLVMContext *Context;
70
71  public:
72    explicit ARMFastISel(FunctionLoweringInfo &funcInfo)
73    : FastISel(funcInfo),
74      TM(funcInfo.MF->getTarget()),
75      TII(*TM.getInstrInfo()),
76      TLI(*TM.getTargetLowering()) {
77      Subtarget = &TM.getSubtarget<ARMSubtarget>();
78      AFI = funcInfo.MF->getInfo<ARMFunctionInfo>();
79      isThumb = AFI->isThumbFunction();
80      Context = &funcInfo.Fn->getContext();
81    }
82
83    // Code from FastISel.cpp.
84    virtual unsigned FastEmitInst_(unsigned MachineInstOpcode,
85                                   const TargetRegisterClass *RC);
86    virtual unsigned FastEmitInst_r(unsigned MachineInstOpcode,
87                                    const TargetRegisterClass *RC,
88                                    unsigned Op0, bool Op0IsKill);
89    virtual unsigned FastEmitInst_rr(unsigned MachineInstOpcode,
90                                     const TargetRegisterClass *RC,
91                                     unsigned Op0, bool Op0IsKill,
92                                     unsigned Op1, bool Op1IsKill);
93    virtual unsigned FastEmitInst_ri(unsigned MachineInstOpcode,
94                                     const TargetRegisterClass *RC,
95                                     unsigned Op0, bool Op0IsKill,
96                                     uint64_t Imm);
97    virtual unsigned FastEmitInst_rf(unsigned MachineInstOpcode,
98                                     const TargetRegisterClass *RC,
99                                     unsigned Op0, bool Op0IsKill,
100                                     const ConstantFP *FPImm);
101    virtual unsigned FastEmitInst_i(unsigned MachineInstOpcode,
102                                    const TargetRegisterClass *RC,
103                                    uint64_t Imm);
104    virtual unsigned FastEmitInst_rri(unsigned MachineInstOpcode,
105                                      const TargetRegisterClass *RC,
106                                      unsigned Op0, bool Op0IsKill,
107                                      unsigned Op1, bool Op1IsKill,
108                                      uint64_t Imm);
109    virtual unsigned FastEmitInst_extractsubreg(MVT RetVT,
110                                                unsigned Op0, bool Op0IsKill,
111                                                uint32_t Idx);
112
113    // Backend specific FastISel code.
114    virtual bool TargetSelectInstruction(const Instruction *I);
115    virtual unsigned TargetMaterializeConstant(const Constant *C);
116    virtual unsigned TargetMaterializeAlloca(const AllocaInst *AI);
117
118  #include "ARMGenFastISel.inc"
119
120    // Instruction selection routines.
121  private:
122    virtual bool SelectLoad(const Instruction *I);
123    virtual bool SelectStore(const Instruction *I);
124    virtual bool SelectBranch(const Instruction *I);
125    virtual bool SelectCmp(const Instruction *I);
126    virtual bool SelectFPExt(const Instruction *I);
127    virtual bool SelectFPTrunc(const Instruction *I);
128    virtual bool SelectBinaryOp(const Instruction *I, unsigned ISDOpcode);
129    virtual bool SelectSIToFP(const Instruction *I);
130    virtual bool SelectFPToSI(const Instruction *I);
131    virtual bool SelectSDiv(const Instruction *I);
132    virtual bool SelectSRem(const Instruction *I);
133    virtual bool SelectCall(const Instruction *I);
134    virtual bool SelectSelect(const Instruction *I);
135
136    // Utility routines.
137  private:
138    bool isTypeLegal(const Type *Ty, EVT &VT);
139    bool isLoadTypeLegal(const Type *Ty, EVT &VT);
140    bool ARMEmitLoad(EVT VT, unsigned &ResultReg, unsigned Base, int Offset);
141    bool ARMEmitStore(EVT VT, unsigned SrcReg, unsigned Base, int Offset);
142    bool ARMComputeRegOffset(const Value *Obj, unsigned &Base, int &Offset);
143    void ARMSimplifyRegOffset(unsigned &Base, int &Offset, EVT VT);
144    unsigned ARMMaterializeFP(const ConstantFP *CFP, EVT VT);
145    unsigned ARMMaterializeInt(const Constant *C, EVT VT);
146    unsigned ARMMaterializeGV(const GlobalValue *GV, EVT VT);
147    unsigned ARMMoveToFPReg(EVT VT, unsigned SrcReg);
148    unsigned ARMMoveToIntReg(EVT VT, unsigned SrcReg);
149
150    // Call handling routines.
151  private:
152    bool FastEmitExtend(ISD::NodeType Opc, EVT DstVT, unsigned Src, EVT SrcVT,
153                        unsigned &ResultReg);
154    CCAssignFn *CCAssignFnForCall(CallingConv::ID CC, bool Return);
155    bool ProcessCallArgs(SmallVectorImpl<Value*> &Args,
156                         SmallVectorImpl<unsigned> &ArgRegs,
157                         SmallVectorImpl<EVT> &ArgVTs,
158                         SmallVectorImpl<ISD::ArgFlagsTy> &ArgFlags,
159                         SmallVectorImpl<unsigned> &RegArgs,
160                         CallingConv::ID CC,
161                         unsigned &NumBytes);
162    bool FinishCall(EVT RetVT, SmallVectorImpl<unsigned> &UsedRegs,
163                    const Instruction *I, CallingConv::ID CC,
164                    unsigned &NumBytes);
165    bool ARMEmitLibcall(const Instruction *I, RTLIB::Libcall Call);
166
167    // OptionalDef handling routines.
168  private:
169    bool DefinesOptionalPredicate(MachineInstr *MI, bool *CPSR);
170    const MachineInstrBuilder &AddOptionalDefs(const MachineInstrBuilder &MIB);
171};
172
173} // end anonymous namespace
174
175#include "ARMGenCallingConv.inc"
176
177// DefinesOptionalPredicate - This is different from DefinesPredicate in that
178// we don't care about implicit defs here, just places we'll need to add a
179// default CCReg argument. Sets CPSR if we're setting CPSR instead of CCR.
180bool ARMFastISel::DefinesOptionalPredicate(MachineInstr *MI, bool *CPSR) {
181  const TargetInstrDesc &TID = MI->getDesc();
182  if (!TID.hasOptionalDef())
183    return false;
184
185  // Look to see if our OptionalDef is defining CPSR or CCR.
186  for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
187    const MachineOperand &MO = MI->getOperand(i);
188    if (!MO.isReg() || !MO.isDef()) continue;
189    if (MO.getReg() == ARM::CPSR)
190      *CPSR = true;
191  }
192  return true;
193}
194
195// If the machine is predicable go ahead and add the predicate operands, if
196// it needs default CC operands add those.
197const MachineInstrBuilder &
198ARMFastISel::AddOptionalDefs(const MachineInstrBuilder &MIB) {
199  MachineInstr *MI = &*MIB;
200
201  // Do we use a predicate?
202  if (TII.isPredicable(MI))
203    AddDefaultPred(MIB);
204
205  // Do we optionally set a predicate?  Preds is size > 0 iff the predicate
206  // defines CPSR. All other OptionalDefines in ARM are the CCR register.
207  bool CPSR = false;
208  if (DefinesOptionalPredicate(MI, &CPSR)) {
209    if (CPSR)
210      AddDefaultT1CC(MIB);
211    else
212      AddDefaultCC(MIB);
213  }
214  return MIB;
215}
216
217unsigned ARMFastISel::FastEmitInst_(unsigned MachineInstOpcode,
218                                    const TargetRegisterClass* RC) {
219  unsigned ResultReg = createResultReg(RC);
220  const TargetInstrDesc &II = TII.get(MachineInstOpcode);
221
222  AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II, ResultReg));
223  return ResultReg;
224}
225
226unsigned ARMFastISel::FastEmitInst_r(unsigned MachineInstOpcode,
227                                     const TargetRegisterClass *RC,
228                                     unsigned Op0, bool Op0IsKill) {
229  unsigned ResultReg = createResultReg(RC);
230  const TargetInstrDesc &II = TII.get(MachineInstOpcode);
231
232  if (II.getNumDefs() >= 1)
233    AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II, ResultReg)
234                   .addReg(Op0, Op0IsKill * RegState::Kill));
235  else {
236    AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II)
237                   .addReg(Op0, Op0IsKill * RegState::Kill));
238    AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
239                   TII.get(TargetOpcode::COPY), ResultReg)
240                   .addReg(II.ImplicitDefs[0]));
241  }
242  return ResultReg;
243}
244
245unsigned ARMFastISel::FastEmitInst_rr(unsigned MachineInstOpcode,
246                                      const TargetRegisterClass *RC,
247                                      unsigned Op0, bool Op0IsKill,
248                                      unsigned Op1, bool Op1IsKill) {
249  unsigned ResultReg = createResultReg(RC);
250  const TargetInstrDesc &II = TII.get(MachineInstOpcode);
251
252  if (II.getNumDefs() >= 1)
253    AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II, ResultReg)
254                   .addReg(Op0, Op0IsKill * RegState::Kill)
255                   .addReg(Op1, Op1IsKill * RegState::Kill));
256  else {
257    AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II)
258                   .addReg(Op0, Op0IsKill * RegState::Kill)
259                   .addReg(Op1, Op1IsKill * RegState::Kill));
260    AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
261                           TII.get(TargetOpcode::COPY), ResultReg)
262                   .addReg(II.ImplicitDefs[0]));
263  }
264  return ResultReg;
265}
266
267unsigned ARMFastISel::FastEmitInst_ri(unsigned MachineInstOpcode,
268                                      const TargetRegisterClass *RC,
269                                      unsigned Op0, bool Op0IsKill,
270                                      uint64_t Imm) {
271  unsigned ResultReg = createResultReg(RC);
272  const TargetInstrDesc &II = TII.get(MachineInstOpcode);
273
274  if (II.getNumDefs() >= 1)
275    AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II, ResultReg)
276                   .addReg(Op0, Op0IsKill * RegState::Kill)
277                   .addImm(Imm));
278  else {
279    AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II)
280                   .addReg(Op0, Op0IsKill * RegState::Kill)
281                   .addImm(Imm));
282    AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
283                           TII.get(TargetOpcode::COPY), ResultReg)
284                   .addReg(II.ImplicitDefs[0]));
285  }
286  return ResultReg;
287}
288
289unsigned ARMFastISel::FastEmitInst_rf(unsigned MachineInstOpcode,
290                                      const TargetRegisterClass *RC,
291                                      unsigned Op0, bool Op0IsKill,
292                                      const ConstantFP *FPImm) {
293  unsigned ResultReg = createResultReg(RC);
294  const TargetInstrDesc &II = TII.get(MachineInstOpcode);
295
296  if (II.getNumDefs() >= 1)
297    AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II, ResultReg)
298                   .addReg(Op0, Op0IsKill * RegState::Kill)
299                   .addFPImm(FPImm));
300  else {
301    AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II)
302                   .addReg(Op0, Op0IsKill * RegState::Kill)
303                   .addFPImm(FPImm));
304    AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
305                           TII.get(TargetOpcode::COPY), ResultReg)
306                   .addReg(II.ImplicitDefs[0]));
307  }
308  return ResultReg;
309}
310
311unsigned ARMFastISel::FastEmitInst_rri(unsigned MachineInstOpcode,
312                                       const TargetRegisterClass *RC,
313                                       unsigned Op0, bool Op0IsKill,
314                                       unsigned Op1, bool Op1IsKill,
315                                       uint64_t Imm) {
316  unsigned ResultReg = createResultReg(RC);
317  const TargetInstrDesc &II = TII.get(MachineInstOpcode);
318
319  if (II.getNumDefs() >= 1)
320    AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II, ResultReg)
321                   .addReg(Op0, Op0IsKill * RegState::Kill)
322                   .addReg(Op1, Op1IsKill * RegState::Kill)
323                   .addImm(Imm));
324  else {
325    AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II)
326                   .addReg(Op0, Op0IsKill * RegState::Kill)
327                   .addReg(Op1, Op1IsKill * RegState::Kill)
328                   .addImm(Imm));
329    AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
330                           TII.get(TargetOpcode::COPY), ResultReg)
331                   .addReg(II.ImplicitDefs[0]));
332  }
333  return ResultReg;
334}
335
336unsigned ARMFastISel::FastEmitInst_i(unsigned MachineInstOpcode,
337                                     const TargetRegisterClass *RC,
338                                     uint64_t Imm) {
339  unsigned ResultReg = createResultReg(RC);
340  const TargetInstrDesc &II = TII.get(MachineInstOpcode);
341
342  if (II.getNumDefs() >= 1)
343    AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II, ResultReg)
344                   .addImm(Imm));
345  else {
346    AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II)
347                   .addImm(Imm));
348    AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
349                           TII.get(TargetOpcode::COPY), ResultReg)
350                   .addReg(II.ImplicitDefs[0]));
351  }
352  return ResultReg;
353}
354
355unsigned ARMFastISel::FastEmitInst_extractsubreg(MVT RetVT,
356                                                 unsigned Op0, bool Op0IsKill,
357                                                 uint32_t Idx) {
358  unsigned ResultReg = createResultReg(TLI.getRegClassFor(RetVT));
359  assert(TargetRegisterInfo::isVirtualRegister(Op0) &&
360         "Cannot yet extract from physregs");
361  AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt,
362                         DL, TII.get(TargetOpcode::COPY), ResultReg)
363                 .addReg(Op0, getKillRegState(Op0IsKill), Idx));
364  return ResultReg;
365}
366
367// TODO: Don't worry about 64-bit now, but when this is fixed remove the
368// checks from the various callers.
369unsigned ARMFastISel::ARMMoveToFPReg(EVT VT, unsigned SrcReg) {
370  if (VT.getSimpleVT().SimpleTy == MVT::f64) return 0;
371
372  unsigned MoveReg = createResultReg(TLI.getRegClassFor(VT));
373  AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
374                          TII.get(ARM::VMOVRS), MoveReg)
375                  .addReg(SrcReg));
376  return MoveReg;
377}
378
379unsigned ARMFastISel::ARMMoveToIntReg(EVT VT, unsigned SrcReg) {
380  if (VT.getSimpleVT().SimpleTy == MVT::i64) return 0;
381
382  unsigned MoveReg = createResultReg(TLI.getRegClassFor(VT));
383  AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
384                          TII.get(ARM::VMOVSR), MoveReg)
385                  .addReg(SrcReg));
386  return MoveReg;
387}
388
389// For double width floating point we need to materialize two constants
390// (the high and the low) into integer registers then use a move to get
391// the combined constant into an FP reg.
392unsigned ARMFastISel::ARMMaterializeFP(const ConstantFP *CFP, EVT VT) {
393  const APFloat Val = CFP->getValueAPF();
394  bool is64bit = VT.getSimpleVT().SimpleTy == MVT::f64;
395
396  // This checks to see if we can use VFP3 instructions to materialize
397  // a constant, otherwise we have to go through the constant pool.
398  if (TLI.isFPImmLegal(Val, VT)) {
399    unsigned Opc = is64bit ? ARM::FCONSTD : ARM::FCONSTS;
400    unsigned DestReg = createResultReg(TLI.getRegClassFor(VT));
401    AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(Opc),
402                            DestReg)
403                    .addFPImm(CFP));
404    return DestReg;
405  }
406
407  // Require VFP2 for loading fp constants.
408  if (!Subtarget->hasVFP2()) return false;
409
410  // MachineConstantPool wants an explicit alignment.
411  unsigned Align = TD.getPrefTypeAlignment(CFP->getType());
412  if (Align == 0) {
413    // TODO: Figure out if this is correct.
414    Align = TD.getTypeAllocSize(CFP->getType());
415  }
416  unsigned Idx = MCP.getConstantPoolIndex(cast<Constant>(CFP), Align);
417  unsigned DestReg = createResultReg(TLI.getRegClassFor(VT));
418  unsigned Opc = is64bit ? ARM::VLDRD : ARM::VLDRS;
419
420  // The extra reg is for addrmode5.
421  AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(Opc),
422                          DestReg)
423                  .addConstantPoolIndex(Idx)
424                  .addReg(0));
425  return DestReg;
426}
427
428unsigned ARMFastISel::ARMMaterializeInt(const Constant *C, EVT VT) {
429
430  // For now 32-bit only.
431  if (VT.getSimpleVT().SimpleTy != MVT::i32) return false;
432
433  // MachineConstantPool wants an explicit alignment.
434  unsigned Align = TD.getPrefTypeAlignment(C->getType());
435  if (Align == 0) {
436    // TODO: Figure out if this is correct.
437    Align = TD.getTypeAllocSize(C->getType());
438  }
439  unsigned Idx = MCP.getConstantPoolIndex(C, Align);
440  unsigned DestReg = createResultReg(TLI.getRegClassFor(VT));
441
442  if (isThumb)
443    AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
444                            TII.get(ARM::t2LDRpci), DestReg)
445                    .addConstantPoolIndex(Idx));
446  else
447    // The extra reg and immediate are for addrmode2.
448    AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
449                            TII.get(ARM::LDRcp), DestReg)
450                    .addConstantPoolIndex(Idx)
451                    .addReg(0).addImm(0));
452
453  return DestReg;
454}
455
456unsigned ARMFastISel::ARMMaterializeGV(const GlobalValue *GV, EVT VT) {
457  // For now 32-bit only.
458  if (VT.getSimpleVT().SimpleTy != MVT::i32) return 0;
459
460  Reloc::Model RelocM = TM.getRelocationModel();
461
462  // TODO: No external globals for now.
463  if (Subtarget->GVIsIndirectSymbol(GV, RelocM)) return 0;
464
465  // TODO: Need more magic for ARM PIC.
466  if (!isThumb && (RelocM == Reloc::PIC_)) return 0;
467
468  // MachineConstantPool wants an explicit alignment.
469  unsigned Align = TD.getPrefTypeAlignment(GV->getType());
470  if (Align == 0) {
471    // TODO: Figure out if this is correct.
472    Align = TD.getTypeAllocSize(GV->getType());
473  }
474
475  // Grab index.
476  unsigned PCAdj = (RelocM != Reloc::PIC_) ? 0 : (Subtarget->isThumb() ? 4 : 8);
477  unsigned Id = AFI->createConstPoolEntryUId();
478  ARMConstantPoolValue *CPV = new ARMConstantPoolValue(GV, Id,
479                                                       ARMCP::CPValue, PCAdj);
480  unsigned Idx = MCP.getConstantPoolIndex(CPV, Align);
481
482  // Load value.
483  MachineInstrBuilder MIB;
484  unsigned DestReg = createResultReg(TLI.getRegClassFor(VT));
485  if (isThumb) {
486    unsigned Opc = (RelocM != Reloc::PIC_) ? ARM::t2LDRpci : ARM::t2LDRpci_pic;
487    MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(Opc), DestReg)
488          .addConstantPoolIndex(Idx);
489    if (RelocM == Reloc::PIC_)
490      MIB.addImm(Id);
491  } else {
492    // The extra reg and immediate are for addrmode2.
493    MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(ARM::LDRcp),
494                  DestReg)
495          .addConstantPoolIndex(Idx)
496          .addReg(0).addImm(0);
497  }
498  AddOptionalDefs(MIB);
499  return DestReg;
500}
501
502unsigned ARMFastISel::TargetMaterializeConstant(const Constant *C) {
503  EVT VT = TLI.getValueType(C->getType(), true);
504
505  // Only handle simple types.
506  if (!VT.isSimple()) return 0;
507
508  if (const ConstantFP *CFP = dyn_cast<ConstantFP>(C))
509    return ARMMaterializeFP(CFP, VT);
510  else if (const GlobalValue *GV = dyn_cast<GlobalValue>(C))
511    return ARMMaterializeGV(GV, VT);
512  else if (isa<ConstantInt>(C))
513    return ARMMaterializeInt(C, VT);
514
515  return 0;
516}
517
518unsigned ARMFastISel::TargetMaterializeAlloca(const AllocaInst *AI) {
519  // Don't handle dynamic allocas.
520  if (!FuncInfo.StaticAllocaMap.count(AI)) return 0;
521
522  EVT VT;
523  if (!isLoadTypeLegal(AI->getType(), VT)) return false;
524
525  DenseMap<const AllocaInst*, int>::iterator SI =
526    FuncInfo.StaticAllocaMap.find(AI);
527
528  // This will get lowered later into the correct offsets and registers
529  // via rewriteXFrameIndex.
530  if (SI != FuncInfo.StaticAllocaMap.end()) {
531    TargetRegisterClass* RC = TLI.getRegClassFor(VT);
532    unsigned ResultReg = createResultReg(RC);
533    unsigned Opc = isThumb ? ARM::t2ADDri : ARM::ADDri;
534    AddOptionalDefs(BuildMI(*FuncInfo.MBB, *FuncInfo.InsertPt, DL,
535                            TII.get(Opc), ResultReg)
536                            .addFrameIndex(SI->second)
537                            .addImm(0));
538    return ResultReg;
539  }
540
541  return 0;
542}
543
544bool ARMFastISel::isTypeLegal(const Type *Ty, EVT &VT) {
545  VT = TLI.getValueType(Ty, true);
546
547  // Only handle simple types.
548  if (VT == MVT::Other || !VT.isSimple()) return false;
549
550  // Handle all legal types, i.e. a register that will directly hold this
551  // value.
552  return TLI.isTypeLegal(VT);
553}
554
555bool ARMFastISel::isLoadTypeLegal(const Type *Ty, EVT &VT) {
556  if (isTypeLegal(Ty, VT)) return true;
557
558  // If this is a type than can be sign or zero-extended to a basic operation
559  // go ahead and accept it now.
560  if (VT == MVT::i8 || VT == MVT::i16)
561    return true;
562
563  return false;
564}
565
566// Computes the Reg+Offset to get to an object.
567bool ARMFastISel::ARMComputeRegOffset(const Value *Obj, unsigned &Base,
568                                      int &Offset) {
569  // Some boilerplate from the X86 FastISel.
570  const User *U = NULL;
571  unsigned Opcode = Instruction::UserOp1;
572  if (const Instruction *I = dyn_cast<Instruction>(Obj)) {
573    // Don't walk into other basic blocks; it's possible we haven't
574    // visited them yet, so the instructions may not yet be assigned
575    // virtual registers.
576    if (FuncInfo.MBBMap[I->getParent()] != FuncInfo.MBB)
577      return false;
578    Opcode = I->getOpcode();
579    U = I;
580  } else if (const ConstantExpr *C = dyn_cast<ConstantExpr>(Obj)) {
581    Opcode = C->getOpcode();
582    U = C;
583  }
584
585  if (const PointerType *Ty = dyn_cast<PointerType>(Obj->getType()))
586    if (Ty->getAddressSpace() > 255)
587      // Fast instruction selection doesn't support the special
588      // address spaces.
589      return false;
590
591  switch (Opcode) {
592    default:
593    break;
594    case Instruction::BitCast: {
595      // Look through bitcasts.
596      return ARMComputeRegOffset(U->getOperand(0), Base, Offset);
597    }
598    case Instruction::IntToPtr: {
599      // Look past no-op inttoptrs.
600      if (TLI.getValueType(U->getOperand(0)->getType()) == TLI.getPointerTy())
601        return ARMComputeRegOffset(U->getOperand(0), Base, Offset);
602      break;
603    }
604    case Instruction::PtrToInt: {
605      // Look past no-op ptrtoints.
606      if (TLI.getValueType(U->getType()) == TLI.getPointerTy())
607        return ARMComputeRegOffset(U->getOperand(0), Base, Offset);
608      break;
609    }
610    case Instruction::GetElementPtr: {
611      int SavedOffset = Offset;
612      unsigned SavedBase = Base;
613      int TmpOffset = Offset;
614
615      // Iterate through the GEP folding the constants into offsets where
616      // we can.
617      gep_type_iterator GTI = gep_type_begin(U);
618      for (User::const_op_iterator i = U->op_begin() + 1, e = U->op_end();
619           i != e; ++i, ++GTI) {
620        const Value *Op = *i;
621        if (const StructType *STy = dyn_cast<StructType>(*GTI)) {
622          const StructLayout *SL = TD.getStructLayout(STy);
623          unsigned Idx = cast<ConstantInt>(Op)->getZExtValue();
624          TmpOffset += SL->getElementOffset(Idx);
625        } else {
626          uint64_t S = TD.getTypeAllocSize(GTI.getIndexedType());
627          SmallVector<const Value *, 4> Worklist;
628          Worklist.push_back(Op);
629          do {
630            Op = Worklist.pop_back_val();
631            if (const ConstantInt *CI = dyn_cast<ConstantInt>(Op)) {
632              // Constant-offset addressing.
633              TmpOffset += CI->getSExtValue() * S;
634            } else if (isa<AddOperator>(Op) &&
635                       isa<ConstantInt>(cast<AddOperator>(Op)->getOperand(1))) {
636              // An add with a constant operand. Fold the constant.
637              ConstantInt *CI =
638                cast<ConstantInt>(cast<AddOperator>(Op)->getOperand(1));
639              TmpOffset += CI->getSExtValue() * S;
640              // Add the other operand back to the work list.
641              Worklist.push_back(cast<AddOperator>(Op)->getOperand(0));
642            } else
643              goto unsupported_gep;
644          } while (!Worklist.empty());
645        }
646      }
647
648      // Try to grab the base operand now.
649      Offset = TmpOffset;
650      if (ARMComputeRegOffset(U->getOperand(0), Base, Offset)) return true;
651
652      // We failed, restore everything and try the other options.
653      Offset = SavedOffset;
654      Base = SavedBase;
655
656      unsupported_gep:
657      break;
658    }
659    case Instruction::Alloca: {
660      const AllocaInst *AI = cast<AllocaInst>(Obj);
661      unsigned Reg = TargetMaterializeAlloca(AI);
662
663      if (Reg == 0) return false;
664
665      Base = Reg;
666      return true;
667    }
668  }
669
670  // Materialize the global variable's address into a reg which can
671  // then be used later to load the variable.
672  if (const GlobalValue *GV = dyn_cast<GlobalValue>(Obj)) {
673    unsigned Tmp = ARMMaterializeGV(GV, TLI.getValueType(Obj->getType()));
674    if (Tmp == 0) return false;
675
676    Base = Tmp;
677    return true;
678  }
679
680  // Try to get this in a register if nothing else has worked.
681  if (Base == 0) Base  = getRegForValue(Obj);
682  return Base != 0;
683}
684
685void ARMFastISel::ARMSimplifyRegOffset(unsigned &Base, int &Offset, EVT VT) {
686
687  assert(VT.isSimple() && "Non-simple types are invalid here!");
688
689  bool needsLowering = false;
690  switch (VT.getSimpleVT().SimpleTy) {
691    default:
692      assert(false && "Unhandled load/store type!");
693    case MVT::i1:
694    case MVT::i8:
695    case MVT::i16:
696    case MVT::i32:
697      // Integer loads/stores handle 12-bit offsets.
698      needsLowering = ((Offset & 0xfff) != Offset);
699      break;
700    case MVT::f32:
701    case MVT::f64:
702      // Floating point operands handle 8-bit offsets.
703      needsLowering = ((Offset & 0xff) != Offset);
704      break;
705  }
706
707  // Since the offset is too large for the load/store instruction
708  // get the reg+offset into a register.
709  if (needsLowering) {
710    ARMCC::CondCodes Pred = ARMCC::AL;
711    unsigned PredReg = 0;
712
713    TargetRegisterClass *RC = isThumb ? ARM::tGPRRegisterClass :
714      ARM::GPRRegisterClass;
715    unsigned BaseReg = createResultReg(RC);
716
717    if (!isThumb)
718      emitARMRegPlusImmediate(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
719                              BaseReg, Base, Offset, Pred, PredReg,
720                              static_cast<const ARMBaseInstrInfo&>(TII));
721    else {
722      assert(AFI->isThumb2Function());
723      emitT2RegPlusImmediate(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
724                             BaseReg, Base, Offset, Pred, PredReg,
725                             static_cast<const ARMBaseInstrInfo&>(TII));
726    }
727    Offset = 0;
728    Base = BaseReg;
729  }
730}
731
732bool ARMFastISel::ARMEmitLoad(EVT VT, unsigned &ResultReg,
733                              unsigned Base, int Offset) {
734
735  assert(VT.isSimple() && "Non-simple types are invalid here!");
736  unsigned Opc;
737  TargetRegisterClass *RC;
738  bool isFloat = false;
739  switch (VT.getSimpleVT().SimpleTy) {
740    default:
741      // This is mostly going to be Neon/vector support.
742      return false;
743    case MVT::i16:
744      Opc = isThumb ? ARM::t2LDRHi12 : ARM::LDRH;
745      RC = ARM::GPRRegisterClass;
746      break;
747    case MVT::i8:
748      Opc = isThumb ? ARM::t2LDRBi12 : ARM::LDRB;
749      RC = ARM::GPRRegisterClass;
750      break;
751    case MVT::i32:
752      Opc = isThumb ? ARM::t2LDRi12 : ARM::LDR;
753      RC = ARM::GPRRegisterClass;
754      break;
755    case MVT::f32:
756      Opc = ARM::VLDRS;
757      RC = TLI.getRegClassFor(VT);
758      isFloat = true;
759      break;
760    case MVT::f64:
761      Opc = ARM::VLDRD;
762      RC = TLI.getRegClassFor(VT);
763      isFloat = true;
764      break;
765  }
766
767  ResultReg = createResultReg(RC);
768
769  ARMSimplifyRegOffset(Base, Offset, VT);
770
771  // addrmode5 output depends on the selection dag addressing dividing the
772  // offset by 4 that it then later multiplies. Do this here as well.
773  if (isFloat)
774    Offset /= 4;
775
776  // The thumb and floating point instructions both take 2 operands, ARM takes
777  // another register.
778  if (isFloat || isThumb)
779    AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
780                            TII.get(Opc), ResultReg)
781                    .addReg(Base).addImm(Offset));
782  else
783    AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
784                            TII.get(Opc), ResultReg)
785                    .addReg(Base).addReg(0).addImm(Offset));
786  return true;
787}
788
789bool ARMFastISel::SelectLoad(const Instruction *I) {
790  // Verify we have a legal type before going any further.
791  EVT VT;
792  if (!isLoadTypeLegal(I->getType(), VT))
793    return false;
794
795  // Our register and offset with innocuous defaults.
796  unsigned Base = 0;
797  int Offset = 0;
798
799  // See if we can handle this as Reg + Offset
800  if (!ARMComputeRegOffset(I->getOperand(0), Base, Offset))
801    return false;
802
803  unsigned ResultReg;
804  if (!ARMEmitLoad(VT, ResultReg, Base, Offset)) return false;
805
806  UpdateValueMap(I, ResultReg);
807  return true;
808}
809
810bool ARMFastISel::ARMEmitStore(EVT VT, unsigned SrcReg,
811                               unsigned Base, int Offset) {
812  unsigned StrOpc;
813  bool isFloat = false;
814  switch (VT.getSimpleVT().SimpleTy) {
815    default: return false;
816    case MVT::i1:
817    case MVT::i8:
818      StrOpc = isThumb ? ARM::t2STRBi12 : ARM::STRB;
819      break;
820    case MVT::i16:
821      StrOpc = isThumb ? ARM::t2STRHi12 : ARM::STRH;
822      break;
823    case MVT::i32:
824      StrOpc = isThumb ? ARM::t2STRi12 : ARM::STR;
825      break;
826    case MVT::f32:
827      if (!Subtarget->hasVFP2()) return false;
828      StrOpc = ARM::VSTRS;
829      isFloat = true;
830      break;
831    case MVT::f64:
832      if (!Subtarget->hasVFP2()) return false;
833      StrOpc = ARM::VSTRD;
834      isFloat = true;
835      break;
836  }
837
838  ARMSimplifyRegOffset(Base, Offset, VT);
839
840  // addrmode5 output depends on the selection dag addressing dividing the
841  // offset by 4 that it then later multiplies. Do this here as well.
842  if (isFloat)
843    Offset /= 4;
844
845  // The thumb addressing mode has operands swapped from the arm addressing
846  // mode, the floating point one only has two operands.
847  if (isFloat || isThumb)
848    AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
849                            TII.get(StrOpc))
850                    .addReg(SrcReg).addReg(Base).addImm(Offset));
851  else
852    AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
853                            TII.get(StrOpc))
854                    .addReg(SrcReg).addReg(Base).addReg(0).addImm(Offset));
855
856  return true;
857}
858
859bool ARMFastISel::SelectStore(const Instruction *I) {
860  Value *Op0 = I->getOperand(0);
861  unsigned SrcReg = 0;
862
863  // Yay type legalization
864  EVT VT;
865  if (!isLoadTypeLegal(I->getOperand(0)->getType(), VT))
866    return false;
867
868  // Get the value to be stored into a register.
869  SrcReg = getRegForValue(Op0);
870  if (SrcReg == 0)
871    return false;
872
873  // Our register and offset with innocuous defaults.
874  unsigned Base = 0;
875  int Offset = 0;
876
877  // See if we can handle this as Reg + Offset
878  if (!ARMComputeRegOffset(I->getOperand(1), Base, Offset))
879    return false;
880
881  if (!ARMEmitStore(VT, SrcReg, Base, Offset)) return false;
882
883  return true;
884}
885
886static ARMCC::CondCodes getComparePred(CmpInst::Predicate Pred) {
887  switch (Pred) {
888    // Needs two compares...
889    case CmpInst::FCMP_ONE:
890    case CmpInst::FCMP_UEQ:
891    default:
892      assert(false && "Unhandled CmpInst::Predicate!");
893      return ARMCC::AL;
894    case CmpInst::ICMP_EQ:
895    case CmpInst::FCMP_OEQ:
896      return ARMCC::EQ;
897    case CmpInst::ICMP_SGT:
898    case CmpInst::FCMP_OGT:
899      return ARMCC::GT;
900    case CmpInst::ICMP_SGE:
901    case CmpInst::FCMP_OGE:
902      return ARMCC::GE;
903    case CmpInst::ICMP_UGT:
904    case CmpInst::FCMP_UGT:
905      return ARMCC::HI;
906    case CmpInst::FCMP_OLT:
907      return ARMCC::MI;
908    case CmpInst::ICMP_ULE:
909    case CmpInst::FCMP_OLE:
910      return ARMCC::LS;
911    case CmpInst::FCMP_ORD:
912      return ARMCC::VC;
913    case CmpInst::FCMP_UNO:
914      return ARMCC::VS;
915    case CmpInst::FCMP_UGE:
916      return ARMCC::PL;
917    case CmpInst::ICMP_SLT:
918    case CmpInst::FCMP_ULT:
919      return ARMCC::LT;
920    case CmpInst::ICMP_SLE:
921    case CmpInst::FCMP_ULE:
922      return ARMCC::LE;
923    case CmpInst::FCMP_UNE:
924    case CmpInst::ICMP_NE:
925      return ARMCC::NE;
926    case CmpInst::ICMP_UGE:
927      return ARMCC::HS;
928    case CmpInst::ICMP_ULT:
929      return ARMCC::LO;
930  }
931}
932
933bool ARMFastISel::SelectBranch(const Instruction *I) {
934  const BranchInst *BI = cast<BranchInst>(I);
935  MachineBasicBlock *TBB = FuncInfo.MBBMap[BI->getSuccessor(0)];
936  MachineBasicBlock *FBB = FuncInfo.MBBMap[BI->getSuccessor(1)];
937
938  // Simple branch support.
939  // TODO: Try to avoid the re-computation in some places.
940  unsigned CondReg = getRegForValue(BI->getCondition());
941  if (CondReg == 0) return false;
942
943  // Re-set the flags just in case.
944  unsigned CmpOpc = isThumb ? ARM::t2CMPri : ARM::CMPri;
945  AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(CmpOpc))
946                  .addReg(CondReg).addImm(1));
947
948  unsigned BrOpc = isThumb ? ARM::t2Bcc : ARM::Bcc;
949  BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(BrOpc))
950                  .addMBB(TBB).addImm(ARMCC::EQ).addReg(ARM::CPSR);
951  FastEmitBranch(FBB, DL);
952  FuncInfo.MBB->addSuccessor(TBB);
953  return true;
954}
955
956bool ARMFastISel::SelectCmp(const Instruction *I) {
957  const CmpInst *CI = cast<CmpInst>(I);
958
959  EVT VT;
960  const Type *Ty = CI->getOperand(0)->getType();
961  if (!isTypeLegal(Ty, VT))
962    return false;
963
964  bool isFloat = (Ty->isDoubleTy() || Ty->isFloatTy());
965  if (isFloat && !Subtarget->hasVFP2())
966    return false;
967
968  unsigned CmpOpc;
969  unsigned CondReg;
970  switch (VT.getSimpleVT().SimpleTy) {
971    default: return false;
972    // TODO: Verify compares.
973    case MVT::f32:
974      CmpOpc = ARM::VCMPES;
975      CondReg = ARM::FPSCR;
976      break;
977    case MVT::f64:
978      CmpOpc = ARM::VCMPED;
979      CondReg = ARM::FPSCR;
980      break;
981    case MVT::i32:
982      CmpOpc = isThumb ? ARM::t2CMPrr : ARM::CMPrr;
983      CondReg = ARM::CPSR;
984      break;
985  }
986
987  // Get the compare predicate.
988  ARMCC::CondCodes ARMPred = getComparePred(CI->getPredicate());
989
990  // We may not handle every CC for now.
991  if (ARMPred == ARMCC::AL) return false;
992
993  unsigned Arg1 = getRegForValue(CI->getOperand(0));
994  if (Arg1 == 0) return false;
995
996  unsigned Arg2 = getRegForValue(CI->getOperand(1));
997  if (Arg2 == 0) return false;
998
999  AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(CmpOpc))
1000                  .addReg(Arg1).addReg(Arg2));
1001
1002  // For floating point we need to move the result to a comparison register
1003  // that we can then use for branches.
1004  if (isFloat)
1005    AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
1006                            TII.get(ARM::FMSTAT)));
1007
1008  // Now set a register based on the comparison. Explicitly set the predicates
1009  // here.
1010  unsigned MovCCOpc = isThumb ? ARM::t2MOVCCi : ARM::MOVCCi;
1011  TargetRegisterClass *RC = isThumb ? ARM::rGPRRegisterClass
1012                                    : ARM::GPRRegisterClass;
1013  unsigned DestReg = createResultReg(RC);
1014  Constant *Zero
1015    = ConstantInt::get(Type::getInt32Ty(*Context), 0);
1016  unsigned ZeroReg = TargetMaterializeConstant(Zero);
1017  BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(MovCCOpc), DestReg)
1018          .addReg(ZeroReg).addImm(1)
1019          .addImm(ARMPred).addReg(CondReg);
1020
1021  UpdateValueMap(I, DestReg);
1022  return true;
1023}
1024
1025bool ARMFastISel::SelectFPExt(const Instruction *I) {
1026  // Make sure we have VFP and that we're extending float to double.
1027  if (!Subtarget->hasVFP2()) return false;
1028
1029  Value *V = I->getOperand(0);
1030  if (!I->getType()->isDoubleTy() ||
1031      !V->getType()->isFloatTy()) return false;
1032
1033  unsigned Op = getRegForValue(V);
1034  if (Op == 0) return false;
1035
1036  unsigned Result = createResultReg(ARM::DPRRegisterClass);
1037  AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
1038                          TII.get(ARM::VCVTDS), Result)
1039                  .addReg(Op));
1040  UpdateValueMap(I, Result);
1041  return true;
1042}
1043
1044bool ARMFastISel::SelectFPTrunc(const Instruction *I) {
1045  // Make sure we have VFP and that we're truncating double to float.
1046  if (!Subtarget->hasVFP2()) return false;
1047
1048  Value *V = I->getOperand(0);
1049  if (!(I->getType()->isFloatTy() &&
1050        V->getType()->isDoubleTy())) return false;
1051
1052  unsigned Op = getRegForValue(V);
1053  if (Op == 0) return false;
1054
1055  unsigned Result = createResultReg(ARM::SPRRegisterClass);
1056  AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
1057                          TII.get(ARM::VCVTSD), Result)
1058                  .addReg(Op));
1059  UpdateValueMap(I, Result);
1060  return true;
1061}
1062
1063bool ARMFastISel::SelectSIToFP(const Instruction *I) {
1064  // Make sure we have VFP.
1065  if (!Subtarget->hasVFP2()) return false;
1066
1067  EVT DstVT;
1068  const Type *Ty = I->getType();
1069  if (!isTypeLegal(Ty, DstVT))
1070    return false;
1071
1072  unsigned Op = getRegForValue(I->getOperand(0));
1073  if (Op == 0) return false;
1074
1075  // The conversion routine works on fp-reg to fp-reg and the operand above
1076  // was an integer, move it to the fp registers if possible.
1077  unsigned FP = ARMMoveToFPReg(MVT::f32, Op);
1078  if (FP == 0) return false;
1079
1080  unsigned Opc;
1081  if (Ty->isFloatTy()) Opc = ARM::VSITOS;
1082  else if (Ty->isDoubleTy()) Opc = ARM::VSITOD;
1083  else return 0;
1084
1085  unsigned ResultReg = createResultReg(TLI.getRegClassFor(DstVT));
1086  AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(Opc),
1087                          ResultReg)
1088                  .addReg(FP));
1089  UpdateValueMap(I, ResultReg);
1090  return true;
1091}
1092
1093bool ARMFastISel::SelectFPToSI(const Instruction *I) {
1094  // Make sure we have VFP.
1095  if (!Subtarget->hasVFP2()) return false;
1096
1097  EVT DstVT;
1098  const Type *RetTy = I->getType();
1099  if (!isTypeLegal(RetTy, DstVT))
1100    return false;
1101
1102  unsigned Op = getRegForValue(I->getOperand(0));
1103  if (Op == 0) return false;
1104
1105  unsigned Opc;
1106  const Type *OpTy = I->getOperand(0)->getType();
1107  if (OpTy->isFloatTy()) Opc = ARM::VTOSIZS;
1108  else if (OpTy->isDoubleTy()) Opc = ARM::VTOSIZD;
1109  else return 0;
1110
1111  // f64->s32 or f32->s32 both need an intermediate f32 reg.
1112  unsigned ResultReg = createResultReg(TLI.getRegClassFor(MVT::f32));
1113  AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(Opc),
1114                          ResultReg)
1115                  .addReg(Op));
1116
1117  // This result needs to be in an integer register, but the conversion only
1118  // takes place in fp-regs.
1119  unsigned IntReg = ARMMoveToIntReg(DstVT, ResultReg);
1120  if (IntReg == 0) return false;
1121
1122  UpdateValueMap(I, IntReg);
1123  return true;
1124}
1125
1126bool ARMFastISel::SelectSelect(const Instruction *I) {
1127  EVT VT = TLI.getValueType(I->getType(), /*HandleUnknown=*/true);
1128  if (VT == MVT::Other || !isTypeLegal(I->getType(), VT))
1129    return false;
1130
1131  // Things need to be register sized for register moves.
1132  if (VT.getSimpleVT().SimpleTy != MVT::i32) return false;
1133  const TargetRegisterClass *RC = TLI.getRegClassFor(VT);
1134
1135  unsigned CondReg = getRegForValue(I->getOperand(0));
1136  if (CondReg == 0) return false;
1137  unsigned Op1Reg = getRegForValue(I->getOperand(1));
1138  if (Op1Reg == 0) return false;
1139  unsigned Op2Reg = getRegForValue(I->getOperand(2));
1140  if (Op2Reg == 0) return false;
1141
1142  unsigned CmpOpc = isThumb ? ARM::t2TSTri : ARM::TSTri;
1143  AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(CmpOpc))
1144                  .addReg(CondReg).addImm(1));
1145  unsigned ResultReg = createResultReg(RC);
1146  unsigned MovCCOpc = isThumb ? ARM::t2MOVCCr : ARM::MOVCCr;
1147  BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(MovCCOpc), ResultReg)
1148    .addReg(Op1Reg).addReg(Op2Reg)
1149    .addImm(ARMCC::EQ).addReg(ARM::CPSR);
1150  UpdateValueMap(I, ResultReg);
1151  return true;
1152}
1153
1154bool ARMFastISel::SelectSDiv(const Instruction *I) {
1155  EVT VT;
1156  const Type *Ty = I->getType();
1157  if (!isTypeLegal(Ty, VT))
1158    return false;
1159
1160  // If we have integer div support we should have selected this automagically.
1161  // In case we have a real miss go ahead and return false and we'll pick
1162  // it up later.
1163  if (Subtarget->hasDivide()) return false;
1164
1165  // Otherwise emit a libcall.
1166  RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
1167  if (VT == MVT::i8)
1168    LC = RTLIB::SDIV_I8;
1169  else if (VT == MVT::i16)
1170    LC = RTLIB::SDIV_I16;
1171  else if (VT == MVT::i32)
1172    LC = RTLIB::SDIV_I32;
1173  else if (VT == MVT::i64)
1174    LC = RTLIB::SDIV_I64;
1175  else if (VT == MVT::i128)
1176    LC = RTLIB::SDIV_I128;
1177  assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unsupported SDIV!");
1178
1179  return ARMEmitLibcall(I, LC);
1180}
1181
1182bool ARMFastISel::SelectSRem(const Instruction *I) {
1183  EVT VT;
1184  const Type *Ty = I->getType();
1185  if (!isTypeLegal(Ty, VT))
1186    return false;
1187
1188  RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
1189  if (VT == MVT::i8)
1190    LC = RTLIB::SREM_I8;
1191  else if (VT == MVT::i16)
1192    LC = RTLIB::SREM_I16;
1193  else if (VT == MVT::i32)
1194    LC = RTLIB::SREM_I32;
1195  else if (VT == MVT::i64)
1196    LC = RTLIB::SREM_I64;
1197  else if (VT == MVT::i128)
1198    LC = RTLIB::SREM_I128;
1199  assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unsupported SREM!");
1200
1201  return ARMEmitLibcall(I, LC);
1202}
1203
1204bool ARMFastISel::SelectBinaryOp(const Instruction *I, unsigned ISDOpcode) {
1205  EVT VT  = TLI.getValueType(I->getType(), true);
1206
1207  // We can get here in the case when we want to use NEON for our fp
1208  // operations, but can't figure out how to. Just use the vfp instructions
1209  // if we have them.
1210  // FIXME: It'd be nice to use NEON instructions.
1211  const Type *Ty = I->getType();
1212  bool isFloat = (Ty->isDoubleTy() || Ty->isFloatTy());
1213  if (isFloat && !Subtarget->hasVFP2())
1214    return false;
1215
1216  unsigned Op1 = getRegForValue(I->getOperand(0));
1217  if (Op1 == 0) return false;
1218
1219  unsigned Op2 = getRegForValue(I->getOperand(1));
1220  if (Op2 == 0) return false;
1221
1222  unsigned Opc;
1223  bool is64bit = VT.getSimpleVT().SimpleTy == MVT::f64 ||
1224                 VT.getSimpleVT().SimpleTy == MVT::i64;
1225  switch (ISDOpcode) {
1226    default: return false;
1227    case ISD::FADD:
1228      Opc = is64bit ? ARM::VADDD : ARM::VADDS;
1229      break;
1230    case ISD::FSUB:
1231      Opc = is64bit ? ARM::VSUBD : ARM::VSUBS;
1232      break;
1233    case ISD::FMUL:
1234      Opc = is64bit ? ARM::VMULD : ARM::VMULS;
1235      break;
1236  }
1237  unsigned ResultReg = createResultReg(TLI.getRegClassFor(VT));
1238  AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
1239                          TII.get(Opc), ResultReg)
1240                  .addReg(Op1).addReg(Op2));
1241  UpdateValueMap(I, ResultReg);
1242  return true;
1243}
1244
1245// Call Handling Code
1246
1247bool ARMFastISel::FastEmitExtend(ISD::NodeType Opc, EVT DstVT, unsigned Src,
1248                                 EVT SrcVT, unsigned &ResultReg) {
1249  unsigned RR = FastEmit_r(SrcVT.getSimpleVT(), DstVT.getSimpleVT(), Opc,
1250                           Src, /*TODO: Kill=*/false);
1251
1252  if (RR != 0) {
1253    ResultReg = RR;
1254    return true;
1255  } else
1256    return false;
1257}
1258
1259// This is largely taken directly from CCAssignFnForNode - we don't support
1260// varargs in FastISel so that part has been removed.
1261// TODO: We may not support all of this.
1262CCAssignFn *ARMFastISel::CCAssignFnForCall(CallingConv::ID CC, bool Return) {
1263  switch (CC) {
1264  default:
1265    llvm_unreachable("Unsupported calling convention");
1266  case CallingConv::C:
1267  case CallingConv::Fast:
1268    // Use target triple & subtarget features to do actual dispatch.
1269    if (Subtarget->isAAPCS_ABI()) {
1270      if (Subtarget->hasVFP2() &&
1271          FloatABIType == FloatABI::Hard)
1272        return (Return ? RetCC_ARM_AAPCS_VFP: CC_ARM_AAPCS_VFP);
1273      else
1274        return (Return ? RetCC_ARM_AAPCS: CC_ARM_AAPCS);
1275    } else
1276        return (Return ? RetCC_ARM_APCS: CC_ARM_APCS);
1277  case CallingConv::ARM_AAPCS_VFP:
1278    return (Return ? RetCC_ARM_AAPCS_VFP: CC_ARM_AAPCS_VFP);
1279  case CallingConv::ARM_AAPCS:
1280    return (Return ? RetCC_ARM_AAPCS: CC_ARM_AAPCS);
1281  case CallingConv::ARM_APCS:
1282    return (Return ? RetCC_ARM_APCS: CC_ARM_APCS);
1283  }
1284}
1285
1286bool ARMFastISel::ProcessCallArgs(SmallVectorImpl<Value*> &Args,
1287                                  SmallVectorImpl<unsigned> &ArgRegs,
1288                                  SmallVectorImpl<EVT> &ArgVTs,
1289                                  SmallVectorImpl<ISD::ArgFlagsTy> &ArgFlags,
1290                                  SmallVectorImpl<unsigned> &RegArgs,
1291                                  CallingConv::ID CC,
1292                                  unsigned &NumBytes) {
1293  SmallVector<CCValAssign, 16> ArgLocs;
1294  CCState CCInfo(CC, false, TM, ArgLocs, *Context);
1295  CCInfo.AnalyzeCallOperands(ArgVTs, ArgFlags, CCAssignFnForCall(CC, false));
1296
1297  // Get a count of how many bytes are to be pushed on the stack.
1298  NumBytes = CCInfo.getNextStackOffset();
1299
1300  // Issue CALLSEQ_START
1301  unsigned AdjStackDown = TM.getRegisterInfo()->getCallFrameSetupOpcode();
1302  AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
1303                          TII.get(AdjStackDown))
1304                  .addImm(NumBytes));
1305
1306  // Process the args.
1307  for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
1308    CCValAssign &VA = ArgLocs[i];
1309    unsigned Arg = ArgRegs[VA.getValNo()];
1310    EVT ArgVT = ArgVTs[VA.getValNo()];
1311
1312    // Handle arg promotion, etc.
1313    switch (VA.getLocInfo()) {
1314      case CCValAssign::Full: break;
1315      case CCValAssign::SExt: {
1316        bool Emitted = FastEmitExtend(ISD::SIGN_EXTEND, VA.getLocVT(),
1317                                         Arg, ArgVT, Arg);
1318        assert(Emitted && "Failed to emit a sext!"); Emitted=Emitted;
1319        Emitted = true;
1320        ArgVT = VA.getLocVT();
1321        break;
1322      }
1323      case CCValAssign::ZExt: {
1324        bool Emitted = FastEmitExtend(ISD::ZERO_EXTEND, VA.getLocVT(),
1325                                         Arg, ArgVT, Arg);
1326        assert(Emitted && "Failed to emit a zext!"); Emitted=Emitted;
1327        Emitted = true;
1328        ArgVT = VA.getLocVT();
1329        break;
1330      }
1331      case CCValAssign::AExt: {
1332        // We don't handle NEON or f64 parameters yet.
1333        if (VA.getLocVT().isVector() && VA.getLocVT().getSizeInBits() >= 64)
1334          return false;
1335        bool Emitted = FastEmitExtend(ISD::ANY_EXTEND, VA.getLocVT(),
1336                                         Arg, ArgVT, Arg);
1337        if (!Emitted)
1338          Emitted = FastEmitExtend(ISD::ZERO_EXTEND, VA.getLocVT(),
1339                                      Arg, ArgVT, Arg);
1340        if (!Emitted)
1341          Emitted = FastEmitExtend(ISD::SIGN_EXTEND, VA.getLocVT(),
1342                                      Arg, ArgVT, Arg);
1343
1344        assert(Emitted && "Failed to emit a aext!"); Emitted=Emitted;
1345        ArgVT = VA.getLocVT();
1346        break;
1347      }
1348      case CCValAssign::BCvt: {
1349        unsigned BC = FastEmit_r(ArgVT.getSimpleVT(),
1350                                 VA.getLocVT().getSimpleVT(),
1351                                 ISD::BIT_CONVERT, Arg, /*TODO: Kill=*/false);
1352        assert(BC != 0 && "Failed to emit a bitcast!");
1353        Arg = BC;
1354        ArgVT = VA.getLocVT();
1355        break;
1356      }
1357      default: llvm_unreachable("Unknown arg promotion!");
1358    }
1359
1360    // Now copy/store arg to correct locations.
1361    if (VA.isRegLoc() && !VA.needsCustom()) {
1362      BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(TargetOpcode::COPY),
1363              VA.getLocReg())
1364      .addReg(Arg);
1365      RegArgs.push_back(VA.getLocReg());
1366    } else if (VA.needsCustom()) {
1367      // TODO: We need custom lowering for vector (v2f64) args.
1368      if (VA.getLocVT() != MVT::f64) return false;
1369
1370      CCValAssign &NextVA = ArgLocs[++i];
1371
1372      // TODO: Only handle register args for now.
1373      if(!(VA.isRegLoc() && NextVA.isRegLoc())) return false;
1374
1375      AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
1376                              TII.get(ARM::VMOVRRD), VA.getLocReg())
1377                      .addReg(NextVA.getLocReg(), RegState::Define)
1378                      .addReg(Arg));
1379      RegArgs.push_back(VA.getLocReg());
1380      RegArgs.push_back(NextVA.getLocReg());
1381    } else {
1382      assert(VA.isMemLoc());
1383      // Need to store on the stack.
1384      unsigned Base = ARM::SP;
1385      int Offset = VA.getLocMemOffset();
1386
1387      if (!ARMEmitStore(ArgVT, Arg, Base, Offset)) return false;
1388    }
1389  }
1390  return true;
1391}
1392
1393bool ARMFastISel::FinishCall(EVT RetVT, SmallVectorImpl<unsigned> &UsedRegs,
1394                             const Instruction *I, CallingConv::ID CC,
1395                             unsigned &NumBytes) {
1396  // Issue CALLSEQ_END
1397  unsigned AdjStackUp = TM.getRegisterInfo()->getCallFrameDestroyOpcode();
1398  AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
1399                          TII.get(AdjStackUp))
1400                  .addImm(NumBytes).addImm(0));
1401
1402  // Now the return value.
1403  if (RetVT.getSimpleVT().SimpleTy != MVT::isVoid) {
1404    SmallVector<CCValAssign, 16> RVLocs;
1405    CCState CCInfo(CC, false, TM, RVLocs, *Context);
1406    CCInfo.AnalyzeCallResult(RetVT, CCAssignFnForCall(CC, true));
1407
1408    // Copy all of the result registers out of their specified physreg.
1409    if (RVLocs.size() == 2 && RetVT.getSimpleVT().SimpleTy == MVT::f64) {
1410      // For this move we copy into two registers and then move into the
1411      // double fp reg we want.
1412      EVT DestVT = RVLocs[0].getValVT();
1413      TargetRegisterClass* DstRC = TLI.getRegClassFor(DestVT);
1414      unsigned ResultReg = createResultReg(DstRC);
1415      AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
1416                              TII.get(ARM::VMOVDRR), ResultReg)
1417                      .addReg(RVLocs[0].getLocReg())
1418                      .addReg(RVLocs[1].getLocReg()));
1419
1420      UsedRegs.push_back(RVLocs[0].getLocReg());
1421      UsedRegs.push_back(RVLocs[1].getLocReg());
1422
1423      // Finally update the result.
1424      UpdateValueMap(I, ResultReg);
1425    } else {
1426      assert(RVLocs.size() == 1 &&"Can't handle non-double multi-reg retvals!");
1427      EVT CopyVT = RVLocs[0].getValVT();
1428      TargetRegisterClass* DstRC = TLI.getRegClassFor(CopyVT);
1429
1430      unsigned ResultReg = createResultReg(DstRC);
1431      BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(TargetOpcode::COPY),
1432              ResultReg).addReg(RVLocs[0].getLocReg());
1433      UsedRegs.push_back(RVLocs[0].getLocReg());
1434
1435      // Finally update the result.
1436      UpdateValueMap(I, ResultReg);
1437    }
1438  }
1439
1440  return true;
1441}
1442
1443// A quick function that will emit a call for a named libcall in F with the
1444// vector of passed arguments for the Instruction in I. We can assume that we
1445// can emit a call for any libcall we can produce. This is an abridged version
1446// of the full call infrastructure since we won't need to worry about things
1447// like computed function pointers or strange arguments at call sites.
1448// TODO: Try to unify this and the normal call bits for ARM, then try to unify
1449// with X86.
1450bool ARMFastISel::ARMEmitLibcall(const Instruction *I, RTLIB::Libcall Call) {
1451  CallingConv::ID CC = TLI.getLibcallCallingConv(Call);
1452
1453  // Handle *simple* calls for now.
1454  const Type *RetTy = I->getType();
1455  EVT RetVT;
1456  if (RetTy->isVoidTy())
1457    RetVT = MVT::isVoid;
1458  else if (!isTypeLegal(RetTy, RetVT))
1459    return false;
1460
1461  // For now we're using BLX etc on the assumption that we have v5t ops.
1462  if (!Subtarget->hasV5TOps()) return false;
1463
1464  // Set up the argument vectors.
1465  SmallVector<Value*, 8> Args;
1466  SmallVector<unsigned, 8> ArgRegs;
1467  SmallVector<EVT, 8> ArgVTs;
1468  SmallVector<ISD::ArgFlagsTy, 8> ArgFlags;
1469  Args.reserve(I->getNumOperands());
1470  ArgRegs.reserve(I->getNumOperands());
1471  ArgVTs.reserve(I->getNumOperands());
1472  ArgFlags.reserve(I->getNumOperands());
1473  for (unsigned i = 0; i < I->getNumOperands(); ++i) {
1474    Value *Op = I->getOperand(i);
1475    unsigned Arg = getRegForValue(Op);
1476    if (Arg == 0) return false;
1477
1478    const Type *ArgTy = Op->getType();
1479    EVT ArgVT;
1480    if (!isTypeLegal(ArgTy, ArgVT)) return false;
1481
1482    ISD::ArgFlagsTy Flags;
1483    unsigned OriginalAlignment = TD.getABITypeAlignment(ArgTy);
1484    Flags.setOrigAlign(OriginalAlignment);
1485
1486    Args.push_back(Op);
1487    ArgRegs.push_back(Arg);
1488    ArgVTs.push_back(ArgVT);
1489    ArgFlags.push_back(Flags);
1490  }
1491
1492  // Handle the arguments now that we've gotten them.
1493  SmallVector<unsigned, 4> RegArgs;
1494  unsigned NumBytes;
1495  if (!ProcessCallArgs(Args, ArgRegs, ArgVTs, ArgFlags, RegArgs, CC, NumBytes))
1496    return false;
1497
1498  // Issue the call, BLXr9 for darwin, BLX otherwise. This uses V5 ops.
1499  // TODO: Turn this into the table of arm call ops.
1500  MachineInstrBuilder MIB;
1501  unsigned CallOpc;
1502  if(isThumb)
1503    CallOpc = Subtarget->isTargetDarwin() ? ARM::tBLXi_r9 : ARM::tBLXi;
1504  else
1505    CallOpc = Subtarget->isTargetDarwin() ? ARM::BLr9 : ARM::BL;
1506  MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(CallOpc))
1507        .addExternalSymbol(TLI.getLibcallName(Call));
1508
1509  // Add implicit physical register uses to the call.
1510  for (unsigned i = 0, e = RegArgs.size(); i != e; ++i)
1511    MIB.addReg(RegArgs[i]);
1512
1513  // Finish off the call including any return values.
1514  SmallVector<unsigned, 4> UsedRegs;
1515  if (!FinishCall(RetVT, UsedRegs, I, CC, NumBytes)) return false;
1516
1517  // Set all unused physreg defs as dead.
1518  static_cast<MachineInstr *>(MIB)->setPhysRegsDeadExcept(UsedRegs, TRI);
1519
1520  return true;
1521}
1522
1523bool ARMFastISel::SelectCall(const Instruction *I) {
1524  const CallInst *CI = cast<CallInst>(I);
1525  const Value *Callee = CI->getCalledValue();
1526
1527  // Can't handle inline asm or worry about intrinsics yet.
1528  if (isa<InlineAsm>(Callee) || isa<IntrinsicInst>(CI)) return false;
1529
1530  // Only handle global variable Callees that are direct calls.
1531  const GlobalValue *GV = dyn_cast<GlobalValue>(Callee);
1532  if (!GV || Subtarget->GVIsIndirectSymbol(GV, TM.getRelocationModel()))
1533    return false;
1534
1535  // Check the calling convention.
1536  ImmutableCallSite CS(CI);
1537  CallingConv::ID CC = CS.getCallingConv();
1538
1539  // TODO: Avoid some calling conventions?
1540
1541  // Let SDISel handle vararg functions.
1542  const PointerType *PT = cast<PointerType>(CS.getCalledValue()->getType());
1543  const FunctionType *FTy = cast<FunctionType>(PT->getElementType());
1544  if (FTy->isVarArg())
1545    return false;
1546
1547  // Handle *simple* calls for now.
1548  const Type *RetTy = I->getType();
1549  EVT RetVT;
1550  if (RetTy->isVoidTy())
1551    RetVT = MVT::isVoid;
1552  else if (!isTypeLegal(RetTy, RetVT))
1553    return false;
1554
1555  // For now we're using BLX etc on the assumption that we have v5t ops.
1556  // TODO: Maybe?
1557  if (!Subtarget->hasV5TOps()) return false;
1558
1559  // Set up the argument vectors.
1560  SmallVector<Value*, 8> Args;
1561  SmallVector<unsigned, 8> ArgRegs;
1562  SmallVector<EVT, 8> ArgVTs;
1563  SmallVector<ISD::ArgFlagsTy, 8> ArgFlags;
1564  Args.reserve(CS.arg_size());
1565  ArgRegs.reserve(CS.arg_size());
1566  ArgVTs.reserve(CS.arg_size());
1567  ArgFlags.reserve(CS.arg_size());
1568  for (ImmutableCallSite::arg_iterator i = CS.arg_begin(), e = CS.arg_end();
1569       i != e; ++i) {
1570    unsigned Arg = getRegForValue(*i);
1571
1572    if (Arg == 0)
1573      return false;
1574    ISD::ArgFlagsTy Flags;
1575    unsigned AttrInd = i - CS.arg_begin() + 1;
1576    if (CS.paramHasAttr(AttrInd, Attribute::SExt))
1577      Flags.setSExt();
1578    if (CS.paramHasAttr(AttrInd, Attribute::ZExt))
1579      Flags.setZExt();
1580
1581         // FIXME: Only handle *easy* calls for now.
1582    if (CS.paramHasAttr(AttrInd, Attribute::InReg) ||
1583        CS.paramHasAttr(AttrInd, Attribute::StructRet) ||
1584        CS.paramHasAttr(AttrInd, Attribute::Nest) ||
1585        CS.paramHasAttr(AttrInd, Attribute::ByVal))
1586      return false;
1587
1588    const Type *ArgTy = (*i)->getType();
1589    EVT ArgVT;
1590    if (!isTypeLegal(ArgTy, ArgVT))
1591      return false;
1592    unsigned OriginalAlignment = TD.getABITypeAlignment(ArgTy);
1593    Flags.setOrigAlign(OriginalAlignment);
1594
1595    Args.push_back(*i);
1596    ArgRegs.push_back(Arg);
1597    ArgVTs.push_back(ArgVT);
1598    ArgFlags.push_back(Flags);
1599  }
1600
1601  // Handle the arguments now that we've gotten them.
1602  SmallVector<unsigned, 4> RegArgs;
1603  unsigned NumBytes;
1604  if (!ProcessCallArgs(Args, ArgRegs, ArgVTs, ArgFlags, RegArgs, CC, NumBytes))
1605    return false;
1606
1607  // Issue the call, BLXr9 for darwin, BLX otherwise. This uses V5 ops.
1608  // TODO: Turn this into the table of arm call ops.
1609  MachineInstrBuilder MIB;
1610  unsigned CallOpc;
1611  if(isThumb)
1612    CallOpc = Subtarget->isTargetDarwin() ? ARM::tBLXi_r9 : ARM::tBLXi;
1613  else
1614    CallOpc = Subtarget->isTargetDarwin() ? ARM::BLr9 : ARM::BL;
1615  MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(CallOpc))
1616              .addGlobalAddress(GV, 0, 0);
1617
1618  // Add implicit physical register uses to the call.
1619  for (unsigned i = 0, e = RegArgs.size(); i != e; ++i)
1620    MIB.addReg(RegArgs[i]);
1621
1622  // Finish off the call including any return values.
1623  SmallVector<unsigned, 4> UsedRegs;
1624  if (!FinishCall(RetVT, UsedRegs, I, CC, NumBytes)) return false;
1625
1626  // Set all unused physreg defs as dead.
1627  static_cast<MachineInstr *>(MIB)->setPhysRegsDeadExcept(UsedRegs, TRI);
1628
1629  return true;
1630
1631}
1632
1633// TODO: SoftFP support.
1634bool ARMFastISel::TargetSelectInstruction(const Instruction *I) {
1635  // No Thumb-1 for now.
1636  if (isThumb && !AFI->isThumb2Function()) return false;
1637
1638  switch (I->getOpcode()) {
1639    case Instruction::Load:
1640      return SelectLoad(I);
1641    case Instruction::Store:
1642      return SelectStore(I);
1643    case Instruction::Br:
1644      return SelectBranch(I);
1645    case Instruction::ICmp:
1646    case Instruction::FCmp:
1647      return SelectCmp(I);
1648    case Instruction::FPExt:
1649      return SelectFPExt(I);
1650    case Instruction::FPTrunc:
1651      return SelectFPTrunc(I);
1652    case Instruction::SIToFP:
1653      return SelectSIToFP(I);
1654    case Instruction::FPToSI:
1655      return SelectFPToSI(I);
1656    case Instruction::FAdd:
1657      return SelectBinaryOp(I, ISD::FADD);
1658    case Instruction::FSub:
1659      return SelectBinaryOp(I, ISD::FSUB);
1660    case Instruction::FMul:
1661      return SelectBinaryOp(I, ISD::FMUL);
1662    case Instruction::SDiv:
1663      return SelectSDiv(I);
1664    case Instruction::SRem:
1665      return SelectSRem(I);
1666    case Instruction::Call:
1667      return SelectCall(I);
1668    case Instruction::Select:
1669      return SelectSelect(I);
1670    default: break;
1671  }
1672  return false;
1673}
1674
1675namespace llvm {
1676  llvm::FastISel *ARM::createFastISel(FunctionLoweringInfo &funcInfo) {
1677    // Completely untested on non-darwin.
1678    const TargetMachine &TM = funcInfo.MF->getTarget();
1679    const ARMSubtarget *Subtarget = &TM.getSubtarget<ARMSubtarget>();
1680    if (Subtarget->isTargetDarwin() && !DisableARMFastISel)
1681      return new ARMFastISel(funcInfo);
1682    return 0;
1683  }
1684}
1685