ARMISelDAGToDAG.cpp revision 1c8f0536b3a19c0ff9f5a8ba039a771c4bb2bfbc 
1//===-- ARMISelDAGToDAG.cpp - A dag to dag inst selector for ARM ----------===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file was developed by Chris Lattner and is distributed under
6// the University of Illinois Open Source License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file defines an instruction selector for the ARM target.
11//
12//===----------------------------------------------------------------------===//
13
14#include "ARM.h"
15#include "ARMTargetMachine.h"
16#include "llvm/DerivedTypes.h"
17#include "llvm/Function.h"
18#include "llvm/Intrinsics.h"
19#include "llvm/CodeGen/MachineFrameInfo.h"
20#include "llvm/CodeGen/MachineFunction.h"
21#include "llvm/CodeGen/MachineInstrBuilder.h"
22#include "llvm/CodeGen/SelectionDAG.h"
23#include "llvm/CodeGen/SelectionDAGISel.h"
24#include "llvm/CodeGen/SSARegMap.h"
25#include "llvm/Target/TargetLowering.h"
26#include "llvm/Support/Debug.h"
27#include <iostream>
28#include <set>
29using namespace llvm;
30
31namespace ARMISD {
32  enum {
33    FIRST_NUMBER = ISD::BUILTIN_OP_END+ARM::INSTRUCTION_LIST_END,
34    RET_FLAG,
35  };
36}
37
38namespace {
39  class ARMTargetLowering : public TargetLowering {
40  public:
41    ARMTargetLowering(TargetMachine &TM);
42    virtual SDOperand LowerOperation(SDOperand Op, SelectionDAG &DAG);
43
44    virtual std::pair<SDOperand, SDOperand>
45      LowerCallTo(SDOperand Chain, const Type *RetTy, bool isVarArg,
46                  unsigned CC,
47                  bool isTailCall, SDOperand Callee, ArgListTy &Args,
48                  SelectionDAG &DAG);
49
50  };
51
52}
53
54ARMTargetLowering::ARMTargetLowering(TargetMachine &TM)
55  : TargetLowering(TM) {
56  setOperationAction(ISD::RET, MVT::Other, Custom);
57}
58
59std::pair<SDOperand, SDOperand>
60ARMTargetLowering::LowerCallTo(SDOperand Chain, const Type *RetTy,
61                                 bool isVarArg, unsigned CC,
62                                 bool isTailCall, SDOperand Callee,
63                                 ArgListTy &Args, SelectionDAG &DAG) {
64  assert(0 && "Not implemented");
65  abort();
66}
67
68static SDOperand LowerRET(SDOperand Op, SelectionDAG &DAG) {
69  SDOperand Copy;
70  switch(Op.getNumOperands()) {
71  default:
72    assert(0 && "Do not know how to return this many arguments!");
73    abort();
74  case 1:
75    return SDOperand(); // ret void is legal
76  case 2:
77    Copy = DAG.getCopyToReg(Op.getOperand(0), ARM::R0, Op.getOperand(1), SDOperand());
78    break;
79  }
80
81  return DAG.getNode(ARMISD::RET_FLAG, MVT::Other, Copy, Copy.getValue(1));
82}
83
84SDOperand ARMTargetLowering::LowerOperation(SDOperand Op, SelectionDAG &DAG) {
85  switch (Op.getOpcode()) {
86  default:
87    assert(0 && "Should not custom lower this!");
88    abort();
89  case ISD::RET:
90    return LowerRET(Op, DAG);
91  }
92}
93
94//===----------------------------------------------------------------------===//
95// Instruction Selector Implementation
96//===----------------------------------------------------------------------===//
97
98//===--------------------------------------------------------------------===//
99/// ARMDAGToDAGISel - ARM specific code to select ARM machine
100/// instructions for SelectionDAG operations.
101///
102namespace {
103class ARMDAGToDAGISel : public SelectionDAGISel {
104  ARMTargetLowering Lowering;
105
106public:
107  ARMDAGToDAGISel(TargetMachine &TM)
108    : SelectionDAGISel(Lowering), Lowering(TM) {
109  }
110
111  void Select(SDOperand &Result, SDOperand Op);
112  virtual void InstructionSelectBasicBlock(SelectionDAG &DAG);
113
114  // Include the pieces autogenerated from the target description.
115#include "ARMGenDAGISel.inc"
116};
117
118void ARMDAGToDAGISel::InstructionSelectBasicBlock(SelectionDAG &DAG) {
119  DEBUG(BB->dump());
120
121  DAG.setRoot(SelectRoot(DAG.getRoot()));
122  CodeGenMap.clear();
123  DAG.RemoveDeadNodes();
124
125  ScheduleAndEmitDAG(DAG);
126}
127
128void ARMDAGToDAGISel::Select(SDOperand &Result, SDOperand Op) {
129  SelectCode(Result, Op);
130}
131
132}  // end anonymous namespace
133
134/// createARMISelDag - This pass converts a legalized DAG into a
135/// ARM-specific DAG, ready for instruction scheduling.
136///
137FunctionPass *llvm::createARMISelDag(TargetMachine &TM) {
138  return new ARMDAGToDAGISel(TM);
139}
140