ARMISelDAGToDAG.cpp revision a028cb524487151b2462e0daa849eee3fc50564e 
1//===-- ARMISelDAGToDAG.cpp - A dag to dag inst selector for ARM ----------===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file defines an instruction selector for the ARM target.
11//
12//===----------------------------------------------------------------------===//
13
14#define DEBUG_TYPE "arm-isel"
15#include "ARM.h"
16#include "ARMBaseInstrInfo.h"
17#include "ARMTargetMachine.h"
18#include "MCTargetDesc/ARMAddressingModes.h"
19#include "llvm/CallingConv.h"
20#include "llvm/Constants.h"
21#include "llvm/DerivedTypes.h"
22#include "llvm/Function.h"
23#include "llvm/Intrinsics.h"
24#include "llvm/LLVMContext.h"
25#include "llvm/CodeGen/MachineFrameInfo.h"
26#include "llvm/CodeGen/MachineFunction.h"
27#include "llvm/CodeGen/MachineInstrBuilder.h"
28#include "llvm/CodeGen/SelectionDAG.h"
29#include "llvm/CodeGen/SelectionDAGISel.h"
30#include "llvm/Target/TargetLowering.h"
31#include "llvm/Target/TargetOptions.h"
32#include "llvm/Support/CommandLine.h"
33#include "llvm/Support/Compiler.h"
34#include "llvm/Support/Debug.h"
35#include "llvm/Support/ErrorHandling.h"
36#include "llvm/Support/raw_ostream.h"
37
38using namespace llvm;
39
40static cl::opt<bool>
41DisableShifterOp("disable-shifter-op", cl::Hidden,
42  cl::desc("Disable isel of shifter-op"),
43  cl::init(false));
44
45static cl::opt<bool>
46CheckVMLxHazard("check-vmlx-hazard", cl::Hidden,
47  cl::desc("Check fp vmla / vmls hazard at isel time"),
48  cl::init(true));
49
50static cl::opt<bool>
51DisableARMIntABS("disable-arm-int-abs", cl::Hidden,
52  cl::desc("Enable / disable ARM integer abs transform"),
53  cl::init(false));
54
55//===--------------------------------------------------------------------===//
56/// ARMDAGToDAGISel - ARM specific code to select ARM machine
57/// instructions for SelectionDAG operations.
58///
59namespace {
60
61enum AddrMode2Type {
62  AM2_BASE, // Simple AM2 (+-imm12)
63  AM2_SHOP  // Shifter-op AM2
64};
65
66class ARMDAGToDAGISel : public SelectionDAGISel {
67  ARMBaseTargetMachine &TM;
68  const ARMBaseInstrInfo *TII;
69
70  /// Subtarget - Keep a pointer to the ARMSubtarget around so that we can
71  /// make the right decision when generating code for different targets.
72  const ARMSubtarget *Subtarget;
73
74public:
75  explicit ARMDAGToDAGISel(ARMBaseTargetMachine &tm,
76                           CodeGenOpt::Level OptLevel)
77    : SelectionDAGISel(tm, OptLevel), TM(tm),
78      TII(static_cast<const ARMBaseInstrInfo*>(TM.getInstrInfo())),
79      Subtarget(&TM.getSubtarget<ARMSubtarget>()) {
80  }
81
82  virtual const char *getPassName() const {
83    return "ARM Instruction Selection";
84  }
85
86  /// getI32Imm - Return a target constant of type i32 with the specified
87  /// value.
88  inline SDValue getI32Imm(unsigned Imm) {
89    return CurDAG->getTargetConstant(Imm, MVT::i32);
90  }
91
92  SDNode *Select(SDNode *N);
93
94
95  bool hasNoVMLxHazardUse(SDNode *N) const;
96  bool isShifterOpProfitable(const SDValue &Shift,
97                             ARM_AM::ShiftOpc ShOpcVal, unsigned ShAmt);
98  bool SelectRegShifterOperand(SDValue N, SDValue &A,
99                               SDValue &B, SDValue &C,
100                               bool CheckProfitability = true);
101  bool SelectImmShifterOperand(SDValue N, SDValue &A,
102                               SDValue &B, bool CheckProfitability = true);
103  bool SelectShiftRegShifterOperand(SDValue N, SDValue &A,
104                                    SDValue &B, SDValue &C) {
105    // Don't apply the profitability check
106    return SelectRegShifterOperand(N, A, B, C, false);
107  }
108  bool SelectShiftImmShifterOperand(SDValue N, SDValue &A,
109                                    SDValue &B) {
110    // Don't apply the profitability check
111    return SelectImmShifterOperand(N, A, B, false);
112  }
113
114  bool SelectAddrModeImm12(SDValue N, SDValue &Base, SDValue &OffImm);
115  bool SelectLdStSOReg(SDValue N, SDValue &Base, SDValue &Offset, SDValue &Opc);
116
117  AddrMode2Type SelectAddrMode2Worker(SDValue N, SDValue &Base,
118                                      SDValue &Offset, SDValue &Opc);
119  bool SelectAddrMode2Base(SDValue N, SDValue &Base, SDValue &Offset,
120                           SDValue &Opc) {
121    return SelectAddrMode2Worker(N, Base, Offset, Opc) == AM2_BASE;
122  }
123
124  bool SelectAddrMode2ShOp(SDValue N, SDValue &Base, SDValue &Offset,
125                           SDValue &Opc) {
126    return SelectAddrMode2Worker(N, Base, Offset, Opc) == AM2_SHOP;
127  }
128
129  bool SelectAddrMode2(SDValue N, SDValue &Base, SDValue &Offset,
130                       SDValue &Opc) {
131    SelectAddrMode2Worker(N, Base, Offset, Opc);
132//    return SelectAddrMode2ShOp(N, Base, Offset, Opc);
133    // This always matches one way or another.
134    return true;
135  }
136
137  bool SelectAddrMode2OffsetReg(SDNode *Op, SDValue N,
138                             SDValue &Offset, SDValue &Opc);
139  bool SelectAddrMode2OffsetImm(SDNode *Op, SDValue N,
140                             SDValue &Offset, SDValue &Opc);
141  bool SelectAddrMode2OffsetImmPre(SDNode *Op, SDValue N,
142                             SDValue &Offset, SDValue &Opc);
143  bool SelectAddrOffsetNone(SDValue N, SDValue &Base);
144  bool SelectAddrMode3(SDValue N, SDValue &Base,
145                       SDValue &Offset, SDValue &Opc);
146  bool SelectAddrMode3Offset(SDNode *Op, SDValue N,
147                             SDValue &Offset, SDValue &Opc);
148  bool SelectAddrMode5(SDValue N, SDValue &Base,
149                       SDValue &Offset);
150  bool SelectAddrMode6(SDNode *Parent, SDValue N, SDValue &Addr,SDValue &Align);
151  bool SelectAddrMode6Offset(SDNode *Op, SDValue N, SDValue &Offset);
152
153  bool SelectAddrModePC(SDValue N, SDValue &Offset, SDValue &Label);
154
155  // Thumb Addressing Modes:
156  bool SelectThumbAddrModeRR(SDValue N, SDValue &Base, SDValue &Offset);
157  bool SelectThumbAddrModeRI(SDValue N, SDValue &Base, SDValue &Offset,
158                             unsigned Scale);
159  bool SelectThumbAddrModeRI5S1(SDValue N, SDValue &Base, SDValue &Offset);
160  bool SelectThumbAddrModeRI5S2(SDValue N, SDValue &Base, SDValue &Offset);
161  bool SelectThumbAddrModeRI5S4(SDValue N, SDValue &Base, SDValue &Offset);
162  bool SelectThumbAddrModeImm5S(SDValue N, unsigned Scale, SDValue &Base,
163                                SDValue &OffImm);
164  bool SelectThumbAddrModeImm5S1(SDValue N, SDValue &Base,
165                                 SDValue &OffImm);
166  bool SelectThumbAddrModeImm5S2(SDValue N, SDValue &Base,
167                                 SDValue &OffImm);
168  bool SelectThumbAddrModeImm5S4(SDValue N, SDValue &Base,
169                                 SDValue &OffImm);
170  bool SelectThumbAddrModeSP(SDValue N, SDValue &Base, SDValue &OffImm);
171
172  // Thumb 2 Addressing Modes:
173  bool SelectT2ShifterOperandReg(SDValue N,
174                                 SDValue &BaseReg, SDValue &Opc);
175  bool SelectT2AddrModeImm12(SDValue N, SDValue &Base, SDValue &OffImm);
176  bool SelectT2AddrModeImm8(SDValue N, SDValue &Base,
177                            SDValue &OffImm);
178  bool SelectT2AddrModeImm8Offset(SDNode *Op, SDValue N,
179                                 SDValue &OffImm);
180  bool SelectT2AddrModeSoReg(SDValue N, SDValue &Base,
181                             SDValue &OffReg, SDValue &ShImm);
182
183  inline bool is_so_imm(unsigned Imm) const {
184    return ARM_AM::getSOImmVal(Imm) != -1;
185  }
186
187  inline bool is_so_imm_not(unsigned Imm) const {
188    return ARM_AM::getSOImmVal(~Imm) != -1;
189  }
190
191  inline bool is_t2_so_imm(unsigned Imm) const {
192    return ARM_AM::getT2SOImmVal(Imm) != -1;
193  }
194
195  inline bool is_t2_so_imm_not(unsigned Imm) const {
196    return ARM_AM::getT2SOImmVal(~Imm) != -1;
197  }
198
199  // Include the pieces autogenerated from the target description.
200#include "ARMGenDAGISel.inc"
201
202private:
203  /// SelectARMIndexedLoad - Indexed (pre/post inc/dec) load matching code for
204  /// ARM.
205  SDNode *SelectARMIndexedLoad(SDNode *N);
206  SDNode *SelectT2IndexedLoad(SDNode *N);
207
208  /// SelectVLD - Select NEON load intrinsics.  NumVecs should be
209  /// 1, 2, 3 or 4.  The opcode arrays specify the instructions used for
210  /// loads of D registers and even subregs and odd subregs of Q registers.
211  /// For NumVecs <= 2, QOpcodes1 is not used.
212  SDNode *SelectVLD(SDNode *N, bool isUpdating, unsigned NumVecs,
213                    unsigned *DOpcodes,
214                    unsigned *QOpcodes0, unsigned *QOpcodes1);
215
216  /// SelectVST - Select NEON store intrinsics.  NumVecs should
217  /// be 1, 2, 3 or 4.  The opcode arrays specify the instructions used for
218  /// stores of D registers and even subregs and odd subregs of Q registers.
219  /// For NumVecs <= 2, QOpcodes1 is not used.
220  SDNode *SelectVST(SDNode *N, bool isUpdating, unsigned NumVecs,
221                    unsigned *DOpcodes,
222                    unsigned *QOpcodes0, unsigned *QOpcodes1);
223
224  /// SelectVLDSTLane - Select NEON load/store lane intrinsics.  NumVecs should
225  /// be 2, 3 or 4.  The opcode arrays specify the instructions used for
226  /// load/store of D registers and Q registers.
227  SDNode *SelectVLDSTLane(SDNode *N, bool IsLoad,
228                          bool isUpdating, unsigned NumVecs,
229                          unsigned *DOpcodes, unsigned *QOpcodes);
230
231  /// SelectVLDDup - Select NEON load-duplicate intrinsics.  NumVecs
232  /// should be 2, 3 or 4.  The opcode array specifies the instructions used
233  /// for loading D registers.  (Q registers are not supported.)
234  SDNode *SelectVLDDup(SDNode *N, bool isUpdating, unsigned NumVecs,
235                       unsigned *Opcodes);
236
237  /// SelectVTBL - Select NEON VTBL and VTBX intrinsics.  NumVecs should be 2,
238  /// 3 or 4.  These are custom-selected so that a REG_SEQUENCE can be
239  /// generated to force the table registers to be consecutive.
240  SDNode *SelectVTBL(SDNode *N, bool IsExt, unsigned NumVecs, unsigned Opc);
241
242  /// SelectV6T2BitfieldExtractOp - Select SBFX/UBFX instructions for ARM.
243  SDNode *SelectV6T2BitfieldExtractOp(SDNode *N, bool isSigned);
244
245  /// SelectCMOVOp - Select CMOV instructions for ARM.
246  SDNode *SelectCMOVOp(SDNode *N);
247  SDNode *SelectT2CMOVShiftOp(SDNode *N, SDValue FalseVal, SDValue TrueVal,
248                              ARMCC::CondCodes CCVal, SDValue CCR,
249                              SDValue InFlag);
250  SDNode *SelectARMCMOVShiftOp(SDNode *N, SDValue FalseVal, SDValue TrueVal,
251                               ARMCC::CondCodes CCVal, SDValue CCR,
252                               SDValue InFlag);
253  SDNode *SelectT2CMOVImmOp(SDNode *N, SDValue FalseVal, SDValue TrueVal,
254                              ARMCC::CondCodes CCVal, SDValue CCR,
255                              SDValue InFlag);
256  SDNode *SelectARMCMOVImmOp(SDNode *N, SDValue FalseVal, SDValue TrueVal,
257                               ARMCC::CondCodes CCVal, SDValue CCR,
258                               SDValue InFlag);
259
260  // Select special operations if node forms integer ABS pattern
261  SDNode *SelectABSOp(SDNode *N);
262
263  SDNode *SelectConcatVector(SDNode *N);
264
265  SDNode *SelectAtomic64(SDNode *Node, unsigned Opc);
266
267  /// SelectInlineAsmMemoryOperand - Implement addressing mode selection for
268  /// inline asm expressions.
269  virtual bool SelectInlineAsmMemoryOperand(const SDValue &Op,
270                                            char ConstraintCode,
271                                            std::vector<SDValue> &OutOps);
272
273  // Form pairs of consecutive S, D, or Q registers.
274  SDNode *PairSRegs(EVT VT, SDValue V0, SDValue V1);
275  SDNode *PairDRegs(EVT VT, SDValue V0, SDValue V1);
276  SDNode *PairQRegs(EVT VT, SDValue V0, SDValue V1);
277
278  // Form sequences of 4 consecutive S, D, or Q registers.
279  SDNode *QuadSRegs(EVT VT, SDValue V0, SDValue V1, SDValue V2, SDValue V3);
280  SDNode *QuadDRegs(EVT VT, SDValue V0, SDValue V1, SDValue V2, SDValue V3);
281  SDNode *QuadQRegs(EVT VT, SDValue V0, SDValue V1, SDValue V2, SDValue V3);
282
283  // Get the alignment operand for a NEON VLD or VST instruction.
284  SDValue GetVLDSTAlign(SDValue Align, unsigned NumVecs, bool is64BitVector);
285};
286}
287
288/// isInt32Immediate - This method tests to see if the node is a 32-bit constant
289/// operand. If so Imm will receive the 32-bit value.
290static bool isInt32Immediate(SDNode *N, unsigned &Imm) {
291  if (N->getOpcode() == ISD::Constant && N->getValueType(0) == MVT::i32) {
292    Imm = cast<ConstantSDNode>(N)->getZExtValue();
293    return true;
294  }
295  return false;
296}
297
298// isInt32Immediate - This method tests to see if a constant operand.
299// If so Imm will receive the 32 bit value.
300static bool isInt32Immediate(SDValue N, unsigned &Imm) {
301  return isInt32Immediate(N.getNode(), Imm);
302}
303
304// isOpcWithIntImmediate - This method tests to see if the node is a specific
305// opcode and that it has a immediate integer right operand.
306// If so Imm will receive the 32 bit value.
307static bool isOpcWithIntImmediate(SDNode *N, unsigned Opc, unsigned& Imm) {
308  return N->getOpcode() == Opc &&
309         isInt32Immediate(N->getOperand(1).getNode(), Imm);
310}
311
312/// \brief Check whether a particular node is a constant value representable as
313/// (N * Scale) where (N in [\arg RangeMin, \arg RangeMax).
314///
315/// \param ScaledConstant [out] - On success, the pre-scaled constant value.
316static bool isScaledConstantInRange(SDValue Node, int Scale,
317                                    int RangeMin, int RangeMax,
318                                    int &ScaledConstant) {
319  assert(Scale > 0 && "Invalid scale!");
320
321  // Check that this is a constant.
322  const ConstantSDNode *C = dyn_cast<ConstantSDNode>(Node);
323  if (!C)
324    return false;
325
326  ScaledConstant = (int) C->getZExtValue();
327  if ((ScaledConstant % Scale) != 0)
328    return false;
329
330  ScaledConstant /= Scale;
331  return ScaledConstant >= RangeMin && ScaledConstant < RangeMax;
332}
333
334/// hasNoVMLxHazardUse - Return true if it's desirable to select a FP MLA / MLS
335/// node. VFP / NEON fp VMLA / VMLS instructions have special RAW hazards (at
336/// least on current ARM implementations) which should be avoidded.
337bool ARMDAGToDAGISel::hasNoVMLxHazardUse(SDNode *N) const {
338  if (OptLevel == CodeGenOpt::None)
339    return true;
340
341  if (!CheckVMLxHazard)
342    return true;
343
344  if (!Subtarget->isCortexA8() && !Subtarget->isCortexA9())
345    return true;
346
347  if (!N->hasOneUse())
348    return false;
349
350  SDNode *Use = *N->use_begin();
351  if (Use->getOpcode() == ISD::CopyToReg)
352    return true;
353  if (Use->isMachineOpcode()) {
354    const MCInstrDesc &MCID = TII->get(Use->getMachineOpcode());
355    if (MCID.mayStore())
356      return true;
357    unsigned Opcode = MCID.getOpcode();
358    if (Opcode == ARM::VMOVRS || Opcode == ARM::VMOVRRD)
359      return true;
360    // vmlx feeding into another vmlx. We actually want to unfold
361    // the use later in the MLxExpansion pass. e.g.
362    // vmla
363    // vmla (stall 8 cycles)
364    //
365    // vmul (5 cycles)
366    // vadd (5 cycles)
367    // vmla
368    // This adds up to about 18 - 19 cycles.
369    //
370    // vmla
371    // vmul (stall 4 cycles)
372    // vadd adds up to about 14 cycles.
373    return TII->isFpMLxInstruction(Opcode);
374  }
375
376  return false;
377}
378
379bool ARMDAGToDAGISel::isShifterOpProfitable(const SDValue &Shift,
380                                            ARM_AM::ShiftOpc ShOpcVal,
381                                            unsigned ShAmt) {
382  if (!Subtarget->isCortexA9())
383    return true;
384  if (Shift.hasOneUse())
385    return true;
386  // R << 2 is free.
387  return ShOpcVal == ARM_AM::lsl && ShAmt == 2;
388}
389
390bool ARMDAGToDAGISel::SelectImmShifterOperand(SDValue N,
391                                              SDValue &BaseReg,
392                                              SDValue &Opc,
393                                              bool CheckProfitability) {
394  if (DisableShifterOp)
395    return false;
396
397  ARM_AM::ShiftOpc ShOpcVal = ARM_AM::getShiftOpcForNode(N.getOpcode());
398
399  // Don't match base register only case. That is matched to a separate
400  // lower complexity pattern with explicit register operand.
401  if (ShOpcVal == ARM_AM::no_shift) return false;
402
403  BaseReg = N.getOperand(0);
404  unsigned ShImmVal = 0;
405  ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N.getOperand(1));
406  if (!RHS) return false;
407  ShImmVal = RHS->getZExtValue() & 31;
408  Opc = CurDAG->getTargetConstant(ARM_AM::getSORegOpc(ShOpcVal, ShImmVal),
409                                  MVT::i32);
410  return true;
411}
412
413bool ARMDAGToDAGISel::SelectRegShifterOperand(SDValue N,
414                                              SDValue &BaseReg,
415                                              SDValue &ShReg,
416                                              SDValue &Opc,
417                                              bool CheckProfitability) {
418  if (DisableShifterOp)
419    return false;
420
421  ARM_AM::ShiftOpc ShOpcVal = ARM_AM::getShiftOpcForNode(N.getOpcode());
422
423  // Don't match base register only case. That is matched to a separate
424  // lower complexity pattern with explicit register operand.
425  if (ShOpcVal == ARM_AM::no_shift) return false;
426
427  BaseReg = N.getOperand(0);
428  unsigned ShImmVal = 0;
429  ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N.getOperand(1));
430  if (RHS) return false;
431
432  ShReg = N.getOperand(1);
433  if (CheckProfitability && !isShifterOpProfitable(N, ShOpcVal, ShImmVal))
434    return false;
435  Opc = CurDAG->getTargetConstant(ARM_AM::getSORegOpc(ShOpcVal, ShImmVal),
436                                  MVT::i32);
437  return true;
438}
439
440
441bool ARMDAGToDAGISel::SelectAddrModeImm12(SDValue N,
442                                          SDValue &Base,
443                                          SDValue &OffImm) {
444  // Match simple R + imm12 operands.
445
446  // Base only.
447  if (N.getOpcode() != ISD::ADD && N.getOpcode() != ISD::SUB &&
448      !CurDAG->isBaseWithConstantOffset(N)) {
449    if (N.getOpcode() == ISD::FrameIndex) {
450      // Match frame index.
451      int FI = cast<FrameIndexSDNode>(N)->getIndex();
452      Base = CurDAG->getTargetFrameIndex(FI, TLI.getPointerTy());
453      OffImm  = CurDAG->getTargetConstant(0, MVT::i32);
454      return true;
455    }
456
457    if (N.getOpcode() == ARMISD::Wrapper &&
458        !(Subtarget->useMovt() &&
459                     N.getOperand(0).getOpcode() == ISD::TargetGlobalAddress)) {
460      Base = N.getOperand(0);
461    } else
462      Base = N;
463    OffImm  = CurDAG->getTargetConstant(0, MVT::i32);
464    return true;
465  }
466
467  if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N.getOperand(1))) {
468    int RHSC = (int)RHS->getZExtValue();
469    if (N.getOpcode() == ISD::SUB)
470      RHSC = -RHSC;
471
472    if (RHSC >= 0 && RHSC < 0x1000) { // 12 bits (unsigned)
473      Base   = N.getOperand(0);
474      if (Base.getOpcode() == ISD::FrameIndex) {
475        int FI = cast<FrameIndexSDNode>(Base)->getIndex();
476        Base = CurDAG->getTargetFrameIndex(FI, TLI.getPointerTy());
477      }
478      OffImm = CurDAG->getTargetConstant(RHSC, MVT::i32);
479      return true;
480    }
481  }
482
483  // Base only.
484  Base = N;
485  OffImm  = CurDAG->getTargetConstant(0, MVT::i32);
486  return true;
487}
488
489
490
491bool ARMDAGToDAGISel::SelectLdStSOReg(SDValue N, SDValue &Base, SDValue &Offset,
492                                      SDValue &Opc) {
493  if (N.getOpcode() == ISD::MUL &&
494      (!Subtarget->isCortexA9() || N.hasOneUse())) {
495    if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N.getOperand(1))) {
496      // X * [3,5,9] -> X + X * [2,4,8] etc.
497      int RHSC = (int)RHS->getZExtValue();
498      if (RHSC & 1) {
499        RHSC = RHSC & ~1;
500        ARM_AM::AddrOpc AddSub = ARM_AM::add;
501        if (RHSC < 0) {
502          AddSub = ARM_AM::sub;
503          RHSC = - RHSC;
504        }
505        if (isPowerOf2_32(RHSC)) {
506          unsigned ShAmt = Log2_32(RHSC);
507          Base = Offset = N.getOperand(0);
508          Opc = CurDAG->getTargetConstant(ARM_AM::getAM2Opc(AddSub, ShAmt,
509                                                            ARM_AM::lsl),
510                                          MVT::i32);
511          return true;
512        }
513      }
514    }
515  }
516
517  if (N.getOpcode() != ISD::ADD && N.getOpcode() != ISD::SUB &&
518      // ISD::OR that is equivalent to an ISD::ADD.
519      !CurDAG->isBaseWithConstantOffset(N))
520    return false;
521
522  // Leave simple R +/- imm12 operands for LDRi12
523  if (N.getOpcode() == ISD::ADD || N.getOpcode() == ISD::OR) {
524    int RHSC;
525    if (isScaledConstantInRange(N.getOperand(1), /*Scale=*/1,
526                                -0x1000+1, 0x1000, RHSC)) // 12 bits.
527      return false;
528  }
529
530  // Otherwise this is R +/- [possibly shifted] R.
531  ARM_AM::AddrOpc AddSub = N.getOpcode() == ISD::SUB ? ARM_AM::sub:ARM_AM::add;
532  ARM_AM::ShiftOpc ShOpcVal =
533    ARM_AM::getShiftOpcForNode(N.getOperand(1).getOpcode());
534  unsigned ShAmt = 0;
535
536  Base   = N.getOperand(0);
537  Offset = N.getOperand(1);
538
539  if (ShOpcVal != ARM_AM::no_shift) {
540    // Check to see if the RHS of the shift is a constant, if not, we can't fold
541    // it.
542    if (ConstantSDNode *Sh =
543           dyn_cast<ConstantSDNode>(N.getOperand(1).getOperand(1))) {
544      ShAmt = Sh->getZExtValue();
545      if (isShifterOpProfitable(Offset, ShOpcVal, ShAmt))
546        Offset = N.getOperand(1).getOperand(0);
547      else {
548        ShAmt = 0;
549        ShOpcVal = ARM_AM::no_shift;
550      }
551    } else {
552      ShOpcVal = ARM_AM::no_shift;
553    }
554  }
555
556  // Try matching (R shl C) + (R).
557  if (N.getOpcode() != ISD::SUB && ShOpcVal == ARM_AM::no_shift &&
558      !(Subtarget->isCortexA9() || N.getOperand(0).hasOneUse())) {
559    ShOpcVal = ARM_AM::getShiftOpcForNode(N.getOperand(0).getOpcode());
560    if (ShOpcVal != ARM_AM::no_shift) {
561      // Check to see if the RHS of the shift is a constant, if not, we can't
562      // fold it.
563      if (ConstantSDNode *Sh =
564          dyn_cast<ConstantSDNode>(N.getOperand(0).getOperand(1))) {
565        ShAmt = Sh->getZExtValue();
566        if (isShifterOpProfitable(N.getOperand(0), ShOpcVal, ShAmt)) {
567          Offset = N.getOperand(0).getOperand(0);
568          Base = N.getOperand(1);
569        } else {
570          ShAmt = 0;
571          ShOpcVal = ARM_AM::no_shift;
572        }
573      } else {
574        ShOpcVal = ARM_AM::no_shift;
575      }
576    }
577  }
578
579  Opc = CurDAG->getTargetConstant(ARM_AM::getAM2Opc(AddSub, ShAmt, ShOpcVal),
580                                  MVT::i32);
581  return true;
582}
583
584
585
586
587//-----
588
589AddrMode2Type ARMDAGToDAGISel::SelectAddrMode2Worker(SDValue N,
590                                                     SDValue &Base,
591                                                     SDValue &Offset,
592                                                     SDValue &Opc) {
593  if (N.getOpcode() == ISD::MUL &&
594      (!Subtarget->isCortexA9() || N.hasOneUse())) {
595    if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N.getOperand(1))) {
596      // X * [3,5,9] -> X + X * [2,4,8] etc.
597      int RHSC = (int)RHS->getZExtValue();
598      if (RHSC & 1) {
599        RHSC = RHSC & ~1;
600        ARM_AM::AddrOpc AddSub = ARM_AM::add;
601        if (RHSC < 0) {
602          AddSub = ARM_AM::sub;
603          RHSC = - RHSC;
604        }
605        if (isPowerOf2_32(RHSC)) {
606          unsigned ShAmt = Log2_32(RHSC);
607          Base = Offset = N.getOperand(0);
608          Opc = CurDAG->getTargetConstant(ARM_AM::getAM2Opc(AddSub, ShAmt,
609                                                            ARM_AM::lsl),
610                                          MVT::i32);
611          return AM2_SHOP;
612        }
613      }
614    }
615  }
616
617  if (N.getOpcode() != ISD::ADD && N.getOpcode() != ISD::SUB &&
618      // ISD::OR that is equivalent to an ADD.
619      !CurDAG->isBaseWithConstantOffset(N)) {
620    Base = N;
621    if (N.getOpcode() == ISD::FrameIndex) {
622      int FI = cast<FrameIndexSDNode>(N)->getIndex();
623      Base = CurDAG->getTargetFrameIndex(FI, TLI.getPointerTy());
624    } else if (N.getOpcode() == ARMISD::Wrapper &&
625               !(Subtarget->useMovt() &&
626                 N.getOperand(0).getOpcode() == ISD::TargetGlobalAddress)) {
627      Base = N.getOperand(0);
628    }
629    Offset = CurDAG->getRegister(0, MVT::i32);
630    Opc = CurDAG->getTargetConstant(ARM_AM::getAM2Opc(ARM_AM::add, 0,
631                                                      ARM_AM::no_shift),
632                                    MVT::i32);
633    return AM2_BASE;
634  }
635
636  // Match simple R +/- imm12 operands.
637  if (N.getOpcode() != ISD::SUB) {
638    int RHSC;
639    if (isScaledConstantInRange(N.getOperand(1), /*Scale=*/1,
640                                -0x1000+1, 0x1000, RHSC)) { // 12 bits.
641      Base = N.getOperand(0);
642      if (Base.getOpcode() == ISD::FrameIndex) {
643        int FI = cast<FrameIndexSDNode>(Base)->getIndex();
644        Base = CurDAG->getTargetFrameIndex(FI, TLI.getPointerTy());
645      }
646      Offset = CurDAG->getRegister(0, MVT::i32);
647
648      ARM_AM::AddrOpc AddSub = ARM_AM::add;
649      if (RHSC < 0) {
650        AddSub = ARM_AM::sub;
651        RHSC = - RHSC;
652      }
653      Opc = CurDAG->getTargetConstant(ARM_AM::getAM2Opc(AddSub, RHSC,
654                                                        ARM_AM::no_shift),
655                                      MVT::i32);
656      return AM2_BASE;
657    }
658  }
659
660  if (Subtarget->isCortexA9() && !N.hasOneUse()) {
661    // Compute R +/- (R << N) and reuse it.
662    Base = N;
663    Offset = CurDAG->getRegister(0, MVT::i32);
664    Opc = CurDAG->getTargetConstant(ARM_AM::getAM2Opc(ARM_AM::add, 0,
665                                                      ARM_AM::no_shift),
666                                    MVT::i32);
667    return AM2_BASE;
668  }
669
670  // Otherwise this is R +/- [possibly shifted] R.
671  ARM_AM::AddrOpc AddSub = N.getOpcode() != ISD::SUB ? ARM_AM::add:ARM_AM::sub;
672  ARM_AM::ShiftOpc ShOpcVal =
673    ARM_AM::getShiftOpcForNode(N.getOperand(1).getOpcode());
674  unsigned ShAmt = 0;
675
676  Base   = N.getOperand(0);
677  Offset = N.getOperand(1);
678
679  if (ShOpcVal != ARM_AM::no_shift) {
680    // Check to see if the RHS of the shift is a constant, if not, we can't fold
681    // it.
682    if (ConstantSDNode *Sh =
683           dyn_cast<ConstantSDNode>(N.getOperand(1).getOperand(1))) {
684      ShAmt = Sh->getZExtValue();
685      if (isShifterOpProfitable(Offset, ShOpcVal, ShAmt))
686        Offset = N.getOperand(1).getOperand(0);
687      else {
688        ShAmt = 0;
689        ShOpcVal = ARM_AM::no_shift;
690      }
691    } else {
692      ShOpcVal = ARM_AM::no_shift;
693    }
694  }
695
696  // Try matching (R shl C) + (R).
697  if (N.getOpcode() != ISD::SUB && ShOpcVal == ARM_AM::no_shift &&
698      !(Subtarget->isCortexA9() || N.getOperand(0).hasOneUse())) {
699    ShOpcVal = ARM_AM::getShiftOpcForNode(N.getOperand(0).getOpcode());
700    if (ShOpcVal != ARM_AM::no_shift) {
701      // Check to see if the RHS of the shift is a constant, if not, we can't
702      // fold it.
703      if (ConstantSDNode *Sh =
704          dyn_cast<ConstantSDNode>(N.getOperand(0).getOperand(1))) {
705        ShAmt = Sh->getZExtValue();
706        if (isShifterOpProfitable(N.getOperand(0), ShOpcVal, ShAmt)) {
707          Offset = N.getOperand(0).getOperand(0);
708          Base = N.getOperand(1);
709        } else {
710          ShAmt = 0;
711          ShOpcVal = ARM_AM::no_shift;
712        }
713      } else {
714        ShOpcVal = ARM_AM::no_shift;
715      }
716    }
717  }
718
719  Opc = CurDAG->getTargetConstant(ARM_AM::getAM2Opc(AddSub, ShAmt, ShOpcVal),
720                                  MVT::i32);
721  return AM2_SHOP;
722}
723
724bool ARMDAGToDAGISel::SelectAddrMode2OffsetReg(SDNode *Op, SDValue N,
725                                            SDValue &Offset, SDValue &Opc) {
726  unsigned Opcode = Op->getOpcode();
727  ISD::MemIndexedMode AM = (Opcode == ISD::LOAD)
728    ? cast<LoadSDNode>(Op)->getAddressingMode()
729    : cast<StoreSDNode>(Op)->getAddressingMode();
730  ARM_AM::AddrOpc AddSub = (AM == ISD::PRE_INC || AM == ISD::POST_INC)
731    ? ARM_AM::add : ARM_AM::sub;
732  int Val;
733  if (isScaledConstantInRange(N, /*Scale=*/1, 0, 0x1000, Val))
734    return false;
735
736  Offset = N;
737  ARM_AM::ShiftOpc ShOpcVal = ARM_AM::getShiftOpcForNode(N.getOpcode());
738  unsigned ShAmt = 0;
739  if (ShOpcVal != ARM_AM::no_shift) {
740    // Check to see if the RHS of the shift is a constant, if not, we can't fold
741    // it.
742    if (ConstantSDNode *Sh = dyn_cast<ConstantSDNode>(N.getOperand(1))) {
743      ShAmt = Sh->getZExtValue();
744      if (isShifterOpProfitable(N, ShOpcVal, ShAmt))
745        Offset = N.getOperand(0);
746      else {
747        ShAmt = 0;
748        ShOpcVal = ARM_AM::no_shift;
749      }
750    } else {
751      ShOpcVal = ARM_AM::no_shift;
752    }
753  }
754
755  Opc = CurDAG->getTargetConstant(ARM_AM::getAM2Opc(AddSub, ShAmt, ShOpcVal),
756                                  MVT::i32);
757  return true;
758}
759
760bool ARMDAGToDAGISel::SelectAddrMode2OffsetImmPre(SDNode *Op, SDValue N,
761                                            SDValue &Offset, SDValue &Opc) {
762  unsigned Opcode = Op->getOpcode();
763  ISD::MemIndexedMode AM = (Opcode == ISD::LOAD)
764    ? cast<LoadSDNode>(Op)->getAddressingMode()
765    : cast<StoreSDNode>(Op)->getAddressingMode();
766  ARM_AM::AddrOpc AddSub = (AM == ISD::PRE_INC || AM == ISD::POST_INC)
767    ? ARM_AM::add : ARM_AM::sub;
768  int Val;
769  if (isScaledConstantInRange(N, /*Scale=*/1, 0, 0x1000, Val)) { // 12 bits.
770    if (AddSub == ARM_AM::sub) Val *= -1;
771    Offset = CurDAG->getRegister(0, MVT::i32);
772    Opc = CurDAG->getTargetConstant(Val, MVT::i32);
773    return true;
774  }
775
776  return false;
777}
778
779
780bool ARMDAGToDAGISel::SelectAddrMode2OffsetImm(SDNode *Op, SDValue N,
781                                            SDValue &Offset, SDValue &Opc) {
782  unsigned Opcode = Op->getOpcode();
783  ISD::MemIndexedMode AM = (Opcode == ISD::LOAD)
784    ? cast<LoadSDNode>(Op)->getAddressingMode()
785    : cast<StoreSDNode>(Op)->getAddressingMode();
786  ARM_AM::AddrOpc AddSub = (AM == ISD::PRE_INC || AM == ISD::POST_INC)
787    ? ARM_AM::add : ARM_AM::sub;
788  int Val;
789  if (isScaledConstantInRange(N, /*Scale=*/1, 0, 0x1000, Val)) { // 12 bits.
790    Offset = CurDAG->getRegister(0, MVT::i32);
791    Opc = CurDAG->getTargetConstant(ARM_AM::getAM2Opc(AddSub, Val,
792                                                      ARM_AM::no_shift),
793                                    MVT::i32);
794    return true;
795  }
796
797  return false;
798}
799
800bool ARMDAGToDAGISel::SelectAddrOffsetNone(SDValue N, SDValue &Base) {
801  Base = N;
802  return true;
803}
804
805bool ARMDAGToDAGISel::SelectAddrMode3(SDValue N,
806                                      SDValue &Base, SDValue &Offset,
807                                      SDValue &Opc) {
808  if (N.getOpcode() == ISD::SUB) {
809    // X - C  is canonicalize to X + -C, no need to handle it here.
810    Base = N.getOperand(0);
811    Offset = N.getOperand(1);
812    Opc = CurDAG->getTargetConstant(ARM_AM::getAM3Opc(ARM_AM::sub, 0),MVT::i32);
813    return true;
814  }
815
816  if (!CurDAG->isBaseWithConstantOffset(N)) {
817    Base = N;
818    if (N.getOpcode() == ISD::FrameIndex) {
819      int FI = cast<FrameIndexSDNode>(N)->getIndex();
820      Base = CurDAG->getTargetFrameIndex(FI, TLI.getPointerTy());
821    }
822    Offset = CurDAG->getRegister(0, MVT::i32);
823    Opc = CurDAG->getTargetConstant(ARM_AM::getAM3Opc(ARM_AM::add, 0),MVT::i32);
824    return true;
825  }
826
827  // If the RHS is +/- imm8, fold into addr mode.
828  int RHSC;
829  if (isScaledConstantInRange(N.getOperand(1), /*Scale=*/1,
830                              -256 + 1, 256, RHSC)) { // 8 bits.
831    Base = N.getOperand(0);
832    if (Base.getOpcode() == ISD::FrameIndex) {
833      int FI = cast<FrameIndexSDNode>(Base)->getIndex();
834      Base = CurDAG->getTargetFrameIndex(FI, TLI.getPointerTy());
835    }
836    Offset = CurDAG->getRegister(0, MVT::i32);
837
838    ARM_AM::AddrOpc AddSub = ARM_AM::add;
839    if (RHSC < 0) {
840      AddSub = ARM_AM::sub;
841      RHSC = -RHSC;
842    }
843    Opc = CurDAG->getTargetConstant(ARM_AM::getAM3Opc(AddSub, RHSC),MVT::i32);
844    return true;
845  }
846
847  Base = N.getOperand(0);
848  Offset = N.getOperand(1);
849  Opc = CurDAG->getTargetConstant(ARM_AM::getAM3Opc(ARM_AM::add, 0), MVT::i32);
850  return true;
851}
852
853bool ARMDAGToDAGISel::SelectAddrMode3Offset(SDNode *Op, SDValue N,
854                                            SDValue &Offset, SDValue &Opc) {
855  unsigned Opcode = Op->getOpcode();
856  ISD::MemIndexedMode AM = (Opcode == ISD::LOAD)
857    ? cast<LoadSDNode>(Op)->getAddressingMode()
858    : cast<StoreSDNode>(Op)->getAddressingMode();
859  ARM_AM::AddrOpc AddSub = (AM == ISD::PRE_INC || AM == ISD::POST_INC)
860    ? ARM_AM::add : ARM_AM::sub;
861  int Val;
862  if (isScaledConstantInRange(N, /*Scale=*/1, 0, 256, Val)) { // 12 bits.
863    Offset = CurDAG->getRegister(0, MVT::i32);
864    Opc = CurDAG->getTargetConstant(ARM_AM::getAM3Opc(AddSub, Val), MVT::i32);
865    return true;
866  }
867
868  Offset = N;
869  Opc = CurDAG->getTargetConstant(ARM_AM::getAM3Opc(AddSub, 0), MVT::i32);
870  return true;
871}
872
873bool ARMDAGToDAGISel::SelectAddrMode5(SDValue N,
874                                      SDValue &Base, SDValue &Offset) {
875  if (!CurDAG->isBaseWithConstantOffset(N)) {
876    Base = N;
877    if (N.getOpcode() == ISD::FrameIndex) {
878      int FI = cast<FrameIndexSDNode>(N)->getIndex();
879      Base = CurDAG->getTargetFrameIndex(FI, TLI.getPointerTy());
880    } else if (N.getOpcode() == ARMISD::Wrapper &&
881               !(Subtarget->useMovt() &&
882                 N.getOperand(0).getOpcode() == ISD::TargetGlobalAddress)) {
883      Base = N.getOperand(0);
884    }
885    Offset = CurDAG->getTargetConstant(ARM_AM::getAM5Opc(ARM_AM::add, 0),
886                                       MVT::i32);
887    return true;
888  }
889
890  // If the RHS is +/- imm8, fold into addr mode.
891  int RHSC;
892  if (isScaledConstantInRange(N.getOperand(1), /*Scale=*/4,
893                              -256 + 1, 256, RHSC)) {
894    Base = N.getOperand(0);
895    if (Base.getOpcode() == ISD::FrameIndex) {
896      int FI = cast<FrameIndexSDNode>(Base)->getIndex();
897      Base = CurDAG->getTargetFrameIndex(FI, TLI.getPointerTy());
898    }
899
900    ARM_AM::AddrOpc AddSub = ARM_AM::add;
901    if (RHSC < 0) {
902      AddSub = ARM_AM::sub;
903      RHSC = -RHSC;
904    }
905    Offset = CurDAG->getTargetConstant(ARM_AM::getAM5Opc(AddSub, RHSC),
906                                       MVT::i32);
907    return true;
908  }
909
910  Base = N;
911  Offset = CurDAG->getTargetConstant(ARM_AM::getAM5Opc(ARM_AM::add, 0),
912                                     MVT::i32);
913  return true;
914}
915
916bool ARMDAGToDAGISel::SelectAddrMode6(SDNode *Parent, SDValue N, SDValue &Addr,
917                                      SDValue &Align) {
918  Addr = N;
919
920  unsigned Alignment = 0;
921  if (LSBaseSDNode *LSN = dyn_cast<LSBaseSDNode>(Parent)) {
922    // This case occurs only for VLD1-lane/dup and VST1-lane instructions.
923    // The maximum alignment is equal to the memory size being referenced.
924    unsigned LSNAlign = LSN->getAlignment();
925    unsigned MemSize = LSN->getMemoryVT().getSizeInBits() / 8;
926    if (LSNAlign > MemSize && MemSize > 1)
927      Alignment = MemSize;
928  } else {
929    // All other uses of addrmode6 are for intrinsics.  For now just record
930    // the raw alignment value; it will be refined later based on the legal
931    // alignment operands for the intrinsic.
932    Alignment = cast<MemIntrinsicSDNode>(Parent)->getAlignment();
933  }
934
935  Align = CurDAG->getTargetConstant(Alignment, MVT::i32);
936  return true;
937}
938
939bool ARMDAGToDAGISel::SelectAddrMode6Offset(SDNode *Op, SDValue N,
940                                            SDValue &Offset) {
941  LSBaseSDNode *LdSt = cast<LSBaseSDNode>(Op);
942  ISD::MemIndexedMode AM = LdSt->getAddressingMode();
943  if (AM != ISD::POST_INC)
944    return false;
945  Offset = N;
946  if (ConstantSDNode *NC = dyn_cast<ConstantSDNode>(N)) {
947    if (NC->getZExtValue() * 8 == LdSt->getMemoryVT().getSizeInBits())
948      Offset = CurDAG->getRegister(0, MVT::i32);
949  }
950  return true;
951}
952
953bool ARMDAGToDAGISel::SelectAddrModePC(SDValue N,
954                                       SDValue &Offset, SDValue &Label) {
955  if (N.getOpcode() == ARMISD::PIC_ADD && N.hasOneUse()) {
956    Offset = N.getOperand(0);
957    SDValue N1 = N.getOperand(1);
958    Label = CurDAG->getTargetConstant(cast<ConstantSDNode>(N1)->getZExtValue(),
959                                      MVT::i32);
960    return true;
961  }
962
963  return false;
964}
965
966
967//===----------------------------------------------------------------------===//
968//                         Thumb Addressing Modes
969//===----------------------------------------------------------------------===//
970
971bool ARMDAGToDAGISel::SelectThumbAddrModeRR(SDValue N,
972                                            SDValue &Base, SDValue &Offset){
973  if (N.getOpcode() != ISD::ADD && !CurDAG->isBaseWithConstantOffset(N)) {
974    ConstantSDNode *NC = dyn_cast<ConstantSDNode>(N);
975    if (!NC || !NC->isNullValue())
976      return false;
977
978    Base = Offset = N;
979    return true;
980  }
981
982  Base = N.getOperand(0);
983  Offset = N.getOperand(1);
984  return true;
985}
986
987bool
988ARMDAGToDAGISel::SelectThumbAddrModeRI(SDValue N, SDValue &Base,
989                                       SDValue &Offset, unsigned Scale) {
990  if (Scale == 4) {
991    SDValue TmpBase, TmpOffImm;
992    if (SelectThumbAddrModeSP(N, TmpBase, TmpOffImm))
993      return false;  // We want to select tLDRspi / tSTRspi instead.
994
995    if (N.getOpcode() == ARMISD::Wrapper &&
996        N.getOperand(0).getOpcode() == ISD::TargetConstantPool)
997      return false;  // We want to select tLDRpci instead.
998  }
999
1000  if (!CurDAG->isBaseWithConstantOffset(N))
1001    return false;
1002
1003  // Thumb does not have [sp, r] address mode.
1004  RegisterSDNode *LHSR = dyn_cast<RegisterSDNode>(N.getOperand(0));
1005  RegisterSDNode *RHSR = dyn_cast<RegisterSDNode>(N.getOperand(1));
1006  if ((LHSR && LHSR->getReg() == ARM::SP) ||
1007      (RHSR && RHSR->getReg() == ARM::SP))
1008    return false;
1009
1010  // FIXME: Why do we explicitly check for a match here and then return false?
1011  // Presumably to allow something else to match, but shouldn't this be
1012  // documented?
1013  int RHSC;
1014  if (isScaledConstantInRange(N.getOperand(1), Scale, 0, 32, RHSC))
1015    return false;
1016
1017  Base = N.getOperand(0);
1018  Offset = N.getOperand(1);
1019  return true;
1020}
1021
1022bool
1023ARMDAGToDAGISel::SelectThumbAddrModeRI5S1(SDValue N,
1024                                          SDValue &Base,
1025                                          SDValue &Offset) {
1026  return SelectThumbAddrModeRI(N, Base, Offset, 1);
1027}
1028
1029bool
1030ARMDAGToDAGISel::SelectThumbAddrModeRI5S2(SDValue N,
1031                                          SDValue &Base,
1032                                          SDValue &Offset) {
1033  return SelectThumbAddrModeRI(N, Base, Offset, 2);
1034}
1035
1036bool
1037ARMDAGToDAGISel::SelectThumbAddrModeRI5S4(SDValue N,
1038                                          SDValue &Base,
1039                                          SDValue &Offset) {
1040  return SelectThumbAddrModeRI(N, Base, Offset, 4);
1041}
1042
1043bool
1044ARMDAGToDAGISel::SelectThumbAddrModeImm5S(SDValue N, unsigned Scale,
1045                                          SDValue &Base, SDValue &OffImm) {
1046  if (Scale == 4) {
1047    SDValue TmpBase, TmpOffImm;
1048    if (SelectThumbAddrModeSP(N, TmpBase, TmpOffImm))
1049      return false;  // We want to select tLDRspi / tSTRspi instead.
1050
1051    if (N.getOpcode() == ARMISD::Wrapper &&
1052        N.getOperand(0).getOpcode() == ISD::TargetConstantPool)
1053      return false;  // We want to select tLDRpci instead.
1054  }
1055
1056  if (!CurDAG->isBaseWithConstantOffset(N)) {
1057    if (N.getOpcode() == ARMISD::Wrapper &&
1058        !(Subtarget->useMovt() &&
1059          N.getOperand(0).getOpcode() == ISD::TargetGlobalAddress)) {
1060      Base = N.getOperand(0);
1061    } else {
1062      Base = N;
1063    }
1064
1065    OffImm = CurDAG->getTargetConstant(0, MVT::i32);
1066    return true;
1067  }
1068
1069  RegisterSDNode *LHSR = dyn_cast<RegisterSDNode>(N.getOperand(0));
1070  RegisterSDNode *RHSR = dyn_cast<RegisterSDNode>(N.getOperand(1));
1071  if ((LHSR && LHSR->getReg() == ARM::SP) ||
1072      (RHSR && RHSR->getReg() == ARM::SP)) {
1073    ConstantSDNode *LHS = dyn_cast<ConstantSDNode>(N.getOperand(0));
1074    ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N.getOperand(1));
1075    unsigned LHSC = LHS ? LHS->getZExtValue() : 0;
1076    unsigned RHSC = RHS ? RHS->getZExtValue() : 0;
1077
1078    // Thumb does not have [sp, #imm5] address mode for non-zero imm5.
1079    if (LHSC != 0 || RHSC != 0) return false;
1080
1081    Base = N;
1082    OffImm = CurDAG->getTargetConstant(0, MVT::i32);
1083    return true;
1084  }
1085
1086  // If the RHS is + imm5 * scale, fold into addr mode.
1087  int RHSC;
1088  if (isScaledConstantInRange(N.getOperand(1), Scale, 0, 32, RHSC)) {
1089    Base = N.getOperand(0);
1090    OffImm = CurDAG->getTargetConstant(RHSC, MVT::i32);
1091    return true;
1092  }
1093
1094  Base = N.getOperand(0);
1095  OffImm = CurDAG->getTargetConstant(0, MVT::i32);
1096  return true;
1097}
1098
1099bool
1100ARMDAGToDAGISel::SelectThumbAddrModeImm5S4(SDValue N, SDValue &Base,
1101                                           SDValue &OffImm) {
1102  return SelectThumbAddrModeImm5S(N, 4, Base, OffImm);
1103}
1104
1105bool
1106ARMDAGToDAGISel::SelectThumbAddrModeImm5S2(SDValue N, SDValue &Base,
1107                                           SDValue &OffImm) {
1108  return SelectThumbAddrModeImm5S(N, 2, Base, OffImm);
1109}
1110
1111bool
1112ARMDAGToDAGISel::SelectThumbAddrModeImm5S1(SDValue N, SDValue &Base,
1113                                           SDValue &OffImm) {
1114  return SelectThumbAddrModeImm5S(N, 1, Base, OffImm);
1115}
1116
1117bool ARMDAGToDAGISel::SelectThumbAddrModeSP(SDValue N,
1118                                            SDValue &Base, SDValue &OffImm) {
1119  if (N.getOpcode() == ISD::FrameIndex) {
1120    int FI = cast<FrameIndexSDNode>(N)->getIndex();
1121    Base = CurDAG->getTargetFrameIndex(FI, TLI.getPointerTy());
1122    OffImm = CurDAG->getTargetConstant(0, MVT::i32);
1123    return true;
1124  }
1125
1126  if (!CurDAG->isBaseWithConstantOffset(N))
1127    return false;
1128
1129  RegisterSDNode *LHSR = dyn_cast<RegisterSDNode>(N.getOperand(0));
1130  if (N.getOperand(0).getOpcode() == ISD::FrameIndex ||
1131      (LHSR && LHSR->getReg() == ARM::SP)) {
1132    // If the RHS is + imm8 * scale, fold into addr mode.
1133    int RHSC;
1134    if (isScaledConstantInRange(N.getOperand(1), /*Scale=*/4, 0, 256, RHSC)) {
1135      Base = N.getOperand(0);
1136      if (Base.getOpcode() == ISD::FrameIndex) {
1137        int FI = cast<FrameIndexSDNode>(Base)->getIndex();
1138        Base = CurDAG->getTargetFrameIndex(FI, TLI.getPointerTy());
1139      }
1140      OffImm = CurDAG->getTargetConstant(RHSC, MVT::i32);
1141      return true;
1142    }
1143  }
1144
1145  return false;
1146}
1147
1148
1149//===----------------------------------------------------------------------===//
1150//                        Thumb 2 Addressing Modes
1151//===----------------------------------------------------------------------===//
1152
1153
1154bool ARMDAGToDAGISel::SelectT2ShifterOperandReg(SDValue N, SDValue &BaseReg,
1155                                                SDValue &Opc) {
1156  if (DisableShifterOp)
1157    return false;
1158
1159  ARM_AM::ShiftOpc ShOpcVal = ARM_AM::getShiftOpcForNode(N.getOpcode());
1160
1161  // Don't match base register only case. That is matched to a separate
1162  // lower complexity pattern with explicit register operand.
1163  if (ShOpcVal == ARM_AM::no_shift) return false;
1164
1165  BaseReg = N.getOperand(0);
1166  unsigned ShImmVal = 0;
1167  if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N.getOperand(1))) {
1168    ShImmVal = RHS->getZExtValue() & 31;
1169    Opc = getI32Imm(ARM_AM::getSORegOpc(ShOpcVal, ShImmVal));
1170    return true;
1171  }
1172
1173  return false;
1174}
1175
1176bool ARMDAGToDAGISel::SelectT2AddrModeImm12(SDValue N,
1177                                            SDValue &Base, SDValue &OffImm) {
1178  // Match simple R + imm12 operands.
1179
1180  // Base only.
1181  if (N.getOpcode() != ISD::ADD && N.getOpcode() != ISD::SUB &&
1182      !CurDAG->isBaseWithConstantOffset(N)) {
1183    if (N.getOpcode() == ISD::FrameIndex) {
1184      // Match frame index.
1185      int FI = cast<FrameIndexSDNode>(N)->getIndex();
1186      Base = CurDAG->getTargetFrameIndex(FI, TLI.getPointerTy());
1187      OffImm  = CurDAG->getTargetConstant(0, MVT::i32);
1188      return true;
1189    }
1190
1191    if (N.getOpcode() == ARMISD::Wrapper &&
1192               !(Subtarget->useMovt() &&
1193                 N.getOperand(0).getOpcode() == ISD::TargetGlobalAddress)) {
1194      Base = N.getOperand(0);
1195      if (Base.getOpcode() == ISD::TargetConstantPool)
1196        return false;  // We want to select t2LDRpci instead.
1197    } else
1198      Base = N;
1199    OffImm  = CurDAG->getTargetConstant(0, MVT::i32);
1200    return true;
1201  }
1202
1203  if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N.getOperand(1))) {
1204    if (SelectT2AddrModeImm8(N, Base, OffImm))
1205      // Let t2LDRi8 handle (R - imm8).
1206      return false;
1207
1208    int RHSC = (int)RHS->getZExtValue();
1209    if (N.getOpcode() == ISD::SUB)
1210      RHSC = -RHSC;
1211
1212    if (RHSC >= 0 && RHSC < 0x1000) { // 12 bits (unsigned)
1213      Base   = N.getOperand(0);
1214      if (Base.getOpcode() == ISD::FrameIndex) {
1215        int FI = cast<FrameIndexSDNode>(Base)->getIndex();
1216        Base = CurDAG->getTargetFrameIndex(FI, TLI.getPointerTy());
1217      }
1218      OffImm = CurDAG->getTargetConstant(RHSC, MVT::i32);
1219      return true;
1220    }
1221  }
1222
1223  // Base only.
1224  Base = N;
1225  OffImm  = CurDAG->getTargetConstant(0, MVT::i32);
1226  return true;
1227}
1228
1229bool ARMDAGToDAGISel::SelectT2AddrModeImm8(SDValue N,
1230                                           SDValue &Base, SDValue &OffImm) {
1231  // Match simple R - imm8 operands.
1232  if (N.getOpcode() != ISD::ADD && N.getOpcode() != ISD::SUB &&
1233      !CurDAG->isBaseWithConstantOffset(N))
1234    return false;
1235
1236  if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N.getOperand(1))) {
1237    int RHSC = (int)RHS->getSExtValue();
1238    if (N.getOpcode() == ISD::SUB)
1239      RHSC = -RHSC;
1240
1241    if ((RHSC >= -255) && (RHSC < 0)) { // 8 bits (always negative)
1242      Base = N.getOperand(0);
1243      if (Base.getOpcode() == ISD::FrameIndex) {
1244        int FI = cast<FrameIndexSDNode>(Base)->getIndex();
1245        Base = CurDAG->getTargetFrameIndex(FI, TLI.getPointerTy());
1246      }
1247      OffImm = CurDAG->getTargetConstant(RHSC, MVT::i32);
1248      return true;
1249    }
1250  }
1251
1252  return false;
1253}
1254
1255bool ARMDAGToDAGISel::SelectT2AddrModeImm8Offset(SDNode *Op, SDValue N,
1256                                                 SDValue &OffImm){
1257  unsigned Opcode = Op->getOpcode();
1258  ISD::MemIndexedMode AM = (Opcode == ISD::LOAD)
1259    ? cast<LoadSDNode>(Op)->getAddressingMode()
1260    : cast<StoreSDNode>(Op)->getAddressingMode();
1261  int RHSC;
1262  if (isScaledConstantInRange(N, /*Scale=*/1, 0, 0x100, RHSC)) { // 8 bits.
1263    OffImm = ((AM == ISD::PRE_INC) || (AM == ISD::POST_INC))
1264      ? CurDAG->getTargetConstant(RHSC, MVT::i32)
1265      : CurDAG->getTargetConstant(-RHSC, MVT::i32);
1266    return true;
1267  }
1268
1269  return false;
1270}
1271
1272bool ARMDAGToDAGISel::SelectT2AddrModeSoReg(SDValue N,
1273                                            SDValue &Base,
1274                                            SDValue &OffReg, SDValue &ShImm) {
1275  // (R - imm8) should be handled by t2LDRi8. The rest are handled by t2LDRi12.
1276  if (N.getOpcode() != ISD::ADD && !CurDAG->isBaseWithConstantOffset(N))
1277    return false;
1278
1279  // Leave (R + imm12) for t2LDRi12, (R - imm8) for t2LDRi8.
1280  if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N.getOperand(1))) {
1281    int RHSC = (int)RHS->getZExtValue();
1282    if (RHSC >= 0 && RHSC < 0x1000) // 12 bits (unsigned)
1283      return false;
1284    else if (RHSC < 0 && RHSC >= -255) // 8 bits
1285      return false;
1286  }
1287
1288  // Look for (R + R) or (R + (R << [1,2,3])).
1289  unsigned ShAmt = 0;
1290  Base   = N.getOperand(0);
1291  OffReg = N.getOperand(1);
1292
1293  // Swap if it is ((R << c) + R).
1294  ARM_AM::ShiftOpc ShOpcVal = ARM_AM::getShiftOpcForNode(OffReg.getOpcode());
1295  if (ShOpcVal != ARM_AM::lsl) {
1296    ShOpcVal = ARM_AM::getShiftOpcForNode(Base.getOpcode());
1297    if (ShOpcVal == ARM_AM::lsl)
1298      std::swap(Base, OffReg);
1299  }
1300
1301  if (ShOpcVal == ARM_AM::lsl) {
1302    // Check to see if the RHS of the shift is a constant, if not, we can't fold
1303    // it.
1304    if (ConstantSDNode *Sh = dyn_cast<ConstantSDNode>(OffReg.getOperand(1))) {
1305      ShAmt = Sh->getZExtValue();
1306      if (ShAmt < 4 && isShifterOpProfitable(OffReg, ShOpcVal, ShAmt))
1307        OffReg = OffReg.getOperand(0);
1308      else {
1309        ShAmt = 0;
1310        ShOpcVal = ARM_AM::no_shift;
1311      }
1312    } else {
1313      ShOpcVal = ARM_AM::no_shift;
1314    }
1315  }
1316
1317  ShImm = CurDAG->getTargetConstant(ShAmt, MVT::i32);
1318
1319  return true;
1320}
1321
1322//===--------------------------------------------------------------------===//
1323
1324/// getAL - Returns a ARMCC::AL immediate node.
1325static inline SDValue getAL(SelectionDAG *CurDAG) {
1326  return CurDAG->getTargetConstant((uint64_t)ARMCC::AL, MVT::i32);
1327}
1328
1329SDNode *ARMDAGToDAGISel::SelectARMIndexedLoad(SDNode *N) {
1330  LoadSDNode *LD = cast<LoadSDNode>(N);
1331  ISD::MemIndexedMode AM = LD->getAddressingMode();
1332  if (AM == ISD::UNINDEXED)
1333    return NULL;
1334
1335  EVT LoadedVT = LD->getMemoryVT();
1336  SDValue Offset, AMOpc;
1337  bool isPre = (AM == ISD::PRE_INC) || (AM == ISD::PRE_DEC);
1338  unsigned Opcode = 0;
1339  bool Match = false;
1340  if (LoadedVT == MVT::i32 && isPre &&
1341      SelectAddrMode2OffsetImmPre(N, LD->getOffset(), Offset, AMOpc)) {
1342    Opcode = ARM::LDR_PRE_IMM;
1343    Match = true;
1344  } else if (LoadedVT == MVT::i32 && !isPre &&
1345      SelectAddrMode2OffsetImm(N, LD->getOffset(), Offset, AMOpc)) {
1346    Opcode = ARM::LDR_POST_IMM;
1347    Match = true;
1348  } else if (LoadedVT == MVT::i32 &&
1349      SelectAddrMode2OffsetReg(N, LD->getOffset(), Offset, AMOpc)) {
1350    Opcode = isPre ? ARM::LDR_PRE_REG : ARM::LDR_POST_REG;
1351    Match = true;
1352
1353  } else if (LoadedVT == MVT::i16 &&
1354             SelectAddrMode3Offset(N, LD->getOffset(), Offset, AMOpc)) {
1355    Match = true;
1356    Opcode = (LD->getExtensionType() == ISD::SEXTLOAD)
1357      ? (isPre ? ARM::LDRSH_PRE : ARM::LDRSH_POST)
1358      : (isPre ? ARM::LDRH_PRE : ARM::LDRH_POST);
1359  } else if (LoadedVT == MVT::i8 || LoadedVT == MVT::i1) {
1360    if (LD->getExtensionType() == ISD::SEXTLOAD) {
1361      if (SelectAddrMode3Offset(N, LD->getOffset(), Offset, AMOpc)) {
1362        Match = true;
1363        Opcode = isPre ? ARM::LDRSB_PRE : ARM::LDRSB_POST;
1364      }
1365    } else {
1366      if (isPre &&
1367          SelectAddrMode2OffsetImmPre(N, LD->getOffset(), Offset, AMOpc)) {
1368        Match = true;
1369        Opcode = ARM::LDRB_PRE_IMM;
1370      } else if (!isPre &&
1371                  SelectAddrMode2OffsetImm(N, LD->getOffset(), Offset, AMOpc)) {
1372        Match = true;
1373        Opcode = ARM::LDRB_POST_IMM;
1374      } else if (SelectAddrMode2OffsetReg(N, LD->getOffset(), Offset, AMOpc)) {
1375        Match = true;
1376        Opcode = isPre ? ARM::LDRB_PRE_REG : ARM::LDRB_POST_REG;
1377      }
1378    }
1379  }
1380
1381  if (Match) {
1382    if (Opcode == ARM::LDR_PRE_IMM || Opcode == ARM::LDRB_PRE_IMM) {
1383      SDValue Chain = LD->getChain();
1384      SDValue Base = LD->getBasePtr();
1385      SDValue Ops[]= { Base, AMOpc, getAL(CurDAG),
1386                       CurDAG->getRegister(0, MVT::i32), Chain };
1387      return CurDAG->getMachineNode(Opcode, N->getDebugLoc(), MVT::i32,
1388                                    MVT::i32, MVT::Other, Ops, 5);
1389    } else {
1390      SDValue Chain = LD->getChain();
1391      SDValue Base = LD->getBasePtr();
1392      SDValue Ops[]= { Base, Offset, AMOpc, getAL(CurDAG),
1393                       CurDAG->getRegister(0, MVT::i32), Chain };
1394      return CurDAG->getMachineNode(Opcode, N->getDebugLoc(), MVT::i32,
1395                                    MVT::i32, MVT::Other, Ops, 6);
1396    }
1397  }
1398
1399  return NULL;
1400}
1401
1402SDNode *ARMDAGToDAGISel::SelectT2IndexedLoad(SDNode *N) {
1403  LoadSDNode *LD = cast<LoadSDNode>(N);
1404  ISD::MemIndexedMode AM = LD->getAddressingMode();
1405  if (AM == ISD::UNINDEXED)
1406    return NULL;
1407
1408  EVT LoadedVT = LD->getMemoryVT();
1409  bool isSExtLd = LD->getExtensionType() == ISD::SEXTLOAD;
1410  SDValue Offset;
1411  bool isPre = (AM == ISD::PRE_INC) || (AM == ISD::PRE_DEC);
1412  unsigned Opcode = 0;
1413  bool Match = false;
1414  if (SelectT2AddrModeImm8Offset(N, LD->getOffset(), Offset)) {
1415    switch (LoadedVT.getSimpleVT().SimpleTy) {
1416    case MVT::i32:
1417      Opcode = isPre ? ARM::t2LDR_PRE : ARM::t2LDR_POST;
1418      break;
1419    case MVT::i16:
1420      if (isSExtLd)
1421        Opcode = isPre ? ARM::t2LDRSH_PRE : ARM::t2LDRSH_POST;
1422      else
1423        Opcode = isPre ? ARM::t2LDRH_PRE : ARM::t2LDRH_POST;
1424      break;
1425    case MVT::i8:
1426    case MVT::i1:
1427      if (isSExtLd)
1428        Opcode = isPre ? ARM::t2LDRSB_PRE : ARM::t2LDRSB_POST;
1429      else
1430        Opcode = isPre ? ARM::t2LDRB_PRE : ARM::t2LDRB_POST;
1431      break;
1432    default:
1433      return NULL;
1434    }
1435    Match = true;
1436  }
1437
1438  if (Match) {
1439    SDValue Chain = LD->getChain();
1440    SDValue Base = LD->getBasePtr();
1441    SDValue Ops[]= { Base, Offset, getAL(CurDAG),
1442                     CurDAG->getRegister(0, MVT::i32), Chain };
1443    return CurDAG->getMachineNode(Opcode, N->getDebugLoc(), MVT::i32, MVT::i32,
1444                                  MVT::Other, Ops, 5);
1445  }
1446
1447  return NULL;
1448}
1449
1450/// PairSRegs - Form a D register from a pair of S registers.
1451///
1452SDNode *ARMDAGToDAGISel::PairSRegs(EVT VT, SDValue V0, SDValue V1) {
1453  DebugLoc dl = V0.getNode()->getDebugLoc();
1454  SDValue RegClass =
1455    CurDAG->getTargetConstant(ARM::DPR_VFP2RegClassID, MVT::i32);
1456  SDValue SubReg0 = CurDAG->getTargetConstant(ARM::ssub_0, MVT::i32);
1457  SDValue SubReg1 = CurDAG->getTargetConstant(ARM::ssub_1, MVT::i32);
1458  const SDValue Ops[] = { RegClass, V0, SubReg0, V1, SubReg1 };
1459  return CurDAG->getMachineNode(TargetOpcode::REG_SEQUENCE, dl, VT, Ops, 5);
1460}
1461
1462/// PairDRegs - Form a quad register from a pair of D registers.
1463///
1464SDNode *ARMDAGToDAGISel::PairDRegs(EVT VT, SDValue V0, SDValue V1) {
1465  DebugLoc dl = V0.getNode()->getDebugLoc();
1466  SDValue RegClass = CurDAG->getTargetConstant(ARM::QPRRegClassID, MVT::i32);
1467  SDValue SubReg0 = CurDAG->getTargetConstant(ARM::dsub_0, MVT::i32);
1468  SDValue SubReg1 = CurDAG->getTargetConstant(ARM::dsub_1, MVT::i32);
1469  const SDValue Ops[] = { RegClass, V0, SubReg0, V1, SubReg1 };
1470  return CurDAG->getMachineNode(TargetOpcode::REG_SEQUENCE, dl, VT, Ops, 5);
1471}
1472
1473/// PairQRegs - Form 4 consecutive D registers from a pair of Q registers.
1474///
1475SDNode *ARMDAGToDAGISel::PairQRegs(EVT VT, SDValue V0, SDValue V1) {
1476  DebugLoc dl = V0.getNode()->getDebugLoc();
1477  SDValue RegClass = CurDAG->getTargetConstant(ARM::QQPRRegClassID, MVT::i32);
1478  SDValue SubReg0 = CurDAG->getTargetConstant(ARM::qsub_0, MVT::i32);
1479  SDValue SubReg1 = CurDAG->getTargetConstant(ARM::qsub_1, MVT::i32);
1480  const SDValue Ops[] = { RegClass, V0, SubReg0, V1, SubReg1 };
1481  return CurDAG->getMachineNode(TargetOpcode::REG_SEQUENCE, dl, VT, Ops, 5);
1482}
1483
1484/// QuadSRegs - Form 4 consecutive S registers.
1485///
1486SDNode *ARMDAGToDAGISel::QuadSRegs(EVT VT, SDValue V0, SDValue V1,
1487                                   SDValue V2, SDValue V3) {
1488  DebugLoc dl = V0.getNode()->getDebugLoc();
1489  SDValue RegClass =
1490    CurDAG->getTargetConstant(ARM::QPR_VFP2RegClassID, MVT::i32);
1491  SDValue SubReg0 = CurDAG->getTargetConstant(ARM::ssub_0, MVT::i32);
1492  SDValue SubReg1 = CurDAG->getTargetConstant(ARM::ssub_1, MVT::i32);
1493  SDValue SubReg2 = CurDAG->getTargetConstant(ARM::ssub_2, MVT::i32);
1494  SDValue SubReg3 = CurDAG->getTargetConstant(ARM::ssub_3, MVT::i32);
1495  const SDValue Ops[] = { RegClass, V0, SubReg0, V1, SubReg1,
1496                                    V2, SubReg2, V3, SubReg3 };
1497  return CurDAG->getMachineNode(TargetOpcode::REG_SEQUENCE, dl, VT, Ops, 9);
1498}
1499
1500/// QuadDRegs - Form 4 consecutive D registers.
1501///
1502SDNode *ARMDAGToDAGISel::QuadDRegs(EVT VT, SDValue V0, SDValue V1,
1503                                   SDValue V2, SDValue V3) {
1504  DebugLoc dl = V0.getNode()->getDebugLoc();
1505  SDValue RegClass = CurDAG->getTargetConstant(ARM::QQPRRegClassID, MVT::i32);
1506  SDValue SubReg0 = CurDAG->getTargetConstant(ARM::dsub_0, MVT::i32);
1507  SDValue SubReg1 = CurDAG->getTargetConstant(ARM::dsub_1, MVT::i32);
1508  SDValue SubReg2 = CurDAG->getTargetConstant(ARM::dsub_2, MVT::i32);
1509  SDValue SubReg3 = CurDAG->getTargetConstant(ARM::dsub_3, MVT::i32);
1510  const SDValue Ops[] = { RegClass, V0, SubReg0, V1, SubReg1,
1511                                    V2, SubReg2, V3, SubReg3 };
1512  return CurDAG->getMachineNode(TargetOpcode::REG_SEQUENCE, dl, VT, Ops, 9);
1513}
1514
1515/// QuadQRegs - Form 4 consecutive Q registers.
1516///
1517SDNode *ARMDAGToDAGISel::QuadQRegs(EVT VT, SDValue V0, SDValue V1,
1518                                   SDValue V2, SDValue V3) {
1519  DebugLoc dl = V0.getNode()->getDebugLoc();
1520  SDValue RegClass = CurDAG->getTargetConstant(ARM::QQQQPRRegClassID, MVT::i32);
1521  SDValue SubReg0 = CurDAG->getTargetConstant(ARM::qsub_0, MVT::i32);
1522  SDValue SubReg1 = CurDAG->getTargetConstant(ARM::qsub_1, MVT::i32);
1523  SDValue SubReg2 = CurDAG->getTargetConstant(ARM::qsub_2, MVT::i32);
1524  SDValue SubReg3 = CurDAG->getTargetConstant(ARM::qsub_3, MVT::i32);
1525  const SDValue Ops[] = { RegClass, V0, SubReg0, V1, SubReg1,
1526                                    V2, SubReg2, V3, SubReg3 };
1527  return CurDAG->getMachineNode(TargetOpcode::REG_SEQUENCE, dl, VT, Ops, 9);
1528}
1529
1530/// GetVLDSTAlign - Get the alignment (in bytes) for the alignment operand
1531/// of a NEON VLD or VST instruction.  The supported values depend on the
1532/// number of registers being loaded.
1533SDValue ARMDAGToDAGISel::GetVLDSTAlign(SDValue Align, unsigned NumVecs,
1534                                       bool is64BitVector) {
1535  unsigned NumRegs = NumVecs;
1536  if (!is64BitVector && NumVecs < 3)
1537    NumRegs *= 2;
1538
1539  unsigned Alignment = cast<ConstantSDNode>(Align)->getZExtValue();
1540  if (Alignment >= 32 && NumRegs == 4)
1541    Alignment = 32;
1542  else if (Alignment >= 16 && (NumRegs == 2 || NumRegs == 4))
1543    Alignment = 16;
1544  else if (Alignment >= 8)
1545    Alignment = 8;
1546  else
1547    Alignment = 0;
1548
1549  return CurDAG->getTargetConstant(Alignment, MVT::i32);
1550}
1551
1552// Get the register stride update opcode of a VLD/VST instruction that
1553// is otherwise equivalent to the given fixed stride updating instruction.
1554static unsigned getVLDSTRegisterUpdateOpcode(unsigned Opc) {
1555  switch (Opc) {
1556  default: break;
1557  case ARM::VLD1d8wb_fixed: return ARM::VLD1d8wb_register;
1558  case ARM::VLD1d16wb_fixed: return ARM::VLD1d16wb_register;
1559  case ARM::VLD1d32wb_fixed: return ARM::VLD1d32wb_register;
1560  case ARM::VLD1d64wb_fixed: return ARM::VLD1d64wb_register;
1561  case ARM::VLD1q8wb_fixed: return ARM::VLD1q8wb_register;
1562  case ARM::VLD1q16wb_fixed: return ARM::VLD1q16wb_register;
1563  case ARM::VLD1q32wb_fixed: return ARM::VLD1q32wb_register;
1564  case ARM::VLD1q64wb_fixed: return ARM::VLD1q64wb_register;
1565  }
1566  return Opc; // If not one we handle, return it unchanged.
1567}
1568
1569SDNode *ARMDAGToDAGISel::SelectVLD(SDNode *N, bool isUpdating, unsigned NumVecs,
1570                                   unsigned *DOpcodes, unsigned *QOpcodes0,
1571                                   unsigned *QOpcodes1) {
1572  assert(NumVecs >= 1 && NumVecs <= 4 && "VLD NumVecs out-of-range");
1573  DebugLoc dl = N->getDebugLoc();
1574
1575  SDValue MemAddr, Align;
1576  unsigned AddrOpIdx = isUpdating ? 1 : 2;
1577  if (!SelectAddrMode6(N, N->getOperand(AddrOpIdx), MemAddr, Align))
1578    return NULL;
1579
1580  SDValue Chain = N->getOperand(0);
1581  EVT VT = N->getValueType(0);
1582  bool is64BitVector = VT.is64BitVector();
1583  Align = GetVLDSTAlign(Align, NumVecs, is64BitVector);
1584
1585  unsigned OpcodeIndex;
1586  switch (VT.getSimpleVT().SimpleTy) {
1587  default: llvm_unreachable("unhandled vld type");
1588    // Double-register operations:
1589  case MVT::v8i8:  OpcodeIndex = 0; break;
1590  case MVT::v4i16: OpcodeIndex = 1; break;
1591  case MVT::v2f32:
1592  case MVT::v2i32: OpcodeIndex = 2; break;
1593  case MVT::v1i64: OpcodeIndex = 3; break;
1594    // Quad-register operations:
1595  case MVT::v16i8: OpcodeIndex = 0; break;
1596  case MVT::v8i16: OpcodeIndex = 1; break;
1597  case MVT::v4f32:
1598  case MVT::v4i32: OpcodeIndex = 2; break;
1599  case MVT::v2i64: OpcodeIndex = 3;
1600    assert(NumVecs == 1 && "v2i64 type only supported for VLD1");
1601    break;
1602  }
1603
1604  EVT ResTy;
1605  if (NumVecs == 1)
1606    ResTy = VT;
1607  else {
1608    unsigned ResTyElts = (NumVecs == 3) ? 4 : NumVecs;
1609    if (!is64BitVector)
1610      ResTyElts *= 2;
1611    ResTy = EVT::getVectorVT(*CurDAG->getContext(), MVT::i64, ResTyElts);
1612  }
1613  std::vector<EVT> ResTys;
1614  ResTys.push_back(ResTy);
1615  if (isUpdating)
1616    ResTys.push_back(MVT::i32);
1617  ResTys.push_back(MVT::Other);
1618
1619  SDValue Pred = getAL(CurDAG);
1620  SDValue Reg0 = CurDAG->getRegister(0, MVT::i32);
1621  SDNode *VLd;
1622  SmallVector<SDValue, 7> Ops;
1623
1624  // Double registers and VLD1/VLD2 quad registers are directly supported.
1625  if (is64BitVector || NumVecs <= 2) {
1626    unsigned Opc = (is64BitVector ? DOpcodes[OpcodeIndex] :
1627                    QOpcodes0[OpcodeIndex]);
1628    Ops.push_back(MemAddr);
1629    Ops.push_back(Align);
1630    if (isUpdating) {
1631      SDValue Inc = N->getOperand(AddrOpIdx + 1);
1632      // FIXME: VLD1 fixed increment doesn't need Reg0. Remove the reg0
1633      // case entirely when the rest are updated to that form, too.
1634      // Do that before committing this change. Likewise, the opcode
1635      // update call will become unconditional.
1636      if (NumVecs == 1 && !isa<ConstantSDNode>(Inc.getNode()))
1637        Opc = getVLDSTRegisterUpdateOpcode(Opc);
1638      if (NumVecs != 1 || !isa<ConstantSDNode>(Inc.getNode()))
1639        Ops.push_back(isa<ConstantSDNode>(Inc.getNode()) ? Reg0 : Inc);
1640    }
1641    Ops.push_back(Pred);
1642    Ops.push_back(Reg0);
1643    Ops.push_back(Chain);
1644    VLd = CurDAG->getMachineNode(Opc, dl, ResTys, Ops.data(), Ops.size());
1645
1646  } else {
1647    // Otherwise, quad registers are loaded with two separate instructions,
1648    // where one loads the even registers and the other loads the odd registers.
1649    EVT AddrTy = MemAddr.getValueType();
1650
1651    // Load the even subregs.  This is always an updating load, so that it
1652    // provides the address to the second load for the odd subregs.
1653    SDValue ImplDef =
1654      SDValue(CurDAG->getMachineNode(TargetOpcode::IMPLICIT_DEF, dl, ResTy), 0);
1655    const SDValue OpsA[] = { MemAddr, Align, Reg0, ImplDef, Pred, Reg0, Chain };
1656    SDNode *VLdA = CurDAG->getMachineNode(QOpcodes0[OpcodeIndex], dl,
1657                                          ResTy, AddrTy, MVT::Other, OpsA, 7);
1658    Chain = SDValue(VLdA, 2);
1659
1660    // Load the odd subregs.
1661    Ops.push_back(SDValue(VLdA, 1));
1662    Ops.push_back(Align);
1663    if (isUpdating) {
1664      SDValue Inc = N->getOperand(AddrOpIdx + 1);
1665      assert(isa<ConstantSDNode>(Inc.getNode()) &&
1666             "only constant post-increment update allowed for VLD3/4");
1667      (void)Inc;
1668      Ops.push_back(Reg0);
1669    }
1670    Ops.push_back(SDValue(VLdA, 0));
1671    Ops.push_back(Pred);
1672    Ops.push_back(Reg0);
1673    Ops.push_back(Chain);
1674    VLd = CurDAG->getMachineNode(QOpcodes1[OpcodeIndex], dl, ResTys,
1675                                 Ops.data(), Ops.size());
1676  }
1677
1678  // Transfer memoperands.
1679  MachineSDNode::mmo_iterator MemOp = MF->allocateMemRefsArray(1);
1680  MemOp[0] = cast<MemIntrinsicSDNode>(N)->getMemOperand();
1681  cast<MachineSDNode>(VLd)->setMemRefs(MemOp, MemOp + 1);
1682
1683  if (NumVecs == 1)
1684    return VLd;
1685
1686  // Extract out the subregisters.
1687  SDValue SuperReg = SDValue(VLd, 0);
1688  assert(ARM::dsub_7 == ARM::dsub_0+7 &&
1689         ARM::qsub_3 == ARM::qsub_0+3 && "Unexpected subreg numbering");
1690  unsigned Sub0 = (is64BitVector ? ARM::dsub_0 : ARM::qsub_0);
1691  for (unsigned Vec = 0; Vec < NumVecs; ++Vec)
1692    ReplaceUses(SDValue(N, Vec),
1693                CurDAG->getTargetExtractSubreg(Sub0 + Vec, dl, VT, SuperReg));
1694  ReplaceUses(SDValue(N, NumVecs), SDValue(VLd, 1));
1695  if (isUpdating)
1696    ReplaceUses(SDValue(N, NumVecs + 1), SDValue(VLd, 2));
1697  return NULL;
1698}
1699
1700SDNode *ARMDAGToDAGISel::SelectVST(SDNode *N, bool isUpdating, unsigned NumVecs,
1701                                   unsigned *DOpcodes, unsigned *QOpcodes0,
1702                                   unsigned *QOpcodes1) {
1703  assert(NumVecs >= 1 && NumVecs <= 4 && "VST NumVecs out-of-range");
1704  DebugLoc dl = N->getDebugLoc();
1705
1706  SDValue MemAddr, Align;
1707  unsigned AddrOpIdx = isUpdating ? 1 : 2;
1708  unsigned Vec0Idx = 3; // AddrOpIdx + (isUpdating ? 2 : 1)
1709  if (!SelectAddrMode6(N, N->getOperand(AddrOpIdx), MemAddr, Align))
1710    return NULL;
1711
1712  MachineSDNode::mmo_iterator MemOp = MF->allocateMemRefsArray(1);
1713  MemOp[0] = cast<MemIntrinsicSDNode>(N)->getMemOperand();
1714
1715  SDValue Chain = N->getOperand(0);
1716  EVT VT = N->getOperand(Vec0Idx).getValueType();
1717  bool is64BitVector = VT.is64BitVector();
1718  Align = GetVLDSTAlign(Align, NumVecs, is64BitVector);
1719
1720  unsigned OpcodeIndex;
1721  switch (VT.getSimpleVT().SimpleTy) {
1722  default: llvm_unreachable("unhandled vst type");
1723    // Double-register operations:
1724  case MVT::v8i8:  OpcodeIndex = 0; break;
1725  case MVT::v4i16: OpcodeIndex = 1; break;
1726  case MVT::v2f32:
1727  case MVT::v2i32: OpcodeIndex = 2; break;
1728  case MVT::v1i64: OpcodeIndex = 3; break;
1729    // Quad-register operations:
1730  case MVT::v16i8: OpcodeIndex = 0; break;
1731  case MVT::v8i16: OpcodeIndex = 1; break;
1732  case MVT::v4f32:
1733  case MVT::v4i32: OpcodeIndex = 2; break;
1734  case MVT::v2i64: OpcodeIndex = 3;
1735    assert(NumVecs == 1 && "v2i64 type only supported for VST1");
1736    break;
1737  }
1738
1739  std::vector<EVT> ResTys;
1740  if (isUpdating)
1741    ResTys.push_back(MVT::i32);
1742  ResTys.push_back(MVT::Other);
1743
1744  SDValue Pred = getAL(CurDAG);
1745  SDValue Reg0 = CurDAG->getRegister(0, MVT::i32);
1746  SmallVector<SDValue, 7> Ops;
1747
1748  // Double registers and VST1/VST2 quad registers are directly supported.
1749  if (is64BitVector || NumVecs <= 2) {
1750    SDValue SrcReg;
1751    if (NumVecs == 1) {
1752      SrcReg = N->getOperand(Vec0Idx);
1753    } else if (is64BitVector) {
1754      // Form a REG_SEQUENCE to force register allocation.
1755      SDValue V0 = N->getOperand(Vec0Idx + 0);
1756      SDValue V1 = N->getOperand(Vec0Idx + 1);
1757      if (NumVecs == 2)
1758        SrcReg = SDValue(PairDRegs(MVT::v2i64, V0, V1), 0);
1759      else {
1760        SDValue V2 = N->getOperand(Vec0Idx + 2);
1761        // If it's a vst3, form a quad D-register and leave the last part as
1762        // an undef.
1763        SDValue V3 = (NumVecs == 3)
1764          ? SDValue(CurDAG->getMachineNode(TargetOpcode::IMPLICIT_DEF,dl,VT), 0)
1765          : N->getOperand(Vec0Idx + 3);
1766        SrcReg = SDValue(QuadDRegs(MVT::v4i64, V0, V1, V2, V3), 0);
1767      }
1768    } else {
1769      // Form a QQ register.
1770      SDValue Q0 = N->getOperand(Vec0Idx);
1771      SDValue Q1 = N->getOperand(Vec0Idx + 1);
1772      SrcReg = SDValue(PairQRegs(MVT::v4i64, Q0, Q1), 0);
1773    }
1774
1775    unsigned Opc = (is64BitVector ? DOpcodes[OpcodeIndex] :
1776                    QOpcodes0[OpcodeIndex]);
1777    Ops.push_back(MemAddr);
1778    Ops.push_back(Align);
1779    if (isUpdating) {
1780      SDValue Inc = N->getOperand(AddrOpIdx + 1);
1781      Ops.push_back(isa<ConstantSDNode>(Inc.getNode()) ? Reg0 : Inc);
1782    }
1783    Ops.push_back(SrcReg);
1784    Ops.push_back(Pred);
1785    Ops.push_back(Reg0);
1786    Ops.push_back(Chain);
1787    SDNode *VSt =
1788      CurDAG->getMachineNode(Opc, dl, ResTys, Ops.data(), Ops.size());
1789
1790    // Transfer memoperands.
1791    cast<MachineSDNode>(VSt)->setMemRefs(MemOp, MemOp + 1);
1792
1793    return VSt;
1794  }
1795
1796  // Otherwise, quad registers are stored with two separate instructions,
1797  // where one stores the even registers and the other stores the odd registers.
1798
1799  // Form the QQQQ REG_SEQUENCE.
1800  SDValue V0 = N->getOperand(Vec0Idx + 0);
1801  SDValue V1 = N->getOperand(Vec0Idx + 1);
1802  SDValue V2 = N->getOperand(Vec0Idx + 2);
1803  SDValue V3 = (NumVecs == 3)
1804    ? SDValue(CurDAG->getMachineNode(TargetOpcode::IMPLICIT_DEF, dl, VT), 0)
1805    : N->getOperand(Vec0Idx + 3);
1806  SDValue RegSeq = SDValue(QuadQRegs(MVT::v8i64, V0, V1, V2, V3), 0);
1807
1808  // Store the even D registers.  This is always an updating store, so that it
1809  // provides the address to the second store for the odd subregs.
1810  const SDValue OpsA[] = { MemAddr, Align, Reg0, RegSeq, Pred, Reg0, Chain };
1811  SDNode *VStA = CurDAG->getMachineNode(QOpcodes0[OpcodeIndex], dl,
1812                                        MemAddr.getValueType(),
1813                                        MVT::Other, OpsA, 7);
1814  cast<MachineSDNode>(VStA)->setMemRefs(MemOp, MemOp + 1);
1815  Chain = SDValue(VStA, 1);
1816
1817  // Store the odd D registers.
1818  Ops.push_back(SDValue(VStA, 0));
1819  Ops.push_back(Align);
1820  if (isUpdating) {
1821    SDValue Inc = N->getOperand(AddrOpIdx + 1);
1822    assert(isa<ConstantSDNode>(Inc.getNode()) &&
1823           "only constant post-increment update allowed for VST3/4");
1824    (void)Inc;
1825    Ops.push_back(Reg0);
1826  }
1827  Ops.push_back(RegSeq);
1828  Ops.push_back(Pred);
1829  Ops.push_back(Reg0);
1830  Ops.push_back(Chain);
1831  SDNode *VStB = CurDAG->getMachineNode(QOpcodes1[OpcodeIndex], dl, ResTys,
1832                                        Ops.data(), Ops.size());
1833  cast<MachineSDNode>(VStB)->setMemRefs(MemOp, MemOp + 1);
1834  return VStB;
1835}
1836
1837SDNode *ARMDAGToDAGISel::SelectVLDSTLane(SDNode *N, bool IsLoad,
1838                                         bool isUpdating, unsigned NumVecs,
1839                                         unsigned *DOpcodes,
1840                                         unsigned *QOpcodes) {
1841  assert(NumVecs >=2 && NumVecs <= 4 && "VLDSTLane NumVecs out-of-range");
1842  DebugLoc dl = N->getDebugLoc();
1843
1844  SDValue MemAddr, Align;
1845  unsigned AddrOpIdx = isUpdating ? 1 : 2;
1846  unsigned Vec0Idx = 3; // AddrOpIdx + (isUpdating ? 2 : 1)
1847  if (!SelectAddrMode6(N, N->getOperand(AddrOpIdx), MemAddr, Align))
1848    return NULL;
1849
1850  MachineSDNode::mmo_iterator MemOp = MF->allocateMemRefsArray(1);
1851  MemOp[0] = cast<MemIntrinsicSDNode>(N)->getMemOperand();
1852
1853  SDValue Chain = N->getOperand(0);
1854  unsigned Lane =
1855    cast<ConstantSDNode>(N->getOperand(Vec0Idx + NumVecs))->getZExtValue();
1856  EVT VT = N->getOperand(Vec0Idx).getValueType();
1857  bool is64BitVector = VT.is64BitVector();
1858
1859  unsigned Alignment = 0;
1860  if (NumVecs != 3) {
1861    Alignment = cast<ConstantSDNode>(Align)->getZExtValue();
1862    unsigned NumBytes = NumVecs * VT.getVectorElementType().getSizeInBits()/8;
1863    if (Alignment > NumBytes)
1864      Alignment = NumBytes;
1865    if (Alignment < 8 && Alignment < NumBytes)
1866      Alignment = 0;
1867    // Alignment must be a power of two; make sure of that.
1868    Alignment = (Alignment & -Alignment);
1869    if (Alignment == 1)
1870      Alignment = 0;
1871  }
1872  Align = CurDAG->getTargetConstant(Alignment, MVT::i32);
1873
1874  unsigned OpcodeIndex;
1875  switch (VT.getSimpleVT().SimpleTy) {
1876  default: llvm_unreachable("unhandled vld/vst lane type");
1877    // Double-register operations:
1878  case MVT::v8i8:  OpcodeIndex = 0; break;
1879  case MVT::v4i16: OpcodeIndex = 1; break;
1880  case MVT::v2f32:
1881  case MVT::v2i32: OpcodeIndex = 2; break;
1882    // Quad-register operations:
1883  case MVT::v8i16: OpcodeIndex = 0; break;
1884  case MVT::v4f32:
1885  case MVT::v4i32: OpcodeIndex = 1; break;
1886  }
1887
1888  std::vector<EVT> ResTys;
1889  if (IsLoad) {
1890    unsigned ResTyElts = (NumVecs == 3) ? 4 : NumVecs;
1891    if (!is64BitVector)
1892      ResTyElts *= 2;
1893    ResTys.push_back(EVT::getVectorVT(*CurDAG->getContext(),
1894                                      MVT::i64, ResTyElts));
1895  }
1896  if (isUpdating)
1897    ResTys.push_back(MVT::i32);
1898  ResTys.push_back(MVT::Other);
1899
1900  SDValue Pred = getAL(CurDAG);
1901  SDValue Reg0 = CurDAG->getRegister(0, MVT::i32);
1902
1903  SmallVector<SDValue, 8> Ops;
1904  Ops.push_back(MemAddr);
1905  Ops.push_back(Align);
1906  if (isUpdating) {
1907    SDValue Inc = N->getOperand(AddrOpIdx + 1);
1908    Ops.push_back(isa<ConstantSDNode>(Inc.getNode()) ? Reg0 : Inc);
1909  }
1910
1911  SDValue SuperReg;
1912  SDValue V0 = N->getOperand(Vec0Idx + 0);
1913  SDValue V1 = N->getOperand(Vec0Idx + 1);
1914  if (NumVecs == 2) {
1915    if (is64BitVector)
1916      SuperReg = SDValue(PairDRegs(MVT::v2i64, V0, V1), 0);
1917    else
1918      SuperReg = SDValue(PairQRegs(MVT::v4i64, V0, V1), 0);
1919  } else {
1920    SDValue V2 = N->getOperand(Vec0Idx + 2);
1921    SDValue V3 = (NumVecs == 3)
1922      ? SDValue(CurDAG->getMachineNode(TargetOpcode::IMPLICIT_DEF, dl, VT), 0)
1923      : N->getOperand(Vec0Idx + 3);
1924    if (is64BitVector)
1925      SuperReg = SDValue(QuadDRegs(MVT::v4i64, V0, V1, V2, V3), 0);
1926    else
1927      SuperReg = SDValue(QuadQRegs(MVT::v8i64, V0, V1, V2, V3), 0);
1928  }
1929  Ops.push_back(SuperReg);
1930  Ops.push_back(getI32Imm(Lane));
1931  Ops.push_back(Pred);
1932  Ops.push_back(Reg0);
1933  Ops.push_back(Chain);
1934
1935  unsigned Opc = (is64BitVector ? DOpcodes[OpcodeIndex] :
1936                                  QOpcodes[OpcodeIndex]);
1937  SDNode *VLdLn = CurDAG->getMachineNode(Opc, dl, ResTys,
1938                                         Ops.data(), Ops.size());
1939  cast<MachineSDNode>(VLdLn)->setMemRefs(MemOp, MemOp + 1);
1940  if (!IsLoad)
1941    return VLdLn;
1942
1943  // Extract the subregisters.
1944  SuperReg = SDValue(VLdLn, 0);
1945  assert(ARM::dsub_7 == ARM::dsub_0+7 &&
1946         ARM::qsub_3 == ARM::qsub_0+3 && "Unexpected subreg numbering");
1947  unsigned Sub0 = is64BitVector ? ARM::dsub_0 : ARM::qsub_0;
1948  for (unsigned Vec = 0; Vec < NumVecs; ++Vec)
1949    ReplaceUses(SDValue(N, Vec),
1950                CurDAG->getTargetExtractSubreg(Sub0 + Vec, dl, VT, SuperReg));
1951  ReplaceUses(SDValue(N, NumVecs), SDValue(VLdLn, 1));
1952  if (isUpdating)
1953    ReplaceUses(SDValue(N, NumVecs + 1), SDValue(VLdLn, 2));
1954  return NULL;
1955}
1956
1957SDNode *ARMDAGToDAGISel::SelectVLDDup(SDNode *N, bool isUpdating,
1958                                      unsigned NumVecs, unsigned *Opcodes) {
1959  assert(NumVecs >=2 && NumVecs <= 4 && "VLDDup NumVecs out-of-range");
1960  DebugLoc dl = N->getDebugLoc();
1961
1962  SDValue MemAddr, Align;
1963  if (!SelectAddrMode6(N, N->getOperand(1), MemAddr, Align))
1964    return NULL;
1965
1966  MachineSDNode::mmo_iterator MemOp = MF->allocateMemRefsArray(1);
1967  MemOp[0] = cast<MemIntrinsicSDNode>(N)->getMemOperand();
1968
1969  SDValue Chain = N->getOperand(0);
1970  EVT VT = N->getValueType(0);
1971
1972  unsigned Alignment = 0;
1973  if (NumVecs != 3) {
1974    Alignment = cast<ConstantSDNode>(Align)->getZExtValue();
1975    unsigned NumBytes = NumVecs * VT.getVectorElementType().getSizeInBits()/8;
1976    if (Alignment > NumBytes)
1977      Alignment = NumBytes;
1978    if (Alignment < 8 && Alignment < NumBytes)
1979      Alignment = 0;
1980    // Alignment must be a power of two; make sure of that.
1981    Alignment = (Alignment & -Alignment);
1982    if (Alignment == 1)
1983      Alignment = 0;
1984  }
1985  Align = CurDAG->getTargetConstant(Alignment, MVT::i32);
1986
1987  unsigned OpcodeIndex;
1988  switch (VT.getSimpleVT().SimpleTy) {
1989  default: llvm_unreachable("unhandled vld-dup type");
1990  case MVT::v8i8:  OpcodeIndex = 0; break;
1991  case MVT::v4i16: OpcodeIndex = 1; break;
1992  case MVT::v2f32:
1993  case MVT::v2i32: OpcodeIndex = 2; break;
1994  }
1995
1996  SDValue Pred = getAL(CurDAG);
1997  SDValue Reg0 = CurDAG->getRegister(0, MVT::i32);
1998  SDValue SuperReg;
1999  unsigned Opc = Opcodes[OpcodeIndex];
2000  SmallVector<SDValue, 6> Ops;
2001  Ops.push_back(MemAddr);
2002  Ops.push_back(Align);
2003  if (isUpdating) {
2004    SDValue Inc = N->getOperand(2);
2005    Ops.push_back(isa<ConstantSDNode>(Inc.getNode()) ? Reg0 : Inc);
2006  }
2007  Ops.push_back(Pred);
2008  Ops.push_back(Reg0);
2009  Ops.push_back(Chain);
2010
2011  unsigned ResTyElts = (NumVecs == 3) ? 4 : NumVecs;
2012  std::vector<EVT> ResTys;
2013  ResTys.push_back(EVT::getVectorVT(*CurDAG->getContext(), MVT::i64,ResTyElts));
2014  if (isUpdating)
2015    ResTys.push_back(MVT::i32);
2016  ResTys.push_back(MVT::Other);
2017  SDNode *VLdDup =
2018    CurDAG->getMachineNode(Opc, dl, ResTys, Ops.data(), Ops.size());
2019  cast<MachineSDNode>(VLdDup)->setMemRefs(MemOp, MemOp + 1);
2020  SuperReg = SDValue(VLdDup, 0);
2021
2022  // Extract the subregisters.
2023  assert(ARM::dsub_7 == ARM::dsub_0+7 && "Unexpected subreg numbering");
2024  unsigned SubIdx = ARM::dsub_0;
2025  for (unsigned Vec = 0; Vec < NumVecs; ++Vec)
2026    ReplaceUses(SDValue(N, Vec),
2027                CurDAG->getTargetExtractSubreg(SubIdx+Vec, dl, VT, SuperReg));
2028  ReplaceUses(SDValue(N, NumVecs), SDValue(VLdDup, 1));
2029  if (isUpdating)
2030    ReplaceUses(SDValue(N, NumVecs + 1), SDValue(VLdDup, 2));
2031  return NULL;
2032}
2033
2034SDNode *ARMDAGToDAGISel::SelectVTBL(SDNode *N, bool IsExt, unsigned NumVecs,
2035                                    unsigned Opc) {
2036  assert(NumVecs >= 2 && NumVecs <= 4 && "VTBL NumVecs out-of-range");
2037  DebugLoc dl = N->getDebugLoc();
2038  EVT VT = N->getValueType(0);
2039  unsigned FirstTblReg = IsExt ? 2 : 1;
2040
2041  // Form a REG_SEQUENCE to force register allocation.
2042  SDValue RegSeq;
2043  SDValue V0 = N->getOperand(FirstTblReg + 0);
2044  SDValue V1 = N->getOperand(FirstTblReg + 1);
2045  if (NumVecs == 2)
2046    RegSeq = SDValue(PairDRegs(MVT::v16i8, V0, V1), 0);
2047  else {
2048    SDValue V2 = N->getOperand(FirstTblReg + 2);
2049    // If it's a vtbl3, form a quad D-register and leave the last part as
2050    // an undef.
2051    SDValue V3 = (NumVecs == 3)
2052      ? SDValue(CurDAG->getMachineNode(TargetOpcode::IMPLICIT_DEF, dl, VT), 0)
2053      : N->getOperand(FirstTblReg + 3);
2054    RegSeq = SDValue(QuadDRegs(MVT::v4i64, V0, V1, V2, V3), 0);
2055  }
2056
2057  SmallVector<SDValue, 6> Ops;
2058  if (IsExt)
2059    Ops.push_back(N->getOperand(1));
2060  Ops.push_back(RegSeq);
2061  Ops.push_back(N->getOperand(FirstTblReg + NumVecs));
2062  Ops.push_back(getAL(CurDAG)); // predicate
2063  Ops.push_back(CurDAG->getRegister(0, MVT::i32)); // predicate register
2064  return CurDAG->getMachineNode(Opc, dl, VT, Ops.data(), Ops.size());
2065}
2066
2067SDNode *ARMDAGToDAGISel::SelectV6T2BitfieldExtractOp(SDNode *N,
2068                                                     bool isSigned) {
2069  if (!Subtarget->hasV6T2Ops())
2070    return NULL;
2071
2072  unsigned Opc = isSigned ? (Subtarget->isThumb() ? ARM::t2SBFX : ARM::SBFX)
2073    : (Subtarget->isThumb() ? ARM::t2UBFX : ARM::UBFX);
2074
2075
2076  // For unsigned extracts, check for a shift right and mask
2077  unsigned And_imm = 0;
2078  if (N->getOpcode() == ISD::AND) {
2079    if (isOpcWithIntImmediate(N, ISD::AND, And_imm)) {
2080
2081      // The immediate is a mask of the low bits iff imm & (imm+1) == 0
2082      if (And_imm & (And_imm + 1))
2083        return NULL;
2084
2085      unsigned Srl_imm = 0;
2086      if (isOpcWithIntImmediate(N->getOperand(0).getNode(), ISD::SRL,
2087                                Srl_imm)) {
2088        assert(Srl_imm > 0 && Srl_imm < 32 && "bad amount in shift node!");
2089
2090        // Note: The width operand is encoded as width-1.
2091        unsigned Width = CountTrailingOnes_32(And_imm) - 1;
2092        unsigned LSB = Srl_imm;
2093        SDValue Reg0 = CurDAG->getRegister(0, MVT::i32);
2094        SDValue Ops[] = { N->getOperand(0).getOperand(0),
2095                          CurDAG->getTargetConstant(LSB, MVT::i32),
2096                          CurDAG->getTargetConstant(Width, MVT::i32),
2097          getAL(CurDAG), Reg0 };
2098        return CurDAG->SelectNodeTo(N, Opc, MVT::i32, Ops, 5);
2099      }
2100    }
2101    return NULL;
2102  }
2103
2104  // Otherwise, we're looking for a shift of a shift
2105  unsigned Shl_imm = 0;
2106  if (isOpcWithIntImmediate(N->getOperand(0).getNode(), ISD::SHL, Shl_imm)) {
2107    assert(Shl_imm > 0 && Shl_imm < 32 && "bad amount in shift node!");
2108    unsigned Srl_imm = 0;
2109    if (isInt32Immediate(N->getOperand(1), Srl_imm)) {
2110      assert(Srl_imm > 0 && Srl_imm < 32 && "bad amount in shift node!");
2111      // Note: The width operand is encoded as width-1.
2112      unsigned Width = 32 - Srl_imm - 1;
2113      int LSB = Srl_imm - Shl_imm;
2114      if (LSB < 0)
2115        return NULL;
2116      SDValue Reg0 = CurDAG->getRegister(0, MVT::i32);
2117      SDValue Ops[] = { N->getOperand(0).getOperand(0),
2118                        CurDAG->getTargetConstant(LSB, MVT::i32),
2119                        CurDAG->getTargetConstant(Width, MVT::i32),
2120                        getAL(CurDAG), Reg0 };
2121      return CurDAG->SelectNodeTo(N, Opc, MVT::i32, Ops, 5);
2122    }
2123  }
2124  return NULL;
2125}
2126
2127SDNode *ARMDAGToDAGISel::
2128SelectT2CMOVShiftOp(SDNode *N, SDValue FalseVal, SDValue TrueVal,
2129                    ARMCC::CondCodes CCVal, SDValue CCR, SDValue InFlag) {
2130  SDValue CPTmp0;
2131  SDValue CPTmp1;
2132  if (SelectT2ShifterOperandReg(TrueVal, CPTmp0, CPTmp1)) {
2133    unsigned SOVal = cast<ConstantSDNode>(CPTmp1)->getZExtValue();
2134    unsigned SOShOp = ARM_AM::getSORegShOp(SOVal);
2135    unsigned Opc = 0;
2136    switch (SOShOp) {
2137    case ARM_AM::lsl: Opc = ARM::t2MOVCClsl; break;
2138    case ARM_AM::lsr: Opc = ARM::t2MOVCClsr; break;
2139    case ARM_AM::asr: Opc = ARM::t2MOVCCasr; break;
2140    case ARM_AM::ror: Opc = ARM::t2MOVCCror; break;
2141    default:
2142      llvm_unreachable("Unknown so_reg opcode!");
2143      break;
2144    }
2145    SDValue SOShImm =
2146      CurDAG->getTargetConstant(ARM_AM::getSORegOffset(SOVal), MVT::i32);
2147    SDValue CC = CurDAG->getTargetConstant(CCVal, MVT::i32);
2148    SDValue Ops[] = { FalseVal, CPTmp0, SOShImm, CC, CCR, InFlag };
2149    return CurDAG->SelectNodeTo(N, Opc, MVT::i32,Ops, 6);
2150  }
2151  return 0;
2152}
2153
2154SDNode *ARMDAGToDAGISel::
2155SelectARMCMOVShiftOp(SDNode *N, SDValue FalseVal, SDValue TrueVal,
2156                     ARMCC::CondCodes CCVal, SDValue CCR, SDValue InFlag) {
2157  SDValue CPTmp0;
2158  SDValue CPTmp1;
2159  SDValue CPTmp2;
2160  if (SelectImmShifterOperand(TrueVal, CPTmp0, CPTmp2)) {
2161    SDValue CC = CurDAG->getTargetConstant(CCVal, MVT::i32);
2162    SDValue Ops[] = { FalseVal, CPTmp0, CPTmp2, CC, CCR, InFlag };
2163    return CurDAG->SelectNodeTo(N, ARM::MOVCCsi, MVT::i32, Ops, 6);
2164  }
2165
2166  if (SelectRegShifterOperand(TrueVal, CPTmp0, CPTmp1, CPTmp2)) {
2167    SDValue CC = CurDAG->getTargetConstant(CCVal, MVT::i32);
2168    SDValue Ops[] = { FalseVal, CPTmp0, CPTmp1, CPTmp2, CC, CCR, InFlag };
2169    return CurDAG->SelectNodeTo(N, ARM::MOVCCsr, MVT::i32, Ops, 7);
2170  }
2171  return 0;
2172}
2173
2174SDNode *ARMDAGToDAGISel::
2175SelectT2CMOVImmOp(SDNode *N, SDValue FalseVal, SDValue TrueVal,
2176                  ARMCC::CondCodes CCVal, SDValue CCR, SDValue InFlag) {
2177  ConstantSDNode *T = dyn_cast<ConstantSDNode>(TrueVal);
2178  if (!T)
2179    return 0;
2180
2181  unsigned Opc = 0;
2182  unsigned TrueImm = T->getZExtValue();
2183  if (is_t2_so_imm(TrueImm)) {
2184    Opc = ARM::t2MOVCCi;
2185  } else if (TrueImm <= 0xffff) {
2186    Opc = ARM::t2MOVCCi16;
2187  } else if (is_t2_so_imm_not(TrueImm)) {
2188    TrueImm = ~TrueImm;
2189    Opc = ARM::t2MVNCCi;
2190  } else if (TrueVal.getNode()->hasOneUse() && Subtarget->hasV6T2Ops()) {
2191    // Large immediate.
2192    Opc = ARM::t2MOVCCi32imm;
2193  }
2194
2195  if (Opc) {
2196    SDValue True = CurDAG->getTargetConstant(TrueImm, MVT::i32);
2197    SDValue CC = CurDAG->getTargetConstant(CCVal, MVT::i32);
2198    SDValue Ops[] = { FalseVal, True, CC, CCR, InFlag };
2199    return CurDAG->SelectNodeTo(N, Opc, MVT::i32, Ops, 5);
2200  }
2201
2202  return 0;
2203}
2204
2205SDNode *ARMDAGToDAGISel::
2206SelectARMCMOVImmOp(SDNode *N, SDValue FalseVal, SDValue TrueVal,
2207                   ARMCC::CondCodes CCVal, SDValue CCR, SDValue InFlag) {
2208  ConstantSDNode *T = dyn_cast<ConstantSDNode>(TrueVal);
2209  if (!T)
2210    return 0;
2211
2212  unsigned Opc = 0;
2213  unsigned TrueImm = T->getZExtValue();
2214  bool isSoImm = is_so_imm(TrueImm);
2215  if (isSoImm) {
2216    Opc = ARM::MOVCCi;
2217  } else if (Subtarget->hasV6T2Ops() && TrueImm <= 0xffff) {
2218    Opc = ARM::MOVCCi16;
2219  } else if (is_so_imm_not(TrueImm)) {
2220    TrueImm = ~TrueImm;
2221    Opc = ARM::MVNCCi;
2222  } else if (TrueVal.getNode()->hasOneUse() &&
2223             (Subtarget->hasV6T2Ops() || ARM_AM::isSOImmTwoPartVal(TrueImm))) {
2224    // Large immediate.
2225    Opc = ARM::MOVCCi32imm;
2226  }
2227
2228  if (Opc) {
2229    SDValue True = CurDAG->getTargetConstant(TrueImm, MVT::i32);
2230    SDValue CC = CurDAG->getTargetConstant(CCVal, MVT::i32);
2231    SDValue Ops[] = { FalseVal, True, CC, CCR, InFlag };
2232    return CurDAG->SelectNodeTo(N, Opc, MVT::i32, Ops, 5);
2233  }
2234
2235  return 0;
2236}
2237
2238SDNode *ARMDAGToDAGISel::SelectCMOVOp(SDNode *N) {
2239  EVT VT = N->getValueType(0);
2240  SDValue FalseVal = N->getOperand(0);
2241  SDValue TrueVal  = N->getOperand(1);
2242  SDValue CC = N->getOperand(2);
2243  SDValue CCR = N->getOperand(3);
2244  SDValue InFlag = N->getOperand(4);
2245  assert(CC.getOpcode() == ISD::Constant);
2246  assert(CCR.getOpcode() == ISD::Register);
2247  ARMCC::CondCodes CCVal =
2248    (ARMCC::CondCodes)cast<ConstantSDNode>(CC)->getZExtValue();
2249
2250  if (!Subtarget->isThumb1Only() && VT == MVT::i32) {
2251    // Pattern: (ARMcmov:i32 GPR:i32:$false, so_reg:i32:$true, (imm:i32):$cc)
2252    // Emits: (MOVCCs:i32 GPR:i32:$false, so_reg:i32:$true, (imm:i32):$cc)
2253    // Pattern complexity = 18  cost = 1  size = 0
2254    SDValue CPTmp0;
2255    SDValue CPTmp1;
2256    SDValue CPTmp2;
2257    if (Subtarget->isThumb()) {
2258      SDNode *Res = SelectT2CMOVShiftOp(N, FalseVal, TrueVal,
2259                                        CCVal, CCR, InFlag);
2260      if (!Res)
2261        Res = SelectT2CMOVShiftOp(N, TrueVal, FalseVal,
2262                               ARMCC::getOppositeCondition(CCVal), CCR, InFlag);
2263      if (Res)
2264        return Res;
2265    } else {
2266      SDNode *Res = SelectARMCMOVShiftOp(N, FalseVal, TrueVal,
2267                                         CCVal, CCR, InFlag);
2268      if (!Res)
2269        Res = SelectARMCMOVShiftOp(N, TrueVal, FalseVal,
2270                               ARMCC::getOppositeCondition(CCVal), CCR, InFlag);
2271      if (Res)
2272        return Res;
2273    }
2274
2275    // Pattern: (ARMcmov:i32 GPR:i32:$false,
2276    //             (imm:i32)<<P:Pred_so_imm>>:$true,
2277    //             (imm:i32):$cc)
2278    // Emits: (MOVCCi:i32 GPR:i32:$false,
2279    //           (so_imm:i32 (imm:i32):$true), (imm:i32):$cc)
2280    // Pattern complexity = 10  cost = 1  size = 0
2281    if (Subtarget->isThumb()) {
2282      SDNode *Res = SelectT2CMOVImmOp(N, FalseVal, TrueVal,
2283                                        CCVal, CCR, InFlag);
2284      if (!Res)
2285        Res = SelectT2CMOVImmOp(N, TrueVal, FalseVal,
2286                               ARMCC::getOppositeCondition(CCVal), CCR, InFlag);
2287      if (Res)
2288        return Res;
2289    } else {
2290      SDNode *Res = SelectARMCMOVImmOp(N, FalseVal, TrueVal,
2291                                         CCVal, CCR, InFlag);
2292      if (!Res)
2293        Res = SelectARMCMOVImmOp(N, TrueVal, FalseVal,
2294                               ARMCC::getOppositeCondition(CCVal), CCR, InFlag);
2295      if (Res)
2296        return Res;
2297    }
2298  }
2299
2300  // Pattern: (ARMcmov:i32 GPR:i32:$false, GPR:i32:$true, (imm:i32):$cc)
2301  // Emits: (MOVCCr:i32 GPR:i32:$false, GPR:i32:$true, (imm:i32):$cc)
2302  // Pattern complexity = 6  cost = 1  size = 0
2303  //
2304  // Pattern: (ARMcmov:i32 GPR:i32:$false, GPR:i32:$true, (imm:i32):$cc)
2305  // Emits: (tMOVCCr:i32 GPR:i32:$false, GPR:i32:$true, (imm:i32):$cc)
2306  // Pattern complexity = 6  cost = 11  size = 0
2307  //
2308  // Also VMOVScc and VMOVDcc.
2309  SDValue Tmp2 = CurDAG->getTargetConstant(CCVal, MVT::i32);
2310  SDValue Ops[] = { FalseVal, TrueVal, Tmp2, CCR, InFlag };
2311  unsigned Opc = 0;
2312  switch (VT.getSimpleVT().SimpleTy) {
2313  default: assert(false && "Illegal conditional move type!");
2314    break;
2315  case MVT::i32:
2316    Opc = Subtarget->isThumb()
2317      ? (Subtarget->hasThumb2() ? ARM::t2MOVCCr : ARM::tMOVCCr_pseudo)
2318      : ARM::MOVCCr;
2319    break;
2320  case MVT::f32:
2321    Opc = ARM::VMOVScc;
2322    break;
2323  case MVT::f64:
2324    Opc = ARM::VMOVDcc;
2325    break;
2326  }
2327  return CurDAG->SelectNodeTo(N, Opc, VT, Ops, 5);
2328}
2329
2330/// Target-specific DAG combining for ISD::XOR.
2331/// Target-independent combining lowers SELECT_CC nodes of the form
2332/// select_cc setg[ge] X,  0,  X, -X
2333/// select_cc setgt    X, -1,  X, -X
2334/// select_cc setl[te] X,  0, -X,  X
2335/// select_cc setlt    X,  1, -X,  X
2336/// which represent Integer ABS into:
2337/// Y = sra (X, size(X)-1); xor (add (X, Y), Y)
2338/// ARM instruction selection detects the latter and matches it to
2339/// ARM::ABS or ARM::t2ABS machine node.
2340SDNode *ARMDAGToDAGISel::SelectABSOp(SDNode *N){
2341  SDValue XORSrc0 = N->getOperand(0);
2342  SDValue XORSrc1 = N->getOperand(1);
2343  EVT VT = N->getValueType(0);
2344
2345  if (DisableARMIntABS)
2346    return NULL;
2347
2348  if (Subtarget->isThumb1Only())
2349    return NULL;
2350
2351  if (XORSrc0.getOpcode() != ISD::ADD ||
2352    XORSrc1.getOpcode() != ISD::SRA)
2353    return NULL;
2354
2355  SDValue ADDSrc0 = XORSrc0.getOperand(0);
2356  SDValue ADDSrc1 = XORSrc0.getOperand(1);
2357  SDValue SRASrc0 = XORSrc1.getOperand(0);
2358  SDValue SRASrc1 = XORSrc1.getOperand(1);
2359  ConstantSDNode *SRAConstant =  dyn_cast<ConstantSDNode>(SRASrc1);
2360  EVT XType = SRASrc0.getValueType();
2361  unsigned Size = XType.getSizeInBits() - 1;
2362
2363  if (ADDSrc1 == XORSrc1  &&
2364      ADDSrc0 == SRASrc0 &&
2365      XType.isInteger() &&
2366      SRAConstant != NULL &&
2367      Size == SRAConstant->getZExtValue()) {
2368
2369    unsigned Opcode = ARM::ABS;
2370    if (Subtarget->isThumb2())
2371      Opcode = ARM::t2ABS;
2372
2373    return CurDAG->SelectNodeTo(N, Opcode, VT, ADDSrc0);
2374  }
2375
2376  return NULL;
2377}
2378
2379SDNode *ARMDAGToDAGISel::SelectConcatVector(SDNode *N) {
2380  // The only time a CONCAT_VECTORS operation can have legal types is when
2381  // two 64-bit vectors are concatenated to a 128-bit vector.
2382  EVT VT = N->getValueType(0);
2383  if (!VT.is128BitVector() || N->getNumOperands() != 2)
2384    llvm_unreachable("unexpected CONCAT_VECTORS");
2385  return PairDRegs(VT, N->getOperand(0), N->getOperand(1));
2386}
2387
2388SDNode *ARMDAGToDAGISel::SelectAtomic64(SDNode *Node, unsigned Opc) {
2389  SmallVector<SDValue, 6> Ops;
2390  Ops.push_back(Node->getOperand(1)); // Ptr
2391  Ops.push_back(Node->getOperand(2)); // Low part of Val1
2392  Ops.push_back(Node->getOperand(3)); // High part of Val1
2393  if (Opc == ARM::ATOMCMPXCHG6432) {
2394    Ops.push_back(Node->getOperand(4)); // Low part of Val2
2395    Ops.push_back(Node->getOperand(5)); // High part of Val2
2396  }
2397  Ops.push_back(Node->getOperand(0)); // Chain
2398  MachineSDNode::mmo_iterator MemOp = MF->allocateMemRefsArray(1);
2399  MemOp[0] = cast<MemSDNode>(Node)->getMemOperand();
2400  SDNode *ResNode = CurDAG->getMachineNode(Opc, Node->getDebugLoc(),
2401                                           MVT::i32, MVT::i32, MVT::Other,
2402                                           Ops.data() ,Ops.size());
2403  cast<MachineSDNode>(ResNode)->setMemRefs(MemOp, MemOp + 1);
2404  return ResNode;
2405}
2406
2407SDNode *ARMDAGToDAGISel::Select(SDNode *N) {
2408  DebugLoc dl = N->getDebugLoc();
2409
2410  if (N->isMachineOpcode())
2411    return NULL;   // Already selected.
2412
2413  switch (N->getOpcode()) {
2414  default: break;
2415  case ISD::XOR: {
2416    // Select special operations if XOR node forms integer ABS pattern
2417    SDNode *ResNode = SelectABSOp(N);
2418    if (ResNode)
2419      return ResNode;
2420    // Other cases are autogenerated.
2421    break;
2422  }
2423  case ISD::Constant: {
2424    unsigned Val = cast<ConstantSDNode>(N)->getZExtValue();
2425    bool UseCP = true;
2426    if (Subtarget->hasThumb2())
2427      // Thumb2-aware targets have the MOVT instruction, so all immediates can
2428      // be done with MOV + MOVT, at worst.
2429      UseCP = 0;
2430    else {
2431      if (Subtarget->isThumb()) {
2432        UseCP = (Val > 255 &&                          // MOV
2433                 ~Val > 255 &&                         // MOV + MVN
2434                 !ARM_AM::isThumbImmShiftedVal(Val));  // MOV + LSL
2435      } else
2436        UseCP = (ARM_AM::getSOImmVal(Val) == -1 &&     // MOV
2437                 ARM_AM::getSOImmVal(~Val) == -1 &&    // MVN
2438                 !ARM_AM::isSOImmTwoPartVal(Val));     // two instrs.
2439    }
2440
2441    if (UseCP) {
2442      SDValue CPIdx =
2443        CurDAG->getTargetConstantPool(ConstantInt::get(
2444                                  Type::getInt32Ty(*CurDAG->getContext()), Val),
2445                                      TLI.getPointerTy());
2446
2447      SDNode *ResNode;
2448      if (Subtarget->isThumb1Only()) {
2449        SDValue Pred = getAL(CurDAG);
2450        SDValue PredReg = CurDAG->getRegister(0, MVT::i32);
2451        SDValue Ops[] = { CPIdx, Pred, PredReg, CurDAG->getEntryNode() };
2452        ResNode = CurDAG->getMachineNode(ARM::tLDRpci, dl, MVT::i32, MVT::Other,
2453                                         Ops, 4);
2454      } else {
2455        SDValue Ops[] = {
2456          CPIdx,
2457          CurDAG->getTargetConstant(0, MVT::i32),
2458          getAL(CurDAG),
2459          CurDAG->getRegister(0, MVT::i32),
2460          CurDAG->getEntryNode()
2461        };
2462        ResNode=CurDAG->getMachineNode(ARM::LDRcp, dl, MVT::i32, MVT::Other,
2463                                       Ops, 5);
2464      }
2465      ReplaceUses(SDValue(N, 0), SDValue(ResNode, 0));
2466      return NULL;
2467    }
2468
2469    // Other cases are autogenerated.
2470    break;
2471  }
2472  case ISD::FrameIndex: {
2473    // Selects to ADDri FI, 0 which in turn will become ADDri SP, imm.
2474    int FI = cast<FrameIndexSDNode>(N)->getIndex();
2475    SDValue TFI = CurDAG->getTargetFrameIndex(FI, TLI.getPointerTy());
2476    if (Subtarget->isThumb1Only()) {
2477      SDValue Ops[] = { TFI, CurDAG->getTargetConstant(0, MVT::i32),
2478                        getAL(CurDAG), CurDAG->getRegister(0, MVT::i32) };
2479      return CurDAG->SelectNodeTo(N, ARM::tADDrSPi, MVT::i32, Ops, 4);
2480    } else {
2481      unsigned Opc = ((Subtarget->isThumb() && Subtarget->hasThumb2()) ?
2482                      ARM::t2ADDri : ARM::ADDri);
2483      SDValue Ops[] = { TFI, CurDAG->getTargetConstant(0, MVT::i32),
2484                        getAL(CurDAG), CurDAG->getRegister(0, MVT::i32),
2485                        CurDAG->getRegister(0, MVT::i32) };
2486      return CurDAG->SelectNodeTo(N, Opc, MVT::i32, Ops, 5);
2487    }
2488  }
2489  case ISD::SRL:
2490    if (SDNode *I = SelectV6T2BitfieldExtractOp(N, false))
2491      return I;
2492    break;
2493  case ISD::SRA:
2494    if (SDNode *I = SelectV6T2BitfieldExtractOp(N, true))
2495      return I;
2496    break;
2497  case ISD::MUL:
2498    if (Subtarget->isThumb1Only())
2499      break;
2500    if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(1))) {
2501      unsigned RHSV = C->getZExtValue();
2502      if (!RHSV) break;
2503      if (isPowerOf2_32(RHSV-1)) {  // 2^n+1?
2504        unsigned ShImm = Log2_32(RHSV-1);
2505        if (ShImm >= 32)
2506          break;
2507        SDValue V = N->getOperand(0);
2508        ShImm = ARM_AM::getSORegOpc(ARM_AM::lsl, ShImm);
2509        SDValue ShImmOp = CurDAG->getTargetConstant(ShImm, MVT::i32);
2510        SDValue Reg0 = CurDAG->getRegister(0, MVT::i32);
2511        if (Subtarget->isThumb()) {
2512          SDValue Ops[] = { V, V, ShImmOp, getAL(CurDAG), Reg0, Reg0 };
2513          return CurDAG->SelectNodeTo(N, ARM::t2ADDrs, MVT::i32, Ops, 6);
2514        } else {
2515          SDValue Ops[] = { V, V, Reg0, ShImmOp, getAL(CurDAG), Reg0, Reg0 };
2516          return CurDAG->SelectNodeTo(N, ARM::ADDrsi, MVT::i32, Ops, 7);
2517        }
2518      }
2519      if (isPowerOf2_32(RHSV+1)) {  // 2^n-1?
2520        unsigned ShImm = Log2_32(RHSV+1);
2521        if (ShImm >= 32)
2522          break;
2523        SDValue V = N->getOperand(0);
2524        ShImm = ARM_AM::getSORegOpc(ARM_AM::lsl, ShImm);
2525        SDValue ShImmOp = CurDAG->getTargetConstant(ShImm, MVT::i32);
2526        SDValue Reg0 = CurDAG->getRegister(0, MVT::i32);
2527        if (Subtarget->isThumb()) {
2528          SDValue Ops[] = { V, V, ShImmOp, getAL(CurDAG), Reg0, Reg0 };
2529          return CurDAG->SelectNodeTo(N, ARM::t2RSBrs, MVT::i32, Ops, 6);
2530        } else {
2531          SDValue Ops[] = { V, V, Reg0, ShImmOp, getAL(CurDAG), Reg0, Reg0 };
2532          return CurDAG->SelectNodeTo(N, ARM::RSBrsi, MVT::i32, Ops, 7);
2533        }
2534      }
2535    }
2536    break;
2537  case ISD::AND: {
2538    // Check for unsigned bitfield extract
2539    if (SDNode *I = SelectV6T2BitfieldExtractOp(N, false))
2540      return I;
2541
2542    // (and (or x, c2), c1) and top 16-bits of c1 and c2 match, lower 16-bits
2543    // of c1 are 0xffff, and lower 16-bit of c2 are 0. That is, the top 16-bits
2544    // are entirely contributed by c2 and lower 16-bits are entirely contributed
2545    // by x. That's equal to (or (and x, 0xffff), (and c1, 0xffff0000)).
2546    // Select it to: "movt x, ((c1 & 0xffff) >> 16)
2547    EVT VT = N->getValueType(0);
2548    if (VT != MVT::i32)
2549      break;
2550    unsigned Opc = (Subtarget->isThumb() && Subtarget->hasThumb2())
2551      ? ARM::t2MOVTi16
2552      : (Subtarget->hasV6T2Ops() ? ARM::MOVTi16 : 0);
2553    if (!Opc)
2554      break;
2555    SDValue N0 = N->getOperand(0), N1 = N->getOperand(1);
2556    ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
2557    if (!N1C)
2558      break;
2559    if (N0.getOpcode() == ISD::OR && N0.getNode()->hasOneUse()) {
2560      SDValue N2 = N0.getOperand(1);
2561      ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(N2);
2562      if (!N2C)
2563        break;
2564      unsigned N1CVal = N1C->getZExtValue();
2565      unsigned N2CVal = N2C->getZExtValue();
2566      if ((N1CVal & 0xffff0000U) == (N2CVal & 0xffff0000U) &&
2567          (N1CVal & 0xffffU) == 0xffffU &&
2568          (N2CVal & 0xffffU) == 0x0U) {
2569        SDValue Imm16 = CurDAG->getTargetConstant((N2CVal & 0xFFFF0000U) >> 16,
2570                                                  MVT::i32);
2571        SDValue Ops[] = { N0.getOperand(0), Imm16,
2572                          getAL(CurDAG), CurDAG->getRegister(0, MVT::i32) };
2573        return CurDAG->getMachineNode(Opc, dl, VT, Ops, 4);
2574      }
2575    }
2576    break;
2577  }
2578  case ARMISD::VMOVRRD:
2579    return CurDAG->getMachineNode(ARM::VMOVRRD, dl, MVT::i32, MVT::i32,
2580                                  N->getOperand(0), getAL(CurDAG),
2581                                  CurDAG->getRegister(0, MVT::i32));
2582  case ISD::UMUL_LOHI: {
2583    if (Subtarget->isThumb1Only())
2584      break;
2585    if (Subtarget->isThumb()) {
2586      SDValue Ops[] = { N->getOperand(0), N->getOperand(1),
2587                        getAL(CurDAG), CurDAG->getRegister(0, MVT::i32),
2588                        CurDAG->getRegister(0, MVT::i32) };
2589      return CurDAG->getMachineNode(ARM::t2UMULL, dl, MVT::i32, MVT::i32,Ops,4);
2590    } else {
2591      SDValue Ops[] = { N->getOperand(0), N->getOperand(1),
2592                        getAL(CurDAG), CurDAG->getRegister(0, MVT::i32),
2593                        CurDAG->getRegister(0, MVT::i32) };
2594      return CurDAG->getMachineNode(Subtarget->hasV6Ops() ?
2595                                    ARM::UMULL : ARM::UMULLv5,
2596                                    dl, MVT::i32, MVT::i32, Ops, 5);
2597    }
2598  }
2599  case ISD::SMUL_LOHI: {
2600    if (Subtarget->isThumb1Only())
2601      break;
2602    if (Subtarget->isThumb()) {
2603      SDValue Ops[] = { N->getOperand(0), N->getOperand(1),
2604                        getAL(CurDAG), CurDAG->getRegister(0, MVT::i32) };
2605      return CurDAG->getMachineNode(ARM::t2SMULL, dl, MVT::i32, MVT::i32,Ops,4);
2606    } else {
2607      SDValue Ops[] = { N->getOperand(0), N->getOperand(1),
2608                        getAL(CurDAG), CurDAG->getRegister(0, MVT::i32),
2609                        CurDAG->getRegister(0, MVT::i32) };
2610      return CurDAG->getMachineNode(Subtarget->hasV6Ops() ?
2611                                    ARM::SMULL : ARM::SMULLv5,
2612                                    dl, MVT::i32, MVT::i32, Ops, 5);
2613    }
2614  }
2615  case ISD::LOAD: {
2616    SDNode *ResNode = 0;
2617    if (Subtarget->isThumb() && Subtarget->hasThumb2())
2618      ResNode = SelectT2IndexedLoad(N);
2619    else
2620      ResNode = SelectARMIndexedLoad(N);
2621    if (ResNode)
2622      return ResNode;
2623    // Other cases are autogenerated.
2624    break;
2625  }
2626  case ARMISD::BRCOND: {
2627    // Pattern: (ARMbrcond:void (bb:Other):$dst, (imm:i32):$cc)
2628    // Emits: (Bcc:void (bb:Other):$dst, (imm:i32):$cc)
2629    // Pattern complexity = 6  cost = 1  size = 0
2630
2631    // Pattern: (ARMbrcond:void (bb:Other):$dst, (imm:i32):$cc)
2632    // Emits: (tBcc:void (bb:Other):$dst, (imm:i32):$cc)
2633    // Pattern complexity = 6  cost = 1  size = 0
2634
2635    // Pattern: (ARMbrcond:void (bb:Other):$dst, (imm:i32):$cc)
2636    // Emits: (t2Bcc:void (bb:Other):$dst, (imm:i32):$cc)
2637    // Pattern complexity = 6  cost = 1  size = 0
2638
2639    unsigned Opc = Subtarget->isThumb() ?
2640      ((Subtarget->hasThumb2()) ? ARM::t2Bcc : ARM::tBcc) : ARM::Bcc;
2641    SDValue Chain = N->getOperand(0);
2642    SDValue N1 = N->getOperand(1);
2643    SDValue N2 = N->getOperand(2);
2644    SDValue N3 = N->getOperand(3);
2645    SDValue InFlag = N->getOperand(4);
2646    assert(N1.getOpcode() == ISD::BasicBlock);
2647    assert(N2.getOpcode() == ISD::Constant);
2648    assert(N3.getOpcode() == ISD::Register);
2649
2650    SDValue Tmp2 = CurDAG->getTargetConstant(((unsigned)
2651                               cast<ConstantSDNode>(N2)->getZExtValue()),
2652                               MVT::i32);
2653    SDValue Ops[] = { N1, Tmp2, N3, Chain, InFlag };
2654    SDNode *ResNode = CurDAG->getMachineNode(Opc, dl, MVT::Other,
2655                                             MVT::Glue, Ops, 5);
2656    Chain = SDValue(ResNode, 0);
2657    if (N->getNumValues() == 2) {
2658      InFlag = SDValue(ResNode, 1);
2659      ReplaceUses(SDValue(N, 1), InFlag);
2660    }
2661    ReplaceUses(SDValue(N, 0),
2662                SDValue(Chain.getNode(), Chain.getResNo()));
2663    return NULL;
2664  }
2665  case ARMISD::CMOV:
2666    return SelectCMOVOp(N);
2667  case ARMISD::VZIP: {
2668    unsigned Opc = 0;
2669    EVT VT = N->getValueType(0);
2670    switch (VT.getSimpleVT().SimpleTy) {
2671    default: return NULL;
2672    case MVT::v8i8:  Opc = ARM::VZIPd8; break;
2673    case MVT::v4i16: Opc = ARM::VZIPd16; break;
2674    case MVT::v2f32:
2675    case MVT::v2i32: Opc = ARM::VZIPd32; break;
2676    case MVT::v16i8: Opc = ARM::VZIPq8; break;
2677    case MVT::v8i16: Opc = ARM::VZIPq16; break;
2678    case MVT::v4f32:
2679    case MVT::v4i32: Opc = ARM::VZIPq32; break;
2680    }
2681    SDValue Pred = getAL(CurDAG);
2682    SDValue PredReg = CurDAG->getRegister(0, MVT::i32);
2683    SDValue Ops[] = { N->getOperand(0), N->getOperand(1), Pred, PredReg };
2684    return CurDAG->getMachineNode(Opc, dl, VT, VT, Ops, 4);
2685  }
2686  case ARMISD::VUZP: {
2687    unsigned Opc = 0;
2688    EVT VT = N->getValueType(0);
2689    switch (VT.getSimpleVT().SimpleTy) {
2690    default: return NULL;
2691    case MVT::v8i8:  Opc = ARM::VUZPd8; break;
2692    case MVT::v4i16: Opc = ARM::VUZPd16; break;
2693    case MVT::v2f32:
2694    case MVT::v2i32: Opc = ARM::VUZPd32; break;
2695    case MVT::v16i8: Opc = ARM::VUZPq8; break;
2696    case MVT::v8i16: Opc = ARM::VUZPq16; break;
2697    case MVT::v4f32:
2698    case MVT::v4i32: Opc = ARM::VUZPq32; break;
2699    }
2700    SDValue Pred = getAL(CurDAG);
2701    SDValue PredReg = CurDAG->getRegister(0, MVT::i32);
2702    SDValue Ops[] = { N->getOperand(0), N->getOperand(1), Pred, PredReg };
2703    return CurDAG->getMachineNode(Opc, dl, VT, VT, Ops, 4);
2704  }
2705  case ARMISD::VTRN: {
2706    unsigned Opc = 0;
2707    EVT VT = N->getValueType(0);
2708    switch (VT.getSimpleVT().SimpleTy) {
2709    default: return NULL;
2710    case MVT::v8i8:  Opc = ARM::VTRNd8; break;
2711    case MVT::v4i16: Opc = ARM::VTRNd16; break;
2712    case MVT::v2f32:
2713    case MVT::v2i32: Opc = ARM::VTRNd32; break;
2714    case MVT::v16i8: Opc = ARM::VTRNq8; break;
2715    case MVT::v8i16: Opc = ARM::VTRNq16; break;
2716    case MVT::v4f32:
2717    case MVT::v4i32: Opc = ARM::VTRNq32; break;
2718    }
2719    SDValue Pred = getAL(CurDAG);
2720    SDValue PredReg = CurDAG->getRegister(0, MVT::i32);
2721    SDValue Ops[] = { N->getOperand(0), N->getOperand(1), Pred, PredReg };
2722    return CurDAG->getMachineNode(Opc, dl, VT, VT, Ops, 4);
2723  }
2724  case ARMISD::BUILD_VECTOR: {
2725    EVT VecVT = N->getValueType(0);
2726    EVT EltVT = VecVT.getVectorElementType();
2727    unsigned NumElts = VecVT.getVectorNumElements();
2728    if (EltVT == MVT::f64) {
2729      assert(NumElts == 2 && "unexpected type for BUILD_VECTOR");
2730      return PairDRegs(VecVT, N->getOperand(0), N->getOperand(1));
2731    }
2732    assert(EltVT == MVT::f32 && "unexpected type for BUILD_VECTOR");
2733    if (NumElts == 2)
2734      return PairSRegs(VecVT, N->getOperand(0), N->getOperand(1));
2735    assert(NumElts == 4 && "unexpected type for BUILD_VECTOR");
2736    return QuadSRegs(VecVT, N->getOperand(0), N->getOperand(1),
2737                     N->getOperand(2), N->getOperand(3));
2738  }
2739
2740  case ARMISD::VLD2DUP: {
2741    unsigned Opcodes[] = { ARM::VLD2DUPd8Pseudo, ARM::VLD2DUPd16Pseudo,
2742                           ARM::VLD2DUPd32Pseudo };
2743    return SelectVLDDup(N, false, 2, Opcodes);
2744  }
2745
2746  case ARMISD::VLD3DUP: {
2747    unsigned Opcodes[] = { ARM::VLD3DUPd8Pseudo, ARM::VLD3DUPd16Pseudo,
2748                           ARM::VLD3DUPd32Pseudo };
2749    return SelectVLDDup(N, false, 3, Opcodes);
2750  }
2751
2752  case ARMISD::VLD4DUP: {
2753    unsigned Opcodes[] = { ARM::VLD4DUPd8Pseudo, ARM::VLD4DUPd16Pseudo,
2754                           ARM::VLD4DUPd32Pseudo };
2755    return SelectVLDDup(N, false, 4, Opcodes);
2756  }
2757
2758  case ARMISD::VLD2DUP_UPD: {
2759    unsigned Opcodes[] = { ARM::VLD2DUPd8Pseudo_UPD, ARM::VLD2DUPd16Pseudo_UPD,
2760                           ARM::VLD2DUPd32Pseudo_UPD };
2761    return SelectVLDDup(N, true, 2, Opcodes);
2762  }
2763
2764  case ARMISD::VLD3DUP_UPD: {
2765    unsigned Opcodes[] = { ARM::VLD3DUPd8Pseudo_UPD, ARM::VLD3DUPd16Pseudo_UPD,
2766                           ARM::VLD3DUPd32Pseudo_UPD };
2767    return SelectVLDDup(N, true, 3, Opcodes);
2768  }
2769
2770  case ARMISD::VLD4DUP_UPD: {
2771    unsigned Opcodes[] = { ARM::VLD4DUPd8Pseudo_UPD, ARM::VLD4DUPd16Pseudo_UPD,
2772                           ARM::VLD4DUPd32Pseudo_UPD };
2773    return SelectVLDDup(N, true, 4, Opcodes);
2774  }
2775
2776  case ARMISD::VLD1_UPD: {
2777    unsigned DOpcodes[] = { ARM::VLD1d8wb_fixed, ARM::VLD1d16wb_fixed,
2778                            ARM::VLD1d32wb_fixed, ARM::VLD1d64wb_fixed };
2779    unsigned QOpcodes[] = { ARM::VLD1q8PseudoWB_fixed,
2780                            ARM::VLD1q16PseudoWB_fixed,
2781                            ARM::VLD1q32PseudoWB_fixed,
2782                            ARM::VLD1q64PseudoWB_fixed };
2783    return SelectVLD(N, true, 1, DOpcodes, QOpcodes, 0);
2784  }
2785
2786  case ARMISD::VLD2_UPD: {
2787    unsigned DOpcodes[] = { ARM::VLD2d8Pseudo_UPD, ARM::VLD2d16Pseudo_UPD,
2788                            ARM::VLD2d32Pseudo_UPD, ARM::VLD1q64PseudoWB_fixed};
2789    unsigned QOpcodes[] = { ARM::VLD2q8Pseudo_UPD, ARM::VLD2q16Pseudo_UPD,
2790                            ARM::VLD2q32Pseudo_UPD };
2791    return SelectVLD(N, true, 2, DOpcodes, QOpcodes, 0);
2792  }
2793
2794  case ARMISD::VLD3_UPD: {
2795    unsigned DOpcodes[] = { ARM::VLD3d8Pseudo_UPD, ARM::VLD3d16Pseudo_UPD,
2796                            ARM::VLD3d32Pseudo_UPD, ARM::VLD1q64PseudoWB_fixed};
2797    unsigned QOpcodes0[] = { ARM::VLD3q8Pseudo_UPD,
2798                             ARM::VLD3q16Pseudo_UPD,
2799                             ARM::VLD3q32Pseudo_UPD };
2800    unsigned QOpcodes1[] = { ARM::VLD3q8oddPseudo_UPD,
2801                             ARM::VLD3q16oddPseudo_UPD,
2802                             ARM::VLD3q32oddPseudo_UPD };
2803    return SelectVLD(N, true, 3, DOpcodes, QOpcodes0, QOpcodes1);
2804  }
2805
2806  case ARMISD::VLD4_UPD: {
2807    unsigned DOpcodes[] = { ARM::VLD4d8Pseudo_UPD, ARM::VLD4d16Pseudo_UPD,
2808                            ARM::VLD4d32Pseudo_UPD, ARM::VLD1q64PseudoWB_fixed};
2809    unsigned QOpcodes0[] = { ARM::VLD4q8Pseudo_UPD,
2810                             ARM::VLD4q16Pseudo_UPD,
2811                             ARM::VLD4q32Pseudo_UPD };
2812    unsigned QOpcodes1[] = { ARM::VLD4q8oddPseudo_UPD,
2813                             ARM::VLD4q16oddPseudo_UPD,
2814                             ARM::VLD4q32oddPseudo_UPD };
2815    return SelectVLD(N, true, 4, DOpcodes, QOpcodes0, QOpcodes1);
2816  }
2817
2818  case ARMISD::VLD2LN_UPD: {
2819    unsigned DOpcodes[] = { ARM::VLD2LNd8Pseudo_UPD, ARM::VLD2LNd16Pseudo_UPD,
2820                            ARM::VLD2LNd32Pseudo_UPD };
2821    unsigned QOpcodes[] = { ARM::VLD2LNq16Pseudo_UPD,
2822                            ARM::VLD2LNq32Pseudo_UPD };
2823    return SelectVLDSTLane(N, true, true, 2, DOpcodes, QOpcodes);
2824  }
2825
2826  case ARMISD::VLD3LN_UPD: {
2827    unsigned DOpcodes[] = { ARM::VLD3LNd8Pseudo_UPD, ARM::VLD3LNd16Pseudo_UPD,
2828                            ARM::VLD3LNd32Pseudo_UPD };
2829    unsigned QOpcodes[] = { ARM::VLD3LNq16Pseudo_UPD,
2830                            ARM::VLD3LNq32Pseudo_UPD };
2831    return SelectVLDSTLane(N, true, true, 3, DOpcodes, QOpcodes);
2832  }
2833
2834  case ARMISD::VLD4LN_UPD: {
2835    unsigned DOpcodes[] = { ARM::VLD4LNd8Pseudo_UPD, ARM::VLD4LNd16Pseudo_UPD,
2836                            ARM::VLD4LNd32Pseudo_UPD };
2837    unsigned QOpcodes[] = { ARM::VLD4LNq16Pseudo_UPD,
2838                            ARM::VLD4LNq32Pseudo_UPD };
2839    return SelectVLDSTLane(N, true, true, 4, DOpcodes, QOpcodes);
2840  }
2841
2842  case ARMISD::VST1_UPD: {
2843    unsigned DOpcodes[] = { ARM::VST1d8_UPD, ARM::VST1d16_UPD,
2844                            ARM::VST1d32_UPD, ARM::VST1d64_UPD };
2845    unsigned QOpcodes[] = { ARM::VST1q8Pseudo_UPD, ARM::VST1q16Pseudo_UPD,
2846                            ARM::VST1q32Pseudo_UPD, ARM::VST1q64Pseudo_UPD };
2847    return SelectVST(N, true, 1, DOpcodes, QOpcodes, 0);
2848  }
2849
2850  case ARMISD::VST2_UPD: {
2851    unsigned DOpcodes[] = { ARM::VST2d8Pseudo_UPD, ARM::VST2d16Pseudo_UPD,
2852                            ARM::VST2d32Pseudo_UPD, ARM::VST1q64Pseudo_UPD };
2853    unsigned QOpcodes[] = { ARM::VST2q8Pseudo_UPD, ARM::VST2q16Pseudo_UPD,
2854                            ARM::VST2q32Pseudo_UPD };
2855    return SelectVST(N, true, 2, DOpcodes, QOpcodes, 0);
2856  }
2857
2858  case ARMISD::VST3_UPD: {
2859    unsigned DOpcodes[] = { ARM::VST3d8Pseudo_UPD, ARM::VST3d16Pseudo_UPD,
2860                            ARM::VST3d32Pseudo_UPD, ARM::VST1d64TPseudo_UPD };
2861    unsigned QOpcodes0[] = { ARM::VST3q8Pseudo_UPD,
2862                             ARM::VST3q16Pseudo_UPD,
2863                             ARM::VST3q32Pseudo_UPD };
2864    unsigned QOpcodes1[] = { ARM::VST3q8oddPseudo_UPD,
2865                             ARM::VST3q16oddPseudo_UPD,
2866                             ARM::VST3q32oddPseudo_UPD };
2867    return SelectVST(N, true, 3, DOpcodes, QOpcodes0, QOpcodes1);
2868  }
2869
2870  case ARMISD::VST4_UPD: {
2871    unsigned DOpcodes[] = { ARM::VST4d8Pseudo_UPD, ARM::VST4d16Pseudo_UPD,
2872                            ARM::VST4d32Pseudo_UPD, ARM::VST1d64QPseudo_UPD };
2873    unsigned QOpcodes0[] = { ARM::VST4q8Pseudo_UPD,
2874                             ARM::VST4q16Pseudo_UPD,
2875                             ARM::VST4q32Pseudo_UPD };
2876    unsigned QOpcodes1[] = { ARM::VST4q8oddPseudo_UPD,
2877                             ARM::VST4q16oddPseudo_UPD,
2878                             ARM::VST4q32oddPseudo_UPD };
2879    return SelectVST(N, true, 4, DOpcodes, QOpcodes0, QOpcodes1);
2880  }
2881
2882  case ARMISD::VST2LN_UPD: {
2883    unsigned DOpcodes[] = { ARM::VST2LNd8Pseudo_UPD, ARM::VST2LNd16Pseudo_UPD,
2884                            ARM::VST2LNd32Pseudo_UPD };
2885    unsigned QOpcodes[] = { ARM::VST2LNq16Pseudo_UPD,
2886                            ARM::VST2LNq32Pseudo_UPD };
2887    return SelectVLDSTLane(N, false, true, 2, DOpcodes, QOpcodes);
2888  }
2889
2890  case ARMISD::VST3LN_UPD: {
2891    unsigned DOpcodes[] = { ARM::VST3LNd8Pseudo_UPD, ARM::VST3LNd16Pseudo_UPD,
2892                            ARM::VST3LNd32Pseudo_UPD };
2893    unsigned QOpcodes[] = { ARM::VST3LNq16Pseudo_UPD,
2894                            ARM::VST3LNq32Pseudo_UPD };
2895    return SelectVLDSTLane(N, false, true, 3, DOpcodes, QOpcodes);
2896  }
2897
2898  case ARMISD::VST4LN_UPD: {
2899    unsigned DOpcodes[] = { ARM::VST4LNd8Pseudo_UPD, ARM::VST4LNd16Pseudo_UPD,
2900                            ARM::VST4LNd32Pseudo_UPD };
2901    unsigned QOpcodes[] = { ARM::VST4LNq16Pseudo_UPD,
2902                            ARM::VST4LNq32Pseudo_UPD };
2903    return SelectVLDSTLane(N, false, true, 4, DOpcodes, QOpcodes);
2904  }
2905
2906  case ISD::INTRINSIC_VOID:
2907  case ISD::INTRINSIC_W_CHAIN: {
2908    unsigned IntNo = cast<ConstantSDNode>(N->getOperand(1))->getZExtValue();
2909    switch (IntNo) {
2910    default:
2911      break;
2912
2913    case Intrinsic::arm_ldrexd: {
2914      SDValue MemAddr = N->getOperand(2);
2915      DebugLoc dl = N->getDebugLoc();
2916      SDValue Chain = N->getOperand(0);
2917
2918      unsigned NewOpc = ARM::LDREXD;
2919      if (Subtarget->isThumb() && Subtarget->hasThumb2())
2920        NewOpc = ARM::t2LDREXD;
2921
2922      // arm_ldrexd returns a i64 value in {i32, i32}
2923      std::vector<EVT> ResTys;
2924      ResTys.push_back(MVT::i32);
2925      ResTys.push_back(MVT::i32);
2926      ResTys.push_back(MVT::Other);
2927
2928      // place arguments in the right order
2929      SmallVector<SDValue, 7> Ops;
2930      Ops.push_back(MemAddr);
2931      Ops.push_back(getAL(CurDAG));
2932      Ops.push_back(CurDAG->getRegister(0, MVT::i32));
2933      Ops.push_back(Chain);
2934      SDNode *Ld = CurDAG->getMachineNode(NewOpc, dl, ResTys, Ops.data(),
2935                                          Ops.size());
2936      // Transfer memoperands.
2937      MachineSDNode::mmo_iterator MemOp = MF->allocateMemRefsArray(1);
2938      MemOp[0] = cast<MemIntrinsicSDNode>(N)->getMemOperand();
2939      cast<MachineSDNode>(Ld)->setMemRefs(MemOp, MemOp + 1);
2940
2941      // Until there's support for specifing explicit register constraints
2942      // like the use of even/odd register pair, hardcode ldrexd to always
2943      // use the pair [R0, R1] to hold the load result.
2944      Chain = CurDAG->getCopyToReg(CurDAG->getEntryNode(), dl, ARM::R0,
2945                                   SDValue(Ld, 0), SDValue(0,0));
2946      Chain = CurDAG->getCopyToReg(Chain, dl, ARM::R1,
2947                                   SDValue(Ld, 1), Chain.getValue(1));
2948
2949      // Remap uses.
2950      SDValue Glue = Chain.getValue(1);
2951      if (!SDValue(N, 0).use_empty()) {
2952        SDValue Result = CurDAG->getCopyFromReg(CurDAG->getEntryNode(), dl,
2953                                                ARM::R0, MVT::i32, Glue);
2954        Glue = Result.getValue(2);
2955        ReplaceUses(SDValue(N, 0), Result);
2956      }
2957      if (!SDValue(N, 1).use_empty()) {
2958        SDValue Result = CurDAG->getCopyFromReg(CurDAG->getEntryNode(), dl,
2959                                                ARM::R1, MVT::i32, Glue);
2960        Glue = Result.getValue(2);
2961        ReplaceUses(SDValue(N, 1), Result);
2962      }
2963
2964      ReplaceUses(SDValue(N, 2), SDValue(Ld, 2));
2965      return NULL;
2966    }
2967
2968    case Intrinsic::arm_strexd: {
2969      DebugLoc dl = N->getDebugLoc();
2970      SDValue Chain = N->getOperand(0);
2971      SDValue Val0 = N->getOperand(2);
2972      SDValue Val1 = N->getOperand(3);
2973      SDValue MemAddr = N->getOperand(4);
2974
2975      // Until there's support for specifing explicit register constraints
2976      // like the use of even/odd register pair, hardcode strexd to always
2977      // use the pair [R2, R3] to hold the i64 (i32, i32) value to be stored.
2978      Chain = CurDAG->getCopyToReg(CurDAG->getEntryNode(), dl, ARM::R2, Val0,
2979                                   SDValue(0, 0));
2980      Chain = CurDAG->getCopyToReg(Chain, dl, ARM::R3, Val1, Chain.getValue(1));
2981
2982      SDValue Glue = Chain.getValue(1);
2983      Val0 = CurDAG->getCopyFromReg(CurDAG->getEntryNode(), dl,
2984                                    ARM::R2, MVT::i32, Glue);
2985      Glue = Val0.getValue(1);
2986      Val1 = CurDAG->getCopyFromReg(CurDAG->getEntryNode(), dl,
2987                                    ARM::R3, MVT::i32, Glue);
2988
2989      // Store exclusive double return a i32 value which is the return status
2990      // of the issued store.
2991      std::vector<EVT> ResTys;
2992      ResTys.push_back(MVT::i32);
2993      ResTys.push_back(MVT::Other);
2994
2995      // place arguments in the right order
2996      SmallVector<SDValue, 7> Ops;
2997      Ops.push_back(Val0);
2998      Ops.push_back(Val1);
2999      Ops.push_back(MemAddr);
3000      Ops.push_back(getAL(CurDAG));
3001      Ops.push_back(CurDAG->getRegister(0, MVT::i32));
3002      Ops.push_back(Chain);
3003
3004      unsigned NewOpc = ARM::STREXD;
3005      if (Subtarget->isThumb() && Subtarget->hasThumb2())
3006        NewOpc = ARM::t2STREXD;
3007
3008      SDNode *St = CurDAG->getMachineNode(NewOpc, dl, ResTys, Ops.data(),
3009                                          Ops.size());
3010      // Transfer memoperands.
3011      MachineSDNode::mmo_iterator MemOp = MF->allocateMemRefsArray(1);
3012      MemOp[0] = cast<MemIntrinsicSDNode>(N)->getMemOperand();
3013      cast<MachineSDNode>(St)->setMemRefs(MemOp, MemOp + 1);
3014
3015      return St;
3016    }
3017
3018    case Intrinsic::arm_neon_vld1: {
3019      unsigned DOpcodes[] = { ARM::VLD1d8, ARM::VLD1d16,
3020                              ARM::VLD1d32, ARM::VLD1d64 };
3021      unsigned QOpcodes[] = { ARM::VLD1q8Pseudo, ARM::VLD1q16Pseudo,
3022                              ARM::VLD1q32Pseudo, ARM::VLD1q64Pseudo };
3023      return SelectVLD(N, false, 1, DOpcodes, QOpcodes, 0);
3024    }
3025
3026    case Intrinsic::arm_neon_vld2: {
3027      unsigned DOpcodes[] = { ARM::VLD2d8Pseudo, ARM::VLD2d16Pseudo,
3028                              ARM::VLD2d32Pseudo, ARM::VLD1q64Pseudo };
3029      unsigned QOpcodes[] = { ARM::VLD2q8Pseudo, ARM::VLD2q16Pseudo,
3030                              ARM::VLD2q32Pseudo };
3031      return SelectVLD(N, false, 2, DOpcodes, QOpcodes, 0);
3032    }
3033
3034    case Intrinsic::arm_neon_vld3: {
3035      unsigned DOpcodes[] = { ARM::VLD3d8Pseudo, ARM::VLD3d16Pseudo,
3036                              ARM::VLD3d32Pseudo, ARM::VLD1d64TPseudo };
3037      unsigned QOpcodes0[] = { ARM::VLD3q8Pseudo_UPD,
3038                               ARM::VLD3q16Pseudo_UPD,
3039                               ARM::VLD3q32Pseudo_UPD };
3040      unsigned QOpcodes1[] = { ARM::VLD3q8oddPseudo,
3041                               ARM::VLD3q16oddPseudo,
3042                               ARM::VLD3q32oddPseudo };
3043      return SelectVLD(N, false, 3, DOpcodes, QOpcodes0, QOpcodes1);
3044    }
3045
3046    case Intrinsic::arm_neon_vld4: {
3047      unsigned DOpcodes[] = { ARM::VLD4d8Pseudo, ARM::VLD4d16Pseudo,
3048                              ARM::VLD4d32Pseudo, ARM::VLD1d64QPseudo };
3049      unsigned QOpcodes0[] = { ARM::VLD4q8Pseudo_UPD,
3050                               ARM::VLD4q16Pseudo_UPD,
3051                               ARM::VLD4q32Pseudo_UPD };
3052      unsigned QOpcodes1[] = { ARM::VLD4q8oddPseudo,
3053                               ARM::VLD4q16oddPseudo,
3054                               ARM::VLD4q32oddPseudo };
3055      return SelectVLD(N, false, 4, DOpcodes, QOpcodes0, QOpcodes1);
3056    }
3057
3058    case Intrinsic::arm_neon_vld2lane: {
3059      unsigned DOpcodes[] = { ARM::VLD2LNd8Pseudo, ARM::VLD2LNd16Pseudo,
3060                              ARM::VLD2LNd32Pseudo };
3061      unsigned QOpcodes[] = { ARM::VLD2LNq16Pseudo, ARM::VLD2LNq32Pseudo };
3062      return SelectVLDSTLane(N, true, false, 2, DOpcodes, QOpcodes);
3063    }
3064
3065    case Intrinsic::arm_neon_vld3lane: {
3066      unsigned DOpcodes[] = { ARM::VLD3LNd8Pseudo, ARM::VLD3LNd16Pseudo,
3067                              ARM::VLD3LNd32Pseudo };
3068      unsigned QOpcodes[] = { ARM::VLD3LNq16Pseudo, ARM::VLD3LNq32Pseudo };
3069      return SelectVLDSTLane(N, true, false, 3, DOpcodes, QOpcodes);
3070    }
3071
3072    case Intrinsic::arm_neon_vld4lane: {
3073      unsigned DOpcodes[] = { ARM::VLD4LNd8Pseudo, ARM::VLD4LNd16Pseudo,
3074                              ARM::VLD4LNd32Pseudo };
3075      unsigned QOpcodes[] = { ARM::VLD4LNq16Pseudo, ARM::VLD4LNq32Pseudo };
3076      return SelectVLDSTLane(N, true, false, 4, DOpcodes, QOpcodes);
3077    }
3078
3079    case Intrinsic::arm_neon_vst1: {
3080      unsigned DOpcodes[] = { ARM::VST1d8, ARM::VST1d16,
3081                              ARM::VST1d32, ARM::VST1d64 };
3082      unsigned QOpcodes[] = { ARM::VST1q8Pseudo, ARM::VST1q16Pseudo,
3083                              ARM::VST1q32Pseudo, ARM::VST1q64Pseudo };
3084      return SelectVST(N, false, 1, DOpcodes, QOpcodes, 0);
3085    }
3086
3087    case Intrinsic::arm_neon_vst2: {
3088      unsigned DOpcodes[] = { ARM::VST2d8Pseudo, ARM::VST2d16Pseudo,
3089                              ARM::VST2d32Pseudo, ARM::VST1q64Pseudo };
3090      unsigned QOpcodes[] = { ARM::VST2q8Pseudo, ARM::VST2q16Pseudo,
3091                              ARM::VST2q32Pseudo };
3092      return SelectVST(N, false, 2, DOpcodes, QOpcodes, 0);
3093    }
3094
3095    case Intrinsic::arm_neon_vst3: {
3096      unsigned DOpcodes[] = { ARM::VST3d8Pseudo, ARM::VST3d16Pseudo,
3097                              ARM::VST3d32Pseudo, ARM::VST1d64TPseudo };
3098      unsigned QOpcodes0[] = { ARM::VST3q8Pseudo_UPD,
3099                               ARM::VST3q16Pseudo_UPD,
3100                               ARM::VST3q32Pseudo_UPD };
3101      unsigned QOpcodes1[] = { ARM::VST3q8oddPseudo,
3102                               ARM::VST3q16oddPseudo,
3103                               ARM::VST3q32oddPseudo };
3104      return SelectVST(N, false, 3, DOpcodes, QOpcodes0, QOpcodes1);
3105    }
3106
3107    case Intrinsic::arm_neon_vst4: {
3108      unsigned DOpcodes[] = { ARM::VST4d8Pseudo, ARM::VST4d16Pseudo,
3109                              ARM::VST4d32Pseudo, ARM::VST1d64QPseudo };
3110      unsigned QOpcodes0[] = { ARM::VST4q8Pseudo_UPD,
3111                               ARM::VST4q16Pseudo_UPD,
3112                               ARM::VST4q32Pseudo_UPD };
3113      unsigned QOpcodes1[] = { ARM::VST4q8oddPseudo,
3114                               ARM::VST4q16oddPseudo,
3115                               ARM::VST4q32oddPseudo };
3116      return SelectVST(N, false, 4, DOpcodes, QOpcodes0, QOpcodes1);
3117    }
3118
3119    case Intrinsic::arm_neon_vst2lane: {
3120      unsigned DOpcodes[] = { ARM::VST2LNd8Pseudo, ARM::VST2LNd16Pseudo,
3121                              ARM::VST2LNd32Pseudo };
3122      unsigned QOpcodes[] = { ARM::VST2LNq16Pseudo, ARM::VST2LNq32Pseudo };
3123      return SelectVLDSTLane(N, false, false, 2, DOpcodes, QOpcodes);
3124    }
3125
3126    case Intrinsic::arm_neon_vst3lane: {
3127      unsigned DOpcodes[] = { ARM::VST3LNd8Pseudo, ARM::VST3LNd16Pseudo,
3128                              ARM::VST3LNd32Pseudo };
3129      unsigned QOpcodes[] = { ARM::VST3LNq16Pseudo, ARM::VST3LNq32Pseudo };
3130      return SelectVLDSTLane(N, false, false, 3, DOpcodes, QOpcodes);
3131    }
3132
3133    case Intrinsic::arm_neon_vst4lane: {
3134      unsigned DOpcodes[] = { ARM::VST4LNd8Pseudo, ARM::VST4LNd16Pseudo,
3135                              ARM::VST4LNd32Pseudo };
3136      unsigned QOpcodes[] = { ARM::VST4LNq16Pseudo, ARM::VST4LNq32Pseudo };
3137      return SelectVLDSTLane(N, false, false, 4, DOpcodes, QOpcodes);
3138    }
3139    }
3140    break;
3141  }
3142
3143  case ISD::INTRINSIC_WO_CHAIN: {
3144    unsigned IntNo = cast<ConstantSDNode>(N->getOperand(0))->getZExtValue();
3145    switch (IntNo) {
3146    default:
3147      break;
3148
3149    case Intrinsic::arm_neon_vtbl2:
3150      return SelectVTBL(N, false, 2, ARM::VTBL2Pseudo);
3151    case Intrinsic::arm_neon_vtbl3:
3152      return SelectVTBL(N, false, 3, ARM::VTBL3Pseudo);
3153    case Intrinsic::arm_neon_vtbl4:
3154      return SelectVTBL(N, false, 4, ARM::VTBL4Pseudo);
3155
3156    case Intrinsic::arm_neon_vtbx2:
3157      return SelectVTBL(N, true, 2, ARM::VTBX2Pseudo);
3158    case Intrinsic::arm_neon_vtbx3:
3159      return SelectVTBL(N, true, 3, ARM::VTBX3Pseudo);
3160    case Intrinsic::arm_neon_vtbx4:
3161      return SelectVTBL(N, true, 4, ARM::VTBX4Pseudo);
3162    }
3163    break;
3164  }
3165
3166  case ARMISD::VTBL1: {
3167    DebugLoc dl = N->getDebugLoc();
3168    EVT VT = N->getValueType(0);
3169    SmallVector<SDValue, 6> Ops;
3170
3171    Ops.push_back(N->getOperand(0));
3172    Ops.push_back(N->getOperand(1));
3173    Ops.push_back(getAL(CurDAG));                    // Predicate
3174    Ops.push_back(CurDAG->getRegister(0, MVT::i32)); // Predicate Register
3175    return CurDAG->getMachineNode(ARM::VTBL1, dl, VT, Ops.data(), Ops.size());
3176  }
3177  case ARMISD::VTBL2: {
3178    DebugLoc dl = N->getDebugLoc();
3179    EVT VT = N->getValueType(0);
3180
3181    // Form a REG_SEQUENCE to force register allocation.
3182    SDValue V0 = N->getOperand(0);
3183    SDValue V1 = N->getOperand(1);
3184    SDValue RegSeq = SDValue(PairDRegs(MVT::v16i8, V0, V1), 0);
3185
3186    SmallVector<SDValue, 6> Ops;
3187    Ops.push_back(RegSeq);
3188    Ops.push_back(N->getOperand(2));
3189    Ops.push_back(getAL(CurDAG));                    // Predicate
3190    Ops.push_back(CurDAG->getRegister(0, MVT::i32)); // Predicate Register
3191    return CurDAG->getMachineNode(ARM::VTBL2Pseudo, dl, VT,
3192                                  Ops.data(), Ops.size());
3193  }
3194
3195  case ISD::CONCAT_VECTORS:
3196    return SelectConcatVector(N);
3197
3198  case ARMISD::ATOMOR64_DAG:
3199    return SelectAtomic64(N, ARM::ATOMOR6432);
3200  case ARMISD::ATOMXOR64_DAG:
3201    return SelectAtomic64(N, ARM::ATOMXOR6432);
3202  case ARMISD::ATOMADD64_DAG:
3203    return SelectAtomic64(N, ARM::ATOMADD6432);
3204  case ARMISD::ATOMSUB64_DAG:
3205    return SelectAtomic64(N, ARM::ATOMSUB6432);
3206  case ARMISD::ATOMNAND64_DAG:
3207    return SelectAtomic64(N, ARM::ATOMNAND6432);
3208  case ARMISD::ATOMAND64_DAG:
3209    return SelectAtomic64(N, ARM::ATOMAND6432);
3210  case ARMISD::ATOMSWAP64_DAG:
3211    return SelectAtomic64(N, ARM::ATOMSWAP6432);
3212  case ARMISD::ATOMCMPXCHG64_DAG:
3213    return SelectAtomic64(N, ARM::ATOMCMPXCHG6432);
3214  }
3215
3216  return SelectCode(N);
3217}
3218
3219bool ARMDAGToDAGISel::
3220SelectInlineAsmMemoryOperand(const SDValue &Op, char ConstraintCode,
3221                             std::vector<SDValue> &OutOps) {
3222  assert(ConstraintCode == 'm' && "unexpected asm memory constraint");
3223  // Require the address to be in a register.  That is safe for all ARM
3224  // variants and it is hard to do anything much smarter without knowing
3225  // how the operand is used.
3226  OutOps.push_back(Op);
3227  return false;
3228}
3229
3230/// createARMISelDag - This pass converts a legalized DAG into a
3231/// ARM-specific DAG, ready for instruction scheduling.
3232///
3233FunctionPass *llvm::createARMISelDag(ARMBaseTargetMachine &TM,
3234                                     CodeGenOpt::Level OptLevel) {
3235  return new ARMDAGToDAGISel(TM, OptLevel);
3236}
3237