ARMISelLowering.cpp revision 36b56886974eae4f9c5ebc96befd3e7bfe5de338 
1//===-- ARMISelLowering.cpp - ARM DAG Lowering Implementation -------------===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file defines the interfaces that ARM uses to lower LLVM code into a
11// selection DAG.
12//
13//===----------------------------------------------------------------------===//
14
15#define DEBUG_TYPE "arm-isel"
16#include "ARMISelLowering.h"
17#include "ARMCallingConv.h"
18#include "ARMConstantPoolValue.h"
19#include "ARMMachineFunctionInfo.h"
20#include "ARMPerfectShuffle.h"
21#include "ARMSubtarget.h"
22#include "ARMTargetMachine.h"
23#include "ARMTargetObjectFile.h"
24#include "MCTargetDesc/ARMAddressingModes.h"
25#include "llvm/ADT/Statistic.h"
26#include "llvm/ADT/StringExtras.h"
27#include "llvm/CodeGen/CallingConvLower.h"
28#include "llvm/CodeGen/IntrinsicLowering.h"
29#include "llvm/CodeGen/MachineBasicBlock.h"
30#include "llvm/CodeGen/MachineFrameInfo.h"
31#include "llvm/CodeGen/MachineFunction.h"
32#include "llvm/CodeGen/MachineInstrBuilder.h"
33#include "llvm/CodeGen/MachineModuleInfo.h"
34#include "llvm/CodeGen/MachineRegisterInfo.h"
35#include "llvm/CodeGen/SelectionDAG.h"
36#include "llvm/IR/CallingConv.h"
37#include "llvm/IR/Constants.h"
38#include "llvm/IR/Function.h"
39#include "llvm/IR/GlobalValue.h"
40#include "llvm/IR/Instruction.h"
41#include "llvm/IR/Instructions.h"
42#include "llvm/IR/Intrinsics.h"
43#include "llvm/IR/Type.h"
44#include "llvm/MC/MCSectionMachO.h"
45#include "llvm/Support/CommandLine.h"
46#include "llvm/Support/ErrorHandling.h"
47#include "llvm/Support/MathExtras.h"
48#include "llvm/Target/TargetOptions.h"
49#include <utility>
50using namespace llvm;
51
52STATISTIC(NumTailCalls, "Number of tail calls");
53STATISTIC(NumMovwMovt, "Number of GAs materialized with movw + movt");
54STATISTIC(NumLoopByVals, "Number of loops generated for byval arguments");
55
56cl::opt<bool>
57EnableARMLongCalls("arm-long-calls", cl::Hidden,
58  cl::desc("Generate calls via indirect call instructions"),
59  cl::init(false));
60
61static cl::opt<bool>
62ARMInterworking("arm-interworking", cl::Hidden,
63  cl::desc("Enable / disable ARM interworking (for debugging only)"),
64  cl::init(true));
65
66namespace {
67  class ARMCCState : public CCState {
68  public:
69    ARMCCState(CallingConv::ID CC, bool isVarArg, MachineFunction &MF,
70               const TargetMachine &TM, SmallVectorImpl<CCValAssign> &locs,
71               LLVMContext &C, ParmContext PC)
72        : CCState(CC, isVarArg, MF, TM, locs, C) {
73      assert(((PC == Call) || (PC == Prologue)) &&
74             "ARMCCState users must specify whether their context is call"
75             "or prologue generation.");
76      CallOrPrologue = PC;
77    }
78  };
79}
80
81// The APCS parameter registers.
82static const uint16_t GPRArgRegs[] = {
83  ARM::R0, ARM::R1, ARM::R2, ARM::R3
84};
85
86void ARMTargetLowering::addTypeForNEON(MVT VT, MVT PromotedLdStVT,
87                                       MVT PromotedBitwiseVT) {
88  if (VT != PromotedLdStVT) {
89    setOperationAction(ISD::LOAD, VT, Promote);
90    AddPromotedToType (ISD::LOAD, VT, PromotedLdStVT);
91
92    setOperationAction(ISD::STORE, VT, Promote);
93    AddPromotedToType (ISD::STORE, VT, PromotedLdStVT);
94  }
95
96  MVT ElemTy = VT.getVectorElementType();
97  if (ElemTy != MVT::i64 && ElemTy != MVT::f64)
98    setOperationAction(ISD::SETCC, VT, Custom);
99  setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Custom);
100  setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Custom);
101  if (ElemTy == MVT::i32) {
102    setOperationAction(ISD::SINT_TO_FP, VT, Custom);
103    setOperationAction(ISD::UINT_TO_FP, VT, Custom);
104    setOperationAction(ISD::FP_TO_SINT, VT, Custom);
105    setOperationAction(ISD::FP_TO_UINT, VT, Custom);
106  } else {
107    setOperationAction(ISD::SINT_TO_FP, VT, Expand);
108    setOperationAction(ISD::UINT_TO_FP, VT, Expand);
109    setOperationAction(ISD::FP_TO_SINT, VT, Expand);
110    setOperationAction(ISD::FP_TO_UINT, VT, Expand);
111  }
112  setOperationAction(ISD::BUILD_VECTOR,      VT, Custom);
113  setOperationAction(ISD::VECTOR_SHUFFLE,    VT, Custom);
114  setOperationAction(ISD::CONCAT_VECTORS,    VT, Legal);
115  setOperationAction(ISD::EXTRACT_SUBVECTOR, VT, Legal);
116  setOperationAction(ISD::SELECT,            VT, Expand);
117  setOperationAction(ISD::SELECT_CC,         VT, Expand);
118  setOperationAction(ISD::VSELECT,           VT, Expand);
119  setOperationAction(ISD::SIGN_EXTEND_INREG, VT, Expand);
120  if (VT.isInteger()) {
121    setOperationAction(ISD::SHL, VT, Custom);
122    setOperationAction(ISD::SRA, VT, Custom);
123    setOperationAction(ISD::SRL, VT, Custom);
124  }
125
126  // Promote all bit-wise operations.
127  if (VT.isInteger() && VT != PromotedBitwiseVT) {
128    setOperationAction(ISD::AND, VT, Promote);
129    AddPromotedToType (ISD::AND, VT, PromotedBitwiseVT);
130    setOperationAction(ISD::OR,  VT, Promote);
131    AddPromotedToType (ISD::OR,  VT, PromotedBitwiseVT);
132    setOperationAction(ISD::XOR, VT, Promote);
133    AddPromotedToType (ISD::XOR, VT, PromotedBitwiseVT);
134  }
135
136  // Neon does not support vector divide/remainder operations.
137  setOperationAction(ISD::SDIV, VT, Expand);
138  setOperationAction(ISD::UDIV, VT, Expand);
139  setOperationAction(ISD::FDIV, VT, Expand);
140  setOperationAction(ISD::SREM, VT, Expand);
141  setOperationAction(ISD::UREM, VT, Expand);
142  setOperationAction(ISD::FREM, VT, Expand);
143}
144
145void ARMTargetLowering::addDRTypeForNEON(MVT VT) {
146  addRegisterClass(VT, &ARM::DPRRegClass);
147  addTypeForNEON(VT, MVT::f64, MVT::v2i32);
148}
149
150void ARMTargetLowering::addQRTypeForNEON(MVT VT) {
151  addRegisterClass(VT, &ARM::DPairRegClass);
152  addTypeForNEON(VT, MVT::v2f64, MVT::v4i32);
153}
154
155static TargetLoweringObjectFile *createTLOF(TargetMachine &TM) {
156  if (TM.getSubtarget<ARMSubtarget>().isTargetMachO())
157    return new TargetLoweringObjectFileMachO();
158
159  return new ARMElfTargetObjectFile();
160}
161
162ARMTargetLowering::ARMTargetLowering(TargetMachine &TM)
163    : TargetLowering(TM, createTLOF(TM)) {
164  Subtarget = &TM.getSubtarget<ARMSubtarget>();
165  RegInfo = TM.getRegisterInfo();
166  Itins = TM.getInstrItineraryData();
167
168  setBooleanVectorContents(ZeroOrNegativeOneBooleanContent);
169
170  if (Subtarget->isTargetMachO()) {
171    // Uses VFP for Thumb libfuncs if available.
172    if (Subtarget->isThumb() && Subtarget->hasVFP2() &&
173        Subtarget->hasARMOps()) {
174      // Single-precision floating-point arithmetic.
175      setLibcallName(RTLIB::ADD_F32, "__addsf3vfp");
176      setLibcallName(RTLIB::SUB_F32, "__subsf3vfp");
177      setLibcallName(RTLIB::MUL_F32, "__mulsf3vfp");
178      setLibcallName(RTLIB::DIV_F32, "__divsf3vfp");
179
180      // Double-precision floating-point arithmetic.
181      setLibcallName(RTLIB::ADD_F64, "__adddf3vfp");
182      setLibcallName(RTLIB::SUB_F64, "__subdf3vfp");
183      setLibcallName(RTLIB::MUL_F64, "__muldf3vfp");
184      setLibcallName(RTLIB::DIV_F64, "__divdf3vfp");
185
186      // Single-precision comparisons.
187      setLibcallName(RTLIB::OEQ_F32, "__eqsf2vfp");
188      setLibcallName(RTLIB::UNE_F32, "__nesf2vfp");
189      setLibcallName(RTLIB::OLT_F32, "__ltsf2vfp");
190      setLibcallName(RTLIB::OLE_F32, "__lesf2vfp");
191      setLibcallName(RTLIB::OGE_F32, "__gesf2vfp");
192      setLibcallName(RTLIB::OGT_F32, "__gtsf2vfp");
193      setLibcallName(RTLIB::UO_F32,  "__unordsf2vfp");
194      setLibcallName(RTLIB::O_F32,   "__unordsf2vfp");
195
196      setCmpLibcallCC(RTLIB::OEQ_F32, ISD::SETNE);
197      setCmpLibcallCC(RTLIB::UNE_F32, ISD::SETNE);
198      setCmpLibcallCC(RTLIB::OLT_F32, ISD::SETNE);
199      setCmpLibcallCC(RTLIB::OLE_F32, ISD::SETNE);
200      setCmpLibcallCC(RTLIB::OGE_F32, ISD::SETNE);
201      setCmpLibcallCC(RTLIB::OGT_F32, ISD::SETNE);
202      setCmpLibcallCC(RTLIB::UO_F32,  ISD::SETNE);
203      setCmpLibcallCC(RTLIB::O_F32,   ISD::SETEQ);
204
205      // Double-precision comparisons.
206      setLibcallName(RTLIB::OEQ_F64, "__eqdf2vfp");
207      setLibcallName(RTLIB::UNE_F64, "__nedf2vfp");
208      setLibcallName(RTLIB::OLT_F64, "__ltdf2vfp");
209      setLibcallName(RTLIB::OLE_F64, "__ledf2vfp");
210      setLibcallName(RTLIB::OGE_F64, "__gedf2vfp");
211      setLibcallName(RTLIB::OGT_F64, "__gtdf2vfp");
212      setLibcallName(RTLIB::UO_F64,  "__unorddf2vfp");
213      setLibcallName(RTLIB::O_F64,   "__unorddf2vfp");
214
215      setCmpLibcallCC(RTLIB::OEQ_F64, ISD::SETNE);
216      setCmpLibcallCC(RTLIB::UNE_F64, ISD::SETNE);
217      setCmpLibcallCC(RTLIB::OLT_F64, ISD::SETNE);
218      setCmpLibcallCC(RTLIB::OLE_F64, ISD::SETNE);
219      setCmpLibcallCC(RTLIB::OGE_F64, ISD::SETNE);
220      setCmpLibcallCC(RTLIB::OGT_F64, ISD::SETNE);
221      setCmpLibcallCC(RTLIB::UO_F64,  ISD::SETNE);
222      setCmpLibcallCC(RTLIB::O_F64,   ISD::SETEQ);
223
224      // Floating-point to integer conversions.
225      // i64 conversions are done via library routines even when generating VFP
226      // instructions, so use the same ones.
227      setLibcallName(RTLIB::FPTOSINT_F64_I32, "__fixdfsivfp");
228      setLibcallName(RTLIB::FPTOUINT_F64_I32, "__fixunsdfsivfp");
229      setLibcallName(RTLIB::FPTOSINT_F32_I32, "__fixsfsivfp");
230      setLibcallName(RTLIB::FPTOUINT_F32_I32, "__fixunssfsivfp");
231
232      // Conversions between floating types.
233      setLibcallName(RTLIB::FPROUND_F64_F32, "__truncdfsf2vfp");
234      setLibcallName(RTLIB::FPEXT_F32_F64,   "__extendsfdf2vfp");
235
236      // Integer to floating-point conversions.
237      // i64 conversions are done via library routines even when generating VFP
238      // instructions, so use the same ones.
239      // FIXME: There appears to be some naming inconsistency in ARM libgcc:
240      // e.g., __floatunsidf vs. __floatunssidfvfp.
241      setLibcallName(RTLIB::SINTTOFP_I32_F64, "__floatsidfvfp");
242      setLibcallName(RTLIB::UINTTOFP_I32_F64, "__floatunssidfvfp");
243      setLibcallName(RTLIB::SINTTOFP_I32_F32, "__floatsisfvfp");
244      setLibcallName(RTLIB::UINTTOFP_I32_F32, "__floatunssisfvfp");
245    }
246  }
247
248  // These libcalls are not available in 32-bit.
249  setLibcallName(RTLIB::SHL_I128, 0);
250  setLibcallName(RTLIB::SRL_I128, 0);
251  setLibcallName(RTLIB::SRA_I128, 0);
252
253  if (Subtarget->isAAPCS_ABI() && !Subtarget->isTargetMachO() &&
254      !Subtarget->isTargetWindows()) {
255    // Double-precision floating-point arithmetic helper functions
256    // RTABI chapter 4.1.2, Table 2
257    setLibcallName(RTLIB::ADD_F64, "__aeabi_dadd");
258    setLibcallName(RTLIB::DIV_F64, "__aeabi_ddiv");
259    setLibcallName(RTLIB::MUL_F64, "__aeabi_dmul");
260    setLibcallName(RTLIB::SUB_F64, "__aeabi_dsub");
261    setLibcallCallingConv(RTLIB::ADD_F64, CallingConv::ARM_AAPCS);
262    setLibcallCallingConv(RTLIB::DIV_F64, CallingConv::ARM_AAPCS);
263    setLibcallCallingConv(RTLIB::MUL_F64, CallingConv::ARM_AAPCS);
264    setLibcallCallingConv(RTLIB::SUB_F64, CallingConv::ARM_AAPCS);
265
266    // Double-precision floating-point comparison helper functions
267    // RTABI chapter 4.1.2, Table 3
268    setLibcallName(RTLIB::OEQ_F64, "__aeabi_dcmpeq");
269    setCmpLibcallCC(RTLIB::OEQ_F64, ISD::SETNE);
270    setLibcallName(RTLIB::UNE_F64, "__aeabi_dcmpeq");
271    setCmpLibcallCC(RTLIB::UNE_F64, ISD::SETEQ);
272    setLibcallName(RTLIB::OLT_F64, "__aeabi_dcmplt");
273    setCmpLibcallCC(RTLIB::OLT_F64, ISD::SETNE);
274    setLibcallName(RTLIB::OLE_F64, "__aeabi_dcmple");
275    setCmpLibcallCC(RTLIB::OLE_F64, ISD::SETNE);
276    setLibcallName(RTLIB::OGE_F64, "__aeabi_dcmpge");
277    setCmpLibcallCC(RTLIB::OGE_F64, ISD::SETNE);
278    setLibcallName(RTLIB::OGT_F64, "__aeabi_dcmpgt");
279    setCmpLibcallCC(RTLIB::OGT_F64, ISD::SETNE);
280    setLibcallName(RTLIB::UO_F64,  "__aeabi_dcmpun");
281    setCmpLibcallCC(RTLIB::UO_F64,  ISD::SETNE);
282    setLibcallName(RTLIB::O_F64,   "__aeabi_dcmpun");
283    setCmpLibcallCC(RTLIB::O_F64,   ISD::SETEQ);
284    setLibcallCallingConv(RTLIB::OEQ_F64, CallingConv::ARM_AAPCS);
285    setLibcallCallingConv(RTLIB::UNE_F64, CallingConv::ARM_AAPCS);
286    setLibcallCallingConv(RTLIB::OLT_F64, CallingConv::ARM_AAPCS);
287    setLibcallCallingConv(RTLIB::OLE_F64, CallingConv::ARM_AAPCS);
288    setLibcallCallingConv(RTLIB::OGE_F64, CallingConv::ARM_AAPCS);
289    setLibcallCallingConv(RTLIB::OGT_F64, CallingConv::ARM_AAPCS);
290    setLibcallCallingConv(RTLIB::UO_F64, CallingConv::ARM_AAPCS);
291    setLibcallCallingConv(RTLIB::O_F64, CallingConv::ARM_AAPCS);
292
293    // Single-precision floating-point arithmetic helper functions
294    // RTABI chapter 4.1.2, Table 4
295    setLibcallName(RTLIB::ADD_F32, "__aeabi_fadd");
296    setLibcallName(RTLIB::DIV_F32, "__aeabi_fdiv");
297    setLibcallName(RTLIB::MUL_F32, "__aeabi_fmul");
298    setLibcallName(RTLIB::SUB_F32, "__aeabi_fsub");
299    setLibcallCallingConv(RTLIB::ADD_F32, CallingConv::ARM_AAPCS);
300    setLibcallCallingConv(RTLIB::DIV_F32, CallingConv::ARM_AAPCS);
301    setLibcallCallingConv(RTLIB::MUL_F32, CallingConv::ARM_AAPCS);
302    setLibcallCallingConv(RTLIB::SUB_F32, CallingConv::ARM_AAPCS);
303
304    // Single-precision floating-point comparison helper functions
305    // RTABI chapter 4.1.2, Table 5
306    setLibcallName(RTLIB::OEQ_F32, "__aeabi_fcmpeq");
307    setCmpLibcallCC(RTLIB::OEQ_F32, ISD::SETNE);
308    setLibcallName(RTLIB::UNE_F32, "__aeabi_fcmpeq");
309    setCmpLibcallCC(RTLIB::UNE_F32, ISD::SETEQ);
310    setLibcallName(RTLIB::OLT_F32, "__aeabi_fcmplt");
311    setCmpLibcallCC(RTLIB::OLT_F32, ISD::SETNE);
312    setLibcallName(RTLIB::OLE_F32, "__aeabi_fcmple");
313    setCmpLibcallCC(RTLIB::OLE_F32, ISD::SETNE);
314    setLibcallName(RTLIB::OGE_F32, "__aeabi_fcmpge");
315    setCmpLibcallCC(RTLIB::OGE_F32, ISD::SETNE);
316    setLibcallName(RTLIB::OGT_F32, "__aeabi_fcmpgt");
317    setCmpLibcallCC(RTLIB::OGT_F32, ISD::SETNE);
318    setLibcallName(RTLIB::UO_F32,  "__aeabi_fcmpun");
319    setCmpLibcallCC(RTLIB::UO_F32,  ISD::SETNE);
320    setLibcallName(RTLIB::O_F32,   "__aeabi_fcmpun");
321    setCmpLibcallCC(RTLIB::O_F32,   ISD::SETEQ);
322    setLibcallCallingConv(RTLIB::OEQ_F32, CallingConv::ARM_AAPCS);
323    setLibcallCallingConv(RTLIB::UNE_F32, CallingConv::ARM_AAPCS);
324    setLibcallCallingConv(RTLIB::OLT_F32, CallingConv::ARM_AAPCS);
325    setLibcallCallingConv(RTLIB::OLE_F32, CallingConv::ARM_AAPCS);
326    setLibcallCallingConv(RTLIB::OGE_F32, CallingConv::ARM_AAPCS);
327    setLibcallCallingConv(RTLIB::OGT_F32, CallingConv::ARM_AAPCS);
328    setLibcallCallingConv(RTLIB::UO_F32, CallingConv::ARM_AAPCS);
329    setLibcallCallingConv(RTLIB::O_F32, CallingConv::ARM_AAPCS);
330
331    // Floating-point to integer conversions.
332    // RTABI chapter 4.1.2, Table 6
333    setLibcallName(RTLIB::FPTOSINT_F64_I32, "__aeabi_d2iz");
334    setLibcallName(RTLIB::FPTOUINT_F64_I32, "__aeabi_d2uiz");
335    setLibcallName(RTLIB::FPTOSINT_F64_I64, "__aeabi_d2lz");
336    setLibcallName(RTLIB::FPTOUINT_F64_I64, "__aeabi_d2ulz");
337    setLibcallName(RTLIB::FPTOSINT_F32_I32, "__aeabi_f2iz");
338    setLibcallName(RTLIB::FPTOUINT_F32_I32, "__aeabi_f2uiz");
339    setLibcallName(RTLIB::FPTOSINT_F32_I64, "__aeabi_f2lz");
340    setLibcallName(RTLIB::FPTOUINT_F32_I64, "__aeabi_f2ulz");
341    setLibcallCallingConv(RTLIB::FPTOSINT_F64_I32, CallingConv::ARM_AAPCS);
342    setLibcallCallingConv(RTLIB::FPTOUINT_F64_I32, CallingConv::ARM_AAPCS);
343    setLibcallCallingConv(RTLIB::FPTOSINT_F64_I64, CallingConv::ARM_AAPCS);
344    setLibcallCallingConv(RTLIB::FPTOUINT_F64_I64, CallingConv::ARM_AAPCS);
345    setLibcallCallingConv(RTLIB::FPTOSINT_F32_I32, CallingConv::ARM_AAPCS);
346    setLibcallCallingConv(RTLIB::FPTOUINT_F32_I32, CallingConv::ARM_AAPCS);
347    setLibcallCallingConv(RTLIB::FPTOSINT_F32_I64, CallingConv::ARM_AAPCS);
348    setLibcallCallingConv(RTLIB::FPTOUINT_F32_I64, CallingConv::ARM_AAPCS);
349
350    // Conversions between floating types.
351    // RTABI chapter 4.1.2, Table 7
352    setLibcallName(RTLIB::FPROUND_F64_F32, "__aeabi_d2f");
353    setLibcallName(RTLIB::FPEXT_F32_F64,   "__aeabi_f2d");
354    setLibcallCallingConv(RTLIB::FPROUND_F64_F32, CallingConv::ARM_AAPCS);
355    setLibcallCallingConv(RTLIB::FPEXT_F32_F64, CallingConv::ARM_AAPCS);
356
357    // Integer to floating-point conversions.
358    // RTABI chapter 4.1.2, Table 8
359    setLibcallName(RTLIB::SINTTOFP_I32_F64, "__aeabi_i2d");
360    setLibcallName(RTLIB::UINTTOFP_I32_F64, "__aeabi_ui2d");
361    setLibcallName(RTLIB::SINTTOFP_I64_F64, "__aeabi_l2d");
362    setLibcallName(RTLIB::UINTTOFP_I64_F64, "__aeabi_ul2d");
363    setLibcallName(RTLIB::SINTTOFP_I32_F32, "__aeabi_i2f");
364    setLibcallName(RTLIB::UINTTOFP_I32_F32, "__aeabi_ui2f");
365    setLibcallName(RTLIB::SINTTOFP_I64_F32, "__aeabi_l2f");
366    setLibcallName(RTLIB::UINTTOFP_I64_F32, "__aeabi_ul2f");
367    setLibcallCallingConv(RTLIB::SINTTOFP_I32_F64, CallingConv::ARM_AAPCS);
368    setLibcallCallingConv(RTLIB::UINTTOFP_I32_F64, CallingConv::ARM_AAPCS);
369    setLibcallCallingConv(RTLIB::SINTTOFP_I64_F64, CallingConv::ARM_AAPCS);
370    setLibcallCallingConv(RTLIB::UINTTOFP_I64_F64, CallingConv::ARM_AAPCS);
371    setLibcallCallingConv(RTLIB::SINTTOFP_I32_F32, CallingConv::ARM_AAPCS);
372    setLibcallCallingConv(RTLIB::UINTTOFP_I32_F32, CallingConv::ARM_AAPCS);
373    setLibcallCallingConv(RTLIB::SINTTOFP_I64_F32, CallingConv::ARM_AAPCS);
374    setLibcallCallingConv(RTLIB::UINTTOFP_I64_F32, CallingConv::ARM_AAPCS);
375
376    // Long long helper functions
377    // RTABI chapter 4.2, Table 9
378    setLibcallName(RTLIB::MUL_I64,  "__aeabi_lmul");
379    setLibcallName(RTLIB::SHL_I64, "__aeabi_llsl");
380    setLibcallName(RTLIB::SRL_I64, "__aeabi_llsr");
381    setLibcallName(RTLIB::SRA_I64, "__aeabi_lasr");
382    setLibcallCallingConv(RTLIB::MUL_I64, CallingConv::ARM_AAPCS);
383    setLibcallCallingConv(RTLIB::SDIV_I64, CallingConv::ARM_AAPCS);
384    setLibcallCallingConv(RTLIB::UDIV_I64, CallingConv::ARM_AAPCS);
385    setLibcallCallingConv(RTLIB::SHL_I64, CallingConv::ARM_AAPCS);
386    setLibcallCallingConv(RTLIB::SRL_I64, CallingConv::ARM_AAPCS);
387    setLibcallCallingConv(RTLIB::SRA_I64, CallingConv::ARM_AAPCS);
388
389    // Integer division functions
390    // RTABI chapter 4.3.1
391    setLibcallName(RTLIB::SDIV_I8,  "__aeabi_idiv");
392    setLibcallName(RTLIB::SDIV_I16, "__aeabi_idiv");
393    setLibcallName(RTLIB::SDIV_I32, "__aeabi_idiv");
394    setLibcallName(RTLIB::SDIV_I64, "__aeabi_ldivmod");
395    setLibcallName(RTLIB::UDIV_I8,  "__aeabi_uidiv");
396    setLibcallName(RTLIB::UDIV_I16, "__aeabi_uidiv");
397    setLibcallName(RTLIB::UDIV_I32, "__aeabi_uidiv");
398    setLibcallName(RTLIB::UDIV_I64, "__aeabi_uldivmod");
399    setLibcallCallingConv(RTLIB::SDIV_I8, CallingConv::ARM_AAPCS);
400    setLibcallCallingConv(RTLIB::SDIV_I16, CallingConv::ARM_AAPCS);
401    setLibcallCallingConv(RTLIB::SDIV_I32, CallingConv::ARM_AAPCS);
402    setLibcallCallingConv(RTLIB::SDIV_I64, CallingConv::ARM_AAPCS);
403    setLibcallCallingConv(RTLIB::UDIV_I8, CallingConv::ARM_AAPCS);
404    setLibcallCallingConv(RTLIB::UDIV_I16, CallingConv::ARM_AAPCS);
405    setLibcallCallingConv(RTLIB::UDIV_I32, CallingConv::ARM_AAPCS);
406    setLibcallCallingConv(RTLIB::UDIV_I64, CallingConv::ARM_AAPCS);
407
408    // Memory operations
409    // RTABI chapter 4.3.4
410    setLibcallName(RTLIB::MEMCPY,  "__aeabi_memcpy");
411    setLibcallName(RTLIB::MEMMOVE, "__aeabi_memmove");
412    setLibcallName(RTLIB::MEMSET,  "__aeabi_memset");
413    setLibcallCallingConv(RTLIB::MEMCPY, CallingConv::ARM_AAPCS);
414    setLibcallCallingConv(RTLIB::MEMMOVE, CallingConv::ARM_AAPCS);
415    setLibcallCallingConv(RTLIB::MEMSET, CallingConv::ARM_AAPCS);
416  }
417
418  // Use divmod compiler-rt calls for iOS 5.0 and later.
419  if (Subtarget->getTargetTriple().isiOS() &&
420      !Subtarget->getTargetTriple().isOSVersionLT(5, 0)) {
421    setLibcallName(RTLIB::SDIVREM_I32, "__divmodsi4");
422    setLibcallName(RTLIB::UDIVREM_I32, "__udivmodsi4");
423  }
424
425  if (Subtarget->isThumb1Only())
426    addRegisterClass(MVT::i32, &ARM::tGPRRegClass);
427  else
428    addRegisterClass(MVT::i32, &ARM::GPRRegClass);
429  if (!TM.Options.UseSoftFloat && Subtarget->hasVFP2() &&
430      !Subtarget->isThumb1Only()) {
431    addRegisterClass(MVT::f32, &ARM::SPRRegClass);
432    if (!Subtarget->isFPOnlySP())
433      addRegisterClass(MVT::f64, &ARM::DPRRegClass);
434
435    setTruncStoreAction(MVT::f64, MVT::f32, Expand);
436  }
437
438  for (unsigned VT = (unsigned)MVT::FIRST_VECTOR_VALUETYPE;
439       VT <= (unsigned)MVT::LAST_VECTOR_VALUETYPE; ++VT) {
440    for (unsigned InnerVT = (unsigned)MVT::FIRST_VECTOR_VALUETYPE;
441         InnerVT <= (unsigned)MVT::LAST_VECTOR_VALUETYPE; ++InnerVT)
442      setTruncStoreAction((MVT::SimpleValueType)VT,
443                          (MVT::SimpleValueType)InnerVT, Expand);
444    setLoadExtAction(ISD::SEXTLOAD, (MVT::SimpleValueType)VT, Expand);
445    setLoadExtAction(ISD::ZEXTLOAD, (MVT::SimpleValueType)VT, Expand);
446    setLoadExtAction(ISD::EXTLOAD, (MVT::SimpleValueType)VT, Expand);
447  }
448
449  setOperationAction(ISD::ConstantFP, MVT::f32, Custom);
450  setOperationAction(ISD::ConstantFP, MVT::f64, Custom);
451
452  if (Subtarget->hasNEON()) {
453    addDRTypeForNEON(MVT::v2f32);
454    addDRTypeForNEON(MVT::v8i8);
455    addDRTypeForNEON(MVT::v4i16);
456    addDRTypeForNEON(MVT::v2i32);
457    addDRTypeForNEON(MVT::v1i64);
458
459    addQRTypeForNEON(MVT::v4f32);
460    addQRTypeForNEON(MVT::v2f64);
461    addQRTypeForNEON(MVT::v16i8);
462    addQRTypeForNEON(MVT::v8i16);
463    addQRTypeForNEON(MVT::v4i32);
464    addQRTypeForNEON(MVT::v2i64);
465
466    // v2f64 is legal so that QR subregs can be extracted as f64 elements, but
467    // neither Neon nor VFP support any arithmetic operations on it.
468    // The same with v4f32. But keep in mind that vadd, vsub, vmul are natively
469    // supported for v4f32.
470    setOperationAction(ISD::FADD, MVT::v2f64, Expand);
471    setOperationAction(ISD::FSUB, MVT::v2f64, Expand);
472    setOperationAction(ISD::FMUL, MVT::v2f64, Expand);
473    // FIXME: Code duplication: FDIV and FREM are expanded always, see
474    // ARMTargetLowering::addTypeForNEON method for details.
475    setOperationAction(ISD::FDIV, MVT::v2f64, Expand);
476    setOperationAction(ISD::FREM, MVT::v2f64, Expand);
477    // FIXME: Create unittest.
478    // In another words, find a way when "copysign" appears in DAG with vector
479    // operands.
480    setOperationAction(ISD::FCOPYSIGN, MVT::v2f64, Expand);
481    // FIXME: Code duplication: SETCC has custom operation action, see
482    // ARMTargetLowering::addTypeForNEON method for details.
483    setOperationAction(ISD::SETCC, MVT::v2f64, Expand);
484    // FIXME: Create unittest for FNEG and for FABS.
485    setOperationAction(ISD::FNEG, MVT::v2f64, Expand);
486    setOperationAction(ISD::FABS, MVT::v2f64, Expand);
487    setOperationAction(ISD::FSQRT, MVT::v2f64, Expand);
488    setOperationAction(ISD::FSIN, MVT::v2f64, Expand);
489    setOperationAction(ISD::FCOS, MVT::v2f64, Expand);
490    setOperationAction(ISD::FPOWI, MVT::v2f64, Expand);
491    setOperationAction(ISD::FPOW, MVT::v2f64, Expand);
492    setOperationAction(ISD::FLOG, MVT::v2f64, Expand);
493    setOperationAction(ISD::FLOG2, MVT::v2f64, Expand);
494    setOperationAction(ISD::FLOG10, MVT::v2f64, Expand);
495    setOperationAction(ISD::FEXP, MVT::v2f64, Expand);
496    setOperationAction(ISD::FEXP2, MVT::v2f64, Expand);
497    // FIXME: Create unittest for FCEIL, FTRUNC, FRINT, FNEARBYINT, FFLOOR.
498    setOperationAction(ISD::FCEIL, MVT::v2f64, Expand);
499    setOperationAction(ISD::FTRUNC, MVT::v2f64, Expand);
500    setOperationAction(ISD::FRINT, MVT::v2f64, Expand);
501    setOperationAction(ISD::FNEARBYINT, MVT::v2f64, Expand);
502    setOperationAction(ISD::FFLOOR, MVT::v2f64, Expand);
503    setOperationAction(ISD::FMA, MVT::v2f64, Expand);
504
505    setOperationAction(ISD::FSQRT, MVT::v4f32, Expand);
506    setOperationAction(ISD::FSIN, MVT::v4f32, Expand);
507    setOperationAction(ISD::FCOS, MVT::v4f32, Expand);
508    setOperationAction(ISD::FPOWI, MVT::v4f32, Expand);
509    setOperationAction(ISD::FPOW, MVT::v4f32, Expand);
510    setOperationAction(ISD::FLOG, MVT::v4f32, Expand);
511    setOperationAction(ISD::FLOG2, MVT::v4f32, Expand);
512    setOperationAction(ISD::FLOG10, MVT::v4f32, Expand);
513    setOperationAction(ISD::FEXP, MVT::v4f32, Expand);
514    setOperationAction(ISD::FEXP2, MVT::v4f32, Expand);
515    setOperationAction(ISD::FCEIL, MVT::v4f32, Expand);
516    setOperationAction(ISD::FTRUNC, MVT::v4f32, Expand);
517    setOperationAction(ISD::FRINT, MVT::v4f32, Expand);
518    setOperationAction(ISD::FNEARBYINT, MVT::v4f32, Expand);
519    setOperationAction(ISD::FFLOOR, MVT::v4f32, Expand);
520
521    // Mark v2f32 intrinsics.
522    setOperationAction(ISD::FSQRT, MVT::v2f32, Expand);
523    setOperationAction(ISD::FSIN, MVT::v2f32, Expand);
524    setOperationAction(ISD::FCOS, MVT::v2f32, Expand);
525    setOperationAction(ISD::FPOWI, MVT::v2f32, Expand);
526    setOperationAction(ISD::FPOW, MVT::v2f32, Expand);
527    setOperationAction(ISD::FLOG, MVT::v2f32, Expand);
528    setOperationAction(ISD::FLOG2, MVT::v2f32, Expand);
529    setOperationAction(ISD::FLOG10, MVT::v2f32, Expand);
530    setOperationAction(ISD::FEXP, MVT::v2f32, Expand);
531    setOperationAction(ISD::FEXP2, MVT::v2f32, Expand);
532    setOperationAction(ISD::FCEIL, MVT::v2f32, Expand);
533    setOperationAction(ISD::FTRUNC, MVT::v2f32, Expand);
534    setOperationAction(ISD::FRINT, MVT::v2f32, Expand);
535    setOperationAction(ISD::FNEARBYINT, MVT::v2f32, Expand);
536    setOperationAction(ISD::FFLOOR, MVT::v2f32, Expand);
537
538    // Neon does not support some operations on v1i64 and v2i64 types.
539    setOperationAction(ISD::MUL, MVT::v1i64, Expand);
540    // Custom handling for some quad-vector types to detect VMULL.
541    setOperationAction(ISD::MUL, MVT::v8i16, Custom);
542    setOperationAction(ISD::MUL, MVT::v4i32, Custom);
543    setOperationAction(ISD::MUL, MVT::v2i64, Custom);
544    // Custom handling for some vector types to avoid expensive expansions
545    setOperationAction(ISD::SDIV, MVT::v4i16, Custom);
546    setOperationAction(ISD::SDIV, MVT::v8i8, Custom);
547    setOperationAction(ISD::UDIV, MVT::v4i16, Custom);
548    setOperationAction(ISD::UDIV, MVT::v8i8, Custom);
549    setOperationAction(ISD::SETCC, MVT::v1i64, Expand);
550    setOperationAction(ISD::SETCC, MVT::v2i64, Expand);
551    // Neon does not have single instruction SINT_TO_FP and UINT_TO_FP with
552    // a destination type that is wider than the source, and nor does
553    // it have a FP_TO_[SU]INT instruction with a narrower destination than
554    // source.
555    setOperationAction(ISD::SINT_TO_FP, MVT::v4i16, Custom);
556    setOperationAction(ISD::UINT_TO_FP, MVT::v4i16, Custom);
557    setOperationAction(ISD::FP_TO_UINT, MVT::v4i16, Custom);
558    setOperationAction(ISD::FP_TO_SINT, MVT::v4i16, Custom);
559
560    setOperationAction(ISD::FP_ROUND,   MVT::v2f32, Expand);
561    setOperationAction(ISD::FP_EXTEND,  MVT::v2f64, Expand);
562
563    // NEON does not have single instruction CTPOP for vectors with element
564    // types wider than 8-bits.  However, custom lowering can leverage the
565    // v8i8/v16i8 vcnt instruction.
566    setOperationAction(ISD::CTPOP,      MVT::v2i32, Custom);
567    setOperationAction(ISD::CTPOP,      MVT::v4i32, Custom);
568    setOperationAction(ISD::CTPOP,      MVT::v4i16, Custom);
569    setOperationAction(ISD::CTPOP,      MVT::v8i16, Custom);
570
571    // NEON only has FMA instructions as of VFP4.
572    if (!Subtarget->hasVFP4()) {
573      setOperationAction(ISD::FMA, MVT::v2f32, Expand);
574      setOperationAction(ISD::FMA, MVT::v4f32, Expand);
575    }
576
577    setTargetDAGCombine(ISD::INTRINSIC_VOID);
578    setTargetDAGCombine(ISD::INTRINSIC_W_CHAIN);
579    setTargetDAGCombine(ISD::INTRINSIC_WO_CHAIN);
580    setTargetDAGCombine(ISD::SHL);
581    setTargetDAGCombine(ISD::SRL);
582    setTargetDAGCombine(ISD::SRA);
583    setTargetDAGCombine(ISD::SIGN_EXTEND);
584    setTargetDAGCombine(ISD::ZERO_EXTEND);
585    setTargetDAGCombine(ISD::ANY_EXTEND);
586    setTargetDAGCombine(ISD::SELECT_CC);
587    setTargetDAGCombine(ISD::BUILD_VECTOR);
588    setTargetDAGCombine(ISD::VECTOR_SHUFFLE);
589    setTargetDAGCombine(ISD::INSERT_VECTOR_ELT);
590    setTargetDAGCombine(ISD::STORE);
591    setTargetDAGCombine(ISD::FP_TO_SINT);
592    setTargetDAGCombine(ISD::FP_TO_UINT);
593    setTargetDAGCombine(ISD::FDIV);
594
595    // It is legal to extload from v4i8 to v4i16 or v4i32.
596    MVT Tys[6] = {MVT::v8i8, MVT::v4i8, MVT::v2i8,
597                  MVT::v4i16, MVT::v2i16,
598                  MVT::v2i32};
599    for (unsigned i = 0; i < 6; ++i) {
600      setLoadExtAction(ISD::EXTLOAD, Tys[i], Legal);
601      setLoadExtAction(ISD::ZEXTLOAD, Tys[i], Legal);
602      setLoadExtAction(ISD::SEXTLOAD, Tys[i], Legal);
603    }
604  }
605
606  // ARM and Thumb2 support UMLAL/SMLAL.
607  if (!Subtarget->isThumb1Only())
608    setTargetDAGCombine(ISD::ADDC);
609
610
611  computeRegisterProperties();
612
613  // ARM does not have f32 extending load.
614  setLoadExtAction(ISD::EXTLOAD, MVT::f32, Expand);
615
616  // ARM does not have i1 sign extending load.
617  setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote);
618
619  // ARM supports all 4 flavors of integer indexed load / store.
620  if (!Subtarget->isThumb1Only()) {
621    for (unsigned im = (unsigned)ISD::PRE_INC;
622         im != (unsigned)ISD::LAST_INDEXED_MODE; ++im) {
623      setIndexedLoadAction(im,  MVT::i1,  Legal);
624      setIndexedLoadAction(im,  MVT::i8,  Legal);
625      setIndexedLoadAction(im,  MVT::i16, Legal);
626      setIndexedLoadAction(im,  MVT::i32, Legal);
627      setIndexedStoreAction(im, MVT::i1,  Legal);
628      setIndexedStoreAction(im, MVT::i8,  Legal);
629      setIndexedStoreAction(im, MVT::i16, Legal);
630      setIndexedStoreAction(im, MVT::i32, Legal);
631    }
632  }
633
634  // i64 operation support.
635  setOperationAction(ISD::MUL,     MVT::i64, Expand);
636  setOperationAction(ISD::MULHU,   MVT::i32, Expand);
637  if (Subtarget->isThumb1Only()) {
638    setOperationAction(ISD::UMUL_LOHI, MVT::i32, Expand);
639    setOperationAction(ISD::SMUL_LOHI, MVT::i32, Expand);
640  }
641  if (Subtarget->isThumb1Only() || !Subtarget->hasV6Ops()
642      || (Subtarget->isThumb2() && !Subtarget->hasThumb2DSP()))
643    setOperationAction(ISD::MULHS, MVT::i32, Expand);
644
645  setOperationAction(ISD::SHL_PARTS, MVT::i32, Custom);
646  setOperationAction(ISD::SRA_PARTS, MVT::i32, Custom);
647  setOperationAction(ISD::SRL_PARTS, MVT::i32, Custom);
648  setOperationAction(ISD::SRL,       MVT::i64, Custom);
649  setOperationAction(ISD::SRA,       MVT::i64, Custom);
650
651  if (!Subtarget->isThumb1Only()) {
652    // FIXME: We should do this for Thumb1 as well.
653    setOperationAction(ISD::ADDC,    MVT::i32, Custom);
654    setOperationAction(ISD::ADDE,    MVT::i32, Custom);
655    setOperationAction(ISD::SUBC,    MVT::i32, Custom);
656    setOperationAction(ISD::SUBE,    MVT::i32, Custom);
657  }
658
659  // ARM does not have ROTL.
660  setOperationAction(ISD::ROTL,  MVT::i32, Expand);
661  setOperationAction(ISD::CTTZ,  MVT::i32, Custom);
662  setOperationAction(ISD::CTPOP, MVT::i32, Expand);
663  if (!Subtarget->hasV5TOps() || Subtarget->isThumb1Only())
664    setOperationAction(ISD::CTLZ, MVT::i32, Expand);
665
666  // These just redirect to CTTZ and CTLZ on ARM.
667  setOperationAction(ISD::CTTZ_ZERO_UNDEF  , MVT::i32  , Expand);
668  setOperationAction(ISD::CTLZ_ZERO_UNDEF  , MVT::i32  , Expand);
669
670  setOperationAction(ISD::READCYCLECOUNTER, MVT::i64, Custom);
671
672  // Only ARMv6 has BSWAP.
673  if (!Subtarget->hasV6Ops())
674    setOperationAction(ISD::BSWAP, MVT::i32, Expand);
675
676  if (!(Subtarget->hasDivide() && Subtarget->isThumb2()) &&
677      !(Subtarget->hasDivideInARMMode() && !Subtarget->isThumb())) {
678    // These are expanded into libcalls if the cpu doesn't have HW divider.
679    setOperationAction(ISD::SDIV,  MVT::i32, Expand);
680    setOperationAction(ISD::UDIV,  MVT::i32, Expand);
681  }
682
683  // FIXME: Also set divmod for SREM on EABI
684  setOperationAction(ISD::SREM,  MVT::i32, Expand);
685  setOperationAction(ISD::UREM,  MVT::i32, Expand);
686  // Register based DivRem for AEABI (RTABI 4.2)
687  if (Subtarget->isTargetAEABI()) {
688    setLibcallName(RTLIB::SDIVREM_I8,  "__aeabi_idivmod");
689    setLibcallName(RTLIB::SDIVREM_I16, "__aeabi_idivmod");
690    setLibcallName(RTLIB::SDIVREM_I32, "__aeabi_idivmod");
691    setLibcallName(RTLIB::SDIVREM_I64, "__aeabi_ldivmod");
692    setLibcallName(RTLIB::UDIVREM_I8,  "__aeabi_uidivmod");
693    setLibcallName(RTLIB::UDIVREM_I16, "__aeabi_uidivmod");
694    setLibcallName(RTLIB::UDIVREM_I32, "__aeabi_uidivmod");
695    setLibcallName(RTLIB::UDIVREM_I64, "__aeabi_uldivmod");
696
697    setLibcallCallingConv(RTLIB::SDIVREM_I8, CallingConv::ARM_AAPCS);
698    setLibcallCallingConv(RTLIB::SDIVREM_I16, CallingConv::ARM_AAPCS);
699    setLibcallCallingConv(RTLIB::SDIVREM_I32, CallingConv::ARM_AAPCS);
700    setLibcallCallingConv(RTLIB::SDIVREM_I64, CallingConv::ARM_AAPCS);
701    setLibcallCallingConv(RTLIB::UDIVREM_I8, CallingConv::ARM_AAPCS);
702    setLibcallCallingConv(RTLIB::UDIVREM_I16, CallingConv::ARM_AAPCS);
703    setLibcallCallingConv(RTLIB::UDIVREM_I32, CallingConv::ARM_AAPCS);
704    setLibcallCallingConv(RTLIB::UDIVREM_I64, CallingConv::ARM_AAPCS);
705
706    setOperationAction(ISD::SDIVREM, MVT::i32, Custom);
707    setOperationAction(ISD::UDIVREM, MVT::i32, Custom);
708  } else {
709    setOperationAction(ISD::SDIVREM, MVT::i32, Expand);
710    setOperationAction(ISD::UDIVREM, MVT::i32, Expand);
711  }
712
713  setOperationAction(ISD::GlobalAddress, MVT::i32,   Custom);
714  setOperationAction(ISD::ConstantPool,  MVT::i32,   Custom);
715  setOperationAction(ISD::GLOBAL_OFFSET_TABLE, MVT::i32, Custom);
716  setOperationAction(ISD::GlobalTLSAddress, MVT::i32, Custom);
717  setOperationAction(ISD::BlockAddress, MVT::i32, Custom);
718
719  setOperationAction(ISD::TRAP, MVT::Other, Legal);
720
721  // Use the default implementation.
722  setOperationAction(ISD::VASTART,            MVT::Other, Custom);
723  setOperationAction(ISD::VAARG,              MVT::Other, Expand);
724  setOperationAction(ISD::VACOPY,             MVT::Other, Expand);
725  setOperationAction(ISD::VAEND,              MVT::Other, Expand);
726  setOperationAction(ISD::STACKSAVE,          MVT::Other, Expand);
727  setOperationAction(ISD::STACKRESTORE,       MVT::Other, Expand);
728
729  if (!Subtarget->isTargetMachO()) {
730    // Non-MachO platforms may return values in these registers via the
731    // personality function.
732    setExceptionPointerRegister(ARM::R0);
733    setExceptionSelectorRegister(ARM::R1);
734  }
735
736  setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32, Expand);
737  // ARMv6 Thumb1 (except for CPUs that support dmb / dsb) and earlier use
738  // the default expansion.
739  if (Subtarget->hasAnyDataBarrier() && !Subtarget->isThumb1Only()) {
740    // ATOMIC_FENCE needs custom lowering; the others should have been expanded
741    // to ldrex/strex loops already.
742    setOperationAction(ISD::ATOMIC_FENCE,     MVT::Other, Custom);
743
744    // On v8, we have particularly efficient implementations of atomic fences
745    // if they can be combined with nearby atomic loads and stores.
746    if (!Subtarget->hasV8Ops()) {
747      // Automatically insert fences (dmb ist) around ATOMIC_SWAP etc.
748      setInsertFencesForAtomic(true);
749    }
750  } else {
751    // If there's anything we can use as a barrier, go through custom lowering
752    // for ATOMIC_FENCE.
753    setOperationAction(ISD::ATOMIC_FENCE,   MVT::Other,
754                       Subtarget->hasAnyDataBarrier() ? Custom : Expand);
755
756    // Set them all for expansion, which will force libcalls.
757    setOperationAction(ISD::ATOMIC_CMP_SWAP,  MVT::i32, Expand);
758    setOperationAction(ISD::ATOMIC_SWAP,      MVT::i32, Expand);
759    setOperationAction(ISD::ATOMIC_LOAD_ADD,  MVT::i32, Expand);
760    setOperationAction(ISD::ATOMIC_LOAD_SUB,  MVT::i32, Expand);
761    setOperationAction(ISD::ATOMIC_LOAD_AND,  MVT::i32, Expand);
762    setOperationAction(ISD::ATOMIC_LOAD_OR,   MVT::i32, Expand);
763    setOperationAction(ISD::ATOMIC_LOAD_XOR,  MVT::i32, Expand);
764    setOperationAction(ISD::ATOMIC_LOAD_NAND, MVT::i32, Expand);
765    setOperationAction(ISD::ATOMIC_LOAD_MIN, MVT::i32, Expand);
766    setOperationAction(ISD::ATOMIC_LOAD_MAX, MVT::i32, Expand);
767    setOperationAction(ISD::ATOMIC_LOAD_UMIN, MVT::i32, Expand);
768    setOperationAction(ISD::ATOMIC_LOAD_UMAX, MVT::i32, Expand);
769    // Mark ATOMIC_LOAD and ATOMIC_STORE custom so we can handle the
770    // Unordered/Monotonic case.
771    setOperationAction(ISD::ATOMIC_LOAD, MVT::i32, Custom);
772    setOperationAction(ISD::ATOMIC_STORE, MVT::i32, Custom);
773  }
774
775  setOperationAction(ISD::PREFETCH,         MVT::Other, Custom);
776
777  // Requires SXTB/SXTH, available on v6 and up in both ARM and Thumb modes.
778  if (!Subtarget->hasV6Ops()) {
779    setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16, Expand);
780    setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8,  Expand);
781  }
782  setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand);
783
784  if (!TM.Options.UseSoftFloat && Subtarget->hasVFP2() &&
785      !Subtarget->isThumb1Only()) {
786    // Turn f64->i64 into VMOVRRD, i64 -> f64 to VMOVDRR
787    // iff target supports vfp2.
788    setOperationAction(ISD::BITCAST, MVT::i64, Custom);
789    setOperationAction(ISD::FLT_ROUNDS_, MVT::i32, Custom);
790  }
791
792  // We want to custom lower some of our intrinsics.
793  setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom);
794  if (Subtarget->isTargetDarwin()) {
795    setOperationAction(ISD::EH_SJLJ_SETJMP, MVT::i32, Custom);
796    setOperationAction(ISD::EH_SJLJ_LONGJMP, MVT::Other, Custom);
797    setLibcallName(RTLIB::UNWIND_RESUME, "_Unwind_SjLj_Resume");
798  }
799
800  setOperationAction(ISD::SETCC,     MVT::i32, Expand);
801  setOperationAction(ISD::SETCC,     MVT::f32, Expand);
802  setOperationAction(ISD::SETCC,     MVT::f64, Expand);
803  setOperationAction(ISD::SELECT,    MVT::i32, Custom);
804  setOperationAction(ISD::SELECT,    MVT::f32, Custom);
805  setOperationAction(ISD::SELECT,    MVT::f64, Custom);
806  setOperationAction(ISD::SELECT_CC, MVT::i32, Custom);
807  setOperationAction(ISD::SELECT_CC, MVT::f32, Custom);
808  setOperationAction(ISD::SELECT_CC, MVT::f64, Custom);
809
810  setOperationAction(ISD::BRCOND,    MVT::Other, Expand);
811  setOperationAction(ISD::BR_CC,     MVT::i32,   Custom);
812  setOperationAction(ISD::BR_CC,     MVT::f32,   Custom);
813  setOperationAction(ISD::BR_CC,     MVT::f64,   Custom);
814  setOperationAction(ISD::BR_JT,     MVT::Other, Custom);
815
816  // We don't support sin/cos/fmod/copysign/pow
817  setOperationAction(ISD::FSIN,      MVT::f64, Expand);
818  setOperationAction(ISD::FSIN,      MVT::f32, Expand);
819  setOperationAction(ISD::FCOS,      MVT::f32, Expand);
820  setOperationAction(ISD::FCOS,      MVT::f64, Expand);
821  setOperationAction(ISD::FSINCOS,   MVT::f64, Expand);
822  setOperationAction(ISD::FSINCOS,   MVT::f32, Expand);
823  setOperationAction(ISD::FREM,      MVT::f64, Expand);
824  setOperationAction(ISD::FREM,      MVT::f32, Expand);
825  if (!TM.Options.UseSoftFloat && Subtarget->hasVFP2() &&
826      !Subtarget->isThumb1Only()) {
827    setOperationAction(ISD::FCOPYSIGN, MVT::f64, Custom);
828    setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom);
829  }
830  setOperationAction(ISD::FPOW,      MVT::f64, Expand);
831  setOperationAction(ISD::FPOW,      MVT::f32, Expand);
832
833  if (!Subtarget->hasVFP4()) {
834    setOperationAction(ISD::FMA, MVT::f64, Expand);
835    setOperationAction(ISD::FMA, MVT::f32, Expand);
836  }
837
838  // Various VFP goodness
839  if (!TM.Options.UseSoftFloat && !Subtarget->isThumb1Only()) {
840    // int <-> fp are custom expanded into bit_convert + ARMISD ops.
841    if (Subtarget->hasVFP2()) {
842      setOperationAction(ISD::SINT_TO_FP, MVT::i32, Custom);
843      setOperationAction(ISD::UINT_TO_FP, MVT::i32, Custom);
844      setOperationAction(ISD::FP_TO_UINT, MVT::i32, Custom);
845      setOperationAction(ISD::FP_TO_SINT, MVT::i32, Custom);
846    }
847    // Special handling for half-precision FP.
848    if (!Subtarget->hasFP16()) {
849      setOperationAction(ISD::FP16_TO_FP32, MVT::f32, Expand);
850      setOperationAction(ISD::FP32_TO_FP16, MVT::i32, Expand);
851    }
852  }
853
854  // Combine sin / cos into one node or libcall if possible.
855  if (Subtarget->hasSinCos()) {
856    setLibcallName(RTLIB::SINCOS_F32, "sincosf");
857    setLibcallName(RTLIB::SINCOS_F64, "sincos");
858    if (Subtarget->getTargetTriple().getOS() == Triple::IOS) {
859      // For iOS, we don't want to the normal expansion of a libcall to
860      // sincos. We want to issue a libcall to __sincos_stret.
861      setOperationAction(ISD::FSINCOS, MVT::f64, Custom);
862      setOperationAction(ISD::FSINCOS, MVT::f32, Custom);
863    }
864  }
865
866  // We have target-specific dag combine patterns for the following nodes:
867  // ARMISD::VMOVRRD  - No need to call setTargetDAGCombine
868  setTargetDAGCombine(ISD::ADD);
869  setTargetDAGCombine(ISD::SUB);
870  setTargetDAGCombine(ISD::MUL);
871  setTargetDAGCombine(ISD::AND);
872  setTargetDAGCombine(ISD::OR);
873  setTargetDAGCombine(ISD::XOR);
874
875  if (Subtarget->hasV6Ops())
876    setTargetDAGCombine(ISD::SRL);
877
878  setStackPointerRegisterToSaveRestore(ARM::SP);
879
880  if (TM.Options.UseSoftFloat || Subtarget->isThumb1Only() ||
881      !Subtarget->hasVFP2())
882    setSchedulingPreference(Sched::RegPressure);
883  else
884    setSchedulingPreference(Sched::Hybrid);
885
886  //// temporary - rewrite interface to use type
887  MaxStoresPerMemset = 8;
888  MaxStoresPerMemsetOptSize = Subtarget->isTargetDarwin() ? 8 : 4;
889  MaxStoresPerMemcpy = 4; // For @llvm.memcpy -> sequence of stores
890  MaxStoresPerMemcpyOptSize = Subtarget->isTargetDarwin() ? 4 : 2;
891  MaxStoresPerMemmove = 4; // For @llvm.memmove -> sequence of stores
892  MaxStoresPerMemmoveOptSize = Subtarget->isTargetDarwin() ? 4 : 2;
893
894  // On ARM arguments smaller than 4 bytes are extended, so all arguments
895  // are at least 4 bytes aligned.
896  setMinStackArgumentAlignment(4);
897
898  // Prefer likely predicted branches to selects on out-of-order cores.
899  PredictableSelectIsExpensive = Subtarget->isLikeA9();
900
901  setMinFunctionAlignment(Subtarget->isThumb() ? 1 : 2);
902}
903
904// FIXME: It might make sense to define the representative register class as the
905// nearest super-register that has a non-null superset. For example, DPR_VFP2 is
906// a super-register of SPR, and DPR is a superset if DPR_VFP2. Consequently,
907// SPR's representative would be DPR_VFP2. This should work well if register
908// pressure tracking were modified such that a register use would increment the
909// pressure of the register class's representative and all of it's super
910// classes' representatives transitively. We have not implemented this because
911// of the difficulty prior to coalescing of modeling operand register classes
912// due to the common occurrence of cross class copies and subregister insertions
913// and extractions.
914std::pair<const TargetRegisterClass*, uint8_t>
915ARMTargetLowering::findRepresentativeClass(MVT VT) const{
916  const TargetRegisterClass *RRC = 0;
917  uint8_t Cost = 1;
918  switch (VT.SimpleTy) {
919  default:
920    return TargetLowering::findRepresentativeClass(VT);
921  // Use DPR as representative register class for all floating point
922  // and vector types. Since there are 32 SPR registers and 32 DPR registers so
923  // the cost is 1 for both f32 and f64.
924  case MVT::f32: case MVT::f64: case MVT::v8i8: case MVT::v4i16:
925  case MVT::v2i32: case MVT::v1i64: case MVT::v2f32:
926    RRC = &ARM::DPRRegClass;
927    // When NEON is used for SP, only half of the register file is available
928    // because operations that define both SP and DP results will be constrained
929    // to the VFP2 class (D0-D15). We currently model this constraint prior to
930    // coalescing by double-counting the SP regs. See the FIXME above.
931    if (Subtarget->useNEONForSinglePrecisionFP())
932      Cost = 2;
933    break;
934  case MVT::v16i8: case MVT::v8i16: case MVT::v4i32: case MVT::v2i64:
935  case MVT::v4f32: case MVT::v2f64:
936    RRC = &ARM::DPRRegClass;
937    Cost = 2;
938    break;
939  case MVT::v4i64:
940    RRC = &ARM::DPRRegClass;
941    Cost = 4;
942    break;
943  case MVT::v8i64:
944    RRC = &ARM::DPRRegClass;
945    Cost = 8;
946    break;
947  }
948  return std::make_pair(RRC, Cost);
949}
950
951const char *ARMTargetLowering::getTargetNodeName(unsigned Opcode) const {
952  switch (Opcode) {
953  default: return 0;
954  case ARMISD::Wrapper:       return "ARMISD::Wrapper";
955  case ARMISD::WrapperPIC:    return "ARMISD::WrapperPIC";
956  case ARMISD::WrapperJT:     return "ARMISD::WrapperJT";
957  case ARMISD::CALL:          return "ARMISD::CALL";
958  case ARMISD::CALL_PRED:     return "ARMISD::CALL_PRED";
959  case ARMISD::CALL_NOLINK:   return "ARMISD::CALL_NOLINK";
960  case ARMISD::tCALL:         return "ARMISD::tCALL";
961  case ARMISD::BRCOND:        return "ARMISD::BRCOND";
962  case ARMISD::BR_JT:         return "ARMISD::BR_JT";
963  case ARMISD::BR2_JT:        return "ARMISD::BR2_JT";
964  case ARMISD::RET_FLAG:      return "ARMISD::RET_FLAG";
965  case ARMISD::INTRET_FLAG:   return "ARMISD::INTRET_FLAG";
966  case ARMISD::PIC_ADD:       return "ARMISD::PIC_ADD";
967  case ARMISD::CMP:           return "ARMISD::CMP";
968  case ARMISD::CMN:           return "ARMISD::CMN";
969  case ARMISD::CMPZ:          return "ARMISD::CMPZ";
970  case ARMISD::CMPFP:         return "ARMISD::CMPFP";
971  case ARMISD::CMPFPw0:       return "ARMISD::CMPFPw0";
972  case ARMISD::BCC_i64:       return "ARMISD::BCC_i64";
973  case ARMISD::FMSTAT:        return "ARMISD::FMSTAT";
974
975  case ARMISD::CMOV:          return "ARMISD::CMOV";
976
977  case ARMISD::RBIT:          return "ARMISD::RBIT";
978
979  case ARMISD::FTOSI:         return "ARMISD::FTOSI";
980  case ARMISD::FTOUI:         return "ARMISD::FTOUI";
981  case ARMISD::SITOF:         return "ARMISD::SITOF";
982  case ARMISD::UITOF:         return "ARMISD::UITOF";
983
984  case ARMISD::SRL_FLAG:      return "ARMISD::SRL_FLAG";
985  case ARMISD::SRA_FLAG:      return "ARMISD::SRA_FLAG";
986  case ARMISD::RRX:           return "ARMISD::RRX";
987
988  case ARMISD::ADDC:          return "ARMISD::ADDC";
989  case ARMISD::ADDE:          return "ARMISD::ADDE";
990  case ARMISD::SUBC:          return "ARMISD::SUBC";
991  case ARMISD::SUBE:          return "ARMISD::SUBE";
992
993  case ARMISD::VMOVRRD:       return "ARMISD::VMOVRRD";
994  case ARMISD::VMOVDRR:       return "ARMISD::VMOVDRR";
995
996  case ARMISD::EH_SJLJ_SETJMP: return "ARMISD::EH_SJLJ_SETJMP";
997  case ARMISD::EH_SJLJ_LONGJMP:return "ARMISD::EH_SJLJ_LONGJMP";
998
999  case ARMISD::TC_RETURN:     return "ARMISD::TC_RETURN";
1000
1001  case ARMISD::THREAD_POINTER:return "ARMISD::THREAD_POINTER";
1002
1003  case ARMISD::DYN_ALLOC:     return "ARMISD::DYN_ALLOC";
1004
1005  case ARMISD::MEMBARRIER_MCR: return "ARMISD::MEMBARRIER_MCR";
1006
1007  case ARMISD::PRELOAD:       return "ARMISD::PRELOAD";
1008
1009  case ARMISD::VCEQ:          return "ARMISD::VCEQ";
1010  case ARMISD::VCEQZ:         return "ARMISD::VCEQZ";
1011  case ARMISD::VCGE:          return "ARMISD::VCGE";
1012  case ARMISD::VCGEZ:         return "ARMISD::VCGEZ";
1013  case ARMISD::VCLEZ:         return "ARMISD::VCLEZ";
1014  case ARMISD::VCGEU:         return "ARMISD::VCGEU";
1015  case ARMISD::VCGT:          return "ARMISD::VCGT";
1016  case ARMISD::VCGTZ:         return "ARMISD::VCGTZ";
1017  case ARMISD::VCLTZ:         return "ARMISD::VCLTZ";
1018  case ARMISD::VCGTU:         return "ARMISD::VCGTU";
1019  case ARMISD::VTST:          return "ARMISD::VTST";
1020
1021  case ARMISD::VSHL:          return "ARMISD::VSHL";
1022  case ARMISD::VSHRs:         return "ARMISD::VSHRs";
1023  case ARMISD::VSHRu:         return "ARMISD::VSHRu";
1024  case ARMISD::VRSHRs:        return "ARMISD::VRSHRs";
1025  case ARMISD::VRSHRu:        return "ARMISD::VRSHRu";
1026  case ARMISD::VRSHRN:        return "ARMISD::VRSHRN";
1027  case ARMISD::VQSHLs:        return "ARMISD::VQSHLs";
1028  case ARMISD::VQSHLu:        return "ARMISD::VQSHLu";
1029  case ARMISD::VQSHLsu:       return "ARMISD::VQSHLsu";
1030  case ARMISD::VQSHRNs:       return "ARMISD::VQSHRNs";
1031  case ARMISD::VQSHRNu:       return "ARMISD::VQSHRNu";
1032  case ARMISD::VQSHRNsu:      return "ARMISD::VQSHRNsu";
1033  case ARMISD::VQRSHRNs:      return "ARMISD::VQRSHRNs";
1034  case ARMISD::VQRSHRNu:      return "ARMISD::VQRSHRNu";
1035  case ARMISD::VQRSHRNsu:     return "ARMISD::VQRSHRNsu";
1036  case ARMISD::VGETLANEu:     return "ARMISD::VGETLANEu";
1037  case ARMISD::VGETLANEs:     return "ARMISD::VGETLANEs";
1038  case ARMISD::VMOVIMM:       return "ARMISD::VMOVIMM";
1039  case ARMISD::VMVNIMM:       return "ARMISD::VMVNIMM";
1040  case ARMISD::VMOVFPIMM:     return "ARMISD::VMOVFPIMM";
1041  case ARMISD::VDUP:          return "ARMISD::VDUP";
1042  case ARMISD::VDUPLANE:      return "ARMISD::VDUPLANE";
1043  case ARMISD::VEXT:          return "ARMISD::VEXT";
1044  case ARMISD::VREV64:        return "ARMISD::VREV64";
1045  case ARMISD::VREV32:        return "ARMISD::VREV32";
1046  case ARMISD::VREV16:        return "ARMISD::VREV16";
1047  case ARMISD::VZIP:          return "ARMISD::VZIP";
1048  case ARMISD::VUZP:          return "ARMISD::VUZP";
1049  case ARMISD::VTRN:          return "ARMISD::VTRN";
1050  case ARMISD::VTBL1:         return "ARMISD::VTBL1";
1051  case ARMISD::VTBL2:         return "ARMISD::VTBL2";
1052  case ARMISD::VMULLs:        return "ARMISD::VMULLs";
1053  case ARMISD::VMULLu:        return "ARMISD::VMULLu";
1054  case ARMISD::UMLAL:         return "ARMISD::UMLAL";
1055  case ARMISD::SMLAL:         return "ARMISD::SMLAL";
1056  case ARMISD::BUILD_VECTOR:  return "ARMISD::BUILD_VECTOR";
1057  case ARMISD::FMAX:          return "ARMISD::FMAX";
1058  case ARMISD::FMIN:          return "ARMISD::FMIN";
1059  case ARMISD::VMAXNM:        return "ARMISD::VMAX";
1060  case ARMISD::VMINNM:        return "ARMISD::VMIN";
1061  case ARMISD::BFI:           return "ARMISD::BFI";
1062  case ARMISD::VORRIMM:       return "ARMISD::VORRIMM";
1063  case ARMISD::VBICIMM:       return "ARMISD::VBICIMM";
1064  case ARMISD::VBSL:          return "ARMISD::VBSL";
1065  case ARMISD::VLD2DUP:       return "ARMISD::VLD2DUP";
1066  case ARMISD::VLD3DUP:       return "ARMISD::VLD3DUP";
1067  case ARMISD::VLD4DUP:       return "ARMISD::VLD4DUP";
1068  case ARMISD::VLD1_UPD:      return "ARMISD::VLD1_UPD";
1069  case ARMISD::VLD2_UPD:      return "ARMISD::VLD2_UPD";
1070  case ARMISD::VLD3_UPD:      return "ARMISD::VLD3_UPD";
1071  case ARMISD::VLD4_UPD:      return "ARMISD::VLD4_UPD";
1072  case ARMISD::VLD2LN_UPD:    return "ARMISD::VLD2LN_UPD";
1073  case ARMISD::VLD3LN_UPD:    return "ARMISD::VLD3LN_UPD";
1074  case ARMISD::VLD4LN_UPD:    return "ARMISD::VLD4LN_UPD";
1075  case ARMISD::VLD2DUP_UPD:   return "ARMISD::VLD2DUP_UPD";
1076  case ARMISD::VLD3DUP_UPD:   return "ARMISD::VLD3DUP_UPD";
1077  case ARMISD::VLD4DUP_UPD:   return "ARMISD::VLD4DUP_UPD";
1078  case ARMISD::VST1_UPD:      return "ARMISD::VST1_UPD";
1079  case ARMISD::VST2_UPD:      return "ARMISD::VST2_UPD";
1080  case ARMISD::VST3_UPD:      return "ARMISD::VST3_UPD";
1081  case ARMISD::VST4_UPD:      return "ARMISD::VST4_UPD";
1082  case ARMISD::VST2LN_UPD:    return "ARMISD::VST2LN_UPD";
1083  case ARMISD::VST3LN_UPD:    return "ARMISD::VST3LN_UPD";
1084  case ARMISD::VST4LN_UPD:    return "ARMISD::VST4LN_UPD";
1085  }
1086}
1087
1088EVT ARMTargetLowering::getSetCCResultType(LLVMContext &, EVT VT) const {
1089  if (!VT.isVector()) return getPointerTy();
1090  return VT.changeVectorElementTypeToInteger();
1091}
1092
1093/// getRegClassFor - Return the register class that should be used for the
1094/// specified value type.
1095const TargetRegisterClass *ARMTargetLowering::getRegClassFor(MVT VT) const {
1096  // Map v4i64 to QQ registers but do not make the type legal. Similarly map
1097  // v8i64 to QQQQ registers. v4i64 and v8i64 are only used for REG_SEQUENCE to
1098  // load / store 4 to 8 consecutive D registers.
1099  if (Subtarget->hasNEON()) {
1100    if (VT == MVT::v4i64)
1101      return &ARM::QQPRRegClass;
1102    if (VT == MVT::v8i64)
1103      return &ARM::QQQQPRRegClass;
1104  }
1105  return TargetLowering::getRegClassFor(VT);
1106}
1107
1108// Create a fast isel object.
1109FastISel *
1110ARMTargetLowering::createFastISel(FunctionLoweringInfo &funcInfo,
1111                                  const TargetLibraryInfo *libInfo) const {
1112  return ARM::createFastISel(funcInfo, libInfo);
1113}
1114
1115/// getMaximalGlobalOffset - Returns the maximal possible offset which can
1116/// be used for loads / stores from the global.
1117unsigned ARMTargetLowering::getMaximalGlobalOffset() const {
1118  return (Subtarget->isThumb1Only() ? 127 : 4095);
1119}
1120
1121Sched::Preference ARMTargetLowering::getSchedulingPreference(SDNode *N) const {
1122  unsigned NumVals = N->getNumValues();
1123  if (!NumVals)
1124    return Sched::RegPressure;
1125
1126  for (unsigned i = 0; i != NumVals; ++i) {
1127    EVT VT = N->getValueType(i);
1128    if (VT == MVT::Glue || VT == MVT::Other)
1129      continue;
1130    if (VT.isFloatingPoint() || VT.isVector())
1131      return Sched::ILP;
1132  }
1133
1134  if (!N->isMachineOpcode())
1135    return Sched::RegPressure;
1136
1137  // Load are scheduled for latency even if there instruction itinerary
1138  // is not available.
1139  const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
1140  const MCInstrDesc &MCID = TII->get(N->getMachineOpcode());
1141
1142  if (MCID.getNumDefs() == 0)
1143    return Sched::RegPressure;
1144  if (!Itins->isEmpty() &&
1145      Itins->getOperandCycle(MCID.getSchedClass(), 0) > 2)
1146    return Sched::ILP;
1147
1148  return Sched::RegPressure;
1149}
1150
1151//===----------------------------------------------------------------------===//
1152// Lowering Code
1153//===----------------------------------------------------------------------===//
1154
1155/// IntCCToARMCC - Convert a DAG integer condition code to an ARM CC
1156static ARMCC::CondCodes IntCCToARMCC(ISD::CondCode CC) {
1157  switch (CC) {
1158  default: llvm_unreachable("Unknown condition code!");
1159  case ISD::SETNE:  return ARMCC::NE;
1160  case ISD::SETEQ:  return ARMCC::EQ;
1161  case ISD::SETGT:  return ARMCC::GT;
1162  case ISD::SETGE:  return ARMCC::GE;
1163  case ISD::SETLT:  return ARMCC::LT;
1164  case ISD::SETLE:  return ARMCC::LE;
1165  case ISD::SETUGT: return ARMCC::HI;
1166  case ISD::SETUGE: return ARMCC::HS;
1167  case ISD::SETULT: return ARMCC::LO;
1168  case ISD::SETULE: return ARMCC::LS;
1169  }
1170}
1171
1172/// FPCCToARMCC - Convert a DAG fp condition code to an ARM CC.
1173static void FPCCToARMCC(ISD::CondCode CC, ARMCC::CondCodes &CondCode,
1174                        ARMCC::CondCodes &CondCode2) {
1175  CondCode2 = ARMCC::AL;
1176  switch (CC) {
1177  default: llvm_unreachable("Unknown FP condition!");
1178  case ISD::SETEQ:
1179  case ISD::SETOEQ: CondCode = ARMCC::EQ; break;
1180  case ISD::SETGT:
1181  case ISD::SETOGT: CondCode = ARMCC::GT; break;
1182  case ISD::SETGE:
1183  case ISD::SETOGE: CondCode = ARMCC::GE; break;
1184  case ISD::SETOLT: CondCode = ARMCC::MI; break;
1185  case ISD::SETOLE: CondCode = ARMCC::LS; break;
1186  case ISD::SETONE: CondCode = ARMCC::MI; CondCode2 = ARMCC::GT; break;
1187  case ISD::SETO:   CondCode = ARMCC::VC; break;
1188  case ISD::SETUO:  CondCode = ARMCC::VS; break;
1189  case ISD::SETUEQ: CondCode = ARMCC::EQ; CondCode2 = ARMCC::VS; break;
1190  case ISD::SETUGT: CondCode = ARMCC::HI; break;
1191  case ISD::SETUGE: CondCode = ARMCC::PL; break;
1192  case ISD::SETLT:
1193  case ISD::SETULT: CondCode = ARMCC::LT; break;
1194  case ISD::SETLE:
1195  case ISD::SETULE: CondCode = ARMCC::LE; break;
1196  case ISD::SETNE:
1197  case ISD::SETUNE: CondCode = ARMCC::NE; break;
1198  }
1199}
1200
1201//===----------------------------------------------------------------------===//
1202//                      Calling Convention Implementation
1203//===----------------------------------------------------------------------===//
1204
1205#include "ARMGenCallingConv.inc"
1206
1207/// CCAssignFnForNode - Selects the correct CCAssignFn for a the
1208/// given CallingConvention value.
1209CCAssignFn *ARMTargetLowering::CCAssignFnForNode(CallingConv::ID CC,
1210                                                 bool Return,
1211                                                 bool isVarArg) const {
1212  switch (CC) {
1213  default:
1214    llvm_unreachable("Unsupported calling convention");
1215  case CallingConv::Fast:
1216    if (Subtarget->hasVFP2() && !isVarArg) {
1217      if (!Subtarget->isAAPCS_ABI())
1218        return (Return ? RetFastCC_ARM_APCS : FastCC_ARM_APCS);
1219      // For AAPCS ABI targets, just use VFP variant of the calling convention.
1220      return (Return ? RetCC_ARM_AAPCS_VFP : CC_ARM_AAPCS_VFP);
1221    }
1222    // Fallthrough
1223  case CallingConv::C: {
1224    // Use target triple & subtarget features to do actual dispatch.
1225    if (!Subtarget->isAAPCS_ABI())
1226      return (Return ? RetCC_ARM_APCS : CC_ARM_APCS);
1227    else if (Subtarget->hasVFP2() &&
1228             getTargetMachine().Options.FloatABIType == FloatABI::Hard &&
1229             !isVarArg)
1230      return (Return ? RetCC_ARM_AAPCS_VFP : CC_ARM_AAPCS_VFP);
1231    return (Return ? RetCC_ARM_AAPCS : CC_ARM_AAPCS);
1232  }
1233  case CallingConv::ARM_AAPCS_VFP:
1234    if (!isVarArg)
1235      return (Return ? RetCC_ARM_AAPCS_VFP : CC_ARM_AAPCS_VFP);
1236    // Fallthrough
1237  case CallingConv::ARM_AAPCS:
1238    return (Return ? RetCC_ARM_AAPCS : CC_ARM_AAPCS);
1239  case CallingConv::ARM_APCS:
1240    return (Return ? RetCC_ARM_APCS : CC_ARM_APCS);
1241  case CallingConv::GHC:
1242    return (Return ? RetCC_ARM_APCS : CC_ARM_APCS_GHC);
1243  }
1244}
1245
1246/// LowerCallResult - Lower the result values of a call into the
1247/// appropriate copies out of appropriate physical registers.
1248SDValue
1249ARMTargetLowering::LowerCallResult(SDValue Chain, SDValue InFlag,
1250                                   CallingConv::ID CallConv, bool isVarArg,
1251                                   const SmallVectorImpl<ISD::InputArg> &Ins,
1252                                   SDLoc dl, SelectionDAG &DAG,
1253                                   SmallVectorImpl<SDValue> &InVals,
1254                                   bool isThisReturn, SDValue ThisVal) const {
1255
1256  // Assign locations to each value returned by this call.
1257  SmallVector<CCValAssign, 16> RVLocs;
1258  ARMCCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(),
1259                    getTargetMachine(), RVLocs, *DAG.getContext(), Call);
1260  CCInfo.AnalyzeCallResult(Ins,
1261                           CCAssignFnForNode(CallConv, /* Return*/ true,
1262                                             isVarArg));
1263
1264  // Copy all of the result registers out of their specified physreg.
1265  for (unsigned i = 0; i != RVLocs.size(); ++i) {
1266    CCValAssign VA = RVLocs[i];
1267
1268    // Pass 'this' value directly from the argument to return value, to avoid
1269    // reg unit interference
1270    if (i == 0 && isThisReturn) {
1271      assert(!VA.needsCustom() && VA.getLocVT() == MVT::i32 &&
1272             "unexpected return calling convention register assignment");
1273      InVals.push_back(ThisVal);
1274      continue;
1275    }
1276
1277    SDValue Val;
1278    if (VA.needsCustom()) {
1279      // Handle f64 or half of a v2f64.
1280      SDValue Lo = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), MVT::i32,
1281                                      InFlag);
1282      Chain = Lo.getValue(1);
1283      InFlag = Lo.getValue(2);
1284      VA = RVLocs[++i]; // skip ahead to next loc
1285      SDValue Hi = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), MVT::i32,
1286                                      InFlag);
1287      Chain = Hi.getValue(1);
1288      InFlag = Hi.getValue(2);
1289      Val = DAG.getNode(ARMISD::VMOVDRR, dl, MVT::f64, Lo, Hi);
1290
1291      if (VA.getLocVT() == MVT::v2f64) {
1292        SDValue Vec = DAG.getNode(ISD::UNDEF, dl, MVT::v2f64);
1293        Vec = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v2f64, Vec, Val,
1294                          DAG.getConstant(0, MVT::i32));
1295
1296        VA = RVLocs[++i]; // skip ahead to next loc
1297        Lo = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), MVT::i32, InFlag);
1298        Chain = Lo.getValue(1);
1299        InFlag = Lo.getValue(2);
1300        VA = RVLocs[++i]; // skip ahead to next loc
1301        Hi = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), MVT::i32, InFlag);
1302        Chain = Hi.getValue(1);
1303        InFlag = Hi.getValue(2);
1304        Val = DAG.getNode(ARMISD::VMOVDRR, dl, MVT::f64, Lo, Hi);
1305        Val = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v2f64, Vec, Val,
1306                          DAG.getConstant(1, MVT::i32));
1307      }
1308    } else {
1309      Val = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), VA.getLocVT(),
1310                               InFlag);
1311      Chain = Val.getValue(1);
1312      InFlag = Val.getValue(2);
1313    }
1314
1315    switch (VA.getLocInfo()) {
1316    default: llvm_unreachable("Unknown loc info!");
1317    case CCValAssign::Full: break;
1318    case CCValAssign::BCvt:
1319      Val = DAG.getNode(ISD::BITCAST, dl, VA.getValVT(), Val);
1320      break;
1321    }
1322
1323    InVals.push_back(Val);
1324  }
1325
1326  return Chain;
1327}
1328
1329/// LowerMemOpCallTo - Store the argument to the stack.
1330SDValue
1331ARMTargetLowering::LowerMemOpCallTo(SDValue Chain,
1332                                    SDValue StackPtr, SDValue Arg,
1333                                    SDLoc dl, SelectionDAG &DAG,
1334                                    const CCValAssign &VA,
1335                                    ISD::ArgFlagsTy Flags) const {
1336  unsigned LocMemOffset = VA.getLocMemOffset();
1337  SDValue PtrOff = DAG.getIntPtrConstant(LocMemOffset);
1338  PtrOff = DAG.getNode(ISD::ADD, dl, getPointerTy(), StackPtr, PtrOff);
1339  return DAG.getStore(Chain, dl, Arg, PtrOff,
1340                      MachinePointerInfo::getStack(LocMemOffset),
1341                      false, false, 0);
1342}
1343
1344void ARMTargetLowering::PassF64ArgInRegs(SDLoc dl, SelectionDAG &DAG,
1345                                         SDValue Chain, SDValue &Arg,
1346                                         RegsToPassVector &RegsToPass,
1347                                         CCValAssign &VA, CCValAssign &NextVA,
1348                                         SDValue &StackPtr,
1349                                         SmallVectorImpl<SDValue> &MemOpChains,
1350                                         ISD::ArgFlagsTy Flags) const {
1351
1352  SDValue fmrrd = DAG.getNode(ARMISD::VMOVRRD, dl,
1353                              DAG.getVTList(MVT::i32, MVT::i32), Arg);
1354  RegsToPass.push_back(std::make_pair(VA.getLocReg(), fmrrd));
1355
1356  if (NextVA.isRegLoc())
1357    RegsToPass.push_back(std::make_pair(NextVA.getLocReg(), fmrrd.getValue(1)));
1358  else {
1359    assert(NextVA.isMemLoc());
1360    if (StackPtr.getNode() == 0)
1361      StackPtr = DAG.getCopyFromReg(Chain, dl, ARM::SP, getPointerTy());
1362
1363    MemOpChains.push_back(LowerMemOpCallTo(Chain, StackPtr, fmrrd.getValue(1),
1364                                           dl, DAG, NextVA,
1365                                           Flags));
1366  }
1367}
1368
1369/// LowerCall - Lowering a call into a callseq_start <-
1370/// ARMISD:CALL <- callseq_end chain. Also add input and output parameter
1371/// nodes.
1372SDValue
1373ARMTargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI,
1374                             SmallVectorImpl<SDValue> &InVals) const {
1375  SelectionDAG &DAG                     = CLI.DAG;
1376  SDLoc &dl                          = CLI.DL;
1377  SmallVectorImpl<ISD::OutputArg> &Outs = CLI.Outs;
1378  SmallVectorImpl<SDValue> &OutVals     = CLI.OutVals;
1379  SmallVectorImpl<ISD::InputArg> &Ins   = CLI.Ins;
1380  SDValue Chain                         = CLI.Chain;
1381  SDValue Callee                        = CLI.Callee;
1382  bool &isTailCall                      = CLI.IsTailCall;
1383  CallingConv::ID CallConv              = CLI.CallConv;
1384  bool doesNotRet                       = CLI.DoesNotReturn;
1385  bool isVarArg                         = CLI.IsVarArg;
1386
1387  MachineFunction &MF = DAG.getMachineFunction();
1388  bool isStructRet    = (Outs.empty()) ? false : Outs[0].Flags.isSRet();
1389  bool isThisReturn   = false;
1390  bool isSibCall      = false;
1391
1392  // Disable tail calls if they're not supported.
1393  if (!Subtarget->supportsTailCall() || MF.getTarget().Options.DisableTailCalls)
1394    isTailCall = false;
1395
1396  if (isTailCall) {
1397    // Check if it's really possible to do a tail call.
1398    isTailCall = IsEligibleForTailCallOptimization(Callee, CallConv,
1399                    isVarArg, isStructRet, MF.getFunction()->hasStructRetAttr(),
1400                                                   Outs, OutVals, Ins, DAG);
1401    // We don't support GuaranteedTailCallOpt for ARM, only automatically
1402    // detected sibcalls.
1403    if (isTailCall) {
1404      ++NumTailCalls;
1405      isSibCall = true;
1406    }
1407  }
1408
1409  // Analyze operands of the call, assigning locations to each operand.
1410  SmallVector<CCValAssign, 16> ArgLocs;
1411  ARMCCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(),
1412                 getTargetMachine(), ArgLocs, *DAG.getContext(), Call);
1413  CCInfo.AnalyzeCallOperands(Outs,
1414                             CCAssignFnForNode(CallConv, /* Return*/ false,
1415                                               isVarArg));
1416
1417  // Get a count of how many bytes are to be pushed on the stack.
1418  unsigned NumBytes = CCInfo.getNextStackOffset();
1419
1420  // For tail calls, memory operands are available in our caller's stack.
1421  if (isSibCall)
1422    NumBytes = 0;
1423
1424  // Adjust the stack pointer for the new arguments...
1425  // These operations are automatically eliminated by the prolog/epilog pass
1426  if (!isSibCall)
1427    Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(NumBytes, true),
1428                                 dl);
1429
1430  SDValue StackPtr = DAG.getCopyFromReg(Chain, dl, ARM::SP, getPointerTy());
1431
1432  RegsToPassVector RegsToPass;
1433  SmallVector<SDValue, 8> MemOpChains;
1434
1435  // Walk the register/memloc assignments, inserting copies/loads.  In the case
1436  // of tail call optimization, arguments are handled later.
1437  for (unsigned i = 0, realArgIdx = 0, e = ArgLocs.size();
1438       i != e;
1439       ++i, ++realArgIdx) {
1440    CCValAssign &VA = ArgLocs[i];
1441    SDValue Arg = OutVals[realArgIdx];
1442    ISD::ArgFlagsTy Flags = Outs[realArgIdx].Flags;
1443    bool isByVal = Flags.isByVal();
1444
1445    // Promote the value if needed.
1446    switch (VA.getLocInfo()) {
1447    default: llvm_unreachable("Unknown loc info!");
1448    case CCValAssign::Full: break;
1449    case CCValAssign::SExt:
1450      Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), Arg);
1451      break;
1452    case CCValAssign::ZExt:
1453      Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, VA.getLocVT(), Arg);
1454      break;
1455    case CCValAssign::AExt:
1456      Arg = DAG.getNode(ISD::ANY_EXTEND, dl, VA.getLocVT(), Arg);
1457      break;
1458    case CCValAssign::BCvt:
1459      Arg = DAG.getNode(ISD::BITCAST, dl, VA.getLocVT(), Arg);
1460      break;
1461    }
1462
1463    // f64 and v2f64 might be passed in i32 pairs and must be split into pieces
1464    if (VA.needsCustom()) {
1465      if (VA.getLocVT() == MVT::v2f64) {
1466        SDValue Op0 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, Arg,
1467                                  DAG.getConstant(0, MVT::i32));
1468        SDValue Op1 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, Arg,
1469                                  DAG.getConstant(1, MVT::i32));
1470
1471        PassF64ArgInRegs(dl, DAG, Chain, Op0, RegsToPass,
1472                         VA, ArgLocs[++i], StackPtr, MemOpChains, Flags);
1473
1474        VA = ArgLocs[++i]; // skip ahead to next loc
1475        if (VA.isRegLoc()) {
1476          PassF64ArgInRegs(dl, DAG, Chain, Op1, RegsToPass,
1477                           VA, ArgLocs[++i], StackPtr, MemOpChains, Flags);
1478        } else {
1479          assert(VA.isMemLoc());
1480
1481          MemOpChains.push_back(LowerMemOpCallTo(Chain, StackPtr, Op1,
1482                                                 dl, DAG, VA, Flags));
1483        }
1484      } else {
1485        PassF64ArgInRegs(dl, DAG, Chain, Arg, RegsToPass, VA, ArgLocs[++i],
1486                         StackPtr, MemOpChains, Flags);
1487      }
1488    } else if (VA.isRegLoc()) {
1489      if (realArgIdx == 0 && Flags.isReturned() && Outs[0].VT == MVT::i32) {
1490        assert(VA.getLocVT() == MVT::i32 &&
1491               "unexpected calling convention register assignment");
1492        assert(!Ins.empty() && Ins[0].VT == MVT::i32 &&
1493               "unexpected use of 'returned'");
1494        isThisReturn = true;
1495      }
1496      RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
1497    } else if (isByVal) {
1498      assert(VA.isMemLoc());
1499      unsigned offset = 0;
1500
1501      // True if this byval aggregate will be split between registers
1502      // and memory.
1503      unsigned ByValArgsCount = CCInfo.getInRegsParamsCount();
1504      unsigned CurByValIdx = CCInfo.getInRegsParamsProceed();
1505
1506      if (CurByValIdx < ByValArgsCount) {
1507
1508        unsigned RegBegin, RegEnd;
1509        CCInfo.getInRegsParamInfo(CurByValIdx, RegBegin, RegEnd);
1510
1511        EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
1512        unsigned int i, j;
1513        for (i = 0, j = RegBegin; j < RegEnd; i++, j++) {
1514          SDValue Const = DAG.getConstant(4*i, MVT::i32);
1515          SDValue AddArg = DAG.getNode(ISD::ADD, dl, PtrVT, Arg, Const);
1516          SDValue Load = DAG.getLoad(PtrVT, dl, Chain, AddArg,
1517                                     MachinePointerInfo(),
1518                                     false, false, false,
1519                                     DAG.InferPtrAlignment(AddArg));
1520          MemOpChains.push_back(Load.getValue(1));
1521          RegsToPass.push_back(std::make_pair(j, Load));
1522        }
1523
1524        // If parameter size outsides register area, "offset" value
1525        // helps us to calculate stack slot for remained part properly.
1526        offset = RegEnd - RegBegin;
1527
1528        CCInfo.nextInRegsParam();
1529      }
1530
1531      if (Flags.getByValSize() > 4*offset) {
1532        unsigned LocMemOffset = VA.getLocMemOffset();
1533        SDValue StkPtrOff = DAG.getIntPtrConstant(LocMemOffset);
1534        SDValue Dst = DAG.getNode(ISD::ADD, dl, getPointerTy(), StackPtr,
1535                                  StkPtrOff);
1536        SDValue SrcOffset = DAG.getIntPtrConstant(4*offset);
1537        SDValue Src = DAG.getNode(ISD::ADD, dl, getPointerTy(), Arg, SrcOffset);
1538        SDValue SizeNode = DAG.getConstant(Flags.getByValSize() - 4*offset,
1539                                           MVT::i32);
1540        SDValue AlignNode = DAG.getConstant(Flags.getByValAlign(), MVT::i32);
1541
1542        SDVTList VTs = DAG.getVTList(MVT::Other, MVT::Glue);
1543        SDValue Ops[] = { Chain, Dst, Src, SizeNode, AlignNode};
1544        MemOpChains.push_back(DAG.getNode(ARMISD::COPY_STRUCT_BYVAL, dl, VTs,
1545                                          Ops, array_lengthof(Ops)));
1546      }
1547    } else if (!isSibCall) {
1548      assert(VA.isMemLoc());
1549
1550      MemOpChains.push_back(LowerMemOpCallTo(Chain, StackPtr, Arg,
1551                                             dl, DAG, VA, Flags));
1552    }
1553  }
1554
1555  if (!MemOpChains.empty())
1556    Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
1557                        &MemOpChains[0], MemOpChains.size());
1558
1559  // Build a sequence of copy-to-reg nodes chained together with token chain
1560  // and flag operands which copy the outgoing args into the appropriate regs.
1561  SDValue InFlag;
1562  // Tail call byval lowering might overwrite argument registers so in case of
1563  // tail call optimization the copies to registers are lowered later.
1564  if (!isTailCall)
1565    for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
1566      Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
1567                               RegsToPass[i].second, InFlag);
1568      InFlag = Chain.getValue(1);
1569    }
1570
1571  // For tail calls lower the arguments to the 'real' stack slot.
1572  if (isTailCall) {
1573    // Force all the incoming stack arguments to be loaded from the stack
1574    // before any new outgoing arguments are stored to the stack, because the
1575    // outgoing stack slots may alias the incoming argument stack slots, and
1576    // the alias isn't otherwise explicit. This is slightly more conservative
1577    // than necessary, because it means that each store effectively depends
1578    // on every argument instead of just those arguments it would clobber.
1579
1580    // Do not flag preceding copytoreg stuff together with the following stuff.
1581    InFlag = SDValue();
1582    for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
1583      Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
1584                               RegsToPass[i].second, InFlag);
1585      InFlag = Chain.getValue(1);
1586    }
1587    InFlag = SDValue();
1588  }
1589
1590  // If the callee is a GlobalAddress/ExternalSymbol node (quite common, every
1591  // direct call is) turn it into a TargetGlobalAddress/TargetExternalSymbol
1592  // node so that legalize doesn't hack it.
1593  bool isDirect = false;
1594  bool isARMFunc = false;
1595  bool isLocalARMFunc = false;
1596  ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
1597
1598  if (EnableARMLongCalls) {
1599    assert (getTargetMachine().getRelocationModel() == Reloc::Static
1600            && "long-calls with non-static relocation model!");
1601    // Handle a global address or an external symbol. If it's not one of
1602    // those, the target's already in a register, so we don't need to do
1603    // anything extra.
1604    if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) {
1605      const GlobalValue *GV = G->getGlobal();
1606      // Create a constant pool entry for the callee address
1607      unsigned ARMPCLabelIndex = AFI->createPICLabelUId();
1608      ARMConstantPoolValue *CPV =
1609        ARMConstantPoolConstant::Create(GV, ARMPCLabelIndex, ARMCP::CPValue, 0);
1610
1611      // Get the address of the callee into a register
1612      SDValue CPAddr = DAG.getTargetConstantPool(CPV, getPointerTy(), 4);
1613      CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr);
1614      Callee = DAG.getLoad(getPointerTy(), dl,
1615                           DAG.getEntryNode(), CPAddr,
1616                           MachinePointerInfo::getConstantPool(),
1617                           false, false, false, 0);
1618    } else if (ExternalSymbolSDNode *S=dyn_cast<ExternalSymbolSDNode>(Callee)) {
1619      const char *Sym = S->getSymbol();
1620
1621      // Create a constant pool entry for the callee address
1622      unsigned ARMPCLabelIndex = AFI->createPICLabelUId();
1623      ARMConstantPoolValue *CPV =
1624        ARMConstantPoolSymbol::Create(*DAG.getContext(), Sym,
1625                                      ARMPCLabelIndex, 0);
1626      // Get the address of the callee into a register
1627      SDValue CPAddr = DAG.getTargetConstantPool(CPV, getPointerTy(), 4);
1628      CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr);
1629      Callee = DAG.getLoad(getPointerTy(), dl,
1630                           DAG.getEntryNode(), CPAddr,
1631                           MachinePointerInfo::getConstantPool(),
1632                           false, false, false, 0);
1633    }
1634  } else if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) {
1635    const GlobalValue *GV = G->getGlobal();
1636    isDirect = true;
1637    bool isExt = GV->isDeclaration() || GV->isWeakForLinker();
1638    bool isStub = (isExt && Subtarget->isTargetMachO()) &&
1639                   getTargetMachine().getRelocationModel() != Reloc::Static;
1640    isARMFunc = !Subtarget->isThumb() || isStub;
1641    // ARM call to a local ARM function is predicable.
1642    isLocalARMFunc = !Subtarget->isThumb() && (!isExt || !ARMInterworking);
1643    // tBX takes a register source operand.
1644    if (isStub && Subtarget->isThumb1Only() && !Subtarget->hasV5TOps()) {
1645      assert(Subtarget->isTargetMachO() && "WrapperPIC use on non-MachO?");
1646      Callee = DAG.getNode(ARMISD::WrapperPIC, dl, getPointerTy(),
1647                           DAG.getTargetGlobalAddress(GV, dl, getPointerTy()));
1648    } else {
1649      // On ELF targets for PIC code, direct calls should go through the PLT
1650      unsigned OpFlags = 0;
1651      if (Subtarget->isTargetELF() &&
1652          getTargetMachine().getRelocationModel() == Reloc::PIC_)
1653        OpFlags = ARMII::MO_PLT;
1654      Callee = DAG.getTargetGlobalAddress(GV, dl, getPointerTy(), 0, OpFlags);
1655    }
1656  } else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee)) {
1657    isDirect = true;
1658    bool isStub = Subtarget->isTargetMachO() &&
1659                  getTargetMachine().getRelocationModel() != Reloc::Static;
1660    isARMFunc = !Subtarget->isThumb() || isStub;
1661    // tBX takes a register source operand.
1662    const char *Sym = S->getSymbol();
1663    if (isARMFunc && Subtarget->isThumb1Only() && !Subtarget->hasV5TOps()) {
1664      unsigned ARMPCLabelIndex = AFI->createPICLabelUId();
1665      ARMConstantPoolValue *CPV =
1666        ARMConstantPoolSymbol::Create(*DAG.getContext(), Sym,
1667                                      ARMPCLabelIndex, 4);
1668      SDValue CPAddr = DAG.getTargetConstantPool(CPV, getPointerTy(), 4);
1669      CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr);
1670      Callee = DAG.getLoad(getPointerTy(), dl,
1671                           DAG.getEntryNode(), CPAddr,
1672                           MachinePointerInfo::getConstantPool(),
1673                           false, false, false, 0);
1674      SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex, MVT::i32);
1675      Callee = DAG.getNode(ARMISD::PIC_ADD, dl,
1676                           getPointerTy(), Callee, PICLabel);
1677    } else {
1678      unsigned OpFlags = 0;
1679      // On ELF targets for PIC code, direct calls should go through the PLT
1680      if (Subtarget->isTargetELF() &&
1681                  getTargetMachine().getRelocationModel() == Reloc::PIC_)
1682        OpFlags = ARMII::MO_PLT;
1683      Callee = DAG.getTargetExternalSymbol(Sym, getPointerTy(), OpFlags);
1684    }
1685  }
1686
1687  // FIXME: handle tail calls differently.
1688  unsigned CallOpc;
1689  bool HasMinSizeAttr = Subtarget->isMinSize();
1690  if (Subtarget->isThumb()) {
1691    if ((!isDirect || isARMFunc) && !Subtarget->hasV5TOps())
1692      CallOpc = ARMISD::CALL_NOLINK;
1693    else
1694      CallOpc = isARMFunc ? ARMISD::CALL : ARMISD::tCALL;
1695  } else {
1696    if (!isDirect && !Subtarget->hasV5TOps())
1697      CallOpc = ARMISD::CALL_NOLINK;
1698    else if (doesNotRet && isDirect && Subtarget->hasRAS() &&
1699               // Emit regular call when code size is the priority
1700               !HasMinSizeAttr)
1701      // "mov lr, pc; b _foo" to avoid confusing the RSP
1702      CallOpc = ARMISD::CALL_NOLINK;
1703    else
1704      CallOpc = isLocalARMFunc ? ARMISD::CALL_PRED : ARMISD::CALL;
1705  }
1706
1707  std::vector<SDValue> Ops;
1708  Ops.push_back(Chain);
1709  Ops.push_back(Callee);
1710
1711  // Add argument registers to the end of the list so that they are known live
1712  // into the call.
1713  for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i)
1714    Ops.push_back(DAG.getRegister(RegsToPass[i].first,
1715                                  RegsToPass[i].second.getValueType()));
1716
1717  // Add a register mask operand representing the call-preserved registers.
1718  if (!isTailCall) {
1719    const uint32_t *Mask;
1720    const TargetRegisterInfo *TRI = getTargetMachine().getRegisterInfo();
1721    const ARMBaseRegisterInfo *ARI = static_cast<const ARMBaseRegisterInfo*>(TRI);
1722    if (isThisReturn) {
1723      // For 'this' returns, use the R0-preserving mask if applicable
1724      Mask = ARI->getThisReturnPreservedMask(CallConv);
1725      if (!Mask) {
1726        // Set isThisReturn to false if the calling convention is not one that
1727        // allows 'returned' to be modeled in this way, so LowerCallResult does
1728        // not try to pass 'this' straight through
1729        isThisReturn = false;
1730        Mask = ARI->getCallPreservedMask(CallConv);
1731      }
1732    } else
1733      Mask = ARI->getCallPreservedMask(CallConv);
1734
1735    assert(Mask && "Missing call preserved mask for calling convention");
1736    Ops.push_back(DAG.getRegisterMask(Mask));
1737  }
1738
1739  if (InFlag.getNode())
1740    Ops.push_back(InFlag);
1741
1742  SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
1743  if (isTailCall)
1744    return DAG.getNode(ARMISD::TC_RETURN, dl, NodeTys, &Ops[0], Ops.size());
1745
1746  // Returns a chain and a flag for retval copy to use.
1747  Chain = DAG.getNode(CallOpc, dl, NodeTys, &Ops[0], Ops.size());
1748  InFlag = Chain.getValue(1);
1749
1750  Chain = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(NumBytes, true),
1751                             DAG.getIntPtrConstant(0, true), InFlag, dl);
1752  if (!Ins.empty())
1753    InFlag = Chain.getValue(1);
1754
1755  // Handle result values, copying them out of physregs into vregs that we
1756  // return.
1757  return LowerCallResult(Chain, InFlag, CallConv, isVarArg, Ins, dl, DAG,
1758                         InVals, isThisReturn,
1759                         isThisReturn ? OutVals[0] : SDValue());
1760}
1761
1762/// HandleByVal - Every parameter *after* a byval parameter is passed
1763/// on the stack.  Remember the next parameter register to allocate,
1764/// and then confiscate the rest of the parameter registers to insure
1765/// this.
1766void
1767ARMTargetLowering::HandleByVal(
1768    CCState *State, unsigned &size, unsigned Align) const {
1769  unsigned reg = State->AllocateReg(GPRArgRegs, 4);
1770  assert((State->getCallOrPrologue() == Prologue ||
1771          State->getCallOrPrologue() == Call) &&
1772         "unhandled ParmContext");
1773
1774  if ((ARM::R0 <= reg) && (reg <= ARM::R3)) {
1775    if (Subtarget->isAAPCS_ABI() && Align > 4) {
1776      unsigned AlignInRegs = Align / 4;
1777      unsigned Waste = (ARM::R4 - reg) % AlignInRegs;
1778      for (unsigned i = 0; i < Waste; ++i)
1779        reg = State->AllocateReg(GPRArgRegs, 4);
1780    }
1781    if (reg != 0) {
1782      unsigned excess = 4 * (ARM::R4 - reg);
1783
1784      // Special case when NSAA != SP and parameter size greater than size of
1785      // all remained GPR regs. In that case we can't split parameter, we must
1786      // send it to stack. We also must set NCRN to R4, so waste all
1787      // remained registers.
1788      const unsigned NSAAOffset = State->getNextStackOffset();
1789      if (Subtarget->isAAPCS_ABI() && NSAAOffset != 0 && size > excess) {
1790        while (State->AllocateReg(GPRArgRegs, 4))
1791          ;
1792        return;
1793      }
1794
1795      // First register for byval parameter is the first register that wasn't
1796      // allocated before this method call, so it would be "reg".
1797      // If parameter is small enough to be saved in range [reg, r4), then
1798      // the end (first after last) register would be reg + param-size-in-regs,
1799      // else parameter would be splitted between registers and stack,
1800      // end register would be r4 in this case.
1801      unsigned ByValRegBegin = reg;
1802      unsigned ByValRegEnd = (size < excess) ? reg + size/4 : (unsigned)ARM::R4;
1803      State->addInRegsParamInfo(ByValRegBegin, ByValRegEnd);
1804      // Note, first register is allocated in the beginning of function already,
1805      // allocate remained amount of registers we need.
1806      for (unsigned i = reg+1; i != ByValRegEnd; ++i)
1807        State->AllocateReg(GPRArgRegs, 4);
1808      // A byval parameter that is split between registers and memory needs its
1809      // size truncated here.
1810      // In the case where the entire structure fits in registers, we set the
1811      // size in memory to zero.
1812      if (size < excess)
1813        size = 0;
1814      else
1815        size -= excess;
1816    }
1817  }
1818}
1819
1820/// MatchingStackOffset - Return true if the given stack call argument is
1821/// already available in the same position (relatively) of the caller's
1822/// incoming argument stack.
1823static
1824bool MatchingStackOffset(SDValue Arg, unsigned Offset, ISD::ArgFlagsTy Flags,
1825                         MachineFrameInfo *MFI, const MachineRegisterInfo *MRI,
1826                         const TargetInstrInfo *TII) {
1827  unsigned Bytes = Arg.getValueType().getSizeInBits() / 8;
1828  int FI = INT_MAX;
1829  if (Arg.getOpcode() == ISD::CopyFromReg) {
1830    unsigned VR = cast<RegisterSDNode>(Arg.getOperand(1))->getReg();
1831    if (!TargetRegisterInfo::isVirtualRegister(VR))
1832      return false;
1833    MachineInstr *Def = MRI->getVRegDef(VR);
1834    if (!Def)
1835      return false;
1836    if (!Flags.isByVal()) {
1837      if (!TII->isLoadFromStackSlot(Def, FI))
1838        return false;
1839    } else {
1840      return false;
1841    }
1842  } else if (LoadSDNode *Ld = dyn_cast<LoadSDNode>(Arg)) {
1843    if (Flags.isByVal())
1844      // ByVal argument is passed in as a pointer but it's now being
1845      // dereferenced. e.g.
1846      // define @foo(%struct.X* %A) {
1847      //   tail call @bar(%struct.X* byval %A)
1848      // }
1849      return false;
1850    SDValue Ptr = Ld->getBasePtr();
1851    FrameIndexSDNode *FINode = dyn_cast<FrameIndexSDNode>(Ptr);
1852    if (!FINode)
1853      return false;
1854    FI = FINode->getIndex();
1855  } else
1856    return false;
1857
1858  assert(FI != INT_MAX);
1859  if (!MFI->isFixedObjectIndex(FI))
1860    return false;
1861  return Offset == MFI->getObjectOffset(FI) && Bytes == MFI->getObjectSize(FI);
1862}
1863
1864/// IsEligibleForTailCallOptimization - Check whether the call is eligible
1865/// for tail call optimization. Targets which want to do tail call
1866/// optimization should implement this function.
1867bool
1868ARMTargetLowering::IsEligibleForTailCallOptimization(SDValue Callee,
1869                                                     CallingConv::ID CalleeCC,
1870                                                     bool isVarArg,
1871                                                     bool isCalleeStructRet,
1872                                                     bool isCallerStructRet,
1873                                    const SmallVectorImpl<ISD::OutputArg> &Outs,
1874                                    const SmallVectorImpl<SDValue> &OutVals,
1875                                    const SmallVectorImpl<ISD::InputArg> &Ins,
1876                                                     SelectionDAG& DAG) const {
1877  const Function *CallerF = DAG.getMachineFunction().getFunction();
1878  CallingConv::ID CallerCC = CallerF->getCallingConv();
1879  bool CCMatch = CallerCC == CalleeCC;
1880
1881  // Look for obvious safe cases to perform tail call optimization that do not
1882  // require ABI changes. This is what gcc calls sibcall.
1883
1884  // Do not sibcall optimize vararg calls unless the call site is not passing
1885  // any arguments.
1886  if (isVarArg && !Outs.empty())
1887    return false;
1888
1889  // Exception-handling functions need a special set of instructions to indicate
1890  // a return to the hardware. Tail-calling another function would probably
1891  // break this.
1892  if (CallerF->hasFnAttribute("interrupt"))
1893    return false;
1894
1895  // Also avoid sibcall optimization if either caller or callee uses struct
1896  // return semantics.
1897  if (isCalleeStructRet || isCallerStructRet)
1898    return false;
1899
1900  // FIXME: Completely disable sibcall for Thumb1 since Thumb1RegisterInfo::
1901  // emitEpilogue is not ready for them. Thumb tail calls also use t2B, as
1902  // the Thumb1 16-bit unconditional branch doesn't have sufficient relocation
1903  // support in the assembler and linker to be used. This would need to be
1904  // fixed to fully support tail calls in Thumb1.
1905  //
1906  // Doing this is tricky, since the LDM/POP instruction on Thumb doesn't take
1907  // LR.  This means if we need to reload LR, it takes an extra instructions,
1908  // which outweighs the value of the tail call; but here we don't know yet
1909  // whether LR is going to be used.  Probably the right approach is to
1910  // generate the tail call here and turn it back into CALL/RET in
1911  // emitEpilogue if LR is used.
1912
1913  // Thumb1 PIC calls to external symbols use BX, so they can be tail calls,
1914  // but we need to make sure there are enough registers; the only valid
1915  // registers are the 4 used for parameters.  We don't currently do this
1916  // case.
1917  if (Subtarget->isThumb1Only())
1918    return false;
1919
1920  // If the calling conventions do not match, then we'd better make sure the
1921  // results are returned in the same way as what the caller expects.
1922  if (!CCMatch) {
1923    SmallVector<CCValAssign, 16> RVLocs1;
1924    ARMCCState CCInfo1(CalleeCC, false, DAG.getMachineFunction(),
1925                       getTargetMachine(), RVLocs1, *DAG.getContext(), Call);
1926    CCInfo1.AnalyzeCallResult(Ins, CCAssignFnForNode(CalleeCC, true, isVarArg));
1927
1928    SmallVector<CCValAssign, 16> RVLocs2;
1929    ARMCCState CCInfo2(CallerCC, false, DAG.getMachineFunction(),
1930                       getTargetMachine(), RVLocs2, *DAG.getContext(), Call);
1931    CCInfo2.AnalyzeCallResult(Ins, CCAssignFnForNode(CallerCC, true, isVarArg));
1932
1933    if (RVLocs1.size() != RVLocs2.size())
1934      return false;
1935    for (unsigned i = 0, e = RVLocs1.size(); i != e; ++i) {
1936      if (RVLocs1[i].isRegLoc() != RVLocs2[i].isRegLoc())
1937        return false;
1938      if (RVLocs1[i].getLocInfo() != RVLocs2[i].getLocInfo())
1939        return false;
1940      if (RVLocs1[i].isRegLoc()) {
1941        if (RVLocs1[i].getLocReg() != RVLocs2[i].getLocReg())
1942          return false;
1943      } else {
1944        if (RVLocs1[i].getLocMemOffset() != RVLocs2[i].getLocMemOffset())
1945          return false;
1946      }
1947    }
1948  }
1949
1950  // If Caller's vararg or byval argument has been split between registers and
1951  // stack, do not perform tail call, since part of the argument is in caller's
1952  // local frame.
1953  const ARMFunctionInfo *AFI_Caller = DAG.getMachineFunction().
1954                                      getInfo<ARMFunctionInfo>();
1955  if (AFI_Caller->getArgRegsSaveSize())
1956    return false;
1957
1958  // If the callee takes no arguments then go on to check the results of the
1959  // call.
1960  if (!Outs.empty()) {
1961    // Check if stack adjustment is needed. For now, do not do this if any
1962    // argument is passed on the stack.
1963    SmallVector<CCValAssign, 16> ArgLocs;
1964    ARMCCState CCInfo(CalleeCC, isVarArg, DAG.getMachineFunction(),
1965                      getTargetMachine(), ArgLocs, *DAG.getContext(), Call);
1966    CCInfo.AnalyzeCallOperands(Outs,
1967                               CCAssignFnForNode(CalleeCC, false, isVarArg));
1968    if (CCInfo.getNextStackOffset()) {
1969      MachineFunction &MF = DAG.getMachineFunction();
1970
1971      // Check if the arguments are already laid out in the right way as
1972      // the caller's fixed stack objects.
1973      MachineFrameInfo *MFI = MF.getFrameInfo();
1974      const MachineRegisterInfo *MRI = &MF.getRegInfo();
1975      const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
1976      for (unsigned i = 0, realArgIdx = 0, e = ArgLocs.size();
1977           i != e;
1978           ++i, ++realArgIdx) {
1979        CCValAssign &VA = ArgLocs[i];
1980        EVT RegVT = VA.getLocVT();
1981        SDValue Arg = OutVals[realArgIdx];
1982        ISD::ArgFlagsTy Flags = Outs[realArgIdx].Flags;
1983        if (VA.getLocInfo() == CCValAssign::Indirect)
1984          return false;
1985        if (VA.needsCustom()) {
1986          // f64 and vector types are split into multiple registers or
1987          // register/stack-slot combinations.  The types will not match
1988          // the registers; give up on memory f64 refs until we figure
1989          // out what to do about this.
1990          if (!VA.isRegLoc())
1991            return false;
1992          if (!ArgLocs[++i].isRegLoc())
1993            return false;
1994          if (RegVT == MVT::v2f64) {
1995            if (!ArgLocs[++i].isRegLoc())
1996              return false;
1997            if (!ArgLocs[++i].isRegLoc())
1998              return false;
1999          }
2000        } else if (!VA.isRegLoc()) {
2001          if (!MatchingStackOffset(Arg, VA.getLocMemOffset(), Flags,
2002                                   MFI, MRI, TII))
2003            return false;
2004        }
2005      }
2006    }
2007  }
2008
2009  return true;
2010}
2011
2012bool
2013ARMTargetLowering::CanLowerReturn(CallingConv::ID CallConv,
2014                                  MachineFunction &MF, bool isVarArg,
2015                                  const SmallVectorImpl<ISD::OutputArg> &Outs,
2016                                  LLVMContext &Context) const {
2017  SmallVector<CCValAssign, 16> RVLocs;
2018  CCState CCInfo(CallConv, isVarArg, MF, getTargetMachine(), RVLocs, Context);
2019  return CCInfo.CheckReturn(Outs, CCAssignFnForNode(CallConv, /*Return=*/true,
2020                                                    isVarArg));
2021}
2022
2023static SDValue LowerInterruptReturn(SmallVectorImpl<SDValue> &RetOps,
2024                                    SDLoc DL, SelectionDAG &DAG) {
2025  const MachineFunction &MF = DAG.getMachineFunction();
2026  const Function *F = MF.getFunction();
2027
2028  StringRef IntKind = F->getFnAttribute("interrupt").getValueAsString();
2029
2030  // See ARM ARM v7 B1.8.3. On exception entry LR is set to a possibly offset
2031  // version of the "preferred return address". These offsets affect the return
2032  // instruction if this is a return from PL1 without hypervisor extensions.
2033  //    IRQ/FIQ: +4     "subs pc, lr, #4"
2034  //    SWI:     0      "subs pc, lr, #0"
2035  //    ABORT:   +4     "subs pc, lr, #4"
2036  //    UNDEF:   +4/+2  "subs pc, lr, #0"
2037  // UNDEF varies depending on where the exception came from ARM or Thumb
2038  // mode. Alongside GCC, we throw our hands up in disgust and pretend it's 0.
2039
2040  int64_t LROffset;
2041  if (IntKind == "" || IntKind == "IRQ" || IntKind == "FIQ" ||
2042      IntKind == "ABORT")
2043    LROffset = 4;
2044  else if (IntKind == "SWI" || IntKind == "UNDEF")
2045    LROffset = 0;
2046  else
2047    report_fatal_error("Unsupported interrupt attribute. If present, value "
2048                       "must be one of: IRQ, FIQ, SWI, ABORT or UNDEF");
2049
2050  RetOps.insert(RetOps.begin() + 1, DAG.getConstant(LROffset, MVT::i32, false));
2051
2052  return DAG.getNode(ARMISD::INTRET_FLAG, DL, MVT::Other,
2053                     RetOps.data(), RetOps.size());
2054}
2055
2056SDValue
2057ARMTargetLowering::LowerReturn(SDValue Chain,
2058                               CallingConv::ID CallConv, bool isVarArg,
2059                               const SmallVectorImpl<ISD::OutputArg> &Outs,
2060                               const SmallVectorImpl<SDValue> &OutVals,
2061                               SDLoc dl, SelectionDAG &DAG) const {
2062
2063  // CCValAssign - represent the assignment of the return value to a location.
2064  SmallVector<CCValAssign, 16> RVLocs;
2065
2066  // CCState - Info about the registers and stack slots.
2067  ARMCCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(),
2068                    getTargetMachine(), RVLocs, *DAG.getContext(), Call);
2069
2070  // Analyze outgoing return values.
2071  CCInfo.AnalyzeReturn(Outs, CCAssignFnForNode(CallConv, /* Return */ true,
2072                                               isVarArg));
2073
2074  SDValue Flag;
2075  SmallVector<SDValue, 4> RetOps;
2076  RetOps.push_back(Chain); // Operand #0 = Chain (updated below)
2077
2078  // Copy the result values into the output registers.
2079  for (unsigned i = 0, realRVLocIdx = 0;
2080       i != RVLocs.size();
2081       ++i, ++realRVLocIdx) {
2082    CCValAssign &VA = RVLocs[i];
2083    assert(VA.isRegLoc() && "Can only return in registers!");
2084
2085    SDValue Arg = OutVals[realRVLocIdx];
2086
2087    switch (VA.getLocInfo()) {
2088    default: llvm_unreachable("Unknown loc info!");
2089    case CCValAssign::Full: break;
2090    case CCValAssign::BCvt:
2091      Arg = DAG.getNode(ISD::BITCAST, dl, VA.getLocVT(), Arg);
2092      break;
2093    }
2094
2095    if (VA.needsCustom()) {
2096      if (VA.getLocVT() == MVT::v2f64) {
2097        // Extract the first half and return it in two registers.
2098        SDValue Half = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, Arg,
2099                                   DAG.getConstant(0, MVT::i32));
2100        SDValue HalfGPRs = DAG.getNode(ARMISD::VMOVRRD, dl,
2101                                       DAG.getVTList(MVT::i32, MVT::i32), Half);
2102
2103        Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), HalfGPRs, Flag);
2104        Flag = Chain.getValue(1);
2105        RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT()));
2106        VA = RVLocs[++i]; // skip ahead to next loc
2107        Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(),
2108                                 HalfGPRs.getValue(1), Flag);
2109        Flag = Chain.getValue(1);
2110        RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT()));
2111        VA = RVLocs[++i]; // skip ahead to next loc
2112
2113        // Extract the 2nd half and fall through to handle it as an f64 value.
2114        Arg = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, Arg,
2115                          DAG.getConstant(1, MVT::i32));
2116      }
2117      // Legalize ret f64 -> ret 2 x i32.  We always have fmrrd if f64 is
2118      // available.
2119      SDValue fmrrd = DAG.getNode(ARMISD::VMOVRRD, dl,
2120                                  DAG.getVTList(MVT::i32, MVT::i32), &Arg, 1);
2121      Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), fmrrd, Flag);
2122      Flag = Chain.getValue(1);
2123      RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT()));
2124      VA = RVLocs[++i]; // skip ahead to next loc
2125      Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), fmrrd.getValue(1),
2126                               Flag);
2127    } else
2128      Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), Arg, Flag);
2129
2130    // Guarantee that all emitted copies are
2131    // stuck together, avoiding something bad.
2132    Flag = Chain.getValue(1);
2133    RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT()));
2134  }
2135
2136  // Update chain and glue.
2137  RetOps[0] = Chain;
2138  if (Flag.getNode())
2139    RetOps.push_back(Flag);
2140
2141  // CPUs which aren't M-class use a special sequence to return from
2142  // exceptions (roughly, any instruction setting pc and cpsr simultaneously,
2143  // though we use "subs pc, lr, #N").
2144  //
2145  // M-class CPUs actually use a normal return sequence with a special
2146  // (hardware-provided) value in LR, so the normal code path works.
2147  if (DAG.getMachineFunction().getFunction()->hasFnAttribute("interrupt") &&
2148      !Subtarget->isMClass()) {
2149    if (Subtarget->isThumb1Only())
2150      report_fatal_error("interrupt attribute is not supported in Thumb1");
2151    return LowerInterruptReturn(RetOps, dl, DAG);
2152  }
2153
2154  return DAG.getNode(ARMISD::RET_FLAG, dl, MVT::Other,
2155                     RetOps.data(), RetOps.size());
2156}
2157
2158bool ARMTargetLowering::isUsedByReturnOnly(SDNode *N, SDValue &Chain) const {
2159  if (N->getNumValues() != 1)
2160    return false;
2161  if (!N->hasNUsesOfValue(1, 0))
2162    return false;
2163
2164  SDValue TCChain = Chain;
2165  SDNode *Copy = *N->use_begin();
2166  if (Copy->getOpcode() == ISD::CopyToReg) {
2167    // If the copy has a glue operand, we conservatively assume it isn't safe to
2168    // perform a tail call.
2169    if (Copy->getOperand(Copy->getNumOperands()-1).getValueType() == MVT::Glue)
2170      return false;
2171    TCChain = Copy->getOperand(0);
2172  } else if (Copy->getOpcode() == ARMISD::VMOVRRD) {
2173    SDNode *VMov = Copy;
2174    // f64 returned in a pair of GPRs.
2175    SmallPtrSet<SDNode*, 2> Copies;
2176    for (SDNode::use_iterator UI = VMov->use_begin(), UE = VMov->use_end();
2177         UI != UE; ++UI) {
2178      if (UI->getOpcode() != ISD::CopyToReg)
2179        return false;
2180      Copies.insert(*UI);
2181    }
2182    if (Copies.size() > 2)
2183      return false;
2184
2185    for (SDNode::use_iterator UI = VMov->use_begin(), UE = VMov->use_end();
2186         UI != UE; ++UI) {
2187      SDValue UseChain = UI->getOperand(0);
2188      if (Copies.count(UseChain.getNode()))
2189        // Second CopyToReg
2190        Copy = *UI;
2191      else
2192        // First CopyToReg
2193        TCChain = UseChain;
2194    }
2195  } else if (Copy->getOpcode() == ISD::BITCAST) {
2196    // f32 returned in a single GPR.
2197    if (!Copy->hasOneUse())
2198      return false;
2199    Copy = *Copy->use_begin();
2200    if (Copy->getOpcode() != ISD::CopyToReg || !Copy->hasNUsesOfValue(1, 0))
2201      return false;
2202    TCChain = Copy->getOperand(0);
2203  } else {
2204    return false;
2205  }
2206
2207  bool HasRet = false;
2208  for (SDNode::use_iterator UI = Copy->use_begin(), UE = Copy->use_end();
2209       UI != UE; ++UI) {
2210    if (UI->getOpcode() != ARMISD::RET_FLAG &&
2211        UI->getOpcode() != ARMISD::INTRET_FLAG)
2212      return false;
2213    HasRet = true;
2214  }
2215
2216  if (!HasRet)
2217    return false;
2218
2219  Chain = TCChain;
2220  return true;
2221}
2222
2223bool ARMTargetLowering::mayBeEmittedAsTailCall(CallInst *CI) const {
2224  if (!Subtarget->supportsTailCall())
2225    return false;
2226
2227  if (!CI->isTailCall() || getTargetMachine().Options.DisableTailCalls)
2228    return false;
2229
2230  return !Subtarget->isThumb1Only();
2231}
2232
2233// ConstantPool, JumpTable, GlobalAddress, and ExternalSymbol are lowered as
2234// their target counterpart wrapped in the ARMISD::Wrapper node. Suppose N is
2235// one of the above mentioned nodes. It has to be wrapped because otherwise
2236// Select(N) returns N. So the raw TargetGlobalAddress nodes, etc. can only
2237// be used to form addressing mode. These wrapped nodes will be selected
2238// into MOVi.
2239static SDValue LowerConstantPool(SDValue Op, SelectionDAG &DAG) {
2240  EVT PtrVT = Op.getValueType();
2241  // FIXME there is no actual debug info here
2242  SDLoc dl(Op);
2243  ConstantPoolSDNode *CP = cast<ConstantPoolSDNode>(Op);
2244  SDValue Res;
2245  if (CP->isMachineConstantPoolEntry())
2246    Res = DAG.getTargetConstantPool(CP->getMachineCPVal(), PtrVT,
2247                                    CP->getAlignment());
2248  else
2249    Res = DAG.getTargetConstantPool(CP->getConstVal(), PtrVT,
2250                                    CP->getAlignment());
2251  return DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, Res);
2252}
2253
2254unsigned ARMTargetLowering::getJumpTableEncoding() const {
2255  return MachineJumpTableInfo::EK_Inline;
2256}
2257
2258SDValue ARMTargetLowering::LowerBlockAddress(SDValue Op,
2259                                             SelectionDAG &DAG) const {
2260  MachineFunction &MF = DAG.getMachineFunction();
2261  ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
2262  unsigned ARMPCLabelIndex = 0;
2263  SDLoc DL(Op);
2264  EVT PtrVT = getPointerTy();
2265  const BlockAddress *BA = cast<BlockAddressSDNode>(Op)->getBlockAddress();
2266  Reloc::Model RelocM = getTargetMachine().getRelocationModel();
2267  SDValue CPAddr;
2268  if (RelocM == Reloc::Static) {
2269    CPAddr = DAG.getTargetConstantPool(BA, PtrVT, 4);
2270  } else {
2271    unsigned PCAdj = Subtarget->isThumb() ? 4 : 8;
2272    ARMPCLabelIndex = AFI->createPICLabelUId();
2273    ARMConstantPoolValue *CPV =
2274      ARMConstantPoolConstant::Create(BA, ARMPCLabelIndex,
2275                                      ARMCP::CPBlockAddress, PCAdj);
2276    CPAddr = DAG.getTargetConstantPool(CPV, PtrVT, 4);
2277  }
2278  CPAddr = DAG.getNode(ARMISD::Wrapper, DL, PtrVT, CPAddr);
2279  SDValue Result = DAG.getLoad(PtrVT, DL, DAG.getEntryNode(), CPAddr,
2280                               MachinePointerInfo::getConstantPool(),
2281                               false, false, false, 0);
2282  if (RelocM == Reloc::Static)
2283    return Result;
2284  SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex, MVT::i32);
2285  return DAG.getNode(ARMISD::PIC_ADD, DL, PtrVT, Result, PICLabel);
2286}
2287
2288// Lower ISD::GlobalTLSAddress using the "general dynamic" model
2289SDValue
2290ARMTargetLowering::LowerToTLSGeneralDynamicModel(GlobalAddressSDNode *GA,
2291                                                 SelectionDAG &DAG) const {
2292  SDLoc dl(GA);
2293  EVT PtrVT = getPointerTy();
2294  unsigned char PCAdj = Subtarget->isThumb() ? 4 : 8;
2295  MachineFunction &MF = DAG.getMachineFunction();
2296  ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
2297  unsigned ARMPCLabelIndex = AFI->createPICLabelUId();
2298  ARMConstantPoolValue *CPV =
2299    ARMConstantPoolConstant::Create(GA->getGlobal(), ARMPCLabelIndex,
2300                                    ARMCP::CPValue, PCAdj, ARMCP::TLSGD, true);
2301  SDValue Argument = DAG.getTargetConstantPool(CPV, PtrVT, 4);
2302  Argument = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, Argument);
2303  Argument = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), Argument,
2304                         MachinePointerInfo::getConstantPool(),
2305                         false, false, false, 0);
2306  SDValue Chain = Argument.getValue(1);
2307
2308  SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex, MVT::i32);
2309  Argument = DAG.getNode(ARMISD::PIC_ADD, dl, PtrVT, Argument, PICLabel);
2310
2311  // call __tls_get_addr.
2312  ArgListTy Args;
2313  ArgListEntry Entry;
2314  Entry.Node = Argument;
2315  Entry.Ty = (Type *) Type::getInt32Ty(*DAG.getContext());
2316  Args.push_back(Entry);
2317  // FIXME: is there useful debug info available here?
2318  TargetLowering::CallLoweringInfo CLI(Chain,
2319                (Type *) Type::getInt32Ty(*DAG.getContext()),
2320                false, false, false, false,
2321                0, CallingConv::C, /*isTailCall=*/false,
2322                /*doesNotRet=*/false, /*isReturnValueUsed=*/true,
2323                DAG.getExternalSymbol("__tls_get_addr", PtrVT), Args, DAG, dl);
2324  std::pair<SDValue, SDValue> CallResult = LowerCallTo(CLI);
2325  return CallResult.first;
2326}
2327
2328// Lower ISD::GlobalTLSAddress using the "initial exec" or
2329// "local exec" model.
2330SDValue
2331ARMTargetLowering::LowerToTLSExecModels(GlobalAddressSDNode *GA,
2332                                        SelectionDAG &DAG,
2333                                        TLSModel::Model model) const {
2334  const GlobalValue *GV = GA->getGlobal();
2335  SDLoc dl(GA);
2336  SDValue Offset;
2337  SDValue Chain = DAG.getEntryNode();
2338  EVT PtrVT = getPointerTy();
2339  // Get the Thread Pointer
2340  SDValue ThreadPointer = DAG.getNode(ARMISD::THREAD_POINTER, dl, PtrVT);
2341
2342  if (model == TLSModel::InitialExec) {
2343    MachineFunction &MF = DAG.getMachineFunction();
2344    ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
2345    unsigned ARMPCLabelIndex = AFI->createPICLabelUId();
2346    // Initial exec model.
2347    unsigned char PCAdj = Subtarget->isThumb() ? 4 : 8;
2348    ARMConstantPoolValue *CPV =
2349      ARMConstantPoolConstant::Create(GA->getGlobal(), ARMPCLabelIndex,
2350                                      ARMCP::CPValue, PCAdj, ARMCP::GOTTPOFF,
2351                                      true);
2352    Offset = DAG.getTargetConstantPool(CPV, PtrVT, 4);
2353    Offset = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, Offset);
2354    Offset = DAG.getLoad(PtrVT, dl, Chain, Offset,
2355                         MachinePointerInfo::getConstantPool(),
2356                         false, false, false, 0);
2357    Chain = Offset.getValue(1);
2358
2359    SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex, MVT::i32);
2360    Offset = DAG.getNode(ARMISD::PIC_ADD, dl, PtrVT, Offset, PICLabel);
2361
2362    Offset = DAG.getLoad(PtrVT, dl, Chain, Offset,
2363                         MachinePointerInfo::getConstantPool(),
2364                         false, false, false, 0);
2365  } else {
2366    // local exec model
2367    assert(model == TLSModel::LocalExec);
2368    ARMConstantPoolValue *CPV =
2369      ARMConstantPoolConstant::Create(GV, ARMCP::TPOFF);
2370    Offset = DAG.getTargetConstantPool(CPV, PtrVT, 4);
2371    Offset = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, Offset);
2372    Offset = DAG.getLoad(PtrVT, dl, Chain, Offset,
2373                         MachinePointerInfo::getConstantPool(),
2374                         false, false, false, 0);
2375  }
2376
2377  // The address of the thread local variable is the add of the thread
2378  // pointer with the offset of the variable.
2379  return DAG.getNode(ISD::ADD, dl, PtrVT, ThreadPointer, Offset);
2380}
2381
2382SDValue
2383ARMTargetLowering::LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const {
2384  // TODO: implement the "local dynamic" model
2385  assert(Subtarget->isTargetELF() &&
2386         "TLS not implemented for non-ELF targets");
2387  GlobalAddressSDNode *GA = cast<GlobalAddressSDNode>(Op);
2388
2389  TLSModel::Model model = getTargetMachine().getTLSModel(GA->getGlobal());
2390
2391  switch (model) {
2392    case TLSModel::GeneralDynamic:
2393    case TLSModel::LocalDynamic:
2394      return LowerToTLSGeneralDynamicModel(GA, DAG);
2395    case TLSModel::InitialExec:
2396    case TLSModel::LocalExec:
2397      return LowerToTLSExecModels(GA, DAG, model);
2398  }
2399  llvm_unreachable("bogus TLS model");
2400}
2401
2402SDValue ARMTargetLowering::LowerGlobalAddressELF(SDValue Op,
2403                                                 SelectionDAG &DAG) const {
2404  EVT PtrVT = getPointerTy();
2405  SDLoc dl(Op);
2406  const GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
2407  if (getTargetMachine().getRelocationModel() == Reloc::PIC_) {
2408    bool UseGOTOFF = GV->hasLocalLinkage() || GV->hasHiddenVisibility();
2409    ARMConstantPoolValue *CPV =
2410      ARMConstantPoolConstant::Create(GV,
2411                                      UseGOTOFF ? ARMCP::GOTOFF : ARMCP::GOT);
2412    SDValue CPAddr = DAG.getTargetConstantPool(CPV, PtrVT, 4);
2413    CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr);
2414    SDValue Result = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(),
2415                                 CPAddr,
2416                                 MachinePointerInfo::getConstantPool(),
2417                                 false, false, false, 0);
2418    SDValue Chain = Result.getValue(1);
2419    SDValue GOT = DAG.getGLOBAL_OFFSET_TABLE(PtrVT);
2420    Result = DAG.getNode(ISD::ADD, dl, PtrVT, Result, GOT);
2421    if (!UseGOTOFF)
2422      Result = DAG.getLoad(PtrVT, dl, Chain, Result,
2423                           MachinePointerInfo::getGOT(),
2424                           false, false, false, 0);
2425    return Result;
2426  }
2427
2428  // If we have T2 ops, we can materialize the address directly via movt/movw
2429  // pair. This is always cheaper.
2430  if (Subtarget->useMovt()) {
2431    ++NumMovwMovt;
2432    // FIXME: Once remat is capable of dealing with instructions with register
2433    // operands, expand this into two nodes.
2434    return DAG.getNode(ARMISD::Wrapper, dl, PtrVT,
2435                       DAG.getTargetGlobalAddress(GV, dl, PtrVT));
2436  } else {
2437    SDValue CPAddr = DAG.getTargetConstantPool(GV, PtrVT, 4);
2438    CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr);
2439    return DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), CPAddr,
2440                       MachinePointerInfo::getConstantPool(),
2441                       false, false, false, 0);
2442  }
2443}
2444
2445SDValue ARMTargetLowering::LowerGlobalAddressDarwin(SDValue Op,
2446                                                    SelectionDAG &DAG) const {
2447  EVT PtrVT = getPointerTy();
2448  SDLoc dl(Op);
2449  const GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
2450  Reloc::Model RelocM = getTargetMachine().getRelocationModel();
2451
2452  if (Subtarget->useMovt())
2453    ++NumMovwMovt;
2454
2455  // FIXME: Once remat is capable of dealing with instructions with register
2456  // operands, expand this into multiple nodes
2457  unsigned Wrapper =
2458      RelocM == Reloc::PIC_ ? ARMISD::WrapperPIC : ARMISD::Wrapper;
2459
2460  SDValue G = DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0, ARMII::MO_NONLAZY);
2461  SDValue Result = DAG.getNode(Wrapper, dl, PtrVT, G);
2462
2463  if (Subtarget->GVIsIndirectSymbol(GV, RelocM))
2464    Result = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), Result,
2465                         MachinePointerInfo::getGOT(), false, false, false, 0);
2466  return Result;
2467}
2468
2469SDValue ARMTargetLowering::LowerGLOBAL_OFFSET_TABLE(SDValue Op,
2470                                                    SelectionDAG &DAG) const {
2471  assert(Subtarget->isTargetELF() &&
2472         "GLOBAL OFFSET TABLE not implemented for non-ELF targets");
2473  MachineFunction &MF = DAG.getMachineFunction();
2474  ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
2475  unsigned ARMPCLabelIndex = AFI->createPICLabelUId();
2476  EVT PtrVT = getPointerTy();
2477  SDLoc dl(Op);
2478  unsigned PCAdj = Subtarget->isThumb() ? 4 : 8;
2479  ARMConstantPoolValue *CPV =
2480    ARMConstantPoolSymbol::Create(*DAG.getContext(), "_GLOBAL_OFFSET_TABLE_",
2481                                  ARMPCLabelIndex, PCAdj);
2482  SDValue CPAddr = DAG.getTargetConstantPool(CPV, PtrVT, 4);
2483  CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr);
2484  SDValue Result = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), CPAddr,
2485                               MachinePointerInfo::getConstantPool(),
2486                               false, false, false, 0);
2487  SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex, MVT::i32);
2488  return DAG.getNode(ARMISD::PIC_ADD, dl, PtrVT, Result, PICLabel);
2489}
2490
2491SDValue
2492ARMTargetLowering::LowerEH_SJLJ_SETJMP(SDValue Op, SelectionDAG &DAG) const {
2493  SDLoc dl(Op);
2494  SDValue Val = DAG.getConstant(0, MVT::i32);
2495  return DAG.getNode(ARMISD::EH_SJLJ_SETJMP, dl,
2496                     DAG.getVTList(MVT::i32, MVT::Other), Op.getOperand(0),
2497                     Op.getOperand(1), Val);
2498}
2499
2500SDValue
2501ARMTargetLowering::LowerEH_SJLJ_LONGJMP(SDValue Op, SelectionDAG &DAG) const {
2502  SDLoc dl(Op);
2503  return DAG.getNode(ARMISD::EH_SJLJ_LONGJMP, dl, MVT::Other, Op.getOperand(0),
2504                     Op.getOperand(1), DAG.getConstant(0, MVT::i32));
2505}
2506
2507SDValue
2508ARMTargetLowering::LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG,
2509                                          const ARMSubtarget *Subtarget) const {
2510  unsigned IntNo = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
2511  SDLoc dl(Op);
2512  switch (IntNo) {
2513  default: return SDValue();    // Don't custom lower most intrinsics.
2514  case Intrinsic::arm_thread_pointer: {
2515    EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
2516    return DAG.getNode(ARMISD::THREAD_POINTER, dl, PtrVT);
2517  }
2518  case Intrinsic::eh_sjlj_lsda: {
2519    MachineFunction &MF = DAG.getMachineFunction();
2520    ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
2521    unsigned ARMPCLabelIndex = AFI->createPICLabelUId();
2522    EVT PtrVT = getPointerTy();
2523    Reloc::Model RelocM = getTargetMachine().getRelocationModel();
2524    SDValue CPAddr;
2525    unsigned PCAdj = (RelocM != Reloc::PIC_)
2526      ? 0 : (Subtarget->isThumb() ? 4 : 8);
2527    ARMConstantPoolValue *CPV =
2528      ARMConstantPoolConstant::Create(MF.getFunction(), ARMPCLabelIndex,
2529                                      ARMCP::CPLSDA, PCAdj);
2530    CPAddr = DAG.getTargetConstantPool(CPV, PtrVT, 4);
2531    CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr);
2532    SDValue Result =
2533      DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), CPAddr,
2534                  MachinePointerInfo::getConstantPool(),
2535                  false, false, false, 0);
2536
2537    if (RelocM == Reloc::PIC_) {
2538      SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex, MVT::i32);
2539      Result = DAG.getNode(ARMISD::PIC_ADD, dl, PtrVT, Result, PICLabel);
2540    }
2541    return Result;
2542  }
2543  case Intrinsic::arm_neon_vmulls:
2544  case Intrinsic::arm_neon_vmullu: {
2545    unsigned NewOpc = (IntNo == Intrinsic::arm_neon_vmulls)
2546      ? ARMISD::VMULLs : ARMISD::VMULLu;
2547    return DAG.getNode(NewOpc, SDLoc(Op), Op.getValueType(),
2548                       Op.getOperand(1), Op.getOperand(2));
2549  }
2550  }
2551}
2552
2553static SDValue LowerATOMIC_FENCE(SDValue Op, SelectionDAG &DAG,
2554                                 const ARMSubtarget *Subtarget) {
2555  // FIXME: handle "fence singlethread" more efficiently.
2556  SDLoc dl(Op);
2557  if (!Subtarget->hasDataBarrier()) {
2558    // Some ARMv6 cpus can support data barriers with an mcr instruction.
2559    // Thumb1 and pre-v6 ARM mode use a libcall instead and should never get
2560    // here.
2561    assert(Subtarget->hasV6Ops() && !Subtarget->isThumb() &&
2562           "Unexpected ISD::ATOMIC_FENCE encountered. Should be libcall!");
2563    return DAG.getNode(ARMISD::MEMBARRIER_MCR, dl, MVT::Other, Op.getOperand(0),
2564                       DAG.getConstant(0, MVT::i32));
2565  }
2566
2567  ConstantSDNode *OrdN = cast<ConstantSDNode>(Op.getOperand(1));
2568  AtomicOrdering Ord = static_cast<AtomicOrdering>(OrdN->getZExtValue());
2569  unsigned Domain = ARM_MB::ISH;
2570  if (Subtarget->isMClass()) {
2571    // Only a full system barrier exists in the M-class architectures.
2572    Domain = ARM_MB::SY;
2573  } else if (Subtarget->isSwift() && Ord == Release) {
2574    // Swift happens to implement ISHST barriers in a way that's compatible with
2575    // Release semantics but weaker than ISH so we'd be fools not to use
2576    // it. Beware: other processors probably don't!
2577    Domain = ARM_MB::ISHST;
2578  }
2579
2580  return DAG.getNode(ISD::INTRINSIC_VOID, dl, MVT::Other, Op.getOperand(0),
2581                     DAG.getConstant(Intrinsic::arm_dmb, MVT::i32),
2582                     DAG.getConstant(Domain, MVT::i32));
2583}
2584
2585static SDValue LowerPREFETCH(SDValue Op, SelectionDAG &DAG,
2586                             const ARMSubtarget *Subtarget) {
2587  // ARM pre v5TE and Thumb1 does not have preload instructions.
2588  if (!(Subtarget->isThumb2() ||
2589        (!Subtarget->isThumb1Only() && Subtarget->hasV5TEOps())))
2590    // Just preserve the chain.
2591    return Op.getOperand(0);
2592
2593  SDLoc dl(Op);
2594  unsigned isRead = ~cast<ConstantSDNode>(Op.getOperand(2))->getZExtValue() & 1;
2595  if (!isRead &&
2596      (!Subtarget->hasV7Ops() || !Subtarget->hasMPExtension()))
2597    // ARMv7 with MP extension has PLDW.
2598    return Op.getOperand(0);
2599
2600  unsigned isData = cast<ConstantSDNode>(Op.getOperand(4))->getZExtValue();
2601  if (Subtarget->isThumb()) {
2602    // Invert the bits.
2603    isRead = ~isRead & 1;
2604    isData = ~isData & 1;
2605  }
2606
2607  return DAG.getNode(ARMISD::PRELOAD, dl, MVT::Other, Op.getOperand(0),
2608                     Op.getOperand(1), DAG.getConstant(isRead, MVT::i32),
2609                     DAG.getConstant(isData, MVT::i32));
2610}
2611
2612static SDValue LowerVASTART(SDValue Op, SelectionDAG &DAG) {
2613  MachineFunction &MF = DAG.getMachineFunction();
2614  ARMFunctionInfo *FuncInfo = MF.getInfo<ARMFunctionInfo>();
2615
2616  // vastart just stores the address of the VarArgsFrameIndex slot into the
2617  // memory location argument.
2618  SDLoc dl(Op);
2619  EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
2620  SDValue FR = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(), PtrVT);
2621  const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
2622  return DAG.getStore(Op.getOperand(0), dl, FR, Op.getOperand(1),
2623                      MachinePointerInfo(SV), false, false, 0);
2624}
2625
2626SDValue
2627ARMTargetLowering::GetF64FormalArgument(CCValAssign &VA, CCValAssign &NextVA,
2628                                        SDValue &Root, SelectionDAG &DAG,
2629                                        SDLoc dl) const {
2630  MachineFunction &MF = DAG.getMachineFunction();
2631  ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
2632
2633  const TargetRegisterClass *RC;
2634  if (AFI->isThumb1OnlyFunction())
2635    RC = &ARM::tGPRRegClass;
2636  else
2637    RC = &ARM::GPRRegClass;
2638
2639  // Transform the arguments stored in physical registers into virtual ones.
2640  unsigned Reg = MF.addLiveIn(VA.getLocReg(), RC);
2641  SDValue ArgValue = DAG.getCopyFromReg(Root, dl, Reg, MVT::i32);
2642
2643  SDValue ArgValue2;
2644  if (NextVA.isMemLoc()) {
2645    MachineFrameInfo *MFI = MF.getFrameInfo();
2646    int FI = MFI->CreateFixedObject(4, NextVA.getLocMemOffset(), true);
2647
2648    // Create load node to retrieve arguments from the stack.
2649    SDValue FIN = DAG.getFrameIndex(FI, getPointerTy());
2650    ArgValue2 = DAG.getLoad(MVT::i32, dl, Root, FIN,
2651                            MachinePointerInfo::getFixedStack(FI),
2652                            false, false, false, 0);
2653  } else {
2654    Reg = MF.addLiveIn(NextVA.getLocReg(), RC);
2655    ArgValue2 = DAG.getCopyFromReg(Root, dl, Reg, MVT::i32);
2656  }
2657
2658  return DAG.getNode(ARMISD::VMOVDRR, dl, MVT::f64, ArgValue, ArgValue2);
2659}
2660
2661void
2662ARMTargetLowering::computeRegArea(CCState &CCInfo, MachineFunction &MF,
2663                                  unsigned InRegsParamRecordIdx,
2664                                  unsigned ArgSize,
2665                                  unsigned &ArgRegsSize,
2666                                  unsigned &ArgRegsSaveSize)
2667  const {
2668  unsigned NumGPRs;
2669  if (InRegsParamRecordIdx < CCInfo.getInRegsParamsCount()) {
2670    unsigned RBegin, REnd;
2671    CCInfo.getInRegsParamInfo(InRegsParamRecordIdx, RBegin, REnd);
2672    NumGPRs = REnd - RBegin;
2673  } else {
2674    unsigned int firstUnalloced;
2675    firstUnalloced = CCInfo.getFirstUnallocated(GPRArgRegs,
2676                                                sizeof(GPRArgRegs) /
2677                                                sizeof(GPRArgRegs[0]));
2678    NumGPRs = (firstUnalloced <= 3) ? (4 - firstUnalloced) : 0;
2679  }
2680
2681  unsigned Align = MF.getTarget().getFrameLowering()->getStackAlignment();
2682  ArgRegsSize = NumGPRs * 4;
2683
2684  // If parameter is split between stack and GPRs...
2685  if (NumGPRs && Align > 4 &&
2686      (ArgRegsSize < ArgSize ||
2687        InRegsParamRecordIdx >= CCInfo.getInRegsParamsCount())) {
2688    // Add padding for part of param recovered from GPRs.  For example,
2689    // if Align == 8, its last byte must be at address K*8 - 1.
2690    // We need to do it, since remained (stack) part of parameter has
2691    // stack alignment, and we need to "attach" "GPRs head" without gaps
2692    // to it:
2693    // Stack:
2694    // |---- 8 bytes block ----| |---- 8 bytes block ----| |---- 8 bytes...
2695    // [ [padding] [GPRs head] ] [        Tail passed via stack       ....
2696    //
2697    ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
2698    unsigned Padding =
2699        OffsetToAlignment(ArgRegsSize + AFI->getArgRegsSaveSize(), Align);
2700    ArgRegsSaveSize = ArgRegsSize + Padding;
2701  } else
2702    // We don't need to extend regs save size for byval parameters if they
2703    // are passed via GPRs only.
2704    ArgRegsSaveSize = ArgRegsSize;
2705}
2706
2707// The remaining GPRs hold either the beginning of variable-argument
2708// data, or the beginning of an aggregate passed by value (usually
2709// byval).  Either way, we allocate stack slots adjacent to the data
2710// provided by our caller, and store the unallocated registers there.
2711// If this is a variadic function, the va_list pointer will begin with
2712// these values; otherwise, this reassembles a (byval) structure that
2713// was split between registers and memory.
2714// Return: The frame index registers were stored into.
2715int
2716ARMTargetLowering::StoreByValRegs(CCState &CCInfo, SelectionDAG &DAG,
2717                                  SDLoc dl, SDValue &Chain,
2718                                  const Value *OrigArg,
2719                                  unsigned InRegsParamRecordIdx,
2720                                  unsigned OffsetFromOrigArg,
2721                                  unsigned ArgOffset,
2722                                  unsigned ArgSize,
2723                                  bool ForceMutable,
2724                                  unsigned ByValStoreOffset,
2725                                  unsigned TotalArgRegsSaveSize) const {
2726
2727  // Currently, two use-cases possible:
2728  // Case #1. Non-var-args function, and we meet first byval parameter.
2729  //          Setup first unallocated register as first byval register;
2730  //          eat all remained registers
2731  //          (these two actions are performed by HandleByVal method).
2732  //          Then, here, we initialize stack frame with
2733  //          "store-reg" instructions.
2734  // Case #2. Var-args function, that doesn't contain byval parameters.
2735  //          The same: eat all remained unallocated registers,
2736  //          initialize stack frame.
2737
2738  MachineFunction &MF = DAG.getMachineFunction();
2739  MachineFrameInfo *MFI = MF.getFrameInfo();
2740  ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
2741  unsigned firstRegToSaveIndex, lastRegToSaveIndex;
2742  unsigned RBegin, REnd;
2743  if (InRegsParamRecordIdx < CCInfo.getInRegsParamsCount()) {
2744    CCInfo.getInRegsParamInfo(InRegsParamRecordIdx, RBegin, REnd);
2745    firstRegToSaveIndex = RBegin - ARM::R0;
2746    lastRegToSaveIndex = REnd - ARM::R0;
2747  } else {
2748    firstRegToSaveIndex = CCInfo.getFirstUnallocated
2749      (GPRArgRegs, array_lengthof(GPRArgRegs));
2750    lastRegToSaveIndex = 4;
2751  }
2752
2753  unsigned ArgRegsSize, ArgRegsSaveSize;
2754  computeRegArea(CCInfo, MF, InRegsParamRecordIdx, ArgSize,
2755                 ArgRegsSize, ArgRegsSaveSize);
2756
2757  // Store any by-val regs to their spots on the stack so that they may be
2758  // loaded by deferencing the result of formal parameter pointer or va_next.
2759  // Note: once stack area for byval/varargs registers
2760  // was initialized, it can't be initialized again.
2761  if (ArgRegsSaveSize) {
2762    unsigned Padding = ArgRegsSaveSize - ArgRegsSize;
2763
2764    if (Padding) {
2765      assert(AFI->getStoredByValParamsPadding() == 0 &&
2766             "The only parameter may be padded.");
2767      AFI->setStoredByValParamsPadding(Padding);
2768    }
2769
2770    int FrameIndex = MFI->CreateFixedObject(ArgRegsSaveSize,
2771                                            Padding +
2772                                              ByValStoreOffset -
2773                                              (int64_t)TotalArgRegsSaveSize,
2774                                            false);
2775    SDValue FIN = DAG.getFrameIndex(FrameIndex, getPointerTy());
2776    if (Padding) {
2777       MFI->CreateFixedObject(Padding,
2778                              ArgOffset + ByValStoreOffset -
2779                                (int64_t)ArgRegsSaveSize,
2780                              false);
2781    }
2782
2783    SmallVector<SDValue, 4> MemOps;
2784    for (unsigned i = 0; firstRegToSaveIndex < lastRegToSaveIndex;
2785         ++firstRegToSaveIndex, ++i) {
2786      const TargetRegisterClass *RC;
2787      if (AFI->isThumb1OnlyFunction())
2788        RC = &ARM::tGPRRegClass;
2789      else
2790        RC = &ARM::GPRRegClass;
2791
2792      unsigned VReg = MF.addLiveIn(GPRArgRegs[firstRegToSaveIndex], RC);
2793      SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, MVT::i32);
2794      SDValue Store =
2795        DAG.getStore(Val.getValue(1), dl, Val, FIN,
2796                     MachinePointerInfo(OrigArg, OffsetFromOrigArg + 4*i),
2797                     false, false, 0);
2798      MemOps.push_back(Store);
2799      FIN = DAG.getNode(ISD::ADD, dl, getPointerTy(), FIN,
2800                        DAG.getConstant(4, getPointerTy()));
2801    }
2802
2803    AFI->setArgRegsSaveSize(ArgRegsSaveSize + AFI->getArgRegsSaveSize());
2804
2805    if (!MemOps.empty())
2806      Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
2807                          &MemOps[0], MemOps.size());
2808    return FrameIndex;
2809  } else {
2810    if (ArgSize == 0) {
2811      // We cannot allocate a zero-byte object for the first variadic argument,
2812      // so just make up a size.
2813      ArgSize = 4;
2814    }
2815    // This will point to the next argument passed via stack.
2816    return MFI->CreateFixedObject(
2817      ArgSize, ArgOffset, !ForceMutable);
2818  }
2819}
2820
2821// Setup stack frame, the va_list pointer will start from.
2822void
2823ARMTargetLowering::VarArgStyleRegisters(CCState &CCInfo, SelectionDAG &DAG,
2824                                        SDLoc dl, SDValue &Chain,
2825                                        unsigned ArgOffset,
2826                                        unsigned TotalArgRegsSaveSize,
2827                                        bool ForceMutable) const {
2828  MachineFunction &MF = DAG.getMachineFunction();
2829  ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
2830
2831  // Try to store any remaining integer argument regs
2832  // to their spots on the stack so that they may be loaded by deferencing
2833  // the result of va_next.
2834  // If there is no regs to be stored, just point address after last
2835  // argument passed via stack.
2836  int FrameIndex =
2837    StoreByValRegs(CCInfo, DAG, dl, Chain, 0, CCInfo.getInRegsParamsCount(),
2838                   0, ArgOffset, 0, ForceMutable, 0, TotalArgRegsSaveSize);
2839
2840  AFI->setVarArgsFrameIndex(FrameIndex);
2841}
2842
2843SDValue
2844ARMTargetLowering::LowerFormalArguments(SDValue Chain,
2845                                        CallingConv::ID CallConv, bool isVarArg,
2846                                        const SmallVectorImpl<ISD::InputArg>
2847                                          &Ins,
2848                                        SDLoc dl, SelectionDAG &DAG,
2849                                        SmallVectorImpl<SDValue> &InVals)
2850                                          const {
2851  MachineFunction &MF = DAG.getMachineFunction();
2852  MachineFrameInfo *MFI = MF.getFrameInfo();
2853
2854  ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
2855
2856  // Assign locations to all of the incoming arguments.
2857  SmallVector<CCValAssign, 16> ArgLocs;
2858  ARMCCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(),
2859                    getTargetMachine(), ArgLocs, *DAG.getContext(), Prologue);
2860  CCInfo.AnalyzeFormalArguments(Ins,
2861                                CCAssignFnForNode(CallConv, /* Return*/ false,
2862                                                  isVarArg));
2863
2864  SmallVector<SDValue, 16> ArgValues;
2865  int lastInsIndex = -1;
2866  SDValue ArgValue;
2867  Function::const_arg_iterator CurOrigArg = MF.getFunction()->arg_begin();
2868  unsigned CurArgIdx = 0;
2869
2870  // Initially ArgRegsSaveSize is zero.
2871  // Then we increase this value each time we meet byval parameter.
2872  // We also increase this value in case of varargs function.
2873  AFI->setArgRegsSaveSize(0);
2874
2875  unsigned ByValStoreOffset = 0;
2876  unsigned TotalArgRegsSaveSize = 0;
2877  unsigned ArgRegsSaveSizeMaxAlign = 4;
2878
2879  // Calculate the amount of stack space that we need to allocate to store
2880  // byval and variadic arguments that are passed in registers.
2881  // We need to know this before we allocate the first byval or variadic
2882  // argument, as they will be allocated a stack slot below the CFA (Canonical
2883  // Frame Address, the stack pointer at entry to the function).
2884  for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2885    CCValAssign &VA = ArgLocs[i];
2886    if (VA.isMemLoc()) {
2887      int index = VA.getValNo();
2888      if (index != lastInsIndex) {
2889        ISD::ArgFlagsTy Flags = Ins[index].Flags;
2890        if (Flags.isByVal()) {
2891          unsigned ExtraArgRegsSize;
2892          unsigned ExtraArgRegsSaveSize;
2893          computeRegArea(CCInfo, MF, CCInfo.getInRegsParamsProceed(),
2894                         Flags.getByValSize(),
2895                         ExtraArgRegsSize, ExtraArgRegsSaveSize);
2896
2897          TotalArgRegsSaveSize += ExtraArgRegsSaveSize;
2898          if (Flags.getByValAlign() > ArgRegsSaveSizeMaxAlign)
2899              ArgRegsSaveSizeMaxAlign = Flags.getByValAlign();
2900          CCInfo.nextInRegsParam();
2901        }
2902        lastInsIndex = index;
2903      }
2904    }
2905  }
2906  CCInfo.rewindByValRegsInfo();
2907  lastInsIndex = -1;
2908  if (isVarArg) {
2909    unsigned ExtraArgRegsSize;
2910    unsigned ExtraArgRegsSaveSize;
2911    computeRegArea(CCInfo, MF, CCInfo.getInRegsParamsCount(), 0,
2912                   ExtraArgRegsSize, ExtraArgRegsSaveSize);
2913    TotalArgRegsSaveSize += ExtraArgRegsSaveSize;
2914  }
2915  // If the arg regs save area contains N-byte aligned values, the
2916  // bottom of it must be at least N-byte aligned.
2917  TotalArgRegsSaveSize = RoundUpToAlignment(TotalArgRegsSaveSize, ArgRegsSaveSizeMaxAlign);
2918  TotalArgRegsSaveSize = std::min(TotalArgRegsSaveSize, 16U);
2919
2920  for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2921    CCValAssign &VA = ArgLocs[i];
2922    std::advance(CurOrigArg, Ins[VA.getValNo()].OrigArgIndex - CurArgIdx);
2923    CurArgIdx = Ins[VA.getValNo()].OrigArgIndex;
2924    // Arguments stored in registers.
2925    if (VA.isRegLoc()) {
2926      EVT RegVT = VA.getLocVT();
2927
2928      if (VA.needsCustom()) {
2929        // f64 and vector types are split up into multiple registers or
2930        // combinations of registers and stack slots.
2931        if (VA.getLocVT() == MVT::v2f64) {
2932          SDValue ArgValue1 = GetF64FormalArgument(VA, ArgLocs[++i],
2933                                                   Chain, DAG, dl);
2934          VA = ArgLocs[++i]; // skip ahead to next loc
2935          SDValue ArgValue2;
2936          if (VA.isMemLoc()) {
2937            int FI = MFI->CreateFixedObject(8, VA.getLocMemOffset(), true);
2938            SDValue FIN = DAG.getFrameIndex(FI, getPointerTy());
2939            ArgValue2 = DAG.getLoad(MVT::f64, dl, Chain, FIN,
2940                                    MachinePointerInfo::getFixedStack(FI),
2941                                    false, false, false, 0);
2942          } else {
2943            ArgValue2 = GetF64FormalArgument(VA, ArgLocs[++i],
2944                                             Chain, DAG, dl);
2945          }
2946          ArgValue = DAG.getNode(ISD::UNDEF, dl, MVT::v2f64);
2947          ArgValue = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v2f64,
2948                                 ArgValue, ArgValue1, DAG.getIntPtrConstant(0));
2949          ArgValue = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v2f64,
2950                                 ArgValue, ArgValue2, DAG.getIntPtrConstant(1));
2951        } else
2952          ArgValue = GetF64FormalArgument(VA, ArgLocs[++i], Chain, DAG, dl);
2953
2954      } else {
2955        const TargetRegisterClass *RC;
2956
2957        if (RegVT == MVT::f32)
2958          RC = &ARM::SPRRegClass;
2959        else if (RegVT == MVT::f64)
2960          RC = &ARM::DPRRegClass;
2961        else if (RegVT == MVT::v2f64)
2962          RC = &ARM::QPRRegClass;
2963        else if (RegVT == MVT::i32)
2964          RC = AFI->isThumb1OnlyFunction() ?
2965            (const TargetRegisterClass*)&ARM::tGPRRegClass :
2966            (const TargetRegisterClass*)&ARM::GPRRegClass;
2967        else
2968          llvm_unreachable("RegVT not supported by FORMAL_ARGUMENTS Lowering");
2969
2970        // Transform the arguments in physical registers into virtual ones.
2971        unsigned Reg = MF.addLiveIn(VA.getLocReg(), RC);
2972        ArgValue = DAG.getCopyFromReg(Chain, dl, Reg, RegVT);
2973      }
2974
2975      // If this is an 8 or 16-bit value, it is really passed promoted
2976      // to 32 bits.  Insert an assert[sz]ext to capture this, then
2977      // truncate to the right size.
2978      switch (VA.getLocInfo()) {
2979      default: llvm_unreachable("Unknown loc info!");
2980      case CCValAssign::Full: break;
2981      case CCValAssign::BCvt:
2982        ArgValue = DAG.getNode(ISD::BITCAST, dl, VA.getValVT(), ArgValue);
2983        break;
2984      case CCValAssign::SExt:
2985        ArgValue = DAG.getNode(ISD::AssertSext, dl, RegVT, ArgValue,
2986                               DAG.getValueType(VA.getValVT()));
2987        ArgValue = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), ArgValue);
2988        break;
2989      case CCValAssign::ZExt:
2990        ArgValue = DAG.getNode(ISD::AssertZext, dl, RegVT, ArgValue,
2991                               DAG.getValueType(VA.getValVT()));
2992        ArgValue = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), ArgValue);
2993        break;
2994      }
2995
2996      InVals.push_back(ArgValue);
2997
2998    } else { // VA.isRegLoc()
2999
3000      // sanity check
3001      assert(VA.isMemLoc());
3002      assert(VA.getValVT() != MVT::i64 && "i64 should already be lowered");
3003
3004      int index = ArgLocs[i].getValNo();
3005
3006      // Some Ins[] entries become multiple ArgLoc[] entries.
3007      // Process them only once.
3008      if (index != lastInsIndex)
3009        {
3010          ISD::ArgFlagsTy Flags = Ins[index].Flags;
3011          // FIXME: For now, all byval parameter objects are marked mutable.
3012          // This can be changed with more analysis.
3013          // In case of tail call optimization mark all arguments mutable.
3014          // Since they could be overwritten by lowering of arguments in case of
3015          // a tail call.
3016          if (Flags.isByVal()) {
3017            unsigned CurByValIndex = CCInfo.getInRegsParamsProceed();
3018
3019            ByValStoreOffset = RoundUpToAlignment(ByValStoreOffset, Flags.getByValAlign());
3020            int FrameIndex = StoreByValRegs(
3021                CCInfo, DAG, dl, Chain, CurOrigArg,
3022                CurByValIndex,
3023                Ins[VA.getValNo()].PartOffset,
3024                VA.getLocMemOffset(),
3025                Flags.getByValSize(),
3026                true /*force mutable frames*/,
3027                ByValStoreOffset,
3028                TotalArgRegsSaveSize);
3029            ByValStoreOffset += Flags.getByValSize();
3030            ByValStoreOffset = std::min(ByValStoreOffset, 16U);
3031            InVals.push_back(DAG.getFrameIndex(FrameIndex, getPointerTy()));
3032            CCInfo.nextInRegsParam();
3033          } else {
3034            unsigned FIOffset = VA.getLocMemOffset();
3035            int FI = MFI->CreateFixedObject(VA.getLocVT().getSizeInBits()/8,
3036                                            FIOffset, true);
3037
3038            // Create load nodes to retrieve arguments from the stack.
3039            SDValue FIN = DAG.getFrameIndex(FI, getPointerTy());
3040            InVals.push_back(DAG.getLoad(VA.getValVT(), dl, Chain, FIN,
3041                                         MachinePointerInfo::getFixedStack(FI),
3042                                         false, false, false, 0));
3043          }
3044          lastInsIndex = index;
3045        }
3046    }
3047  }
3048
3049  // varargs
3050  if (isVarArg)
3051    VarArgStyleRegisters(CCInfo, DAG, dl, Chain,
3052                         CCInfo.getNextStackOffset(),
3053                         TotalArgRegsSaveSize);
3054
3055  AFI->setArgumentStackSize(CCInfo.getNextStackOffset());
3056
3057  return Chain;
3058}
3059
3060/// isFloatingPointZero - Return true if this is +0.0.
3061static bool isFloatingPointZero(SDValue Op) {
3062  if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(Op))
3063    return CFP->getValueAPF().isPosZero();
3064  else if (ISD::isEXTLoad(Op.getNode()) || ISD::isNON_EXTLoad(Op.getNode())) {
3065    // Maybe this has already been legalized into the constant pool?
3066    if (Op.getOperand(1).getOpcode() == ARMISD::Wrapper) {
3067      SDValue WrapperOp = Op.getOperand(1).getOperand(0);
3068      if (ConstantPoolSDNode *CP = dyn_cast<ConstantPoolSDNode>(WrapperOp))
3069        if (const ConstantFP *CFP = dyn_cast<ConstantFP>(CP->getConstVal()))
3070          return CFP->getValueAPF().isPosZero();
3071    }
3072  }
3073  return false;
3074}
3075
3076/// Returns appropriate ARM CMP (cmp) and corresponding condition code for
3077/// the given operands.
3078SDValue
3079ARMTargetLowering::getARMCmp(SDValue LHS, SDValue RHS, ISD::CondCode CC,
3080                             SDValue &ARMcc, SelectionDAG &DAG,
3081                             SDLoc dl) const {
3082  if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(RHS.getNode())) {
3083    unsigned C = RHSC->getZExtValue();
3084    if (!isLegalICmpImmediate(C)) {
3085      // Constant does not fit, try adjusting it by one?
3086      switch (CC) {
3087      default: break;
3088      case ISD::SETLT:
3089      case ISD::SETGE:
3090        if (C != 0x80000000 && isLegalICmpImmediate(C-1)) {
3091          CC = (CC == ISD::SETLT) ? ISD::SETLE : ISD::SETGT;
3092          RHS = DAG.getConstant(C-1, MVT::i32);
3093        }
3094        break;
3095      case ISD::SETULT:
3096      case ISD::SETUGE:
3097        if (C != 0 && isLegalICmpImmediate(C-1)) {
3098          CC = (CC == ISD::SETULT) ? ISD::SETULE : ISD::SETUGT;
3099          RHS = DAG.getConstant(C-1, MVT::i32);
3100        }
3101        break;
3102      case ISD::SETLE:
3103      case ISD::SETGT:
3104        if (C != 0x7fffffff && isLegalICmpImmediate(C+1)) {
3105          CC = (CC == ISD::SETLE) ? ISD::SETLT : ISD::SETGE;
3106          RHS = DAG.getConstant(C+1, MVT::i32);
3107        }
3108        break;
3109      case ISD::SETULE:
3110      case ISD::SETUGT:
3111        if (C != 0xffffffff && isLegalICmpImmediate(C+1)) {
3112          CC = (CC == ISD::SETULE) ? ISD::SETULT : ISD::SETUGE;
3113          RHS = DAG.getConstant(C+1, MVT::i32);
3114        }
3115        break;
3116      }
3117    }
3118  }
3119
3120  ARMCC::CondCodes CondCode = IntCCToARMCC(CC);
3121  ARMISD::NodeType CompareType;
3122  switch (CondCode) {
3123  default:
3124    CompareType = ARMISD::CMP;
3125    break;
3126  case ARMCC::EQ:
3127  case ARMCC::NE:
3128    // Uses only Z Flag
3129    CompareType = ARMISD::CMPZ;
3130    break;
3131  }
3132  ARMcc = DAG.getConstant(CondCode, MVT::i32);
3133  return DAG.getNode(CompareType, dl, MVT::Glue, LHS, RHS);
3134}
3135
3136/// Returns a appropriate VFP CMP (fcmp{s|d}+fmstat) for the given operands.
3137SDValue
3138ARMTargetLowering::getVFPCmp(SDValue LHS, SDValue RHS, SelectionDAG &DAG,
3139                             SDLoc dl) const {
3140  SDValue Cmp;
3141  if (!isFloatingPointZero(RHS))
3142    Cmp = DAG.getNode(ARMISD::CMPFP, dl, MVT::Glue, LHS, RHS);
3143  else
3144    Cmp = DAG.getNode(ARMISD::CMPFPw0, dl, MVT::Glue, LHS);
3145  return DAG.getNode(ARMISD::FMSTAT, dl, MVT::Glue, Cmp);
3146}
3147
3148/// duplicateCmp - Glue values can have only one use, so this function
3149/// duplicates a comparison node.
3150SDValue
3151ARMTargetLowering::duplicateCmp(SDValue Cmp, SelectionDAG &DAG) const {
3152  unsigned Opc = Cmp.getOpcode();
3153  SDLoc DL(Cmp);
3154  if (Opc == ARMISD::CMP || Opc == ARMISD::CMPZ)
3155    return DAG.getNode(Opc, DL, MVT::Glue, Cmp.getOperand(0),Cmp.getOperand(1));
3156
3157  assert(Opc == ARMISD::FMSTAT && "unexpected comparison operation");
3158  Cmp = Cmp.getOperand(0);
3159  Opc = Cmp.getOpcode();
3160  if (Opc == ARMISD::CMPFP)
3161    Cmp = DAG.getNode(Opc, DL, MVT::Glue, Cmp.getOperand(0),Cmp.getOperand(1));
3162  else {
3163    assert(Opc == ARMISD::CMPFPw0 && "unexpected operand of FMSTAT");
3164    Cmp = DAG.getNode(Opc, DL, MVT::Glue, Cmp.getOperand(0));
3165  }
3166  return DAG.getNode(ARMISD::FMSTAT, DL, MVT::Glue, Cmp);
3167}
3168
3169SDValue ARMTargetLowering::LowerSELECT(SDValue Op, SelectionDAG &DAG) const {
3170  SDValue Cond = Op.getOperand(0);
3171  SDValue SelectTrue = Op.getOperand(1);
3172  SDValue SelectFalse = Op.getOperand(2);
3173  SDLoc dl(Op);
3174
3175  // Convert:
3176  //
3177  //   (select (cmov 1, 0, cond), t, f) -> (cmov t, f, cond)
3178  //   (select (cmov 0, 1, cond), t, f) -> (cmov f, t, cond)
3179  //
3180  if (Cond.getOpcode() == ARMISD::CMOV && Cond.hasOneUse()) {
3181    const ConstantSDNode *CMOVTrue =
3182      dyn_cast<ConstantSDNode>(Cond.getOperand(0));
3183    const ConstantSDNode *CMOVFalse =
3184      dyn_cast<ConstantSDNode>(Cond.getOperand(1));
3185
3186    if (CMOVTrue && CMOVFalse) {
3187      unsigned CMOVTrueVal = CMOVTrue->getZExtValue();
3188      unsigned CMOVFalseVal = CMOVFalse->getZExtValue();
3189
3190      SDValue True;
3191      SDValue False;
3192      if (CMOVTrueVal == 1 && CMOVFalseVal == 0) {
3193        True = SelectTrue;
3194        False = SelectFalse;
3195      } else if (CMOVTrueVal == 0 && CMOVFalseVal == 1) {
3196        True = SelectFalse;
3197        False = SelectTrue;
3198      }
3199
3200      if (True.getNode() && False.getNode()) {
3201        EVT VT = Op.getValueType();
3202        SDValue ARMcc = Cond.getOperand(2);
3203        SDValue CCR = Cond.getOperand(3);
3204        SDValue Cmp = duplicateCmp(Cond.getOperand(4), DAG);
3205        assert(True.getValueType() == VT);
3206        return DAG.getNode(ARMISD::CMOV, dl, VT, True, False, ARMcc, CCR, Cmp);
3207      }
3208    }
3209  }
3210
3211  // ARM's BooleanContents value is UndefinedBooleanContent. Mask out the
3212  // undefined bits before doing a full-word comparison with zero.
3213  Cond = DAG.getNode(ISD::AND, dl, Cond.getValueType(), Cond,
3214                     DAG.getConstant(1, Cond.getValueType()));
3215
3216  return DAG.getSelectCC(dl, Cond,
3217                         DAG.getConstant(0, Cond.getValueType()),
3218                         SelectTrue, SelectFalse, ISD::SETNE);
3219}
3220
3221static ISD::CondCode getInverseCCForVSEL(ISD::CondCode CC) {
3222  if (CC == ISD::SETNE)
3223    return ISD::SETEQ;
3224  return ISD::getSetCCInverse(CC, true);
3225}
3226
3227static void checkVSELConstraints(ISD::CondCode CC, ARMCC::CondCodes &CondCode,
3228                                 bool &swpCmpOps, bool &swpVselOps) {
3229  // Start by selecting the GE condition code for opcodes that return true for
3230  // 'equality'
3231  if (CC == ISD::SETUGE || CC == ISD::SETOGE || CC == ISD::SETOLE ||
3232      CC == ISD::SETULE)
3233    CondCode = ARMCC::GE;
3234
3235  // and GT for opcodes that return false for 'equality'.
3236  else if (CC == ISD::SETUGT || CC == ISD::SETOGT || CC == ISD::SETOLT ||
3237           CC == ISD::SETULT)
3238    CondCode = ARMCC::GT;
3239
3240  // Since we are constrained to GE/GT, if the opcode contains 'less', we need
3241  // to swap the compare operands.
3242  if (CC == ISD::SETOLE || CC == ISD::SETULE || CC == ISD::SETOLT ||
3243      CC == ISD::SETULT)
3244    swpCmpOps = true;
3245
3246  // Both GT and GE are ordered comparisons, and return false for 'unordered'.
3247  // If we have an unordered opcode, we need to swap the operands to the VSEL
3248  // instruction (effectively negating the condition).
3249  //
3250  // This also has the effect of swapping which one of 'less' or 'greater'
3251  // returns true, so we also swap the compare operands. It also switches
3252  // whether we return true for 'equality', so we compensate by picking the
3253  // opposite condition code to our original choice.
3254  if (CC == ISD::SETULE || CC == ISD::SETULT || CC == ISD::SETUGE ||
3255      CC == ISD::SETUGT) {
3256    swpCmpOps = !swpCmpOps;
3257    swpVselOps = !swpVselOps;
3258    CondCode = CondCode == ARMCC::GT ? ARMCC::GE : ARMCC::GT;
3259  }
3260
3261  // 'ordered' is 'anything but unordered', so use the VS condition code and
3262  // swap the VSEL operands.
3263  if (CC == ISD::SETO) {
3264    CondCode = ARMCC::VS;
3265    swpVselOps = true;
3266  }
3267
3268  // 'unordered or not equal' is 'anything but equal', so use the EQ condition
3269  // code and swap the VSEL operands.
3270  if (CC == ISD::SETUNE) {
3271    CondCode = ARMCC::EQ;
3272    swpVselOps = true;
3273  }
3274}
3275
3276SDValue ARMTargetLowering::LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const {
3277  EVT VT = Op.getValueType();
3278  SDValue LHS = Op.getOperand(0);
3279  SDValue RHS = Op.getOperand(1);
3280  ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(4))->get();
3281  SDValue TrueVal = Op.getOperand(2);
3282  SDValue FalseVal = Op.getOperand(3);
3283  SDLoc dl(Op);
3284
3285  if (LHS.getValueType() == MVT::i32) {
3286    // Try to generate VSEL on ARMv8.
3287    // The VSEL instruction can't use all the usual ARM condition
3288    // codes: it only has two bits to select the condition code, so it's
3289    // constrained to use only GE, GT, VS and EQ.
3290    //
3291    // To implement all the various ISD::SETXXX opcodes, we sometimes need to
3292    // swap the operands of the previous compare instruction (effectively
3293    // inverting the compare condition, swapping 'less' and 'greater') and
3294    // sometimes need to swap the operands to the VSEL (which inverts the
3295    // condition in the sense of firing whenever the previous condition didn't)
3296    if (getSubtarget()->hasFPARMv8() && (TrueVal.getValueType() == MVT::f32 ||
3297                                      TrueVal.getValueType() == MVT::f64)) {
3298      ARMCC::CondCodes CondCode = IntCCToARMCC(CC);
3299      if (CondCode == ARMCC::LT || CondCode == ARMCC::LE ||
3300          CondCode == ARMCC::VC || CondCode == ARMCC::NE) {
3301        CC = getInverseCCForVSEL(CC);
3302        std::swap(TrueVal, FalseVal);
3303      }
3304    }
3305
3306    SDValue ARMcc;
3307    SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
3308    SDValue Cmp = getARMCmp(LHS, RHS, CC, ARMcc, DAG, dl);
3309    return DAG.getNode(ARMISD::CMOV, dl, VT, FalseVal, TrueVal, ARMcc, CCR,
3310                       Cmp);
3311  }
3312
3313  ARMCC::CondCodes CondCode, CondCode2;
3314  FPCCToARMCC(CC, CondCode, CondCode2);
3315
3316  // Try to generate VSEL on ARMv8.
3317  if (getSubtarget()->hasFPARMv8() && (TrueVal.getValueType() == MVT::f32 ||
3318                                    TrueVal.getValueType() == MVT::f64)) {
3319    // We can select VMAXNM/VMINNM from a compare followed by a select with the
3320    // same operands, as follows:
3321    //   c = fcmp [ogt, olt, ugt, ult] a, b
3322    //   select c, a, b
3323    // We only do this in unsafe-fp-math, because signed zeros and NaNs are
3324    // handled differently than the original code sequence.
3325    if (getTargetMachine().Options.UnsafeFPMath && LHS == TrueVal &&
3326        RHS == FalseVal) {
3327      if (CC == ISD::SETOGT || CC == ISD::SETUGT)
3328        return DAG.getNode(ARMISD::VMAXNM, dl, VT, TrueVal, FalseVal);
3329      if (CC == ISD::SETOLT || CC == ISD::SETULT)
3330        return DAG.getNode(ARMISD::VMINNM, dl, VT, TrueVal, FalseVal);
3331    }
3332
3333    bool swpCmpOps = false;
3334    bool swpVselOps = false;
3335    checkVSELConstraints(CC, CondCode, swpCmpOps, swpVselOps);
3336
3337    if (CondCode == ARMCC::GT || CondCode == ARMCC::GE ||
3338        CondCode == ARMCC::VS || CondCode == ARMCC::EQ) {
3339      if (swpCmpOps)
3340        std::swap(LHS, RHS);
3341      if (swpVselOps)
3342        std::swap(TrueVal, FalseVal);
3343    }
3344  }
3345
3346  SDValue ARMcc = DAG.getConstant(CondCode, MVT::i32);
3347  SDValue Cmp = getVFPCmp(LHS, RHS, DAG, dl);
3348  SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
3349  SDValue Result = DAG.getNode(ARMISD::CMOV, dl, VT, FalseVal, TrueVal,
3350                               ARMcc, CCR, Cmp);
3351  if (CondCode2 != ARMCC::AL) {
3352    SDValue ARMcc2 = DAG.getConstant(CondCode2, MVT::i32);
3353    // FIXME: Needs another CMP because flag can have but one use.
3354    SDValue Cmp2 = getVFPCmp(LHS, RHS, DAG, dl);
3355    Result = DAG.getNode(ARMISD::CMOV, dl, VT,
3356                         Result, TrueVal, ARMcc2, CCR, Cmp2);
3357  }
3358  return Result;
3359}
3360
3361/// canChangeToInt - Given the fp compare operand, return true if it is suitable
3362/// to morph to an integer compare sequence.
3363static bool canChangeToInt(SDValue Op, bool &SeenZero,
3364                           const ARMSubtarget *Subtarget) {
3365  SDNode *N = Op.getNode();
3366  if (!N->hasOneUse())
3367    // Otherwise it requires moving the value from fp to integer registers.
3368    return false;
3369  if (!N->getNumValues())
3370    return false;
3371  EVT VT = Op.getValueType();
3372  if (VT != MVT::f32 && !Subtarget->isFPBrccSlow())
3373    // f32 case is generally profitable. f64 case only makes sense when vcmpe +
3374    // vmrs are very slow, e.g. cortex-a8.
3375    return false;
3376
3377  if (isFloatingPointZero(Op)) {
3378    SeenZero = true;
3379    return true;
3380  }
3381  return ISD::isNormalLoad(N);
3382}
3383
3384static SDValue bitcastf32Toi32(SDValue Op, SelectionDAG &DAG) {
3385  if (isFloatingPointZero(Op))
3386    return DAG.getConstant(0, MVT::i32);
3387
3388  if (LoadSDNode *Ld = dyn_cast<LoadSDNode>(Op))
3389    return DAG.getLoad(MVT::i32, SDLoc(Op),
3390                       Ld->getChain(), Ld->getBasePtr(), Ld->getPointerInfo(),
3391                       Ld->isVolatile(), Ld->isNonTemporal(),
3392                       Ld->isInvariant(), Ld->getAlignment());
3393
3394  llvm_unreachable("Unknown VFP cmp argument!");
3395}
3396
3397static void expandf64Toi32(SDValue Op, SelectionDAG &DAG,
3398                           SDValue &RetVal1, SDValue &RetVal2) {
3399  if (isFloatingPointZero(Op)) {
3400    RetVal1 = DAG.getConstant(0, MVT::i32);
3401    RetVal2 = DAG.getConstant(0, MVT::i32);
3402    return;
3403  }
3404
3405  if (LoadSDNode *Ld = dyn_cast<LoadSDNode>(Op)) {
3406    SDValue Ptr = Ld->getBasePtr();
3407    RetVal1 = DAG.getLoad(MVT::i32, SDLoc(Op),
3408                          Ld->getChain(), Ptr,
3409                          Ld->getPointerInfo(),
3410                          Ld->isVolatile(), Ld->isNonTemporal(),
3411                          Ld->isInvariant(), Ld->getAlignment());
3412
3413    EVT PtrType = Ptr.getValueType();
3414    unsigned NewAlign = MinAlign(Ld->getAlignment(), 4);
3415    SDValue NewPtr = DAG.getNode(ISD::ADD, SDLoc(Op),
3416                                 PtrType, Ptr, DAG.getConstant(4, PtrType));
3417    RetVal2 = DAG.getLoad(MVT::i32, SDLoc(Op),
3418                          Ld->getChain(), NewPtr,
3419                          Ld->getPointerInfo().getWithOffset(4),
3420                          Ld->isVolatile(), Ld->isNonTemporal(),
3421                          Ld->isInvariant(), NewAlign);
3422    return;
3423  }
3424
3425  llvm_unreachable("Unknown VFP cmp argument!");
3426}
3427
3428/// OptimizeVFPBrcond - With -enable-unsafe-fp-math, it's legal to optimize some
3429/// f32 and even f64 comparisons to integer ones.
3430SDValue
3431ARMTargetLowering::OptimizeVFPBrcond(SDValue Op, SelectionDAG &DAG) const {
3432  SDValue Chain = Op.getOperand(0);
3433  ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(1))->get();
3434  SDValue LHS = Op.getOperand(2);
3435  SDValue RHS = Op.getOperand(3);
3436  SDValue Dest = Op.getOperand(4);
3437  SDLoc dl(Op);
3438
3439  bool LHSSeenZero = false;
3440  bool LHSOk = canChangeToInt(LHS, LHSSeenZero, Subtarget);
3441  bool RHSSeenZero = false;
3442  bool RHSOk = canChangeToInt(RHS, RHSSeenZero, Subtarget);
3443  if (LHSOk && RHSOk && (LHSSeenZero || RHSSeenZero)) {
3444    // If unsafe fp math optimization is enabled and there are no other uses of
3445    // the CMP operands, and the condition code is EQ or NE, we can optimize it
3446    // to an integer comparison.
3447    if (CC == ISD::SETOEQ)
3448      CC = ISD::SETEQ;
3449    else if (CC == ISD::SETUNE)
3450      CC = ISD::SETNE;
3451
3452    SDValue Mask = DAG.getConstant(0x7fffffff, MVT::i32);
3453    SDValue ARMcc;
3454    if (LHS.getValueType() == MVT::f32) {
3455      LHS = DAG.getNode(ISD::AND, dl, MVT::i32,
3456                        bitcastf32Toi32(LHS, DAG), Mask);
3457      RHS = DAG.getNode(ISD::AND, dl, MVT::i32,
3458                        bitcastf32Toi32(RHS, DAG), Mask);
3459      SDValue Cmp = getARMCmp(LHS, RHS, CC, ARMcc, DAG, dl);
3460      SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
3461      return DAG.getNode(ARMISD::BRCOND, dl, MVT::Other,
3462                         Chain, Dest, ARMcc, CCR, Cmp);
3463    }
3464
3465    SDValue LHS1, LHS2;
3466    SDValue RHS1, RHS2;
3467    expandf64Toi32(LHS, DAG, LHS1, LHS2);
3468    expandf64Toi32(RHS, DAG, RHS1, RHS2);
3469    LHS2 = DAG.getNode(ISD::AND, dl, MVT::i32, LHS2, Mask);
3470    RHS2 = DAG.getNode(ISD::AND, dl, MVT::i32, RHS2, Mask);
3471    ARMCC::CondCodes CondCode = IntCCToARMCC(CC);
3472    ARMcc = DAG.getConstant(CondCode, MVT::i32);
3473    SDVTList VTList = DAG.getVTList(MVT::Other, MVT::Glue);
3474    SDValue Ops[] = { Chain, ARMcc, LHS1, LHS2, RHS1, RHS2, Dest };
3475    return DAG.getNode(ARMISD::BCC_i64, dl, VTList, Ops, 7);
3476  }
3477
3478  return SDValue();
3479}
3480
3481SDValue ARMTargetLowering::LowerBR_CC(SDValue Op, SelectionDAG &DAG) const {
3482  SDValue Chain = Op.getOperand(0);
3483  ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(1))->get();
3484  SDValue LHS = Op.getOperand(2);
3485  SDValue RHS = Op.getOperand(3);
3486  SDValue Dest = Op.getOperand(4);
3487  SDLoc dl(Op);
3488
3489  if (LHS.getValueType() == MVT::i32) {
3490    SDValue ARMcc;
3491    SDValue Cmp = getARMCmp(LHS, RHS, CC, ARMcc, DAG, dl);
3492    SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
3493    return DAG.getNode(ARMISD::BRCOND, dl, MVT::Other,
3494                       Chain, Dest, ARMcc, CCR, Cmp);
3495  }
3496
3497  assert(LHS.getValueType() == MVT::f32 || LHS.getValueType() == MVT::f64);
3498
3499  if (getTargetMachine().Options.UnsafeFPMath &&
3500      (CC == ISD::SETEQ || CC == ISD::SETOEQ ||
3501       CC == ISD::SETNE || CC == ISD::SETUNE)) {
3502    SDValue Result = OptimizeVFPBrcond(Op, DAG);
3503    if (Result.getNode())
3504      return Result;
3505  }
3506
3507  ARMCC::CondCodes CondCode, CondCode2;
3508  FPCCToARMCC(CC, CondCode, CondCode2);
3509
3510  SDValue ARMcc = DAG.getConstant(CondCode, MVT::i32);
3511  SDValue Cmp = getVFPCmp(LHS, RHS, DAG, dl);
3512  SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
3513  SDVTList VTList = DAG.getVTList(MVT::Other, MVT::Glue);
3514  SDValue Ops[] = { Chain, Dest, ARMcc, CCR, Cmp };
3515  SDValue Res = DAG.getNode(ARMISD::BRCOND, dl, VTList, Ops, 5);
3516  if (CondCode2 != ARMCC::AL) {
3517    ARMcc = DAG.getConstant(CondCode2, MVT::i32);
3518    SDValue Ops[] = { Res, Dest, ARMcc, CCR, Res.getValue(1) };
3519    Res = DAG.getNode(ARMISD::BRCOND, dl, VTList, Ops, 5);
3520  }
3521  return Res;
3522}
3523
3524SDValue ARMTargetLowering::LowerBR_JT(SDValue Op, SelectionDAG &DAG) const {
3525  SDValue Chain = Op.getOperand(0);
3526  SDValue Table = Op.getOperand(1);
3527  SDValue Index = Op.getOperand(2);
3528  SDLoc dl(Op);
3529
3530  EVT PTy = getPointerTy();
3531  JumpTableSDNode *JT = cast<JumpTableSDNode>(Table);
3532  ARMFunctionInfo *AFI = DAG.getMachineFunction().getInfo<ARMFunctionInfo>();
3533  SDValue UId = DAG.getConstant(AFI->createJumpTableUId(), PTy);
3534  SDValue JTI = DAG.getTargetJumpTable(JT->getIndex(), PTy);
3535  Table = DAG.getNode(ARMISD::WrapperJT, dl, MVT::i32, JTI, UId);
3536  Index = DAG.getNode(ISD::MUL, dl, PTy, Index, DAG.getConstant(4, PTy));
3537  SDValue Addr = DAG.getNode(ISD::ADD, dl, PTy, Index, Table);
3538  if (Subtarget->isThumb2()) {
3539    // Thumb2 uses a two-level jump. That is, it jumps into the jump table
3540    // which does another jump to the destination. This also makes it easier
3541    // to translate it to TBB / TBH later.
3542    // FIXME: This might not work if the function is extremely large.
3543    return DAG.getNode(ARMISD::BR2_JT, dl, MVT::Other, Chain,
3544                       Addr, Op.getOperand(2), JTI, UId);
3545  }
3546  if (getTargetMachine().getRelocationModel() == Reloc::PIC_) {
3547    Addr = DAG.getLoad((EVT)MVT::i32, dl, Chain, Addr,
3548                       MachinePointerInfo::getJumpTable(),
3549                       false, false, false, 0);
3550    Chain = Addr.getValue(1);
3551    Addr = DAG.getNode(ISD::ADD, dl, PTy, Addr, Table);
3552    return DAG.getNode(ARMISD::BR_JT, dl, MVT::Other, Chain, Addr, JTI, UId);
3553  } else {
3554    Addr = DAG.getLoad(PTy, dl, Chain, Addr,
3555                       MachinePointerInfo::getJumpTable(),
3556                       false, false, false, 0);
3557    Chain = Addr.getValue(1);
3558    return DAG.getNode(ARMISD::BR_JT, dl, MVT::Other, Chain, Addr, JTI, UId);
3559  }
3560}
3561
3562static SDValue LowerVectorFP_TO_INT(SDValue Op, SelectionDAG &DAG) {
3563  EVT VT = Op.getValueType();
3564  SDLoc dl(Op);
3565
3566  if (Op.getValueType().getVectorElementType() == MVT::i32) {
3567    if (Op.getOperand(0).getValueType().getVectorElementType() == MVT::f32)
3568      return Op;
3569    return DAG.UnrollVectorOp(Op.getNode());
3570  }
3571
3572  assert(Op.getOperand(0).getValueType() == MVT::v4f32 &&
3573         "Invalid type for custom lowering!");
3574  if (VT != MVT::v4i16)
3575    return DAG.UnrollVectorOp(Op.getNode());
3576
3577  Op = DAG.getNode(Op.getOpcode(), dl, MVT::v4i32, Op.getOperand(0));
3578  return DAG.getNode(ISD::TRUNCATE, dl, VT, Op);
3579}
3580
3581static SDValue LowerFP_TO_INT(SDValue Op, SelectionDAG &DAG) {
3582  EVT VT = Op.getValueType();
3583  if (VT.isVector())
3584    return LowerVectorFP_TO_INT(Op, DAG);
3585
3586  SDLoc dl(Op);
3587  unsigned Opc;
3588
3589  switch (Op.getOpcode()) {
3590  default: llvm_unreachable("Invalid opcode!");
3591  case ISD::FP_TO_SINT:
3592    Opc = ARMISD::FTOSI;
3593    break;
3594  case ISD::FP_TO_UINT:
3595    Opc = ARMISD::FTOUI;
3596    break;
3597  }
3598  Op = DAG.getNode(Opc, dl, MVT::f32, Op.getOperand(0));
3599  return DAG.getNode(ISD::BITCAST, dl, MVT::i32, Op);
3600}
3601
3602static SDValue LowerVectorINT_TO_FP(SDValue Op, SelectionDAG &DAG) {
3603  EVT VT = Op.getValueType();
3604  SDLoc dl(Op);
3605
3606  if (Op.getOperand(0).getValueType().getVectorElementType() == MVT::i32) {
3607    if (VT.getVectorElementType() == MVT::f32)
3608      return Op;
3609    return DAG.UnrollVectorOp(Op.getNode());
3610  }
3611
3612  assert(Op.getOperand(0).getValueType() == MVT::v4i16 &&
3613         "Invalid type for custom lowering!");
3614  if (VT != MVT::v4f32)
3615    return DAG.UnrollVectorOp(Op.getNode());
3616
3617  unsigned CastOpc;
3618  unsigned Opc;
3619  switch (Op.getOpcode()) {
3620  default: llvm_unreachable("Invalid opcode!");
3621  case ISD::SINT_TO_FP:
3622    CastOpc = ISD::SIGN_EXTEND;
3623    Opc = ISD::SINT_TO_FP;
3624    break;
3625  case ISD::UINT_TO_FP:
3626    CastOpc = ISD::ZERO_EXTEND;
3627    Opc = ISD::UINT_TO_FP;
3628    break;
3629  }
3630
3631  Op = DAG.getNode(CastOpc, dl, MVT::v4i32, Op.getOperand(0));
3632  return DAG.getNode(Opc, dl, VT, Op);
3633}
3634
3635static SDValue LowerINT_TO_FP(SDValue Op, SelectionDAG &DAG) {
3636  EVT VT = Op.getValueType();
3637  if (VT.isVector())
3638    return LowerVectorINT_TO_FP(Op, DAG);
3639
3640  SDLoc dl(Op);
3641  unsigned Opc;
3642
3643  switch (Op.getOpcode()) {
3644  default: llvm_unreachable("Invalid opcode!");
3645  case ISD::SINT_TO_FP:
3646    Opc = ARMISD::SITOF;
3647    break;
3648  case ISD::UINT_TO_FP:
3649    Opc = ARMISD::UITOF;
3650    break;
3651  }
3652
3653  Op = DAG.getNode(ISD::BITCAST, dl, MVT::f32, Op.getOperand(0));
3654  return DAG.getNode(Opc, dl, VT, Op);
3655}
3656
3657SDValue ARMTargetLowering::LowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG) const {
3658  // Implement fcopysign with a fabs and a conditional fneg.
3659  SDValue Tmp0 = Op.getOperand(0);
3660  SDValue Tmp1 = Op.getOperand(1);
3661  SDLoc dl(Op);
3662  EVT VT = Op.getValueType();
3663  EVT SrcVT = Tmp1.getValueType();
3664  bool InGPR = Tmp0.getOpcode() == ISD::BITCAST ||
3665    Tmp0.getOpcode() == ARMISD::VMOVDRR;
3666  bool UseNEON = !InGPR && Subtarget->hasNEON();
3667
3668  if (UseNEON) {
3669    // Use VBSL to copy the sign bit.
3670    unsigned EncodedVal = ARM_AM::createNEONModImm(0x6, 0x80);
3671    SDValue Mask = DAG.getNode(ARMISD::VMOVIMM, dl, MVT::v2i32,
3672                               DAG.getTargetConstant(EncodedVal, MVT::i32));
3673    EVT OpVT = (VT == MVT::f32) ? MVT::v2i32 : MVT::v1i64;
3674    if (VT == MVT::f64)
3675      Mask = DAG.getNode(ARMISD::VSHL, dl, OpVT,
3676                         DAG.getNode(ISD::BITCAST, dl, OpVT, Mask),
3677                         DAG.getConstant(32, MVT::i32));
3678    else /*if (VT == MVT::f32)*/
3679      Tmp0 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2f32, Tmp0);
3680    if (SrcVT == MVT::f32) {
3681      Tmp1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2f32, Tmp1);
3682      if (VT == MVT::f64)
3683        Tmp1 = DAG.getNode(ARMISD::VSHL, dl, OpVT,
3684                           DAG.getNode(ISD::BITCAST, dl, OpVT, Tmp1),
3685                           DAG.getConstant(32, MVT::i32));
3686    } else if (VT == MVT::f32)
3687      Tmp1 = DAG.getNode(ARMISD::VSHRu, dl, MVT::v1i64,
3688                         DAG.getNode(ISD::BITCAST, dl, MVT::v1i64, Tmp1),
3689                         DAG.getConstant(32, MVT::i32));
3690    Tmp0 = DAG.getNode(ISD::BITCAST, dl, OpVT, Tmp0);
3691    Tmp1 = DAG.getNode(ISD::BITCAST, dl, OpVT, Tmp1);
3692
3693    SDValue AllOnes = DAG.getTargetConstant(ARM_AM::createNEONModImm(0xe, 0xff),
3694                                            MVT::i32);
3695    AllOnes = DAG.getNode(ARMISD::VMOVIMM, dl, MVT::v8i8, AllOnes);
3696    SDValue MaskNot = DAG.getNode(ISD::XOR, dl, OpVT, Mask,
3697                                  DAG.getNode(ISD::BITCAST, dl, OpVT, AllOnes));
3698
3699    SDValue Res = DAG.getNode(ISD::OR, dl, OpVT,
3700                              DAG.getNode(ISD::AND, dl, OpVT, Tmp1, Mask),
3701                              DAG.getNode(ISD::AND, dl, OpVT, Tmp0, MaskNot));
3702    if (VT == MVT::f32) {
3703      Res = DAG.getNode(ISD::BITCAST, dl, MVT::v2f32, Res);
3704      Res = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f32, Res,
3705                        DAG.getConstant(0, MVT::i32));
3706    } else {
3707      Res = DAG.getNode(ISD::BITCAST, dl, MVT::f64, Res);
3708    }
3709
3710    return Res;
3711  }
3712
3713  // Bitcast operand 1 to i32.
3714  if (SrcVT == MVT::f64)
3715    Tmp1 = DAG.getNode(ARMISD::VMOVRRD, dl, DAG.getVTList(MVT::i32, MVT::i32),
3716                       &Tmp1, 1).getValue(1);
3717  Tmp1 = DAG.getNode(ISD::BITCAST, dl, MVT::i32, Tmp1);
3718
3719  // Or in the signbit with integer operations.
3720  SDValue Mask1 = DAG.getConstant(0x80000000, MVT::i32);
3721  SDValue Mask2 = DAG.getConstant(0x7fffffff, MVT::i32);
3722  Tmp1 = DAG.getNode(ISD::AND, dl, MVT::i32, Tmp1, Mask1);
3723  if (VT == MVT::f32) {
3724    Tmp0 = DAG.getNode(ISD::AND, dl, MVT::i32,
3725                       DAG.getNode(ISD::BITCAST, dl, MVT::i32, Tmp0), Mask2);
3726    return DAG.getNode(ISD::BITCAST, dl, MVT::f32,
3727                       DAG.getNode(ISD::OR, dl, MVT::i32, Tmp0, Tmp1));
3728  }
3729
3730  // f64: Or the high part with signbit and then combine two parts.
3731  Tmp0 = DAG.getNode(ARMISD::VMOVRRD, dl, DAG.getVTList(MVT::i32, MVT::i32),
3732                     &Tmp0, 1);
3733  SDValue Lo = Tmp0.getValue(0);
3734  SDValue Hi = DAG.getNode(ISD::AND, dl, MVT::i32, Tmp0.getValue(1), Mask2);
3735  Hi = DAG.getNode(ISD::OR, dl, MVT::i32, Hi, Tmp1);
3736  return DAG.getNode(ARMISD::VMOVDRR, dl, MVT::f64, Lo, Hi);
3737}
3738
3739SDValue ARMTargetLowering::LowerRETURNADDR(SDValue Op, SelectionDAG &DAG) const{
3740  MachineFunction &MF = DAG.getMachineFunction();
3741  MachineFrameInfo *MFI = MF.getFrameInfo();
3742  MFI->setReturnAddressIsTaken(true);
3743
3744  if (verifyReturnAddressArgumentIsConstant(Op, DAG))
3745    return SDValue();
3746
3747  EVT VT = Op.getValueType();
3748  SDLoc dl(Op);
3749  unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
3750  if (Depth) {
3751    SDValue FrameAddr = LowerFRAMEADDR(Op, DAG);
3752    SDValue Offset = DAG.getConstant(4, MVT::i32);
3753    return DAG.getLoad(VT, dl, DAG.getEntryNode(),
3754                       DAG.getNode(ISD::ADD, dl, VT, FrameAddr, Offset),
3755                       MachinePointerInfo(), false, false, false, 0);
3756  }
3757
3758  // Return LR, which contains the return address. Mark it an implicit live-in.
3759  unsigned Reg = MF.addLiveIn(ARM::LR, getRegClassFor(MVT::i32));
3760  return DAG.getCopyFromReg(DAG.getEntryNode(), dl, Reg, VT);
3761}
3762
3763SDValue ARMTargetLowering::LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const {
3764  MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
3765  MFI->setFrameAddressIsTaken(true);
3766
3767  EVT VT = Op.getValueType();
3768  SDLoc dl(Op);  // FIXME probably not meaningful
3769  unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
3770  unsigned FrameReg = (Subtarget->isThumb() || Subtarget->isTargetMachO())
3771    ? ARM::R7 : ARM::R11;
3772  SDValue FrameAddr = DAG.getCopyFromReg(DAG.getEntryNode(), dl, FrameReg, VT);
3773  while (Depth--)
3774    FrameAddr = DAG.getLoad(VT, dl, DAG.getEntryNode(), FrameAddr,
3775                            MachinePointerInfo(),
3776                            false, false, false, 0);
3777  return FrameAddr;
3778}
3779
3780/// ExpandBITCAST - If the target supports VFP, this function is called to
3781/// expand a bit convert where either the source or destination type is i64 to
3782/// use a VMOVDRR or VMOVRRD node.  This should not be done when the non-i64
3783/// operand type is illegal (e.g., v2f32 for a target that doesn't support
3784/// vectors), since the legalizer won't know what to do with that.
3785static SDValue ExpandBITCAST(SDNode *N, SelectionDAG &DAG) {
3786  const TargetLowering &TLI = DAG.getTargetLoweringInfo();
3787  SDLoc dl(N);
3788  SDValue Op = N->getOperand(0);
3789
3790  // This function is only supposed to be called for i64 types, either as the
3791  // source or destination of the bit convert.
3792  EVT SrcVT = Op.getValueType();
3793  EVT DstVT = N->getValueType(0);
3794  assert((SrcVT == MVT::i64 || DstVT == MVT::i64) &&
3795         "ExpandBITCAST called for non-i64 type");
3796
3797  // Turn i64->f64 into VMOVDRR.
3798  if (SrcVT == MVT::i64 && TLI.isTypeLegal(DstVT)) {
3799    SDValue Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, Op,
3800                             DAG.getConstant(0, MVT::i32));
3801    SDValue Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, Op,
3802                             DAG.getConstant(1, MVT::i32));
3803    return DAG.getNode(ISD::BITCAST, dl, DstVT,
3804                       DAG.getNode(ARMISD::VMOVDRR, dl, MVT::f64, Lo, Hi));
3805  }
3806
3807  // Turn f64->i64 into VMOVRRD.
3808  if (DstVT == MVT::i64 && TLI.isTypeLegal(SrcVT)) {
3809    SDValue Cvt = DAG.getNode(ARMISD::VMOVRRD, dl,
3810                              DAG.getVTList(MVT::i32, MVT::i32), &Op, 1);
3811    // Merge the pieces into a single i64 value.
3812    return DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, Cvt, Cvt.getValue(1));
3813  }
3814
3815  return SDValue();
3816}
3817
3818/// getZeroVector - Returns a vector of specified type with all zero elements.
3819/// Zero vectors are used to represent vector negation and in those cases
3820/// will be implemented with the NEON VNEG instruction.  However, VNEG does
3821/// not support i64 elements, so sometimes the zero vectors will need to be
3822/// explicitly constructed.  Regardless, use a canonical VMOV to create the
3823/// zero vector.
3824static SDValue getZeroVector(EVT VT, SelectionDAG &DAG, SDLoc dl) {
3825  assert(VT.isVector() && "Expected a vector type");
3826  // The canonical modified immediate encoding of a zero vector is....0!
3827  SDValue EncodedVal = DAG.getTargetConstant(0, MVT::i32);
3828  EVT VmovVT = VT.is128BitVector() ? MVT::v4i32 : MVT::v2i32;
3829  SDValue Vmov = DAG.getNode(ARMISD::VMOVIMM, dl, VmovVT, EncodedVal);
3830  return DAG.getNode(ISD::BITCAST, dl, VT, Vmov);
3831}
3832
3833/// LowerShiftRightParts - Lower SRA_PARTS, which returns two
3834/// i32 values and take a 2 x i32 value to shift plus a shift amount.
3835SDValue ARMTargetLowering::LowerShiftRightParts(SDValue Op,
3836                                                SelectionDAG &DAG) const {
3837  assert(Op.getNumOperands() == 3 && "Not a double-shift!");
3838  EVT VT = Op.getValueType();
3839  unsigned VTBits = VT.getSizeInBits();
3840  SDLoc dl(Op);
3841  SDValue ShOpLo = Op.getOperand(0);
3842  SDValue ShOpHi = Op.getOperand(1);
3843  SDValue ShAmt  = Op.getOperand(2);
3844  SDValue ARMcc;
3845  unsigned Opc = (Op.getOpcode() == ISD::SRA_PARTS) ? ISD::SRA : ISD::SRL;
3846
3847  assert(Op.getOpcode() == ISD::SRA_PARTS || Op.getOpcode() == ISD::SRL_PARTS);
3848
3849  SDValue RevShAmt = DAG.getNode(ISD::SUB, dl, MVT::i32,
3850                                 DAG.getConstant(VTBits, MVT::i32), ShAmt);
3851  SDValue Tmp1 = DAG.getNode(ISD::SRL, dl, VT, ShOpLo, ShAmt);
3852  SDValue ExtraShAmt = DAG.getNode(ISD::SUB, dl, MVT::i32, ShAmt,
3853                                   DAG.getConstant(VTBits, MVT::i32));
3854  SDValue Tmp2 = DAG.getNode(ISD::SHL, dl, VT, ShOpHi, RevShAmt);
3855  SDValue FalseVal = DAG.getNode(ISD::OR, dl, VT, Tmp1, Tmp2);
3856  SDValue TrueVal = DAG.getNode(Opc, dl, VT, ShOpHi, ExtraShAmt);
3857
3858  SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
3859  SDValue Cmp = getARMCmp(ExtraShAmt, DAG.getConstant(0, MVT::i32), ISD::SETGE,
3860                          ARMcc, DAG, dl);
3861  SDValue Hi = DAG.getNode(Opc, dl, VT, ShOpHi, ShAmt);
3862  SDValue Lo = DAG.getNode(ARMISD::CMOV, dl, VT, FalseVal, TrueVal, ARMcc,
3863                           CCR, Cmp);
3864
3865  SDValue Ops[2] = { Lo, Hi };
3866  return DAG.getMergeValues(Ops, 2, dl);
3867}
3868
3869/// LowerShiftLeftParts - Lower SHL_PARTS, which returns two
3870/// i32 values and take a 2 x i32 value to shift plus a shift amount.
3871SDValue ARMTargetLowering::LowerShiftLeftParts(SDValue Op,
3872                                               SelectionDAG &DAG) const {
3873  assert(Op.getNumOperands() == 3 && "Not a double-shift!");
3874  EVT VT = Op.getValueType();
3875  unsigned VTBits = VT.getSizeInBits();
3876  SDLoc dl(Op);
3877  SDValue ShOpLo = Op.getOperand(0);
3878  SDValue ShOpHi = Op.getOperand(1);
3879  SDValue ShAmt  = Op.getOperand(2);
3880  SDValue ARMcc;
3881
3882  assert(Op.getOpcode() == ISD::SHL_PARTS);
3883  SDValue RevShAmt = DAG.getNode(ISD::SUB, dl, MVT::i32,
3884                                 DAG.getConstant(VTBits, MVT::i32), ShAmt);
3885  SDValue Tmp1 = DAG.getNode(ISD::SRL, dl, VT, ShOpLo, RevShAmt);
3886  SDValue ExtraShAmt = DAG.getNode(ISD::SUB, dl, MVT::i32, ShAmt,
3887                                   DAG.getConstant(VTBits, MVT::i32));
3888  SDValue Tmp2 = DAG.getNode(ISD::SHL, dl, VT, ShOpHi, ShAmt);
3889  SDValue Tmp3 = DAG.getNode(ISD::SHL, dl, VT, ShOpLo, ExtraShAmt);
3890
3891  SDValue FalseVal = DAG.getNode(ISD::OR, dl, VT, Tmp1, Tmp2);
3892  SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
3893  SDValue Cmp = getARMCmp(ExtraShAmt, DAG.getConstant(0, MVT::i32), ISD::SETGE,
3894                          ARMcc, DAG, dl);
3895  SDValue Lo = DAG.getNode(ISD::SHL, dl, VT, ShOpLo, ShAmt);
3896  SDValue Hi = DAG.getNode(ARMISD::CMOV, dl, VT, FalseVal, Tmp3, ARMcc,
3897                           CCR, Cmp);
3898
3899  SDValue Ops[2] = { Lo, Hi };
3900  return DAG.getMergeValues(Ops, 2, dl);
3901}
3902
3903SDValue ARMTargetLowering::LowerFLT_ROUNDS_(SDValue Op,
3904                                            SelectionDAG &DAG) const {
3905  // The rounding mode is in bits 23:22 of the FPSCR.
3906  // The ARM rounding mode value to FLT_ROUNDS mapping is 0->1, 1->2, 2->3, 3->0
3907  // The formula we use to implement this is (((FPSCR + 1 << 22) >> 22) & 3)
3908  // so that the shift + and get folded into a bitfield extract.
3909  SDLoc dl(Op);
3910  SDValue FPSCR = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, MVT::i32,
3911                              DAG.getConstant(Intrinsic::arm_get_fpscr,
3912                                              MVT::i32));
3913  SDValue FltRounds = DAG.getNode(ISD::ADD, dl, MVT::i32, FPSCR,
3914                                  DAG.getConstant(1U << 22, MVT::i32));
3915  SDValue RMODE = DAG.getNode(ISD::SRL, dl, MVT::i32, FltRounds,
3916                              DAG.getConstant(22, MVT::i32));
3917  return DAG.getNode(ISD::AND, dl, MVT::i32, RMODE,
3918                     DAG.getConstant(3, MVT::i32));
3919}
3920
3921static SDValue LowerCTTZ(SDNode *N, SelectionDAG &DAG,
3922                         const ARMSubtarget *ST) {
3923  EVT VT = N->getValueType(0);
3924  SDLoc dl(N);
3925
3926  if (!ST->hasV6T2Ops())
3927    return SDValue();
3928
3929  SDValue rbit = DAG.getNode(ARMISD::RBIT, dl, VT, N->getOperand(0));
3930  return DAG.getNode(ISD::CTLZ, dl, VT, rbit);
3931}
3932
3933/// getCTPOP16BitCounts - Returns a v8i8/v16i8 vector containing the bit-count
3934/// for each 16-bit element from operand, repeated.  The basic idea is to
3935/// leverage vcnt to get the 8-bit counts, gather and add the results.
3936///
3937/// Trace for v4i16:
3938/// input    = [v0    v1    v2    v3   ] (vi 16-bit element)
3939/// cast: N0 = [w0 w1 w2 w3 w4 w5 w6 w7] (v0 = [w0 w1], wi 8-bit element)
3940/// vcnt: N1 = [b0 b1 b2 b3 b4 b5 b6 b7] (bi = bit-count of 8-bit element wi)
3941/// vrev: N2 = [b1 b0 b3 b2 b5 b4 b7 b6]
3942///            [b0 b1 b2 b3 b4 b5 b6 b7]
3943///           +[b1 b0 b3 b2 b5 b4 b7 b6]
3944/// N3=N1+N2 = [k0 k0 k1 k1 k2 k2 k3 k3] (k0 = b0+b1 = bit-count of 16-bit v0,
3945/// vuzp:    = [k0 k1 k2 k3 k0 k1 k2 k3]  each ki is 8-bits)
3946static SDValue getCTPOP16BitCounts(SDNode *N, SelectionDAG &DAG) {
3947  EVT VT = N->getValueType(0);
3948  SDLoc DL(N);
3949
3950  EVT VT8Bit = VT.is64BitVector() ? MVT::v8i8 : MVT::v16i8;
3951  SDValue N0 = DAG.getNode(ISD::BITCAST, DL, VT8Bit, N->getOperand(0));
3952  SDValue N1 = DAG.getNode(ISD::CTPOP, DL, VT8Bit, N0);
3953  SDValue N2 = DAG.getNode(ARMISD::VREV16, DL, VT8Bit, N1);
3954  SDValue N3 = DAG.getNode(ISD::ADD, DL, VT8Bit, N1, N2);
3955  return DAG.getNode(ARMISD::VUZP, DL, VT8Bit, N3, N3);
3956}
3957
3958/// lowerCTPOP16BitElements - Returns a v4i16/v8i16 vector containing the
3959/// bit-count for each 16-bit element from the operand.  We need slightly
3960/// different sequencing for v4i16 and v8i16 to stay within NEON's available
3961/// 64/128-bit registers.
3962///
3963/// Trace for v4i16:
3964/// input           = [v0    v1    v2    v3    ] (vi 16-bit element)
3965/// v8i8: BitCounts = [k0 k1 k2 k3 k0 k1 k2 k3 ] (ki is the bit-count of vi)
3966/// v8i16:Extended  = [k0    k1    k2    k3    k0    k1    k2    k3    ]
3967/// v4i16:Extracted = [k0    k1    k2    k3    ]
3968static SDValue lowerCTPOP16BitElements(SDNode *N, SelectionDAG &DAG) {
3969  EVT VT = N->getValueType(0);
3970  SDLoc DL(N);
3971
3972  SDValue BitCounts = getCTPOP16BitCounts(N, DAG);
3973  if (VT.is64BitVector()) {
3974    SDValue Extended = DAG.getNode(ISD::ZERO_EXTEND, DL, MVT::v8i16, BitCounts);
3975    return DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v4i16, Extended,
3976                       DAG.getIntPtrConstant(0));
3977  } else {
3978    SDValue Extracted = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v8i8,
3979                                    BitCounts, DAG.getIntPtrConstant(0));
3980    return DAG.getNode(ISD::ZERO_EXTEND, DL, MVT::v8i16, Extracted);
3981  }
3982}
3983
3984/// lowerCTPOP32BitElements - Returns a v2i32/v4i32 vector containing the
3985/// bit-count for each 32-bit element from the operand.  The idea here is
3986/// to split the vector into 16-bit elements, leverage the 16-bit count
3987/// routine, and then combine the results.
3988///
3989/// Trace for v2i32 (v4i32 similar with Extracted/Extended exchanged):
3990/// input    = [v0    v1    ] (vi: 32-bit elements)
3991/// Bitcast  = [w0 w1 w2 w3 ] (wi: 16-bit elements, v0 = [w0 w1])
3992/// Counts16 = [k0 k1 k2 k3 ] (ki: 16-bit elements, bit-count of wi)
3993/// vrev: N0 = [k1 k0 k3 k2 ]
3994///            [k0 k1 k2 k3 ]
3995///       N1 =+[k1 k0 k3 k2 ]
3996///            [k0 k2 k1 k3 ]
3997///       N2 =+[k1 k3 k0 k2 ]
3998///            [k0    k2    k1    k3    ]
3999/// Extended =+[k1    k3    k0    k2    ]
4000///            [k0    k2    ]
4001/// Extracted=+[k1    k3    ]
4002///
4003static SDValue lowerCTPOP32BitElements(SDNode *N, SelectionDAG &DAG) {
4004  EVT VT = N->getValueType(0);
4005  SDLoc DL(N);
4006
4007  EVT VT16Bit = VT.is64BitVector() ? MVT::v4i16 : MVT::v8i16;
4008
4009  SDValue Bitcast = DAG.getNode(ISD::BITCAST, DL, VT16Bit, N->getOperand(0));
4010  SDValue Counts16 = lowerCTPOP16BitElements(Bitcast.getNode(), DAG);
4011  SDValue N0 = DAG.getNode(ARMISD::VREV32, DL, VT16Bit, Counts16);
4012  SDValue N1 = DAG.getNode(ISD::ADD, DL, VT16Bit, Counts16, N0);
4013  SDValue N2 = DAG.getNode(ARMISD::VUZP, DL, VT16Bit, N1, N1);
4014
4015  if (VT.is64BitVector()) {
4016    SDValue Extended = DAG.getNode(ISD::ZERO_EXTEND, DL, MVT::v4i32, N2);
4017    return DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v2i32, Extended,
4018                       DAG.getIntPtrConstant(0));
4019  } else {
4020    SDValue Extracted = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v4i16, N2,
4021                                    DAG.getIntPtrConstant(0));
4022    return DAG.getNode(ISD::ZERO_EXTEND, DL, MVT::v4i32, Extracted);
4023  }
4024}
4025
4026static SDValue LowerCTPOP(SDNode *N, SelectionDAG &DAG,
4027                          const ARMSubtarget *ST) {
4028  EVT VT = N->getValueType(0);
4029
4030  assert(ST->hasNEON() && "Custom ctpop lowering requires NEON.");
4031  assert((VT == MVT::v2i32 || VT == MVT::v4i32 ||
4032          VT == MVT::v4i16 || VT == MVT::v8i16) &&
4033         "Unexpected type for custom ctpop lowering");
4034
4035  if (VT.getVectorElementType() == MVT::i32)
4036    return lowerCTPOP32BitElements(N, DAG);
4037  else
4038    return lowerCTPOP16BitElements(N, DAG);
4039}
4040
4041static SDValue LowerShift(SDNode *N, SelectionDAG &DAG,
4042                          const ARMSubtarget *ST) {
4043  EVT VT = N->getValueType(0);
4044  SDLoc dl(N);
4045
4046  if (!VT.isVector())
4047    return SDValue();
4048
4049  // Lower vector shifts on NEON to use VSHL.
4050  assert(ST->hasNEON() && "unexpected vector shift");
4051
4052  // Left shifts translate directly to the vshiftu intrinsic.
4053  if (N->getOpcode() == ISD::SHL)
4054    return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
4055                       DAG.getConstant(Intrinsic::arm_neon_vshiftu, MVT::i32),
4056                       N->getOperand(0), N->getOperand(1));
4057
4058  assert((N->getOpcode() == ISD::SRA ||
4059          N->getOpcode() == ISD::SRL) && "unexpected vector shift opcode");
4060
4061  // NEON uses the same intrinsics for both left and right shifts.  For
4062  // right shifts, the shift amounts are negative, so negate the vector of
4063  // shift amounts.
4064  EVT ShiftVT = N->getOperand(1).getValueType();
4065  SDValue NegatedCount = DAG.getNode(ISD::SUB, dl, ShiftVT,
4066                                     getZeroVector(ShiftVT, DAG, dl),
4067                                     N->getOperand(1));
4068  Intrinsic::ID vshiftInt = (N->getOpcode() == ISD::SRA ?
4069                             Intrinsic::arm_neon_vshifts :
4070                             Intrinsic::arm_neon_vshiftu);
4071  return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
4072                     DAG.getConstant(vshiftInt, MVT::i32),
4073                     N->getOperand(0), NegatedCount);
4074}
4075
4076static SDValue Expand64BitShift(SDNode *N, SelectionDAG &DAG,
4077                                const ARMSubtarget *ST) {
4078  EVT VT = N->getValueType(0);
4079  SDLoc dl(N);
4080
4081  // We can get here for a node like i32 = ISD::SHL i32, i64
4082  if (VT != MVT::i64)
4083    return SDValue();
4084
4085  assert((N->getOpcode() == ISD::SRL || N->getOpcode() == ISD::SRA) &&
4086         "Unknown shift to lower!");
4087
4088  // We only lower SRA, SRL of 1 here, all others use generic lowering.
4089  if (!isa<ConstantSDNode>(N->getOperand(1)) ||
4090      cast<ConstantSDNode>(N->getOperand(1))->getZExtValue() != 1)
4091    return SDValue();
4092
4093  // If we are in thumb mode, we don't have RRX.
4094  if (ST->isThumb1Only()) return SDValue();
4095
4096  // Okay, we have a 64-bit SRA or SRL of 1.  Lower this to an RRX expr.
4097  SDValue Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, N->getOperand(0),
4098                           DAG.getConstant(0, MVT::i32));
4099  SDValue Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, N->getOperand(0),
4100                           DAG.getConstant(1, MVT::i32));
4101
4102  // First, build a SRA_FLAG/SRL_FLAG op, which shifts the top part by one and
4103  // captures the result into a carry flag.
4104  unsigned Opc = N->getOpcode() == ISD::SRL ? ARMISD::SRL_FLAG:ARMISD::SRA_FLAG;
4105  Hi = DAG.getNode(Opc, dl, DAG.getVTList(MVT::i32, MVT::Glue), &Hi, 1);
4106
4107  // The low part is an ARMISD::RRX operand, which shifts the carry in.
4108  Lo = DAG.getNode(ARMISD::RRX, dl, MVT::i32, Lo, Hi.getValue(1));
4109
4110  // Merge the pieces into a single i64 value.
4111 return DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, Lo, Hi);
4112}
4113
4114static SDValue LowerVSETCC(SDValue Op, SelectionDAG &DAG) {
4115  SDValue TmpOp0, TmpOp1;
4116  bool Invert = false;
4117  bool Swap = false;
4118  unsigned Opc = 0;
4119
4120  SDValue Op0 = Op.getOperand(0);
4121  SDValue Op1 = Op.getOperand(1);
4122  SDValue CC = Op.getOperand(2);
4123  EVT VT = Op.getValueType();
4124  ISD::CondCode SetCCOpcode = cast<CondCodeSDNode>(CC)->get();
4125  SDLoc dl(Op);
4126
4127  if (Op.getOperand(1).getValueType().isFloatingPoint()) {
4128    switch (SetCCOpcode) {
4129    default: llvm_unreachable("Illegal FP comparison");
4130    case ISD::SETUNE:
4131    case ISD::SETNE:  Invert = true; // Fallthrough
4132    case ISD::SETOEQ:
4133    case ISD::SETEQ:  Opc = ARMISD::VCEQ; break;
4134    case ISD::SETOLT:
4135    case ISD::SETLT: Swap = true; // Fallthrough
4136    case ISD::SETOGT:
4137    case ISD::SETGT:  Opc = ARMISD::VCGT; break;
4138    case ISD::SETOLE:
4139    case ISD::SETLE:  Swap = true; // Fallthrough
4140    case ISD::SETOGE:
4141    case ISD::SETGE: Opc = ARMISD::VCGE; break;
4142    case ISD::SETUGE: Swap = true; // Fallthrough
4143    case ISD::SETULE: Invert = true; Opc = ARMISD::VCGT; break;
4144    case ISD::SETUGT: Swap = true; // Fallthrough
4145    case ISD::SETULT: Invert = true; Opc = ARMISD::VCGE; break;
4146    case ISD::SETUEQ: Invert = true; // Fallthrough
4147    case ISD::SETONE:
4148      // Expand this to (OLT | OGT).
4149      TmpOp0 = Op0;
4150      TmpOp1 = Op1;
4151      Opc = ISD::OR;
4152      Op0 = DAG.getNode(ARMISD::VCGT, dl, VT, TmpOp1, TmpOp0);
4153      Op1 = DAG.getNode(ARMISD::VCGT, dl, VT, TmpOp0, TmpOp1);
4154      break;
4155    case ISD::SETUO: Invert = true; // Fallthrough
4156    case ISD::SETO:
4157      // Expand this to (OLT | OGE).
4158      TmpOp0 = Op0;
4159      TmpOp1 = Op1;
4160      Opc = ISD::OR;
4161      Op0 = DAG.getNode(ARMISD::VCGT, dl, VT, TmpOp1, TmpOp0);
4162      Op1 = DAG.getNode(ARMISD::VCGE, dl, VT, TmpOp0, TmpOp1);
4163      break;
4164    }
4165  } else {
4166    // Integer comparisons.
4167    switch (SetCCOpcode) {
4168    default: llvm_unreachable("Illegal integer comparison");
4169    case ISD::SETNE:  Invert = true;
4170    case ISD::SETEQ:  Opc = ARMISD::VCEQ; break;
4171    case ISD::SETLT:  Swap = true;
4172    case ISD::SETGT:  Opc = ARMISD::VCGT; break;
4173    case ISD::SETLE:  Swap = true;
4174    case ISD::SETGE:  Opc = ARMISD::VCGE; break;
4175    case ISD::SETULT: Swap = true;
4176    case ISD::SETUGT: Opc = ARMISD::VCGTU; break;
4177    case ISD::SETULE: Swap = true;
4178    case ISD::SETUGE: Opc = ARMISD::VCGEU; break;
4179    }
4180
4181    // Detect VTST (Vector Test Bits) = icmp ne (and (op0, op1), zero).
4182    if (Opc == ARMISD::VCEQ) {
4183
4184      SDValue AndOp;
4185      if (ISD::isBuildVectorAllZeros(Op1.getNode()))
4186        AndOp = Op0;
4187      else if (ISD::isBuildVectorAllZeros(Op0.getNode()))
4188        AndOp = Op1;
4189
4190      // Ignore bitconvert.
4191      if (AndOp.getNode() && AndOp.getOpcode() == ISD::BITCAST)
4192        AndOp = AndOp.getOperand(0);
4193
4194      if (AndOp.getNode() && AndOp.getOpcode() == ISD::AND) {
4195        Opc = ARMISD::VTST;
4196        Op0 = DAG.getNode(ISD::BITCAST, dl, VT, AndOp.getOperand(0));
4197        Op1 = DAG.getNode(ISD::BITCAST, dl, VT, AndOp.getOperand(1));
4198        Invert = !Invert;
4199      }
4200    }
4201  }
4202
4203  if (Swap)
4204    std::swap(Op0, Op1);
4205
4206  // If one of the operands is a constant vector zero, attempt to fold the
4207  // comparison to a specialized compare-against-zero form.
4208  SDValue SingleOp;
4209  if (ISD::isBuildVectorAllZeros(Op1.getNode()))
4210    SingleOp = Op0;
4211  else if (ISD::isBuildVectorAllZeros(Op0.getNode())) {
4212    if (Opc == ARMISD::VCGE)
4213      Opc = ARMISD::VCLEZ;
4214    else if (Opc == ARMISD::VCGT)
4215      Opc = ARMISD::VCLTZ;
4216    SingleOp = Op1;
4217  }
4218
4219  SDValue Result;
4220  if (SingleOp.getNode()) {
4221    switch (Opc) {
4222    case ARMISD::VCEQ:
4223      Result = DAG.getNode(ARMISD::VCEQZ, dl, VT, SingleOp); break;
4224    case ARMISD::VCGE:
4225      Result = DAG.getNode(ARMISD::VCGEZ, dl, VT, SingleOp); break;
4226    case ARMISD::VCLEZ:
4227      Result = DAG.getNode(ARMISD::VCLEZ, dl, VT, SingleOp); break;
4228    case ARMISD::VCGT:
4229      Result = DAG.getNode(ARMISD::VCGTZ, dl, VT, SingleOp); break;
4230    case ARMISD::VCLTZ:
4231      Result = DAG.getNode(ARMISD::VCLTZ, dl, VT, SingleOp); break;
4232    default:
4233      Result = DAG.getNode(Opc, dl, VT, Op0, Op1);
4234    }
4235  } else {
4236     Result = DAG.getNode(Opc, dl, VT, Op0, Op1);
4237  }
4238
4239  if (Invert)
4240    Result = DAG.getNOT(dl, Result, VT);
4241
4242  return Result;
4243}
4244
4245/// isNEONModifiedImm - Check if the specified splat value corresponds to a
4246/// valid vector constant for a NEON instruction with a "modified immediate"
4247/// operand (e.g., VMOV).  If so, return the encoded value.
4248static SDValue isNEONModifiedImm(uint64_t SplatBits, uint64_t SplatUndef,
4249                                 unsigned SplatBitSize, SelectionDAG &DAG,
4250                                 EVT &VT, bool is128Bits, NEONModImmType type) {
4251  unsigned OpCmode, Imm;
4252
4253  // SplatBitSize is set to the smallest size that splats the vector, so a
4254  // zero vector will always have SplatBitSize == 8.  However, NEON modified
4255  // immediate instructions others than VMOV do not support the 8-bit encoding
4256  // of a zero vector, and the default encoding of zero is supposed to be the
4257  // 32-bit version.
4258  if (SplatBits == 0)
4259    SplatBitSize = 32;
4260
4261  switch (SplatBitSize) {
4262  case 8:
4263    if (type != VMOVModImm)
4264      return SDValue();
4265    // Any 1-byte value is OK.  Op=0, Cmode=1110.
4266    assert((SplatBits & ~0xff) == 0 && "one byte splat value is too big");
4267    OpCmode = 0xe;
4268    Imm = SplatBits;
4269    VT = is128Bits ? MVT::v16i8 : MVT::v8i8;
4270    break;
4271
4272  case 16:
4273    // NEON's 16-bit VMOV supports splat values where only one byte is nonzero.
4274    VT = is128Bits ? MVT::v8i16 : MVT::v4i16;
4275    if ((SplatBits & ~0xff) == 0) {
4276      // Value = 0x00nn: Op=x, Cmode=100x.
4277      OpCmode = 0x8;
4278      Imm = SplatBits;
4279      break;
4280    }
4281    if ((SplatBits & ~0xff00) == 0) {
4282      // Value = 0xnn00: Op=x, Cmode=101x.
4283      OpCmode = 0xa;
4284      Imm = SplatBits >> 8;
4285      break;
4286    }
4287    return SDValue();
4288
4289  case 32:
4290    // NEON's 32-bit VMOV supports splat values where:
4291    // * only one byte is nonzero, or
4292    // * the least significant byte is 0xff and the second byte is nonzero, or
4293    // * the least significant 2 bytes are 0xff and the third is nonzero.
4294    VT = is128Bits ? MVT::v4i32 : MVT::v2i32;
4295    if ((SplatBits & ~0xff) == 0) {
4296      // Value = 0x000000nn: Op=x, Cmode=000x.
4297      OpCmode = 0;
4298      Imm = SplatBits;
4299      break;
4300    }
4301    if ((SplatBits & ~0xff00) == 0) {
4302      // Value = 0x0000nn00: Op=x, Cmode=001x.
4303      OpCmode = 0x2;
4304      Imm = SplatBits >> 8;
4305      break;
4306    }
4307    if ((SplatBits & ~0xff0000) == 0) {
4308      // Value = 0x00nn0000: Op=x, Cmode=010x.
4309      OpCmode = 0x4;
4310      Imm = SplatBits >> 16;
4311      break;
4312    }
4313    if ((SplatBits & ~0xff000000) == 0) {
4314      // Value = 0xnn000000: Op=x, Cmode=011x.
4315      OpCmode = 0x6;
4316      Imm = SplatBits >> 24;
4317      break;
4318    }
4319
4320    // cmode == 0b1100 and cmode == 0b1101 are not supported for VORR or VBIC
4321    if (type == OtherModImm) return SDValue();
4322
4323    if ((SplatBits & ~0xffff) == 0 &&
4324        ((SplatBits | SplatUndef) & 0xff) == 0xff) {
4325      // Value = 0x0000nnff: Op=x, Cmode=1100.
4326      OpCmode = 0xc;
4327      Imm = SplatBits >> 8;
4328      break;
4329    }
4330
4331    if ((SplatBits & ~0xffffff) == 0 &&
4332        ((SplatBits | SplatUndef) & 0xffff) == 0xffff) {
4333      // Value = 0x00nnffff: Op=x, Cmode=1101.
4334      OpCmode = 0xd;
4335      Imm = SplatBits >> 16;
4336      break;
4337    }
4338
4339    // Note: there are a few 32-bit splat values (specifically: 00ffff00,
4340    // ff000000, ff0000ff, and ffff00ff) that are valid for VMOV.I64 but not
4341    // VMOV.I32.  A (very) minor optimization would be to replicate the value
4342    // and fall through here to test for a valid 64-bit splat.  But, then the
4343    // caller would also need to check and handle the change in size.
4344    return SDValue();
4345
4346  case 64: {
4347    if (type != VMOVModImm)
4348      return SDValue();
4349    // NEON has a 64-bit VMOV splat where each byte is either 0 or 0xff.
4350    uint64_t BitMask = 0xff;
4351    uint64_t Val = 0;
4352    unsigned ImmMask = 1;
4353    Imm = 0;
4354    for (int ByteNum = 0; ByteNum < 8; ++ByteNum) {
4355      if (((SplatBits | SplatUndef) & BitMask) == BitMask) {
4356        Val |= BitMask;
4357        Imm |= ImmMask;
4358      } else if ((SplatBits & BitMask) != 0) {
4359        return SDValue();
4360      }
4361      BitMask <<= 8;
4362      ImmMask <<= 1;
4363    }
4364    // Op=1, Cmode=1110.
4365    OpCmode = 0x1e;
4366    VT = is128Bits ? MVT::v2i64 : MVT::v1i64;
4367    break;
4368  }
4369
4370  default:
4371    llvm_unreachable("unexpected size for isNEONModifiedImm");
4372  }
4373
4374  unsigned EncodedVal = ARM_AM::createNEONModImm(OpCmode, Imm);
4375  return DAG.getTargetConstant(EncodedVal, MVT::i32);
4376}
4377
4378SDValue ARMTargetLowering::LowerConstantFP(SDValue Op, SelectionDAG &DAG,
4379                                           const ARMSubtarget *ST) const {
4380  if (!ST->hasVFP3())
4381    return SDValue();
4382
4383  bool IsDouble = Op.getValueType() == MVT::f64;
4384  ConstantFPSDNode *CFP = cast<ConstantFPSDNode>(Op);
4385
4386  // Try splatting with a VMOV.f32...
4387  APFloat FPVal = CFP->getValueAPF();
4388  int ImmVal = IsDouble ? ARM_AM::getFP64Imm(FPVal) : ARM_AM::getFP32Imm(FPVal);
4389
4390  if (ImmVal != -1) {
4391    if (IsDouble || !ST->useNEONForSinglePrecisionFP()) {
4392      // We have code in place to select a valid ConstantFP already, no need to
4393      // do any mangling.
4394      return Op;
4395    }
4396
4397    // It's a float and we are trying to use NEON operations where
4398    // possible. Lower it to a splat followed by an extract.
4399    SDLoc DL(Op);
4400    SDValue NewVal = DAG.getTargetConstant(ImmVal, MVT::i32);
4401    SDValue VecConstant = DAG.getNode(ARMISD::VMOVFPIMM, DL, MVT::v2f32,
4402                                      NewVal);
4403    return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::f32, VecConstant,
4404                       DAG.getConstant(0, MVT::i32));
4405  }
4406
4407  // The rest of our options are NEON only, make sure that's allowed before
4408  // proceeding..
4409  if (!ST->hasNEON() || (!IsDouble && !ST->useNEONForSinglePrecisionFP()))
4410    return SDValue();
4411
4412  EVT VMovVT;
4413  uint64_t iVal = FPVal.bitcastToAPInt().getZExtValue();
4414
4415  // It wouldn't really be worth bothering for doubles except for one very
4416  // important value, which does happen to match: 0.0. So make sure we don't do
4417  // anything stupid.
4418  if (IsDouble && (iVal & 0xffffffff) != (iVal >> 32))
4419    return SDValue();
4420
4421  // Try a VMOV.i32 (FIXME: i8, i16, or i64 could work too).
4422  SDValue NewVal = isNEONModifiedImm(iVal & 0xffffffffU, 0, 32, DAG, VMovVT,
4423                                     false, VMOVModImm);
4424  if (NewVal != SDValue()) {
4425    SDLoc DL(Op);
4426    SDValue VecConstant = DAG.getNode(ARMISD::VMOVIMM, DL, VMovVT,
4427                                      NewVal);
4428    if (IsDouble)
4429      return DAG.getNode(ISD::BITCAST, DL, MVT::f64, VecConstant);
4430
4431    // It's a float: cast and extract a vector element.
4432    SDValue VecFConstant = DAG.getNode(ISD::BITCAST, DL, MVT::v2f32,
4433                                       VecConstant);
4434    return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::f32, VecFConstant,
4435                       DAG.getConstant(0, MVT::i32));
4436  }
4437
4438  // Finally, try a VMVN.i32
4439  NewVal = isNEONModifiedImm(~iVal & 0xffffffffU, 0, 32, DAG, VMovVT,
4440                             false, VMVNModImm);
4441  if (NewVal != SDValue()) {
4442    SDLoc DL(Op);
4443    SDValue VecConstant = DAG.getNode(ARMISD::VMVNIMM, DL, VMovVT, NewVal);
4444
4445    if (IsDouble)
4446      return DAG.getNode(ISD::BITCAST, DL, MVT::f64, VecConstant);
4447
4448    // It's a float: cast and extract a vector element.
4449    SDValue VecFConstant = DAG.getNode(ISD::BITCAST, DL, MVT::v2f32,
4450                                       VecConstant);
4451    return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::f32, VecFConstant,
4452                       DAG.getConstant(0, MVT::i32));
4453  }
4454
4455  return SDValue();
4456}
4457
4458// check if an VEXT instruction can handle the shuffle mask when the
4459// vector sources of the shuffle are the same.
4460static bool isSingletonVEXTMask(ArrayRef<int> M, EVT VT, unsigned &Imm) {
4461  unsigned NumElts = VT.getVectorNumElements();
4462
4463  // Assume that the first shuffle index is not UNDEF.  Fail if it is.
4464  if (M[0] < 0)
4465    return false;
4466
4467  Imm = M[0];
4468
4469  // If this is a VEXT shuffle, the immediate value is the index of the first
4470  // element.  The other shuffle indices must be the successive elements after
4471  // the first one.
4472  unsigned ExpectedElt = Imm;
4473  for (unsigned i = 1; i < NumElts; ++i) {
4474    // Increment the expected index.  If it wraps around, just follow it
4475    // back to index zero and keep going.
4476    ++ExpectedElt;
4477    if (ExpectedElt == NumElts)
4478      ExpectedElt = 0;
4479
4480    if (M[i] < 0) continue; // ignore UNDEF indices
4481    if (ExpectedElt != static_cast<unsigned>(M[i]))
4482      return false;
4483  }
4484
4485  return true;
4486}
4487
4488
4489static bool isVEXTMask(ArrayRef<int> M, EVT VT,
4490                       bool &ReverseVEXT, unsigned &Imm) {
4491  unsigned NumElts = VT.getVectorNumElements();
4492  ReverseVEXT = false;
4493
4494  // Assume that the first shuffle index is not UNDEF.  Fail if it is.
4495  if (M[0] < 0)
4496    return false;
4497
4498  Imm = M[0];
4499
4500  // If this is a VEXT shuffle, the immediate value is the index of the first
4501  // element.  The other shuffle indices must be the successive elements after
4502  // the first one.
4503  unsigned ExpectedElt = Imm;
4504  for (unsigned i = 1; i < NumElts; ++i) {
4505    // Increment the expected index.  If it wraps around, it may still be
4506    // a VEXT but the source vectors must be swapped.
4507    ExpectedElt += 1;
4508    if (ExpectedElt == NumElts * 2) {
4509      ExpectedElt = 0;
4510      ReverseVEXT = true;
4511    }
4512
4513    if (M[i] < 0) continue; // ignore UNDEF indices
4514    if (ExpectedElt != static_cast<unsigned>(M[i]))
4515      return false;
4516  }
4517
4518  // Adjust the index value if the source operands will be swapped.
4519  if (ReverseVEXT)
4520    Imm -= NumElts;
4521
4522  return true;
4523}
4524
4525/// isVREVMask - Check if a vector shuffle corresponds to a VREV
4526/// instruction with the specified blocksize.  (The order of the elements
4527/// within each block of the vector is reversed.)
4528static bool isVREVMask(ArrayRef<int> M, EVT VT, unsigned BlockSize) {
4529  assert((BlockSize==16 || BlockSize==32 || BlockSize==64) &&
4530         "Only possible block sizes for VREV are: 16, 32, 64");
4531
4532  unsigned EltSz = VT.getVectorElementType().getSizeInBits();
4533  if (EltSz == 64)
4534    return false;
4535
4536  unsigned NumElts = VT.getVectorNumElements();
4537  unsigned BlockElts = M[0] + 1;
4538  // If the first shuffle index is UNDEF, be optimistic.
4539  if (M[0] < 0)
4540    BlockElts = BlockSize / EltSz;
4541
4542  if (BlockSize <= EltSz || BlockSize != BlockElts * EltSz)
4543    return false;
4544
4545  for (unsigned i = 0; i < NumElts; ++i) {
4546    if (M[i] < 0) continue; // ignore UNDEF indices
4547    if ((unsigned) M[i] != (i - i%BlockElts) + (BlockElts - 1 - i%BlockElts))
4548      return false;
4549  }
4550
4551  return true;
4552}
4553
4554static bool isVTBLMask(ArrayRef<int> M, EVT VT) {
4555  // We can handle <8 x i8> vector shuffles. If the index in the mask is out of
4556  // range, then 0 is placed into the resulting vector. So pretty much any mask
4557  // of 8 elements can work here.
4558  return VT == MVT::v8i8 && M.size() == 8;
4559}
4560
4561static bool isVTRNMask(ArrayRef<int> M, EVT VT, unsigned &WhichResult) {
4562  unsigned EltSz = VT.getVectorElementType().getSizeInBits();
4563  if (EltSz == 64)
4564    return false;
4565
4566  unsigned NumElts = VT.getVectorNumElements();
4567  WhichResult = (M[0] == 0 ? 0 : 1);
4568  for (unsigned i = 0; i < NumElts; i += 2) {
4569    if ((M[i] >= 0 && (unsigned) M[i] != i + WhichResult) ||
4570        (M[i+1] >= 0 && (unsigned) M[i+1] != i + NumElts + WhichResult))
4571      return false;
4572  }
4573  return true;
4574}
4575
4576/// isVTRN_v_undef_Mask - Special case of isVTRNMask for canonical form of
4577/// "vector_shuffle v, v", i.e., "vector_shuffle v, undef".
4578/// Mask is e.g., <0, 0, 2, 2> instead of <0, 4, 2, 6>.
4579static bool isVTRN_v_undef_Mask(ArrayRef<int> M, EVT VT, unsigned &WhichResult){
4580  unsigned EltSz = VT.getVectorElementType().getSizeInBits();
4581  if (EltSz == 64)
4582    return false;
4583
4584  unsigned NumElts = VT.getVectorNumElements();
4585  WhichResult = (M[0] == 0 ? 0 : 1);
4586  for (unsigned i = 0; i < NumElts; i += 2) {
4587    if ((M[i] >= 0 && (unsigned) M[i] != i + WhichResult) ||
4588        (M[i+1] >= 0 && (unsigned) M[i+1] != i + WhichResult))
4589      return false;
4590  }
4591  return true;
4592}
4593
4594static bool isVUZPMask(ArrayRef<int> M, EVT VT, unsigned &WhichResult) {
4595  unsigned EltSz = VT.getVectorElementType().getSizeInBits();
4596  if (EltSz == 64)
4597    return false;
4598
4599  unsigned NumElts = VT.getVectorNumElements();
4600  WhichResult = (M[0] == 0 ? 0 : 1);
4601  for (unsigned i = 0; i != NumElts; ++i) {
4602    if (M[i] < 0) continue; // ignore UNDEF indices
4603    if ((unsigned) M[i] != 2 * i + WhichResult)
4604      return false;
4605  }
4606
4607  // VUZP.32 for 64-bit vectors is a pseudo-instruction alias for VTRN.32.
4608  if (VT.is64BitVector() && EltSz == 32)
4609    return false;
4610
4611  return true;
4612}
4613
4614/// isVUZP_v_undef_Mask - Special case of isVUZPMask for canonical form of
4615/// "vector_shuffle v, v", i.e., "vector_shuffle v, undef".
4616/// Mask is e.g., <0, 2, 0, 2> instead of <0, 2, 4, 6>,
4617static bool isVUZP_v_undef_Mask(ArrayRef<int> M, EVT VT, unsigned &WhichResult){
4618  unsigned EltSz = VT.getVectorElementType().getSizeInBits();
4619  if (EltSz == 64)
4620    return false;
4621
4622  unsigned Half = VT.getVectorNumElements() / 2;
4623  WhichResult = (M[0] == 0 ? 0 : 1);
4624  for (unsigned j = 0; j != 2; ++j) {
4625    unsigned Idx = WhichResult;
4626    for (unsigned i = 0; i != Half; ++i) {
4627      int MIdx = M[i + j * Half];
4628      if (MIdx >= 0 && (unsigned) MIdx != Idx)
4629        return false;
4630      Idx += 2;
4631    }
4632  }
4633
4634  // VUZP.32 for 64-bit vectors is a pseudo-instruction alias for VTRN.32.
4635  if (VT.is64BitVector() && EltSz == 32)
4636    return false;
4637
4638  return true;
4639}
4640
4641static bool isVZIPMask(ArrayRef<int> M, EVT VT, unsigned &WhichResult) {
4642  unsigned EltSz = VT.getVectorElementType().getSizeInBits();
4643  if (EltSz == 64)
4644    return false;
4645
4646  unsigned NumElts = VT.getVectorNumElements();
4647  WhichResult = (M[0] == 0 ? 0 : 1);
4648  unsigned Idx = WhichResult * NumElts / 2;
4649  for (unsigned i = 0; i != NumElts; i += 2) {
4650    if ((M[i] >= 0 && (unsigned) M[i] != Idx) ||
4651        (M[i+1] >= 0 && (unsigned) M[i+1] != Idx + NumElts))
4652      return false;
4653    Idx += 1;
4654  }
4655
4656  // VZIP.32 for 64-bit vectors is a pseudo-instruction alias for VTRN.32.
4657  if (VT.is64BitVector() && EltSz == 32)
4658    return false;
4659
4660  return true;
4661}
4662
4663/// isVZIP_v_undef_Mask - Special case of isVZIPMask for canonical form of
4664/// "vector_shuffle v, v", i.e., "vector_shuffle v, undef".
4665/// Mask is e.g., <0, 0, 1, 1> instead of <0, 4, 1, 5>.
4666static bool isVZIP_v_undef_Mask(ArrayRef<int> M, EVT VT, unsigned &WhichResult){
4667  unsigned EltSz = VT.getVectorElementType().getSizeInBits();
4668  if (EltSz == 64)
4669    return false;
4670
4671  unsigned NumElts = VT.getVectorNumElements();
4672  WhichResult = (M[0] == 0 ? 0 : 1);
4673  unsigned Idx = WhichResult * NumElts / 2;
4674  for (unsigned i = 0; i != NumElts; i += 2) {
4675    if ((M[i] >= 0 && (unsigned) M[i] != Idx) ||
4676        (M[i+1] >= 0 && (unsigned) M[i+1] != Idx))
4677      return false;
4678    Idx += 1;
4679  }
4680
4681  // VZIP.32 for 64-bit vectors is a pseudo-instruction alias for VTRN.32.
4682  if (VT.is64BitVector() && EltSz == 32)
4683    return false;
4684
4685  return true;
4686}
4687
4688/// \return true if this is a reverse operation on an vector.
4689static bool isReverseMask(ArrayRef<int> M, EVT VT) {
4690  unsigned NumElts = VT.getVectorNumElements();
4691  // Make sure the mask has the right size.
4692  if (NumElts != M.size())
4693      return false;
4694
4695  // Look for <15, ..., 3, -1, 1, 0>.
4696  for (unsigned i = 0; i != NumElts; ++i)
4697    if (M[i] >= 0 && M[i] != (int) (NumElts - 1 - i))
4698      return false;
4699
4700  return true;
4701}
4702
4703// If N is an integer constant that can be moved into a register in one
4704// instruction, return an SDValue of such a constant (will become a MOV
4705// instruction).  Otherwise return null.
4706static SDValue IsSingleInstrConstant(SDValue N, SelectionDAG &DAG,
4707                                     const ARMSubtarget *ST, SDLoc dl) {
4708  uint64_t Val;
4709  if (!isa<ConstantSDNode>(N))
4710    return SDValue();
4711  Val = cast<ConstantSDNode>(N)->getZExtValue();
4712
4713  if (ST->isThumb1Only()) {
4714    if (Val <= 255 || ~Val <= 255)
4715      return DAG.getConstant(Val, MVT::i32);
4716  } else {
4717    if (ARM_AM::getSOImmVal(Val) != -1 || ARM_AM::getSOImmVal(~Val) != -1)
4718      return DAG.getConstant(Val, MVT::i32);
4719  }
4720  return SDValue();
4721}
4722
4723// If this is a case we can't handle, return null and let the default
4724// expansion code take care of it.
4725SDValue ARMTargetLowering::LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG,
4726                                             const ARMSubtarget *ST) const {
4727  BuildVectorSDNode *BVN = cast<BuildVectorSDNode>(Op.getNode());
4728  SDLoc dl(Op);
4729  EVT VT = Op.getValueType();
4730
4731  APInt SplatBits, SplatUndef;
4732  unsigned SplatBitSize;
4733  bool HasAnyUndefs;
4734  if (BVN->isConstantSplat(SplatBits, SplatUndef, SplatBitSize, HasAnyUndefs)) {
4735    if (SplatBitSize <= 64) {
4736      // Check if an immediate VMOV works.
4737      EVT VmovVT;
4738      SDValue Val = isNEONModifiedImm(SplatBits.getZExtValue(),
4739                                      SplatUndef.getZExtValue(), SplatBitSize,
4740                                      DAG, VmovVT, VT.is128BitVector(),
4741                                      VMOVModImm);
4742      if (Val.getNode()) {
4743        SDValue Vmov = DAG.getNode(ARMISD::VMOVIMM, dl, VmovVT, Val);
4744        return DAG.getNode(ISD::BITCAST, dl, VT, Vmov);
4745      }
4746
4747      // Try an immediate VMVN.
4748      uint64_t NegatedImm = (~SplatBits).getZExtValue();
4749      Val = isNEONModifiedImm(NegatedImm,
4750                                      SplatUndef.getZExtValue(), SplatBitSize,
4751                                      DAG, VmovVT, VT.is128BitVector(),
4752                                      VMVNModImm);
4753      if (Val.getNode()) {
4754        SDValue Vmov = DAG.getNode(ARMISD::VMVNIMM, dl, VmovVT, Val);
4755        return DAG.getNode(ISD::BITCAST, dl, VT, Vmov);
4756      }
4757
4758      // Use vmov.f32 to materialize other v2f32 and v4f32 splats.
4759      if ((VT == MVT::v2f32 || VT == MVT::v4f32) && SplatBitSize == 32) {
4760        int ImmVal = ARM_AM::getFP32Imm(SplatBits);
4761        if (ImmVal != -1) {
4762          SDValue Val = DAG.getTargetConstant(ImmVal, MVT::i32);
4763          return DAG.getNode(ARMISD::VMOVFPIMM, dl, VT, Val);
4764        }
4765      }
4766    }
4767  }
4768
4769  // Scan through the operands to see if only one value is used.
4770  //
4771  // As an optimisation, even if more than one value is used it may be more
4772  // profitable to splat with one value then change some lanes.
4773  //
4774  // Heuristically we decide to do this if the vector has a "dominant" value,
4775  // defined as splatted to more than half of the lanes.
4776  unsigned NumElts = VT.getVectorNumElements();
4777  bool isOnlyLowElement = true;
4778  bool usesOnlyOneValue = true;
4779  bool hasDominantValue = false;
4780  bool isConstant = true;
4781
4782  // Map of the number of times a particular SDValue appears in the
4783  // element list.
4784  DenseMap<SDValue, unsigned> ValueCounts;
4785  SDValue Value;
4786  for (unsigned i = 0; i < NumElts; ++i) {
4787    SDValue V = Op.getOperand(i);
4788    if (V.getOpcode() == ISD::UNDEF)
4789      continue;
4790    if (i > 0)
4791      isOnlyLowElement = false;
4792    if (!isa<ConstantFPSDNode>(V) && !isa<ConstantSDNode>(V))
4793      isConstant = false;
4794
4795    ValueCounts.insert(std::make_pair(V, 0));
4796    unsigned &Count = ValueCounts[V];
4797
4798    // Is this value dominant? (takes up more than half of the lanes)
4799    if (++Count > (NumElts / 2)) {
4800      hasDominantValue = true;
4801      Value = V;
4802    }
4803  }
4804  if (ValueCounts.size() != 1)
4805    usesOnlyOneValue = false;
4806  if (!Value.getNode() && ValueCounts.size() > 0)
4807    Value = ValueCounts.begin()->first;
4808
4809  if (ValueCounts.size() == 0)
4810    return DAG.getUNDEF(VT);
4811
4812  // Loads are better lowered with insert_vector_elt/ARMISD::BUILD_VECTOR.
4813  // Keep going if we are hitting this case.
4814  if (isOnlyLowElement && !ISD::isNormalLoad(Value.getNode()))
4815    return DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Value);
4816
4817  unsigned EltSize = VT.getVectorElementType().getSizeInBits();
4818
4819  // Use VDUP for non-constant splats.  For f32 constant splats, reduce to
4820  // i32 and try again.
4821  if (hasDominantValue && EltSize <= 32) {
4822    if (!isConstant) {
4823      SDValue N;
4824
4825      // If we are VDUPing a value that comes directly from a vector, that will
4826      // cause an unnecessary move to and from a GPR, where instead we could
4827      // just use VDUPLANE. We can only do this if the lane being extracted
4828      // is at a constant index, as the VDUP from lane instructions only have
4829      // constant-index forms.
4830      if (Value->getOpcode() == ISD::EXTRACT_VECTOR_ELT &&
4831          isa<ConstantSDNode>(Value->getOperand(1))) {
4832        // We need to create a new undef vector to use for the VDUPLANE if the
4833        // size of the vector from which we get the value is different than the
4834        // size of the vector that we need to create. We will insert the element
4835        // such that the register coalescer will remove unnecessary copies.
4836        if (VT != Value->getOperand(0).getValueType()) {
4837          ConstantSDNode *constIndex;
4838          constIndex = dyn_cast<ConstantSDNode>(Value->getOperand(1));
4839          assert(constIndex && "The index is not a constant!");
4840          unsigned index = constIndex->getAPIntValue().getLimitedValue() %
4841                             VT.getVectorNumElements();
4842          N =  DAG.getNode(ARMISD::VDUPLANE, dl, VT,
4843                 DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, DAG.getUNDEF(VT),
4844                        Value, DAG.getConstant(index, MVT::i32)),
4845                           DAG.getConstant(index, MVT::i32));
4846        } else
4847          N = DAG.getNode(ARMISD::VDUPLANE, dl, VT,
4848                        Value->getOperand(0), Value->getOperand(1));
4849      } else
4850        N = DAG.getNode(ARMISD::VDUP, dl, VT, Value);
4851
4852      if (!usesOnlyOneValue) {
4853        // The dominant value was splatted as 'N', but we now have to insert
4854        // all differing elements.
4855        for (unsigned I = 0; I < NumElts; ++I) {
4856          if (Op.getOperand(I) == Value)
4857            continue;
4858          SmallVector<SDValue, 3> Ops;
4859          Ops.push_back(N);
4860          Ops.push_back(Op.getOperand(I));
4861          Ops.push_back(DAG.getConstant(I, MVT::i32));
4862          N = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, &Ops[0], 3);
4863        }
4864      }
4865      return N;
4866    }
4867    if (VT.getVectorElementType().isFloatingPoint()) {
4868      SmallVector<SDValue, 8> Ops;
4869      for (unsigned i = 0; i < NumElts; ++i)
4870        Ops.push_back(DAG.getNode(ISD::BITCAST, dl, MVT::i32,
4871                                  Op.getOperand(i)));
4872      EVT VecVT = EVT::getVectorVT(*DAG.getContext(), MVT::i32, NumElts);
4873      SDValue Val = DAG.getNode(ISD::BUILD_VECTOR, dl, VecVT, &Ops[0], NumElts);
4874      Val = LowerBUILD_VECTOR(Val, DAG, ST);
4875      if (Val.getNode())
4876        return DAG.getNode(ISD::BITCAST, dl, VT, Val);
4877    }
4878    if (usesOnlyOneValue) {
4879      SDValue Val = IsSingleInstrConstant(Value, DAG, ST, dl);
4880      if (isConstant && Val.getNode())
4881        return DAG.getNode(ARMISD::VDUP, dl, VT, Val);
4882    }
4883  }
4884
4885  // If all elements are constants and the case above didn't get hit, fall back
4886  // to the default expansion, which will generate a load from the constant
4887  // pool.
4888  if (isConstant)
4889    return SDValue();
4890
4891  // Empirical tests suggest this is rarely worth it for vectors of length <= 2.
4892  if (NumElts >= 4) {
4893    SDValue shuffle = ReconstructShuffle(Op, DAG);
4894    if (shuffle != SDValue())
4895      return shuffle;
4896  }
4897
4898  // Vectors with 32- or 64-bit elements can be built by directly assigning
4899  // the subregisters.  Lower it to an ARMISD::BUILD_VECTOR so the operands
4900  // will be legalized.
4901  if (EltSize >= 32) {
4902    // Do the expansion with floating-point types, since that is what the VFP
4903    // registers are defined to use, and since i64 is not legal.
4904    EVT EltVT = EVT::getFloatingPointVT(EltSize);
4905    EVT VecVT = EVT::getVectorVT(*DAG.getContext(), EltVT, NumElts);
4906    SmallVector<SDValue, 8> Ops;
4907    for (unsigned i = 0; i < NumElts; ++i)
4908      Ops.push_back(DAG.getNode(ISD::BITCAST, dl, EltVT, Op.getOperand(i)));
4909    SDValue Val = DAG.getNode(ARMISD::BUILD_VECTOR, dl, VecVT, &Ops[0],NumElts);
4910    return DAG.getNode(ISD::BITCAST, dl, VT, Val);
4911  }
4912
4913  // If all else fails, just use a sequence of INSERT_VECTOR_ELT when we
4914  // know the default expansion would otherwise fall back on something even
4915  // worse. For a vector with one or two non-undef values, that's
4916  // scalar_to_vector for the elements followed by a shuffle (provided the
4917  // shuffle is valid for the target) and materialization element by element
4918  // on the stack followed by a load for everything else.
4919  if (!isConstant && !usesOnlyOneValue) {
4920    SDValue Vec = DAG.getUNDEF(VT);
4921    for (unsigned i = 0 ; i < NumElts; ++i) {
4922      SDValue V = Op.getOperand(i);
4923      if (V.getOpcode() == ISD::UNDEF)
4924        continue;
4925      SDValue LaneIdx = DAG.getConstant(i, MVT::i32);
4926      Vec = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, Vec, V, LaneIdx);
4927    }
4928    return Vec;
4929  }
4930
4931  return SDValue();
4932}
4933
4934// Gather data to see if the operation can be modelled as a
4935// shuffle in combination with VEXTs.
4936SDValue ARMTargetLowering::ReconstructShuffle(SDValue Op,
4937                                              SelectionDAG &DAG) const {
4938  SDLoc dl(Op);
4939  EVT VT = Op.getValueType();
4940  unsigned NumElts = VT.getVectorNumElements();
4941
4942  SmallVector<SDValue, 2> SourceVecs;
4943  SmallVector<unsigned, 2> MinElts;
4944  SmallVector<unsigned, 2> MaxElts;
4945
4946  for (unsigned i = 0; i < NumElts; ++i) {
4947    SDValue V = Op.getOperand(i);
4948    if (V.getOpcode() == ISD::UNDEF)
4949      continue;
4950    else if (V.getOpcode() != ISD::EXTRACT_VECTOR_ELT) {
4951      // A shuffle can only come from building a vector from various
4952      // elements of other vectors.
4953      return SDValue();
4954    } else if (V.getOperand(0).getValueType().getVectorElementType() !=
4955               VT.getVectorElementType()) {
4956      // This code doesn't know how to handle shuffles where the vector
4957      // element types do not match (this happens because type legalization
4958      // promotes the return type of EXTRACT_VECTOR_ELT).
4959      // FIXME: It might be appropriate to extend this code to handle
4960      // mismatched types.
4961      return SDValue();
4962    }
4963
4964    // Record this extraction against the appropriate vector if possible...
4965    SDValue SourceVec = V.getOperand(0);
4966    // If the element number isn't a constant, we can't effectively
4967    // analyze what's going on.
4968    if (!isa<ConstantSDNode>(V.getOperand(1)))
4969      return SDValue();
4970    unsigned EltNo = cast<ConstantSDNode>(V.getOperand(1))->getZExtValue();
4971    bool FoundSource = false;
4972    for (unsigned j = 0; j < SourceVecs.size(); ++j) {
4973      if (SourceVecs[j] == SourceVec) {
4974        if (MinElts[j] > EltNo)
4975          MinElts[j] = EltNo;
4976        if (MaxElts[j] < EltNo)
4977          MaxElts[j] = EltNo;
4978        FoundSource = true;
4979        break;
4980      }
4981    }
4982
4983    // Or record a new source if not...
4984    if (!FoundSource) {
4985      SourceVecs.push_back(SourceVec);
4986      MinElts.push_back(EltNo);
4987      MaxElts.push_back(EltNo);
4988    }
4989  }
4990
4991  // Currently only do something sane when at most two source vectors
4992  // involved.
4993  if (SourceVecs.size() > 2)
4994    return SDValue();
4995
4996  SDValue ShuffleSrcs[2] = {DAG.getUNDEF(VT), DAG.getUNDEF(VT) };
4997  int VEXTOffsets[2] = {0, 0};
4998
4999  // This loop extracts the usage patterns of the source vectors
5000  // and prepares appropriate SDValues for a shuffle if possible.
5001  for (unsigned i = 0; i < SourceVecs.size(); ++i) {
5002    if (SourceVecs[i].getValueType() == VT) {
5003      // No VEXT necessary
5004      ShuffleSrcs[i] = SourceVecs[i];
5005      VEXTOffsets[i] = 0;
5006      continue;
5007    } else if (SourceVecs[i].getValueType().getVectorNumElements() < NumElts) {
5008      // It probably isn't worth padding out a smaller vector just to
5009      // break it down again in a shuffle.
5010      return SDValue();
5011    }
5012
5013    // Since only 64-bit and 128-bit vectors are legal on ARM and
5014    // we've eliminated the other cases...
5015    assert(SourceVecs[i].getValueType().getVectorNumElements() == 2*NumElts &&
5016           "unexpected vector sizes in ReconstructShuffle");
5017
5018    if (MaxElts[i] - MinElts[i] >= NumElts) {
5019      // Span too large for a VEXT to cope
5020      return SDValue();
5021    }
5022
5023    if (MinElts[i] >= NumElts) {
5024      // The extraction can just take the second half
5025      VEXTOffsets[i] = NumElts;
5026      ShuffleSrcs[i] = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, VT,
5027                                   SourceVecs[i],
5028                                   DAG.getIntPtrConstant(NumElts));
5029    } else if (MaxElts[i] < NumElts) {
5030      // The extraction can just take the first half
5031      VEXTOffsets[i] = 0;
5032      ShuffleSrcs[i] = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, VT,
5033                                   SourceVecs[i],
5034                                   DAG.getIntPtrConstant(0));
5035    } else {
5036      // An actual VEXT is needed
5037      VEXTOffsets[i] = MinElts[i];
5038      SDValue VEXTSrc1 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, VT,
5039                                     SourceVecs[i],
5040                                     DAG.getIntPtrConstant(0));
5041      SDValue VEXTSrc2 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, VT,
5042                                     SourceVecs[i],
5043                                     DAG.getIntPtrConstant(NumElts));
5044      ShuffleSrcs[i] = DAG.getNode(ARMISD::VEXT, dl, VT, VEXTSrc1, VEXTSrc2,
5045                                   DAG.getConstant(VEXTOffsets[i], MVT::i32));
5046    }
5047  }
5048
5049  SmallVector<int, 8> Mask;
5050
5051  for (unsigned i = 0; i < NumElts; ++i) {
5052    SDValue Entry = Op.getOperand(i);
5053    if (Entry.getOpcode() == ISD::UNDEF) {
5054      Mask.push_back(-1);
5055      continue;
5056    }
5057
5058    SDValue ExtractVec = Entry.getOperand(0);
5059    int ExtractElt = cast<ConstantSDNode>(Op.getOperand(i)
5060                                          .getOperand(1))->getSExtValue();
5061    if (ExtractVec == SourceVecs[0]) {
5062      Mask.push_back(ExtractElt - VEXTOffsets[0]);
5063    } else {
5064      Mask.push_back(ExtractElt + NumElts - VEXTOffsets[1]);
5065    }
5066  }
5067
5068  // Final check before we try to produce nonsense...
5069  if (isShuffleMaskLegal(Mask, VT))
5070    return DAG.getVectorShuffle(VT, dl, ShuffleSrcs[0], ShuffleSrcs[1],
5071                                &Mask[0]);
5072
5073  return SDValue();
5074}
5075
5076/// isShuffleMaskLegal - Targets can use this to indicate that they only
5077/// support *some* VECTOR_SHUFFLE operations, those with specific masks.
5078/// By default, if a target supports the VECTOR_SHUFFLE node, all mask values
5079/// are assumed to be legal.
5080bool
5081ARMTargetLowering::isShuffleMaskLegal(const SmallVectorImpl<int> &M,
5082                                      EVT VT) const {
5083  if (VT.getVectorNumElements() == 4 &&
5084      (VT.is128BitVector() || VT.is64BitVector())) {
5085    unsigned PFIndexes[4];
5086    for (unsigned i = 0; i != 4; ++i) {
5087      if (M[i] < 0)
5088        PFIndexes[i] = 8;
5089      else
5090        PFIndexes[i] = M[i];
5091    }
5092
5093    // Compute the index in the perfect shuffle table.
5094    unsigned PFTableIndex =
5095      PFIndexes[0]*9*9*9+PFIndexes[1]*9*9+PFIndexes[2]*9+PFIndexes[3];
5096    unsigned PFEntry = PerfectShuffleTable[PFTableIndex];
5097    unsigned Cost = (PFEntry >> 30);
5098
5099    if (Cost <= 4)
5100      return true;
5101  }
5102
5103  bool ReverseVEXT;
5104  unsigned Imm, WhichResult;
5105
5106  unsigned EltSize = VT.getVectorElementType().getSizeInBits();
5107  return (EltSize >= 32 ||
5108          ShuffleVectorSDNode::isSplatMask(&M[0], VT) ||
5109          isVREVMask(M, VT, 64) ||
5110          isVREVMask(M, VT, 32) ||
5111          isVREVMask(M, VT, 16) ||
5112          isVEXTMask(M, VT, ReverseVEXT, Imm) ||
5113          isVTBLMask(M, VT) ||
5114          isVTRNMask(M, VT, WhichResult) ||
5115          isVUZPMask(M, VT, WhichResult) ||
5116          isVZIPMask(M, VT, WhichResult) ||
5117          isVTRN_v_undef_Mask(M, VT, WhichResult) ||
5118          isVUZP_v_undef_Mask(M, VT, WhichResult) ||
5119          isVZIP_v_undef_Mask(M, VT, WhichResult) ||
5120          ((VT == MVT::v8i16 || VT == MVT::v16i8) && isReverseMask(M, VT)));
5121}
5122
5123/// GeneratePerfectShuffle - Given an entry in the perfect-shuffle table, emit
5124/// the specified operations to build the shuffle.
5125static SDValue GeneratePerfectShuffle(unsigned PFEntry, SDValue LHS,
5126                                      SDValue RHS, SelectionDAG &DAG,
5127                                      SDLoc dl) {
5128  unsigned OpNum = (PFEntry >> 26) & 0x0F;
5129  unsigned LHSID = (PFEntry >> 13) & ((1 << 13)-1);
5130  unsigned RHSID = (PFEntry >>  0) & ((1 << 13)-1);
5131
5132  enum {
5133    OP_COPY = 0, // Copy, used for things like <u,u,u,3> to say it is <0,1,2,3>
5134    OP_VREV,
5135    OP_VDUP0,
5136    OP_VDUP1,
5137    OP_VDUP2,
5138    OP_VDUP3,
5139    OP_VEXT1,
5140    OP_VEXT2,
5141    OP_VEXT3,
5142    OP_VUZPL, // VUZP, left result
5143    OP_VUZPR, // VUZP, right result
5144    OP_VZIPL, // VZIP, left result
5145    OP_VZIPR, // VZIP, right result
5146    OP_VTRNL, // VTRN, left result
5147    OP_VTRNR  // VTRN, right result
5148  };
5149
5150  if (OpNum == OP_COPY) {
5151    if (LHSID == (1*9+2)*9+3) return LHS;
5152    assert(LHSID == ((4*9+5)*9+6)*9+7 && "Illegal OP_COPY!");
5153    return RHS;
5154  }
5155
5156  SDValue OpLHS, OpRHS;
5157  OpLHS = GeneratePerfectShuffle(PerfectShuffleTable[LHSID], LHS, RHS, DAG, dl);
5158  OpRHS = GeneratePerfectShuffle(PerfectShuffleTable[RHSID], LHS, RHS, DAG, dl);
5159  EVT VT = OpLHS.getValueType();
5160
5161  switch (OpNum) {
5162  default: llvm_unreachable("Unknown shuffle opcode!");
5163  case OP_VREV:
5164    // VREV divides the vector in half and swaps within the half.
5165    if (VT.getVectorElementType() == MVT::i32 ||
5166        VT.getVectorElementType() == MVT::f32)
5167      return DAG.getNode(ARMISD::VREV64, dl, VT, OpLHS);
5168    // vrev <4 x i16> -> VREV32
5169    if (VT.getVectorElementType() == MVT::i16)
5170      return DAG.getNode(ARMISD::VREV32, dl, VT, OpLHS);
5171    // vrev <4 x i8> -> VREV16
5172    assert(VT.getVectorElementType() == MVT::i8);
5173    return DAG.getNode(ARMISD::VREV16, dl, VT, OpLHS);
5174  case OP_VDUP0:
5175  case OP_VDUP1:
5176  case OP_VDUP2:
5177  case OP_VDUP3:
5178    return DAG.getNode(ARMISD::VDUPLANE, dl, VT,
5179                       OpLHS, DAG.getConstant(OpNum-OP_VDUP0, MVT::i32));
5180  case OP_VEXT1:
5181  case OP_VEXT2:
5182  case OP_VEXT3:
5183    return DAG.getNode(ARMISD::VEXT, dl, VT,
5184                       OpLHS, OpRHS,
5185                       DAG.getConstant(OpNum-OP_VEXT1+1, MVT::i32));
5186  case OP_VUZPL:
5187  case OP_VUZPR:
5188    return DAG.getNode(ARMISD::VUZP, dl, DAG.getVTList(VT, VT),
5189                       OpLHS, OpRHS).getValue(OpNum-OP_VUZPL);
5190  case OP_VZIPL:
5191  case OP_VZIPR:
5192    return DAG.getNode(ARMISD::VZIP, dl, DAG.getVTList(VT, VT),
5193                       OpLHS, OpRHS).getValue(OpNum-OP_VZIPL);
5194  case OP_VTRNL:
5195  case OP_VTRNR:
5196    return DAG.getNode(ARMISD::VTRN, dl, DAG.getVTList(VT, VT),
5197                       OpLHS, OpRHS).getValue(OpNum-OP_VTRNL);
5198  }
5199}
5200
5201static SDValue LowerVECTOR_SHUFFLEv8i8(SDValue Op,
5202                                       ArrayRef<int> ShuffleMask,
5203                                       SelectionDAG &DAG) {
5204  // Check to see if we can use the VTBL instruction.
5205  SDValue V1 = Op.getOperand(0);
5206  SDValue V2 = Op.getOperand(1);
5207  SDLoc DL(Op);
5208
5209  SmallVector<SDValue, 8> VTBLMask;
5210  for (ArrayRef<int>::iterator
5211         I = ShuffleMask.begin(), E = ShuffleMask.end(); I != E; ++I)
5212    VTBLMask.push_back(DAG.getConstant(*I, MVT::i32));
5213
5214  if (V2.getNode()->getOpcode() == ISD::UNDEF)
5215    return DAG.getNode(ARMISD::VTBL1, DL, MVT::v8i8, V1,
5216                       DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v8i8,
5217                                   &VTBLMask[0], 8));
5218
5219  return DAG.getNode(ARMISD::VTBL2, DL, MVT::v8i8, V1, V2,
5220                     DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v8i8,
5221                                 &VTBLMask[0], 8));
5222}
5223
5224static SDValue LowerReverse_VECTOR_SHUFFLEv16i8_v8i16(SDValue Op,
5225                                                      SelectionDAG &DAG) {
5226  SDLoc DL(Op);
5227  SDValue OpLHS = Op.getOperand(0);
5228  EVT VT = OpLHS.getValueType();
5229
5230  assert((VT == MVT::v8i16 || VT == MVT::v16i8) &&
5231         "Expect an v8i16/v16i8 type");
5232  OpLHS = DAG.getNode(ARMISD::VREV64, DL, VT, OpLHS);
5233  // For a v16i8 type: After the VREV, we have got <8, ...15, 8, ..., 0>. Now,
5234  // extract the first 8 bytes into the top double word and the last 8 bytes
5235  // into the bottom double word. The v8i16 case is similar.
5236  unsigned ExtractNum = (VT == MVT::v16i8) ? 8 : 4;
5237  return DAG.getNode(ARMISD::VEXT, DL, VT, OpLHS, OpLHS,
5238                     DAG.getConstant(ExtractNum, MVT::i32));
5239}
5240
5241static SDValue LowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG) {
5242  SDValue V1 = Op.getOperand(0);
5243  SDValue V2 = Op.getOperand(1);
5244  SDLoc dl(Op);
5245  EVT VT = Op.getValueType();
5246  ShuffleVectorSDNode *SVN = cast<ShuffleVectorSDNode>(Op.getNode());
5247
5248  // Convert shuffles that are directly supported on NEON to target-specific
5249  // DAG nodes, instead of keeping them as shuffles and matching them again
5250  // during code selection.  This is more efficient and avoids the possibility
5251  // of inconsistencies between legalization and selection.
5252  // FIXME: floating-point vectors should be canonicalized to integer vectors
5253  // of the same time so that they get CSEd properly.
5254  ArrayRef<int> ShuffleMask = SVN->getMask();
5255
5256  unsigned EltSize = VT.getVectorElementType().getSizeInBits();
5257  if (EltSize <= 32) {
5258    if (ShuffleVectorSDNode::isSplatMask(&ShuffleMask[0], VT)) {
5259      int Lane = SVN->getSplatIndex();
5260      // If this is undef splat, generate it via "just" vdup, if possible.
5261      if (Lane == -1) Lane = 0;
5262
5263      // Test if V1 is a SCALAR_TO_VECTOR.
5264      if (Lane == 0 && V1.getOpcode() == ISD::SCALAR_TO_VECTOR) {
5265        return DAG.getNode(ARMISD::VDUP, dl, VT, V1.getOperand(0));
5266      }
5267      // Test if V1 is a BUILD_VECTOR which is equivalent to a SCALAR_TO_VECTOR
5268      // (and probably will turn into a SCALAR_TO_VECTOR once legalization
5269      // reaches it).
5270      if (Lane == 0 && V1.getOpcode() == ISD::BUILD_VECTOR &&
5271          !isa<ConstantSDNode>(V1.getOperand(0))) {
5272        bool IsScalarToVector = true;
5273        for (unsigned i = 1, e = V1.getNumOperands(); i != e; ++i)
5274          if (V1.getOperand(i).getOpcode() != ISD::UNDEF) {
5275            IsScalarToVector = false;
5276            break;
5277          }
5278        if (IsScalarToVector)
5279          return DAG.getNode(ARMISD::VDUP, dl, VT, V1.getOperand(0));
5280      }
5281      return DAG.getNode(ARMISD::VDUPLANE, dl, VT, V1,
5282                         DAG.getConstant(Lane, MVT::i32));
5283    }
5284
5285    bool ReverseVEXT;
5286    unsigned Imm;
5287    if (isVEXTMask(ShuffleMask, VT, ReverseVEXT, Imm)) {
5288      if (ReverseVEXT)
5289        std::swap(V1, V2);
5290      return DAG.getNode(ARMISD::VEXT, dl, VT, V1, V2,
5291                         DAG.getConstant(Imm, MVT::i32));
5292    }
5293
5294    if (isVREVMask(ShuffleMask, VT, 64))
5295      return DAG.getNode(ARMISD::VREV64, dl, VT, V1);
5296    if (isVREVMask(ShuffleMask, VT, 32))
5297      return DAG.getNode(ARMISD::VREV32, dl, VT, V1);
5298    if (isVREVMask(ShuffleMask, VT, 16))
5299      return DAG.getNode(ARMISD::VREV16, dl, VT, V1);
5300
5301    if (V2->getOpcode() == ISD::UNDEF &&
5302        isSingletonVEXTMask(ShuffleMask, VT, Imm)) {
5303      return DAG.getNode(ARMISD::VEXT, dl, VT, V1, V1,
5304                         DAG.getConstant(Imm, MVT::i32));
5305    }
5306
5307    // Check for Neon shuffles that modify both input vectors in place.
5308    // If both results are used, i.e., if there are two shuffles with the same
5309    // source operands and with masks corresponding to both results of one of
5310    // these operations, DAG memoization will ensure that a single node is
5311    // used for both shuffles.
5312    unsigned WhichResult;
5313    if (isVTRNMask(ShuffleMask, VT, WhichResult))
5314      return DAG.getNode(ARMISD::VTRN, dl, DAG.getVTList(VT, VT),
5315                         V1, V2).getValue(WhichResult);
5316    if (isVUZPMask(ShuffleMask, VT, WhichResult))
5317      return DAG.getNode(ARMISD::VUZP, dl, DAG.getVTList(VT, VT),
5318                         V1, V2).getValue(WhichResult);
5319    if (isVZIPMask(ShuffleMask, VT, WhichResult))
5320      return DAG.getNode(ARMISD::VZIP, dl, DAG.getVTList(VT, VT),
5321                         V1, V2).getValue(WhichResult);
5322
5323    if (isVTRN_v_undef_Mask(ShuffleMask, VT, WhichResult))
5324      return DAG.getNode(ARMISD::VTRN, dl, DAG.getVTList(VT, VT),
5325                         V1, V1).getValue(WhichResult);
5326    if (isVUZP_v_undef_Mask(ShuffleMask, VT, WhichResult))
5327      return DAG.getNode(ARMISD::VUZP, dl, DAG.getVTList(VT, VT),
5328                         V1, V1).getValue(WhichResult);
5329    if (isVZIP_v_undef_Mask(ShuffleMask, VT, WhichResult))
5330      return DAG.getNode(ARMISD::VZIP, dl, DAG.getVTList(VT, VT),
5331                         V1, V1).getValue(WhichResult);
5332  }
5333
5334  // If the shuffle is not directly supported and it has 4 elements, use
5335  // the PerfectShuffle-generated table to synthesize it from other shuffles.
5336  unsigned NumElts = VT.getVectorNumElements();
5337  if (NumElts == 4) {
5338    unsigned PFIndexes[4];
5339    for (unsigned i = 0; i != 4; ++i) {
5340      if (ShuffleMask[i] < 0)
5341        PFIndexes[i] = 8;
5342      else
5343        PFIndexes[i] = ShuffleMask[i];
5344    }
5345
5346    // Compute the index in the perfect shuffle table.
5347    unsigned PFTableIndex =
5348      PFIndexes[0]*9*9*9+PFIndexes[1]*9*9+PFIndexes[2]*9+PFIndexes[3];
5349    unsigned PFEntry = PerfectShuffleTable[PFTableIndex];
5350    unsigned Cost = (PFEntry >> 30);
5351
5352    if (Cost <= 4)
5353      return GeneratePerfectShuffle(PFEntry, V1, V2, DAG, dl);
5354  }
5355
5356  // Implement shuffles with 32- or 64-bit elements as ARMISD::BUILD_VECTORs.
5357  if (EltSize >= 32) {
5358    // Do the expansion with floating-point types, since that is what the VFP
5359    // registers are defined to use, and since i64 is not legal.
5360    EVT EltVT = EVT::getFloatingPointVT(EltSize);
5361    EVT VecVT = EVT::getVectorVT(*DAG.getContext(), EltVT, NumElts);
5362    V1 = DAG.getNode(ISD::BITCAST, dl, VecVT, V1);
5363    V2 = DAG.getNode(ISD::BITCAST, dl, VecVT, V2);
5364    SmallVector<SDValue, 8> Ops;
5365    for (unsigned i = 0; i < NumElts; ++i) {
5366      if (ShuffleMask[i] < 0)
5367        Ops.push_back(DAG.getUNDEF(EltVT));
5368      else
5369        Ops.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT,
5370                                  ShuffleMask[i] < (int)NumElts ? V1 : V2,
5371                                  DAG.getConstant(ShuffleMask[i] & (NumElts-1),
5372                                                  MVT::i32)));
5373    }
5374    SDValue Val = DAG.getNode(ARMISD::BUILD_VECTOR, dl, VecVT, &Ops[0],NumElts);
5375    return DAG.getNode(ISD::BITCAST, dl, VT, Val);
5376  }
5377
5378  if ((VT == MVT::v8i16 || VT == MVT::v16i8) && isReverseMask(ShuffleMask, VT))
5379    return LowerReverse_VECTOR_SHUFFLEv16i8_v8i16(Op, DAG);
5380
5381  if (VT == MVT::v8i8) {
5382    SDValue NewOp = LowerVECTOR_SHUFFLEv8i8(Op, ShuffleMask, DAG);
5383    if (NewOp.getNode())
5384      return NewOp;
5385  }
5386
5387  return SDValue();
5388}
5389
5390static SDValue LowerINSERT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) {
5391  // INSERT_VECTOR_ELT is legal only for immediate indexes.
5392  SDValue Lane = Op.getOperand(2);
5393  if (!isa<ConstantSDNode>(Lane))
5394    return SDValue();
5395
5396  return Op;
5397}
5398
5399static SDValue LowerEXTRACT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) {
5400  // EXTRACT_VECTOR_ELT is legal only for immediate indexes.
5401  SDValue Lane = Op.getOperand(1);
5402  if (!isa<ConstantSDNode>(Lane))
5403    return SDValue();
5404
5405  SDValue Vec = Op.getOperand(0);
5406  if (Op.getValueType() == MVT::i32 &&
5407      Vec.getValueType().getVectorElementType().getSizeInBits() < 32) {
5408    SDLoc dl(Op);
5409    return DAG.getNode(ARMISD::VGETLANEu, dl, MVT::i32, Vec, Lane);
5410  }
5411
5412  return Op;
5413}
5414
5415static SDValue LowerCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG) {
5416  // The only time a CONCAT_VECTORS operation can have legal types is when
5417  // two 64-bit vectors are concatenated to a 128-bit vector.
5418  assert(Op.getValueType().is128BitVector() && Op.getNumOperands() == 2 &&
5419         "unexpected CONCAT_VECTORS");
5420  SDLoc dl(Op);
5421  SDValue Val = DAG.getUNDEF(MVT::v2f64);
5422  SDValue Op0 = Op.getOperand(0);
5423  SDValue Op1 = Op.getOperand(1);
5424  if (Op0.getOpcode() != ISD::UNDEF)
5425    Val = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v2f64, Val,
5426                      DAG.getNode(ISD::BITCAST, dl, MVT::f64, Op0),
5427                      DAG.getIntPtrConstant(0));
5428  if (Op1.getOpcode() != ISD::UNDEF)
5429    Val = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v2f64, Val,
5430                      DAG.getNode(ISD::BITCAST, dl, MVT::f64, Op1),
5431                      DAG.getIntPtrConstant(1));
5432  return DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), Val);
5433}
5434
5435/// isExtendedBUILD_VECTOR - Check if N is a constant BUILD_VECTOR where each
5436/// element has been zero/sign-extended, depending on the isSigned parameter,
5437/// from an integer type half its size.
5438static bool isExtendedBUILD_VECTOR(SDNode *N, SelectionDAG &DAG,
5439                                   bool isSigned) {
5440  // A v2i64 BUILD_VECTOR will have been legalized to a BITCAST from v4i32.
5441  EVT VT = N->getValueType(0);
5442  if (VT == MVT::v2i64 && N->getOpcode() == ISD::BITCAST) {
5443    SDNode *BVN = N->getOperand(0).getNode();
5444    if (BVN->getValueType(0) != MVT::v4i32 ||
5445        BVN->getOpcode() != ISD::BUILD_VECTOR)
5446      return false;
5447    unsigned LoElt = DAG.getTargetLoweringInfo().isBigEndian() ? 1 : 0;
5448    unsigned HiElt = 1 - LoElt;
5449    ConstantSDNode *Lo0 = dyn_cast<ConstantSDNode>(BVN->getOperand(LoElt));
5450    ConstantSDNode *Hi0 = dyn_cast<ConstantSDNode>(BVN->getOperand(HiElt));
5451    ConstantSDNode *Lo1 = dyn_cast<ConstantSDNode>(BVN->getOperand(LoElt+2));
5452    ConstantSDNode *Hi1 = dyn_cast<ConstantSDNode>(BVN->getOperand(HiElt+2));
5453    if (!Lo0 || !Hi0 || !Lo1 || !Hi1)
5454      return false;
5455    if (isSigned) {
5456      if (Hi0->getSExtValue() == Lo0->getSExtValue() >> 32 &&
5457          Hi1->getSExtValue() == Lo1->getSExtValue() >> 32)
5458        return true;
5459    } else {
5460      if (Hi0->isNullValue() && Hi1->isNullValue())
5461        return true;
5462    }
5463    return false;
5464  }
5465
5466  if (N->getOpcode() != ISD::BUILD_VECTOR)
5467    return false;
5468
5469  for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) {
5470    SDNode *Elt = N->getOperand(i).getNode();
5471    if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Elt)) {
5472      unsigned EltSize = VT.getVectorElementType().getSizeInBits();
5473      unsigned HalfSize = EltSize / 2;
5474      if (isSigned) {
5475        if (!isIntN(HalfSize, C->getSExtValue()))
5476          return false;
5477      } else {
5478        if (!isUIntN(HalfSize, C->getZExtValue()))
5479          return false;
5480      }
5481      continue;
5482    }
5483    return false;
5484  }
5485
5486  return true;
5487}
5488
5489/// isSignExtended - Check if a node is a vector value that is sign-extended
5490/// or a constant BUILD_VECTOR with sign-extended elements.
5491static bool isSignExtended(SDNode *N, SelectionDAG &DAG) {
5492  if (N->getOpcode() == ISD::SIGN_EXTEND || ISD::isSEXTLoad(N))
5493    return true;
5494  if (isExtendedBUILD_VECTOR(N, DAG, true))
5495    return true;
5496  return false;
5497}
5498
5499/// isZeroExtended - Check if a node is a vector value that is zero-extended
5500/// or a constant BUILD_VECTOR with zero-extended elements.
5501static bool isZeroExtended(SDNode *N, SelectionDAG &DAG) {
5502  if (N->getOpcode() == ISD::ZERO_EXTEND || ISD::isZEXTLoad(N))
5503    return true;
5504  if (isExtendedBUILD_VECTOR(N, DAG, false))
5505    return true;
5506  return false;
5507}
5508
5509static EVT getExtensionTo64Bits(const EVT &OrigVT) {
5510  if (OrigVT.getSizeInBits() >= 64)
5511    return OrigVT;
5512
5513  assert(OrigVT.isSimple() && "Expecting a simple value type");
5514
5515  MVT::SimpleValueType OrigSimpleTy = OrigVT.getSimpleVT().SimpleTy;
5516  switch (OrigSimpleTy) {
5517  default: llvm_unreachable("Unexpected Vector Type");
5518  case MVT::v2i8:
5519  case MVT::v2i16:
5520     return MVT::v2i32;
5521  case MVT::v4i8:
5522    return  MVT::v4i16;
5523  }
5524}
5525
5526/// AddRequiredExtensionForVMULL - Add a sign/zero extension to extend the total
5527/// value size to 64 bits. We need a 64-bit D register as an operand to VMULL.
5528/// We insert the required extension here to get the vector to fill a D register.
5529static SDValue AddRequiredExtensionForVMULL(SDValue N, SelectionDAG &DAG,
5530                                            const EVT &OrigTy,
5531                                            const EVT &ExtTy,
5532                                            unsigned ExtOpcode) {
5533  // The vector originally had a size of OrigTy. It was then extended to ExtTy.
5534  // We expect the ExtTy to be 128-bits total. If the OrigTy is less than
5535  // 64-bits we need to insert a new extension so that it will be 64-bits.
5536  assert(ExtTy.is128BitVector() && "Unexpected extension size");
5537  if (OrigTy.getSizeInBits() >= 64)
5538    return N;
5539
5540  // Must extend size to at least 64 bits to be used as an operand for VMULL.
5541  EVT NewVT = getExtensionTo64Bits(OrigTy);
5542
5543  return DAG.getNode(ExtOpcode, SDLoc(N), NewVT, N);
5544}
5545
5546/// SkipLoadExtensionForVMULL - return a load of the original vector size that
5547/// does not do any sign/zero extension. If the original vector is less
5548/// than 64 bits, an appropriate extension will be added after the load to
5549/// reach a total size of 64 bits. We have to add the extension separately
5550/// because ARM does not have a sign/zero extending load for vectors.
5551static SDValue SkipLoadExtensionForVMULL(LoadSDNode *LD, SelectionDAG& DAG) {
5552  EVT ExtendedTy = getExtensionTo64Bits(LD->getMemoryVT());
5553
5554  // The load already has the right type.
5555  if (ExtendedTy == LD->getMemoryVT())
5556    return DAG.getLoad(LD->getMemoryVT(), SDLoc(LD), LD->getChain(),
5557                LD->getBasePtr(), LD->getPointerInfo(), LD->isVolatile(),
5558                LD->isNonTemporal(), LD->isInvariant(),
5559                LD->getAlignment());
5560
5561  // We need to create a zextload/sextload. We cannot just create a load
5562  // followed by a zext/zext node because LowerMUL is also run during normal
5563  // operation legalization where we can't create illegal types.
5564  return DAG.getExtLoad(LD->getExtensionType(), SDLoc(LD), ExtendedTy,
5565                        LD->getChain(), LD->getBasePtr(), LD->getPointerInfo(),
5566                        LD->getMemoryVT(), LD->isVolatile(),
5567                        LD->isNonTemporal(), LD->getAlignment());
5568}
5569
5570/// SkipExtensionForVMULL - For a node that is a SIGN_EXTEND, ZERO_EXTEND,
5571/// extending load, or BUILD_VECTOR with extended elements, return the
5572/// unextended value. The unextended vector should be 64 bits so that it can
5573/// be used as an operand to a VMULL instruction. If the original vector size
5574/// before extension is less than 64 bits we add a an extension to resize
5575/// the vector to 64 bits.
5576static SDValue SkipExtensionForVMULL(SDNode *N, SelectionDAG &DAG) {
5577  if (N->getOpcode() == ISD::SIGN_EXTEND || N->getOpcode() == ISD::ZERO_EXTEND)
5578    return AddRequiredExtensionForVMULL(N->getOperand(0), DAG,
5579                                        N->getOperand(0)->getValueType(0),
5580                                        N->getValueType(0),
5581                                        N->getOpcode());
5582
5583  if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N))
5584    return SkipLoadExtensionForVMULL(LD, DAG);
5585
5586  // Otherwise, the value must be a BUILD_VECTOR.  For v2i64, it will
5587  // have been legalized as a BITCAST from v4i32.
5588  if (N->getOpcode() == ISD::BITCAST) {
5589    SDNode *BVN = N->getOperand(0).getNode();
5590    assert(BVN->getOpcode() == ISD::BUILD_VECTOR &&
5591           BVN->getValueType(0) == MVT::v4i32 && "expected v4i32 BUILD_VECTOR");
5592    unsigned LowElt = DAG.getTargetLoweringInfo().isBigEndian() ? 1 : 0;
5593    return DAG.getNode(ISD::BUILD_VECTOR, SDLoc(N), MVT::v2i32,
5594                       BVN->getOperand(LowElt), BVN->getOperand(LowElt+2));
5595  }
5596  // Construct a new BUILD_VECTOR with elements truncated to half the size.
5597  assert(N->getOpcode() == ISD::BUILD_VECTOR && "expected BUILD_VECTOR");
5598  EVT VT = N->getValueType(0);
5599  unsigned EltSize = VT.getVectorElementType().getSizeInBits() / 2;
5600  unsigned NumElts = VT.getVectorNumElements();
5601  MVT TruncVT = MVT::getIntegerVT(EltSize);
5602  SmallVector<SDValue, 8> Ops;
5603  for (unsigned i = 0; i != NumElts; ++i) {
5604    ConstantSDNode *C = cast<ConstantSDNode>(N->getOperand(i));
5605    const APInt &CInt = C->getAPIntValue();
5606    // Element types smaller than 32 bits are not legal, so use i32 elements.
5607    // The values are implicitly truncated so sext vs. zext doesn't matter.
5608    Ops.push_back(DAG.getConstant(CInt.zextOrTrunc(32), MVT::i32));
5609  }
5610  return DAG.getNode(ISD::BUILD_VECTOR, SDLoc(N),
5611                     MVT::getVectorVT(TruncVT, NumElts), Ops.data(), NumElts);
5612}
5613
5614static bool isAddSubSExt(SDNode *N, SelectionDAG &DAG) {
5615  unsigned Opcode = N->getOpcode();
5616  if (Opcode == ISD::ADD || Opcode == ISD::SUB) {
5617    SDNode *N0 = N->getOperand(0).getNode();
5618    SDNode *N1 = N->getOperand(1).getNode();
5619    return N0->hasOneUse() && N1->hasOneUse() &&
5620      isSignExtended(N0, DAG) && isSignExtended(N1, DAG);
5621  }
5622  return false;
5623}
5624
5625static bool isAddSubZExt(SDNode *N, SelectionDAG &DAG) {
5626  unsigned Opcode = N->getOpcode();
5627  if (Opcode == ISD::ADD || Opcode == ISD::SUB) {
5628    SDNode *N0 = N->getOperand(0).getNode();
5629    SDNode *N1 = N->getOperand(1).getNode();
5630    return N0->hasOneUse() && N1->hasOneUse() &&
5631      isZeroExtended(N0, DAG) && isZeroExtended(N1, DAG);
5632  }
5633  return false;
5634}
5635
5636static SDValue LowerMUL(SDValue Op, SelectionDAG &DAG) {
5637  // Multiplications are only custom-lowered for 128-bit vectors so that
5638  // VMULL can be detected.  Otherwise v2i64 multiplications are not legal.
5639  EVT VT = Op.getValueType();
5640  assert(VT.is128BitVector() && VT.isInteger() &&
5641         "unexpected type for custom-lowering ISD::MUL");
5642  SDNode *N0 = Op.getOperand(0).getNode();
5643  SDNode *N1 = Op.getOperand(1).getNode();
5644  unsigned NewOpc = 0;
5645  bool isMLA = false;
5646  bool isN0SExt = isSignExtended(N0, DAG);
5647  bool isN1SExt = isSignExtended(N1, DAG);
5648  if (isN0SExt && isN1SExt)
5649    NewOpc = ARMISD::VMULLs;
5650  else {
5651    bool isN0ZExt = isZeroExtended(N0, DAG);
5652    bool isN1ZExt = isZeroExtended(N1, DAG);
5653    if (isN0ZExt && isN1ZExt)
5654      NewOpc = ARMISD::VMULLu;
5655    else if (isN1SExt || isN1ZExt) {
5656      // Look for (s/zext A + s/zext B) * (s/zext C). We want to turn these
5657      // into (s/zext A * s/zext C) + (s/zext B * s/zext C)
5658      if (isN1SExt && isAddSubSExt(N0, DAG)) {
5659        NewOpc = ARMISD::VMULLs;
5660        isMLA = true;
5661      } else if (isN1ZExt && isAddSubZExt(N0, DAG)) {
5662        NewOpc = ARMISD::VMULLu;
5663        isMLA = true;
5664      } else if (isN0ZExt && isAddSubZExt(N1, DAG)) {
5665        std::swap(N0, N1);
5666        NewOpc = ARMISD::VMULLu;
5667        isMLA = true;
5668      }
5669    }
5670
5671    if (!NewOpc) {
5672      if (VT == MVT::v2i64)
5673        // Fall through to expand this.  It is not legal.
5674        return SDValue();
5675      else
5676        // Other vector multiplications are legal.
5677        return Op;
5678    }
5679  }
5680
5681  // Legalize to a VMULL instruction.
5682  SDLoc DL(Op);
5683  SDValue Op0;
5684  SDValue Op1 = SkipExtensionForVMULL(N1, DAG);
5685  if (!isMLA) {
5686    Op0 = SkipExtensionForVMULL(N0, DAG);
5687    assert(Op0.getValueType().is64BitVector() &&
5688           Op1.getValueType().is64BitVector() &&
5689           "unexpected types for extended operands to VMULL");
5690    return DAG.getNode(NewOpc, DL, VT, Op0, Op1);
5691  }
5692
5693  // Optimizing (zext A + zext B) * C, to (VMULL A, C) + (VMULL B, C) during
5694  // isel lowering to take advantage of no-stall back to back vmul + vmla.
5695  //   vmull q0, d4, d6
5696  //   vmlal q0, d5, d6
5697  // is faster than
5698  //   vaddl q0, d4, d5
5699  //   vmovl q1, d6
5700  //   vmul  q0, q0, q1
5701  SDValue N00 = SkipExtensionForVMULL(N0->getOperand(0).getNode(), DAG);
5702  SDValue N01 = SkipExtensionForVMULL(N0->getOperand(1).getNode(), DAG);
5703  EVT Op1VT = Op1.getValueType();
5704  return DAG.getNode(N0->getOpcode(), DL, VT,
5705                     DAG.getNode(NewOpc, DL, VT,
5706                               DAG.getNode(ISD::BITCAST, DL, Op1VT, N00), Op1),
5707                     DAG.getNode(NewOpc, DL, VT,
5708                               DAG.getNode(ISD::BITCAST, DL, Op1VT, N01), Op1));
5709}
5710
5711static SDValue
5712LowerSDIV_v4i8(SDValue X, SDValue Y, SDLoc dl, SelectionDAG &DAG) {
5713  // Convert to float
5714  // float4 xf = vcvt_f32_s32(vmovl_s16(a.lo));
5715  // float4 yf = vcvt_f32_s32(vmovl_s16(b.lo));
5716  X = DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::v4i32, X);
5717  Y = DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::v4i32, Y);
5718  X = DAG.getNode(ISD::SINT_TO_FP, dl, MVT::v4f32, X);
5719  Y = DAG.getNode(ISD::SINT_TO_FP, dl, MVT::v4f32, Y);
5720  // Get reciprocal estimate.
5721  // float4 recip = vrecpeq_f32(yf);
5722  Y = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, MVT::v4f32,
5723                   DAG.getConstant(Intrinsic::arm_neon_vrecpe, MVT::i32), Y);
5724  // Because char has a smaller range than uchar, we can actually get away
5725  // without any newton steps.  This requires that we use a weird bias
5726  // of 0xb000, however (again, this has been exhaustively tested).
5727  // float4 result = as_float4(as_int4(xf*recip) + 0xb000);
5728  X = DAG.getNode(ISD::FMUL, dl, MVT::v4f32, X, Y);
5729  X = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, X);
5730  Y = DAG.getConstant(0xb000, MVT::i32);
5731  Y = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Y, Y, Y, Y);
5732  X = DAG.getNode(ISD::ADD, dl, MVT::v4i32, X, Y);
5733  X = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, X);
5734  // Convert back to short.
5735  X = DAG.getNode(ISD::FP_TO_SINT, dl, MVT::v4i32, X);
5736  X = DAG.getNode(ISD::TRUNCATE, dl, MVT::v4i16, X);
5737  return X;
5738}
5739
5740static SDValue
5741LowerSDIV_v4i16(SDValue N0, SDValue N1, SDLoc dl, SelectionDAG &DAG) {
5742  SDValue N2;
5743  // Convert to float.
5744  // float4 yf = vcvt_f32_s32(vmovl_s16(y));
5745  // float4 xf = vcvt_f32_s32(vmovl_s16(x));
5746  N0 = DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::v4i32, N0);
5747  N1 = DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::v4i32, N1);
5748  N0 = DAG.getNode(ISD::SINT_TO_FP, dl, MVT::v4f32, N0);
5749  N1 = DAG.getNode(ISD::SINT_TO_FP, dl, MVT::v4f32, N1);
5750
5751  // Use reciprocal estimate and one refinement step.
5752  // float4 recip = vrecpeq_f32(yf);
5753  // recip *= vrecpsq_f32(yf, recip);
5754  N2 = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, MVT::v4f32,
5755                   DAG.getConstant(Intrinsic::arm_neon_vrecpe, MVT::i32), N1);
5756  N1 = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, MVT::v4f32,
5757                   DAG.getConstant(Intrinsic::arm_neon_vrecps, MVT::i32),
5758                   N1, N2);
5759  N2 = DAG.getNode(ISD::FMUL, dl, MVT::v4f32, N1, N2);
5760  // Because short has a smaller range than ushort, we can actually get away
5761  // with only a single newton step.  This requires that we use a weird bias
5762  // of 89, however (again, this has been exhaustively tested).
5763  // float4 result = as_float4(as_int4(xf*recip) + 0x89);
5764  N0 = DAG.getNode(ISD::FMUL, dl, MVT::v4f32, N0, N2);
5765  N0 = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, N0);
5766  N1 = DAG.getConstant(0x89, MVT::i32);
5767  N1 = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, N1, N1, N1, N1);
5768  N0 = DAG.getNode(ISD::ADD, dl, MVT::v4i32, N0, N1);
5769  N0 = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, N0);
5770  // Convert back to integer and return.
5771  // return vmovn_s32(vcvt_s32_f32(result));
5772  N0 = DAG.getNode(ISD::FP_TO_SINT, dl, MVT::v4i32, N0);
5773  N0 = DAG.getNode(ISD::TRUNCATE, dl, MVT::v4i16, N0);
5774  return N0;
5775}
5776
5777static SDValue LowerSDIV(SDValue Op, SelectionDAG &DAG) {
5778  EVT VT = Op.getValueType();
5779  assert((VT == MVT::v4i16 || VT == MVT::v8i8) &&
5780         "unexpected type for custom-lowering ISD::SDIV");
5781
5782  SDLoc dl(Op);
5783  SDValue N0 = Op.getOperand(0);
5784  SDValue N1 = Op.getOperand(1);
5785  SDValue N2, N3;
5786
5787  if (VT == MVT::v8i8) {
5788    N0 = DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::v8i16, N0);
5789    N1 = DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::v8i16, N1);
5790
5791    N2 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MVT::v4i16, N0,
5792                     DAG.getIntPtrConstant(4));
5793    N3 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MVT::v4i16, N1,
5794                     DAG.getIntPtrConstant(4));
5795    N0 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MVT::v4i16, N0,
5796                     DAG.getIntPtrConstant(0));
5797    N1 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MVT::v4i16, N1,
5798                     DAG.getIntPtrConstant(0));
5799
5800    N0 = LowerSDIV_v4i8(N0, N1, dl, DAG); // v4i16
5801    N2 = LowerSDIV_v4i8(N2, N3, dl, DAG); // v4i16
5802
5803    N0 = DAG.getNode(ISD::CONCAT_VECTORS, dl, MVT::v8i16, N0, N2);
5804    N0 = LowerCONCAT_VECTORS(N0, DAG);
5805
5806    N0 = DAG.getNode(ISD::TRUNCATE, dl, MVT::v8i8, N0);
5807    return N0;
5808  }
5809  return LowerSDIV_v4i16(N0, N1, dl, DAG);
5810}
5811
5812static SDValue LowerUDIV(SDValue Op, SelectionDAG &DAG) {
5813  EVT VT = Op.getValueType();
5814  assert((VT == MVT::v4i16 || VT == MVT::v8i8) &&
5815         "unexpected type for custom-lowering ISD::UDIV");
5816
5817  SDLoc dl(Op);
5818  SDValue N0 = Op.getOperand(0);
5819  SDValue N1 = Op.getOperand(1);
5820  SDValue N2, N3;
5821
5822  if (VT == MVT::v8i8) {
5823    N0 = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::v8i16, N0);
5824    N1 = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::v8i16, N1);
5825
5826    N2 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MVT::v4i16, N0,
5827                     DAG.getIntPtrConstant(4));
5828    N3 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MVT::v4i16, N1,
5829                     DAG.getIntPtrConstant(4));
5830    N0 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MVT::v4i16, N0,
5831                     DAG.getIntPtrConstant(0));
5832    N1 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MVT::v4i16, N1,
5833                     DAG.getIntPtrConstant(0));
5834
5835    N0 = LowerSDIV_v4i16(N0, N1, dl, DAG); // v4i16
5836    N2 = LowerSDIV_v4i16(N2, N3, dl, DAG); // v4i16
5837
5838    N0 = DAG.getNode(ISD::CONCAT_VECTORS, dl, MVT::v8i16, N0, N2);
5839    N0 = LowerCONCAT_VECTORS(N0, DAG);
5840
5841    N0 = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, MVT::v8i8,
5842                     DAG.getConstant(Intrinsic::arm_neon_vqmovnsu, MVT::i32),
5843                     N0);
5844    return N0;
5845  }
5846
5847  // v4i16 sdiv ... Convert to float.
5848  // float4 yf = vcvt_f32_s32(vmovl_u16(y));
5849  // float4 xf = vcvt_f32_s32(vmovl_u16(x));
5850  N0 = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::v4i32, N0);
5851  N1 = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::v4i32, N1);
5852  N0 = DAG.getNode(ISD::SINT_TO_FP, dl, MVT::v4f32, N0);
5853  SDValue BN1 = DAG.getNode(ISD::SINT_TO_FP, dl, MVT::v4f32, N1);
5854
5855  // Use reciprocal estimate and two refinement steps.
5856  // float4 recip = vrecpeq_f32(yf);
5857  // recip *= vrecpsq_f32(yf, recip);
5858  // recip *= vrecpsq_f32(yf, recip);
5859  N2 = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, MVT::v4f32,
5860                   DAG.getConstant(Intrinsic::arm_neon_vrecpe, MVT::i32), BN1);
5861  N1 = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, MVT::v4f32,
5862                   DAG.getConstant(Intrinsic::arm_neon_vrecps, MVT::i32),
5863                   BN1, N2);
5864  N2 = DAG.getNode(ISD::FMUL, dl, MVT::v4f32, N1, N2);
5865  N1 = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, MVT::v4f32,
5866                   DAG.getConstant(Intrinsic::arm_neon_vrecps, MVT::i32),
5867                   BN1, N2);
5868  N2 = DAG.getNode(ISD::FMUL, dl, MVT::v4f32, N1, N2);
5869  // Simply multiplying by the reciprocal estimate can leave us a few ulps
5870  // too low, so we add 2 ulps (exhaustive testing shows that this is enough,
5871  // and that it will never cause us to return an answer too large).
5872  // float4 result = as_float4(as_int4(xf*recip) + 2);
5873  N0 = DAG.getNode(ISD::FMUL, dl, MVT::v4f32, N0, N2);
5874  N0 = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, N0);
5875  N1 = DAG.getConstant(2, MVT::i32);
5876  N1 = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, N1, N1, N1, N1);
5877  N0 = DAG.getNode(ISD::ADD, dl, MVT::v4i32, N0, N1);
5878  N0 = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, N0);
5879  // Convert back to integer and return.
5880  // return vmovn_u32(vcvt_s32_f32(result));
5881  N0 = DAG.getNode(ISD::FP_TO_SINT, dl, MVT::v4i32, N0);
5882  N0 = DAG.getNode(ISD::TRUNCATE, dl, MVT::v4i16, N0);
5883  return N0;
5884}
5885
5886static SDValue LowerADDC_ADDE_SUBC_SUBE(SDValue Op, SelectionDAG &DAG) {
5887  EVT VT = Op.getNode()->getValueType(0);
5888  SDVTList VTs = DAG.getVTList(VT, MVT::i32);
5889
5890  unsigned Opc;
5891  bool ExtraOp = false;
5892  switch (Op.getOpcode()) {
5893  default: llvm_unreachable("Invalid code");
5894  case ISD::ADDC: Opc = ARMISD::ADDC; break;
5895  case ISD::ADDE: Opc = ARMISD::ADDE; ExtraOp = true; break;
5896  case ISD::SUBC: Opc = ARMISD::SUBC; break;
5897  case ISD::SUBE: Opc = ARMISD::SUBE; ExtraOp = true; break;
5898  }
5899
5900  if (!ExtraOp)
5901    return DAG.getNode(Opc, SDLoc(Op), VTs, Op.getOperand(0),
5902                       Op.getOperand(1));
5903  return DAG.getNode(Opc, SDLoc(Op), VTs, Op.getOperand(0),
5904                     Op.getOperand(1), Op.getOperand(2));
5905}
5906
5907SDValue ARMTargetLowering::LowerFSINCOS(SDValue Op, SelectionDAG &DAG) const {
5908  assert(Subtarget->isTargetDarwin());
5909
5910  // For iOS, we want to call an alternative entry point: __sincos_stret,
5911  // return values are passed via sret.
5912  SDLoc dl(Op);
5913  SDValue Arg = Op.getOperand(0);
5914  EVT ArgVT = Arg.getValueType();
5915  Type *ArgTy = ArgVT.getTypeForEVT(*DAG.getContext());
5916
5917  MachineFrameInfo *FrameInfo = DAG.getMachineFunction().getFrameInfo();
5918  const TargetLowering &TLI = DAG.getTargetLoweringInfo();
5919
5920  // Pair of floats / doubles used to pass the result.
5921  StructType *RetTy = StructType::get(ArgTy, ArgTy, NULL);
5922
5923  // Create stack object for sret.
5924  const uint64_t ByteSize = TLI.getDataLayout()->getTypeAllocSize(RetTy);
5925  const unsigned StackAlign = TLI.getDataLayout()->getPrefTypeAlignment(RetTy);
5926  int FrameIdx = FrameInfo->CreateStackObject(ByteSize, StackAlign, false);
5927  SDValue SRet = DAG.getFrameIndex(FrameIdx, TLI.getPointerTy());
5928
5929  ArgListTy Args;
5930  ArgListEntry Entry;
5931
5932  Entry.Node = SRet;
5933  Entry.Ty = RetTy->getPointerTo();
5934  Entry.isSExt = false;
5935  Entry.isZExt = false;
5936  Entry.isSRet = true;
5937  Args.push_back(Entry);
5938
5939  Entry.Node = Arg;
5940  Entry.Ty = ArgTy;
5941  Entry.isSExt = false;
5942  Entry.isZExt = false;
5943  Args.push_back(Entry);
5944
5945  const char *LibcallName  = (ArgVT == MVT::f64)
5946  ? "__sincos_stret" : "__sincosf_stret";
5947  SDValue Callee = DAG.getExternalSymbol(LibcallName, getPointerTy());
5948
5949  TargetLowering::
5950  CallLoweringInfo CLI(DAG.getEntryNode(), Type::getVoidTy(*DAG.getContext()),
5951                       false, false, false, false, 0,
5952                       CallingConv::C, /*isTaillCall=*/false,
5953                       /*doesNotRet=*/false, /*isReturnValueUsed*/false,
5954                       Callee, Args, DAG, dl);
5955  std::pair<SDValue, SDValue> CallResult = LowerCallTo(CLI);
5956
5957  SDValue LoadSin = DAG.getLoad(ArgVT, dl, CallResult.second, SRet,
5958                                MachinePointerInfo(), false, false, false, 0);
5959
5960  // Address of cos field.
5961  SDValue Add = DAG.getNode(ISD::ADD, dl, getPointerTy(), SRet,
5962                            DAG.getIntPtrConstant(ArgVT.getStoreSize()));
5963  SDValue LoadCos = DAG.getLoad(ArgVT, dl, LoadSin.getValue(1), Add,
5964                                MachinePointerInfo(), false, false, false, 0);
5965
5966  SDVTList Tys = DAG.getVTList(ArgVT, ArgVT);
5967  return DAG.getNode(ISD::MERGE_VALUES, dl, Tys,
5968                     LoadSin.getValue(0), LoadCos.getValue(0));
5969}
5970
5971static SDValue LowerAtomicLoadStore(SDValue Op, SelectionDAG &DAG) {
5972  // Monotonic load/store is legal for all targets
5973  if (cast<AtomicSDNode>(Op)->getOrdering() <= Monotonic)
5974    return Op;
5975
5976  // Acquire/Release load/store is not legal for targets without a
5977  // dmb or equivalent available.
5978  return SDValue();
5979}
5980
5981static void ReplaceREADCYCLECOUNTER(SDNode *N,
5982                                    SmallVectorImpl<SDValue> &Results,
5983                                    SelectionDAG &DAG,
5984                                    const ARMSubtarget *Subtarget) {
5985  SDLoc DL(N);
5986  SDValue Cycles32, OutChain;
5987
5988  if (Subtarget->hasPerfMon()) {
5989    // Under Power Management extensions, the cycle-count is:
5990    //    mrc p15, #0, <Rt>, c9, c13, #0
5991    SDValue Ops[] = { N->getOperand(0), // Chain
5992                      DAG.getConstant(Intrinsic::arm_mrc, MVT::i32),
5993                      DAG.getConstant(15, MVT::i32),
5994                      DAG.getConstant(0, MVT::i32),
5995                      DAG.getConstant(9, MVT::i32),
5996                      DAG.getConstant(13, MVT::i32),
5997                      DAG.getConstant(0, MVT::i32)
5998    };
5999
6000    Cycles32 = DAG.getNode(ISD::INTRINSIC_W_CHAIN, DL,
6001                           DAG.getVTList(MVT::i32, MVT::Other), &Ops[0],
6002                           array_lengthof(Ops));
6003    OutChain = Cycles32.getValue(1);
6004  } else {
6005    // Intrinsic is defined to return 0 on unsupported platforms. Technically
6006    // there are older ARM CPUs that have implementation-specific ways of
6007    // obtaining this information (FIXME!).
6008    Cycles32 = DAG.getConstant(0, MVT::i32);
6009    OutChain = DAG.getEntryNode();
6010  }
6011
6012
6013  SDValue Cycles64 = DAG.getNode(ISD::BUILD_PAIR, DL, MVT::i64,
6014                                 Cycles32, DAG.getConstant(0, MVT::i32));
6015  Results.push_back(Cycles64);
6016  Results.push_back(OutChain);
6017}
6018
6019SDValue ARMTargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const {
6020  switch (Op.getOpcode()) {
6021  default: llvm_unreachable("Don't know how to custom lower this!");
6022  case ISD::ConstantPool:  return LowerConstantPool(Op, DAG);
6023  case ISD::BlockAddress:  return LowerBlockAddress(Op, DAG);
6024  case ISD::GlobalAddress:
6025    return Subtarget->isTargetMachO() ? LowerGlobalAddressDarwin(Op, DAG) :
6026      LowerGlobalAddressELF(Op, DAG);
6027  case ISD::GlobalTLSAddress: return LowerGlobalTLSAddress(Op, DAG);
6028  case ISD::SELECT:        return LowerSELECT(Op, DAG);
6029  case ISD::SELECT_CC:     return LowerSELECT_CC(Op, DAG);
6030  case ISD::BR_CC:         return LowerBR_CC(Op, DAG);
6031  case ISD::BR_JT:         return LowerBR_JT(Op, DAG);
6032  case ISD::VASTART:       return LowerVASTART(Op, DAG);
6033  case ISD::ATOMIC_FENCE:  return LowerATOMIC_FENCE(Op, DAG, Subtarget);
6034  case ISD::PREFETCH:      return LowerPREFETCH(Op, DAG, Subtarget);
6035  case ISD::SINT_TO_FP:
6036  case ISD::UINT_TO_FP:    return LowerINT_TO_FP(Op, DAG);
6037  case ISD::FP_TO_SINT:
6038  case ISD::FP_TO_UINT:    return LowerFP_TO_INT(Op, DAG);
6039  case ISD::FCOPYSIGN:     return LowerFCOPYSIGN(Op, DAG);
6040  case ISD::RETURNADDR:    return LowerRETURNADDR(Op, DAG);
6041  case ISD::FRAMEADDR:     return LowerFRAMEADDR(Op, DAG);
6042  case ISD::GLOBAL_OFFSET_TABLE: return LowerGLOBAL_OFFSET_TABLE(Op, DAG);
6043  case ISD::EH_SJLJ_SETJMP: return LowerEH_SJLJ_SETJMP(Op, DAG);
6044  case ISD::EH_SJLJ_LONGJMP: return LowerEH_SJLJ_LONGJMP(Op, DAG);
6045  case ISD::INTRINSIC_WO_CHAIN: return LowerINTRINSIC_WO_CHAIN(Op, DAG,
6046                                                               Subtarget);
6047  case ISD::BITCAST:       return ExpandBITCAST(Op.getNode(), DAG);
6048  case ISD::SHL:
6049  case ISD::SRL:
6050  case ISD::SRA:           return LowerShift(Op.getNode(), DAG, Subtarget);
6051  case ISD::SHL_PARTS:     return LowerShiftLeftParts(Op, DAG);
6052  case ISD::SRL_PARTS:
6053  case ISD::SRA_PARTS:     return LowerShiftRightParts(Op, DAG);
6054  case ISD::CTTZ:          return LowerCTTZ(Op.getNode(), DAG, Subtarget);
6055  case ISD::CTPOP:         return LowerCTPOP(Op.getNode(), DAG, Subtarget);
6056  case ISD::SETCC:         return LowerVSETCC(Op, DAG);
6057  case ISD::ConstantFP:    return LowerConstantFP(Op, DAG, Subtarget);
6058  case ISD::BUILD_VECTOR:  return LowerBUILD_VECTOR(Op, DAG, Subtarget);
6059  case ISD::VECTOR_SHUFFLE: return LowerVECTOR_SHUFFLE(Op, DAG);
6060  case ISD::INSERT_VECTOR_ELT: return LowerINSERT_VECTOR_ELT(Op, DAG);
6061  case ISD::EXTRACT_VECTOR_ELT: return LowerEXTRACT_VECTOR_ELT(Op, DAG);
6062  case ISD::CONCAT_VECTORS: return LowerCONCAT_VECTORS(Op, DAG);
6063  case ISD::FLT_ROUNDS_:   return LowerFLT_ROUNDS_(Op, DAG);
6064  case ISD::MUL:           return LowerMUL(Op, DAG);
6065  case ISD::SDIV:          return LowerSDIV(Op, DAG);
6066  case ISD::UDIV:          return LowerUDIV(Op, DAG);
6067  case ISD::ADDC:
6068  case ISD::ADDE:
6069  case ISD::SUBC:
6070  case ISD::SUBE:          return LowerADDC_ADDE_SUBC_SUBE(Op, DAG);
6071  case ISD::ATOMIC_LOAD:
6072  case ISD::ATOMIC_STORE:  return LowerAtomicLoadStore(Op, DAG);
6073  case ISD::FSINCOS:       return LowerFSINCOS(Op, DAG);
6074  case ISD::SDIVREM:
6075  case ISD::UDIVREM:       return LowerDivRem(Op, DAG);
6076  }
6077}
6078
6079/// ReplaceNodeResults - Replace the results of node with an illegal result
6080/// type with new values built out of custom code.
6081void ARMTargetLowering::ReplaceNodeResults(SDNode *N,
6082                                           SmallVectorImpl<SDValue>&Results,
6083                                           SelectionDAG &DAG) const {
6084  SDValue Res;
6085  switch (N->getOpcode()) {
6086  default:
6087    llvm_unreachable("Don't know how to custom expand this!");
6088  case ISD::BITCAST:
6089    Res = ExpandBITCAST(N, DAG);
6090    break;
6091  case ISD::SRL:
6092  case ISD::SRA:
6093    Res = Expand64BitShift(N, DAG, Subtarget);
6094    break;
6095  case ISD::READCYCLECOUNTER:
6096    ReplaceREADCYCLECOUNTER(N, Results, DAG, Subtarget);
6097    return;
6098  }
6099  if (Res.getNode())
6100    Results.push_back(Res);
6101}
6102
6103//===----------------------------------------------------------------------===//
6104//                           ARM Scheduler Hooks
6105//===----------------------------------------------------------------------===//
6106
6107/// SetupEntryBlockForSjLj - Insert code into the entry block that creates and
6108/// registers the function context.
6109void ARMTargetLowering::
6110SetupEntryBlockForSjLj(MachineInstr *MI, MachineBasicBlock *MBB,
6111                       MachineBasicBlock *DispatchBB, int FI) const {
6112  const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
6113  DebugLoc dl = MI->getDebugLoc();
6114  MachineFunction *MF = MBB->getParent();
6115  MachineRegisterInfo *MRI = &MF->getRegInfo();
6116  MachineConstantPool *MCP = MF->getConstantPool();
6117  ARMFunctionInfo *AFI = MF->getInfo<ARMFunctionInfo>();
6118  const Function *F = MF->getFunction();
6119
6120  bool isThumb = Subtarget->isThumb();
6121  bool isThumb2 = Subtarget->isThumb2();
6122
6123  unsigned PCLabelId = AFI->createPICLabelUId();
6124  unsigned PCAdj = (isThumb || isThumb2) ? 4 : 8;
6125  ARMConstantPoolValue *CPV =
6126    ARMConstantPoolMBB::Create(F->getContext(), DispatchBB, PCLabelId, PCAdj);
6127  unsigned CPI = MCP->getConstantPoolIndex(CPV, 4);
6128
6129  const TargetRegisterClass *TRC = isThumb ?
6130    (const TargetRegisterClass*)&ARM::tGPRRegClass :
6131    (const TargetRegisterClass*)&ARM::GPRRegClass;
6132
6133  // Grab constant pool and fixed stack memory operands.
6134  MachineMemOperand *CPMMO =
6135    MF->getMachineMemOperand(MachinePointerInfo::getConstantPool(),
6136                             MachineMemOperand::MOLoad, 4, 4);
6137
6138  MachineMemOperand *FIMMOSt =
6139    MF->getMachineMemOperand(MachinePointerInfo::getFixedStack(FI),
6140                             MachineMemOperand::MOStore, 4, 4);
6141
6142  // Load the address of the dispatch MBB into the jump buffer.
6143  if (isThumb2) {
6144    // Incoming value: jbuf
6145    //   ldr.n  r5, LCPI1_1
6146    //   orr    r5, r5, #1
6147    //   add    r5, pc
6148    //   str    r5, [$jbuf, #+4] ; &jbuf[1]
6149    unsigned NewVReg1 = MRI->createVirtualRegister(TRC);
6150    AddDefaultPred(BuildMI(*MBB, MI, dl, TII->get(ARM::t2LDRpci), NewVReg1)
6151                   .addConstantPoolIndex(CPI)
6152                   .addMemOperand(CPMMO));
6153    // Set the low bit because of thumb mode.
6154    unsigned NewVReg2 = MRI->createVirtualRegister(TRC);
6155    AddDefaultCC(
6156      AddDefaultPred(BuildMI(*MBB, MI, dl, TII->get(ARM::t2ORRri), NewVReg2)
6157                     .addReg(NewVReg1, RegState::Kill)
6158                     .addImm(0x01)));
6159    unsigned NewVReg3 = MRI->createVirtualRegister(TRC);
6160    BuildMI(*MBB, MI, dl, TII->get(ARM::tPICADD), NewVReg3)
6161      .addReg(NewVReg2, RegState::Kill)
6162      .addImm(PCLabelId);
6163    AddDefaultPred(BuildMI(*MBB, MI, dl, TII->get(ARM::t2STRi12))
6164                   .addReg(NewVReg3, RegState::Kill)
6165                   .addFrameIndex(FI)
6166                   .addImm(36)  // &jbuf[1] :: pc
6167                   .addMemOperand(FIMMOSt));
6168  } else if (isThumb) {
6169    // Incoming value: jbuf
6170    //   ldr.n  r1, LCPI1_4
6171    //   add    r1, pc
6172    //   mov    r2, #1
6173    //   orrs   r1, r2
6174    //   add    r2, $jbuf, #+4 ; &jbuf[1]
6175    //   str    r1, [r2]
6176    unsigned NewVReg1 = MRI->createVirtualRegister(TRC);
6177    AddDefaultPred(BuildMI(*MBB, MI, dl, TII->get(ARM::tLDRpci), NewVReg1)
6178                   .addConstantPoolIndex(CPI)
6179                   .addMemOperand(CPMMO));
6180    unsigned NewVReg2 = MRI->createVirtualRegister(TRC);
6181    BuildMI(*MBB, MI, dl, TII->get(ARM::tPICADD), NewVReg2)
6182      .addReg(NewVReg1, RegState::Kill)
6183      .addImm(PCLabelId);
6184    // Set the low bit because of thumb mode.
6185    unsigned NewVReg3 = MRI->createVirtualRegister(TRC);
6186    AddDefaultPred(BuildMI(*MBB, MI, dl, TII->get(ARM::tMOVi8), NewVReg3)
6187                   .addReg(ARM::CPSR, RegState::Define)
6188                   .addImm(1));
6189    unsigned NewVReg4 = MRI->createVirtualRegister(TRC);
6190    AddDefaultPred(BuildMI(*MBB, MI, dl, TII->get(ARM::tORR), NewVReg4)
6191                   .addReg(ARM::CPSR, RegState::Define)
6192                   .addReg(NewVReg2, RegState::Kill)
6193                   .addReg(NewVReg3, RegState::Kill));
6194    unsigned NewVReg5 = MRI->createVirtualRegister(TRC);
6195    AddDefaultPred(BuildMI(*MBB, MI, dl, TII->get(ARM::tADDrSPi), NewVReg5)
6196                   .addFrameIndex(FI)
6197                   .addImm(36)); // &jbuf[1] :: pc
6198    AddDefaultPred(BuildMI(*MBB, MI, dl, TII->get(ARM::tSTRi))
6199                   .addReg(NewVReg4, RegState::Kill)
6200                   .addReg(NewVReg5, RegState::Kill)
6201                   .addImm(0)
6202                   .addMemOperand(FIMMOSt));
6203  } else {
6204    // Incoming value: jbuf
6205    //   ldr  r1, LCPI1_1
6206    //   add  r1, pc, r1
6207    //   str  r1, [$jbuf, #+4] ; &jbuf[1]
6208    unsigned NewVReg1 = MRI->createVirtualRegister(TRC);
6209    AddDefaultPred(BuildMI(*MBB, MI, dl, TII->get(ARM::LDRi12),  NewVReg1)
6210                   .addConstantPoolIndex(CPI)
6211                   .addImm(0)
6212                   .addMemOperand(CPMMO));
6213    unsigned NewVReg2 = MRI->createVirtualRegister(TRC);
6214    AddDefaultPred(BuildMI(*MBB, MI, dl, TII->get(ARM::PICADD), NewVReg2)
6215                   .addReg(NewVReg1, RegState::Kill)
6216                   .addImm(PCLabelId));
6217    AddDefaultPred(BuildMI(*MBB, MI, dl, TII->get(ARM::STRi12))
6218                   .addReg(NewVReg2, RegState::Kill)
6219                   .addFrameIndex(FI)
6220                   .addImm(36)  // &jbuf[1] :: pc
6221                   .addMemOperand(FIMMOSt));
6222  }
6223}
6224
6225MachineBasicBlock *ARMTargetLowering::
6226EmitSjLjDispatchBlock(MachineInstr *MI, MachineBasicBlock *MBB) const {
6227  const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
6228  DebugLoc dl = MI->getDebugLoc();
6229  MachineFunction *MF = MBB->getParent();
6230  MachineRegisterInfo *MRI = &MF->getRegInfo();
6231  ARMFunctionInfo *AFI = MF->getInfo<ARMFunctionInfo>();
6232  MachineFrameInfo *MFI = MF->getFrameInfo();
6233  int FI = MFI->getFunctionContextIndex();
6234
6235  const TargetRegisterClass *TRC = Subtarget->isThumb() ?
6236    (const TargetRegisterClass*)&ARM::tGPRRegClass :
6237    (const TargetRegisterClass*)&ARM::GPRnopcRegClass;
6238
6239  // Get a mapping of the call site numbers to all of the landing pads they're
6240  // associated with.
6241  DenseMap<unsigned, SmallVector<MachineBasicBlock*, 2> > CallSiteNumToLPad;
6242  unsigned MaxCSNum = 0;
6243  MachineModuleInfo &MMI = MF->getMMI();
6244  for (MachineFunction::iterator BB = MF->begin(), E = MF->end(); BB != E;
6245       ++BB) {
6246    if (!BB->isLandingPad()) continue;
6247
6248    // FIXME: We should assert that the EH_LABEL is the first MI in the landing
6249    // pad.
6250    for (MachineBasicBlock::iterator
6251           II = BB->begin(), IE = BB->end(); II != IE; ++II) {
6252      if (!II->isEHLabel()) continue;
6253
6254      MCSymbol *Sym = II->getOperand(0).getMCSymbol();
6255      if (!MMI.hasCallSiteLandingPad(Sym)) continue;
6256
6257      SmallVectorImpl<unsigned> &CallSiteIdxs = MMI.getCallSiteLandingPad(Sym);
6258      for (SmallVectorImpl<unsigned>::iterator
6259             CSI = CallSiteIdxs.begin(), CSE = CallSiteIdxs.end();
6260           CSI != CSE; ++CSI) {
6261        CallSiteNumToLPad[*CSI].push_back(BB);
6262        MaxCSNum = std::max(MaxCSNum, *CSI);
6263      }
6264      break;
6265    }
6266  }
6267
6268  // Get an ordered list of the machine basic blocks for the jump table.
6269  std::vector<MachineBasicBlock*> LPadList;
6270  SmallPtrSet<MachineBasicBlock*, 64> InvokeBBs;
6271  LPadList.reserve(CallSiteNumToLPad.size());
6272  for (unsigned I = 1; I <= MaxCSNum; ++I) {
6273    SmallVectorImpl<MachineBasicBlock*> &MBBList = CallSiteNumToLPad[I];
6274    for (SmallVectorImpl<MachineBasicBlock*>::iterator
6275           II = MBBList.begin(), IE = MBBList.end(); II != IE; ++II) {
6276      LPadList.push_back(*II);
6277      InvokeBBs.insert((*II)->pred_begin(), (*II)->pred_end());
6278    }
6279  }
6280
6281  assert(!LPadList.empty() &&
6282         "No landing pad destinations for the dispatch jump table!");
6283
6284  // Create the jump table and associated information.
6285  MachineJumpTableInfo *JTI =
6286    MF->getOrCreateJumpTableInfo(MachineJumpTableInfo::EK_Inline);
6287  unsigned MJTI = JTI->createJumpTableIndex(LPadList);
6288  unsigned UId = AFI->createJumpTableUId();
6289  Reloc::Model RelocM = getTargetMachine().getRelocationModel();
6290
6291  // Create the MBBs for the dispatch code.
6292
6293  // Shove the dispatch's address into the return slot in the function context.
6294  MachineBasicBlock *DispatchBB = MF->CreateMachineBasicBlock();
6295  DispatchBB->setIsLandingPad();
6296
6297  MachineBasicBlock *TrapBB = MF->CreateMachineBasicBlock();
6298  unsigned trap_opcode;
6299  if (Subtarget->isThumb())
6300    trap_opcode = ARM::tTRAP;
6301  else
6302    trap_opcode = Subtarget->useNaClTrap() ? ARM::TRAPNaCl : ARM::TRAP;
6303
6304  BuildMI(TrapBB, dl, TII->get(trap_opcode));
6305  DispatchBB->addSuccessor(TrapBB);
6306
6307  MachineBasicBlock *DispContBB = MF->CreateMachineBasicBlock();
6308  DispatchBB->addSuccessor(DispContBB);
6309
6310  // Insert and MBBs.
6311  MF->insert(MF->end(), DispatchBB);
6312  MF->insert(MF->end(), DispContBB);
6313  MF->insert(MF->end(), TrapBB);
6314
6315  // Insert code into the entry block that creates and registers the function
6316  // context.
6317  SetupEntryBlockForSjLj(MI, MBB, DispatchBB, FI);
6318
6319  MachineMemOperand *FIMMOLd =
6320    MF->getMachineMemOperand(MachinePointerInfo::getFixedStack(FI),
6321                             MachineMemOperand::MOLoad |
6322                             MachineMemOperand::MOVolatile, 4, 4);
6323
6324  MachineInstrBuilder MIB;
6325  MIB = BuildMI(DispatchBB, dl, TII->get(ARM::Int_eh_sjlj_dispatchsetup));
6326
6327  const ARMBaseInstrInfo *AII = static_cast<const ARMBaseInstrInfo*>(TII);
6328  const ARMBaseRegisterInfo &RI = AII->getRegisterInfo();
6329
6330  // Add a register mask with no preserved registers.  This results in all
6331  // registers being marked as clobbered.
6332  MIB.addRegMask(RI.getNoPreservedMask());
6333
6334  unsigned NumLPads = LPadList.size();
6335  if (Subtarget->isThumb2()) {
6336    unsigned NewVReg1 = MRI->createVirtualRegister(TRC);
6337    AddDefaultPred(BuildMI(DispatchBB, dl, TII->get(ARM::t2LDRi12), NewVReg1)
6338                   .addFrameIndex(FI)
6339                   .addImm(4)
6340                   .addMemOperand(FIMMOLd));
6341
6342    if (NumLPads < 256) {
6343      AddDefaultPred(BuildMI(DispatchBB, dl, TII->get(ARM::t2CMPri))
6344                     .addReg(NewVReg1)
6345                     .addImm(LPadList.size()));
6346    } else {
6347      unsigned VReg1 = MRI->createVirtualRegister(TRC);
6348      AddDefaultPred(BuildMI(DispatchBB, dl, TII->get(ARM::t2MOVi16), VReg1)
6349                     .addImm(NumLPads & 0xFFFF));
6350
6351      unsigned VReg2 = VReg1;
6352      if ((NumLPads & 0xFFFF0000) != 0) {
6353        VReg2 = MRI->createVirtualRegister(TRC);
6354        AddDefaultPred(BuildMI(DispatchBB, dl, TII->get(ARM::t2MOVTi16), VReg2)
6355                       .addReg(VReg1)
6356                       .addImm(NumLPads >> 16));
6357      }
6358
6359      AddDefaultPred(BuildMI(DispatchBB, dl, TII->get(ARM::t2CMPrr))
6360                     .addReg(NewVReg1)
6361                     .addReg(VReg2));
6362    }
6363
6364    BuildMI(DispatchBB, dl, TII->get(ARM::t2Bcc))
6365      .addMBB(TrapBB)
6366      .addImm(ARMCC::HI)
6367      .addReg(ARM::CPSR);
6368
6369    unsigned NewVReg3 = MRI->createVirtualRegister(TRC);
6370    AddDefaultPred(BuildMI(DispContBB, dl, TII->get(ARM::t2LEApcrelJT),NewVReg3)
6371                   .addJumpTableIndex(MJTI)
6372                   .addImm(UId));
6373
6374    unsigned NewVReg4 = MRI->createVirtualRegister(TRC);
6375    AddDefaultCC(
6376      AddDefaultPred(
6377        BuildMI(DispContBB, dl, TII->get(ARM::t2ADDrs), NewVReg4)
6378        .addReg(NewVReg3, RegState::Kill)
6379        .addReg(NewVReg1)
6380        .addImm(ARM_AM::getSORegOpc(ARM_AM::lsl, 2))));
6381
6382    BuildMI(DispContBB, dl, TII->get(ARM::t2BR_JT))
6383      .addReg(NewVReg4, RegState::Kill)
6384      .addReg(NewVReg1)
6385      .addJumpTableIndex(MJTI)
6386      .addImm(UId);
6387  } else if (Subtarget->isThumb()) {
6388    unsigned NewVReg1 = MRI->createVirtualRegister(TRC);
6389    AddDefaultPred(BuildMI(DispatchBB, dl, TII->get(ARM::tLDRspi), NewVReg1)
6390                   .addFrameIndex(FI)
6391                   .addImm(1)
6392                   .addMemOperand(FIMMOLd));
6393
6394    if (NumLPads < 256) {
6395      AddDefaultPred(BuildMI(DispatchBB, dl, TII->get(ARM::tCMPi8))
6396                     .addReg(NewVReg1)
6397                     .addImm(NumLPads));
6398    } else {
6399      MachineConstantPool *ConstantPool = MF->getConstantPool();
6400      Type *Int32Ty = Type::getInt32Ty(MF->getFunction()->getContext());
6401      const Constant *C = ConstantInt::get(Int32Ty, NumLPads);
6402
6403      // MachineConstantPool wants an explicit alignment.
6404      unsigned Align = getDataLayout()->getPrefTypeAlignment(Int32Ty);
6405      if (Align == 0)
6406        Align = getDataLayout()->getTypeAllocSize(C->getType());
6407      unsigned Idx = ConstantPool->getConstantPoolIndex(C, Align);
6408
6409      unsigned VReg1 = MRI->createVirtualRegister(TRC);
6410      AddDefaultPred(BuildMI(DispatchBB, dl, TII->get(ARM::tLDRpci))
6411                     .addReg(VReg1, RegState::Define)
6412                     .addConstantPoolIndex(Idx));
6413      AddDefaultPred(BuildMI(DispatchBB, dl, TII->get(ARM::tCMPr))
6414                     .addReg(NewVReg1)
6415                     .addReg(VReg1));
6416    }
6417
6418    BuildMI(DispatchBB, dl, TII->get(ARM::tBcc))
6419      .addMBB(TrapBB)
6420      .addImm(ARMCC::HI)
6421      .addReg(ARM::CPSR);
6422
6423    unsigned NewVReg2 = MRI->createVirtualRegister(TRC);
6424    AddDefaultPred(BuildMI(DispContBB, dl, TII->get(ARM::tLSLri), NewVReg2)
6425                   .addReg(ARM::CPSR, RegState::Define)
6426                   .addReg(NewVReg1)
6427                   .addImm(2));
6428
6429    unsigned NewVReg3 = MRI->createVirtualRegister(TRC);
6430    AddDefaultPred(BuildMI(DispContBB, dl, TII->get(ARM::tLEApcrelJT), NewVReg3)
6431                   .addJumpTableIndex(MJTI)
6432                   .addImm(UId));
6433
6434    unsigned NewVReg4 = MRI->createVirtualRegister(TRC);
6435    AddDefaultPred(BuildMI(DispContBB, dl, TII->get(ARM::tADDrr), NewVReg4)
6436                   .addReg(ARM::CPSR, RegState::Define)
6437                   .addReg(NewVReg2, RegState::Kill)
6438                   .addReg(NewVReg3));
6439
6440    MachineMemOperand *JTMMOLd =
6441      MF->getMachineMemOperand(MachinePointerInfo::getJumpTable(),
6442                               MachineMemOperand::MOLoad, 4, 4);
6443
6444    unsigned NewVReg5 = MRI->createVirtualRegister(TRC);
6445    AddDefaultPred(BuildMI(DispContBB, dl, TII->get(ARM::tLDRi), NewVReg5)
6446                   .addReg(NewVReg4, RegState::Kill)
6447                   .addImm(0)
6448                   .addMemOperand(JTMMOLd));
6449
6450    unsigned NewVReg6 = NewVReg5;
6451    if (RelocM == Reloc::PIC_) {
6452      NewVReg6 = MRI->createVirtualRegister(TRC);
6453      AddDefaultPred(BuildMI(DispContBB, dl, TII->get(ARM::tADDrr), NewVReg6)
6454                     .addReg(ARM::CPSR, RegState::Define)
6455                     .addReg(NewVReg5, RegState::Kill)
6456                     .addReg(NewVReg3));
6457    }
6458
6459    BuildMI(DispContBB, dl, TII->get(ARM::tBR_JTr))
6460      .addReg(NewVReg6, RegState::Kill)
6461      .addJumpTableIndex(MJTI)
6462      .addImm(UId);
6463  } else {
6464    unsigned NewVReg1 = MRI->createVirtualRegister(TRC);
6465    AddDefaultPred(BuildMI(DispatchBB, dl, TII->get(ARM::LDRi12), NewVReg1)
6466                   .addFrameIndex(FI)
6467                   .addImm(4)
6468                   .addMemOperand(FIMMOLd));
6469
6470    if (NumLPads < 256) {
6471      AddDefaultPred(BuildMI(DispatchBB, dl, TII->get(ARM::CMPri))
6472                     .addReg(NewVReg1)
6473                     .addImm(NumLPads));
6474    } else if (Subtarget->hasV6T2Ops() && isUInt<16>(NumLPads)) {
6475      unsigned VReg1 = MRI->createVirtualRegister(TRC);
6476      AddDefaultPred(BuildMI(DispatchBB, dl, TII->get(ARM::MOVi16), VReg1)
6477                     .addImm(NumLPads & 0xFFFF));
6478
6479      unsigned VReg2 = VReg1;
6480      if ((NumLPads & 0xFFFF0000) != 0) {
6481        VReg2 = MRI->createVirtualRegister(TRC);
6482        AddDefaultPred(BuildMI(DispatchBB, dl, TII->get(ARM::MOVTi16), VReg2)
6483                       .addReg(VReg1)
6484                       .addImm(NumLPads >> 16));
6485      }
6486
6487      AddDefaultPred(BuildMI(DispatchBB, dl, TII->get(ARM::CMPrr))
6488                     .addReg(NewVReg1)
6489                     .addReg(VReg2));
6490    } else {
6491      MachineConstantPool *ConstantPool = MF->getConstantPool();
6492      Type *Int32Ty = Type::getInt32Ty(MF->getFunction()->getContext());
6493      const Constant *C = ConstantInt::get(Int32Ty, NumLPads);
6494
6495      // MachineConstantPool wants an explicit alignment.
6496      unsigned Align = getDataLayout()->getPrefTypeAlignment(Int32Ty);
6497      if (Align == 0)
6498        Align = getDataLayout()->getTypeAllocSize(C->getType());
6499      unsigned Idx = ConstantPool->getConstantPoolIndex(C, Align);
6500
6501      unsigned VReg1 = MRI->createVirtualRegister(TRC);
6502      AddDefaultPred(BuildMI(DispatchBB, dl, TII->get(ARM::LDRcp))
6503                     .addReg(VReg1, RegState::Define)
6504                     .addConstantPoolIndex(Idx)
6505                     .addImm(0));
6506      AddDefaultPred(BuildMI(DispatchBB, dl, TII->get(ARM::CMPrr))
6507                     .addReg(NewVReg1)
6508                     .addReg(VReg1, RegState::Kill));
6509    }
6510
6511    BuildMI(DispatchBB, dl, TII->get(ARM::Bcc))
6512      .addMBB(TrapBB)
6513      .addImm(ARMCC::HI)
6514      .addReg(ARM::CPSR);
6515
6516    unsigned NewVReg3 = MRI->createVirtualRegister(TRC);
6517    AddDefaultCC(
6518      AddDefaultPred(BuildMI(DispContBB, dl, TII->get(ARM::MOVsi), NewVReg3)
6519                     .addReg(NewVReg1)
6520                     .addImm(ARM_AM::getSORegOpc(ARM_AM::lsl, 2))));
6521    unsigned NewVReg4 = MRI->createVirtualRegister(TRC);
6522    AddDefaultPred(BuildMI(DispContBB, dl, TII->get(ARM::LEApcrelJT), NewVReg4)
6523                   .addJumpTableIndex(MJTI)
6524                   .addImm(UId));
6525
6526    MachineMemOperand *JTMMOLd =
6527      MF->getMachineMemOperand(MachinePointerInfo::getJumpTable(),
6528                               MachineMemOperand::MOLoad, 4, 4);
6529    unsigned NewVReg5 = MRI->createVirtualRegister(TRC);
6530    AddDefaultPred(
6531      BuildMI(DispContBB, dl, TII->get(ARM::LDRrs), NewVReg5)
6532      .addReg(NewVReg3, RegState::Kill)
6533      .addReg(NewVReg4)
6534      .addImm(0)
6535      .addMemOperand(JTMMOLd));
6536
6537    if (RelocM == Reloc::PIC_) {
6538      BuildMI(DispContBB, dl, TII->get(ARM::BR_JTadd))
6539        .addReg(NewVReg5, RegState::Kill)
6540        .addReg(NewVReg4)
6541        .addJumpTableIndex(MJTI)
6542        .addImm(UId);
6543    } else {
6544      BuildMI(DispContBB, dl, TII->get(ARM::BR_JTr))
6545        .addReg(NewVReg5, RegState::Kill)
6546        .addJumpTableIndex(MJTI)
6547        .addImm(UId);
6548    }
6549  }
6550
6551  // Add the jump table entries as successors to the MBB.
6552  SmallPtrSet<MachineBasicBlock*, 8> SeenMBBs;
6553  for (std::vector<MachineBasicBlock*>::iterator
6554         I = LPadList.begin(), E = LPadList.end(); I != E; ++I) {
6555    MachineBasicBlock *CurMBB = *I;
6556    if (SeenMBBs.insert(CurMBB))
6557      DispContBB->addSuccessor(CurMBB);
6558  }
6559
6560  // N.B. the order the invoke BBs are processed in doesn't matter here.
6561  const uint16_t *SavedRegs = RI.getCalleeSavedRegs(MF);
6562  SmallVector<MachineBasicBlock*, 64> MBBLPads;
6563  for (SmallPtrSet<MachineBasicBlock*, 64>::iterator
6564         I = InvokeBBs.begin(), E = InvokeBBs.end(); I != E; ++I) {
6565    MachineBasicBlock *BB = *I;
6566
6567    // Remove the landing pad successor from the invoke block and replace it
6568    // with the new dispatch block.
6569    SmallVector<MachineBasicBlock*, 4> Successors(BB->succ_begin(),
6570                                                  BB->succ_end());
6571    while (!Successors.empty()) {
6572      MachineBasicBlock *SMBB = Successors.pop_back_val();
6573      if (SMBB->isLandingPad()) {
6574        BB->removeSuccessor(SMBB);
6575        MBBLPads.push_back(SMBB);
6576      }
6577    }
6578
6579    BB->addSuccessor(DispatchBB);
6580
6581    // Find the invoke call and mark all of the callee-saved registers as
6582    // 'implicit defined' so that they're spilled. This prevents code from
6583    // moving instructions to before the EH block, where they will never be
6584    // executed.
6585    for (MachineBasicBlock::reverse_iterator
6586           II = BB->rbegin(), IE = BB->rend(); II != IE; ++II) {
6587      if (!II->isCall()) continue;
6588
6589      DenseMap<unsigned, bool> DefRegs;
6590      for (MachineInstr::mop_iterator
6591             OI = II->operands_begin(), OE = II->operands_end();
6592           OI != OE; ++OI) {
6593        if (!OI->isReg()) continue;
6594        DefRegs[OI->getReg()] = true;
6595      }
6596
6597      MachineInstrBuilder MIB(*MF, &*II);
6598
6599      for (unsigned i = 0; SavedRegs[i] != 0; ++i) {
6600        unsigned Reg = SavedRegs[i];
6601        if (Subtarget->isThumb2() &&
6602            !ARM::tGPRRegClass.contains(Reg) &&
6603            !ARM::hGPRRegClass.contains(Reg))
6604          continue;
6605        if (Subtarget->isThumb1Only() && !ARM::tGPRRegClass.contains(Reg))
6606          continue;
6607        if (!Subtarget->isThumb() && !ARM::GPRRegClass.contains(Reg))
6608          continue;
6609        if (!DefRegs[Reg])
6610          MIB.addReg(Reg, RegState::ImplicitDefine | RegState::Dead);
6611      }
6612
6613      break;
6614    }
6615  }
6616
6617  // Mark all former landing pads as non-landing pads. The dispatch is the only
6618  // landing pad now.
6619  for (SmallVectorImpl<MachineBasicBlock*>::iterator
6620         I = MBBLPads.begin(), E = MBBLPads.end(); I != E; ++I)
6621    (*I)->setIsLandingPad(false);
6622
6623  // The instruction is gone now.
6624  MI->eraseFromParent();
6625
6626  return MBB;
6627}
6628
6629static
6630MachineBasicBlock *OtherSucc(MachineBasicBlock *MBB, MachineBasicBlock *Succ) {
6631  for (MachineBasicBlock::succ_iterator I = MBB->succ_begin(),
6632       E = MBB->succ_end(); I != E; ++I)
6633    if (*I != Succ)
6634      return *I;
6635  llvm_unreachable("Expecting a BB with two successors!");
6636}
6637
6638/// Return the load opcode for a given load size. If load size >= 8,
6639/// neon opcode will be returned.
6640static unsigned getLdOpcode(unsigned LdSize, bool IsThumb1, bool IsThumb2) {
6641  if (LdSize >= 8)
6642    return LdSize == 16 ? ARM::VLD1q32wb_fixed
6643                        : LdSize == 8 ? ARM::VLD1d32wb_fixed : 0;
6644  if (IsThumb1)
6645    return LdSize == 4 ? ARM::tLDRi
6646                       : LdSize == 2 ? ARM::tLDRHi
6647                                     : LdSize == 1 ? ARM::tLDRBi : 0;
6648  if (IsThumb2)
6649    return LdSize == 4 ? ARM::t2LDR_POST
6650                       : LdSize == 2 ? ARM::t2LDRH_POST
6651                                     : LdSize == 1 ? ARM::t2LDRB_POST : 0;
6652  return LdSize == 4 ? ARM::LDR_POST_IMM
6653                     : LdSize == 2 ? ARM::LDRH_POST
6654                                   : LdSize == 1 ? ARM::LDRB_POST_IMM : 0;
6655}
6656
6657/// Return the store opcode for a given store size. If store size >= 8,
6658/// neon opcode will be returned.
6659static unsigned getStOpcode(unsigned StSize, bool IsThumb1, bool IsThumb2) {
6660  if (StSize >= 8)
6661    return StSize == 16 ? ARM::VST1q32wb_fixed
6662                        : StSize == 8 ? ARM::VST1d32wb_fixed : 0;
6663  if (IsThumb1)
6664    return StSize == 4 ? ARM::tSTRi
6665                       : StSize == 2 ? ARM::tSTRHi
6666                                     : StSize == 1 ? ARM::tSTRBi : 0;
6667  if (IsThumb2)
6668    return StSize == 4 ? ARM::t2STR_POST
6669                       : StSize == 2 ? ARM::t2STRH_POST
6670                                     : StSize == 1 ? ARM::t2STRB_POST : 0;
6671  return StSize == 4 ? ARM::STR_POST_IMM
6672                     : StSize == 2 ? ARM::STRH_POST
6673                                   : StSize == 1 ? ARM::STRB_POST_IMM : 0;
6674}
6675
6676/// Emit a post-increment load operation with given size. The instructions
6677/// will be added to BB at Pos.
6678static void emitPostLd(MachineBasicBlock *BB, MachineInstr *Pos,
6679                       const TargetInstrInfo *TII, DebugLoc dl,
6680                       unsigned LdSize, unsigned Data, unsigned AddrIn,
6681                       unsigned AddrOut, bool IsThumb1, bool IsThumb2) {
6682  unsigned LdOpc = getLdOpcode(LdSize, IsThumb1, IsThumb2);
6683  assert(LdOpc != 0 && "Should have a load opcode");
6684  if (LdSize >= 8) {
6685    AddDefaultPred(BuildMI(*BB, Pos, dl, TII->get(LdOpc), Data)
6686                       .addReg(AddrOut, RegState::Define).addReg(AddrIn)
6687                       .addImm(0));
6688  } else if (IsThumb1) {
6689    // load + update AddrIn
6690    AddDefaultPred(BuildMI(*BB, Pos, dl, TII->get(LdOpc), Data)
6691                       .addReg(AddrIn).addImm(0));
6692    MachineInstrBuilder MIB =
6693        BuildMI(*BB, Pos, dl, TII->get(ARM::tADDi8), AddrOut);
6694    MIB = AddDefaultT1CC(MIB);
6695    MIB.addReg(AddrIn).addImm(LdSize);
6696    AddDefaultPred(MIB);
6697  } else if (IsThumb2) {
6698    AddDefaultPred(BuildMI(*BB, Pos, dl, TII->get(LdOpc), Data)
6699                       .addReg(AddrOut, RegState::Define).addReg(AddrIn)
6700                       .addImm(LdSize));
6701  } else { // arm
6702    AddDefaultPred(BuildMI(*BB, Pos, dl, TII->get(LdOpc), Data)
6703                       .addReg(AddrOut, RegState::Define).addReg(AddrIn)
6704                       .addReg(0).addImm(LdSize));
6705  }
6706}
6707
6708/// Emit a post-increment store operation with given size. The instructions
6709/// will be added to BB at Pos.
6710static void emitPostSt(MachineBasicBlock *BB, MachineInstr *Pos,
6711                       const TargetInstrInfo *TII, DebugLoc dl,
6712                       unsigned StSize, unsigned Data, unsigned AddrIn,
6713                       unsigned AddrOut, bool IsThumb1, bool IsThumb2) {
6714  unsigned StOpc = getStOpcode(StSize, IsThumb1, IsThumb2);
6715  assert(StOpc != 0 && "Should have a store opcode");
6716  if (StSize >= 8) {
6717    AddDefaultPred(BuildMI(*BB, Pos, dl, TII->get(StOpc), AddrOut)
6718                       .addReg(AddrIn).addImm(0).addReg(Data));
6719  } else if (IsThumb1) {
6720    // store + update AddrIn
6721    AddDefaultPred(BuildMI(*BB, Pos, dl, TII->get(StOpc)).addReg(Data)
6722                       .addReg(AddrIn).addImm(0));
6723    MachineInstrBuilder MIB =
6724        BuildMI(*BB, Pos, dl, TII->get(ARM::tADDi8), AddrOut);
6725    MIB = AddDefaultT1CC(MIB);
6726    MIB.addReg(AddrIn).addImm(StSize);
6727    AddDefaultPred(MIB);
6728  } else if (IsThumb2) {
6729    AddDefaultPred(BuildMI(*BB, Pos, dl, TII->get(StOpc), AddrOut)
6730                       .addReg(Data).addReg(AddrIn).addImm(StSize));
6731  } else { // arm
6732    AddDefaultPred(BuildMI(*BB, Pos, dl, TII->get(StOpc), AddrOut)
6733                       .addReg(Data).addReg(AddrIn).addReg(0)
6734                       .addImm(StSize));
6735  }
6736}
6737
6738MachineBasicBlock *
6739ARMTargetLowering::EmitStructByval(MachineInstr *MI,
6740                                   MachineBasicBlock *BB) const {
6741  // This pseudo instruction has 3 operands: dst, src, size
6742  // We expand it to a loop if size > Subtarget->getMaxInlineSizeThreshold().
6743  // Otherwise, we will generate unrolled scalar copies.
6744  const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
6745  const BasicBlock *LLVM_BB = BB->getBasicBlock();
6746  MachineFunction::iterator It = BB;
6747  ++It;
6748
6749  unsigned dest = MI->getOperand(0).getReg();
6750  unsigned src = MI->getOperand(1).getReg();
6751  unsigned SizeVal = MI->getOperand(2).getImm();
6752  unsigned Align = MI->getOperand(3).getImm();
6753  DebugLoc dl = MI->getDebugLoc();
6754
6755  MachineFunction *MF = BB->getParent();
6756  MachineRegisterInfo &MRI = MF->getRegInfo();
6757  unsigned UnitSize = 0;
6758  const TargetRegisterClass *TRC = 0;
6759  const TargetRegisterClass *VecTRC = 0;
6760
6761  bool IsThumb1 = Subtarget->isThumb1Only();
6762  bool IsThumb2 = Subtarget->isThumb2();
6763
6764  if (Align & 1) {
6765    UnitSize = 1;
6766  } else if (Align & 2) {
6767    UnitSize = 2;
6768  } else {
6769    // Check whether we can use NEON instructions.
6770    if (!MF->getFunction()->getAttributes().
6771          hasAttribute(AttributeSet::FunctionIndex,
6772                       Attribute::NoImplicitFloat) &&
6773        Subtarget->hasNEON()) {
6774      if ((Align % 16 == 0) && SizeVal >= 16)
6775        UnitSize = 16;
6776      else if ((Align % 8 == 0) && SizeVal >= 8)
6777        UnitSize = 8;
6778    }
6779    // Can't use NEON instructions.
6780    if (UnitSize == 0)
6781      UnitSize = 4;
6782  }
6783
6784  // Select the correct opcode and register class for unit size load/store
6785  bool IsNeon = UnitSize >= 8;
6786  TRC = (IsThumb1 || IsThumb2) ? (const TargetRegisterClass *)&ARM::tGPRRegClass
6787                               : (const TargetRegisterClass *)&ARM::GPRRegClass;
6788  if (IsNeon)
6789    VecTRC = UnitSize == 16
6790                 ? (const TargetRegisterClass *)&ARM::DPairRegClass
6791                 : UnitSize == 8
6792                       ? (const TargetRegisterClass *)&ARM::DPRRegClass
6793                       : 0;
6794
6795  unsigned BytesLeft = SizeVal % UnitSize;
6796  unsigned LoopSize = SizeVal - BytesLeft;
6797
6798  if (SizeVal <= Subtarget->getMaxInlineSizeThreshold()) {
6799    // Use LDR and STR to copy.
6800    // [scratch, srcOut] = LDR_POST(srcIn, UnitSize)
6801    // [destOut] = STR_POST(scratch, destIn, UnitSize)
6802    unsigned srcIn = src;
6803    unsigned destIn = dest;
6804    for (unsigned i = 0; i < LoopSize; i+=UnitSize) {
6805      unsigned srcOut = MRI.createVirtualRegister(TRC);
6806      unsigned destOut = MRI.createVirtualRegister(TRC);
6807      unsigned scratch = MRI.createVirtualRegister(IsNeon ? VecTRC : TRC);
6808      emitPostLd(BB, MI, TII, dl, UnitSize, scratch, srcIn, srcOut,
6809                 IsThumb1, IsThumb2);
6810      emitPostSt(BB, MI, TII, dl, UnitSize, scratch, destIn, destOut,
6811                 IsThumb1, IsThumb2);
6812      srcIn = srcOut;
6813      destIn = destOut;
6814    }
6815
6816    // Handle the leftover bytes with LDRB and STRB.
6817    // [scratch, srcOut] = LDRB_POST(srcIn, 1)
6818    // [destOut] = STRB_POST(scratch, destIn, 1)
6819    for (unsigned i = 0; i < BytesLeft; i++) {
6820      unsigned srcOut = MRI.createVirtualRegister(TRC);
6821      unsigned destOut = MRI.createVirtualRegister(TRC);
6822      unsigned scratch = MRI.createVirtualRegister(TRC);
6823      emitPostLd(BB, MI, TII, dl, 1, scratch, srcIn, srcOut,
6824                 IsThumb1, IsThumb2);
6825      emitPostSt(BB, MI, TII, dl, 1, scratch, destIn, destOut,
6826                 IsThumb1, IsThumb2);
6827      srcIn = srcOut;
6828      destIn = destOut;
6829    }
6830    MI->eraseFromParent();   // The instruction is gone now.
6831    return BB;
6832  }
6833
6834  // Expand the pseudo op to a loop.
6835  // thisMBB:
6836  //   ...
6837  //   movw varEnd, # --> with thumb2
6838  //   movt varEnd, #
6839  //   ldrcp varEnd, idx --> without thumb2
6840  //   fallthrough --> loopMBB
6841  // loopMBB:
6842  //   PHI varPhi, varEnd, varLoop
6843  //   PHI srcPhi, src, srcLoop
6844  //   PHI destPhi, dst, destLoop
6845  //   [scratch, srcLoop] = LDR_POST(srcPhi, UnitSize)
6846  //   [destLoop] = STR_POST(scratch, destPhi, UnitSize)
6847  //   subs varLoop, varPhi, #UnitSize
6848  //   bne loopMBB
6849  //   fallthrough --> exitMBB
6850  // exitMBB:
6851  //   epilogue to handle left-over bytes
6852  //   [scratch, srcOut] = LDRB_POST(srcLoop, 1)
6853  //   [destOut] = STRB_POST(scratch, destLoop, 1)
6854  MachineBasicBlock *loopMBB = MF->CreateMachineBasicBlock(LLVM_BB);
6855  MachineBasicBlock *exitMBB = MF->CreateMachineBasicBlock(LLVM_BB);
6856  MF->insert(It, loopMBB);
6857  MF->insert(It, exitMBB);
6858
6859  // Transfer the remainder of BB and its successor edges to exitMBB.
6860  exitMBB->splice(exitMBB->begin(), BB,
6861                  std::next(MachineBasicBlock::iterator(MI)), BB->end());
6862  exitMBB->transferSuccessorsAndUpdatePHIs(BB);
6863
6864  // Load an immediate to varEnd.
6865  unsigned varEnd = MRI.createVirtualRegister(TRC);
6866  if (IsThumb2) {
6867    unsigned Vtmp = varEnd;
6868    if ((LoopSize & 0xFFFF0000) != 0)
6869      Vtmp = MRI.createVirtualRegister(TRC);
6870    AddDefaultPred(BuildMI(BB, dl, TII->get(ARM::t2MOVi16), Vtmp)
6871                       .addImm(LoopSize & 0xFFFF));
6872
6873    if ((LoopSize & 0xFFFF0000) != 0)
6874      AddDefaultPred(BuildMI(BB, dl, TII->get(ARM::t2MOVTi16), varEnd)
6875                         .addReg(Vtmp).addImm(LoopSize >> 16));
6876  } else {
6877    MachineConstantPool *ConstantPool = MF->getConstantPool();
6878    Type *Int32Ty = Type::getInt32Ty(MF->getFunction()->getContext());
6879    const Constant *C = ConstantInt::get(Int32Ty, LoopSize);
6880
6881    // MachineConstantPool wants an explicit alignment.
6882    unsigned Align = getDataLayout()->getPrefTypeAlignment(Int32Ty);
6883    if (Align == 0)
6884      Align = getDataLayout()->getTypeAllocSize(C->getType());
6885    unsigned Idx = ConstantPool->getConstantPoolIndex(C, Align);
6886
6887    if (IsThumb1)
6888      AddDefaultPred(BuildMI(*BB, MI, dl, TII->get(ARM::tLDRpci)).addReg(
6889          varEnd, RegState::Define).addConstantPoolIndex(Idx));
6890    else
6891      AddDefaultPred(BuildMI(*BB, MI, dl, TII->get(ARM::LDRcp)).addReg(
6892          varEnd, RegState::Define).addConstantPoolIndex(Idx).addImm(0));
6893  }
6894  BB->addSuccessor(loopMBB);
6895
6896  // Generate the loop body:
6897  //   varPhi = PHI(varLoop, varEnd)
6898  //   srcPhi = PHI(srcLoop, src)
6899  //   destPhi = PHI(destLoop, dst)
6900  MachineBasicBlock *entryBB = BB;
6901  BB = loopMBB;
6902  unsigned varLoop = MRI.createVirtualRegister(TRC);
6903  unsigned varPhi = MRI.createVirtualRegister(TRC);
6904  unsigned srcLoop = MRI.createVirtualRegister(TRC);
6905  unsigned srcPhi = MRI.createVirtualRegister(TRC);
6906  unsigned destLoop = MRI.createVirtualRegister(TRC);
6907  unsigned destPhi = MRI.createVirtualRegister(TRC);
6908
6909  BuildMI(*BB, BB->begin(), dl, TII->get(ARM::PHI), varPhi)
6910    .addReg(varLoop).addMBB(loopMBB)
6911    .addReg(varEnd).addMBB(entryBB);
6912  BuildMI(BB, dl, TII->get(ARM::PHI), srcPhi)
6913    .addReg(srcLoop).addMBB(loopMBB)
6914    .addReg(src).addMBB(entryBB);
6915  BuildMI(BB, dl, TII->get(ARM::PHI), destPhi)
6916    .addReg(destLoop).addMBB(loopMBB)
6917    .addReg(dest).addMBB(entryBB);
6918
6919  //   [scratch, srcLoop] = LDR_POST(srcPhi, UnitSize)
6920  //   [destLoop] = STR_POST(scratch, destPhi, UnitSiz)
6921  unsigned scratch = MRI.createVirtualRegister(IsNeon ? VecTRC : TRC);
6922  emitPostLd(BB, BB->end(), TII, dl, UnitSize, scratch, srcPhi, srcLoop,
6923             IsThumb1, IsThumb2);
6924  emitPostSt(BB, BB->end(), TII, dl, UnitSize, scratch, destPhi, destLoop,
6925             IsThumb1, IsThumb2);
6926
6927  // Decrement loop variable by UnitSize.
6928  if (IsThumb1) {
6929    MachineInstrBuilder MIB =
6930        BuildMI(*BB, BB->end(), dl, TII->get(ARM::tSUBi8), varLoop);
6931    MIB = AddDefaultT1CC(MIB);
6932    MIB.addReg(varPhi).addImm(UnitSize);
6933    AddDefaultPred(MIB);
6934  } else {
6935    MachineInstrBuilder MIB =
6936        BuildMI(*BB, BB->end(), dl,
6937                TII->get(IsThumb2 ? ARM::t2SUBri : ARM::SUBri), varLoop);
6938    AddDefaultCC(AddDefaultPred(MIB.addReg(varPhi).addImm(UnitSize)));
6939    MIB->getOperand(5).setReg(ARM::CPSR);
6940    MIB->getOperand(5).setIsDef(true);
6941  }
6942  BuildMI(*BB, BB->end(), dl,
6943          TII->get(IsThumb1 ? ARM::tBcc : IsThumb2 ? ARM::t2Bcc : ARM::Bcc))
6944      .addMBB(loopMBB).addImm(ARMCC::NE).addReg(ARM::CPSR);
6945
6946  // loopMBB can loop back to loopMBB or fall through to exitMBB.
6947  BB->addSuccessor(loopMBB);
6948  BB->addSuccessor(exitMBB);
6949
6950  // Add epilogue to handle BytesLeft.
6951  BB = exitMBB;
6952  MachineInstr *StartOfExit = exitMBB->begin();
6953
6954  //   [scratch, srcOut] = LDRB_POST(srcLoop, 1)
6955  //   [destOut] = STRB_POST(scratch, destLoop, 1)
6956  unsigned srcIn = srcLoop;
6957  unsigned destIn = destLoop;
6958  for (unsigned i = 0; i < BytesLeft; i++) {
6959    unsigned srcOut = MRI.createVirtualRegister(TRC);
6960    unsigned destOut = MRI.createVirtualRegister(TRC);
6961    unsigned scratch = MRI.createVirtualRegister(TRC);
6962    emitPostLd(BB, StartOfExit, TII, dl, 1, scratch, srcIn, srcOut,
6963               IsThumb1, IsThumb2);
6964    emitPostSt(BB, StartOfExit, TII, dl, 1, scratch, destIn, destOut,
6965               IsThumb1, IsThumb2);
6966    srcIn = srcOut;
6967    destIn = destOut;
6968  }
6969
6970  MI->eraseFromParent();   // The instruction is gone now.
6971  return BB;
6972}
6973
6974MachineBasicBlock *
6975ARMTargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
6976                                               MachineBasicBlock *BB) const {
6977  const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
6978  DebugLoc dl = MI->getDebugLoc();
6979  bool isThumb2 = Subtarget->isThumb2();
6980  switch (MI->getOpcode()) {
6981  default: {
6982    MI->dump();
6983    llvm_unreachable("Unexpected instr type to insert");
6984  }
6985  // The Thumb2 pre-indexed stores have the same MI operands, they just
6986  // define them differently in the .td files from the isel patterns, so
6987  // they need pseudos.
6988  case ARM::t2STR_preidx:
6989    MI->setDesc(TII->get(ARM::t2STR_PRE));
6990    return BB;
6991  case ARM::t2STRB_preidx:
6992    MI->setDesc(TII->get(ARM::t2STRB_PRE));
6993    return BB;
6994  case ARM::t2STRH_preidx:
6995    MI->setDesc(TII->get(ARM::t2STRH_PRE));
6996    return BB;
6997
6998  case ARM::STRi_preidx:
6999  case ARM::STRBi_preidx: {
7000    unsigned NewOpc = MI->getOpcode() == ARM::STRi_preidx ?
7001      ARM::STR_PRE_IMM : ARM::STRB_PRE_IMM;
7002    // Decode the offset.
7003    unsigned Offset = MI->getOperand(4).getImm();
7004    bool isSub = ARM_AM::getAM2Op(Offset) == ARM_AM::sub;
7005    Offset = ARM_AM::getAM2Offset(Offset);
7006    if (isSub)
7007      Offset = -Offset;
7008
7009    MachineMemOperand *MMO = *MI->memoperands_begin();
7010    BuildMI(*BB, MI, dl, TII->get(NewOpc))
7011      .addOperand(MI->getOperand(0))  // Rn_wb
7012      .addOperand(MI->getOperand(1))  // Rt
7013      .addOperand(MI->getOperand(2))  // Rn
7014      .addImm(Offset)                 // offset (skip GPR==zero_reg)
7015      .addOperand(MI->getOperand(5))  // pred
7016      .addOperand(MI->getOperand(6))
7017      .addMemOperand(MMO);
7018    MI->eraseFromParent();
7019    return BB;
7020  }
7021  case ARM::STRr_preidx:
7022  case ARM::STRBr_preidx:
7023  case ARM::STRH_preidx: {
7024    unsigned NewOpc;
7025    switch (MI->getOpcode()) {
7026    default: llvm_unreachable("unexpected opcode!");
7027    case ARM::STRr_preidx: NewOpc = ARM::STR_PRE_REG; break;
7028    case ARM::STRBr_preidx: NewOpc = ARM::STRB_PRE_REG; break;
7029    case ARM::STRH_preidx: NewOpc = ARM::STRH_PRE; break;
7030    }
7031    MachineInstrBuilder MIB = BuildMI(*BB, MI, dl, TII->get(NewOpc));
7032    for (unsigned i = 0; i < MI->getNumOperands(); ++i)
7033      MIB.addOperand(MI->getOperand(i));
7034    MI->eraseFromParent();
7035    return BB;
7036  }
7037
7038  case ARM::tMOVCCr_pseudo: {
7039    // To "insert" a SELECT_CC instruction, we actually have to insert the
7040    // diamond control-flow pattern.  The incoming instruction knows the
7041    // destination vreg to set, the condition code register to branch on, the
7042    // true/false values to select between, and a branch opcode to use.
7043    const BasicBlock *LLVM_BB = BB->getBasicBlock();
7044    MachineFunction::iterator It = BB;
7045    ++It;
7046
7047    //  thisMBB:
7048    //  ...
7049    //   TrueVal = ...
7050    //   cmpTY ccX, r1, r2
7051    //   bCC copy1MBB
7052    //   fallthrough --> copy0MBB
7053    MachineBasicBlock *thisMBB  = BB;
7054    MachineFunction *F = BB->getParent();
7055    MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB);
7056    MachineBasicBlock *sinkMBB  = F->CreateMachineBasicBlock(LLVM_BB);
7057    F->insert(It, copy0MBB);
7058    F->insert(It, sinkMBB);
7059
7060    // Transfer the remainder of BB and its successor edges to sinkMBB.
7061    sinkMBB->splice(sinkMBB->begin(), BB,
7062                    std::next(MachineBasicBlock::iterator(MI)), BB->end());
7063    sinkMBB->transferSuccessorsAndUpdatePHIs(BB);
7064
7065    BB->addSuccessor(copy0MBB);
7066    BB->addSuccessor(sinkMBB);
7067
7068    BuildMI(BB, dl, TII->get(ARM::tBcc)).addMBB(sinkMBB)
7069      .addImm(MI->getOperand(3).getImm()).addReg(MI->getOperand(4).getReg());
7070
7071    //  copy0MBB:
7072    //   %FalseValue = ...
7073    //   # fallthrough to sinkMBB
7074    BB = copy0MBB;
7075
7076    // Update machine-CFG edges
7077    BB->addSuccessor(sinkMBB);
7078
7079    //  sinkMBB:
7080    //   %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ]
7081    //  ...
7082    BB = sinkMBB;
7083    BuildMI(*BB, BB->begin(), dl,
7084            TII->get(ARM::PHI), MI->getOperand(0).getReg())
7085      .addReg(MI->getOperand(1).getReg()).addMBB(copy0MBB)
7086      .addReg(MI->getOperand(2).getReg()).addMBB(thisMBB);
7087
7088    MI->eraseFromParent();   // The pseudo instruction is gone now.
7089    return BB;
7090  }
7091
7092  case ARM::BCCi64:
7093  case ARM::BCCZi64: {
7094    // If there is an unconditional branch to the other successor, remove it.
7095    BB->erase(std::next(MachineBasicBlock::iterator(MI)), BB->end());
7096
7097    // Compare both parts that make up the double comparison separately for
7098    // equality.
7099    bool RHSisZero = MI->getOpcode() == ARM::BCCZi64;
7100
7101    unsigned LHS1 = MI->getOperand(1).getReg();
7102    unsigned LHS2 = MI->getOperand(2).getReg();
7103    if (RHSisZero) {
7104      AddDefaultPred(BuildMI(BB, dl,
7105                             TII->get(isThumb2 ? ARM::t2CMPri : ARM::CMPri))
7106                     .addReg(LHS1).addImm(0));
7107      BuildMI(BB, dl, TII->get(isThumb2 ? ARM::t2CMPri : ARM::CMPri))
7108        .addReg(LHS2).addImm(0)
7109        .addImm(ARMCC::EQ).addReg(ARM::CPSR);
7110    } else {
7111      unsigned RHS1 = MI->getOperand(3).getReg();
7112      unsigned RHS2 = MI->getOperand(4).getReg();
7113      AddDefaultPred(BuildMI(BB, dl,
7114                             TII->get(isThumb2 ? ARM::t2CMPrr : ARM::CMPrr))
7115                     .addReg(LHS1).addReg(RHS1));
7116      BuildMI(BB, dl, TII->get(isThumb2 ? ARM::t2CMPrr : ARM::CMPrr))
7117        .addReg(LHS2).addReg(RHS2)
7118        .addImm(ARMCC::EQ).addReg(ARM::CPSR);
7119    }
7120
7121    MachineBasicBlock *destMBB = MI->getOperand(RHSisZero ? 3 : 5).getMBB();
7122    MachineBasicBlock *exitMBB = OtherSucc(BB, destMBB);
7123    if (MI->getOperand(0).getImm() == ARMCC::NE)
7124      std::swap(destMBB, exitMBB);
7125
7126    BuildMI(BB, dl, TII->get(isThumb2 ? ARM::t2Bcc : ARM::Bcc))
7127      .addMBB(destMBB).addImm(ARMCC::EQ).addReg(ARM::CPSR);
7128    if (isThumb2)
7129      AddDefaultPred(BuildMI(BB, dl, TII->get(ARM::t2B)).addMBB(exitMBB));
7130    else
7131      BuildMI(BB, dl, TII->get(ARM::B)) .addMBB(exitMBB);
7132
7133    MI->eraseFromParent();   // The pseudo instruction is gone now.
7134    return BB;
7135  }
7136
7137  case ARM::Int_eh_sjlj_setjmp:
7138  case ARM::Int_eh_sjlj_setjmp_nofp:
7139  case ARM::tInt_eh_sjlj_setjmp:
7140  case ARM::t2Int_eh_sjlj_setjmp:
7141  case ARM::t2Int_eh_sjlj_setjmp_nofp:
7142    EmitSjLjDispatchBlock(MI, BB);
7143    return BB;
7144
7145  case ARM::ABS:
7146  case ARM::t2ABS: {
7147    // To insert an ABS instruction, we have to insert the
7148    // diamond control-flow pattern.  The incoming instruction knows the
7149    // source vreg to test against 0, the destination vreg to set,
7150    // the condition code register to branch on, the
7151    // true/false values to select between, and a branch opcode to use.
7152    // It transforms
7153    //     V1 = ABS V0
7154    // into
7155    //     V2 = MOVS V0
7156    //     BCC                      (branch to SinkBB if V0 >= 0)
7157    //     RSBBB: V3 = RSBri V2, 0  (compute ABS if V2 < 0)
7158    //     SinkBB: V1 = PHI(V2, V3)
7159    const BasicBlock *LLVM_BB = BB->getBasicBlock();
7160    MachineFunction::iterator BBI = BB;
7161    ++BBI;
7162    MachineFunction *Fn = BB->getParent();
7163    MachineBasicBlock *RSBBB = Fn->CreateMachineBasicBlock(LLVM_BB);
7164    MachineBasicBlock *SinkBB  = Fn->CreateMachineBasicBlock(LLVM_BB);
7165    Fn->insert(BBI, RSBBB);
7166    Fn->insert(BBI, SinkBB);
7167
7168    unsigned int ABSSrcReg = MI->getOperand(1).getReg();
7169    unsigned int ABSDstReg = MI->getOperand(0).getReg();
7170    bool isThumb2 = Subtarget->isThumb2();
7171    MachineRegisterInfo &MRI = Fn->getRegInfo();
7172    // In Thumb mode S must not be specified if source register is the SP or
7173    // PC and if destination register is the SP, so restrict register class
7174    unsigned NewRsbDstReg = MRI.createVirtualRegister(isThumb2 ?
7175      (const TargetRegisterClass*)&ARM::rGPRRegClass :
7176      (const TargetRegisterClass*)&ARM::GPRRegClass);
7177
7178    // Transfer the remainder of BB and its successor edges to sinkMBB.
7179    SinkBB->splice(SinkBB->begin(), BB,
7180                   std::next(MachineBasicBlock::iterator(MI)), BB->end());
7181    SinkBB->transferSuccessorsAndUpdatePHIs(BB);
7182
7183    BB->addSuccessor(RSBBB);
7184    BB->addSuccessor(SinkBB);
7185
7186    // fall through to SinkMBB
7187    RSBBB->addSuccessor(SinkBB);
7188
7189    // insert a cmp at the end of BB
7190    AddDefaultPred(BuildMI(BB, dl,
7191                           TII->get(isThumb2 ? ARM::t2CMPri : ARM::CMPri))
7192                   .addReg(ABSSrcReg).addImm(0));
7193
7194    // insert a bcc with opposite CC to ARMCC::MI at the end of BB
7195    BuildMI(BB, dl,
7196      TII->get(isThumb2 ? ARM::t2Bcc : ARM::Bcc)).addMBB(SinkBB)
7197      .addImm(ARMCC::getOppositeCondition(ARMCC::MI)).addReg(ARM::CPSR);
7198
7199    // insert rsbri in RSBBB
7200    // Note: BCC and rsbri will be converted into predicated rsbmi
7201    // by if-conversion pass
7202    BuildMI(*RSBBB, RSBBB->begin(), dl,
7203      TII->get(isThumb2 ? ARM::t2RSBri : ARM::RSBri), NewRsbDstReg)
7204      .addReg(ABSSrcReg, RegState::Kill)
7205      .addImm(0).addImm((unsigned)ARMCC::AL).addReg(0).addReg(0);
7206
7207    // insert PHI in SinkBB,
7208    // reuse ABSDstReg to not change uses of ABS instruction
7209    BuildMI(*SinkBB, SinkBB->begin(), dl,
7210      TII->get(ARM::PHI), ABSDstReg)
7211      .addReg(NewRsbDstReg).addMBB(RSBBB)
7212      .addReg(ABSSrcReg).addMBB(BB);
7213
7214    // remove ABS instruction
7215    MI->eraseFromParent();
7216
7217    // return last added BB
7218    return SinkBB;
7219  }
7220  case ARM::COPY_STRUCT_BYVAL_I32:
7221    ++NumLoopByVals;
7222    return EmitStructByval(MI, BB);
7223  }
7224}
7225
7226void ARMTargetLowering::AdjustInstrPostInstrSelection(MachineInstr *MI,
7227                                                      SDNode *Node) const {
7228  if (!MI->hasPostISelHook()) {
7229    assert(!convertAddSubFlagsOpcode(MI->getOpcode()) &&
7230           "Pseudo flag-setting opcodes must be marked with 'hasPostISelHook'");
7231    return;
7232  }
7233
7234  const MCInstrDesc *MCID = &MI->getDesc();
7235  // Adjust potentially 's' setting instructions after isel, i.e. ADC, SBC, RSB,
7236  // RSC. Coming out of isel, they have an implicit CPSR def, but the optional
7237  // operand is still set to noreg. If needed, set the optional operand's
7238  // register to CPSR, and remove the redundant implicit def.
7239  //
7240  // e.g. ADCS (..., CPSR<imp-def>) -> ADC (... opt:CPSR<def>).
7241
7242  // Rename pseudo opcodes.
7243  unsigned NewOpc = convertAddSubFlagsOpcode(MI->getOpcode());
7244  if (NewOpc) {
7245    const ARMBaseInstrInfo *TII =
7246      static_cast<const ARMBaseInstrInfo*>(getTargetMachine().getInstrInfo());
7247    MCID = &TII->get(NewOpc);
7248
7249    assert(MCID->getNumOperands() == MI->getDesc().getNumOperands() + 1 &&
7250           "converted opcode should be the same except for cc_out");
7251
7252    MI->setDesc(*MCID);
7253
7254    // Add the optional cc_out operand
7255    MI->addOperand(MachineOperand::CreateReg(0, /*isDef=*/true));
7256  }
7257  unsigned ccOutIdx = MCID->getNumOperands() - 1;
7258
7259  // Any ARM instruction that sets the 's' bit should specify an optional
7260  // "cc_out" operand in the last operand position.
7261  if (!MI->hasOptionalDef() || !MCID->OpInfo[ccOutIdx].isOptionalDef()) {
7262    assert(!NewOpc && "Optional cc_out operand required");
7263    return;
7264  }
7265  // Look for an implicit def of CPSR added by MachineInstr ctor. Remove it
7266  // since we already have an optional CPSR def.
7267  bool definesCPSR = false;
7268  bool deadCPSR = false;
7269  for (unsigned i = MCID->getNumOperands(), e = MI->getNumOperands();
7270       i != e; ++i) {
7271    const MachineOperand &MO = MI->getOperand(i);
7272    if (MO.isReg() && MO.isDef() && MO.getReg() == ARM::CPSR) {
7273      definesCPSR = true;
7274      if (MO.isDead())
7275        deadCPSR = true;
7276      MI->RemoveOperand(i);
7277      break;
7278    }
7279  }
7280  if (!definesCPSR) {
7281    assert(!NewOpc && "Optional cc_out operand required");
7282    return;
7283  }
7284  assert(deadCPSR == !Node->hasAnyUseOfValue(1) && "inconsistent dead flag");
7285  if (deadCPSR) {
7286    assert(!MI->getOperand(ccOutIdx).getReg() &&
7287           "expect uninitialized optional cc_out operand");
7288    return;
7289  }
7290
7291  // If this instruction was defined with an optional CPSR def and its dag node
7292  // had a live implicit CPSR def, then activate the optional CPSR def.
7293  MachineOperand &MO = MI->getOperand(ccOutIdx);
7294  MO.setReg(ARM::CPSR);
7295  MO.setIsDef(true);
7296}
7297
7298//===----------------------------------------------------------------------===//
7299//                           ARM Optimization Hooks
7300//===----------------------------------------------------------------------===//
7301
7302// Helper function that checks if N is a null or all ones constant.
7303static inline bool isZeroOrAllOnes(SDValue N, bool AllOnes) {
7304  ConstantSDNode *C = dyn_cast<ConstantSDNode>(N);
7305  if (!C)
7306    return false;
7307  return AllOnes ? C->isAllOnesValue() : C->isNullValue();
7308}
7309
7310// Return true if N is conditionally 0 or all ones.
7311// Detects these expressions where cc is an i1 value:
7312//
7313//   (select cc 0, y)   [AllOnes=0]
7314//   (select cc y, 0)   [AllOnes=0]
7315//   (zext cc)          [AllOnes=0]
7316//   (sext cc)          [AllOnes=0/1]
7317//   (select cc -1, y)  [AllOnes=1]
7318//   (select cc y, -1)  [AllOnes=1]
7319//
7320// Invert is set when N is the null/all ones constant when CC is false.
7321// OtherOp is set to the alternative value of N.
7322static bool isConditionalZeroOrAllOnes(SDNode *N, bool AllOnes,
7323                                       SDValue &CC, bool &Invert,
7324                                       SDValue &OtherOp,
7325                                       SelectionDAG &DAG) {
7326  switch (N->getOpcode()) {
7327  default: return false;
7328  case ISD::SELECT: {
7329    CC = N->getOperand(0);
7330    SDValue N1 = N->getOperand(1);
7331    SDValue N2 = N->getOperand(2);
7332    if (isZeroOrAllOnes(N1, AllOnes)) {
7333      Invert = false;
7334      OtherOp = N2;
7335      return true;
7336    }
7337    if (isZeroOrAllOnes(N2, AllOnes)) {
7338      Invert = true;
7339      OtherOp = N1;
7340      return true;
7341    }
7342    return false;
7343  }
7344  case ISD::ZERO_EXTEND:
7345    // (zext cc) can never be the all ones value.
7346    if (AllOnes)
7347      return false;
7348    // Fall through.
7349  case ISD::SIGN_EXTEND: {
7350    EVT VT = N->getValueType(0);
7351    CC = N->getOperand(0);
7352    if (CC.getValueType() != MVT::i1)
7353      return false;
7354    Invert = !AllOnes;
7355    if (AllOnes)
7356      // When looking for an AllOnes constant, N is an sext, and the 'other'
7357      // value is 0.
7358      OtherOp = DAG.getConstant(0, VT);
7359    else if (N->getOpcode() == ISD::ZERO_EXTEND)
7360      // When looking for a 0 constant, N can be zext or sext.
7361      OtherOp = DAG.getConstant(1, VT);
7362    else
7363      OtherOp = DAG.getConstant(APInt::getAllOnesValue(VT.getSizeInBits()), VT);
7364    return true;
7365  }
7366  }
7367}
7368
7369// Combine a constant select operand into its use:
7370//
7371//   (add (select cc, 0, c), x)  -> (select cc, x, (add, x, c))
7372//   (sub x, (select cc, 0, c))  -> (select cc, x, (sub, x, c))
7373//   (and (select cc, -1, c), x) -> (select cc, x, (and, x, c))  [AllOnes=1]
7374//   (or  (select cc, 0, c), x)  -> (select cc, x, (or, x, c))
7375//   (xor (select cc, 0, c), x)  -> (select cc, x, (xor, x, c))
7376//
7377// The transform is rejected if the select doesn't have a constant operand that
7378// is null, or all ones when AllOnes is set.
7379//
7380// Also recognize sext/zext from i1:
7381//
7382//   (add (zext cc), x) -> (select cc (add x, 1), x)
7383//   (add (sext cc), x) -> (select cc (add x, -1), x)
7384//
7385// These transformations eventually create predicated instructions.
7386//
7387// @param N       The node to transform.
7388// @param Slct    The N operand that is a select.
7389// @param OtherOp The other N operand (x above).
7390// @param DCI     Context.
7391// @param AllOnes Require the select constant to be all ones instead of null.
7392// @returns The new node, or SDValue() on failure.
7393static
7394SDValue combineSelectAndUse(SDNode *N, SDValue Slct, SDValue OtherOp,
7395                            TargetLowering::DAGCombinerInfo &DCI,
7396                            bool AllOnes = false) {
7397  SelectionDAG &DAG = DCI.DAG;
7398  EVT VT = N->getValueType(0);
7399  SDValue NonConstantVal;
7400  SDValue CCOp;
7401  bool SwapSelectOps;
7402  if (!isConditionalZeroOrAllOnes(Slct.getNode(), AllOnes, CCOp, SwapSelectOps,
7403                                  NonConstantVal, DAG))
7404    return SDValue();
7405
7406  // Slct is now know to be the desired identity constant when CC is true.
7407  SDValue TrueVal = OtherOp;
7408  SDValue FalseVal = DAG.getNode(N->getOpcode(), SDLoc(N), VT,
7409                                 OtherOp, NonConstantVal);
7410  // Unless SwapSelectOps says CC should be false.
7411  if (SwapSelectOps)
7412    std::swap(TrueVal, FalseVal);
7413
7414  return DAG.getNode(ISD::SELECT, SDLoc(N), VT,
7415                     CCOp, TrueVal, FalseVal);
7416}
7417
7418// Attempt combineSelectAndUse on each operand of a commutative operator N.
7419static
7420SDValue combineSelectAndUseCommutative(SDNode *N, bool AllOnes,
7421                                       TargetLowering::DAGCombinerInfo &DCI) {
7422  SDValue N0 = N->getOperand(0);
7423  SDValue N1 = N->getOperand(1);
7424  if (N0.getNode()->hasOneUse()) {
7425    SDValue Result = combineSelectAndUse(N, N0, N1, DCI, AllOnes);
7426    if (Result.getNode())
7427      return Result;
7428  }
7429  if (N1.getNode()->hasOneUse()) {
7430    SDValue Result = combineSelectAndUse(N, N1, N0, DCI, AllOnes);
7431    if (Result.getNode())
7432      return Result;
7433  }
7434  return SDValue();
7435}
7436
7437// AddCombineToVPADDL- For pair-wise add on neon, use the vpaddl instruction
7438// (only after legalization).
7439static SDValue AddCombineToVPADDL(SDNode *N, SDValue N0, SDValue N1,
7440                                 TargetLowering::DAGCombinerInfo &DCI,
7441                                 const ARMSubtarget *Subtarget) {
7442
7443  // Only perform optimization if after legalize, and if NEON is available. We
7444  // also expected both operands to be BUILD_VECTORs.
7445  if (DCI.isBeforeLegalize() || !Subtarget->hasNEON()
7446      || N0.getOpcode() != ISD::BUILD_VECTOR
7447      || N1.getOpcode() != ISD::BUILD_VECTOR)
7448    return SDValue();
7449
7450  // Check output type since VPADDL operand elements can only be 8, 16, or 32.
7451  EVT VT = N->getValueType(0);
7452  if (!VT.isInteger() || VT.getVectorElementType() == MVT::i64)
7453    return SDValue();
7454
7455  // Check that the vector operands are of the right form.
7456  // N0 and N1 are BUILD_VECTOR nodes with N number of EXTRACT_VECTOR
7457  // operands, where N is the size of the formed vector.
7458  // Each EXTRACT_VECTOR should have the same input vector and odd or even
7459  // index such that we have a pair wise add pattern.
7460
7461  // Grab the vector that all EXTRACT_VECTOR nodes should be referencing.
7462  if (N0->getOperand(0)->getOpcode() != ISD::EXTRACT_VECTOR_ELT)
7463    return SDValue();
7464  SDValue Vec = N0->getOperand(0)->getOperand(0);
7465  SDNode *V = Vec.getNode();
7466  unsigned nextIndex = 0;
7467
7468  // For each operands to the ADD which are BUILD_VECTORs,
7469  // check to see if each of their operands are an EXTRACT_VECTOR with
7470  // the same vector and appropriate index.
7471  for (unsigned i = 0, e = N0->getNumOperands(); i != e; ++i) {
7472    if (N0->getOperand(i)->getOpcode() == ISD::EXTRACT_VECTOR_ELT
7473        && N1->getOperand(i)->getOpcode() == ISD::EXTRACT_VECTOR_ELT) {
7474
7475      SDValue ExtVec0 = N0->getOperand(i);
7476      SDValue ExtVec1 = N1->getOperand(i);
7477
7478      // First operand is the vector, verify its the same.
7479      if (V != ExtVec0->getOperand(0).getNode() ||
7480          V != ExtVec1->getOperand(0).getNode())
7481        return SDValue();
7482
7483      // Second is the constant, verify its correct.
7484      ConstantSDNode *C0 = dyn_cast<ConstantSDNode>(ExtVec0->getOperand(1));
7485      ConstantSDNode *C1 = dyn_cast<ConstantSDNode>(ExtVec1->getOperand(1));
7486
7487      // For the constant, we want to see all the even or all the odd.
7488      if (!C0 || !C1 || C0->getZExtValue() != nextIndex
7489          || C1->getZExtValue() != nextIndex+1)
7490        return SDValue();
7491
7492      // Increment index.
7493      nextIndex+=2;
7494    } else
7495      return SDValue();
7496  }
7497
7498  // Create VPADDL node.
7499  SelectionDAG &DAG = DCI.DAG;
7500  const TargetLowering &TLI = DAG.getTargetLoweringInfo();
7501
7502  // Build operand list.
7503  SmallVector<SDValue, 8> Ops;
7504  Ops.push_back(DAG.getConstant(Intrinsic::arm_neon_vpaddls,
7505                                TLI.getPointerTy()));
7506
7507  // Input is the vector.
7508  Ops.push_back(Vec);
7509
7510  // Get widened type and narrowed type.
7511  MVT widenType;
7512  unsigned numElem = VT.getVectorNumElements();
7513
7514  EVT inputLaneType = Vec.getValueType().getVectorElementType();
7515  switch (inputLaneType.getSimpleVT().SimpleTy) {
7516    case MVT::i8: widenType = MVT::getVectorVT(MVT::i16, numElem); break;
7517    case MVT::i16: widenType = MVT::getVectorVT(MVT::i32, numElem); break;
7518    case MVT::i32: widenType = MVT::getVectorVT(MVT::i64, numElem); break;
7519    default:
7520      llvm_unreachable("Invalid vector element type for padd optimization.");
7521  }
7522
7523  SDValue tmp = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, SDLoc(N),
7524                            widenType, &Ops[0], Ops.size());
7525  unsigned ExtOp = VT.bitsGT(tmp.getValueType()) ? ISD::ANY_EXTEND : ISD::TRUNCATE;
7526  return DAG.getNode(ExtOp, SDLoc(N), VT, tmp);
7527}
7528
7529static SDValue findMUL_LOHI(SDValue V) {
7530  if (V->getOpcode() == ISD::UMUL_LOHI ||
7531      V->getOpcode() == ISD::SMUL_LOHI)
7532    return V;
7533  return SDValue();
7534}
7535
7536static SDValue AddCombineTo64bitMLAL(SDNode *AddcNode,
7537                                     TargetLowering::DAGCombinerInfo &DCI,
7538                                     const ARMSubtarget *Subtarget) {
7539
7540  if (Subtarget->isThumb1Only()) return SDValue();
7541
7542  // Only perform the checks after legalize when the pattern is available.
7543  if (DCI.isBeforeLegalize()) return SDValue();
7544
7545  // Look for multiply add opportunities.
7546  // The pattern is a ISD::UMUL_LOHI followed by two add nodes, where
7547  // each add nodes consumes a value from ISD::UMUL_LOHI and there is
7548  // a glue link from the first add to the second add.
7549  // If we find this pattern, we can replace the U/SMUL_LOHI, ADDC, and ADDE by
7550  // a S/UMLAL instruction.
7551  //          loAdd   UMUL_LOHI
7552  //            \    / :lo    \ :hi
7553  //             \  /          \          [no multiline comment]
7554  //              ADDC         |  hiAdd
7555  //                 \ :glue  /  /
7556  //                  \      /  /
7557  //                    ADDE
7558  //
7559  assert(AddcNode->getOpcode() == ISD::ADDC && "Expect an ADDC");
7560  SDValue AddcOp0 = AddcNode->getOperand(0);
7561  SDValue AddcOp1 = AddcNode->getOperand(1);
7562
7563  // Check if the two operands are from the same mul_lohi node.
7564  if (AddcOp0.getNode() == AddcOp1.getNode())
7565    return SDValue();
7566
7567  assert(AddcNode->getNumValues() == 2 &&
7568         AddcNode->getValueType(0) == MVT::i32 &&
7569         "Expect ADDC with two result values. First: i32");
7570
7571  // Check that we have a glued ADDC node.
7572  if (AddcNode->getValueType(1) != MVT::Glue)
7573    return SDValue();
7574
7575  // Check that the ADDC adds the low result of the S/UMUL_LOHI.
7576  if (AddcOp0->getOpcode() != ISD::UMUL_LOHI &&
7577      AddcOp0->getOpcode() != ISD::SMUL_LOHI &&
7578      AddcOp1->getOpcode() != ISD::UMUL_LOHI &&
7579      AddcOp1->getOpcode() != ISD::SMUL_LOHI)
7580    return SDValue();
7581
7582  // Look for the glued ADDE.
7583  SDNode* AddeNode = AddcNode->getGluedUser();
7584  if (AddeNode == NULL)
7585    return SDValue();
7586
7587  // Make sure it is really an ADDE.
7588  if (AddeNode->getOpcode() != ISD::ADDE)
7589    return SDValue();
7590
7591  assert(AddeNode->getNumOperands() == 3 &&
7592         AddeNode->getOperand(2).getValueType() == MVT::Glue &&
7593         "ADDE node has the wrong inputs");
7594
7595  // Check for the triangle shape.
7596  SDValue AddeOp0 = AddeNode->getOperand(0);
7597  SDValue AddeOp1 = AddeNode->getOperand(1);
7598
7599  // Make sure that the ADDE operands are not coming from the same node.
7600  if (AddeOp0.getNode() == AddeOp1.getNode())
7601    return SDValue();
7602
7603  // Find the MUL_LOHI node walking up ADDE's operands.
7604  bool IsLeftOperandMUL = false;
7605  SDValue MULOp = findMUL_LOHI(AddeOp0);
7606  if (MULOp == SDValue())
7607   MULOp = findMUL_LOHI(AddeOp1);
7608  else
7609    IsLeftOperandMUL = true;
7610  if (MULOp == SDValue())
7611     return SDValue();
7612
7613  // Figure out the right opcode.
7614  unsigned Opc = MULOp->getOpcode();
7615  unsigned FinalOpc = (Opc == ISD::SMUL_LOHI) ? ARMISD::SMLAL : ARMISD::UMLAL;
7616
7617  // Figure out the high and low input values to the MLAL node.
7618  SDValue* HiMul = &MULOp;
7619  SDValue* HiAdd = NULL;
7620  SDValue* LoMul = NULL;
7621  SDValue* LowAdd = NULL;
7622
7623  if (IsLeftOperandMUL)
7624    HiAdd = &AddeOp1;
7625  else
7626    HiAdd = &AddeOp0;
7627
7628
7629  if (AddcOp0->getOpcode() == Opc) {
7630    LoMul = &AddcOp0;
7631    LowAdd = &AddcOp1;
7632  }
7633  if (AddcOp1->getOpcode() == Opc) {
7634    LoMul = &AddcOp1;
7635    LowAdd = &AddcOp0;
7636  }
7637
7638  if (LoMul == NULL)
7639    return SDValue();
7640
7641  if (LoMul->getNode() != HiMul->getNode())
7642    return SDValue();
7643
7644  // Create the merged node.
7645  SelectionDAG &DAG = DCI.DAG;
7646
7647  // Build operand list.
7648  SmallVector<SDValue, 8> Ops;
7649  Ops.push_back(LoMul->getOperand(0));
7650  Ops.push_back(LoMul->getOperand(1));
7651  Ops.push_back(*LowAdd);
7652  Ops.push_back(*HiAdd);
7653
7654  SDValue MLALNode =  DAG.getNode(FinalOpc, SDLoc(AddcNode),
7655                                 DAG.getVTList(MVT::i32, MVT::i32),
7656                                 &Ops[0], Ops.size());
7657
7658  // Replace the ADDs' nodes uses by the MLA node's values.
7659  SDValue HiMLALResult(MLALNode.getNode(), 1);
7660  DAG.ReplaceAllUsesOfValueWith(SDValue(AddeNode, 0), HiMLALResult);
7661
7662  SDValue LoMLALResult(MLALNode.getNode(), 0);
7663  DAG.ReplaceAllUsesOfValueWith(SDValue(AddcNode, 0), LoMLALResult);
7664
7665  // Return original node to notify the driver to stop replacing.
7666  SDValue resNode(AddcNode, 0);
7667  return resNode;
7668}
7669
7670/// PerformADDCCombine - Target-specific dag combine transform from
7671/// ISD::ADDC, ISD::ADDE, and ISD::MUL_LOHI to MLAL.
7672static SDValue PerformADDCCombine(SDNode *N,
7673                                 TargetLowering::DAGCombinerInfo &DCI,
7674                                 const ARMSubtarget *Subtarget) {
7675
7676  return AddCombineTo64bitMLAL(N, DCI, Subtarget);
7677
7678}
7679
7680/// PerformADDCombineWithOperands - Try DAG combinations for an ADD with
7681/// operands N0 and N1.  This is a helper for PerformADDCombine that is
7682/// called with the default operands, and if that fails, with commuted
7683/// operands.
7684static SDValue PerformADDCombineWithOperands(SDNode *N, SDValue N0, SDValue N1,
7685                                          TargetLowering::DAGCombinerInfo &DCI,
7686                                          const ARMSubtarget *Subtarget){
7687
7688  // Attempt to create vpaddl for this add.
7689  SDValue Result = AddCombineToVPADDL(N, N0, N1, DCI, Subtarget);
7690  if (Result.getNode())
7691    return Result;
7692
7693  // fold (add (select cc, 0, c), x) -> (select cc, x, (add, x, c))
7694  if (N0.getNode()->hasOneUse()) {
7695    SDValue Result = combineSelectAndUse(N, N0, N1, DCI);
7696    if (Result.getNode()) return Result;
7697  }
7698  return SDValue();
7699}
7700
7701/// PerformADDCombine - Target-specific dag combine xforms for ISD::ADD.
7702///
7703static SDValue PerformADDCombine(SDNode *N,
7704                                 TargetLowering::DAGCombinerInfo &DCI,
7705                                 const ARMSubtarget *Subtarget) {
7706  SDValue N0 = N->getOperand(0);
7707  SDValue N1 = N->getOperand(1);
7708
7709  // First try with the default operand order.
7710  SDValue Result = PerformADDCombineWithOperands(N, N0, N1, DCI, Subtarget);
7711  if (Result.getNode())
7712    return Result;
7713
7714  // If that didn't work, try again with the operands commuted.
7715  return PerformADDCombineWithOperands(N, N1, N0, DCI, Subtarget);
7716}
7717
7718/// PerformSUBCombine - Target-specific dag combine xforms for ISD::SUB.
7719///
7720static SDValue PerformSUBCombine(SDNode *N,
7721                                 TargetLowering::DAGCombinerInfo &DCI) {
7722  SDValue N0 = N->getOperand(0);
7723  SDValue N1 = N->getOperand(1);
7724
7725  // fold (sub x, (select cc, 0, c)) -> (select cc, x, (sub, x, c))
7726  if (N1.getNode()->hasOneUse()) {
7727    SDValue Result = combineSelectAndUse(N, N1, N0, DCI);
7728    if (Result.getNode()) return Result;
7729  }
7730
7731  return SDValue();
7732}
7733
7734/// PerformVMULCombine
7735/// Distribute (A + B) * C to (A * C) + (B * C) to take advantage of the
7736/// special multiplier accumulator forwarding.
7737///   vmul d3, d0, d2
7738///   vmla d3, d1, d2
7739/// is faster than
7740///   vadd d3, d0, d1
7741///   vmul d3, d3, d2
7742//  However, for (A + B) * (A + B),
7743//    vadd d2, d0, d1
7744//    vmul d3, d0, d2
7745//    vmla d3, d1, d2
7746//  is slower than
7747//    vadd d2, d0, d1
7748//    vmul d3, d2, d2
7749static SDValue PerformVMULCombine(SDNode *N,
7750                                  TargetLowering::DAGCombinerInfo &DCI,
7751                                  const ARMSubtarget *Subtarget) {
7752  if (!Subtarget->hasVMLxForwarding())
7753    return SDValue();
7754
7755  SelectionDAG &DAG = DCI.DAG;
7756  SDValue N0 = N->getOperand(0);
7757  SDValue N1 = N->getOperand(1);
7758  unsigned Opcode = N0.getOpcode();
7759  if (Opcode != ISD::ADD && Opcode != ISD::SUB &&
7760      Opcode != ISD::FADD && Opcode != ISD::FSUB) {
7761    Opcode = N1.getOpcode();
7762    if (Opcode != ISD::ADD && Opcode != ISD::SUB &&
7763        Opcode != ISD::FADD && Opcode != ISD::FSUB)
7764      return SDValue();
7765    std::swap(N0, N1);
7766  }
7767
7768  if (N0 == N1)
7769    return SDValue();
7770
7771  EVT VT = N->getValueType(0);
7772  SDLoc DL(N);
7773  SDValue N00 = N0->getOperand(0);
7774  SDValue N01 = N0->getOperand(1);
7775  return DAG.getNode(Opcode, DL, VT,
7776                     DAG.getNode(ISD::MUL, DL, VT, N00, N1),
7777                     DAG.getNode(ISD::MUL, DL, VT, N01, N1));
7778}
7779
7780static SDValue PerformMULCombine(SDNode *N,
7781                                 TargetLowering::DAGCombinerInfo &DCI,
7782                                 const ARMSubtarget *Subtarget) {
7783  SelectionDAG &DAG = DCI.DAG;
7784
7785  if (Subtarget->isThumb1Only())
7786    return SDValue();
7787
7788  if (DCI.isBeforeLegalize() || DCI.isCalledByLegalizer())
7789    return SDValue();
7790
7791  EVT VT = N->getValueType(0);
7792  if (VT.is64BitVector() || VT.is128BitVector())
7793    return PerformVMULCombine(N, DCI, Subtarget);
7794  if (VT != MVT::i32)
7795    return SDValue();
7796
7797  ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(1));
7798  if (!C)
7799    return SDValue();
7800
7801  int64_t MulAmt = C->getSExtValue();
7802  unsigned ShiftAmt = countTrailingZeros<uint64_t>(MulAmt);
7803
7804  ShiftAmt = ShiftAmt & (32 - 1);
7805  SDValue V = N->getOperand(0);
7806  SDLoc DL(N);
7807
7808  SDValue Res;
7809  MulAmt >>= ShiftAmt;
7810
7811  if (MulAmt >= 0) {
7812    if (isPowerOf2_32(MulAmt - 1)) {
7813      // (mul x, 2^N + 1) => (add (shl x, N), x)
7814      Res = DAG.getNode(ISD::ADD, DL, VT,
7815                        V,
7816                        DAG.getNode(ISD::SHL, DL, VT,
7817                                    V,
7818                                    DAG.getConstant(Log2_32(MulAmt - 1),
7819                                                    MVT::i32)));
7820    } else if (isPowerOf2_32(MulAmt + 1)) {
7821      // (mul x, 2^N - 1) => (sub (shl x, N), x)
7822      Res = DAG.getNode(ISD::SUB, DL, VT,
7823                        DAG.getNode(ISD::SHL, DL, VT,
7824                                    V,
7825                                    DAG.getConstant(Log2_32(MulAmt + 1),
7826                                                    MVT::i32)),
7827                        V);
7828    } else
7829      return SDValue();
7830  } else {
7831    uint64_t MulAmtAbs = -MulAmt;
7832    if (isPowerOf2_32(MulAmtAbs + 1)) {
7833      // (mul x, -(2^N - 1)) => (sub x, (shl x, N))
7834      Res = DAG.getNode(ISD::SUB, DL, VT,
7835                        V,
7836                        DAG.getNode(ISD::SHL, DL, VT,
7837                                    V,
7838                                    DAG.getConstant(Log2_32(MulAmtAbs + 1),
7839                                                    MVT::i32)));
7840    } else if (isPowerOf2_32(MulAmtAbs - 1)) {
7841      // (mul x, -(2^N + 1)) => - (add (shl x, N), x)
7842      Res = DAG.getNode(ISD::ADD, DL, VT,
7843                        V,
7844                        DAG.getNode(ISD::SHL, DL, VT,
7845                                    V,
7846                                    DAG.getConstant(Log2_32(MulAmtAbs-1),
7847                                                    MVT::i32)));
7848      Res = DAG.getNode(ISD::SUB, DL, VT,
7849                        DAG.getConstant(0, MVT::i32),Res);
7850
7851    } else
7852      return SDValue();
7853  }
7854
7855  if (ShiftAmt != 0)
7856    Res = DAG.getNode(ISD::SHL, DL, VT,
7857                      Res, DAG.getConstant(ShiftAmt, MVT::i32));
7858
7859  // Do not add new nodes to DAG combiner worklist.
7860  DCI.CombineTo(N, Res, false);
7861  return SDValue();
7862}
7863
7864static SDValue PerformANDCombine(SDNode *N,
7865                                 TargetLowering::DAGCombinerInfo &DCI,
7866                                 const ARMSubtarget *Subtarget) {
7867
7868  // Attempt to use immediate-form VBIC
7869  BuildVectorSDNode *BVN = dyn_cast<BuildVectorSDNode>(N->getOperand(1));
7870  SDLoc dl(N);
7871  EVT VT = N->getValueType(0);
7872  SelectionDAG &DAG = DCI.DAG;
7873
7874  if(!DAG.getTargetLoweringInfo().isTypeLegal(VT))
7875    return SDValue();
7876
7877  APInt SplatBits, SplatUndef;
7878  unsigned SplatBitSize;
7879  bool HasAnyUndefs;
7880  if (BVN &&
7881      BVN->isConstantSplat(SplatBits, SplatUndef, SplatBitSize, HasAnyUndefs)) {
7882    if (SplatBitSize <= 64) {
7883      EVT VbicVT;
7884      SDValue Val = isNEONModifiedImm((~SplatBits).getZExtValue(),
7885                                      SplatUndef.getZExtValue(), SplatBitSize,
7886                                      DAG, VbicVT, VT.is128BitVector(),
7887                                      OtherModImm);
7888      if (Val.getNode()) {
7889        SDValue Input =
7890          DAG.getNode(ISD::BITCAST, dl, VbicVT, N->getOperand(0));
7891        SDValue Vbic = DAG.getNode(ARMISD::VBICIMM, dl, VbicVT, Input, Val);
7892        return DAG.getNode(ISD::BITCAST, dl, VT, Vbic);
7893      }
7894    }
7895  }
7896
7897  if (!Subtarget->isThumb1Only()) {
7898    // fold (and (select cc, -1, c), x) -> (select cc, x, (and, x, c))
7899    SDValue Result = combineSelectAndUseCommutative(N, true, DCI);
7900    if (Result.getNode())
7901      return Result;
7902  }
7903
7904  return SDValue();
7905}
7906
7907/// PerformORCombine - Target-specific dag combine xforms for ISD::OR
7908static SDValue PerformORCombine(SDNode *N,
7909                                TargetLowering::DAGCombinerInfo &DCI,
7910                                const ARMSubtarget *Subtarget) {
7911  // Attempt to use immediate-form VORR
7912  BuildVectorSDNode *BVN = dyn_cast<BuildVectorSDNode>(N->getOperand(1));
7913  SDLoc dl(N);
7914  EVT VT = N->getValueType(0);
7915  SelectionDAG &DAG = DCI.DAG;
7916
7917  if(!DAG.getTargetLoweringInfo().isTypeLegal(VT))
7918    return SDValue();
7919
7920  APInt SplatBits, SplatUndef;
7921  unsigned SplatBitSize;
7922  bool HasAnyUndefs;
7923  if (BVN && Subtarget->hasNEON() &&
7924      BVN->isConstantSplat(SplatBits, SplatUndef, SplatBitSize, HasAnyUndefs)) {
7925    if (SplatBitSize <= 64) {
7926      EVT VorrVT;
7927      SDValue Val = isNEONModifiedImm(SplatBits.getZExtValue(),
7928                                      SplatUndef.getZExtValue(), SplatBitSize,
7929                                      DAG, VorrVT, VT.is128BitVector(),
7930                                      OtherModImm);
7931      if (Val.getNode()) {
7932        SDValue Input =
7933          DAG.getNode(ISD::BITCAST, dl, VorrVT, N->getOperand(0));
7934        SDValue Vorr = DAG.getNode(ARMISD::VORRIMM, dl, VorrVT, Input, Val);
7935        return DAG.getNode(ISD::BITCAST, dl, VT, Vorr);
7936      }
7937    }
7938  }
7939
7940  if (!Subtarget->isThumb1Only()) {
7941    // fold (or (select cc, 0, c), x) -> (select cc, x, (or, x, c))
7942    SDValue Result = combineSelectAndUseCommutative(N, false, DCI);
7943    if (Result.getNode())
7944      return Result;
7945  }
7946
7947  // The code below optimizes (or (and X, Y), Z).
7948  // The AND operand needs to have a single user to make these optimizations
7949  // profitable.
7950  SDValue N0 = N->getOperand(0);
7951  if (N0.getOpcode() != ISD::AND || !N0.hasOneUse())
7952    return SDValue();
7953  SDValue N1 = N->getOperand(1);
7954
7955  // (or (and B, A), (and C, ~A)) => (VBSL A, B, C) when A is a constant.
7956  if (Subtarget->hasNEON() && N1.getOpcode() == ISD::AND && VT.isVector() &&
7957      DAG.getTargetLoweringInfo().isTypeLegal(VT)) {
7958    APInt SplatUndef;
7959    unsigned SplatBitSize;
7960    bool HasAnyUndefs;
7961
7962    APInt SplatBits0, SplatBits1;
7963    BuildVectorSDNode *BVN0 = dyn_cast<BuildVectorSDNode>(N0->getOperand(1));
7964    BuildVectorSDNode *BVN1 = dyn_cast<BuildVectorSDNode>(N1->getOperand(1));
7965    // Ensure that the second operand of both ands are constants
7966    if (BVN0 && BVN0->isConstantSplat(SplatBits0, SplatUndef, SplatBitSize,
7967                                      HasAnyUndefs) && !HasAnyUndefs) {
7968        if (BVN1 && BVN1->isConstantSplat(SplatBits1, SplatUndef, SplatBitSize,
7969                                          HasAnyUndefs) && !HasAnyUndefs) {
7970            // Ensure that the bit width of the constants are the same and that
7971            // the splat arguments are logical inverses as per the pattern we
7972            // are trying to simplify.
7973            if (SplatBits0.getBitWidth() == SplatBits1.getBitWidth() &&
7974                SplatBits0 == ~SplatBits1) {
7975                // Canonicalize the vector type to make instruction selection
7976                // simpler.
7977                EVT CanonicalVT = VT.is128BitVector() ? MVT::v4i32 : MVT::v2i32;
7978                SDValue Result = DAG.getNode(ARMISD::VBSL, dl, CanonicalVT,
7979                                             N0->getOperand(1),
7980                                             N0->getOperand(0),
7981                                             N1->getOperand(0));
7982                return DAG.getNode(ISD::BITCAST, dl, VT, Result);
7983            }
7984        }
7985    }
7986  }
7987
7988  // Try to use the ARM/Thumb2 BFI (bitfield insert) instruction when
7989  // reasonable.
7990
7991  // BFI is only available on V6T2+
7992  if (Subtarget->isThumb1Only() || !Subtarget->hasV6T2Ops())
7993    return SDValue();
7994
7995  SDLoc DL(N);
7996  // 1) or (and A, mask), val => ARMbfi A, val, mask
7997  //      iff (val & mask) == val
7998  //
7999  // 2) or (and A, mask), (and B, mask2) => ARMbfi A, (lsr B, amt), mask
8000  //  2a) iff isBitFieldInvertedMask(mask) && isBitFieldInvertedMask(~mask2)
8001  //          && mask == ~mask2
8002  //  2b) iff isBitFieldInvertedMask(~mask) && isBitFieldInvertedMask(mask2)
8003  //          && ~mask == mask2
8004  //  (i.e., copy a bitfield value into another bitfield of the same width)
8005
8006  if (VT != MVT::i32)
8007    return SDValue();
8008
8009  SDValue N00 = N0.getOperand(0);
8010
8011  // The value and the mask need to be constants so we can verify this is
8012  // actually a bitfield set. If the mask is 0xffff, we can do better
8013  // via a movt instruction, so don't use BFI in that case.
8014  SDValue MaskOp = N0.getOperand(1);
8015  ConstantSDNode *MaskC = dyn_cast<ConstantSDNode>(MaskOp);
8016  if (!MaskC)
8017    return SDValue();
8018  unsigned Mask = MaskC->getZExtValue();
8019  if (Mask == 0xffff)
8020    return SDValue();
8021  SDValue Res;
8022  // Case (1): or (and A, mask), val => ARMbfi A, val, mask
8023  ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
8024  if (N1C) {
8025    unsigned Val = N1C->getZExtValue();
8026    if ((Val & ~Mask) != Val)
8027      return SDValue();
8028
8029    if (ARM::isBitFieldInvertedMask(Mask)) {
8030      Val >>= countTrailingZeros(~Mask);
8031
8032      Res = DAG.getNode(ARMISD::BFI, DL, VT, N00,
8033                        DAG.getConstant(Val, MVT::i32),
8034                        DAG.getConstant(Mask, MVT::i32));
8035
8036      // Do not add new nodes to DAG combiner worklist.
8037      DCI.CombineTo(N, Res, false);
8038      return SDValue();
8039    }
8040  } else if (N1.getOpcode() == ISD::AND) {
8041    // case (2) or (and A, mask), (and B, mask2) => ARMbfi A, (lsr B, amt), mask
8042    ConstantSDNode *N11C = dyn_cast<ConstantSDNode>(N1.getOperand(1));
8043    if (!N11C)
8044      return SDValue();
8045    unsigned Mask2 = N11C->getZExtValue();
8046
8047    // Mask and ~Mask2 (or reverse) must be equivalent for the BFI pattern
8048    // as is to match.
8049    if (ARM::isBitFieldInvertedMask(Mask) &&
8050        (Mask == ~Mask2)) {
8051      // The pack halfword instruction works better for masks that fit it,
8052      // so use that when it's available.
8053      if (Subtarget->hasT2ExtractPack() &&
8054          (Mask == 0xffff || Mask == 0xffff0000))
8055        return SDValue();
8056      // 2a
8057      unsigned amt = countTrailingZeros(Mask2);
8058      Res = DAG.getNode(ISD::SRL, DL, VT, N1.getOperand(0),
8059                        DAG.getConstant(amt, MVT::i32));
8060      Res = DAG.getNode(ARMISD::BFI, DL, VT, N00, Res,
8061                        DAG.getConstant(Mask, MVT::i32));
8062      // Do not add new nodes to DAG combiner worklist.
8063      DCI.CombineTo(N, Res, false);
8064      return SDValue();
8065    } else if (ARM::isBitFieldInvertedMask(~Mask) &&
8066               (~Mask == Mask2)) {
8067      // The pack halfword instruction works better for masks that fit it,
8068      // so use that when it's available.
8069      if (Subtarget->hasT2ExtractPack() &&
8070          (Mask2 == 0xffff || Mask2 == 0xffff0000))
8071        return SDValue();
8072      // 2b
8073      unsigned lsb = countTrailingZeros(Mask);
8074      Res = DAG.getNode(ISD::SRL, DL, VT, N00,
8075                        DAG.getConstant(lsb, MVT::i32));
8076      Res = DAG.getNode(ARMISD::BFI, DL, VT, N1.getOperand(0), Res,
8077                        DAG.getConstant(Mask2, MVT::i32));
8078      // Do not add new nodes to DAG combiner worklist.
8079      DCI.CombineTo(N, Res, false);
8080      return SDValue();
8081    }
8082  }
8083
8084  if (DAG.MaskedValueIsZero(N1, MaskC->getAPIntValue()) &&
8085      N00.getOpcode() == ISD::SHL && isa<ConstantSDNode>(N00.getOperand(1)) &&
8086      ARM::isBitFieldInvertedMask(~Mask)) {
8087    // Case (3): or (and (shl A, #shamt), mask), B => ARMbfi B, A, ~mask
8088    // where lsb(mask) == #shamt and masked bits of B are known zero.
8089    SDValue ShAmt = N00.getOperand(1);
8090    unsigned ShAmtC = cast<ConstantSDNode>(ShAmt)->getZExtValue();
8091    unsigned LSB = countTrailingZeros(Mask);
8092    if (ShAmtC != LSB)
8093      return SDValue();
8094
8095    Res = DAG.getNode(ARMISD::BFI, DL, VT, N1, N00.getOperand(0),
8096                      DAG.getConstant(~Mask, MVT::i32));
8097
8098    // Do not add new nodes to DAG combiner worklist.
8099    DCI.CombineTo(N, Res, false);
8100  }
8101
8102  return SDValue();
8103}
8104
8105static SDValue PerformXORCombine(SDNode *N,
8106                                 TargetLowering::DAGCombinerInfo &DCI,
8107                                 const ARMSubtarget *Subtarget) {
8108  EVT VT = N->getValueType(0);
8109  SelectionDAG &DAG = DCI.DAG;
8110
8111  if(!DAG.getTargetLoweringInfo().isTypeLegal(VT))
8112    return SDValue();
8113
8114  if (!Subtarget->isThumb1Only()) {
8115    // fold (xor (select cc, 0, c), x) -> (select cc, x, (xor, x, c))
8116    SDValue Result = combineSelectAndUseCommutative(N, false, DCI);
8117    if (Result.getNode())
8118      return Result;
8119  }
8120
8121  return SDValue();
8122}
8123
8124/// PerformBFICombine - (bfi A, (and B, Mask1), Mask2) -> (bfi A, B, Mask2) iff
8125/// the bits being cleared by the AND are not demanded by the BFI.
8126static SDValue PerformBFICombine(SDNode *N,
8127                                 TargetLowering::DAGCombinerInfo &DCI) {
8128  SDValue N1 = N->getOperand(1);
8129  if (N1.getOpcode() == ISD::AND) {
8130    ConstantSDNode *N11C = dyn_cast<ConstantSDNode>(N1.getOperand(1));
8131    if (!N11C)
8132      return SDValue();
8133    unsigned InvMask = cast<ConstantSDNode>(N->getOperand(2))->getZExtValue();
8134    unsigned LSB = countTrailingZeros(~InvMask);
8135    unsigned Width = (32 - countLeadingZeros(~InvMask)) - LSB;
8136    unsigned Mask = (1 << Width)-1;
8137    unsigned Mask2 = N11C->getZExtValue();
8138    if ((Mask & (~Mask2)) == 0)
8139      return DCI.DAG.getNode(ARMISD::BFI, SDLoc(N), N->getValueType(0),
8140                             N->getOperand(0), N1.getOperand(0),
8141                             N->getOperand(2));
8142  }
8143  return SDValue();
8144}
8145
8146/// PerformVMOVRRDCombine - Target-specific dag combine xforms for
8147/// ARMISD::VMOVRRD.
8148static SDValue PerformVMOVRRDCombine(SDNode *N,
8149                                     TargetLowering::DAGCombinerInfo &DCI) {
8150  // vmovrrd(vmovdrr x, y) -> x,y
8151  SDValue InDouble = N->getOperand(0);
8152  if (InDouble.getOpcode() == ARMISD::VMOVDRR)
8153    return DCI.CombineTo(N, InDouble.getOperand(0), InDouble.getOperand(1));
8154
8155  // vmovrrd(load f64) -> (load i32), (load i32)
8156  SDNode *InNode = InDouble.getNode();
8157  if (ISD::isNormalLoad(InNode) && InNode->hasOneUse() &&
8158      InNode->getValueType(0) == MVT::f64 &&
8159      InNode->getOperand(1).getOpcode() == ISD::FrameIndex &&
8160      !cast<LoadSDNode>(InNode)->isVolatile()) {
8161    // TODO: Should this be done for non-FrameIndex operands?
8162    LoadSDNode *LD = cast<LoadSDNode>(InNode);
8163
8164    SelectionDAG &DAG = DCI.DAG;
8165    SDLoc DL(LD);
8166    SDValue BasePtr = LD->getBasePtr();
8167    SDValue NewLD1 = DAG.getLoad(MVT::i32, DL, LD->getChain(), BasePtr,
8168                                 LD->getPointerInfo(), LD->isVolatile(),
8169                                 LD->isNonTemporal(), LD->isInvariant(),
8170                                 LD->getAlignment());
8171
8172    SDValue OffsetPtr = DAG.getNode(ISD::ADD, DL, MVT::i32, BasePtr,
8173                                    DAG.getConstant(4, MVT::i32));
8174    SDValue NewLD2 = DAG.getLoad(MVT::i32, DL, NewLD1.getValue(1), OffsetPtr,
8175                                 LD->getPointerInfo(), LD->isVolatile(),
8176                                 LD->isNonTemporal(), LD->isInvariant(),
8177                                 std::min(4U, LD->getAlignment() / 2));
8178
8179    DAG.ReplaceAllUsesOfValueWith(SDValue(LD, 1), NewLD2.getValue(1));
8180    SDValue Result = DCI.CombineTo(N, NewLD1, NewLD2);
8181    DCI.RemoveFromWorklist(LD);
8182    DAG.DeleteNode(LD);
8183    return Result;
8184  }
8185
8186  return SDValue();
8187}
8188
8189/// PerformVMOVDRRCombine - Target-specific dag combine xforms for
8190/// ARMISD::VMOVDRR.  This is also used for BUILD_VECTORs with 2 operands.
8191static SDValue PerformVMOVDRRCombine(SDNode *N, SelectionDAG &DAG) {
8192  // N=vmovrrd(X); vmovdrr(N:0, N:1) -> bit_convert(X)
8193  SDValue Op0 = N->getOperand(0);
8194  SDValue Op1 = N->getOperand(1);
8195  if (Op0.getOpcode() == ISD::BITCAST)
8196    Op0 = Op0.getOperand(0);
8197  if (Op1.getOpcode() == ISD::BITCAST)
8198    Op1 = Op1.getOperand(0);
8199  if (Op0.getOpcode() == ARMISD::VMOVRRD &&
8200      Op0.getNode() == Op1.getNode() &&
8201      Op0.getResNo() == 0 && Op1.getResNo() == 1)
8202    return DAG.getNode(ISD::BITCAST, SDLoc(N),
8203                       N->getValueType(0), Op0.getOperand(0));
8204  return SDValue();
8205}
8206
8207/// PerformSTORECombine - Target-specific dag combine xforms for
8208/// ISD::STORE.
8209static SDValue PerformSTORECombine(SDNode *N,
8210                                   TargetLowering::DAGCombinerInfo &DCI) {
8211  StoreSDNode *St = cast<StoreSDNode>(N);
8212  if (St->isVolatile())
8213    return SDValue();
8214
8215  // Optimize trunc store (of multiple scalars) to shuffle and store.  First,
8216  // pack all of the elements in one place.  Next, store to memory in fewer
8217  // chunks.
8218  SDValue StVal = St->getValue();
8219  EVT VT = StVal.getValueType();
8220  if (St->isTruncatingStore() && VT.isVector()) {
8221    SelectionDAG &DAG = DCI.DAG;
8222    const TargetLowering &TLI = DAG.getTargetLoweringInfo();
8223    EVT StVT = St->getMemoryVT();
8224    unsigned NumElems = VT.getVectorNumElements();
8225    assert(StVT != VT && "Cannot truncate to the same type");
8226    unsigned FromEltSz = VT.getVectorElementType().getSizeInBits();
8227    unsigned ToEltSz = StVT.getVectorElementType().getSizeInBits();
8228
8229    // From, To sizes and ElemCount must be pow of two
8230    if (!isPowerOf2_32(NumElems * FromEltSz * ToEltSz)) return SDValue();
8231
8232    // We are going to use the original vector elt for storing.
8233    // Accumulated smaller vector elements must be a multiple of the store size.
8234    if (0 != (NumElems * FromEltSz) % ToEltSz) return SDValue();
8235
8236    unsigned SizeRatio  = FromEltSz / ToEltSz;
8237    assert(SizeRatio * NumElems * ToEltSz == VT.getSizeInBits());
8238
8239    // Create a type on which we perform the shuffle.
8240    EVT WideVecVT = EVT::getVectorVT(*DAG.getContext(), StVT.getScalarType(),
8241                                     NumElems*SizeRatio);
8242    assert(WideVecVT.getSizeInBits() == VT.getSizeInBits());
8243
8244    SDLoc DL(St);
8245    SDValue WideVec = DAG.getNode(ISD::BITCAST, DL, WideVecVT, StVal);
8246    SmallVector<int, 8> ShuffleVec(NumElems * SizeRatio, -1);
8247    for (unsigned i = 0; i < NumElems; ++i) ShuffleVec[i] = i * SizeRatio;
8248
8249    // Can't shuffle using an illegal type.
8250    if (!TLI.isTypeLegal(WideVecVT)) return SDValue();
8251
8252    SDValue Shuff = DAG.getVectorShuffle(WideVecVT, DL, WideVec,
8253                                DAG.getUNDEF(WideVec.getValueType()),
8254                                ShuffleVec.data());
8255    // At this point all of the data is stored at the bottom of the
8256    // register. We now need to save it to mem.
8257
8258    // Find the largest store unit
8259    MVT StoreType = MVT::i8;
8260    for (unsigned tp = MVT::FIRST_INTEGER_VALUETYPE;
8261         tp < MVT::LAST_INTEGER_VALUETYPE; ++tp) {
8262      MVT Tp = (MVT::SimpleValueType)tp;
8263      if (TLI.isTypeLegal(Tp) && Tp.getSizeInBits() <= NumElems * ToEltSz)
8264        StoreType = Tp;
8265    }
8266    // Didn't find a legal store type.
8267    if (!TLI.isTypeLegal(StoreType))
8268      return SDValue();
8269
8270    // Bitcast the original vector into a vector of store-size units
8271    EVT StoreVecVT = EVT::getVectorVT(*DAG.getContext(),
8272            StoreType, VT.getSizeInBits()/EVT(StoreType).getSizeInBits());
8273    assert(StoreVecVT.getSizeInBits() == VT.getSizeInBits());
8274    SDValue ShuffWide = DAG.getNode(ISD::BITCAST, DL, StoreVecVT, Shuff);
8275    SmallVector<SDValue, 8> Chains;
8276    SDValue Increment = DAG.getConstant(StoreType.getSizeInBits()/8,
8277                                        TLI.getPointerTy());
8278    SDValue BasePtr = St->getBasePtr();
8279
8280    // Perform one or more big stores into memory.
8281    unsigned E = (ToEltSz*NumElems)/StoreType.getSizeInBits();
8282    for (unsigned I = 0; I < E; I++) {
8283      SDValue SubVec = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL,
8284                                   StoreType, ShuffWide,
8285                                   DAG.getIntPtrConstant(I));
8286      SDValue Ch = DAG.getStore(St->getChain(), DL, SubVec, BasePtr,
8287                                St->getPointerInfo(), St->isVolatile(),
8288                                St->isNonTemporal(), St->getAlignment());
8289      BasePtr = DAG.getNode(ISD::ADD, DL, BasePtr.getValueType(), BasePtr,
8290                            Increment);
8291      Chains.push_back(Ch);
8292    }
8293    return DAG.getNode(ISD::TokenFactor, DL, MVT::Other, &Chains[0],
8294                       Chains.size());
8295  }
8296
8297  if (!ISD::isNormalStore(St))
8298    return SDValue();
8299
8300  // Split a store of a VMOVDRR into two integer stores to avoid mixing NEON and
8301  // ARM stores of arguments in the same cache line.
8302  if (StVal.getNode()->getOpcode() == ARMISD::VMOVDRR &&
8303      StVal.getNode()->hasOneUse()) {
8304    SelectionDAG  &DAG = DCI.DAG;
8305    SDLoc DL(St);
8306    SDValue BasePtr = St->getBasePtr();
8307    SDValue NewST1 = DAG.getStore(St->getChain(), DL,
8308                                  StVal.getNode()->getOperand(0), BasePtr,
8309                                  St->getPointerInfo(), St->isVolatile(),
8310                                  St->isNonTemporal(), St->getAlignment());
8311
8312    SDValue OffsetPtr = DAG.getNode(ISD::ADD, DL, MVT::i32, BasePtr,
8313                                    DAG.getConstant(4, MVT::i32));
8314    return DAG.getStore(NewST1.getValue(0), DL, StVal.getNode()->getOperand(1),
8315                        OffsetPtr, St->getPointerInfo(), St->isVolatile(),
8316                        St->isNonTemporal(),
8317                        std::min(4U, St->getAlignment() / 2));
8318  }
8319
8320  if (StVal.getValueType() != MVT::i64 ||
8321      StVal.getNode()->getOpcode() != ISD::EXTRACT_VECTOR_ELT)
8322    return SDValue();
8323
8324  // Bitcast an i64 store extracted from a vector to f64.
8325  // Otherwise, the i64 value will be legalized to a pair of i32 values.
8326  SelectionDAG &DAG = DCI.DAG;
8327  SDLoc dl(StVal);
8328  SDValue IntVec = StVal.getOperand(0);
8329  EVT FloatVT = EVT::getVectorVT(*DAG.getContext(), MVT::f64,
8330                                 IntVec.getValueType().getVectorNumElements());
8331  SDValue Vec = DAG.getNode(ISD::BITCAST, dl, FloatVT, IntVec);
8332  SDValue ExtElt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64,
8333                               Vec, StVal.getOperand(1));
8334  dl = SDLoc(N);
8335  SDValue V = DAG.getNode(ISD::BITCAST, dl, MVT::i64, ExtElt);
8336  // Make the DAGCombiner fold the bitcasts.
8337  DCI.AddToWorklist(Vec.getNode());
8338  DCI.AddToWorklist(ExtElt.getNode());
8339  DCI.AddToWorklist(V.getNode());
8340  return DAG.getStore(St->getChain(), dl, V, St->getBasePtr(),
8341                      St->getPointerInfo(), St->isVolatile(),
8342                      St->isNonTemporal(), St->getAlignment(),
8343                      St->getTBAAInfo());
8344}
8345
8346/// hasNormalLoadOperand - Check if any of the operands of a BUILD_VECTOR node
8347/// are normal, non-volatile loads.  If so, it is profitable to bitcast an
8348/// i64 vector to have f64 elements, since the value can then be loaded
8349/// directly into a VFP register.
8350static bool hasNormalLoadOperand(SDNode *N) {
8351  unsigned NumElts = N->getValueType(0).getVectorNumElements();
8352  for (unsigned i = 0; i < NumElts; ++i) {
8353    SDNode *Elt = N->getOperand(i).getNode();
8354    if (ISD::isNormalLoad(Elt) && !cast<LoadSDNode>(Elt)->isVolatile())
8355      return true;
8356  }
8357  return false;
8358}
8359
8360/// PerformBUILD_VECTORCombine - Target-specific dag combine xforms for
8361/// ISD::BUILD_VECTOR.
8362static SDValue PerformBUILD_VECTORCombine(SDNode *N,
8363                                          TargetLowering::DAGCombinerInfo &DCI){
8364  // build_vector(N=ARMISD::VMOVRRD(X), N:1) -> bit_convert(X):
8365  // VMOVRRD is introduced when legalizing i64 types.  It forces the i64 value
8366  // into a pair of GPRs, which is fine when the value is used as a scalar,
8367  // but if the i64 value is converted to a vector, we need to undo the VMOVRRD.
8368  SelectionDAG &DAG = DCI.DAG;
8369  if (N->getNumOperands() == 2) {
8370    SDValue RV = PerformVMOVDRRCombine(N, DAG);
8371    if (RV.getNode())
8372      return RV;
8373  }
8374
8375  // Load i64 elements as f64 values so that type legalization does not split
8376  // them up into i32 values.
8377  EVT VT = N->getValueType(0);
8378  if (VT.getVectorElementType() != MVT::i64 || !hasNormalLoadOperand(N))
8379    return SDValue();
8380  SDLoc dl(N);
8381  SmallVector<SDValue, 8> Ops;
8382  unsigned NumElts = VT.getVectorNumElements();
8383  for (unsigned i = 0; i < NumElts; ++i) {
8384    SDValue V = DAG.getNode(ISD::BITCAST, dl, MVT::f64, N->getOperand(i));
8385    Ops.push_back(V);
8386    // Make the DAGCombiner fold the bitcast.
8387    DCI.AddToWorklist(V.getNode());
8388  }
8389  EVT FloatVT = EVT::getVectorVT(*DAG.getContext(), MVT::f64, NumElts);
8390  SDValue BV = DAG.getNode(ISD::BUILD_VECTOR, dl, FloatVT, Ops.data(), NumElts);
8391  return DAG.getNode(ISD::BITCAST, dl, VT, BV);
8392}
8393
8394/// \brief Target-specific dag combine xforms for ARMISD::BUILD_VECTOR.
8395static SDValue
8396PerformARMBUILD_VECTORCombine(SDNode *N, TargetLowering::DAGCombinerInfo &DCI) {
8397  // ARMISD::BUILD_VECTOR is introduced when legalizing ISD::BUILD_VECTOR.
8398  // At that time, we may have inserted bitcasts from integer to float.
8399  // If these bitcasts have survived DAGCombine, change the lowering of this
8400  // BUILD_VECTOR in something more vector friendly, i.e., that does not
8401  // force to use floating point types.
8402
8403  // Make sure we can change the type of the vector.
8404  // This is possible iff:
8405  // 1. The vector is only used in a bitcast to a integer type. I.e.,
8406  //    1.1. Vector is used only once.
8407  //    1.2. Use is a bit convert to an integer type.
8408  // 2. The size of its operands are 32-bits (64-bits are not legal).
8409  EVT VT = N->getValueType(0);
8410  EVT EltVT = VT.getVectorElementType();
8411
8412  // Check 1.1. and 2.
8413  if (EltVT.getSizeInBits() != 32 || !N->hasOneUse())
8414    return SDValue();
8415
8416  // By construction, the input type must be float.
8417  assert(EltVT == MVT::f32 && "Unexpected type!");
8418
8419  // Check 1.2.
8420  SDNode *Use = *N->use_begin();
8421  if (Use->getOpcode() != ISD::BITCAST ||
8422      Use->getValueType(0).isFloatingPoint())
8423    return SDValue();
8424
8425  // Check profitability.
8426  // Model is, if more than half of the relevant operands are bitcast from
8427  // i32, turn the build_vector into a sequence of insert_vector_elt.
8428  // Relevant operands are everything that is not statically
8429  // (i.e., at compile time) bitcasted.
8430  unsigned NumOfBitCastedElts = 0;
8431  unsigned NumElts = VT.getVectorNumElements();
8432  unsigned NumOfRelevantElts = NumElts;
8433  for (unsigned Idx = 0; Idx < NumElts; ++Idx) {
8434    SDValue Elt = N->getOperand(Idx);
8435    if (Elt->getOpcode() == ISD::BITCAST) {
8436      // Assume only bit cast to i32 will go away.
8437      if (Elt->getOperand(0).getValueType() == MVT::i32)
8438        ++NumOfBitCastedElts;
8439    } else if (Elt.getOpcode() == ISD::UNDEF || isa<ConstantSDNode>(Elt))
8440      // Constants are statically casted, thus do not count them as
8441      // relevant operands.
8442      --NumOfRelevantElts;
8443  }
8444
8445  // Check if more than half of the elements require a non-free bitcast.
8446  if (NumOfBitCastedElts <= NumOfRelevantElts / 2)
8447    return SDValue();
8448
8449  SelectionDAG &DAG = DCI.DAG;
8450  // Create the new vector type.
8451  EVT VecVT = EVT::getVectorVT(*DAG.getContext(), MVT::i32, NumElts);
8452  // Check if the type is legal.
8453  const TargetLowering &TLI = DAG.getTargetLoweringInfo();
8454  if (!TLI.isTypeLegal(VecVT))
8455    return SDValue();
8456
8457  // Combine:
8458  // ARMISD::BUILD_VECTOR E1, E2, ..., EN.
8459  // => BITCAST INSERT_VECTOR_ELT
8460  //                      (INSERT_VECTOR_ELT (...), (BITCAST EN-1), N-1),
8461  //                      (BITCAST EN), N.
8462  SDValue Vec = DAG.getUNDEF(VecVT);
8463  SDLoc dl(N);
8464  for (unsigned Idx = 0 ; Idx < NumElts; ++Idx) {
8465    SDValue V = N->getOperand(Idx);
8466    if (V.getOpcode() == ISD::UNDEF)
8467      continue;
8468    if (V.getOpcode() == ISD::BITCAST &&
8469        V->getOperand(0).getValueType() == MVT::i32)
8470      // Fold obvious case.
8471      V = V.getOperand(0);
8472    else {
8473      V = DAG.getNode(ISD::BITCAST, SDLoc(V), MVT::i32, V);
8474      // Make the DAGCombiner fold the bitcasts.
8475      DCI.AddToWorklist(V.getNode());
8476    }
8477    SDValue LaneIdx = DAG.getConstant(Idx, MVT::i32);
8478    Vec = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VecVT, Vec, V, LaneIdx);
8479  }
8480  Vec = DAG.getNode(ISD::BITCAST, dl, VT, Vec);
8481  // Make the DAGCombiner fold the bitcasts.
8482  DCI.AddToWorklist(Vec.getNode());
8483  return Vec;
8484}
8485
8486/// PerformInsertEltCombine - Target-specific dag combine xforms for
8487/// ISD::INSERT_VECTOR_ELT.
8488static SDValue PerformInsertEltCombine(SDNode *N,
8489                                       TargetLowering::DAGCombinerInfo &DCI) {
8490  // Bitcast an i64 load inserted into a vector to f64.
8491  // Otherwise, the i64 value will be legalized to a pair of i32 values.
8492  EVT VT = N->getValueType(0);
8493  SDNode *Elt = N->getOperand(1).getNode();
8494  if (VT.getVectorElementType() != MVT::i64 ||
8495      !ISD::isNormalLoad(Elt) || cast<LoadSDNode>(Elt)->isVolatile())
8496    return SDValue();
8497
8498  SelectionDAG &DAG = DCI.DAG;
8499  SDLoc dl(N);
8500  EVT FloatVT = EVT::getVectorVT(*DAG.getContext(), MVT::f64,
8501                                 VT.getVectorNumElements());
8502  SDValue Vec = DAG.getNode(ISD::BITCAST, dl, FloatVT, N->getOperand(0));
8503  SDValue V = DAG.getNode(ISD::BITCAST, dl, MVT::f64, N->getOperand(1));
8504  // Make the DAGCombiner fold the bitcasts.
8505  DCI.AddToWorklist(Vec.getNode());
8506  DCI.AddToWorklist(V.getNode());
8507  SDValue InsElt = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, FloatVT,
8508                               Vec, V, N->getOperand(2));
8509  return DAG.getNode(ISD::BITCAST, dl, VT, InsElt);
8510}
8511
8512/// PerformVECTOR_SHUFFLECombine - Target-specific dag combine xforms for
8513/// ISD::VECTOR_SHUFFLE.
8514static SDValue PerformVECTOR_SHUFFLECombine(SDNode *N, SelectionDAG &DAG) {
8515  // The LLVM shufflevector instruction does not require the shuffle mask
8516  // length to match the operand vector length, but ISD::VECTOR_SHUFFLE does
8517  // have that requirement.  When translating to ISD::VECTOR_SHUFFLE, if the
8518  // operands do not match the mask length, they are extended by concatenating
8519  // them with undef vectors.  That is probably the right thing for other
8520  // targets, but for NEON it is better to concatenate two double-register
8521  // size vector operands into a single quad-register size vector.  Do that
8522  // transformation here:
8523  //   shuffle(concat(v1, undef), concat(v2, undef)) ->
8524  //   shuffle(concat(v1, v2), undef)
8525  SDValue Op0 = N->getOperand(0);
8526  SDValue Op1 = N->getOperand(1);
8527  if (Op0.getOpcode() != ISD::CONCAT_VECTORS ||
8528      Op1.getOpcode() != ISD::CONCAT_VECTORS ||
8529      Op0.getNumOperands() != 2 ||
8530      Op1.getNumOperands() != 2)
8531    return SDValue();
8532  SDValue Concat0Op1 = Op0.getOperand(1);
8533  SDValue Concat1Op1 = Op1.getOperand(1);
8534  if (Concat0Op1.getOpcode() != ISD::UNDEF ||
8535      Concat1Op1.getOpcode() != ISD::UNDEF)
8536    return SDValue();
8537  // Skip the transformation if any of the types are illegal.
8538  const TargetLowering &TLI = DAG.getTargetLoweringInfo();
8539  EVT VT = N->getValueType(0);
8540  if (!TLI.isTypeLegal(VT) ||
8541      !TLI.isTypeLegal(Concat0Op1.getValueType()) ||
8542      !TLI.isTypeLegal(Concat1Op1.getValueType()))
8543    return SDValue();
8544
8545  SDValue NewConcat = DAG.getNode(ISD::CONCAT_VECTORS, SDLoc(N), VT,
8546                                  Op0.getOperand(0), Op1.getOperand(0));
8547  // Translate the shuffle mask.
8548  SmallVector<int, 16> NewMask;
8549  unsigned NumElts = VT.getVectorNumElements();
8550  unsigned HalfElts = NumElts/2;
8551  ShuffleVectorSDNode *SVN = cast<ShuffleVectorSDNode>(N);
8552  for (unsigned n = 0; n < NumElts; ++n) {
8553    int MaskElt = SVN->getMaskElt(n);
8554    int NewElt = -1;
8555    if (MaskElt < (int)HalfElts)
8556      NewElt = MaskElt;
8557    else if (MaskElt >= (int)NumElts && MaskElt < (int)(NumElts + HalfElts))
8558      NewElt = HalfElts + MaskElt - NumElts;
8559    NewMask.push_back(NewElt);
8560  }
8561  return DAG.getVectorShuffle(VT, SDLoc(N), NewConcat,
8562                              DAG.getUNDEF(VT), NewMask.data());
8563}
8564
8565/// CombineBaseUpdate - Target-specific DAG combine function for VLDDUP and
8566/// NEON load/store intrinsics to merge base address updates.
8567static SDValue CombineBaseUpdate(SDNode *N,
8568                                 TargetLowering::DAGCombinerInfo &DCI) {
8569  if (DCI.isBeforeLegalize() || DCI.isCalledByLegalizer())
8570    return SDValue();
8571
8572  SelectionDAG &DAG = DCI.DAG;
8573  bool isIntrinsic = (N->getOpcode() == ISD::INTRINSIC_VOID ||
8574                      N->getOpcode() == ISD::INTRINSIC_W_CHAIN);
8575  unsigned AddrOpIdx = (isIntrinsic ? 2 : 1);
8576  SDValue Addr = N->getOperand(AddrOpIdx);
8577
8578  // Search for a use of the address operand that is an increment.
8579  for (SDNode::use_iterator UI = Addr.getNode()->use_begin(),
8580         UE = Addr.getNode()->use_end(); UI != UE; ++UI) {
8581    SDNode *User = *UI;
8582    if (User->getOpcode() != ISD::ADD ||
8583        UI.getUse().getResNo() != Addr.getResNo())
8584      continue;
8585
8586    // Check that the add is independent of the load/store.  Otherwise, folding
8587    // it would create a cycle.
8588    if (User->isPredecessorOf(N) || N->isPredecessorOf(User))
8589      continue;
8590
8591    // Find the new opcode for the updating load/store.
8592    bool isLoad = true;
8593    bool isLaneOp = false;
8594    unsigned NewOpc = 0;
8595    unsigned NumVecs = 0;
8596    if (isIntrinsic) {
8597      unsigned IntNo = cast<ConstantSDNode>(N->getOperand(1))->getZExtValue();
8598      switch (IntNo) {
8599      default: llvm_unreachable("unexpected intrinsic for Neon base update");
8600      case Intrinsic::arm_neon_vld1:     NewOpc = ARMISD::VLD1_UPD;
8601        NumVecs = 1; break;
8602      case Intrinsic::arm_neon_vld2:     NewOpc = ARMISD::VLD2_UPD;
8603        NumVecs = 2; break;
8604      case Intrinsic::arm_neon_vld3:     NewOpc = ARMISD::VLD3_UPD;
8605        NumVecs = 3; break;
8606      case Intrinsic::arm_neon_vld4:     NewOpc = ARMISD::VLD4_UPD;
8607        NumVecs = 4; break;
8608      case Intrinsic::arm_neon_vld2lane: NewOpc = ARMISD::VLD2LN_UPD;
8609        NumVecs = 2; isLaneOp = true; break;
8610      case Intrinsic::arm_neon_vld3lane: NewOpc = ARMISD::VLD3LN_UPD;
8611        NumVecs = 3; isLaneOp = true; break;
8612      case Intrinsic::arm_neon_vld4lane: NewOpc = ARMISD::VLD4LN_UPD;
8613        NumVecs = 4; isLaneOp = true; break;
8614      case Intrinsic::arm_neon_vst1:     NewOpc = ARMISD::VST1_UPD;
8615        NumVecs = 1; isLoad = false; break;
8616      case Intrinsic::arm_neon_vst2:     NewOpc = ARMISD::VST2_UPD;
8617        NumVecs = 2; isLoad = false; break;
8618      case Intrinsic::arm_neon_vst3:     NewOpc = ARMISD::VST3_UPD;
8619        NumVecs = 3; isLoad = false; break;
8620      case Intrinsic::arm_neon_vst4:     NewOpc = ARMISD::VST4_UPD;
8621        NumVecs = 4; isLoad = false; break;
8622      case Intrinsic::arm_neon_vst2lane: NewOpc = ARMISD::VST2LN_UPD;
8623        NumVecs = 2; isLoad = false; isLaneOp = true; break;
8624      case Intrinsic::arm_neon_vst3lane: NewOpc = ARMISD::VST3LN_UPD;
8625        NumVecs = 3; isLoad = false; isLaneOp = true; break;
8626      case Intrinsic::arm_neon_vst4lane: NewOpc = ARMISD::VST4LN_UPD;
8627        NumVecs = 4; isLoad = false; isLaneOp = true; break;
8628      }
8629    } else {
8630      isLaneOp = true;
8631      switch (N->getOpcode()) {
8632      default: llvm_unreachable("unexpected opcode for Neon base update");
8633      case ARMISD::VLD2DUP: NewOpc = ARMISD::VLD2DUP_UPD; NumVecs = 2; break;
8634      case ARMISD::VLD3DUP: NewOpc = ARMISD::VLD3DUP_UPD; NumVecs = 3; break;
8635      case ARMISD::VLD4DUP: NewOpc = ARMISD::VLD4DUP_UPD; NumVecs = 4; break;
8636      }
8637    }
8638
8639    // Find the size of memory referenced by the load/store.
8640    EVT VecTy;
8641    if (isLoad)
8642      VecTy = N->getValueType(0);
8643    else
8644      VecTy = N->getOperand(AddrOpIdx+1).getValueType();
8645    unsigned NumBytes = NumVecs * VecTy.getSizeInBits() / 8;
8646    if (isLaneOp)
8647      NumBytes /= VecTy.getVectorNumElements();
8648
8649    // If the increment is a constant, it must match the memory ref size.
8650    SDValue Inc = User->getOperand(User->getOperand(0) == Addr ? 1 : 0);
8651    if (ConstantSDNode *CInc = dyn_cast<ConstantSDNode>(Inc.getNode())) {
8652      uint64_t IncVal = CInc->getZExtValue();
8653      if (IncVal != NumBytes)
8654        continue;
8655    } else if (NumBytes >= 3 * 16) {
8656      // VLD3/4 and VST3/4 for 128-bit vectors are implemented with two
8657      // separate instructions that make it harder to use a non-constant update.
8658      continue;
8659    }
8660
8661    // Create the new updating load/store node.
8662    EVT Tys[6];
8663    unsigned NumResultVecs = (isLoad ? NumVecs : 0);
8664    unsigned n;
8665    for (n = 0; n < NumResultVecs; ++n)
8666      Tys[n] = VecTy;
8667    Tys[n++] = MVT::i32;
8668    Tys[n] = MVT::Other;
8669    SDVTList SDTys = DAG.getVTList(Tys, NumResultVecs+2);
8670    SmallVector<SDValue, 8> Ops;
8671    Ops.push_back(N->getOperand(0)); // incoming chain
8672    Ops.push_back(N->getOperand(AddrOpIdx));
8673    Ops.push_back(Inc);
8674    for (unsigned i = AddrOpIdx + 1; i < N->getNumOperands(); ++i) {
8675      Ops.push_back(N->getOperand(i));
8676    }
8677    MemIntrinsicSDNode *MemInt = cast<MemIntrinsicSDNode>(N);
8678    SDValue UpdN = DAG.getMemIntrinsicNode(NewOpc, SDLoc(N), SDTys,
8679                                           Ops.data(), Ops.size(),
8680                                           MemInt->getMemoryVT(),
8681                                           MemInt->getMemOperand());
8682
8683    // Update the uses.
8684    std::vector<SDValue> NewResults;
8685    for (unsigned i = 0; i < NumResultVecs; ++i) {
8686      NewResults.push_back(SDValue(UpdN.getNode(), i));
8687    }
8688    NewResults.push_back(SDValue(UpdN.getNode(), NumResultVecs+1)); // chain
8689    DCI.CombineTo(N, NewResults);
8690    DCI.CombineTo(User, SDValue(UpdN.getNode(), NumResultVecs));
8691
8692    break;
8693  }
8694  return SDValue();
8695}
8696
8697/// CombineVLDDUP - For a VDUPLANE node N, check if its source operand is a
8698/// vldN-lane (N > 1) intrinsic, and if all the other uses of that intrinsic
8699/// are also VDUPLANEs.  If so, combine them to a vldN-dup operation and
8700/// return true.
8701static bool CombineVLDDUP(SDNode *N, TargetLowering::DAGCombinerInfo &DCI) {
8702  SelectionDAG &DAG = DCI.DAG;
8703  EVT VT = N->getValueType(0);
8704  // vldN-dup instructions only support 64-bit vectors for N > 1.
8705  if (!VT.is64BitVector())
8706    return false;
8707
8708  // Check if the VDUPLANE operand is a vldN-dup intrinsic.
8709  SDNode *VLD = N->getOperand(0).getNode();
8710  if (VLD->getOpcode() != ISD::INTRINSIC_W_CHAIN)
8711    return false;
8712  unsigned NumVecs = 0;
8713  unsigned NewOpc = 0;
8714  unsigned IntNo = cast<ConstantSDNode>(VLD->getOperand(1))->getZExtValue();
8715  if (IntNo == Intrinsic::arm_neon_vld2lane) {
8716    NumVecs = 2;
8717    NewOpc = ARMISD::VLD2DUP;
8718  } else if (IntNo == Intrinsic::arm_neon_vld3lane) {
8719    NumVecs = 3;
8720    NewOpc = ARMISD::VLD3DUP;
8721  } else if (IntNo == Intrinsic::arm_neon_vld4lane) {
8722    NumVecs = 4;
8723    NewOpc = ARMISD::VLD4DUP;
8724  } else {
8725    return false;
8726  }
8727
8728  // First check that all the vldN-lane uses are VDUPLANEs and that the lane
8729  // numbers match the load.
8730  unsigned VLDLaneNo =
8731    cast<ConstantSDNode>(VLD->getOperand(NumVecs+3))->getZExtValue();
8732  for (SDNode::use_iterator UI = VLD->use_begin(), UE = VLD->use_end();
8733       UI != UE; ++UI) {
8734    // Ignore uses of the chain result.
8735    if (UI.getUse().getResNo() == NumVecs)
8736      continue;
8737    SDNode *User = *UI;
8738    if (User->getOpcode() != ARMISD::VDUPLANE ||
8739        VLDLaneNo != cast<ConstantSDNode>(User->getOperand(1))->getZExtValue())
8740      return false;
8741  }
8742
8743  // Create the vldN-dup node.
8744  EVT Tys[5];
8745  unsigned n;
8746  for (n = 0; n < NumVecs; ++n)
8747    Tys[n] = VT;
8748  Tys[n] = MVT::Other;
8749  SDVTList SDTys = DAG.getVTList(Tys, NumVecs+1);
8750  SDValue Ops[] = { VLD->getOperand(0), VLD->getOperand(2) };
8751  MemIntrinsicSDNode *VLDMemInt = cast<MemIntrinsicSDNode>(VLD);
8752  SDValue VLDDup = DAG.getMemIntrinsicNode(NewOpc, SDLoc(VLD), SDTys,
8753                                           Ops, 2, VLDMemInt->getMemoryVT(),
8754                                           VLDMemInt->getMemOperand());
8755
8756  // Update the uses.
8757  for (SDNode::use_iterator UI = VLD->use_begin(), UE = VLD->use_end();
8758       UI != UE; ++UI) {
8759    unsigned ResNo = UI.getUse().getResNo();
8760    // Ignore uses of the chain result.
8761    if (ResNo == NumVecs)
8762      continue;
8763    SDNode *User = *UI;
8764    DCI.CombineTo(User, SDValue(VLDDup.getNode(), ResNo));
8765  }
8766
8767  // Now the vldN-lane intrinsic is dead except for its chain result.
8768  // Update uses of the chain.
8769  std::vector<SDValue> VLDDupResults;
8770  for (unsigned n = 0; n < NumVecs; ++n)
8771    VLDDupResults.push_back(SDValue(VLDDup.getNode(), n));
8772  VLDDupResults.push_back(SDValue(VLDDup.getNode(), NumVecs));
8773  DCI.CombineTo(VLD, VLDDupResults);
8774
8775  return true;
8776}
8777
8778/// PerformVDUPLANECombine - Target-specific dag combine xforms for
8779/// ARMISD::VDUPLANE.
8780static SDValue PerformVDUPLANECombine(SDNode *N,
8781                                      TargetLowering::DAGCombinerInfo &DCI) {
8782  SDValue Op = N->getOperand(0);
8783
8784  // If the source is a vldN-lane (N > 1) intrinsic, and all the other uses
8785  // of that intrinsic are also VDUPLANEs, combine them to a vldN-dup operation.
8786  if (CombineVLDDUP(N, DCI))
8787    return SDValue(N, 0);
8788
8789  // If the source is already a VMOVIMM or VMVNIMM splat, the VDUPLANE is
8790  // redundant.  Ignore bit_converts for now; element sizes are checked below.
8791  while (Op.getOpcode() == ISD::BITCAST)
8792    Op = Op.getOperand(0);
8793  if (Op.getOpcode() != ARMISD::VMOVIMM && Op.getOpcode() != ARMISD::VMVNIMM)
8794    return SDValue();
8795
8796  // Make sure the VMOV element size is not bigger than the VDUPLANE elements.
8797  unsigned EltSize = Op.getValueType().getVectorElementType().getSizeInBits();
8798  // The canonical VMOV for a zero vector uses a 32-bit element size.
8799  unsigned Imm = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
8800  unsigned EltBits;
8801  if (ARM_AM::decodeNEONModImm(Imm, EltBits) == 0)
8802    EltSize = 8;
8803  EVT VT = N->getValueType(0);
8804  if (EltSize > VT.getVectorElementType().getSizeInBits())
8805    return SDValue();
8806
8807  return DCI.DAG.getNode(ISD::BITCAST, SDLoc(N), VT, Op);
8808}
8809
8810// isConstVecPow2 - Return true if each vector element is a power of 2, all
8811// elements are the same constant, C, and Log2(C) ranges from 1 to 32.
8812static bool isConstVecPow2(SDValue ConstVec, bool isSigned, uint64_t &C)
8813{
8814  integerPart cN;
8815  integerPart c0 = 0;
8816  for (unsigned I = 0, E = ConstVec.getValueType().getVectorNumElements();
8817       I != E; I++) {
8818    ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(ConstVec.getOperand(I));
8819    if (!C)
8820      return false;
8821
8822    bool isExact;
8823    APFloat APF = C->getValueAPF();
8824    if (APF.convertToInteger(&cN, 64, isSigned, APFloat::rmTowardZero, &isExact)
8825        != APFloat::opOK || !isExact)
8826      return false;
8827
8828    c0 = (I == 0) ? cN : c0;
8829    if (!isPowerOf2_64(cN) || c0 != cN || Log2_64(c0) < 1 || Log2_64(c0) > 32)
8830      return false;
8831  }
8832  C = c0;
8833  return true;
8834}
8835
8836/// PerformVCVTCombine - VCVT (floating-point to fixed-point, Advanced SIMD)
8837/// can replace combinations of VMUL and VCVT (floating-point to integer)
8838/// when the VMUL has a constant operand that is a power of 2.
8839///
8840/// Example (assume d17 = <float 8.000000e+00, float 8.000000e+00>):
8841///  vmul.f32        d16, d17, d16
8842///  vcvt.s32.f32    d16, d16
8843/// becomes:
8844///  vcvt.s32.f32    d16, d16, #3
8845static SDValue PerformVCVTCombine(SDNode *N,
8846                                  TargetLowering::DAGCombinerInfo &DCI,
8847                                  const ARMSubtarget *Subtarget) {
8848  SelectionDAG &DAG = DCI.DAG;
8849  SDValue Op = N->getOperand(0);
8850
8851  if (!Subtarget->hasNEON() || !Op.getValueType().isVector() ||
8852      Op.getOpcode() != ISD::FMUL)
8853    return SDValue();
8854
8855  uint64_t C;
8856  SDValue N0 = Op->getOperand(0);
8857  SDValue ConstVec = Op->getOperand(1);
8858  bool isSigned = N->getOpcode() == ISD::FP_TO_SINT;
8859
8860  if (ConstVec.getOpcode() != ISD::BUILD_VECTOR ||
8861      !isConstVecPow2(ConstVec, isSigned, C))
8862    return SDValue();
8863
8864  MVT FloatTy = Op.getSimpleValueType().getVectorElementType();
8865  MVT IntTy = N->getSimpleValueType(0).getVectorElementType();
8866  if (FloatTy.getSizeInBits() != 32 || IntTy.getSizeInBits() > 32) {
8867    // These instructions only exist converting from f32 to i32. We can handle
8868    // smaller integers by generating an extra truncate, but larger ones would
8869    // be lossy.
8870    return SDValue();
8871  }
8872
8873  unsigned IntrinsicOpcode = isSigned ? Intrinsic::arm_neon_vcvtfp2fxs :
8874    Intrinsic::arm_neon_vcvtfp2fxu;
8875  unsigned NumLanes = Op.getValueType().getVectorNumElements();
8876  SDValue FixConv =  DAG.getNode(ISD::INTRINSIC_WO_CHAIN, SDLoc(N),
8877                                 NumLanes == 2 ? MVT::v2i32 : MVT::v4i32,
8878                                 DAG.getConstant(IntrinsicOpcode, MVT::i32), N0,
8879                                 DAG.getConstant(Log2_64(C), MVT::i32));
8880
8881  if (IntTy.getSizeInBits() < FloatTy.getSizeInBits())
8882    FixConv = DAG.getNode(ISD::TRUNCATE, SDLoc(N), N->getValueType(0), FixConv);
8883
8884  return FixConv;
8885}
8886
8887/// PerformVDIVCombine - VCVT (fixed-point to floating-point, Advanced SIMD)
8888/// can replace combinations of VCVT (integer to floating-point) and VDIV
8889/// when the VDIV has a constant operand that is a power of 2.
8890///
8891/// Example (assume d17 = <float 8.000000e+00, float 8.000000e+00>):
8892///  vcvt.f32.s32    d16, d16
8893///  vdiv.f32        d16, d17, d16
8894/// becomes:
8895///  vcvt.f32.s32    d16, d16, #3
8896static SDValue PerformVDIVCombine(SDNode *N,
8897                                  TargetLowering::DAGCombinerInfo &DCI,
8898                                  const ARMSubtarget *Subtarget) {
8899  SelectionDAG &DAG = DCI.DAG;
8900  SDValue Op = N->getOperand(0);
8901  unsigned OpOpcode = Op.getNode()->getOpcode();
8902
8903  if (!Subtarget->hasNEON() || !N->getValueType(0).isVector() ||
8904      (OpOpcode != ISD::SINT_TO_FP && OpOpcode != ISD::UINT_TO_FP))
8905    return SDValue();
8906
8907  uint64_t C;
8908  SDValue ConstVec = N->getOperand(1);
8909  bool isSigned = OpOpcode == ISD::SINT_TO_FP;
8910
8911  if (ConstVec.getOpcode() != ISD::BUILD_VECTOR ||
8912      !isConstVecPow2(ConstVec, isSigned, C))
8913    return SDValue();
8914
8915  MVT FloatTy = N->getSimpleValueType(0).getVectorElementType();
8916  MVT IntTy = Op.getOperand(0).getSimpleValueType().getVectorElementType();
8917  if (FloatTy.getSizeInBits() != 32 || IntTy.getSizeInBits() > 32) {
8918    // These instructions only exist converting from i32 to f32. We can handle
8919    // smaller integers by generating an extra extend, but larger ones would
8920    // be lossy.
8921    return SDValue();
8922  }
8923
8924  SDValue ConvInput = Op.getOperand(0);
8925  unsigned NumLanes = Op.getValueType().getVectorNumElements();
8926  if (IntTy.getSizeInBits() < FloatTy.getSizeInBits())
8927    ConvInput = DAG.getNode(isSigned ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND,
8928                            SDLoc(N), NumLanes == 2 ? MVT::v2i32 : MVT::v4i32,
8929                            ConvInput);
8930
8931  unsigned IntrinsicOpcode = isSigned ? Intrinsic::arm_neon_vcvtfxs2fp :
8932    Intrinsic::arm_neon_vcvtfxu2fp;
8933  return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, SDLoc(N),
8934                     Op.getValueType(),
8935                     DAG.getConstant(IntrinsicOpcode, MVT::i32),
8936                     ConvInput, DAG.getConstant(Log2_64(C), MVT::i32));
8937}
8938
8939/// Getvshiftimm - Check if this is a valid build_vector for the immediate
8940/// operand of a vector shift operation, where all the elements of the
8941/// build_vector must have the same constant integer value.
8942static bool getVShiftImm(SDValue Op, unsigned ElementBits, int64_t &Cnt) {
8943  // Ignore bit_converts.
8944  while (Op.getOpcode() == ISD::BITCAST)
8945    Op = Op.getOperand(0);
8946  BuildVectorSDNode *BVN = dyn_cast<BuildVectorSDNode>(Op.getNode());
8947  APInt SplatBits, SplatUndef;
8948  unsigned SplatBitSize;
8949  bool HasAnyUndefs;
8950  if (! BVN || ! BVN->isConstantSplat(SplatBits, SplatUndef, SplatBitSize,
8951                                      HasAnyUndefs, ElementBits) ||
8952      SplatBitSize > ElementBits)
8953    return false;
8954  Cnt = SplatBits.getSExtValue();
8955  return true;
8956}
8957
8958/// isVShiftLImm - Check if this is a valid build_vector for the immediate
8959/// operand of a vector shift left operation.  That value must be in the range:
8960///   0 <= Value < ElementBits for a left shift; or
8961///   0 <= Value <= ElementBits for a long left shift.
8962static bool isVShiftLImm(SDValue Op, EVT VT, bool isLong, int64_t &Cnt) {
8963  assert(VT.isVector() && "vector shift count is not a vector type");
8964  unsigned ElementBits = VT.getVectorElementType().getSizeInBits();
8965  if (! getVShiftImm(Op, ElementBits, Cnt))
8966    return false;
8967  return (Cnt >= 0 && (isLong ? Cnt-1 : Cnt) < ElementBits);
8968}
8969
8970/// isVShiftRImm - Check if this is a valid build_vector for the immediate
8971/// operand of a vector shift right operation.  For a shift opcode, the value
8972/// is positive, but for an intrinsic the value count must be negative. The
8973/// absolute value must be in the range:
8974///   1 <= |Value| <= ElementBits for a right shift; or
8975///   1 <= |Value| <= ElementBits/2 for a narrow right shift.
8976static bool isVShiftRImm(SDValue Op, EVT VT, bool isNarrow, bool isIntrinsic,
8977                         int64_t &Cnt) {
8978  assert(VT.isVector() && "vector shift count is not a vector type");
8979  unsigned ElementBits = VT.getVectorElementType().getSizeInBits();
8980  if (! getVShiftImm(Op, ElementBits, Cnt))
8981    return false;
8982  if (isIntrinsic)
8983    Cnt = -Cnt;
8984  return (Cnt >= 1 && Cnt <= (isNarrow ? ElementBits/2 : ElementBits));
8985}
8986
8987/// PerformIntrinsicCombine - ARM-specific DAG combining for intrinsics.
8988static SDValue PerformIntrinsicCombine(SDNode *N, SelectionDAG &DAG) {
8989  unsigned IntNo = cast<ConstantSDNode>(N->getOperand(0))->getZExtValue();
8990  switch (IntNo) {
8991  default:
8992    // Don't do anything for most intrinsics.
8993    break;
8994
8995  // Vector shifts: check for immediate versions and lower them.
8996  // Note: This is done during DAG combining instead of DAG legalizing because
8997  // the build_vectors for 64-bit vector element shift counts are generally
8998  // not legal, and it is hard to see their values after they get legalized to
8999  // loads from a constant pool.
9000  case Intrinsic::arm_neon_vshifts:
9001  case Intrinsic::arm_neon_vshiftu:
9002  case Intrinsic::arm_neon_vrshifts:
9003  case Intrinsic::arm_neon_vrshiftu:
9004  case Intrinsic::arm_neon_vrshiftn:
9005  case Intrinsic::arm_neon_vqshifts:
9006  case Intrinsic::arm_neon_vqshiftu:
9007  case Intrinsic::arm_neon_vqshiftsu:
9008  case Intrinsic::arm_neon_vqshiftns:
9009  case Intrinsic::arm_neon_vqshiftnu:
9010  case Intrinsic::arm_neon_vqshiftnsu:
9011  case Intrinsic::arm_neon_vqrshiftns:
9012  case Intrinsic::arm_neon_vqrshiftnu:
9013  case Intrinsic::arm_neon_vqrshiftnsu: {
9014    EVT VT = N->getOperand(1).getValueType();
9015    int64_t Cnt;
9016    unsigned VShiftOpc = 0;
9017
9018    switch (IntNo) {
9019    case Intrinsic::arm_neon_vshifts:
9020    case Intrinsic::arm_neon_vshiftu:
9021      if (isVShiftLImm(N->getOperand(2), VT, false, Cnt)) {
9022        VShiftOpc = ARMISD::VSHL;
9023        break;
9024      }
9025      if (isVShiftRImm(N->getOperand(2), VT, false, true, Cnt)) {
9026        VShiftOpc = (IntNo == Intrinsic::arm_neon_vshifts ?
9027                     ARMISD::VSHRs : ARMISD::VSHRu);
9028        break;
9029      }
9030      return SDValue();
9031
9032    case Intrinsic::arm_neon_vrshifts:
9033    case Intrinsic::arm_neon_vrshiftu:
9034      if (isVShiftRImm(N->getOperand(2), VT, false, true, Cnt))
9035        break;
9036      return SDValue();
9037
9038    case Intrinsic::arm_neon_vqshifts:
9039    case Intrinsic::arm_neon_vqshiftu:
9040      if (isVShiftLImm(N->getOperand(2), VT, false, Cnt))
9041        break;
9042      return SDValue();
9043
9044    case Intrinsic::arm_neon_vqshiftsu:
9045      if (isVShiftLImm(N->getOperand(2), VT, false, Cnt))
9046        break;
9047      llvm_unreachable("invalid shift count for vqshlu intrinsic");
9048
9049    case Intrinsic::arm_neon_vrshiftn:
9050    case Intrinsic::arm_neon_vqshiftns:
9051    case Intrinsic::arm_neon_vqshiftnu:
9052    case Intrinsic::arm_neon_vqshiftnsu:
9053    case Intrinsic::arm_neon_vqrshiftns:
9054    case Intrinsic::arm_neon_vqrshiftnu:
9055    case Intrinsic::arm_neon_vqrshiftnsu:
9056      // Narrowing shifts require an immediate right shift.
9057      if (isVShiftRImm(N->getOperand(2), VT, true, true, Cnt))
9058        break;
9059      llvm_unreachable("invalid shift count for narrowing vector shift "
9060                       "intrinsic");
9061
9062    default:
9063      llvm_unreachable("unhandled vector shift");
9064    }
9065
9066    switch (IntNo) {
9067    case Intrinsic::arm_neon_vshifts:
9068    case Intrinsic::arm_neon_vshiftu:
9069      // Opcode already set above.
9070      break;
9071    case Intrinsic::arm_neon_vrshifts:
9072      VShiftOpc = ARMISD::VRSHRs; break;
9073    case Intrinsic::arm_neon_vrshiftu:
9074      VShiftOpc = ARMISD::VRSHRu; break;
9075    case Intrinsic::arm_neon_vrshiftn:
9076      VShiftOpc = ARMISD::VRSHRN; break;
9077    case Intrinsic::arm_neon_vqshifts:
9078      VShiftOpc = ARMISD::VQSHLs; break;
9079    case Intrinsic::arm_neon_vqshiftu:
9080      VShiftOpc = ARMISD::VQSHLu; break;
9081    case Intrinsic::arm_neon_vqshiftsu:
9082      VShiftOpc = ARMISD::VQSHLsu; break;
9083    case Intrinsic::arm_neon_vqshiftns:
9084      VShiftOpc = ARMISD::VQSHRNs; break;
9085    case Intrinsic::arm_neon_vqshiftnu:
9086      VShiftOpc = ARMISD::VQSHRNu; break;
9087    case Intrinsic::arm_neon_vqshiftnsu:
9088      VShiftOpc = ARMISD::VQSHRNsu; break;
9089    case Intrinsic::arm_neon_vqrshiftns:
9090      VShiftOpc = ARMISD::VQRSHRNs; break;
9091    case Intrinsic::arm_neon_vqrshiftnu:
9092      VShiftOpc = ARMISD::VQRSHRNu; break;
9093    case Intrinsic::arm_neon_vqrshiftnsu:
9094      VShiftOpc = ARMISD::VQRSHRNsu; break;
9095    }
9096
9097    return DAG.getNode(VShiftOpc, SDLoc(N), N->getValueType(0),
9098                       N->getOperand(1), DAG.getConstant(Cnt, MVT::i32));
9099  }
9100
9101  case Intrinsic::arm_neon_vshiftins: {
9102    EVT VT = N->getOperand(1).getValueType();
9103    int64_t Cnt;
9104    unsigned VShiftOpc = 0;
9105
9106    if (isVShiftLImm(N->getOperand(3), VT, false, Cnt))
9107      VShiftOpc = ARMISD::VSLI;
9108    else if (isVShiftRImm(N->getOperand(3), VT, false, true, Cnt))
9109      VShiftOpc = ARMISD::VSRI;
9110    else {
9111      llvm_unreachable("invalid shift count for vsli/vsri intrinsic");
9112    }
9113
9114    return DAG.getNode(VShiftOpc, SDLoc(N), N->getValueType(0),
9115                       N->getOperand(1), N->getOperand(2),
9116                       DAG.getConstant(Cnt, MVT::i32));
9117  }
9118
9119  case Intrinsic::arm_neon_vqrshifts:
9120  case Intrinsic::arm_neon_vqrshiftu:
9121    // No immediate versions of these to check for.
9122    break;
9123  }
9124
9125  return SDValue();
9126}
9127
9128/// PerformShiftCombine - Checks for immediate versions of vector shifts and
9129/// lowers them.  As with the vector shift intrinsics, this is done during DAG
9130/// combining instead of DAG legalizing because the build_vectors for 64-bit
9131/// vector element shift counts are generally not legal, and it is hard to see
9132/// their values after they get legalized to loads from a constant pool.
9133static SDValue PerformShiftCombine(SDNode *N, SelectionDAG &DAG,
9134                                   const ARMSubtarget *ST) {
9135  EVT VT = N->getValueType(0);
9136  if (N->getOpcode() == ISD::SRL && VT == MVT::i32 && ST->hasV6Ops()) {
9137    // Canonicalize (srl (bswap x), 16) to (rotr (bswap x), 16) if the high
9138    // 16-bits of x is zero. This optimizes rev + lsr 16 to rev16.
9139    SDValue N1 = N->getOperand(1);
9140    if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(N1)) {
9141      SDValue N0 = N->getOperand(0);
9142      if (C->getZExtValue() == 16 && N0.getOpcode() == ISD::BSWAP &&
9143          DAG.MaskedValueIsZero(N0.getOperand(0),
9144                                APInt::getHighBitsSet(32, 16)))
9145        return DAG.getNode(ISD::ROTR, SDLoc(N), VT, N0, N1);
9146    }
9147  }
9148
9149  // Nothing to be done for scalar shifts.
9150  const TargetLowering &TLI = DAG.getTargetLoweringInfo();
9151  if (!VT.isVector() || !TLI.isTypeLegal(VT))
9152    return SDValue();
9153
9154  assert(ST->hasNEON() && "unexpected vector shift");
9155  int64_t Cnt;
9156
9157  switch (N->getOpcode()) {
9158  default: llvm_unreachable("unexpected shift opcode");
9159
9160  case ISD::SHL:
9161    if (isVShiftLImm(N->getOperand(1), VT, false, Cnt))
9162      return DAG.getNode(ARMISD::VSHL, SDLoc(N), VT, N->getOperand(0),
9163                         DAG.getConstant(Cnt, MVT::i32));
9164    break;
9165
9166  case ISD::SRA:
9167  case ISD::SRL:
9168    if (isVShiftRImm(N->getOperand(1), VT, false, false, Cnt)) {
9169      unsigned VShiftOpc = (N->getOpcode() == ISD::SRA ?
9170                            ARMISD::VSHRs : ARMISD::VSHRu);
9171      return DAG.getNode(VShiftOpc, SDLoc(N), VT, N->getOperand(0),
9172                         DAG.getConstant(Cnt, MVT::i32));
9173    }
9174  }
9175  return SDValue();
9176}
9177
9178/// PerformExtendCombine - Target-specific DAG combining for ISD::SIGN_EXTEND,
9179/// ISD::ZERO_EXTEND, and ISD::ANY_EXTEND.
9180static SDValue PerformExtendCombine(SDNode *N, SelectionDAG &DAG,
9181                                    const ARMSubtarget *ST) {
9182  SDValue N0 = N->getOperand(0);
9183
9184  // Check for sign- and zero-extensions of vector extract operations of 8-
9185  // and 16-bit vector elements.  NEON supports these directly.  They are
9186  // handled during DAG combining because type legalization will promote them
9187  // to 32-bit types and it is messy to recognize the operations after that.
9188  if (ST->hasNEON() && N0.getOpcode() == ISD::EXTRACT_VECTOR_ELT) {
9189    SDValue Vec = N0.getOperand(0);
9190    SDValue Lane = N0.getOperand(1);
9191    EVT VT = N->getValueType(0);
9192    EVT EltVT = N0.getValueType();
9193    const TargetLowering &TLI = DAG.getTargetLoweringInfo();
9194
9195    if (VT == MVT::i32 &&
9196        (EltVT == MVT::i8 || EltVT == MVT::i16) &&
9197        TLI.isTypeLegal(Vec.getValueType()) &&
9198        isa<ConstantSDNode>(Lane)) {
9199
9200      unsigned Opc = 0;
9201      switch (N->getOpcode()) {
9202      default: llvm_unreachable("unexpected opcode");
9203      case ISD::SIGN_EXTEND:
9204        Opc = ARMISD::VGETLANEs;
9205        break;
9206      case ISD::ZERO_EXTEND:
9207      case ISD::ANY_EXTEND:
9208        Opc = ARMISD::VGETLANEu;
9209        break;
9210      }
9211      return DAG.getNode(Opc, SDLoc(N), VT, Vec, Lane);
9212    }
9213  }
9214
9215  return SDValue();
9216}
9217
9218/// PerformSELECT_CCCombine - Target-specific DAG combining for ISD::SELECT_CC
9219/// to match f32 max/min patterns to use NEON vmax/vmin instructions.
9220static SDValue PerformSELECT_CCCombine(SDNode *N, SelectionDAG &DAG,
9221                                       const ARMSubtarget *ST) {
9222  // If the target supports NEON, try to use vmax/vmin instructions for f32
9223  // selects like "x < y ? x : y".  Unless the NoNaNsFPMath option is set,
9224  // be careful about NaNs:  NEON's vmax/vmin return NaN if either operand is
9225  // a NaN; only do the transformation when it matches that behavior.
9226
9227  // For now only do this when using NEON for FP operations; if using VFP, it
9228  // is not obvious that the benefit outweighs the cost of switching to the
9229  // NEON pipeline.
9230  if (!ST->hasNEON() || !ST->useNEONForSinglePrecisionFP() ||
9231      N->getValueType(0) != MVT::f32)
9232    return SDValue();
9233
9234  SDValue CondLHS = N->getOperand(0);
9235  SDValue CondRHS = N->getOperand(1);
9236  SDValue LHS = N->getOperand(2);
9237  SDValue RHS = N->getOperand(3);
9238  ISD::CondCode CC = cast<CondCodeSDNode>(N->getOperand(4))->get();
9239
9240  unsigned Opcode = 0;
9241  bool IsReversed;
9242  if (DAG.isEqualTo(LHS, CondLHS) && DAG.isEqualTo(RHS, CondRHS)) {
9243    IsReversed = false; // x CC y ? x : y
9244  } else if (DAG.isEqualTo(LHS, CondRHS) && DAG.isEqualTo(RHS, CondLHS)) {
9245    IsReversed = true ; // x CC y ? y : x
9246  } else {
9247    return SDValue();
9248  }
9249
9250  bool IsUnordered;
9251  switch (CC) {
9252  default: break;
9253  case ISD::SETOLT:
9254  case ISD::SETOLE:
9255  case ISD::SETLT:
9256  case ISD::SETLE:
9257  case ISD::SETULT:
9258  case ISD::SETULE:
9259    // If LHS is NaN, an ordered comparison will be false and the result will
9260    // be the RHS, but vmin(NaN, RHS) = NaN.  Avoid this by checking that LHS
9261    // != NaN.  Likewise, for unordered comparisons, check for RHS != NaN.
9262    IsUnordered = (CC == ISD::SETULT || CC == ISD::SETULE);
9263    if (!DAG.isKnownNeverNaN(IsUnordered ? RHS : LHS))
9264      break;
9265    // For less-than-or-equal comparisons, "+0 <= -0" will be true but vmin
9266    // will return -0, so vmin can only be used for unsafe math or if one of
9267    // the operands is known to be nonzero.
9268    if ((CC == ISD::SETLE || CC == ISD::SETOLE || CC == ISD::SETULE) &&
9269        !DAG.getTarget().Options.UnsafeFPMath &&
9270        !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS)))
9271      break;
9272    Opcode = IsReversed ? ARMISD::FMAX : ARMISD::FMIN;
9273    break;
9274
9275  case ISD::SETOGT:
9276  case ISD::SETOGE:
9277  case ISD::SETGT:
9278  case ISD::SETGE:
9279  case ISD::SETUGT:
9280  case ISD::SETUGE:
9281    // If LHS is NaN, an ordered comparison will be false and the result will
9282    // be the RHS, but vmax(NaN, RHS) = NaN.  Avoid this by checking that LHS
9283    // != NaN.  Likewise, for unordered comparisons, check for RHS != NaN.
9284    IsUnordered = (CC == ISD::SETUGT || CC == ISD::SETUGE);
9285    if (!DAG.isKnownNeverNaN(IsUnordered ? RHS : LHS))
9286      break;
9287    // For greater-than-or-equal comparisons, "-0 >= +0" will be true but vmax
9288    // will return +0, so vmax can only be used for unsafe math or if one of
9289    // the operands is known to be nonzero.
9290    if ((CC == ISD::SETGE || CC == ISD::SETOGE || CC == ISD::SETUGE) &&
9291        !DAG.getTarget().Options.UnsafeFPMath &&
9292        !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS)))
9293      break;
9294    Opcode = IsReversed ? ARMISD::FMIN : ARMISD::FMAX;
9295    break;
9296  }
9297
9298  if (!Opcode)
9299    return SDValue();
9300  return DAG.getNode(Opcode, SDLoc(N), N->getValueType(0), LHS, RHS);
9301}
9302
9303/// PerformCMOVCombine - Target-specific DAG combining for ARMISD::CMOV.
9304SDValue
9305ARMTargetLowering::PerformCMOVCombine(SDNode *N, SelectionDAG &DAG) const {
9306  SDValue Cmp = N->getOperand(4);
9307  if (Cmp.getOpcode() != ARMISD::CMPZ)
9308    // Only looking at EQ and NE cases.
9309    return SDValue();
9310
9311  EVT VT = N->getValueType(0);
9312  SDLoc dl(N);
9313  SDValue LHS = Cmp.getOperand(0);
9314  SDValue RHS = Cmp.getOperand(1);
9315  SDValue FalseVal = N->getOperand(0);
9316  SDValue TrueVal = N->getOperand(1);
9317  SDValue ARMcc = N->getOperand(2);
9318  ARMCC::CondCodes CC =
9319    (ARMCC::CondCodes)cast<ConstantSDNode>(ARMcc)->getZExtValue();
9320
9321  // Simplify
9322  //   mov     r1, r0
9323  //   cmp     r1, x
9324  //   mov     r0, y
9325  //   moveq   r0, x
9326  // to
9327  //   cmp     r0, x
9328  //   movne   r0, y
9329  //
9330  //   mov     r1, r0
9331  //   cmp     r1, x
9332  //   mov     r0, x
9333  //   movne   r0, y
9334  // to
9335  //   cmp     r0, x
9336  //   movne   r0, y
9337  /// FIXME: Turn this into a target neutral optimization?
9338  SDValue Res;
9339  if (CC == ARMCC::NE && FalseVal == RHS && FalseVal != LHS) {
9340    Res = DAG.getNode(ARMISD::CMOV, dl, VT, LHS, TrueVal, ARMcc,
9341                      N->getOperand(3), Cmp);
9342  } else if (CC == ARMCC::EQ && TrueVal == RHS) {
9343    SDValue ARMcc;
9344    SDValue NewCmp = getARMCmp(LHS, RHS, ISD::SETNE, ARMcc, DAG, dl);
9345    Res = DAG.getNode(ARMISD::CMOV, dl, VT, LHS, FalseVal, ARMcc,
9346                      N->getOperand(3), NewCmp);
9347  }
9348
9349  if (Res.getNode()) {
9350    APInt KnownZero, KnownOne;
9351    DAG.ComputeMaskedBits(SDValue(N,0), KnownZero, KnownOne);
9352    // Capture demanded bits information that would be otherwise lost.
9353    if (KnownZero == 0xfffffffe)
9354      Res = DAG.getNode(ISD::AssertZext, dl, MVT::i32, Res,
9355                        DAG.getValueType(MVT::i1));
9356    else if (KnownZero == 0xffffff00)
9357      Res = DAG.getNode(ISD::AssertZext, dl, MVT::i32, Res,
9358                        DAG.getValueType(MVT::i8));
9359    else if (KnownZero == 0xffff0000)
9360      Res = DAG.getNode(ISD::AssertZext, dl, MVT::i32, Res,
9361                        DAG.getValueType(MVT::i16));
9362  }
9363
9364  return Res;
9365}
9366
9367SDValue ARMTargetLowering::PerformDAGCombine(SDNode *N,
9368                                             DAGCombinerInfo &DCI) const {
9369  switch (N->getOpcode()) {
9370  default: break;
9371  case ISD::ADDC:       return PerformADDCCombine(N, DCI, Subtarget);
9372  case ISD::ADD:        return PerformADDCombine(N, DCI, Subtarget);
9373  case ISD::SUB:        return PerformSUBCombine(N, DCI);
9374  case ISD::MUL:        return PerformMULCombine(N, DCI, Subtarget);
9375  case ISD::OR:         return PerformORCombine(N, DCI, Subtarget);
9376  case ISD::XOR:        return PerformXORCombine(N, DCI, Subtarget);
9377  case ISD::AND:        return PerformANDCombine(N, DCI, Subtarget);
9378  case ARMISD::BFI:     return PerformBFICombine(N, DCI);
9379  case ARMISD::VMOVRRD: return PerformVMOVRRDCombine(N, DCI);
9380  case ARMISD::VMOVDRR: return PerformVMOVDRRCombine(N, DCI.DAG);
9381  case ISD::STORE:      return PerformSTORECombine(N, DCI);
9382  case ISD::BUILD_VECTOR: return PerformBUILD_VECTORCombine(N, DCI);
9383  case ISD::INSERT_VECTOR_ELT: return PerformInsertEltCombine(N, DCI);
9384  case ISD::VECTOR_SHUFFLE: return PerformVECTOR_SHUFFLECombine(N, DCI.DAG);
9385  case ARMISD::VDUPLANE: return PerformVDUPLANECombine(N, DCI);
9386  case ISD::FP_TO_SINT:
9387  case ISD::FP_TO_UINT: return PerformVCVTCombine(N, DCI, Subtarget);
9388  case ISD::FDIV:       return PerformVDIVCombine(N, DCI, Subtarget);
9389  case ISD::INTRINSIC_WO_CHAIN: return PerformIntrinsicCombine(N, DCI.DAG);
9390  case ISD::SHL:
9391  case ISD::SRA:
9392  case ISD::SRL:        return PerformShiftCombine(N, DCI.DAG, Subtarget);
9393  case ISD::SIGN_EXTEND:
9394  case ISD::ZERO_EXTEND:
9395  case ISD::ANY_EXTEND: return PerformExtendCombine(N, DCI.DAG, Subtarget);
9396  case ISD::SELECT_CC:  return PerformSELECT_CCCombine(N, DCI.DAG, Subtarget);
9397  case ARMISD::CMOV: return PerformCMOVCombine(N, DCI.DAG);
9398  case ARMISD::VLD2DUP:
9399  case ARMISD::VLD3DUP:
9400  case ARMISD::VLD4DUP:
9401    return CombineBaseUpdate(N, DCI);
9402  case ARMISD::BUILD_VECTOR:
9403    return PerformARMBUILD_VECTORCombine(N, DCI);
9404  case ISD::INTRINSIC_VOID:
9405  case ISD::INTRINSIC_W_CHAIN:
9406    switch (cast<ConstantSDNode>(N->getOperand(1))->getZExtValue()) {
9407    case Intrinsic::arm_neon_vld1:
9408    case Intrinsic::arm_neon_vld2:
9409    case Intrinsic::arm_neon_vld3:
9410    case Intrinsic::arm_neon_vld4:
9411    case Intrinsic::arm_neon_vld2lane:
9412    case Intrinsic::arm_neon_vld3lane:
9413    case Intrinsic::arm_neon_vld4lane:
9414    case Intrinsic::arm_neon_vst1:
9415    case Intrinsic::arm_neon_vst2:
9416    case Intrinsic::arm_neon_vst3:
9417    case Intrinsic::arm_neon_vst4:
9418    case Intrinsic::arm_neon_vst2lane:
9419    case Intrinsic::arm_neon_vst3lane:
9420    case Intrinsic::arm_neon_vst4lane:
9421      return CombineBaseUpdate(N, DCI);
9422    default: break;
9423    }
9424    break;
9425  }
9426  return SDValue();
9427}
9428
9429bool ARMTargetLowering::isDesirableToTransformToIntegerOp(unsigned Opc,
9430                                                          EVT VT) const {
9431  return (VT == MVT::f32) && (Opc == ISD::LOAD || Opc == ISD::STORE);
9432}
9433
9434bool ARMTargetLowering::allowsUnalignedMemoryAccesses(EVT VT, unsigned,
9435                                                      bool *Fast) const {
9436  // The AllowsUnaliged flag models the SCTLR.A setting in ARM cpus
9437  bool AllowsUnaligned = Subtarget->allowsUnalignedMem();
9438
9439  switch (VT.getSimpleVT().SimpleTy) {
9440  default:
9441    return false;
9442  case MVT::i8:
9443  case MVT::i16:
9444  case MVT::i32: {
9445    // Unaligned access can use (for example) LRDB, LRDH, LDR
9446    if (AllowsUnaligned) {
9447      if (Fast)
9448        *Fast = Subtarget->hasV7Ops();
9449      return true;
9450    }
9451    return false;
9452  }
9453  case MVT::f64:
9454  case MVT::v2f64: {
9455    // For any little-endian targets with neon, we can support unaligned ld/st
9456    // of D and Q (e.g. {D0,D1}) registers by using vld1.i8/vst1.i8.
9457    // A big-endian target may also explicitly support unaligned accesses
9458    if (Subtarget->hasNEON() && (AllowsUnaligned || isLittleEndian())) {
9459      if (Fast)
9460        *Fast = true;
9461      return true;
9462    }
9463    return false;
9464  }
9465  }
9466}
9467
9468static bool memOpAlign(unsigned DstAlign, unsigned SrcAlign,
9469                       unsigned AlignCheck) {
9470  return ((SrcAlign == 0 || SrcAlign % AlignCheck == 0) &&
9471          (DstAlign == 0 || DstAlign % AlignCheck == 0));
9472}
9473
9474EVT ARMTargetLowering::getOptimalMemOpType(uint64_t Size,
9475                                           unsigned DstAlign, unsigned SrcAlign,
9476                                           bool IsMemset, bool ZeroMemset,
9477                                           bool MemcpyStrSrc,
9478                                           MachineFunction &MF) const {
9479  const Function *F = MF.getFunction();
9480
9481  // See if we can use NEON instructions for this...
9482  if ((!IsMemset || ZeroMemset) &&
9483      Subtarget->hasNEON() &&
9484      !F->getAttributes().hasAttribute(AttributeSet::FunctionIndex,
9485                                       Attribute::NoImplicitFloat)) {
9486    bool Fast;
9487    if (Size >= 16 &&
9488        (memOpAlign(SrcAlign, DstAlign, 16) ||
9489         (allowsUnalignedMemoryAccesses(MVT::v2f64, 0, &Fast) && Fast))) {
9490      return MVT::v2f64;
9491    } else if (Size >= 8 &&
9492               (memOpAlign(SrcAlign, DstAlign, 8) ||
9493                (allowsUnalignedMemoryAccesses(MVT::f64, 0, &Fast) && Fast))) {
9494      return MVT::f64;
9495    }
9496  }
9497
9498  // Lowering to i32/i16 if the size permits.
9499  if (Size >= 4)
9500    return MVT::i32;
9501  else if (Size >= 2)
9502    return MVT::i16;
9503
9504  // Let the target-independent logic figure it out.
9505  return MVT::Other;
9506}
9507
9508bool ARMTargetLowering::isZExtFree(SDValue Val, EVT VT2) const {
9509  if (Val.getOpcode() != ISD::LOAD)
9510    return false;
9511
9512  EVT VT1 = Val.getValueType();
9513  if (!VT1.isSimple() || !VT1.isInteger() ||
9514      !VT2.isSimple() || !VT2.isInteger())
9515    return false;
9516
9517  switch (VT1.getSimpleVT().SimpleTy) {
9518  default: break;
9519  case MVT::i1:
9520  case MVT::i8:
9521  case MVT::i16:
9522    // 8-bit and 16-bit loads implicitly zero-extend to 32-bits.
9523    return true;
9524  }
9525
9526  return false;
9527}
9528
9529bool ARMTargetLowering::allowTruncateForTailCall(Type *Ty1, Type *Ty2) const {
9530  if (!Ty1->isIntegerTy() || !Ty2->isIntegerTy())
9531    return false;
9532
9533  if (!isTypeLegal(EVT::getEVT(Ty1)))
9534    return false;
9535
9536  assert(Ty1->getPrimitiveSizeInBits() <= 64 && "i128 is probably not a noop");
9537
9538  // Assuming the caller doesn't have a zeroext or signext return parameter,
9539  // truncation all the way down to i1 is valid.
9540  return true;
9541}
9542
9543
9544static bool isLegalT1AddressImmediate(int64_t V, EVT VT) {
9545  if (V < 0)
9546    return false;
9547
9548  unsigned Scale = 1;
9549  switch (VT.getSimpleVT().SimpleTy) {
9550  default: return false;
9551  case MVT::i1:
9552  case MVT::i8:
9553    // Scale == 1;
9554    break;
9555  case MVT::i16:
9556    // Scale == 2;
9557    Scale = 2;
9558    break;
9559  case MVT::i32:
9560    // Scale == 4;
9561    Scale = 4;
9562    break;
9563  }
9564
9565  if ((V & (Scale - 1)) != 0)
9566    return false;
9567  V /= Scale;
9568  return V == (V & ((1LL << 5) - 1));
9569}
9570
9571static bool isLegalT2AddressImmediate(int64_t V, EVT VT,
9572                                      const ARMSubtarget *Subtarget) {
9573  bool isNeg = false;
9574  if (V < 0) {
9575    isNeg = true;
9576    V = - V;
9577  }
9578
9579  switch (VT.getSimpleVT().SimpleTy) {
9580  default: return false;
9581  case MVT::i1:
9582  case MVT::i8:
9583  case MVT::i16:
9584  case MVT::i32:
9585    // + imm12 or - imm8
9586    if (isNeg)
9587      return V == (V & ((1LL << 8) - 1));
9588    return V == (V & ((1LL << 12) - 1));
9589  case MVT::f32:
9590  case MVT::f64:
9591    // Same as ARM mode. FIXME: NEON?
9592    if (!Subtarget->hasVFP2())
9593      return false;
9594    if ((V & 3) != 0)
9595      return false;
9596    V >>= 2;
9597    return V == (V & ((1LL << 8) - 1));
9598  }
9599}
9600
9601/// isLegalAddressImmediate - Return true if the integer value can be used
9602/// as the offset of the target addressing mode for load / store of the
9603/// given type.
9604static bool isLegalAddressImmediate(int64_t V, EVT VT,
9605                                    const ARMSubtarget *Subtarget) {
9606  if (V == 0)
9607    return true;
9608
9609  if (!VT.isSimple())
9610    return false;
9611
9612  if (Subtarget->isThumb1Only())
9613    return isLegalT1AddressImmediate(V, VT);
9614  else if (Subtarget->isThumb2())
9615    return isLegalT2AddressImmediate(V, VT, Subtarget);
9616
9617  // ARM mode.
9618  if (V < 0)
9619    V = - V;
9620  switch (VT.getSimpleVT().SimpleTy) {
9621  default: return false;
9622  case MVT::i1:
9623  case MVT::i8:
9624  case MVT::i32:
9625    // +- imm12
9626    return V == (V & ((1LL << 12) - 1));
9627  case MVT::i16:
9628    // +- imm8
9629    return V == (V & ((1LL << 8) - 1));
9630  case MVT::f32:
9631  case MVT::f64:
9632    if (!Subtarget->hasVFP2()) // FIXME: NEON?
9633      return false;
9634    if ((V & 3) != 0)
9635      return false;
9636    V >>= 2;
9637    return V == (V & ((1LL << 8) - 1));
9638  }
9639}
9640
9641bool ARMTargetLowering::isLegalT2ScaledAddressingMode(const AddrMode &AM,
9642                                                      EVT VT) const {
9643  int Scale = AM.Scale;
9644  if (Scale < 0)
9645    return false;
9646
9647  switch (VT.getSimpleVT().SimpleTy) {
9648  default: return false;
9649  case MVT::i1:
9650  case MVT::i8:
9651  case MVT::i16:
9652  case MVT::i32:
9653    if (Scale == 1)
9654      return true;
9655    // r + r << imm
9656    Scale = Scale & ~1;
9657    return Scale == 2 || Scale == 4 || Scale == 8;
9658  case MVT::i64:
9659    // r + r
9660    if (((unsigned)AM.HasBaseReg + Scale) <= 2)
9661      return true;
9662    return false;
9663  case MVT::isVoid:
9664    // Note, we allow "void" uses (basically, uses that aren't loads or
9665    // stores), because arm allows folding a scale into many arithmetic
9666    // operations.  This should be made more precise and revisited later.
9667
9668    // Allow r << imm, but the imm has to be a multiple of two.
9669    if (Scale & 1) return false;
9670    return isPowerOf2_32(Scale);
9671  }
9672}
9673
9674/// isLegalAddressingMode - Return true if the addressing mode represented
9675/// by AM is legal for this target, for a load/store of the specified type.
9676bool ARMTargetLowering::isLegalAddressingMode(const AddrMode &AM,
9677                                              Type *Ty) const {
9678  EVT VT = getValueType(Ty, true);
9679  if (!isLegalAddressImmediate(AM.BaseOffs, VT, Subtarget))
9680    return false;
9681
9682  // Can never fold addr of global into load/store.
9683  if (AM.BaseGV)
9684    return false;
9685
9686  switch (AM.Scale) {
9687  case 0:  // no scale reg, must be "r+i" or "r", or "i".
9688    break;
9689  case 1:
9690    if (Subtarget->isThumb1Only())
9691      return false;
9692    // FALL THROUGH.
9693  default:
9694    // ARM doesn't support any R+R*scale+imm addr modes.
9695    if (AM.BaseOffs)
9696      return false;
9697
9698    if (!VT.isSimple())
9699      return false;
9700
9701    if (Subtarget->isThumb2())
9702      return isLegalT2ScaledAddressingMode(AM, VT);
9703
9704    int Scale = AM.Scale;
9705    switch (VT.getSimpleVT().SimpleTy) {
9706    default: return false;
9707    case MVT::i1:
9708    case MVT::i8:
9709    case MVT::i32:
9710      if (Scale < 0) Scale = -Scale;
9711      if (Scale == 1)
9712        return true;
9713      // r + r << imm
9714      return isPowerOf2_32(Scale & ~1);
9715    case MVT::i16:
9716    case MVT::i64:
9717      // r + r
9718      if (((unsigned)AM.HasBaseReg + Scale) <= 2)
9719        return true;
9720      return false;
9721
9722    case MVT::isVoid:
9723      // Note, we allow "void" uses (basically, uses that aren't loads or
9724      // stores), because arm allows folding a scale into many arithmetic
9725      // operations.  This should be made more precise and revisited later.
9726
9727      // Allow r << imm, but the imm has to be a multiple of two.
9728      if (Scale & 1) return false;
9729      return isPowerOf2_32(Scale);
9730    }
9731  }
9732  return true;
9733}
9734
9735/// isLegalICmpImmediate - Return true if the specified immediate is legal
9736/// icmp immediate, that is the target has icmp instructions which can compare
9737/// a register against the immediate without having to materialize the
9738/// immediate into a register.
9739bool ARMTargetLowering::isLegalICmpImmediate(int64_t Imm) const {
9740  // Thumb2 and ARM modes can use cmn for negative immediates.
9741  if (!Subtarget->isThumb())
9742    return ARM_AM::getSOImmVal(llvm::abs64(Imm)) != -1;
9743  if (Subtarget->isThumb2())
9744    return ARM_AM::getT2SOImmVal(llvm::abs64(Imm)) != -1;
9745  // Thumb1 doesn't have cmn, and only 8-bit immediates.
9746  return Imm >= 0 && Imm <= 255;
9747}
9748
9749/// isLegalAddImmediate - Return true if the specified immediate is a legal add
9750/// *or sub* immediate, that is the target has add or sub instructions which can
9751/// add a register with the immediate without having to materialize the
9752/// immediate into a register.
9753bool ARMTargetLowering::isLegalAddImmediate(int64_t Imm) const {
9754  // Same encoding for add/sub, just flip the sign.
9755  int64_t AbsImm = llvm::abs64(Imm);
9756  if (!Subtarget->isThumb())
9757    return ARM_AM::getSOImmVal(AbsImm) != -1;
9758  if (Subtarget->isThumb2())
9759    return ARM_AM::getT2SOImmVal(AbsImm) != -1;
9760  // Thumb1 only has 8-bit unsigned immediate.
9761  return AbsImm >= 0 && AbsImm <= 255;
9762}
9763
9764static bool getARMIndexedAddressParts(SDNode *Ptr, EVT VT,
9765                                      bool isSEXTLoad, SDValue &Base,
9766                                      SDValue &Offset, bool &isInc,
9767                                      SelectionDAG &DAG) {
9768  if (Ptr->getOpcode() != ISD::ADD && Ptr->getOpcode() != ISD::SUB)
9769    return false;
9770
9771  if (VT == MVT::i16 || ((VT == MVT::i8 || VT == MVT::i1) && isSEXTLoad)) {
9772    // AddressingMode 3
9773    Base = Ptr->getOperand(0);
9774    if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(Ptr->getOperand(1))) {
9775      int RHSC = (int)RHS->getZExtValue();
9776      if (RHSC < 0 && RHSC > -256) {
9777        assert(Ptr->getOpcode() == ISD::ADD);
9778        isInc = false;
9779        Offset = DAG.getConstant(-RHSC, RHS->getValueType(0));
9780        return true;
9781      }
9782    }
9783    isInc = (Ptr->getOpcode() == ISD::ADD);
9784    Offset = Ptr->getOperand(1);
9785    return true;
9786  } else if (VT == MVT::i32 || VT == MVT::i8 || VT == MVT::i1) {
9787    // AddressingMode 2
9788    if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(Ptr->getOperand(1))) {
9789      int RHSC = (int)RHS->getZExtValue();
9790      if (RHSC < 0 && RHSC > -0x1000) {
9791        assert(Ptr->getOpcode() == ISD::ADD);
9792        isInc = false;
9793        Offset = DAG.getConstant(-RHSC, RHS->getValueType(0));
9794        Base = Ptr->getOperand(0);
9795        return true;
9796      }
9797    }
9798
9799    if (Ptr->getOpcode() == ISD::ADD) {
9800      isInc = true;
9801      ARM_AM::ShiftOpc ShOpcVal=
9802        ARM_AM::getShiftOpcForNode(Ptr->getOperand(0).getOpcode());
9803      if (ShOpcVal != ARM_AM::no_shift) {
9804        Base = Ptr->getOperand(1);
9805        Offset = Ptr->getOperand(0);
9806      } else {
9807        Base = Ptr->getOperand(0);
9808        Offset = Ptr->getOperand(1);
9809      }
9810      return true;
9811    }
9812
9813    isInc = (Ptr->getOpcode() == ISD::ADD);
9814    Base = Ptr->getOperand(0);
9815    Offset = Ptr->getOperand(1);
9816    return true;
9817  }
9818
9819  // FIXME: Use VLDM / VSTM to emulate indexed FP load / store.
9820  return false;
9821}
9822
9823static bool getT2IndexedAddressParts(SDNode *Ptr, EVT VT,
9824                                     bool isSEXTLoad, SDValue &Base,
9825                                     SDValue &Offset, bool &isInc,
9826                                     SelectionDAG &DAG) {
9827  if (Ptr->getOpcode() != ISD::ADD && Ptr->getOpcode() != ISD::SUB)
9828    return false;
9829
9830  Base = Ptr->getOperand(0);
9831  if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(Ptr->getOperand(1))) {
9832    int RHSC = (int)RHS->getZExtValue();
9833    if (RHSC < 0 && RHSC > -0x100) { // 8 bits.
9834      assert(Ptr->getOpcode() == ISD::ADD);
9835      isInc = false;
9836      Offset = DAG.getConstant(-RHSC, RHS->getValueType(0));
9837      return true;
9838    } else if (RHSC > 0 && RHSC < 0x100) { // 8 bit, no zero.
9839      isInc = Ptr->getOpcode() == ISD::ADD;
9840      Offset = DAG.getConstant(RHSC, RHS->getValueType(0));
9841      return true;
9842    }
9843  }
9844
9845  return false;
9846}
9847
9848/// getPreIndexedAddressParts - returns true by value, base pointer and
9849/// offset pointer and addressing mode by reference if the node's address
9850/// can be legally represented as pre-indexed load / store address.
9851bool
9852ARMTargetLowering::getPreIndexedAddressParts(SDNode *N, SDValue &Base,
9853                                             SDValue &Offset,
9854                                             ISD::MemIndexedMode &AM,
9855                                             SelectionDAG &DAG) const {
9856  if (Subtarget->isThumb1Only())
9857    return false;
9858
9859  EVT VT;
9860  SDValue Ptr;
9861  bool isSEXTLoad = false;
9862  if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) {
9863    Ptr = LD->getBasePtr();
9864    VT  = LD->getMemoryVT();
9865    isSEXTLoad = LD->getExtensionType() == ISD::SEXTLOAD;
9866  } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) {
9867    Ptr = ST->getBasePtr();
9868    VT  = ST->getMemoryVT();
9869  } else
9870    return false;
9871
9872  bool isInc;
9873  bool isLegal = false;
9874  if (Subtarget->isThumb2())
9875    isLegal = getT2IndexedAddressParts(Ptr.getNode(), VT, isSEXTLoad, Base,
9876                                       Offset, isInc, DAG);
9877  else
9878    isLegal = getARMIndexedAddressParts(Ptr.getNode(), VT, isSEXTLoad, Base,
9879                                        Offset, isInc, DAG);
9880  if (!isLegal)
9881    return false;
9882
9883  AM = isInc ? ISD::PRE_INC : ISD::PRE_DEC;
9884  return true;
9885}
9886
9887/// getPostIndexedAddressParts - returns true by value, base pointer and
9888/// offset pointer and addressing mode by reference if this node can be
9889/// combined with a load / store to form a post-indexed load / store.
9890bool ARMTargetLowering::getPostIndexedAddressParts(SDNode *N, SDNode *Op,
9891                                                   SDValue &Base,
9892                                                   SDValue &Offset,
9893                                                   ISD::MemIndexedMode &AM,
9894                                                   SelectionDAG &DAG) const {
9895  if (Subtarget->isThumb1Only())
9896    return false;
9897
9898  EVT VT;
9899  SDValue Ptr;
9900  bool isSEXTLoad = false;
9901  if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) {
9902    VT  = LD->getMemoryVT();
9903    Ptr = LD->getBasePtr();
9904    isSEXTLoad = LD->getExtensionType() == ISD::SEXTLOAD;
9905  } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) {
9906    VT  = ST->getMemoryVT();
9907    Ptr = ST->getBasePtr();
9908  } else
9909    return false;
9910
9911  bool isInc;
9912  bool isLegal = false;
9913  if (Subtarget->isThumb2())
9914    isLegal = getT2IndexedAddressParts(Op, VT, isSEXTLoad, Base, Offset,
9915                                       isInc, DAG);
9916  else
9917    isLegal = getARMIndexedAddressParts(Op, VT, isSEXTLoad, Base, Offset,
9918                                        isInc, DAG);
9919  if (!isLegal)
9920    return false;
9921
9922  if (Ptr != Base) {
9923    // Swap base ptr and offset to catch more post-index load / store when
9924    // it's legal. In Thumb2 mode, offset must be an immediate.
9925    if (Ptr == Offset && Op->getOpcode() == ISD::ADD &&
9926        !Subtarget->isThumb2())
9927      std::swap(Base, Offset);
9928
9929    // Post-indexed load / store update the base pointer.
9930    if (Ptr != Base)
9931      return false;
9932  }
9933
9934  AM = isInc ? ISD::POST_INC : ISD::POST_DEC;
9935  return true;
9936}
9937
9938void ARMTargetLowering::computeMaskedBitsForTargetNode(const SDValue Op,
9939                                                       APInt &KnownZero,
9940                                                       APInt &KnownOne,
9941                                                       const SelectionDAG &DAG,
9942                                                       unsigned Depth) const {
9943  unsigned BitWidth = KnownOne.getBitWidth();
9944  KnownZero = KnownOne = APInt(BitWidth, 0);
9945  switch (Op.getOpcode()) {
9946  default: break;
9947  case ARMISD::ADDC:
9948  case ARMISD::ADDE:
9949  case ARMISD::SUBC:
9950  case ARMISD::SUBE:
9951    // These nodes' second result is a boolean
9952    if (Op.getResNo() == 0)
9953      break;
9954    KnownZero |= APInt::getHighBitsSet(BitWidth, BitWidth - 1);
9955    break;
9956  case ARMISD::CMOV: {
9957    // Bits are known zero/one if known on the LHS and RHS.
9958    DAG.ComputeMaskedBits(Op.getOperand(0), KnownZero, KnownOne, Depth+1);
9959    if (KnownZero == 0 && KnownOne == 0) return;
9960
9961    APInt KnownZeroRHS, KnownOneRHS;
9962    DAG.ComputeMaskedBits(Op.getOperand(1), KnownZeroRHS, KnownOneRHS, Depth+1);
9963    KnownZero &= KnownZeroRHS;
9964    KnownOne  &= KnownOneRHS;
9965    return;
9966  }
9967  case ISD::INTRINSIC_W_CHAIN: {
9968    ConstantSDNode *CN = cast<ConstantSDNode>(Op->getOperand(1));
9969    Intrinsic::ID IntID = static_cast<Intrinsic::ID>(CN->getZExtValue());
9970    switch (IntID) {
9971    default: return;
9972    case Intrinsic::arm_ldaex:
9973    case Intrinsic::arm_ldrex: {
9974      EVT VT = cast<MemIntrinsicSDNode>(Op)->getMemoryVT();
9975      unsigned MemBits = VT.getScalarType().getSizeInBits();
9976      KnownZero |= APInt::getHighBitsSet(BitWidth, BitWidth - MemBits);
9977      return;
9978    }
9979    }
9980  }
9981  }
9982}
9983
9984//===----------------------------------------------------------------------===//
9985//                           ARM Inline Assembly Support
9986//===----------------------------------------------------------------------===//
9987
9988bool ARMTargetLowering::ExpandInlineAsm(CallInst *CI) const {
9989  // Looking for "rev" which is V6+.
9990  if (!Subtarget->hasV6Ops())
9991    return false;
9992
9993  InlineAsm *IA = cast<InlineAsm>(CI->getCalledValue());
9994  std::string AsmStr = IA->getAsmString();
9995  SmallVector<StringRef, 4> AsmPieces;
9996  SplitString(AsmStr, AsmPieces, ";\n");
9997
9998  switch (AsmPieces.size()) {
9999  default: return false;
10000  case 1:
10001    AsmStr = AsmPieces[0];
10002    AsmPieces.clear();
10003    SplitString(AsmStr, AsmPieces, " \t,");
10004
10005    // rev $0, $1
10006    if (AsmPieces.size() == 3 &&
10007        AsmPieces[0] == "rev" && AsmPieces[1] == "$0" && AsmPieces[2] == "$1" &&
10008        IA->getConstraintString().compare(0, 4, "=l,l") == 0) {
10009      IntegerType *Ty = dyn_cast<IntegerType>(CI->getType());
10010      if (Ty && Ty->getBitWidth() == 32)
10011        return IntrinsicLowering::LowerToByteSwap(CI);
10012    }
10013    break;
10014  }
10015
10016  return false;
10017}
10018
10019/// getConstraintType - Given a constraint letter, return the type of
10020/// constraint it is for this target.
10021ARMTargetLowering::ConstraintType
10022ARMTargetLowering::getConstraintType(const std::string &Constraint) const {
10023  if (Constraint.size() == 1) {
10024    switch (Constraint[0]) {
10025    default:  break;
10026    case 'l': return C_RegisterClass;
10027    case 'w': return C_RegisterClass;
10028    case 'h': return C_RegisterClass;
10029    case 'x': return C_RegisterClass;
10030    case 't': return C_RegisterClass;
10031    case 'j': return C_Other; // Constant for movw.
10032      // An address with a single base register. Due to the way we
10033      // currently handle addresses it is the same as an 'r' memory constraint.
10034    case 'Q': return C_Memory;
10035    }
10036  } else if (Constraint.size() == 2) {
10037    switch (Constraint[0]) {
10038    default: break;
10039    // All 'U+' constraints are addresses.
10040    case 'U': return C_Memory;
10041    }
10042  }
10043  return TargetLowering::getConstraintType(Constraint);
10044}
10045
10046/// Examine constraint type and operand type and determine a weight value.
10047/// This object must already have been set up with the operand type
10048/// and the current alternative constraint selected.
10049TargetLowering::ConstraintWeight
10050ARMTargetLowering::getSingleConstraintMatchWeight(
10051    AsmOperandInfo &info, const char *constraint) const {
10052  ConstraintWeight weight = CW_Invalid;
10053  Value *CallOperandVal = info.CallOperandVal;
10054    // If we don't have a value, we can't do a match,
10055    // but allow it at the lowest weight.
10056  if (CallOperandVal == NULL)
10057    return CW_Default;
10058  Type *type = CallOperandVal->getType();
10059  // Look at the constraint type.
10060  switch (*constraint) {
10061  default:
10062    weight = TargetLowering::getSingleConstraintMatchWeight(info, constraint);
10063    break;
10064  case 'l':
10065    if (type->isIntegerTy()) {
10066      if (Subtarget->isThumb())
10067        weight = CW_SpecificReg;
10068      else
10069        weight = CW_Register;
10070    }
10071    break;
10072  case 'w':
10073    if (type->isFloatingPointTy())
10074      weight = CW_Register;
10075    break;
10076  }
10077  return weight;
10078}
10079
10080typedef std::pair<unsigned, const TargetRegisterClass*> RCPair;
10081RCPair
10082ARMTargetLowering::getRegForInlineAsmConstraint(const std::string &Constraint,
10083                                                MVT VT) const {
10084  if (Constraint.size() == 1) {
10085    // GCC ARM Constraint Letters
10086    switch (Constraint[0]) {
10087    case 'l': // Low regs or general regs.
10088      if (Subtarget->isThumb())
10089        return RCPair(0U, &ARM::tGPRRegClass);
10090      return RCPair(0U, &ARM::GPRRegClass);
10091    case 'h': // High regs or no regs.
10092      if (Subtarget->isThumb())
10093        return RCPair(0U, &ARM::hGPRRegClass);
10094      break;
10095    case 'r':
10096      return RCPair(0U, &ARM::GPRRegClass);
10097    case 'w':
10098      if (VT == MVT::Other)
10099        break;
10100      if (VT == MVT::f32)
10101        return RCPair(0U, &ARM::SPRRegClass);
10102      if (VT.getSizeInBits() == 64)
10103        return RCPair(0U, &ARM::DPRRegClass);
10104      if (VT.getSizeInBits() == 128)
10105        return RCPair(0U, &ARM::QPRRegClass);
10106      break;
10107    case 'x':
10108      if (VT == MVT::Other)
10109        break;
10110      if (VT == MVT::f32)
10111        return RCPair(0U, &ARM::SPR_8RegClass);
10112      if (VT.getSizeInBits() == 64)
10113        return RCPair(0U, &ARM::DPR_8RegClass);
10114      if (VT.getSizeInBits() == 128)
10115        return RCPair(0U, &ARM::QPR_8RegClass);
10116      break;
10117    case 't':
10118      if (VT == MVT::f32)
10119        return RCPair(0U, &ARM::SPRRegClass);
10120      break;
10121    }
10122  }
10123  if (StringRef("{cc}").equals_lower(Constraint))
10124    return std::make_pair(unsigned(ARM::CPSR), &ARM::CCRRegClass);
10125
10126  return TargetLowering::getRegForInlineAsmConstraint(Constraint, VT);
10127}
10128
10129/// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
10130/// vector.  If it is invalid, don't add anything to Ops.
10131void ARMTargetLowering::LowerAsmOperandForConstraint(SDValue Op,
10132                                                     std::string &Constraint,
10133                                                     std::vector<SDValue>&Ops,
10134                                                     SelectionDAG &DAG) const {
10135  SDValue Result(0, 0);
10136
10137  // Currently only support length 1 constraints.
10138  if (Constraint.length() != 1) return;
10139
10140  char ConstraintLetter = Constraint[0];
10141  switch (ConstraintLetter) {
10142  default: break;
10143  case 'j':
10144  case 'I': case 'J': case 'K': case 'L':
10145  case 'M': case 'N': case 'O':
10146    ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op);
10147    if (!C)
10148      return;
10149
10150    int64_t CVal64 = C->getSExtValue();
10151    int CVal = (int) CVal64;
10152    // None of these constraints allow values larger than 32 bits.  Check
10153    // that the value fits in an int.
10154    if (CVal != CVal64)
10155      return;
10156
10157    switch (ConstraintLetter) {
10158      case 'j':
10159        // Constant suitable for movw, must be between 0 and
10160        // 65535.
10161        if (Subtarget->hasV6T2Ops())
10162          if (CVal >= 0 && CVal <= 65535)
10163            break;
10164        return;
10165      case 'I':
10166        if (Subtarget->isThumb1Only()) {
10167          // This must be a constant between 0 and 255, for ADD
10168          // immediates.
10169          if (CVal >= 0 && CVal <= 255)
10170            break;
10171        } else if (Subtarget->isThumb2()) {
10172          // A constant that can be used as an immediate value in a
10173          // data-processing instruction.
10174          if (ARM_AM::getT2SOImmVal(CVal) != -1)
10175            break;
10176        } else {
10177          // A constant that can be used as an immediate value in a
10178          // data-processing instruction.
10179          if (ARM_AM::getSOImmVal(CVal) != -1)
10180            break;
10181        }
10182        return;
10183
10184      case 'J':
10185        if (Subtarget->isThumb()) {  // FIXME thumb2
10186          // This must be a constant between -255 and -1, for negated ADD
10187          // immediates. This can be used in GCC with an "n" modifier that
10188          // prints the negated value, for use with SUB instructions. It is
10189          // not useful otherwise but is implemented for compatibility.
10190          if (CVal >= -255 && CVal <= -1)
10191            break;
10192        } else {
10193          // This must be a constant between -4095 and 4095. It is not clear
10194          // what this constraint is intended for. Implemented for
10195          // compatibility with GCC.
10196          if (CVal >= -4095 && CVal <= 4095)
10197            break;
10198        }
10199        return;
10200
10201      case 'K':
10202        if (Subtarget->isThumb1Only()) {
10203          // A 32-bit value where only one byte has a nonzero value. Exclude
10204          // zero to match GCC. This constraint is used by GCC internally for
10205          // constants that can be loaded with a move/shift combination.
10206          // It is not useful otherwise but is implemented for compatibility.
10207          if (CVal != 0 && ARM_AM::isThumbImmShiftedVal(CVal))
10208            break;
10209        } else if (Subtarget->isThumb2()) {
10210          // A constant whose bitwise inverse can be used as an immediate
10211          // value in a data-processing instruction. This can be used in GCC
10212          // with a "B" modifier that prints the inverted value, for use with
10213          // BIC and MVN instructions. It is not useful otherwise but is
10214          // implemented for compatibility.
10215          if (ARM_AM::getT2SOImmVal(~CVal) != -1)
10216            break;
10217        } else {
10218          // A constant whose bitwise inverse can be used as an immediate
10219          // value in a data-processing instruction. This can be used in GCC
10220          // with a "B" modifier that prints the inverted value, for use with
10221          // BIC and MVN instructions. It is not useful otherwise but is
10222          // implemented for compatibility.
10223          if (ARM_AM::getSOImmVal(~CVal) != -1)
10224            break;
10225        }
10226        return;
10227
10228      case 'L':
10229        if (Subtarget->isThumb1Only()) {
10230          // This must be a constant between -7 and 7,
10231          // for 3-operand ADD/SUB immediate instructions.
10232          if (CVal >= -7 && CVal < 7)
10233            break;
10234        } else if (Subtarget->isThumb2()) {
10235          // A constant whose negation can be used as an immediate value in a
10236          // data-processing instruction. This can be used in GCC with an "n"
10237          // modifier that prints the negated value, for use with SUB
10238          // instructions. It is not useful otherwise but is implemented for
10239          // compatibility.
10240          if (ARM_AM::getT2SOImmVal(-CVal) != -1)
10241            break;
10242        } else {
10243          // A constant whose negation can be used as an immediate value in a
10244          // data-processing instruction. This can be used in GCC with an "n"
10245          // modifier that prints the negated value, for use with SUB
10246          // instructions. It is not useful otherwise but is implemented for
10247          // compatibility.
10248          if (ARM_AM::getSOImmVal(-CVal) != -1)
10249            break;
10250        }
10251        return;
10252
10253      case 'M':
10254        if (Subtarget->isThumb()) { // FIXME thumb2
10255          // This must be a multiple of 4 between 0 and 1020, for
10256          // ADD sp + immediate.
10257          if ((CVal >= 0 && CVal <= 1020) && ((CVal & 3) == 0))
10258            break;
10259        } else {
10260          // A power of two or a constant between 0 and 32.  This is used in
10261          // GCC for the shift amount on shifted register operands, but it is
10262          // useful in general for any shift amounts.
10263          if ((CVal >= 0 && CVal <= 32) || ((CVal & (CVal - 1)) == 0))
10264            break;
10265        }
10266        return;
10267
10268      case 'N':
10269        if (Subtarget->isThumb()) {  // FIXME thumb2
10270          // This must be a constant between 0 and 31, for shift amounts.
10271          if (CVal >= 0 && CVal <= 31)
10272            break;
10273        }
10274        return;
10275
10276      case 'O':
10277        if (Subtarget->isThumb()) {  // FIXME thumb2
10278          // This must be a multiple of 4 between -508 and 508, for
10279          // ADD/SUB sp = sp + immediate.
10280          if ((CVal >= -508 && CVal <= 508) && ((CVal & 3) == 0))
10281            break;
10282        }
10283        return;
10284    }
10285    Result = DAG.getTargetConstant(CVal, Op.getValueType());
10286    break;
10287  }
10288
10289  if (Result.getNode()) {
10290    Ops.push_back(Result);
10291    return;
10292  }
10293  return TargetLowering::LowerAsmOperandForConstraint(Op, Constraint, Ops, DAG);
10294}
10295
10296SDValue ARMTargetLowering::LowerDivRem(SDValue Op, SelectionDAG &DAG) const {
10297  assert(Subtarget->isTargetAEABI() && "Register-based DivRem lowering only");
10298  unsigned Opcode = Op->getOpcode();
10299  assert((Opcode == ISD::SDIVREM || Opcode == ISD::UDIVREM) &&
10300      "Invalid opcode for Div/Rem lowering");
10301  bool isSigned = (Opcode == ISD::SDIVREM);
10302  EVT VT = Op->getValueType(0);
10303  Type *Ty = VT.getTypeForEVT(*DAG.getContext());
10304
10305  RTLIB::Libcall LC;
10306  switch (VT.getSimpleVT().SimpleTy) {
10307  default: llvm_unreachable("Unexpected request for libcall!");
10308  case MVT::i8:   LC= isSigned ? RTLIB::SDIVREM_I8  : RTLIB::UDIVREM_I8;  break;
10309  case MVT::i16:  LC= isSigned ? RTLIB::SDIVREM_I16 : RTLIB::UDIVREM_I16; break;
10310  case MVT::i32:  LC= isSigned ? RTLIB::SDIVREM_I32 : RTLIB::UDIVREM_I32; break;
10311  case MVT::i64:  LC= isSigned ? RTLIB::SDIVREM_I64 : RTLIB::UDIVREM_I64; break;
10312  }
10313
10314  SDValue InChain = DAG.getEntryNode();
10315
10316  TargetLowering::ArgListTy Args;
10317  TargetLowering::ArgListEntry Entry;
10318  for (unsigned i = 0, e = Op->getNumOperands(); i != e; ++i) {
10319    EVT ArgVT = Op->getOperand(i).getValueType();
10320    Type *ArgTy = ArgVT.getTypeForEVT(*DAG.getContext());
10321    Entry.Node = Op->getOperand(i);
10322    Entry.Ty = ArgTy;
10323    Entry.isSExt = isSigned;
10324    Entry.isZExt = !isSigned;
10325    Args.push_back(Entry);
10326  }
10327
10328  SDValue Callee = DAG.getExternalSymbol(getLibcallName(LC),
10329                                         getPointerTy());
10330
10331  Type *RetTy = (Type*)StructType::get(Ty, Ty, NULL);
10332
10333  SDLoc dl(Op);
10334  TargetLowering::
10335  CallLoweringInfo CLI(InChain, RetTy, isSigned, !isSigned, false, true,
10336                    0, getLibcallCallingConv(LC), /*isTailCall=*/false,
10337                    /*doesNotReturn=*/false, /*isReturnValueUsed=*/true,
10338                    Callee, Args, DAG, dl);
10339  std::pair<SDValue, SDValue> CallInfo = LowerCallTo(CLI);
10340
10341  return CallInfo.first;
10342}
10343
10344bool
10345ARMTargetLowering::isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const {
10346  // The ARM target isn't yet aware of offsets.
10347  return false;
10348}
10349
10350bool ARM::isBitFieldInvertedMask(unsigned v) {
10351  if (v == 0xffffffff)
10352    return false;
10353
10354  // there can be 1's on either or both "outsides", all the "inside"
10355  // bits must be 0's
10356  unsigned TO = CountTrailingOnes_32(v);
10357  unsigned LO = CountLeadingOnes_32(v);
10358  v = (v >> TO) << TO;
10359  v = (v << LO) >> LO;
10360  return v == 0;
10361}
10362
10363/// isFPImmLegal - Returns true if the target can instruction select the
10364/// specified FP immediate natively. If false, the legalizer will
10365/// materialize the FP immediate as a load from a constant pool.
10366bool ARMTargetLowering::isFPImmLegal(const APFloat &Imm, EVT VT) const {
10367  if (!Subtarget->hasVFP3())
10368    return false;
10369  if (VT == MVT::f32)
10370    return ARM_AM::getFP32Imm(Imm) != -1;
10371  if (VT == MVT::f64)
10372    return ARM_AM::getFP64Imm(Imm) != -1;
10373  return false;
10374}
10375
10376/// getTgtMemIntrinsic - Represent NEON load and store intrinsics as
10377/// MemIntrinsicNodes.  The associated MachineMemOperands record the alignment
10378/// specified in the intrinsic calls.
10379bool ARMTargetLowering::getTgtMemIntrinsic(IntrinsicInfo &Info,
10380                                           const CallInst &I,
10381                                           unsigned Intrinsic) const {
10382  switch (Intrinsic) {
10383  case Intrinsic::arm_neon_vld1:
10384  case Intrinsic::arm_neon_vld2:
10385  case Intrinsic::arm_neon_vld3:
10386  case Intrinsic::arm_neon_vld4:
10387  case Intrinsic::arm_neon_vld2lane:
10388  case Intrinsic::arm_neon_vld3lane:
10389  case Intrinsic::arm_neon_vld4lane: {
10390    Info.opc = ISD::INTRINSIC_W_CHAIN;
10391    // Conservatively set memVT to the entire set of vectors loaded.
10392    uint64_t NumElts = getDataLayout()->getTypeAllocSize(I.getType()) / 8;
10393    Info.memVT = EVT::getVectorVT(I.getType()->getContext(), MVT::i64, NumElts);
10394    Info.ptrVal = I.getArgOperand(0);
10395    Info.offset = 0;
10396    Value *AlignArg = I.getArgOperand(I.getNumArgOperands() - 1);
10397    Info.align = cast<ConstantInt>(AlignArg)->getZExtValue();
10398    Info.vol = false; // volatile loads with NEON intrinsics not supported
10399    Info.readMem = true;
10400    Info.writeMem = false;
10401    return true;
10402  }
10403  case Intrinsic::arm_neon_vst1:
10404  case Intrinsic::arm_neon_vst2:
10405  case Intrinsic::arm_neon_vst3:
10406  case Intrinsic::arm_neon_vst4:
10407  case Intrinsic::arm_neon_vst2lane:
10408  case Intrinsic::arm_neon_vst3lane:
10409  case Intrinsic::arm_neon_vst4lane: {
10410    Info.opc = ISD::INTRINSIC_VOID;
10411    // Conservatively set memVT to the entire set of vectors stored.
10412    unsigned NumElts = 0;
10413    for (unsigned ArgI = 1, ArgE = I.getNumArgOperands(); ArgI < ArgE; ++ArgI) {
10414      Type *ArgTy = I.getArgOperand(ArgI)->getType();
10415      if (!ArgTy->isVectorTy())
10416        break;
10417      NumElts += getDataLayout()->getTypeAllocSize(ArgTy) / 8;
10418    }
10419    Info.memVT = EVT::getVectorVT(I.getType()->getContext(), MVT::i64, NumElts);
10420    Info.ptrVal = I.getArgOperand(0);
10421    Info.offset = 0;
10422    Value *AlignArg = I.getArgOperand(I.getNumArgOperands() - 1);
10423    Info.align = cast<ConstantInt>(AlignArg)->getZExtValue();
10424    Info.vol = false; // volatile stores with NEON intrinsics not supported
10425    Info.readMem = false;
10426    Info.writeMem = true;
10427    return true;
10428  }
10429  case Intrinsic::arm_ldaex:
10430  case Intrinsic::arm_ldrex: {
10431    PointerType *PtrTy = cast<PointerType>(I.getArgOperand(0)->getType());
10432    Info.opc = ISD::INTRINSIC_W_CHAIN;
10433    Info.memVT = MVT::getVT(PtrTy->getElementType());
10434    Info.ptrVal = I.getArgOperand(0);
10435    Info.offset = 0;
10436    Info.align = getDataLayout()->getABITypeAlignment(PtrTy->getElementType());
10437    Info.vol = true;
10438    Info.readMem = true;
10439    Info.writeMem = false;
10440    return true;
10441  }
10442  case Intrinsic::arm_stlex:
10443  case Intrinsic::arm_strex: {
10444    PointerType *PtrTy = cast<PointerType>(I.getArgOperand(1)->getType());
10445    Info.opc = ISD::INTRINSIC_W_CHAIN;
10446    Info.memVT = MVT::getVT(PtrTy->getElementType());
10447    Info.ptrVal = I.getArgOperand(1);
10448    Info.offset = 0;
10449    Info.align = getDataLayout()->getABITypeAlignment(PtrTy->getElementType());
10450    Info.vol = true;
10451    Info.readMem = false;
10452    Info.writeMem = true;
10453    return true;
10454  }
10455  case Intrinsic::arm_stlexd:
10456  case Intrinsic::arm_strexd: {
10457    Info.opc = ISD::INTRINSIC_W_CHAIN;
10458    Info.memVT = MVT::i64;
10459    Info.ptrVal = I.getArgOperand(2);
10460    Info.offset = 0;
10461    Info.align = 8;
10462    Info.vol = true;
10463    Info.readMem = false;
10464    Info.writeMem = true;
10465    return true;
10466  }
10467  case Intrinsic::arm_ldaexd:
10468  case Intrinsic::arm_ldrexd: {
10469    Info.opc = ISD::INTRINSIC_W_CHAIN;
10470    Info.memVT = MVT::i64;
10471    Info.ptrVal = I.getArgOperand(0);
10472    Info.offset = 0;
10473    Info.align = 8;
10474    Info.vol = true;
10475    Info.readMem = true;
10476    Info.writeMem = false;
10477    return true;
10478  }
10479  default:
10480    break;
10481  }
10482
10483  return false;
10484}
10485
10486/// \brief Returns true if it is beneficial to convert a load of a constant
10487/// to just the constant itself.
10488bool ARMTargetLowering::shouldConvertConstantLoadToIntImm(const APInt &Imm,
10489                                                          Type *Ty) const {
10490  assert(Ty->isIntegerTy());
10491
10492  unsigned Bits = Ty->getPrimitiveSizeInBits();
10493  if (Bits == 0 || Bits > 32)
10494    return false;
10495  return true;
10496}
10497