ARMISelLowering.cpp revision 97c9bb5cc6c2f936493ae5e8f577ecbfc1f750ce
1//===-- ARMISelLowering.cpp - ARM DAG Lowering Implementation -------------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file was developed by Evan Cheng and is distributed under 6// the University of Illinois Open Source License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file defines the interfaces that ARM uses to lower LLVM code into a 11// selection DAG. 12// 13//===----------------------------------------------------------------------===// 14 15#include "ARM.h" 16#include "ARMAddressingModes.h" 17#include "ARMConstantPoolValue.h" 18#include "ARMISelLowering.h" 19#include "ARMMachineFunctionInfo.h" 20#include "ARMRegisterInfo.h" 21#include "ARMSubtarget.h" 22#include "ARMTargetMachine.h" 23#include "llvm/CallingConv.h" 24#include "llvm/Constants.h" 25#include "llvm/Instruction.h" 26#include "llvm/CodeGen/MachineBasicBlock.h" 27#include "llvm/CodeGen/MachineFrameInfo.h" 28#include "llvm/CodeGen/MachineFunction.h" 29#include "llvm/CodeGen/MachineInstrBuilder.h" 30#include "llvm/CodeGen/SelectionDAG.h" 31#include "llvm/CodeGen/SSARegMap.h" 32#include "llvm/Target/TargetOptions.h" 33#include "llvm/ADT/VectorExtras.h" 34#include "llvm/Support/MathExtras.h" 35using namespace llvm; 36 37ARMTargetLowering::ARMTargetLowering(TargetMachine &TM) 38 : TargetLowering(TM), ARMPCLabelIndex(0) { 39 Subtarget = &TM.getSubtarget<ARMSubtarget>(); 40 41 if (Subtarget->isTargetDarwin()) { 42 // Don't have these. 43 setLibcallName(RTLIB::UINTTOFP_I64_F32, NULL); 44 setLibcallName(RTLIB::UINTTOFP_I64_F64, NULL); 45 46 // Uses VFP for Thumb libfuncs if available. 47 if (Subtarget->isThumb() && Subtarget->hasVFP2()) { 48 // Single-precision floating-point arithmetic. 49 setLibcallName(RTLIB::ADD_F32, "__addsf3vfp"); 50 setLibcallName(RTLIB::SUB_F32, "__subsf3vfp"); 51 setLibcallName(RTLIB::MUL_F32, "__mulsf3vfp"); 52 setLibcallName(RTLIB::DIV_F32, "__divsf3vfp"); 53 54 // Double-precision floating-point arithmetic. 55 setLibcallName(RTLIB::ADD_F64, "__adddf3vfp"); 56 setLibcallName(RTLIB::SUB_F64, "__subdf3vfp"); 57 setLibcallName(RTLIB::MUL_F64, "__muldf3vfp"); 58 setLibcallName(RTLIB::DIV_F64, "__divdf3vfp"); 59 60 // Single-precision comparisons. 61 setLibcallName(RTLIB::OEQ_F32, "__eqsf2vfp"); 62 setLibcallName(RTLIB::UNE_F32, "__nesf2vfp"); 63 setLibcallName(RTLIB::OLT_F32, "__ltsf2vfp"); 64 setLibcallName(RTLIB::OLE_F32, "__lesf2vfp"); 65 setLibcallName(RTLIB::OGE_F32, "__gesf2vfp"); 66 setLibcallName(RTLIB::OGT_F32, "__gtsf2vfp"); 67 setLibcallName(RTLIB::UO_F32, "__unordsf2vfp"); 68 setLibcallName(RTLIB::O_F32, "__unordsf2vfp"); 69 70 setCmpLibcallCC(RTLIB::OEQ_F32, ISD::SETNE); 71 setCmpLibcallCC(RTLIB::UNE_F32, ISD::SETNE); 72 setCmpLibcallCC(RTLIB::OLT_F32, ISD::SETNE); 73 setCmpLibcallCC(RTLIB::OLE_F32, ISD::SETNE); 74 setCmpLibcallCC(RTLIB::OGE_F32, ISD::SETNE); 75 setCmpLibcallCC(RTLIB::OGT_F32, ISD::SETNE); 76 setCmpLibcallCC(RTLIB::UO_F32, ISD::SETNE); 77 setCmpLibcallCC(RTLIB::O_F32, ISD::SETEQ); 78 79 // Double-precision comparisons. 80 setLibcallName(RTLIB::OEQ_F64, "__eqdf2vfp"); 81 setLibcallName(RTLIB::UNE_F64, "__nedf2vfp"); 82 setLibcallName(RTLIB::OLT_F64, "__ltdf2vfp"); 83 setLibcallName(RTLIB::OLE_F64, "__ledf2vfp"); 84 setLibcallName(RTLIB::OGE_F64, "__gedf2vfp"); 85 setLibcallName(RTLIB::OGT_F64, "__gtdf2vfp"); 86 setLibcallName(RTLIB::UO_F64, "__unorddf2vfp"); 87 setLibcallName(RTLIB::O_F64, "__unorddf2vfp"); 88 89 setCmpLibcallCC(RTLIB::OEQ_F64, ISD::SETNE); 90 setCmpLibcallCC(RTLIB::UNE_F64, ISD::SETNE); 91 setCmpLibcallCC(RTLIB::OLT_F64, ISD::SETNE); 92 setCmpLibcallCC(RTLIB::OLE_F64, ISD::SETNE); 93 setCmpLibcallCC(RTLIB::OGE_F64, ISD::SETNE); 94 setCmpLibcallCC(RTLIB::OGT_F64, ISD::SETNE); 95 setCmpLibcallCC(RTLIB::UO_F64, ISD::SETNE); 96 setCmpLibcallCC(RTLIB::O_F64, ISD::SETEQ); 97 98 // Floating-point to integer conversions. 99 // i64 conversions are done via library routines even when generating VFP 100 // instructions, so use the same ones. 101 setLibcallName(RTLIB::FPTOSINT_F64_I32, "__fixdfsivfp"); 102 setLibcallName(RTLIB::FPTOUINT_F64_I32, "__fixunsdfsivfp"); 103 setLibcallName(RTLIB::FPTOSINT_F32_I32, "__fixsfsivfp"); 104 setLibcallName(RTLIB::FPTOUINT_F32_I32, "__fixunssfsivfp"); 105 106 // Conversions between floating types. 107 setLibcallName(RTLIB::FPROUND_F64_F32, "__truncdfsf2vfp"); 108 setLibcallName(RTLIB::FPEXT_F32_F64, "__extendsfdf2vfp"); 109 110 // Integer to floating-point conversions. 111 // i64 conversions are done via library routines even when generating VFP 112 // instructions, so use the same ones. 113 // FIXME: There appears to be some naming inconsistency in ARM libgcc: e.g. 114 // __floatunsidf vs. __floatunssidfvfp. 115 setLibcallName(RTLIB::SINTTOFP_I32_F64, "__floatsidfvfp"); 116 setLibcallName(RTLIB::UINTTOFP_I32_F64, "__floatunssidfvfp"); 117 setLibcallName(RTLIB::SINTTOFP_I32_F32, "__floatsisfvfp"); 118 setLibcallName(RTLIB::UINTTOFP_I32_F32, "__floatunssisfvfp"); 119 } 120 } 121 122 addRegisterClass(MVT::i32, ARM::GPRRegisterClass); 123 if (!UseSoftFloat && Subtarget->hasVFP2() && !Subtarget->isThumb()) { 124 addRegisterClass(MVT::f32, ARM::SPRRegisterClass); 125 addRegisterClass(MVT::f64, ARM::DPRRegisterClass); 126 } 127 128 // ARM does not have f32 extending load. 129 setLoadXAction(ISD::EXTLOAD, MVT::f32, Expand); 130 131 // ARM supports all 4 flavors of integer indexed load / store. 132 for (unsigned im = (unsigned)ISD::PRE_INC; 133 im != (unsigned)ISD::LAST_INDEXED_MODE; ++im) { 134 setIndexedLoadAction(im, MVT::i1, Legal); 135 setIndexedLoadAction(im, MVT::i8, Legal); 136 setIndexedLoadAction(im, MVT::i16, Legal); 137 setIndexedLoadAction(im, MVT::i32, Legal); 138 setIndexedStoreAction(im, MVT::i1, Legal); 139 setIndexedStoreAction(im, MVT::i8, Legal); 140 setIndexedStoreAction(im, MVT::i16, Legal); 141 setIndexedStoreAction(im, MVT::i32, Legal); 142 } 143 144 // i64 operation support. 145 if (Subtarget->isThumb()) { 146 setOperationAction(ISD::MUL, MVT::i64, Expand); 147 setOperationAction(ISD::MULHU, MVT::i32, Expand); 148 setOperationAction(ISD::MULHS, MVT::i32, Expand); 149 } else { 150 setOperationAction(ISD::MUL, MVT::i64, Custom); 151 setOperationAction(ISD::MULHU, MVT::i32, Custom); 152 if (!Subtarget->hasV6Ops()) 153 setOperationAction(ISD::MULHS, MVT::i32, Custom); 154 } 155 setOperationAction(ISD::SHL_PARTS, MVT::i32, Expand); 156 setOperationAction(ISD::SRA_PARTS, MVT::i32, Expand); 157 setOperationAction(ISD::SRL_PARTS, MVT::i32, Expand); 158 setOperationAction(ISD::SRL, MVT::i64, Custom); 159 setOperationAction(ISD::SRA, MVT::i64, Custom); 160 161 // ARM does not have ROTL. 162 setOperationAction(ISD::ROTL, MVT::i32, Expand); 163 setOperationAction(ISD::CTTZ , MVT::i32, Expand); 164 setOperationAction(ISD::CTPOP, MVT::i32, Expand); 165 if (!Subtarget->hasV5TOps() || Subtarget->isThumb()) 166 setOperationAction(ISD::CTLZ, MVT::i32, Expand); 167 168 // Only ARMv6 has BSWAP. 169 if (!Subtarget->hasV6Ops()) 170 setOperationAction(ISD::BSWAP, MVT::i32, Expand); 171 172 // These are expanded into libcalls. 173 setOperationAction(ISD::SDIV, MVT::i32, Expand); 174 setOperationAction(ISD::UDIV, MVT::i32, Expand); 175 setOperationAction(ISD::SREM, MVT::i32, Expand); 176 setOperationAction(ISD::UREM, MVT::i32, Expand); 177 178 // Support label based line numbers. 179 setOperationAction(ISD::LOCATION, MVT::Other, Expand); 180 setOperationAction(ISD::DEBUG_LOC, MVT::Other, Expand); 181 182 setOperationAction(ISD::RET, MVT::Other, Custom); 183 setOperationAction(ISD::GlobalAddress, MVT::i32, Custom); 184 setOperationAction(ISD::ConstantPool, MVT::i32, Custom); 185 setOperationAction(ISD::GLOBAL_OFFSET_TABLE, MVT::i32, Custom); 186 setOperationAction(ISD::GlobalTLSAddress, MVT::i32, Custom); 187 188 // Expand mem operations genericly. 189 setOperationAction(ISD::MEMSET , MVT::Other, Expand); 190 setOperationAction(ISD::MEMCPY , MVT::Other, Expand); 191 setOperationAction(ISD::MEMMOVE , MVT::Other, Expand); 192 193 // Use the default implementation. 194 setOperationAction(ISD::VASTART , MVT::Other, Expand); 195 setOperationAction(ISD::VAARG , MVT::Other, Expand); 196 setOperationAction(ISD::VACOPY , MVT::Other, Expand); 197 setOperationAction(ISD::VAEND , MVT::Other, Expand); 198 setOperationAction(ISD::STACKSAVE, MVT::Other, Expand); 199 setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand); 200 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32 , Expand); 201 202 if (!Subtarget->hasV6Ops()) { 203 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16, Expand); 204 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8, Expand); 205 } 206 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand); 207 208 if (!UseSoftFloat && Subtarget->hasVFP2() && !Subtarget->isThumb()) 209 // Turn f64->i64 into FMRRD iff target supports vfp2. 210 setOperationAction(ISD::BIT_CONVERT, MVT::i64, Custom); 211 212 setOperationAction(ISD::SETCC , MVT::i32, Expand); 213 setOperationAction(ISD::SETCC , MVT::f32, Expand); 214 setOperationAction(ISD::SETCC , MVT::f64, Expand); 215 setOperationAction(ISD::SELECT , MVT::i32, Expand); 216 setOperationAction(ISD::SELECT , MVT::f32, Expand); 217 setOperationAction(ISD::SELECT , MVT::f64, Expand); 218 setOperationAction(ISD::SELECT_CC, MVT::i32, Custom); 219 setOperationAction(ISD::SELECT_CC, MVT::f32, Custom); 220 setOperationAction(ISD::SELECT_CC, MVT::f64, Custom); 221 222 setOperationAction(ISD::BRCOND , MVT::Other, Expand); 223 setOperationAction(ISD::BR_CC , MVT::i32, Custom); 224 setOperationAction(ISD::BR_CC , MVT::f32, Custom); 225 setOperationAction(ISD::BR_CC , MVT::f64, Custom); 226 setOperationAction(ISD::BR_JT , MVT::Other, Custom); 227 228 setOperationAction(ISD::VASTART, MVT::Other, Custom); 229 setOperationAction(ISD::VACOPY, MVT::Other, Expand); 230 setOperationAction(ISD::VAEND, MVT::Other, Expand); 231 setOperationAction(ISD::STACKSAVE, MVT::Other, Expand); 232 setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand); 233 234 // FP Constants can't be immediates. 235 setOperationAction(ISD::ConstantFP, MVT::f64, Expand); 236 setOperationAction(ISD::ConstantFP, MVT::f32, Expand); 237 238 // We don't support sin/cos/fmod/copysign 239 setOperationAction(ISD::FSIN , MVT::f64, Expand); 240 setOperationAction(ISD::FSIN , MVT::f32, Expand); 241 setOperationAction(ISD::FCOS , MVT::f32, Expand); 242 setOperationAction(ISD::FCOS , MVT::f64, Expand); 243 setOperationAction(ISD::FREM , MVT::f64, Expand); 244 setOperationAction(ISD::FREM , MVT::f32, Expand); 245 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Custom); 246 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom); 247 248 // int <-> fp are custom expanded into bit_convert + ARMISD ops. 249 setOperationAction(ISD::SINT_TO_FP, MVT::i32, Custom); 250 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Custom); 251 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Custom); 252 setOperationAction(ISD::FP_TO_SINT, MVT::i32, Custom); 253 254 setStackPointerRegisterToSaveRestore(ARM::SP); 255 256 setSchedulingPreference(SchedulingForRegPressure); 257 computeRegisterProperties(); 258} 259 260 261const char *ARMTargetLowering::getTargetNodeName(unsigned Opcode) const { 262 switch (Opcode) { 263 default: return 0; 264 case ARMISD::Wrapper: return "ARMISD::Wrapper"; 265 case ARMISD::WrapperJT: return "ARMISD::WrapperJT"; 266 case ARMISD::CALL: return "ARMISD::CALL"; 267 case ARMISD::CALL_NOLINK: return "ARMISD::CALL_NOLINK"; 268 case ARMISD::tCALL: return "ARMISD::tCALL"; 269 case ARMISD::BRCOND: return "ARMISD::BRCOND"; 270 case ARMISD::BR_JT: return "ARMISD::BR_JT"; 271 case ARMISD::RET_FLAG: return "ARMISD::RET_FLAG"; 272 case ARMISD::PIC_ADD: return "ARMISD::PIC_ADD"; 273 case ARMISD::CMP: return "ARMISD::CMP"; 274 case ARMISD::CMPNZ: return "ARMISD::CMPNZ"; 275 case ARMISD::CMPFP: return "ARMISD::CMPFP"; 276 case ARMISD::CMPFPw0: return "ARMISD::CMPFPw0"; 277 case ARMISD::FMSTAT: return "ARMISD::FMSTAT"; 278 case ARMISD::CMOV: return "ARMISD::CMOV"; 279 case ARMISD::CNEG: return "ARMISD::CNEG"; 280 281 case ARMISD::FTOSI: return "ARMISD::FTOSI"; 282 case ARMISD::FTOUI: return "ARMISD::FTOUI"; 283 case ARMISD::SITOF: return "ARMISD::SITOF"; 284 case ARMISD::UITOF: return "ARMISD::UITOF"; 285 case ARMISD::MULHILOU: return "ARMISD::MULHILOU"; 286 case ARMISD::MULHILOS: return "ARMISD::MULHILOS"; 287 288 case ARMISD::SRL_FLAG: return "ARMISD::SRL_FLAG"; 289 case ARMISD::SRA_FLAG: return "ARMISD::SRA_FLAG"; 290 case ARMISD::RRX: return "ARMISD::RRX"; 291 292 case ARMISD::FMRRD: return "ARMISD::FMRRD"; 293 case ARMISD::FMDRR: return "ARMISD::FMDRR"; 294 295 case ARMISD::THREAD_POINTER:return "ARMISD::THREAD_POINTER"; 296 } 297} 298 299//===----------------------------------------------------------------------===// 300// Lowering Code 301//===----------------------------------------------------------------------===// 302 303 304/// IntCCToARMCC - Convert a DAG integer condition code to an ARM CC 305static ARMCC::CondCodes IntCCToARMCC(ISD::CondCode CC) { 306 switch (CC) { 307 default: assert(0 && "Unknown condition code!"); 308 case ISD::SETNE: return ARMCC::NE; 309 case ISD::SETEQ: return ARMCC::EQ; 310 case ISD::SETGT: return ARMCC::GT; 311 case ISD::SETGE: return ARMCC::GE; 312 case ISD::SETLT: return ARMCC::LT; 313 case ISD::SETLE: return ARMCC::LE; 314 case ISD::SETUGT: return ARMCC::HI; 315 case ISD::SETUGE: return ARMCC::HS; 316 case ISD::SETULT: return ARMCC::LO; 317 case ISD::SETULE: return ARMCC::LS; 318 } 319} 320 321/// FPCCToARMCC - Convert a DAG fp condition code to an ARM CC. It 322/// returns true if the operands should be inverted to form the proper 323/// comparison. 324static bool FPCCToARMCC(ISD::CondCode CC, ARMCC::CondCodes &CondCode, 325 ARMCC::CondCodes &CondCode2) { 326 bool Invert = false; 327 CondCode2 = ARMCC::AL; 328 switch (CC) { 329 default: assert(0 && "Unknown FP condition!"); 330 case ISD::SETEQ: 331 case ISD::SETOEQ: CondCode = ARMCC::EQ; break; 332 case ISD::SETGT: 333 case ISD::SETOGT: CondCode = ARMCC::GT; break; 334 case ISD::SETGE: 335 case ISD::SETOGE: CondCode = ARMCC::GE; break; 336 case ISD::SETOLT: CondCode = ARMCC::MI; break; 337 case ISD::SETOLE: CondCode = ARMCC::GT; Invert = true; break; 338 case ISD::SETONE: CondCode = ARMCC::MI; CondCode2 = ARMCC::GT; break; 339 case ISD::SETO: CondCode = ARMCC::VC; break; 340 case ISD::SETUO: CondCode = ARMCC::VS; break; 341 case ISD::SETUEQ: CondCode = ARMCC::EQ; CondCode2 = ARMCC::VS; break; 342 case ISD::SETUGT: CondCode = ARMCC::HI; break; 343 case ISD::SETUGE: CondCode = ARMCC::PL; break; 344 case ISD::SETLT: 345 case ISD::SETULT: CondCode = ARMCC::LT; break; 346 case ISD::SETLE: 347 case ISD::SETULE: CondCode = ARMCC::LE; break; 348 case ISD::SETNE: 349 case ISD::SETUNE: CondCode = ARMCC::NE; break; 350 } 351 return Invert; 352} 353 354static void 355HowToPassArgument(MVT::ValueType ObjectVT, unsigned NumGPRs, 356 unsigned StackOffset, unsigned &NeededGPRs, 357 unsigned &NeededStackSize, unsigned &GPRPad, 358 unsigned &StackPad, unsigned Flags) { 359 NeededStackSize = 0; 360 NeededGPRs = 0; 361 StackPad = 0; 362 GPRPad = 0; 363 unsigned align = (Flags >> ISD::ParamFlags::OrigAlignmentOffs); 364 GPRPad = NumGPRs % ((align + 3)/4); 365 StackPad = StackOffset % align; 366 unsigned firstGPR = NumGPRs + GPRPad; 367 switch (ObjectVT) { 368 default: assert(0 && "Unhandled argument type!"); 369 case MVT::i32: 370 case MVT::f32: 371 if (firstGPR < 4) 372 NeededGPRs = 1; 373 else 374 NeededStackSize = 4; 375 break; 376 case MVT::i64: 377 case MVT::f64: 378 if (firstGPR < 3) 379 NeededGPRs = 2; 380 else if (firstGPR == 3) { 381 NeededGPRs = 1; 382 NeededStackSize = 4; 383 } else 384 NeededStackSize = 8; 385 } 386} 387 388/// LowerCALL - Lowering a ISD::CALL node into a callseq_start <- 389/// ARMISD:CALL <- callseq_end chain. Also add input and output parameter 390/// nodes. 391SDOperand ARMTargetLowering::LowerCALL(SDOperand Op, SelectionDAG &DAG) { 392 MVT::ValueType RetVT= Op.Val->getValueType(0); 393 SDOperand Chain = Op.getOperand(0); 394 unsigned CallConv = cast<ConstantSDNode>(Op.getOperand(1))->getValue(); 395 assert((CallConv == CallingConv::C || 396 CallConv == CallingConv::Fast) && "unknown calling convention"); 397 SDOperand Callee = Op.getOperand(4); 398 unsigned NumOps = (Op.getNumOperands() - 5) / 2; 399 unsigned ArgOffset = 0; // Frame mechanisms handle retaddr slot 400 unsigned NumGPRs = 0; // GPRs used for parameter passing. 401 402 // Count how many bytes are to be pushed on the stack. 403 unsigned NumBytes = 0; 404 405 // Add up all the space actually used. 406 for (unsigned i = 0; i < NumOps; ++i) { 407 unsigned ObjSize; 408 unsigned ObjGPRs; 409 unsigned StackPad; 410 unsigned GPRPad; 411 MVT::ValueType ObjectVT = Op.getOperand(5+2*i).getValueType(); 412 unsigned Flags = Op.getConstantOperandVal(5+2*i+1); 413 HowToPassArgument(ObjectVT, NumGPRs, NumBytes, ObjGPRs, ObjSize, 414 GPRPad, StackPad, Flags); 415 NumBytes += ObjSize + StackPad; 416 NumGPRs += ObjGPRs + GPRPad; 417 } 418 419 // Adjust the stack pointer for the new arguments... 420 // These operations are automatically eliminated by the prolog/epilog pass 421 Chain = DAG.getCALLSEQ_START(Chain, 422 DAG.getConstant(NumBytes, MVT::i32)); 423 424 SDOperand StackPtr = DAG.getRegister(ARM::SP, MVT::i32); 425 426 static const unsigned GPRArgRegs[] = { 427 ARM::R0, ARM::R1, ARM::R2, ARM::R3 428 }; 429 430 NumGPRs = 0; 431 std::vector<std::pair<unsigned, SDOperand> > RegsToPass; 432 std::vector<SDOperand> MemOpChains; 433 for (unsigned i = 0; i != NumOps; ++i) { 434 SDOperand Arg = Op.getOperand(5+2*i); 435 unsigned Flags = Op.getConstantOperandVal(5+2*i+1); 436 MVT::ValueType ArgVT = Arg.getValueType(); 437 438 unsigned ObjSize; 439 unsigned ObjGPRs; 440 unsigned GPRPad; 441 unsigned StackPad; 442 HowToPassArgument(ArgVT, NumGPRs, ArgOffset, ObjGPRs, 443 ObjSize, GPRPad, StackPad, Flags); 444 NumGPRs += GPRPad; 445 ArgOffset += StackPad; 446 if (ObjGPRs > 0) { 447 switch (ArgVT) { 448 default: assert(0 && "Unexpected ValueType for argument!"); 449 case MVT::i32: 450 RegsToPass.push_back(std::make_pair(GPRArgRegs[NumGPRs], Arg)); 451 break; 452 case MVT::f32: 453 RegsToPass.push_back(std::make_pair(GPRArgRegs[NumGPRs], 454 DAG.getNode(ISD::BIT_CONVERT, MVT::i32, Arg))); 455 break; 456 case MVT::i64: { 457 SDOperand Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32, Arg, 458 DAG.getConstant(0, getPointerTy())); 459 SDOperand Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32, Arg, 460 DAG.getConstant(1, getPointerTy())); 461 RegsToPass.push_back(std::make_pair(GPRArgRegs[NumGPRs], Lo)); 462 if (ObjGPRs == 2) 463 RegsToPass.push_back(std::make_pair(GPRArgRegs[NumGPRs+1], Hi)); 464 else { 465 SDOperand PtrOff= DAG.getConstant(ArgOffset, StackPtr.getValueType()); 466 PtrOff = DAG.getNode(ISD::ADD, MVT::i32, StackPtr, PtrOff); 467 MemOpChains.push_back(DAG.getStore(Chain, Hi, PtrOff, NULL, 0)); 468 } 469 break; 470 } 471 case MVT::f64: { 472 SDOperand Cvt = DAG.getNode(ARMISD::FMRRD, 473 DAG.getVTList(MVT::i32, MVT::i32), 474 &Arg, 1); 475 RegsToPass.push_back(std::make_pair(GPRArgRegs[NumGPRs], Cvt)); 476 if (ObjGPRs == 2) 477 RegsToPass.push_back(std::make_pair(GPRArgRegs[NumGPRs+1], 478 Cvt.getValue(1))); 479 else { 480 SDOperand PtrOff= DAG.getConstant(ArgOffset, StackPtr.getValueType()); 481 PtrOff = DAG.getNode(ISD::ADD, MVT::i32, StackPtr, PtrOff); 482 MemOpChains.push_back(DAG.getStore(Chain, Cvt.getValue(1), PtrOff, 483 NULL, 0)); 484 } 485 break; 486 } 487 } 488 } else { 489 assert(ObjSize != 0); 490 SDOperand PtrOff = DAG.getConstant(ArgOffset, StackPtr.getValueType()); 491 PtrOff = DAG.getNode(ISD::ADD, MVT::i32, StackPtr, PtrOff); 492 MemOpChains.push_back(DAG.getStore(Chain, Arg, PtrOff, NULL, 0)); 493 } 494 495 NumGPRs += ObjGPRs; 496 ArgOffset += ObjSize; 497 } 498 499 if (!MemOpChains.empty()) 500 Chain = DAG.getNode(ISD::TokenFactor, MVT::Other, 501 &MemOpChains[0], MemOpChains.size()); 502 503 // Build a sequence of copy-to-reg nodes chained together with token chain 504 // and flag operands which copy the outgoing args into the appropriate regs. 505 SDOperand InFlag; 506 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) { 507 Chain = DAG.getCopyToReg(Chain, RegsToPass[i].first, RegsToPass[i].second, 508 InFlag); 509 InFlag = Chain.getValue(1); 510 } 511 512 // If the callee is a GlobalAddress/ExternalSymbol node (quite common, every 513 // direct call is) turn it into a TargetGlobalAddress/TargetExternalSymbol 514 // node so that legalize doesn't hack it. 515 bool isDirect = false; 516 bool isARMFunc = false; 517 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) { 518 GlobalValue *GV = G->getGlobal(); 519 isDirect = true; 520 bool isExt = (GV->isDeclaration() || GV->hasWeakLinkage() || 521 GV->hasLinkOnceLinkage()); 522 bool isStub = (isExt && Subtarget->isTargetDarwin()) && 523 getTargetMachine().getRelocationModel() != Reloc::Static; 524 isARMFunc = !Subtarget->isThumb() || isStub; 525 // tBX takes a register source operand. 526 if (isARMFunc && Subtarget->isThumb() && !Subtarget->hasV5TOps()) { 527 ARMConstantPoolValue *CPV = new ARMConstantPoolValue(GV, ARMPCLabelIndex, 528 ARMCP::CPStub, 4); 529 SDOperand CPAddr = DAG.getTargetConstantPool(CPV, getPointerTy(), 2); 530 CPAddr = DAG.getNode(ARMISD::Wrapper, MVT::i32, CPAddr); 531 Callee = DAG.getLoad(getPointerTy(), DAG.getEntryNode(), CPAddr, NULL, 0); 532 SDOperand PICLabel = DAG.getConstant(ARMPCLabelIndex++, MVT::i32); 533 Callee = DAG.getNode(ARMISD::PIC_ADD, getPointerTy(), Callee, PICLabel); 534 } else 535 Callee = DAG.getTargetGlobalAddress(GV, getPointerTy()); 536 } else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee)) { 537 isDirect = true; 538 bool isStub = Subtarget->isTargetDarwin() && 539 getTargetMachine().getRelocationModel() != Reloc::Static; 540 isARMFunc = !Subtarget->isThumb() || isStub; 541 // tBX takes a register source operand. 542 const char *Sym = S->getSymbol(); 543 if (isARMFunc && Subtarget->isThumb() && !Subtarget->hasV5TOps()) { 544 ARMConstantPoolValue *CPV = new ARMConstantPoolValue(Sym, ARMPCLabelIndex, 545 ARMCP::CPStub, 4); 546 SDOperand CPAddr = DAG.getTargetConstantPool(CPV, getPointerTy(), 2); 547 CPAddr = DAG.getNode(ARMISD::Wrapper, MVT::i32, CPAddr); 548 Callee = DAG.getLoad(getPointerTy(), DAG.getEntryNode(), CPAddr, NULL, 0); 549 SDOperand PICLabel = DAG.getConstant(ARMPCLabelIndex++, MVT::i32); 550 Callee = DAG.getNode(ARMISD::PIC_ADD, getPointerTy(), Callee, PICLabel); 551 } else 552 Callee = DAG.getTargetExternalSymbol(Sym, getPointerTy()); 553 } 554 555 // FIXME: handle tail calls differently. 556 unsigned CallOpc; 557 if (Subtarget->isThumb()) { 558 if (!Subtarget->hasV5TOps() && (!isDirect || isARMFunc)) 559 CallOpc = ARMISD::CALL_NOLINK; 560 else 561 CallOpc = isARMFunc ? ARMISD::CALL : ARMISD::tCALL; 562 } else { 563 CallOpc = (isDirect || Subtarget->hasV5TOps()) 564 ? ARMISD::CALL : ARMISD::CALL_NOLINK; 565 } 566 if (CallOpc == ARMISD::CALL_NOLINK && !Subtarget->isThumb()) { 567 // implicit def LR - LR mustn't be allocated as GRP:$dst of CALL_NOLINK 568 Chain = DAG.getCopyToReg(Chain, ARM::LR, 569 DAG.getNode(ISD::UNDEF, MVT::i32), InFlag); 570 InFlag = Chain.getValue(1); 571 } 572 573 std::vector<MVT::ValueType> NodeTys; 574 NodeTys.push_back(MVT::Other); // Returns a chain 575 NodeTys.push_back(MVT::Flag); // Returns a flag for retval copy to use. 576 577 std::vector<SDOperand> Ops; 578 Ops.push_back(Chain); 579 Ops.push_back(Callee); 580 581 // Add argument registers to the end of the list so that they are known live 582 // into the call. 583 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) 584 Ops.push_back(DAG.getRegister(RegsToPass[i].first, 585 RegsToPass[i].second.getValueType())); 586 587 if (InFlag.Val) 588 Ops.push_back(InFlag); 589 Chain = DAG.getNode(CallOpc, NodeTys, &Ops[0], Ops.size()); 590 InFlag = Chain.getValue(1); 591 592 SDOperand CSOps[] = { Chain, DAG.getConstant(NumBytes, MVT::i32), InFlag }; 593 Chain = DAG.getNode(ISD::CALLSEQ_END, 594 DAG.getNodeValueTypes(MVT::Other, MVT::Flag), 595 ((RetVT != MVT::Other) ? 2 : 1), CSOps, 3); 596 if (RetVT != MVT::Other) 597 InFlag = Chain.getValue(1); 598 599 std::vector<SDOperand> ResultVals; 600 NodeTys.clear(); 601 602 // If the call has results, copy the values out of the ret val registers. 603 switch (RetVT) { 604 default: assert(0 && "Unexpected ret value!"); 605 case MVT::Other: 606 break; 607 case MVT::i32: 608 Chain = DAG.getCopyFromReg(Chain, ARM::R0, MVT::i32, InFlag).getValue(1); 609 ResultVals.push_back(Chain.getValue(0)); 610 if (Op.Val->getValueType(1) == MVT::i32) { 611 // Returns a i64 value. 612 Chain = DAG.getCopyFromReg(Chain, ARM::R1, MVT::i32, 613 Chain.getValue(2)).getValue(1); 614 ResultVals.push_back(Chain.getValue(0)); 615 NodeTys.push_back(MVT::i32); 616 } 617 NodeTys.push_back(MVT::i32); 618 break; 619 case MVT::f32: 620 Chain = DAG.getCopyFromReg(Chain, ARM::R0, MVT::i32, InFlag).getValue(1); 621 ResultVals.push_back(DAG.getNode(ISD::BIT_CONVERT, MVT::f32, 622 Chain.getValue(0))); 623 NodeTys.push_back(MVT::f32); 624 break; 625 case MVT::f64: { 626 SDOperand Lo = DAG.getCopyFromReg(Chain, ARM::R0, MVT::i32, InFlag); 627 SDOperand Hi = DAG.getCopyFromReg(Lo, ARM::R1, MVT::i32, Lo.getValue(2)); 628 ResultVals.push_back(DAG.getNode(ARMISD::FMDRR, MVT::f64, Lo, Hi)); 629 NodeTys.push_back(MVT::f64); 630 break; 631 } 632 } 633 634 NodeTys.push_back(MVT::Other); 635 636 if (ResultVals.empty()) 637 return Chain; 638 639 ResultVals.push_back(Chain); 640 SDOperand Res = DAG.getNode(ISD::MERGE_VALUES, NodeTys, &ResultVals[0], 641 ResultVals.size()); 642 return Res.getValue(Op.ResNo); 643} 644 645static SDOperand LowerRET(SDOperand Op, SelectionDAG &DAG) { 646 SDOperand Copy; 647 SDOperand Chain = Op.getOperand(0); 648 switch(Op.getNumOperands()) { 649 default: 650 assert(0 && "Do not know how to return this many arguments!"); 651 abort(); 652 case 1: { 653 SDOperand LR = DAG.getRegister(ARM::LR, MVT::i32); 654 return DAG.getNode(ARMISD::RET_FLAG, MVT::Other, Chain); 655 } 656 case 3: 657 Op = Op.getOperand(1); 658 if (Op.getValueType() == MVT::f32) { 659 Op = DAG.getNode(ISD::BIT_CONVERT, MVT::i32, Op); 660 } else if (Op.getValueType() == MVT::f64) { 661 // Recursively legalize f64 -> i64. 662 Op = DAG.getNode(ISD::BIT_CONVERT, MVT::i64, Op); 663 return DAG.getNode(ISD::RET, MVT::Other, Chain, Op, 664 DAG.getConstant(0, MVT::i32)); 665 } 666 Copy = DAG.getCopyToReg(Chain, ARM::R0, Op, SDOperand()); 667 if (DAG.getMachineFunction().liveout_empty()) 668 DAG.getMachineFunction().addLiveOut(ARM::R0); 669 break; 670 case 5: 671 Copy = DAG.getCopyToReg(Chain, ARM::R1, Op.getOperand(3), SDOperand()); 672 Copy = DAG.getCopyToReg(Copy, ARM::R0, Op.getOperand(1), Copy.getValue(1)); 673 // If we haven't noted the R0+R1 are live out, do so now. 674 if (DAG.getMachineFunction().liveout_empty()) { 675 DAG.getMachineFunction().addLiveOut(ARM::R0); 676 DAG.getMachineFunction().addLiveOut(ARM::R1); 677 } 678 break; 679 } 680 681 //We must use RET_FLAG instead of BRIND because BRIND doesn't have a flag 682 return DAG.getNode(ARMISD::RET_FLAG, MVT::Other, Copy, Copy.getValue(1)); 683} 684 685// ConstantPool, JumpTable, GlobalAddress, and ExternalSymbol are lowered as 686// their target countpart wrapped in the ARMISD::Wrapper node. Suppose N is 687// one of the above mentioned nodes. It has to be wrapped because otherwise 688// Select(N) returns N. So the raw TargetGlobalAddress nodes, etc. can only 689// be used to form addressing mode. These wrapped nodes will be selected 690// into MOVi. 691static SDOperand LowerConstantPool(SDOperand Op, SelectionDAG &DAG) { 692 MVT::ValueType PtrVT = Op.getValueType(); 693 ConstantPoolSDNode *CP = cast<ConstantPoolSDNode>(Op); 694 SDOperand Res; 695 if (CP->isMachineConstantPoolEntry()) 696 Res = DAG.getTargetConstantPool(CP->getMachineCPVal(), PtrVT, 697 CP->getAlignment()); 698 else 699 Res = DAG.getTargetConstantPool(CP->getConstVal(), PtrVT, 700 CP->getAlignment()); 701 return DAG.getNode(ARMISD::Wrapper, MVT::i32, Res); 702} 703 704// Lower ISD::GlobalTLSAddress using the "general dynamic" model 705SDOperand 706ARMTargetLowering::LowerToTLSGeneralDynamicModel(GlobalAddressSDNode *GA, 707 SelectionDAG &DAG) { 708 MVT::ValueType PtrVT = getPointerTy(); 709 unsigned char PCAdj = Subtarget->isThumb() ? 4 : 8; 710 ARMConstantPoolValue *CPV = 711 new ARMConstantPoolValue(GA->getGlobal(), ARMPCLabelIndex, ARMCP::CPValue, 712 PCAdj, "tlsgd", true); 713 SDOperand Argument = DAG.getTargetConstantPool(CPV, PtrVT, 2); 714 Argument = DAG.getNode(ARMISD::Wrapper, MVT::i32, Argument); 715 Argument = DAG.getLoad(PtrVT, DAG.getEntryNode(), Argument, NULL, 0); 716 SDOperand Chain = Argument.getValue(1); 717 718 SDOperand PICLabel = DAG.getConstant(ARMPCLabelIndex++, MVT::i32); 719 Argument = DAG.getNode(ARMISD::PIC_ADD, PtrVT, Argument, PICLabel); 720 721 // call __tls_get_addr. 722 ArgListTy Args; 723 ArgListEntry Entry; 724 Entry.Node = Argument; 725 Entry.Ty = (const Type *) Type::Int32Ty; 726 Args.push_back(Entry); 727 std::pair<SDOperand, SDOperand> CallResult = 728 LowerCallTo(Chain, (const Type *) Type::Int32Ty, false, false, 729 CallingConv::C, false, 730 DAG.getExternalSymbol("__tls_get_addr", PtrVT), Args, DAG); 731 return CallResult.first; 732} 733 734// Lower ISD::GlobalTLSAddress using the "initial exec" or 735// "local exec" model. 736SDOperand 737ARMTargetLowering::LowerToTLSExecModels(GlobalAddressSDNode *GA, 738 SelectionDAG &DAG) { 739 GlobalValue *GV = GA->getGlobal(); 740 SDOperand Offset; 741 SDOperand Chain = DAG.getEntryNode(); 742 MVT::ValueType PtrVT = getPointerTy(); 743 // Get the Thread Pointer 744 SDOperand ThreadPointer = DAG.getNode(ARMISD::THREAD_POINTER, PtrVT); 745 746 if (GV->isDeclaration()){ 747 // initial exec model 748 unsigned char PCAdj = Subtarget->isThumb() ? 4 : 8; 749 ARMConstantPoolValue *CPV = 750 new ARMConstantPoolValue(GA->getGlobal(), ARMPCLabelIndex, ARMCP::CPValue, 751 PCAdj, "gottpoff", true); 752 Offset = DAG.getTargetConstantPool(CPV, PtrVT, 2); 753 Offset = DAG.getNode(ARMISD::Wrapper, MVT::i32, Offset); 754 Offset = DAG.getLoad(PtrVT, Chain, Offset, NULL, 0); 755 Chain = Offset.getValue(1); 756 757 SDOperand PICLabel = DAG.getConstant(ARMPCLabelIndex++, MVT::i32); 758 Offset = DAG.getNode(ARMISD::PIC_ADD, PtrVT, Offset, PICLabel); 759 760 Offset = DAG.getLoad(PtrVT, Chain, Offset, NULL, 0); 761 } else { 762 // local exec model 763 ARMConstantPoolValue *CPV = 764 new ARMConstantPoolValue(GV, ARMCP::CPValue, "tpoff"); 765 Offset = DAG.getTargetConstantPool(CPV, PtrVT, 2); 766 Offset = DAG.getNode(ARMISD::Wrapper, MVT::i32, Offset); 767 Offset = DAG.getLoad(PtrVT, Chain, Offset, NULL, 0); 768 } 769 770 // The address of the thread local variable is the add of the thread 771 // pointer with the offset of the variable. 772 return DAG.getNode(ISD::ADD, PtrVT, ThreadPointer, Offset); 773} 774 775SDOperand 776ARMTargetLowering::LowerGlobalTLSAddress(SDOperand Op, SelectionDAG &DAG) { 777 // TODO: implement the "local dynamic" model 778 assert(Subtarget->isTargetELF() && 779 "TLS not implemented for non-ELF targets"); 780 GlobalAddressSDNode *GA = cast<GlobalAddressSDNode>(Op); 781 // If the relocation model is PIC, use the "General Dynamic" TLS Model, 782 // otherwise use the "Local Exec" TLS Model 783 if (getTargetMachine().getRelocationModel() == Reloc::PIC_) 784 return LowerToTLSGeneralDynamicModel(GA, DAG); 785 else 786 return LowerToTLSExecModels(GA, DAG); 787} 788 789SDOperand ARMTargetLowering::LowerGlobalAddressELF(SDOperand Op, 790 SelectionDAG &DAG) { 791 MVT::ValueType PtrVT = getPointerTy(); 792 GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal(); 793 Reloc::Model RelocM = getTargetMachine().getRelocationModel(); 794 if (RelocM == Reloc::PIC_) { 795 bool UseGOTOFF = GV->hasInternalLinkage(); 796 ARMConstantPoolValue *CPV = 797 new ARMConstantPoolValue(GV, ARMCP::CPValue, UseGOTOFF ? "GOTOFF":"GOT"); 798 SDOperand CPAddr = DAG.getTargetConstantPool(CPV, PtrVT, 2); 799 CPAddr = DAG.getNode(ARMISD::Wrapper, MVT::i32, CPAddr); 800 SDOperand Result = DAG.getLoad(PtrVT, DAG.getEntryNode(), CPAddr, NULL, 0); 801 SDOperand Chain = Result.getValue(1); 802 SDOperand GOT = DAG.getNode(ISD::GLOBAL_OFFSET_TABLE, PtrVT); 803 Result = DAG.getNode(ISD::ADD, PtrVT, Result, GOT); 804 if (!UseGOTOFF) 805 Result = DAG.getLoad(PtrVT, Chain, Result, NULL, 0); 806 return Result; 807 } else { 808 SDOperand CPAddr = DAG.getTargetConstantPool(GV, PtrVT, 2); 809 CPAddr = DAG.getNode(ARMISD::Wrapper, MVT::i32, CPAddr); 810 return DAG.getLoad(PtrVT, DAG.getEntryNode(), CPAddr, NULL, 0); 811 } 812} 813 814/// GVIsIndirectSymbol - true if the GV will be accessed via an indirect symbol 815/// even in non-static mode. 816static bool GVIsIndirectSymbol(GlobalValue *GV, Reloc::Model RelocM) { 817 return RelocM != Reloc::Static && 818 (GV->hasWeakLinkage() || GV->hasLinkOnceLinkage() || 819 (GV->isDeclaration() && !GV->hasNotBeenReadFromBytecode())); 820} 821 822SDOperand ARMTargetLowering::LowerGlobalAddressDarwin(SDOperand Op, 823 SelectionDAG &DAG) { 824 MVT::ValueType PtrVT = getPointerTy(); 825 GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal(); 826 Reloc::Model RelocM = getTargetMachine().getRelocationModel(); 827 bool IsIndirect = GVIsIndirectSymbol(GV, RelocM); 828 SDOperand CPAddr; 829 if (RelocM == Reloc::Static) 830 CPAddr = DAG.getTargetConstantPool(GV, PtrVT, 2); 831 else { 832 unsigned PCAdj = (RelocM != Reloc::PIC_) 833 ? 0 : (Subtarget->isThumb() ? 4 : 8); 834 ARMCP::ARMCPKind Kind = IsIndirect ? ARMCP::CPNonLazyPtr 835 : ARMCP::CPValue; 836 ARMConstantPoolValue *CPV = new ARMConstantPoolValue(GV, ARMPCLabelIndex, 837 Kind, PCAdj); 838 CPAddr = DAG.getTargetConstantPool(CPV, PtrVT, 2); 839 } 840 CPAddr = DAG.getNode(ARMISD::Wrapper, MVT::i32, CPAddr); 841 842 SDOperand Result = DAG.getLoad(PtrVT, DAG.getEntryNode(), CPAddr, NULL, 0); 843 SDOperand Chain = Result.getValue(1); 844 845 if (RelocM == Reloc::PIC_) { 846 SDOperand PICLabel = DAG.getConstant(ARMPCLabelIndex++, MVT::i32); 847 Result = DAG.getNode(ARMISD::PIC_ADD, PtrVT, Result, PICLabel); 848 } 849 if (IsIndirect) 850 Result = DAG.getLoad(PtrVT, Chain, Result, NULL, 0); 851 852 return Result; 853} 854 855SDOperand ARMTargetLowering::LowerGLOBAL_OFFSET_TABLE(SDOperand Op, 856 SelectionDAG &DAG){ 857 assert(Subtarget->isTargetELF() && 858 "GLOBAL OFFSET TABLE not implemented for non-ELF targets"); 859 MVT::ValueType PtrVT = getPointerTy(); 860 unsigned PCAdj = Subtarget->isThumb() ? 4 : 8; 861 ARMConstantPoolValue *CPV = new ARMConstantPoolValue("_GLOBAL_OFFSET_TABLE_", 862 ARMPCLabelIndex, 863 ARMCP::CPValue, PCAdj); 864 SDOperand CPAddr = DAG.getTargetConstantPool(CPV, PtrVT, 2); 865 CPAddr = DAG.getNode(ARMISD::Wrapper, MVT::i32, CPAddr); 866 SDOperand Result = DAG.getLoad(PtrVT, DAG.getEntryNode(), CPAddr, NULL, 0); 867 SDOperand PICLabel = DAG.getConstant(ARMPCLabelIndex++, MVT::i32); 868 return DAG.getNode(ARMISD::PIC_ADD, PtrVT, Result, PICLabel); 869} 870 871static SDOperand LowerVASTART(SDOperand Op, SelectionDAG &DAG, 872 unsigned VarArgsFrameIndex) { 873 // vastart just stores the address of the VarArgsFrameIndex slot into the 874 // memory location argument. 875 MVT::ValueType PtrVT = DAG.getTargetLoweringInfo().getPointerTy(); 876 SDOperand FR = DAG.getFrameIndex(VarArgsFrameIndex, PtrVT); 877 SrcValueSDNode *SV = cast<SrcValueSDNode>(Op.getOperand(2)); 878 return DAG.getStore(Op.getOperand(0), FR, Op.getOperand(1), SV->getValue(), 879 SV->getOffset()); 880} 881 882static SDOperand LowerFORMAL_ARGUMENT(SDOperand Op, SelectionDAG &DAG, 883 unsigned *vRegs, unsigned ArgNo, 884 unsigned &NumGPRs, unsigned &ArgOffset) { 885 MachineFunction &MF = DAG.getMachineFunction(); 886 MVT::ValueType ObjectVT = Op.getValue(ArgNo).getValueType(); 887 SDOperand Root = Op.getOperand(0); 888 std::vector<SDOperand> ArgValues; 889 SSARegMap *RegMap = MF.getSSARegMap(); 890 891 static const unsigned GPRArgRegs[] = { 892 ARM::R0, ARM::R1, ARM::R2, ARM::R3 893 }; 894 895 unsigned ObjSize; 896 unsigned ObjGPRs; 897 unsigned GPRPad; 898 unsigned StackPad; 899 unsigned Flags = Op.getConstantOperandVal(ArgNo + 3); 900 HowToPassArgument(ObjectVT, NumGPRs, ArgOffset, ObjGPRs, 901 ObjSize, GPRPad, StackPad, Flags); 902 NumGPRs += GPRPad; 903 ArgOffset += StackPad; 904 905 SDOperand ArgValue; 906 if (ObjGPRs == 1) { 907 unsigned VReg = RegMap->createVirtualRegister(&ARM::GPRRegClass); 908 MF.addLiveIn(GPRArgRegs[NumGPRs], VReg); 909 vRegs[NumGPRs] = VReg; 910 ArgValue = DAG.getCopyFromReg(Root, VReg, MVT::i32); 911 if (ObjectVT == MVT::f32) 912 ArgValue = DAG.getNode(ISD::BIT_CONVERT, MVT::f32, ArgValue); 913 } else if (ObjGPRs == 2) { 914 unsigned VReg = RegMap->createVirtualRegister(&ARM::GPRRegClass); 915 MF.addLiveIn(GPRArgRegs[NumGPRs], VReg); 916 vRegs[NumGPRs] = VReg; 917 ArgValue = DAG.getCopyFromReg(Root, VReg, MVT::i32); 918 919 VReg = RegMap->createVirtualRegister(&ARM::GPRRegClass); 920 MF.addLiveIn(GPRArgRegs[NumGPRs+1], VReg); 921 vRegs[NumGPRs+1] = VReg; 922 SDOperand ArgValue2 = DAG.getCopyFromReg(Root, VReg, MVT::i32); 923 924 if (ObjectVT == MVT::i64) 925 ArgValue = DAG.getNode(ISD::BUILD_PAIR, MVT::i64, ArgValue, ArgValue2); 926 else 927 ArgValue = DAG.getNode(ARMISD::FMDRR, MVT::f64, ArgValue, ArgValue2); 928 } 929 NumGPRs += ObjGPRs; 930 931 if (ObjSize) { 932 // If the argument is actually used, emit a load from the right stack 933 // slot. 934 if (!Op.Val->hasNUsesOfValue(0, ArgNo)) { 935 MachineFrameInfo *MFI = MF.getFrameInfo(); 936 int FI = MFI->CreateFixedObject(ObjSize, ArgOffset); 937 SDOperand FIN = DAG.getFrameIndex(FI, MVT::i32); 938 if (ObjGPRs == 0) 939 ArgValue = DAG.getLoad(ObjectVT, Root, FIN, NULL, 0); 940 else { 941 SDOperand ArgValue2 = 942 DAG.getLoad(MVT::i32, Root, FIN, NULL, 0); 943 if (ObjectVT == MVT::i64) 944 ArgValue= DAG.getNode(ISD::BUILD_PAIR, MVT::i64, ArgValue, ArgValue2); 945 else 946 ArgValue= DAG.getNode(ARMISD::FMDRR, MVT::f64, ArgValue, ArgValue2); 947 } 948 } else { 949 // Don't emit a dead load. 950 ArgValue = DAG.getNode(ISD::UNDEF, ObjectVT); 951 } 952 953 ArgOffset += ObjSize; // Move on to the next argument. 954 } 955 956 return ArgValue; 957} 958 959SDOperand 960ARMTargetLowering::LowerFORMAL_ARGUMENTS(SDOperand Op, SelectionDAG &DAG) { 961 std::vector<SDOperand> ArgValues; 962 SDOperand Root = Op.getOperand(0); 963 unsigned ArgOffset = 0; // Frame mechanisms handle retaddr slot 964 unsigned NumGPRs = 0; // GPRs used for parameter passing. 965 unsigned VRegs[4]; 966 967 unsigned NumArgs = Op.Val->getNumValues()-1; 968 for (unsigned ArgNo = 0; ArgNo < NumArgs; ++ArgNo) 969 ArgValues.push_back(LowerFORMAL_ARGUMENT(Op, DAG, VRegs, ArgNo, 970 NumGPRs, ArgOffset)); 971 972 bool isVarArg = cast<ConstantSDNode>(Op.getOperand(2))->getValue() != 0; 973 if (isVarArg) { 974 static const unsigned GPRArgRegs[] = { 975 ARM::R0, ARM::R1, ARM::R2, ARM::R3 976 }; 977 978 MachineFunction &MF = DAG.getMachineFunction(); 979 SSARegMap *RegMap = MF.getSSARegMap(); 980 MachineFrameInfo *MFI = MF.getFrameInfo(); 981 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>(); 982 unsigned Align = MF.getTarget().getFrameInfo()->getStackAlignment(); 983 unsigned VARegSize = (4 - NumGPRs) * 4; 984 unsigned VARegSaveSize = (VARegSize + Align - 1) & ~(Align - 1); 985 if (VARegSaveSize) { 986 // If this function is vararg, store any remaining integer argument regs 987 // to their spots on the stack so that they may be loaded by deferencing 988 // the result of va_next. 989 AFI->setVarArgsRegSaveSize(VARegSaveSize); 990 VarArgsFrameIndex = MFI->CreateFixedObject(VARegSaveSize, ArgOffset + 991 VARegSaveSize - VARegSize); 992 SDOperand FIN = DAG.getFrameIndex(VarArgsFrameIndex, getPointerTy()); 993 994 SmallVector<SDOperand, 4> MemOps; 995 for (; NumGPRs < 4; ++NumGPRs) { 996 unsigned VReg = RegMap->createVirtualRegister(&ARM::GPRRegClass); 997 MF.addLiveIn(GPRArgRegs[NumGPRs], VReg); 998 SDOperand Val = DAG.getCopyFromReg(Root, VReg, MVT::i32); 999 SDOperand Store = DAG.getStore(Val.getValue(1), Val, FIN, NULL, 0); 1000 MemOps.push_back(Store); 1001 FIN = DAG.getNode(ISD::ADD, getPointerTy(), FIN, 1002 DAG.getConstant(4, getPointerTy())); 1003 } 1004 if (!MemOps.empty()) 1005 Root = DAG.getNode(ISD::TokenFactor, MVT::Other, 1006 &MemOps[0], MemOps.size()); 1007 } else 1008 // This will point to the next argument passed via stack. 1009 VarArgsFrameIndex = MFI->CreateFixedObject(4, ArgOffset); 1010 } 1011 1012 ArgValues.push_back(Root); 1013 1014 // Return the new list of results. 1015 std::vector<MVT::ValueType> RetVT(Op.Val->value_begin(), 1016 Op.Val->value_end()); 1017 return DAG.getNode(ISD::MERGE_VALUES, RetVT, &ArgValues[0], ArgValues.size()); 1018} 1019 1020/// isFloatingPointZero - Return true if this is +0.0. 1021static bool isFloatingPointZero(SDOperand Op) { 1022 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(Op)) 1023 return CFP->isExactlyValue(0.0); 1024 else if (ISD::isEXTLoad(Op.Val) || ISD::isNON_EXTLoad(Op.Val)) { 1025 // Maybe this has already been legalized into the constant pool? 1026 if (Op.getOperand(1).getOpcode() == ARMISD::Wrapper) { 1027 SDOperand WrapperOp = Op.getOperand(1).getOperand(0); 1028 if (ConstantPoolSDNode *CP = dyn_cast<ConstantPoolSDNode>(WrapperOp)) 1029 if (ConstantFP *CFP = dyn_cast<ConstantFP>(CP->getConstVal())) 1030 return CFP->isExactlyValue(0.0); 1031 } 1032 } 1033 return false; 1034} 1035 1036static bool isLegalCmpImmediate(unsigned C, bool isThumb) { 1037 return ( isThumb && (C & ~255U) == 0) || 1038 (!isThumb && ARM_AM::getSOImmVal(C) != -1); 1039} 1040 1041/// Returns appropriate ARM CMP (cmp) and corresponding condition code for 1042/// the given operands. 1043static SDOperand getARMCmp(SDOperand LHS, SDOperand RHS, ISD::CondCode CC, 1044 SDOperand &ARMCC, SelectionDAG &DAG, bool isThumb) { 1045 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(RHS.Val)) { 1046 unsigned C = RHSC->getValue(); 1047 if (!isLegalCmpImmediate(C, isThumb)) { 1048 // Constant does not fit, try adjusting it by one? 1049 switch (CC) { 1050 default: break; 1051 case ISD::SETLT: 1052 case ISD::SETGE: 1053 if (isLegalCmpImmediate(C-1, isThumb)) { 1054 CC = (CC == ISD::SETLT) ? ISD::SETLE : ISD::SETGT; 1055 RHS = DAG.getConstant(C-1, MVT::i32); 1056 } 1057 break; 1058 case ISD::SETULT: 1059 case ISD::SETUGE: 1060 if (C > 0 && isLegalCmpImmediate(C-1, isThumb)) { 1061 CC = (CC == ISD::SETULT) ? ISD::SETULE : ISD::SETUGT; 1062 RHS = DAG.getConstant(C-1, MVT::i32); 1063 } 1064 break; 1065 case ISD::SETLE: 1066 case ISD::SETGT: 1067 if (isLegalCmpImmediate(C+1, isThumb)) { 1068 CC = (CC == ISD::SETLE) ? ISD::SETLT : ISD::SETGE; 1069 RHS = DAG.getConstant(C+1, MVT::i32); 1070 } 1071 break; 1072 case ISD::SETULE: 1073 case ISD::SETUGT: 1074 if (C < 0xffffffff && isLegalCmpImmediate(C+1, isThumb)) { 1075 CC = (CC == ISD::SETULE) ? ISD::SETULT : ISD::SETUGE; 1076 RHS = DAG.getConstant(C+1, MVT::i32); 1077 } 1078 break; 1079 } 1080 } 1081 } 1082 1083 ARMCC::CondCodes CondCode = IntCCToARMCC(CC); 1084 ARMISD::NodeType CompareType; 1085 switch (CondCode) { 1086 default: 1087 CompareType = ARMISD::CMP; 1088 break; 1089 case ARMCC::EQ: 1090 case ARMCC::NE: 1091 case ARMCC::MI: 1092 case ARMCC::PL: 1093 // Uses only N and Z Flags 1094 CompareType = ARMISD::CMPNZ; 1095 break; 1096 } 1097 ARMCC = DAG.getConstant(CondCode, MVT::i32); 1098 return DAG.getNode(CompareType, MVT::Flag, LHS, RHS); 1099} 1100 1101/// Returns a appropriate VFP CMP (fcmp{s|d}+fmstat) for the given operands. 1102static SDOperand getVFPCmp(SDOperand LHS, SDOperand RHS, SelectionDAG &DAG) { 1103 SDOperand Cmp; 1104 if (!isFloatingPointZero(RHS)) 1105 Cmp = DAG.getNode(ARMISD::CMPFP, MVT::Flag, LHS, RHS); 1106 else 1107 Cmp = DAG.getNode(ARMISD::CMPFPw0, MVT::Flag, LHS); 1108 return DAG.getNode(ARMISD::FMSTAT, MVT::Flag, Cmp); 1109} 1110 1111static SDOperand LowerSELECT_CC(SDOperand Op, SelectionDAG &DAG, 1112 const ARMSubtarget *ST) { 1113 MVT::ValueType VT = Op.getValueType(); 1114 SDOperand LHS = Op.getOperand(0); 1115 SDOperand RHS = Op.getOperand(1); 1116 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(4))->get(); 1117 SDOperand TrueVal = Op.getOperand(2); 1118 SDOperand FalseVal = Op.getOperand(3); 1119 1120 if (LHS.getValueType() == MVT::i32) { 1121 SDOperand ARMCC; 1122 SDOperand Cmp = getARMCmp(LHS, RHS, CC, ARMCC, DAG, ST->isThumb()); 1123 return DAG.getNode(ARMISD::CMOV, VT, FalseVal, TrueVal, ARMCC, Cmp); 1124 } 1125 1126 ARMCC::CondCodes CondCode, CondCode2; 1127 if (FPCCToARMCC(CC, CondCode, CondCode2)) 1128 std::swap(TrueVal, FalseVal); 1129 1130 SDOperand ARMCC = DAG.getConstant(CondCode, MVT::i32); 1131 SDOperand Cmp = getVFPCmp(LHS, RHS, DAG); 1132 SDOperand Result = DAG.getNode(ARMISD::CMOV, VT, FalseVal, TrueVal, 1133 ARMCC, Cmp); 1134 if (CondCode2 != ARMCC::AL) { 1135 SDOperand ARMCC2 = DAG.getConstant(CondCode2, MVT::i32); 1136 // FIXME: Needs another CMP because flag can have but one use. 1137 SDOperand Cmp2 = getVFPCmp(LHS, RHS, DAG); 1138 Result = DAG.getNode(ARMISD::CMOV, VT, Result, TrueVal, ARMCC2, Cmp2); 1139 } 1140 return Result; 1141} 1142 1143static SDOperand LowerBR_CC(SDOperand Op, SelectionDAG &DAG, 1144 const ARMSubtarget *ST) { 1145 SDOperand Chain = Op.getOperand(0); 1146 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(1))->get(); 1147 SDOperand LHS = Op.getOperand(2); 1148 SDOperand RHS = Op.getOperand(3); 1149 SDOperand Dest = Op.getOperand(4); 1150 1151 if (LHS.getValueType() == MVT::i32) { 1152 SDOperand ARMCC; 1153 SDOperand Cmp = getARMCmp(LHS, RHS, CC, ARMCC, DAG, ST->isThumb()); 1154 return DAG.getNode(ARMISD::BRCOND, MVT::Other, Chain, Dest, ARMCC, Cmp); 1155 } 1156 1157 assert(LHS.getValueType() == MVT::f32 || LHS.getValueType() == MVT::f64); 1158 ARMCC::CondCodes CondCode, CondCode2; 1159 if (FPCCToARMCC(CC, CondCode, CondCode2)) 1160 // Swap the LHS/RHS of the comparison if needed. 1161 std::swap(LHS, RHS); 1162 1163 SDOperand Cmp = getVFPCmp(LHS, RHS, DAG); 1164 SDOperand ARMCC = DAG.getConstant(CondCode, MVT::i32); 1165 SDVTList VTList = DAG.getVTList(MVT::Other, MVT::Flag); 1166 SDOperand Ops[] = { Chain, Dest, ARMCC, Cmp }; 1167 SDOperand Res = DAG.getNode(ARMISD::BRCOND, VTList, Ops, 4); 1168 if (CondCode2 != ARMCC::AL) { 1169 ARMCC = DAG.getConstant(CondCode2, MVT::i32); 1170 SDOperand Ops[] = { Res, Dest, ARMCC, Res.getValue(1) }; 1171 Res = DAG.getNode(ARMISD::BRCOND, VTList, Ops, 4); 1172 } 1173 return Res; 1174} 1175 1176SDOperand ARMTargetLowering::LowerBR_JT(SDOperand Op, SelectionDAG &DAG) { 1177 SDOperand Chain = Op.getOperand(0); 1178 SDOperand Table = Op.getOperand(1); 1179 SDOperand Index = Op.getOperand(2); 1180 1181 MVT::ValueType PTy = getPointerTy(); 1182 JumpTableSDNode *JT = cast<JumpTableSDNode>(Table); 1183 ARMFunctionInfo *AFI = DAG.getMachineFunction().getInfo<ARMFunctionInfo>(); 1184 SDOperand UId = DAG.getConstant(AFI->createJumpTableUId(), PTy); 1185 SDOperand JTI = DAG.getTargetJumpTable(JT->getIndex(), PTy); 1186 Table = DAG.getNode(ARMISD::WrapperJT, MVT::i32, JTI, UId); 1187 Index = DAG.getNode(ISD::MUL, PTy, Index, DAG.getConstant(4, PTy)); 1188 SDOperand Addr = DAG.getNode(ISD::ADD, PTy, Index, Table); 1189 bool isPIC = getTargetMachine().getRelocationModel() == Reloc::PIC_; 1190 Addr = DAG.getLoad(isPIC ? MVT::i32 : PTy, Chain, Addr, NULL, 0); 1191 Chain = Addr.getValue(1); 1192 if (isPIC) 1193 Addr = DAG.getNode(ISD::ADD, PTy, Addr, Table); 1194 return DAG.getNode(ARMISD::BR_JT, MVT::Other, Chain, Addr, JTI, UId); 1195} 1196 1197static SDOperand LowerFP_TO_INT(SDOperand Op, SelectionDAG &DAG) { 1198 unsigned Opc = 1199 Op.getOpcode() == ISD::FP_TO_SINT ? ARMISD::FTOSI : ARMISD::FTOUI; 1200 Op = DAG.getNode(Opc, MVT::f32, Op.getOperand(0)); 1201 return DAG.getNode(ISD::BIT_CONVERT, MVT::i32, Op); 1202} 1203 1204static SDOperand LowerINT_TO_FP(SDOperand Op, SelectionDAG &DAG) { 1205 MVT::ValueType VT = Op.getValueType(); 1206 unsigned Opc = 1207 Op.getOpcode() == ISD::SINT_TO_FP ? ARMISD::SITOF : ARMISD::UITOF; 1208 1209 Op = DAG.getNode(ISD::BIT_CONVERT, MVT::f32, Op.getOperand(0)); 1210 return DAG.getNode(Opc, VT, Op); 1211} 1212 1213static SDOperand LowerFCOPYSIGN(SDOperand Op, SelectionDAG &DAG) { 1214 // Implement fcopysign with a fabs and a conditional fneg. 1215 SDOperand Tmp0 = Op.getOperand(0); 1216 SDOperand Tmp1 = Op.getOperand(1); 1217 MVT::ValueType VT = Op.getValueType(); 1218 MVT::ValueType SrcVT = Tmp1.getValueType(); 1219 SDOperand AbsVal = DAG.getNode(ISD::FABS, VT, Tmp0); 1220 SDOperand Cmp = getVFPCmp(Tmp1, DAG.getConstantFP(0.0, SrcVT), DAG); 1221 SDOperand ARMCC = DAG.getConstant(ARMCC::LT, MVT::i32); 1222 return DAG.getNode(ARMISD::CNEG, VT, AbsVal, AbsVal, ARMCC, Cmp); 1223} 1224 1225static SDOperand LowerBIT_CONVERT(SDOperand Op, SelectionDAG &DAG) { 1226 // Turn f64->i64 into FMRRD. 1227 assert(Op.getValueType() == MVT::i64 && 1228 Op.getOperand(0).getValueType() == MVT::f64); 1229 1230 Op = Op.getOperand(0); 1231 SDOperand Cvt = DAG.getNode(ARMISD::FMRRD, DAG.getVTList(MVT::i32, MVT::i32), 1232 &Op, 1); 1233 1234 // Merge the pieces into a single i64 value. 1235 return DAG.getNode(ISD::BUILD_PAIR, MVT::i64, Cvt, Cvt.getValue(1)); 1236} 1237 1238static SDOperand LowerMUL(SDOperand Op, SelectionDAG &DAG) { 1239 // FIXME: All this code is target-independent. Create a new target-indep 1240 // MULHILO node and move this code to the legalizer. 1241 // 1242 assert(Op.getValueType() == MVT::i64 && "Only handles i64 expand right now!"); 1243 1244 SDOperand LL = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32, Op.getOperand(0), 1245 DAG.getConstant(0, MVT::i32)); 1246 SDOperand RL = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32, Op.getOperand(1), 1247 DAG.getConstant(0, MVT::i32)); 1248 1249 const TargetLowering &TL = DAG.getTargetLoweringInfo(); 1250 unsigned LHSSB = TL.ComputeNumSignBits(Op.getOperand(0)); 1251 unsigned RHSSB = TL.ComputeNumSignBits(Op.getOperand(1)); 1252 1253 SDOperand Lo, Hi; 1254 // Figure out how to lower this multiply. 1255 if (LHSSB >= 33 && RHSSB >= 33) { 1256 // If the input values are both sign extended, we can emit a mulhs+mul. 1257 Lo = DAG.getNode(ISD::MUL, MVT::i32, LL, RL); 1258 Hi = DAG.getNode(ISD::MULHS, MVT::i32, LL, RL); 1259 } else if (LHSSB == 32 && RHSSB == 32 && 1260 TL.MaskedValueIsZero(Op.getOperand(0), 0xFFFFFFFF00000000ULL) && 1261 TL.MaskedValueIsZero(Op.getOperand(1), 0xFFFFFFFF00000000ULL)) { 1262 // If the inputs are zero extended, use mulhu. 1263 Lo = DAG.getNode(ISD::MUL, MVT::i32, LL, RL); 1264 Hi = DAG.getNode(ISD::MULHU, MVT::i32, LL, RL); 1265 } else { 1266 SDOperand LH = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32, Op.getOperand(0), 1267 DAG.getConstant(1, MVT::i32)); 1268 SDOperand RH = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32, Op.getOperand(1), 1269 DAG.getConstant(1, MVT::i32)); 1270 1271 // Lo,Hi = umul LHS, RHS. 1272 SDOperand Ops[] = { LL, RL }; 1273 SDOperand UMul64 = DAG.getNode(ARMISD::MULHILOU, 1274 DAG.getVTList(MVT::i32, MVT::i32), Ops, 2); 1275 Lo = UMul64; 1276 Hi = UMul64.getValue(1); 1277 RH = DAG.getNode(ISD::MUL, MVT::i32, LL, RH); 1278 LH = DAG.getNode(ISD::MUL, MVT::i32, LH, RL); 1279 Hi = DAG.getNode(ISD::ADD, MVT::i32, Hi, RH); 1280 Hi = DAG.getNode(ISD::ADD, MVT::i32, Hi, LH); 1281 } 1282 1283 // Merge the pieces into a single i64 value. 1284 return DAG.getNode(ISD::BUILD_PAIR, MVT::i64, Lo, Hi); 1285} 1286 1287static SDOperand LowerMULHU(SDOperand Op, SelectionDAG &DAG) { 1288 SDOperand Ops[] = { Op.getOperand(0), Op.getOperand(1) }; 1289 return DAG.getNode(ARMISD::MULHILOU, 1290 DAG.getVTList(MVT::i32, MVT::i32), Ops, 2).getValue(1); 1291} 1292 1293static SDOperand LowerMULHS(SDOperand Op, SelectionDAG &DAG) { 1294 SDOperand Ops[] = { Op.getOperand(0), Op.getOperand(1) }; 1295 return DAG.getNode(ARMISD::MULHILOS, 1296 DAG.getVTList(MVT::i32, MVT::i32), Ops, 2).getValue(1); 1297} 1298 1299static SDOperand LowerSRx(SDOperand Op, SelectionDAG &DAG, 1300 const ARMSubtarget *ST) { 1301 assert(Op.getValueType() == MVT::i64 && 1302 (Op.getOpcode() == ISD::SRL || Op.getOpcode() == ISD::SRA) && 1303 "Unknown shift to lower!"); 1304 1305 // We only lower SRA, SRL of 1 here, all others use generic lowering. 1306 if (!isa<ConstantSDNode>(Op.getOperand(1)) || 1307 cast<ConstantSDNode>(Op.getOperand(1))->getValue() != 1) 1308 return SDOperand(); 1309 1310 // If we are in thumb mode, we don't have RRX. 1311 if (ST->isThumb()) return SDOperand(); 1312 1313 // Okay, we have a 64-bit SRA or SRL of 1. Lower this to an RRX expr. 1314 SDOperand Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32, Op.getOperand(0), 1315 DAG.getConstant(0, MVT::i32)); 1316 SDOperand Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32, Op.getOperand(0), 1317 DAG.getConstant(1, MVT::i32)); 1318 1319 // First, build a SRA_FLAG/SRL_FLAG op, which shifts the top part by one and 1320 // captures the result into a carry flag. 1321 unsigned Opc = Op.getOpcode() == ISD::SRL ? ARMISD::SRL_FLAG:ARMISD::SRA_FLAG; 1322 Hi = DAG.getNode(Opc, DAG.getVTList(MVT::i32, MVT::Flag), &Hi, 1); 1323 1324 // The low part is an ARMISD::RRX operand, which shifts the carry in. 1325 Lo = DAG.getNode(ARMISD::RRX, MVT::i32, Lo, Hi.getValue(1)); 1326 1327 // Merge the pieces into a single i64 value. 1328 return DAG.getNode(ISD::BUILD_PAIR, MVT::i64, Lo, Hi); 1329} 1330 1331SDOperand ARMTargetLowering::LowerOperation(SDOperand Op, SelectionDAG &DAG) { 1332 switch (Op.getOpcode()) { 1333 default: assert(0 && "Don't know how to custom lower this!"); abort(); 1334 case ISD::ConstantPool: return LowerConstantPool(Op, DAG); 1335 case ISD::GlobalAddress: 1336 return Subtarget->isTargetDarwin() ? LowerGlobalAddressDarwin(Op, DAG) : 1337 LowerGlobalAddressELF(Op, DAG); 1338 case ISD::GlobalTLSAddress: return LowerGlobalTLSAddress(Op, DAG); 1339 case ISD::CALL: return LowerCALL(Op, DAG); 1340 case ISD::RET: return LowerRET(Op, DAG); 1341 case ISD::SELECT_CC: return LowerSELECT_CC(Op, DAG, Subtarget); 1342 case ISD::BR_CC: return LowerBR_CC(Op, DAG, Subtarget); 1343 case ISD::BR_JT: return LowerBR_JT(Op, DAG); 1344 case ISD::VASTART: return LowerVASTART(Op, DAG, VarArgsFrameIndex); 1345 case ISD::SINT_TO_FP: 1346 case ISD::UINT_TO_FP: return LowerINT_TO_FP(Op, DAG); 1347 case ISD::FP_TO_SINT: 1348 case ISD::FP_TO_UINT: return LowerFP_TO_INT(Op, DAG); 1349 case ISD::FCOPYSIGN: return LowerFCOPYSIGN(Op, DAG); 1350 case ISD::BIT_CONVERT: return LowerBIT_CONVERT(Op, DAG); 1351 case ISD::MUL: return LowerMUL(Op, DAG); 1352 case ISD::MULHU: return LowerMULHU(Op, DAG); 1353 case ISD::MULHS: return LowerMULHS(Op, DAG); 1354 case ISD::SRL: 1355 case ISD::SRA: return LowerSRx(Op, DAG, Subtarget); 1356 case ISD::FORMAL_ARGUMENTS: 1357 return LowerFORMAL_ARGUMENTS(Op, DAG); 1358 case ISD::RETURNADDR: break; 1359 case ISD::FRAMEADDR: break; 1360 case ISD::GLOBAL_OFFSET_TABLE: return LowerGLOBAL_OFFSET_TABLE(Op, DAG); 1361 } 1362 return SDOperand(); 1363} 1364 1365//===----------------------------------------------------------------------===// 1366// ARM Scheduler Hooks 1367//===----------------------------------------------------------------------===// 1368 1369MachineBasicBlock * 1370ARMTargetLowering::InsertAtEndOfBasicBlock(MachineInstr *MI, 1371 MachineBasicBlock *BB) { 1372 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); 1373 switch (MI->getOpcode()) { 1374 default: assert(false && "Unexpected instr type to insert"); 1375 case ARM::tMOVCCr: { 1376 // To "insert" a SELECT_CC instruction, we actually have to insert the 1377 // diamond control-flow pattern. The incoming instruction knows the 1378 // destination vreg to set, the condition code register to branch on, the 1379 // true/false values to select between, and a branch opcode to use. 1380 const BasicBlock *LLVM_BB = BB->getBasicBlock(); 1381 ilist<MachineBasicBlock>::iterator It = BB; 1382 ++It; 1383 1384 // thisMBB: 1385 // ... 1386 // TrueVal = ... 1387 // cmpTY ccX, r1, r2 1388 // bCC copy1MBB 1389 // fallthrough --> copy0MBB 1390 MachineBasicBlock *thisMBB = BB; 1391 MachineBasicBlock *copy0MBB = new MachineBasicBlock(LLVM_BB); 1392 MachineBasicBlock *sinkMBB = new MachineBasicBlock(LLVM_BB); 1393 BuildMI(BB, TII->get(ARM::tBcc)).addMBB(sinkMBB) 1394 .addImm(MI->getOperand(3).getImm()); 1395 MachineFunction *F = BB->getParent(); 1396 F->getBasicBlockList().insert(It, copy0MBB); 1397 F->getBasicBlockList().insert(It, sinkMBB); 1398 // Update machine-CFG edges by first adding all successors of the current 1399 // block to the new block which will contain the Phi node for the select. 1400 for(MachineBasicBlock::succ_iterator i = BB->succ_begin(), 1401 e = BB->succ_end(); i != e; ++i) 1402 sinkMBB->addSuccessor(*i); 1403 // Next, remove all successors of the current block, and add the true 1404 // and fallthrough blocks as its successors. 1405 while(!BB->succ_empty()) 1406 BB->removeSuccessor(BB->succ_begin()); 1407 BB->addSuccessor(copy0MBB); 1408 BB->addSuccessor(sinkMBB); 1409 1410 // copy0MBB: 1411 // %FalseValue = ... 1412 // # fallthrough to sinkMBB 1413 BB = copy0MBB; 1414 1415 // Update machine-CFG edges 1416 BB->addSuccessor(sinkMBB); 1417 1418 // sinkMBB: 1419 // %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ] 1420 // ... 1421 BB = sinkMBB; 1422 BuildMI(BB, TII->get(ARM::PHI), MI->getOperand(0).getReg()) 1423 .addReg(MI->getOperand(1).getReg()).addMBB(copy0MBB) 1424 .addReg(MI->getOperand(2).getReg()).addMBB(thisMBB); 1425 1426 delete MI; // The pseudo instruction is gone now. 1427 return BB; 1428 } 1429 } 1430} 1431 1432//===----------------------------------------------------------------------===// 1433// ARM Optimization Hooks 1434//===----------------------------------------------------------------------===// 1435 1436/// isLegalAddressImmediate - Return true if the integer value can be used 1437/// as the offset of the target addressing mode for load / store of the 1438/// given type. 1439static bool isLegalAddressImmediate(int64_t V, MVT::ValueType VT, 1440 const ARMSubtarget *Subtarget) { 1441 if (V == 0) 1442 return true; 1443 1444 if (Subtarget->isThumb()) { 1445 if (V < 0) 1446 return false; 1447 1448 unsigned Scale = 1; 1449 switch (VT) { 1450 default: return false; 1451 case MVT::i1: 1452 case MVT::i8: 1453 // Scale == 1; 1454 break; 1455 case MVT::i16: 1456 // Scale == 2; 1457 Scale = 2; 1458 break; 1459 case MVT::i32: 1460 // Scale == 4; 1461 Scale = 4; 1462 break; 1463 } 1464 1465 if ((V & (Scale - 1)) != 0) 1466 return false; 1467 V /= Scale; 1468 return V == V & ((1LL << 5) - 1); 1469 } 1470 1471 if (V < 0) 1472 V = - V; 1473 switch (VT) { 1474 default: return false; 1475 case MVT::i1: 1476 case MVT::i8: 1477 case MVT::i32: 1478 // +- imm12 1479 return V == V & ((1LL << 12) - 1); 1480 case MVT::i16: 1481 // +- imm8 1482 return V == V & ((1LL << 8) - 1); 1483 case MVT::f32: 1484 case MVT::f64: 1485 if (!Subtarget->hasVFP2()) 1486 return false; 1487 if ((V & 3) != 0) 1488 return false; 1489 V >>= 2; 1490 return V == V & ((1LL << 8) - 1); 1491 } 1492} 1493 1494/// isLegalAddressingMode - Return true if the addressing mode represented 1495/// by AM is legal for this target, for a load/store of the specified type. 1496bool ARMTargetLowering::isLegalAddressingMode(const AddrMode &AM, 1497 const Type *Ty) const { 1498 if (!isLegalAddressImmediate(AM.BaseOffs, getValueType(Ty), Subtarget)) 1499 return false; 1500 1501 // Can never fold addr of global into load/store. 1502 if (AM.BaseGV) 1503 return false; 1504 1505 switch (AM.Scale) { 1506 case 0: // no scale reg, must be "r+i" or "r", or "i". 1507 break; 1508 case 1: 1509 if (Subtarget->isThumb()) 1510 return false; 1511 // FALL THROUGH. 1512 default: 1513 // ARM doesn't support any R+R*scale+imm addr modes. 1514 if (AM.BaseOffs) 1515 return false; 1516 1517 int Scale = AM.Scale; 1518 switch (getValueType(Ty)) { 1519 default: return false; 1520 case MVT::i1: 1521 case MVT::i8: 1522 case MVT::i32: 1523 case MVT::i64: 1524 // This assumes i64 is legalized to a pair of i32. If not (i.e. 1525 // ldrd / strd are used, then its address mode is same as i16. 1526 // r + r 1527 if (Scale < 0) Scale = -Scale; 1528 if (Scale == 1) 1529 return true; 1530 // r + r << imm 1531 return isPowerOf2_32(Scale & ~1); 1532 case MVT::i16: 1533 // r + r 1534 if (((unsigned)AM.HasBaseReg + Scale) <= 2) 1535 return true; 1536 return false; 1537 1538 case MVT::isVoid: 1539 // Note, we allow "void" uses (basically, uses that aren't loads or 1540 // stores), because arm allows folding a scale into many arithmetic 1541 // operations. This should be made more precise and revisited later. 1542 1543 // Allow r << imm, but the imm has to be a multiple of two. 1544 if (AM.Scale & 1) return false; 1545 return isPowerOf2_32(AM.Scale); 1546 } 1547 break; 1548 } 1549 return true; 1550} 1551 1552 1553static bool getIndexedAddressParts(SDNode *Ptr, MVT::ValueType VT, 1554 bool isSEXTLoad, SDOperand &Base, 1555 SDOperand &Offset, bool &isInc, 1556 SelectionDAG &DAG) { 1557 if (Ptr->getOpcode() != ISD::ADD && Ptr->getOpcode() != ISD::SUB) 1558 return false; 1559 1560 if (VT == MVT::i16 || ((VT == MVT::i8 || VT == MVT::i1) && isSEXTLoad)) { 1561 // AddressingMode 3 1562 Base = Ptr->getOperand(0); 1563 if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(Ptr->getOperand(1))) { 1564 int RHSC = (int)RHS->getValue(); 1565 if (RHSC < 0 && RHSC > -256) { 1566 isInc = false; 1567 Offset = DAG.getConstant(-RHSC, RHS->getValueType(0)); 1568 return true; 1569 } 1570 } 1571 isInc = (Ptr->getOpcode() == ISD::ADD); 1572 Offset = Ptr->getOperand(1); 1573 return true; 1574 } else if (VT == MVT::i32 || VT == MVT::i8 || VT == MVT::i1) { 1575 // AddressingMode 2 1576 if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(Ptr->getOperand(1))) { 1577 int RHSC = (int)RHS->getValue(); 1578 if (RHSC < 0 && RHSC > -0x1000) { 1579 isInc = false; 1580 Offset = DAG.getConstant(-RHSC, RHS->getValueType(0)); 1581 Base = Ptr->getOperand(0); 1582 return true; 1583 } 1584 } 1585 1586 if (Ptr->getOpcode() == ISD::ADD) { 1587 isInc = true; 1588 ARM_AM::ShiftOpc ShOpcVal= ARM_AM::getShiftOpcForNode(Ptr->getOperand(0)); 1589 if (ShOpcVal != ARM_AM::no_shift) { 1590 Base = Ptr->getOperand(1); 1591 Offset = Ptr->getOperand(0); 1592 } else { 1593 Base = Ptr->getOperand(0); 1594 Offset = Ptr->getOperand(1); 1595 } 1596 return true; 1597 } 1598 1599 isInc = (Ptr->getOpcode() == ISD::ADD); 1600 Base = Ptr->getOperand(0); 1601 Offset = Ptr->getOperand(1); 1602 return true; 1603 } 1604 1605 // FIXME: Use FLDM / FSTM to emulate indexed FP load / store. 1606 return false; 1607} 1608 1609/// getPreIndexedAddressParts - returns true by value, base pointer and 1610/// offset pointer and addressing mode by reference if the node's address 1611/// can be legally represented as pre-indexed load / store address. 1612bool 1613ARMTargetLowering::getPreIndexedAddressParts(SDNode *N, SDOperand &Base, 1614 SDOperand &Offset, 1615 ISD::MemIndexedMode &AM, 1616 SelectionDAG &DAG) { 1617 if (Subtarget->isThumb()) 1618 return false; 1619 1620 MVT::ValueType VT; 1621 SDOperand Ptr; 1622 bool isSEXTLoad = false; 1623 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) { 1624 Ptr = LD->getBasePtr(); 1625 VT = LD->getLoadedVT(); 1626 isSEXTLoad = LD->getExtensionType() == ISD::SEXTLOAD; 1627 } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) { 1628 Ptr = ST->getBasePtr(); 1629 VT = ST->getStoredVT(); 1630 } else 1631 return false; 1632 1633 bool isInc; 1634 bool isLegal = getIndexedAddressParts(Ptr.Val, VT, isSEXTLoad, Base, Offset, 1635 isInc, DAG); 1636 if (isLegal) { 1637 AM = isInc ? ISD::PRE_INC : ISD::PRE_DEC; 1638 return true; 1639 } 1640 return false; 1641} 1642 1643/// getPostIndexedAddressParts - returns true by value, base pointer and 1644/// offset pointer and addressing mode by reference if this node can be 1645/// combined with a load / store to form a post-indexed load / store. 1646bool ARMTargetLowering::getPostIndexedAddressParts(SDNode *N, SDNode *Op, 1647 SDOperand &Base, 1648 SDOperand &Offset, 1649 ISD::MemIndexedMode &AM, 1650 SelectionDAG &DAG) { 1651 if (Subtarget->isThumb()) 1652 return false; 1653 1654 MVT::ValueType VT; 1655 SDOperand Ptr; 1656 bool isSEXTLoad = false; 1657 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) { 1658 VT = LD->getLoadedVT(); 1659 isSEXTLoad = LD->getExtensionType() == ISD::SEXTLOAD; 1660 } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) { 1661 VT = ST->getStoredVT(); 1662 } else 1663 return false; 1664 1665 bool isInc; 1666 bool isLegal = getIndexedAddressParts(Op, VT, isSEXTLoad, Base, Offset, 1667 isInc, DAG); 1668 if (isLegal) { 1669 AM = isInc ? ISD::POST_INC : ISD::POST_DEC; 1670 return true; 1671 } 1672 return false; 1673} 1674 1675void ARMTargetLowering::computeMaskedBitsForTargetNode(const SDOperand Op, 1676 uint64_t Mask, 1677 uint64_t &KnownZero, 1678 uint64_t &KnownOne, 1679 unsigned Depth) const { 1680 KnownZero = 0; 1681 KnownOne = 0; 1682 switch (Op.getOpcode()) { 1683 default: break; 1684 case ARMISD::CMOV: { 1685 // Bits are known zero/one if known on the LHS and RHS. 1686 ComputeMaskedBits(Op.getOperand(0), Mask, KnownZero, KnownOne, Depth+1); 1687 if (KnownZero == 0 && KnownOne == 0) return; 1688 1689 uint64_t KnownZeroRHS, KnownOneRHS; 1690 ComputeMaskedBits(Op.getOperand(1), Mask, 1691 KnownZeroRHS, KnownOneRHS, Depth+1); 1692 KnownZero &= KnownZeroRHS; 1693 KnownOne &= KnownOneRHS; 1694 return; 1695 } 1696 } 1697} 1698 1699//===----------------------------------------------------------------------===// 1700// ARM Inline Assembly Support 1701//===----------------------------------------------------------------------===// 1702 1703/// getConstraintType - Given a constraint letter, return the type of 1704/// constraint it is for this target. 1705ARMTargetLowering::ConstraintType 1706ARMTargetLowering::getConstraintType(const std::string &Constraint) const { 1707 if (Constraint.size() == 1) { 1708 switch (Constraint[0]) { 1709 default: break; 1710 case 'l': return C_RegisterClass; 1711 case 'w': return C_RegisterClass; 1712 } 1713 } 1714 return TargetLowering::getConstraintType(Constraint); 1715} 1716 1717std::pair<unsigned, const TargetRegisterClass*> 1718ARMTargetLowering::getRegForInlineAsmConstraint(const std::string &Constraint, 1719 MVT::ValueType VT) const { 1720 if (Constraint.size() == 1) { 1721 // GCC RS6000 Constraint Letters 1722 switch (Constraint[0]) { 1723 case 'l': 1724 // FIXME: in thumb mode, 'l' is only low-regs. 1725 // FALL THROUGH. 1726 case 'r': 1727 return std::make_pair(0U, ARM::GPRRegisterClass); 1728 case 'w': 1729 if (VT == MVT::f32) 1730 return std::make_pair(0U, ARM::SPRRegisterClass); 1731 if (VT == MVT::f64) 1732 return std::make_pair(0U, ARM::DPRRegisterClass); 1733 break; 1734 } 1735 } 1736 return TargetLowering::getRegForInlineAsmConstraint(Constraint, VT); 1737} 1738 1739std::vector<unsigned> ARMTargetLowering:: 1740getRegClassForInlineAsmConstraint(const std::string &Constraint, 1741 MVT::ValueType VT) const { 1742 if (Constraint.size() != 1) 1743 return std::vector<unsigned>(); 1744 1745 switch (Constraint[0]) { // GCC ARM Constraint Letters 1746 default: break; 1747 case 'l': 1748 case 'r': 1749 return make_vector<unsigned>(ARM::R0, ARM::R1, ARM::R2, ARM::R3, 1750 ARM::R4, ARM::R5, ARM::R6, ARM::R7, 1751 ARM::R8, ARM::R9, ARM::R10, ARM::R11, 1752 ARM::R12, ARM::LR, 0); 1753 case 'w': 1754 if (VT == MVT::f32) 1755 return make_vector<unsigned>(ARM::S0, ARM::S1, ARM::S2, ARM::S3, 1756 ARM::S4, ARM::S5, ARM::S6, ARM::S7, 1757 ARM::S8, ARM::S9, ARM::S10, ARM::S11, 1758 ARM::S12,ARM::S13,ARM::S14,ARM::S15, 1759 ARM::S16,ARM::S17,ARM::S18,ARM::S19, 1760 ARM::S20,ARM::S21,ARM::S22,ARM::S23, 1761 ARM::S24,ARM::S25,ARM::S26,ARM::S27, 1762 ARM::S28,ARM::S29,ARM::S30,ARM::S31, 0); 1763 if (VT == MVT::f64) 1764 return make_vector<unsigned>(ARM::D0, ARM::D1, ARM::D2, ARM::D3, 1765 ARM::D4, ARM::D5, ARM::D6, ARM::D7, 1766 ARM::D8, ARM::D9, ARM::D10,ARM::D11, 1767 ARM::D12,ARM::D13,ARM::D14,ARM::D15, 0); 1768 break; 1769 } 1770 1771 return std::vector<unsigned>(); 1772} 1773