ARMISelLowering.cpp revision e637db117eb826a539e230590ee6a5db585f1ffb
1//===-- ARMISelLowering.cpp - ARM DAG Lowering Implementation -------------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file defines the interfaces that ARM uses to lower LLVM code into a 11// selection DAG. 12// 13//===----------------------------------------------------------------------===// 14 15#include "ARM.h" 16#include "ARMAddressingModes.h" 17#include "ARMConstantPoolValue.h" 18#include "ARMISelLowering.h" 19#include "ARMMachineFunctionInfo.h" 20#include "ARMRegisterInfo.h" 21#include "ARMSubtarget.h" 22#include "ARMTargetMachine.h" 23#include "llvm/CallingConv.h" 24#include "llvm/Constants.h" 25#include "llvm/Instruction.h" 26#include "llvm/Intrinsics.h" 27#include "llvm/GlobalValue.h" 28#include "llvm/CodeGen/MachineBasicBlock.h" 29#include "llvm/CodeGen/MachineFrameInfo.h" 30#include "llvm/CodeGen/MachineFunction.h" 31#include "llvm/CodeGen/MachineInstrBuilder.h" 32#include "llvm/CodeGen/MachineRegisterInfo.h" 33#include "llvm/CodeGen/SelectionDAG.h" 34#include "llvm/Target/TargetOptions.h" 35#include "llvm/ADT/VectorExtras.h" 36#include "llvm/Support/MathExtras.h" 37using namespace llvm; 38 39ARMTargetLowering::ARMTargetLowering(TargetMachine &TM) 40 : TargetLowering(TM), ARMPCLabelIndex(0) { 41 Subtarget = &TM.getSubtarget<ARMSubtarget>(); 42 43 if (Subtarget->isTargetDarwin()) { 44 // Don't have these. 45 setLibcallName(RTLIB::UINTTOFP_I64_F32, NULL); 46 setLibcallName(RTLIB::UINTTOFP_I64_F64, NULL); 47 48 // Uses VFP for Thumb libfuncs if available. 49 if (Subtarget->isThumb() && Subtarget->hasVFP2()) { 50 // Single-precision floating-point arithmetic. 51 setLibcallName(RTLIB::ADD_F32, "__addsf3vfp"); 52 setLibcallName(RTLIB::SUB_F32, "__subsf3vfp"); 53 setLibcallName(RTLIB::MUL_F32, "__mulsf3vfp"); 54 setLibcallName(RTLIB::DIV_F32, "__divsf3vfp"); 55 56 // Double-precision floating-point arithmetic. 57 setLibcallName(RTLIB::ADD_F64, "__adddf3vfp"); 58 setLibcallName(RTLIB::SUB_F64, "__subdf3vfp"); 59 setLibcallName(RTLIB::MUL_F64, "__muldf3vfp"); 60 setLibcallName(RTLIB::DIV_F64, "__divdf3vfp"); 61 62 // Single-precision comparisons. 63 setLibcallName(RTLIB::OEQ_F32, "__eqsf2vfp"); 64 setLibcallName(RTLIB::UNE_F32, "__nesf2vfp"); 65 setLibcallName(RTLIB::OLT_F32, "__ltsf2vfp"); 66 setLibcallName(RTLIB::OLE_F32, "__lesf2vfp"); 67 setLibcallName(RTLIB::OGE_F32, "__gesf2vfp"); 68 setLibcallName(RTLIB::OGT_F32, "__gtsf2vfp"); 69 setLibcallName(RTLIB::UO_F32, "__unordsf2vfp"); 70 setLibcallName(RTLIB::O_F32, "__unordsf2vfp"); 71 72 setCmpLibcallCC(RTLIB::OEQ_F32, ISD::SETNE); 73 setCmpLibcallCC(RTLIB::UNE_F32, ISD::SETNE); 74 setCmpLibcallCC(RTLIB::OLT_F32, ISD::SETNE); 75 setCmpLibcallCC(RTLIB::OLE_F32, ISD::SETNE); 76 setCmpLibcallCC(RTLIB::OGE_F32, ISD::SETNE); 77 setCmpLibcallCC(RTLIB::OGT_F32, ISD::SETNE); 78 setCmpLibcallCC(RTLIB::UO_F32, ISD::SETNE); 79 setCmpLibcallCC(RTLIB::O_F32, ISD::SETEQ); 80 81 // Double-precision comparisons. 82 setLibcallName(RTLIB::OEQ_F64, "__eqdf2vfp"); 83 setLibcallName(RTLIB::UNE_F64, "__nedf2vfp"); 84 setLibcallName(RTLIB::OLT_F64, "__ltdf2vfp"); 85 setLibcallName(RTLIB::OLE_F64, "__ledf2vfp"); 86 setLibcallName(RTLIB::OGE_F64, "__gedf2vfp"); 87 setLibcallName(RTLIB::OGT_F64, "__gtdf2vfp"); 88 setLibcallName(RTLIB::UO_F64, "__unorddf2vfp"); 89 setLibcallName(RTLIB::O_F64, "__unorddf2vfp"); 90 91 setCmpLibcallCC(RTLIB::OEQ_F64, ISD::SETNE); 92 setCmpLibcallCC(RTLIB::UNE_F64, ISD::SETNE); 93 setCmpLibcallCC(RTLIB::OLT_F64, ISD::SETNE); 94 setCmpLibcallCC(RTLIB::OLE_F64, ISD::SETNE); 95 setCmpLibcallCC(RTLIB::OGE_F64, ISD::SETNE); 96 setCmpLibcallCC(RTLIB::OGT_F64, ISD::SETNE); 97 setCmpLibcallCC(RTLIB::UO_F64, ISD::SETNE); 98 setCmpLibcallCC(RTLIB::O_F64, ISD::SETEQ); 99 100 // Floating-point to integer conversions. 101 // i64 conversions are done via library routines even when generating VFP 102 // instructions, so use the same ones. 103 setLibcallName(RTLIB::FPTOSINT_F64_I32, "__fixdfsivfp"); 104 setLibcallName(RTLIB::FPTOUINT_F64_I32, "__fixunsdfsivfp"); 105 setLibcallName(RTLIB::FPTOSINT_F32_I32, "__fixsfsivfp"); 106 setLibcallName(RTLIB::FPTOUINT_F32_I32, "__fixunssfsivfp"); 107 108 // Conversions between floating types. 109 setLibcallName(RTLIB::FPROUND_F64_F32, "__truncdfsf2vfp"); 110 setLibcallName(RTLIB::FPEXT_F32_F64, "__extendsfdf2vfp"); 111 112 // Integer to floating-point conversions. 113 // i64 conversions are done via library routines even when generating VFP 114 // instructions, so use the same ones. 115 // FIXME: There appears to be some naming inconsistency in ARM libgcc: e.g. 116 // __floatunsidf vs. __floatunssidfvfp. 117 setLibcallName(RTLIB::SINTTOFP_I32_F64, "__floatsidfvfp"); 118 setLibcallName(RTLIB::UINTTOFP_I32_F64, "__floatunssidfvfp"); 119 setLibcallName(RTLIB::SINTTOFP_I32_F32, "__floatsisfvfp"); 120 setLibcallName(RTLIB::UINTTOFP_I32_F32, "__floatunssisfvfp"); 121 } 122 } 123 124 addRegisterClass(MVT::i32, ARM::GPRRegisterClass); 125 if (!UseSoftFloat && Subtarget->hasVFP2() && !Subtarget->isThumb()) { 126 addRegisterClass(MVT::f32, ARM::SPRRegisterClass); 127 addRegisterClass(MVT::f64, ARM::DPRRegisterClass); 128 129 setTruncStoreAction(MVT::f64, MVT::f32, Expand); 130 } 131 computeRegisterProperties(); 132 133 // ARM does not have f32 extending load. 134 setLoadXAction(ISD::EXTLOAD, MVT::f32, Expand); 135 136 // ARM does not have i1 sign extending load. 137 setLoadXAction(ISD::SEXTLOAD, MVT::i1, Promote); 138 139 // ARM supports all 4 flavors of integer indexed load / store. 140 for (unsigned im = (unsigned)ISD::PRE_INC; 141 im != (unsigned)ISD::LAST_INDEXED_MODE; ++im) { 142 setIndexedLoadAction(im, MVT::i1, Legal); 143 setIndexedLoadAction(im, MVT::i8, Legal); 144 setIndexedLoadAction(im, MVT::i16, Legal); 145 setIndexedLoadAction(im, MVT::i32, Legal); 146 setIndexedStoreAction(im, MVT::i1, Legal); 147 setIndexedStoreAction(im, MVT::i8, Legal); 148 setIndexedStoreAction(im, MVT::i16, Legal); 149 setIndexedStoreAction(im, MVT::i32, Legal); 150 } 151 152 // i64 operation support. 153 if (Subtarget->isThumb()) { 154 setOperationAction(ISD::MUL, MVT::i64, Expand); 155 setOperationAction(ISD::MULHU, MVT::i32, Expand); 156 setOperationAction(ISD::MULHS, MVT::i32, Expand); 157 setOperationAction(ISD::UMUL_LOHI, MVT::i32, Expand); 158 setOperationAction(ISD::SMUL_LOHI, MVT::i32, Expand); 159 } else { 160 setOperationAction(ISD::MUL, MVT::i64, Expand); 161 setOperationAction(ISD::MULHU, MVT::i32, Expand); 162 if (!Subtarget->hasV6Ops()) 163 setOperationAction(ISD::MULHS, MVT::i32, Expand); 164 } 165 setOperationAction(ISD::SHL_PARTS, MVT::i32, Expand); 166 setOperationAction(ISD::SRA_PARTS, MVT::i32, Expand); 167 setOperationAction(ISD::SRL_PARTS, MVT::i32, Expand); 168 setOperationAction(ISD::SRL, MVT::i64, Custom); 169 setOperationAction(ISD::SRA, MVT::i64, Custom); 170 171 // ARM does not have ROTL. 172 setOperationAction(ISD::ROTL, MVT::i32, Expand); 173 setOperationAction(ISD::CTTZ , MVT::i32, Expand); 174 setOperationAction(ISD::CTPOP, MVT::i32, Expand); 175 if (!Subtarget->hasV5TOps() || Subtarget->isThumb()) 176 setOperationAction(ISD::CTLZ, MVT::i32, Expand); 177 178 // Only ARMv6 has BSWAP. 179 if (!Subtarget->hasV6Ops()) 180 setOperationAction(ISD::BSWAP, MVT::i32, Expand); 181 182 // These are expanded into libcalls. 183 setOperationAction(ISD::SDIV, MVT::i32, Expand); 184 setOperationAction(ISD::UDIV, MVT::i32, Expand); 185 setOperationAction(ISD::SREM, MVT::i32, Expand); 186 setOperationAction(ISD::UREM, MVT::i32, Expand); 187 setOperationAction(ISD::SDIVREM, MVT::i32, Expand); 188 setOperationAction(ISD::UDIVREM, MVT::i32, Expand); 189 190 // Support label based line numbers. 191 setOperationAction(ISD::LOCATION, MVT::Other, Expand); 192 setOperationAction(ISD::DEBUG_LOC, MVT::Other, Expand); 193 194 setOperationAction(ISD::RET, MVT::Other, Custom); 195 setOperationAction(ISD::GlobalAddress, MVT::i32, Custom); 196 setOperationAction(ISD::ConstantPool, MVT::i32, Custom); 197 setOperationAction(ISD::GLOBAL_OFFSET_TABLE, MVT::i32, Custom); 198 setOperationAction(ISD::GlobalTLSAddress, MVT::i32, Custom); 199 200 // Expand mem operations genericly. 201 setOperationAction(ISD::MEMSET , MVT::Other, Expand); 202 setOperationAction(ISD::MEMCPY , MVT::Other, Custom); 203 setOperationAction(ISD::MEMMOVE , MVT::Other, Expand); 204 205 // Use the default implementation. 206 setOperationAction(ISD::VASTART , MVT::Other, Expand); 207 setOperationAction(ISD::VAARG , MVT::Other, Expand); 208 setOperationAction(ISD::VACOPY , MVT::Other, Expand); 209 setOperationAction(ISD::VAEND , MVT::Other, Expand); 210 setOperationAction(ISD::STACKSAVE, MVT::Other, Expand); 211 setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand); 212 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32 , Expand); 213 214 if (!Subtarget->hasV6Ops()) { 215 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16, Expand); 216 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8, Expand); 217 } 218 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand); 219 220 if (!UseSoftFloat && Subtarget->hasVFP2() && !Subtarget->isThumb()) 221 // Turn f64->i64 into FMRRD iff target supports vfp2. 222 setOperationAction(ISD::BIT_CONVERT, MVT::i64, Custom); 223 224 // We want to custom lower some of our intrinsics. 225 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom); 226 227 setOperationAction(ISD::SETCC , MVT::i32, Expand); 228 setOperationAction(ISD::SETCC , MVT::f32, Expand); 229 setOperationAction(ISD::SETCC , MVT::f64, Expand); 230 setOperationAction(ISD::SELECT , MVT::i32, Expand); 231 setOperationAction(ISD::SELECT , MVT::f32, Expand); 232 setOperationAction(ISD::SELECT , MVT::f64, Expand); 233 setOperationAction(ISD::SELECT_CC, MVT::i32, Custom); 234 setOperationAction(ISD::SELECT_CC, MVT::f32, Custom); 235 setOperationAction(ISD::SELECT_CC, MVT::f64, Custom); 236 237 setOperationAction(ISD::BRCOND , MVT::Other, Expand); 238 setOperationAction(ISD::BR_CC , MVT::i32, Custom); 239 setOperationAction(ISD::BR_CC , MVT::f32, Custom); 240 setOperationAction(ISD::BR_CC , MVT::f64, Custom); 241 setOperationAction(ISD::BR_JT , MVT::Other, Custom); 242 243 setOperationAction(ISD::VASTART, MVT::Other, Custom); 244 setOperationAction(ISD::VACOPY, MVT::Other, Expand); 245 setOperationAction(ISD::VAEND, MVT::Other, Expand); 246 setOperationAction(ISD::STACKSAVE, MVT::Other, Expand); 247 setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand); 248 249 // FP Constants can't be immediates. 250 setOperationAction(ISD::ConstantFP, MVT::f64, Expand); 251 setOperationAction(ISD::ConstantFP, MVT::f32, Expand); 252 253 // We don't support sin/cos/fmod/copysign/pow 254 setOperationAction(ISD::FSIN , MVT::f64, Expand); 255 setOperationAction(ISD::FSIN , MVT::f32, Expand); 256 setOperationAction(ISD::FCOS , MVT::f32, Expand); 257 setOperationAction(ISD::FCOS , MVT::f64, Expand); 258 setOperationAction(ISD::FREM , MVT::f64, Expand); 259 setOperationAction(ISD::FREM , MVT::f32, Expand); 260 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Custom); 261 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom); 262 setOperationAction(ISD::FPOW , MVT::f64, Expand); 263 setOperationAction(ISD::FPOW , MVT::f32, Expand); 264 265 // int <-> fp are custom expanded into bit_convert + ARMISD ops. 266 setOperationAction(ISD::SINT_TO_FP, MVT::i32, Custom); 267 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Custom); 268 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Custom); 269 setOperationAction(ISD::FP_TO_SINT, MVT::i32, Custom); 270 271 // We have target-specific dag combine patterns for the following nodes: 272 // ARMISD::FMRRD - No need to call setTargetDAGCombine 273 274 setStackPointerRegisterToSaveRestore(ARM::SP); 275 setSchedulingPreference(SchedulingForRegPressure); 276 setIfCvtBlockSizeLimit(Subtarget->isThumb() ? 0 : 10); 277 setIfCvtDupBlockSizeLimit(Subtarget->isThumb() ? 0 : 2); 278 279 maxStoresPerMemcpy = 1; //// temporary - rewrite interface to use type 280} 281 282 283const char *ARMTargetLowering::getTargetNodeName(unsigned Opcode) const { 284 switch (Opcode) { 285 default: return 0; 286 case ARMISD::Wrapper: return "ARMISD::Wrapper"; 287 case ARMISD::WrapperJT: return "ARMISD::WrapperJT"; 288 case ARMISD::CALL: return "ARMISD::CALL"; 289 case ARMISD::CALL_PRED: return "ARMISD::CALL_PRED"; 290 case ARMISD::CALL_NOLINK: return "ARMISD::CALL_NOLINK"; 291 case ARMISD::tCALL: return "ARMISD::tCALL"; 292 case ARMISD::BRCOND: return "ARMISD::BRCOND"; 293 case ARMISD::BR_JT: return "ARMISD::BR_JT"; 294 case ARMISD::RET_FLAG: return "ARMISD::RET_FLAG"; 295 case ARMISD::PIC_ADD: return "ARMISD::PIC_ADD"; 296 case ARMISD::CMP: return "ARMISD::CMP"; 297 case ARMISD::CMPNZ: return "ARMISD::CMPNZ"; 298 case ARMISD::CMPFP: return "ARMISD::CMPFP"; 299 case ARMISD::CMPFPw0: return "ARMISD::CMPFPw0"; 300 case ARMISD::FMSTAT: return "ARMISD::FMSTAT"; 301 case ARMISD::CMOV: return "ARMISD::CMOV"; 302 case ARMISD::CNEG: return "ARMISD::CNEG"; 303 304 case ARMISD::FTOSI: return "ARMISD::FTOSI"; 305 case ARMISD::FTOUI: return "ARMISD::FTOUI"; 306 case ARMISD::SITOF: return "ARMISD::SITOF"; 307 case ARMISD::UITOF: return "ARMISD::UITOF"; 308 309 case ARMISD::SRL_FLAG: return "ARMISD::SRL_FLAG"; 310 case ARMISD::SRA_FLAG: return "ARMISD::SRA_FLAG"; 311 case ARMISD::RRX: return "ARMISD::RRX"; 312 313 case ARMISD::FMRRD: return "ARMISD::FMRRD"; 314 case ARMISD::FMDRR: return "ARMISD::FMDRR"; 315 316 case ARMISD::THREAD_POINTER:return "ARMISD::THREAD_POINTER"; 317 } 318} 319 320//===----------------------------------------------------------------------===// 321// Lowering Code 322//===----------------------------------------------------------------------===// 323 324 325/// IntCCToARMCC - Convert a DAG integer condition code to an ARM CC 326static ARMCC::CondCodes IntCCToARMCC(ISD::CondCode CC) { 327 switch (CC) { 328 default: assert(0 && "Unknown condition code!"); 329 case ISD::SETNE: return ARMCC::NE; 330 case ISD::SETEQ: return ARMCC::EQ; 331 case ISD::SETGT: return ARMCC::GT; 332 case ISD::SETGE: return ARMCC::GE; 333 case ISD::SETLT: return ARMCC::LT; 334 case ISD::SETLE: return ARMCC::LE; 335 case ISD::SETUGT: return ARMCC::HI; 336 case ISD::SETUGE: return ARMCC::HS; 337 case ISD::SETULT: return ARMCC::LO; 338 case ISD::SETULE: return ARMCC::LS; 339 } 340} 341 342/// FPCCToARMCC - Convert a DAG fp condition code to an ARM CC. It 343/// returns true if the operands should be inverted to form the proper 344/// comparison. 345static bool FPCCToARMCC(ISD::CondCode CC, ARMCC::CondCodes &CondCode, 346 ARMCC::CondCodes &CondCode2) { 347 bool Invert = false; 348 CondCode2 = ARMCC::AL; 349 switch (CC) { 350 default: assert(0 && "Unknown FP condition!"); 351 case ISD::SETEQ: 352 case ISD::SETOEQ: CondCode = ARMCC::EQ; break; 353 case ISD::SETGT: 354 case ISD::SETOGT: CondCode = ARMCC::GT; break; 355 case ISD::SETGE: 356 case ISD::SETOGE: CondCode = ARMCC::GE; break; 357 case ISD::SETOLT: CondCode = ARMCC::MI; break; 358 case ISD::SETOLE: CondCode = ARMCC::GT; Invert = true; break; 359 case ISD::SETONE: CondCode = ARMCC::MI; CondCode2 = ARMCC::GT; break; 360 case ISD::SETO: CondCode = ARMCC::VC; break; 361 case ISD::SETUO: CondCode = ARMCC::VS; break; 362 case ISD::SETUEQ: CondCode = ARMCC::EQ; CondCode2 = ARMCC::VS; break; 363 case ISD::SETUGT: CondCode = ARMCC::HI; break; 364 case ISD::SETUGE: CondCode = ARMCC::PL; break; 365 case ISD::SETLT: 366 case ISD::SETULT: CondCode = ARMCC::LT; break; 367 case ISD::SETLE: 368 case ISD::SETULE: CondCode = ARMCC::LE; break; 369 case ISD::SETNE: 370 case ISD::SETUNE: CondCode = ARMCC::NE; break; 371 } 372 return Invert; 373} 374 375static void 376HowToPassArgument(MVT::ValueType ObjectVT, unsigned NumGPRs, 377 unsigned StackOffset, unsigned &NeededGPRs, 378 unsigned &NeededStackSize, unsigned &GPRPad, 379 unsigned &StackPad, unsigned Flags) { 380 NeededStackSize = 0; 381 NeededGPRs = 0; 382 StackPad = 0; 383 GPRPad = 0; 384 unsigned align = (Flags >> ISD::ParamFlags::OrigAlignmentOffs); 385 GPRPad = NumGPRs % ((align + 3)/4); 386 StackPad = StackOffset % align; 387 unsigned firstGPR = NumGPRs + GPRPad; 388 switch (ObjectVT) { 389 default: assert(0 && "Unhandled argument type!"); 390 case MVT::i32: 391 case MVT::f32: 392 if (firstGPR < 4) 393 NeededGPRs = 1; 394 else 395 NeededStackSize = 4; 396 break; 397 case MVT::i64: 398 case MVT::f64: 399 if (firstGPR < 3) 400 NeededGPRs = 2; 401 else if (firstGPR == 3) { 402 NeededGPRs = 1; 403 NeededStackSize = 4; 404 } else 405 NeededStackSize = 8; 406 } 407} 408 409/// LowerCALL - Lowering a ISD::CALL node into a callseq_start <- 410/// ARMISD:CALL <- callseq_end chain. Also add input and output parameter 411/// nodes. 412SDOperand ARMTargetLowering::LowerCALL(SDOperand Op, SelectionDAG &DAG) { 413 MVT::ValueType RetVT= Op.Val->getValueType(0); 414 SDOperand Chain = Op.getOperand(0); 415 unsigned CallConv = cast<ConstantSDNode>(Op.getOperand(1))->getValue(); 416 assert((CallConv == CallingConv::C || 417 CallConv == CallingConv::Fast) && "unknown calling convention"); 418 SDOperand Callee = Op.getOperand(4); 419 unsigned NumOps = (Op.getNumOperands() - 5) / 2; 420 unsigned ArgOffset = 0; // Frame mechanisms handle retaddr slot 421 unsigned NumGPRs = 0; // GPRs used for parameter passing. 422 423 // Count how many bytes are to be pushed on the stack. 424 unsigned NumBytes = 0; 425 426 // Add up all the space actually used. 427 for (unsigned i = 0; i < NumOps; ++i) { 428 unsigned ObjSize; 429 unsigned ObjGPRs; 430 unsigned StackPad; 431 unsigned GPRPad; 432 MVT::ValueType ObjectVT = Op.getOperand(5+2*i).getValueType(); 433 unsigned Flags = Op.getConstantOperandVal(5+2*i+1); 434 HowToPassArgument(ObjectVT, NumGPRs, NumBytes, ObjGPRs, ObjSize, 435 GPRPad, StackPad, Flags); 436 NumBytes += ObjSize + StackPad; 437 NumGPRs += ObjGPRs + GPRPad; 438 } 439 440 // Adjust the stack pointer for the new arguments... 441 // These operations are automatically eliminated by the prolog/epilog pass 442 Chain = DAG.getCALLSEQ_START(Chain, 443 DAG.getConstant(NumBytes, MVT::i32)); 444 445 SDOperand StackPtr = DAG.getRegister(ARM::SP, MVT::i32); 446 447 static const unsigned GPRArgRegs[] = { 448 ARM::R0, ARM::R1, ARM::R2, ARM::R3 449 }; 450 451 NumGPRs = 0; 452 std::vector<std::pair<unsigned, SDOperand> > RegsToPass; 453 std::vector<SDOperand> MemOpChains; 454 for (unsigned i = 0; i != NumOps; ++i) { 455 SDOperand Arg = Op.getOperand(5+2*i); 456 unsigned Flags = Op.getConstantOperandVal(5+2*i+1); 457 MVT::ValueType ArgVT = Arg.getValueType(); 458 459 unsigned ObjSize; 460 unsigned ObjGPRs; 461 unsigned GPRPad; 462 unsigned StackPad; 463 HowToPassArgument(ArgVT, NumGPRs, ArgOffset, ObjGPRs, 464 ObjSize, GPRPad, StackPad, Flags); 465 NumGPRs += GPRPad; 466 ArgOffset += StackPad; 467 if (ObjGPRs > 0) { 468 switch (ArgVT) { 469 default: assert(0 && "Unexpected ValueType for argument!"); 470 case MVT::i32: 471 RegsToPass.push_back(std::make_pair(GPRArgRegs[NumGPRs], Arg)); 472 break; 473 case MVT::f32: 474 RegsToPass.push_back(std::make_pair(GPRArgRegs[NumGPRs], 475 DAG.getNode(ISD::BIT_CONVERT, MVT::i32, Arg))); 476 break; 477 case MVT::i64: { 478 SDOperand Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32, Arg, 479 DAG.getConstant(0, getPointerTy())); 480 SDOperand Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32, Arg, 481 DAG.getConstant(1, getPointerTy())); 482 RegsToPass.push_back(std::make_pair(GPRArgRegs[NumGPRs], Lo)); 483 if (ObjGPRs == 2) 484 RegsToPass.push_back(std::make_pair(GPRArgRegs[NumGPRs+1], Hi)); 485 else { 486 SDOperand PtrOff= DAG.getConstant(ArgOffset, StackPtr.getValueType()); 487 PtrOff = DAG.getNode(ISD::ADD, MVT::i32, StackPtr, PtrOff); 488 MemOpChains.push_back(DAG.getStore(Chain, Hi, PtrOff, NULL, 0)); 489 } 490 break; 491 } 492 case MVT::f64: { 493 SDOperand Cvt = DAG.getNode(ARMISD::FMRRD, 494 DAG.getVTList(MVT::i32, MVT::i32), 495 &Arg, 1); 496 RegsToPass.push_back(std::make_pair(GPRArgRegs[NumGPRs], Cvt)); 497 if (ObjGPRs == 2) 498 RegsToPass.push_back(std::make_pair(GPRArgRegs[NumGPRs+1], 499 Cvt.getValue(1))); 500 else { 501 SDOperand PtrOff= DAG.getConstant(ArgOffset, StackPtr.getValueType()); 502 PtrOff = DAG.getNode(ISD::ADD, MVT::i32, StackPtr, PtrOff); 503 MemOpChains.push_back(DAG.getStore(Chain, Cvt.getValue(1), PtrOff, 504 NULL, 0)); 505 } 506 break; 507 } 508 } 509 } else { 510 assert(ObjSize != 0); 511 SDOperand PtrOff = DAG.getConstant(ArgOffset, StackPtr.getValueType()); 512 PtrOff = DAG.getNode(ISD::ADD, MVT::i32, StackPtr, PtrOff); 513 MemOpChains.push_back(DAG.getStore(Chain, Arg, PtrOff, NULL, 0)); 514 } 515 516 NumGPRs += ObjGPRs; 517 ArgOffset += ObjSize; 518 } 519 520 if (!MemOpChains.empty()) 521 Chain = DAG.getNode(ISD::TokenFactor, MVT::Other, 522 &MemOpChains[0], MemOpChains.size()); 523 524 // Build a sequence of copy-to-reg nodes chained together with token chain 525 // and flag operands which copy the outgoing args into the appropriate regs. 526 SDOperand InFlag; 527 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) { 528 Chain = DAG.getCopyToReg(Chain, RegsToPass[i].first, RegsToPass[i].second, 529 InFlag); 530 InFlag = Chain.getValue(1); 531 } 532 533 // If the callee is a GlobalAddress/ExternalSymbol node (quite common, every 534 // direct call is) turn it into a TargetGlobalAddress/TargetExternalSymbol 535 // node so that legalize doesn't hack it. 536 bool isDirect = false; 537 bool isARMFunc = false; 538 bool isLocalARMFunc = false; 539 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) { 540 GlobalValue *GV = G->getGlobal(); 541 isDirect = true; 542 bool isExt = (GV->isDeclaration() || GV->hasWeakLinkage() || 543 GV->hasLinkOnceLinkage()); 544 bool isStub = (isExt && Subtarget->isTargetDarwin()) && 545 getTargetMachine().getRelocationModel() != Reloc::Static; 546 isARMFunc = !Subtarget->isThumb() || isStub; 547 // ARM call to a local ARM function is predicable. 548 isLocalARMFunc = !Subtarget->isThumb() && !isExt; 549 // tBX takes a register source operand. 550 if (isARMFunc && Subtarget->isThumb() && !Subtarget->hasV5TOps()) { 551 ARMConstantPoolValue *CPV = new ARMConstantPoolValue(GV, ARMPCLabelIndex, 552 ARMCP::CPStub, 4); 553 SDOperand CPAddr = DAG.getTargetConstantPool(CPV, getPointerTy(), 2); 554 CPAddr = DAG.getNode(ARMISD::Wrapper, MVT::i32, CPAddr); 555 Callee = DAG.getLoad(getPointerTy(), DAG.getEntryNode(), CPAddr, NULL, 0); 556 SDOperand PICLabel = DAG.getConstant(ARMPCLabelIndex++, MVT::i32); 557 Callee = DAG.getNode(ARMISD::PIC_ADD, getPointerTy(), Callee, PICLabel); 558 } else 559 Callee = DAG.getTargetGlobalAddress(GV, getPointerTy()); 560 } else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee)) { 561 isDirect = true; 562 bool isStub = Subtarget->isTargetDarwin() && 563 getTargetMachine().getRelocationModel() != Reloc::Static; 564 isARMFunc = !Subtarget->isThumb() || isStub; 565 // tBX takes a register source operand. 566 const char *Sym = S->getSymbol(); 567 if (isARMFunc && Subtarget->isThumb() && !Subtarget->hasV5TOps()) { 568 ARMConstantPoolValue *CPV = new ARMConstantPoolValue(Sym, ARMPCLabelIndex, 569 ARMCP::CPStub, 4); 570 SDOperand CPAddr = DAG.getTargetConstantPool(CPV, getPointerTy(), 2); 571 CPAddr = DAG.getNode(ARMISD::Wrapper, MVT::i32, CPAddr); 572 Callee = DAG.getLoad(getPointerTy(), DAG.getEntryNode(), CPAddr, NULL, 0); 573 SDOperand PICLabel = DAG.getConstant(ARMPCLabelIndex++, MVT::i32); 574 Callee = DAG.getNode(ARMISD::PIC_ADD, getPointerTy(), Callee, PICLabel); 575 } else 576 Callee = DAG.getTargetExternalSymbol(Sym, getPointerTy()); 577 } 578 579 // FIXME: handle tail calls differently. 580 unsigned CallOpc; 581 if (Subtarget->isThumb()) { 582 if (!Subtarget->hasV5TOps() && (!isDirect || isARMFunc)) 583 CallOpc = ARMISD::CALL_NOLINK; 584 else 585 CallOpc = isARMFunc ? ARMISD::CALL : ARMISD::tCALL; 586 } else { 587 CallOpc = (isDirect || Subtarget->hasV5TOps()) 588 ? (isLocalARMFunc ? ARMISD::CALL_PRED : ARMISD::CALL) 589 : ARMISD::CALL_NOLINK; 590 } 591 if (CallOpc == ARMISD::CALL_NOLINK && !Subtarget->isThumb()) { 592 // implicit def LR - LR mustn't be allocated as GRP:$dst of CALL_NOLINK 593 Chain = DAG.getCopyToReg(Chain, ARM::LR, 594 DAG.getNode(ISD::UNDEF, MVT::i32), InFlag); 595 InFlag = Chain.getValue(1); 596 } 597 598 std::vector<MVT::ValueType> NodeTys; 599 NodeTys.push_back(MVT::Other); // Returns a chain 600 NodeTys.push_back(MVT::Flag); // Returns a flag for retval copy to use. 601 602 std::vector<SDOperand> Ops; 603 Ops.push_back(Chain); 604 Ops.push_back(Callee); 605 606 // Add argument registers to the end of the list so that they are known live 607 // into the call. 608 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) 609 Ops.push_back(DAG.getRegister(RegsToPass[i].first, 610 RegsToPass[i].second.getValueType())); 611 612 if (InFlag.Val) 613 Ops.push_back(InFlag); 614 Chain = DAG.getNode(CallOpc, NodeTys, &Ops[0], Ops.size()); 615 InFlag = Chain.getValue(1); 616 617 Chain = DAG.getCALLSEQ_END(Chain, 618 DAG.getConstant(NumBytes, MVT::i32), 619 DAG.getConstant(0, MVT::i32), 620 InFlag); 621 if (RetVT != MVT::Other) 622 InFlag = Chain.getValue(1); 623 624 std::vector<SDOperand> ResultVals; 625 NodeTys.clear(); 626 627 // If the call has results, copy the values out of the ret val registers. 628 switch (RetVT) { 629 default: assert(0 && "Unexpected ret value!"); 630 case MVT::Other: 631 break; 632 case MVT::i32: 633 Chain = DAG.getCopyFromReg(Chain, ARM::R0, MVT::i32, InFlag).getValue(1); 634 ResultVals.push_back(Chain.getValue(0)); 635 if (Op.Val->getValueType(1) == MVT::i32) { 636 // Returns a i64 value. 637 Chain = DAG.getCopyFromReg(Chain, ARM::R1, MVT::i32, 638 Chain.getValue(2)).getValue(1); 639 ResultVals.push_back(Chain.getValue(0)); 640 NodeTys.push_back(MVT::i32); 641 } 642 NodeTys.push_back(MVT::i32); 643 break; 644 case MVT::f32: 645 Chain = DAG.getCopyFromReg(Chain, ARM::R0, MVT::i32, InFlag).getValue(1); 646 ResultVals.push_back(DAG.getNode(ISD::BIT_CONVERT, MVT::f32, 647 Chain.getValue(0))); 648 NodeTys.push_back(MVT::f32); 649 break; 650 case MVT::f64: { 651 SDOperand Lo = DAG.getCopyFromReg(Chain, ARM::R0, MVT::i32, InFlag); 652 SDOperand Hi = DAG.getCopyFromReg(Lo, ARM::R1, MVT::i32, Lo.getValue(2)); 653 ResultVals.push_back(DAG.getNode(ARMISD::FMDRR, MVT::f64, Lo, Hi)); 654 NodeTys.push_back(MVT::f64); 655 break; 656 } 657 } 658 659 NodeTys.push_back(MVT::Other); 660 661 if (ResultVals.empty()) 662 return Chain; 663 664 ResultVals.push_back(Chain); 665 SDOperand Res = DAG.getNode(ISD::MERGE_VALUES, NodeTys, &ResultVals[0], 666 ResultVals.size()); 667 return Res.getValue(Op.ResNo); 668} 669 670static SDOperand LowerRET(SDOperand Op, SelectionDAG &DAG) { 671 SDOperand Copy; 672 SDOperand Chain = Op.getOperand(0); 673 switch(Op.getNumOperands()) { 674 default: 675 assert(0 && "Do not know how to return this many arguments!"); 676 abort(); 677 case 1: { 678 SDOperand LR = DAG.getRegister(ARM::LR, MVT::i32); 679 return DAG.getNode(ARMISD::RET_FLAG, MVT::Other, Chain); 680 } 681 case 3: 682 Op = Op.getOperand(1); 683 if (Op.getValueType() == MVT::f32) { 684 Op = DAG.getNode(ISD::BIT_CONVERT, MVT::i32, Op); 685 } else if (Op.getValueType() == MVT::f64) { 686 // Legalize ret f64 -> ret 2 x i32. We always have fmrrd if f64 is 687 // available. 688 Op = DAG.getNode(ARMISD::FMRRD, DAG.getVTList(MVT::i32, MVT::i32), &Op,1); 689 SDOperand Sign = DAG.getConstant(0, MVT::i32); 690 return DAG.getNode(ISD::RET, MVT::Other, Chain, Op, Sign, 691 Op.getValue(1), Sign); 692 } 693 Copy = DAG.getCopyToReg(Chain, ARM::R0, Op, SDOperand()); 694 if (DAG.getMachineFunction().getRegInfo().liveout_empty()) 695 DAG.getMachineFunction().getRegInfo().addLiveOut(ARM::R0); 696 break; 697 case 5: 698 Copy = DAG.getCopyToReg(Chain, ARM::R1, Op.getOperand(3), SDOperand()); 699 Copy = DAG.getCopyToReg(Copy, ARM::R0, Op.getOperand(1), Copy.getValue(1)); 700 // If we haven't noted the R0+R1 are live out, do so now. 701 if (DAG.getMachineFunction().getRegInfo().liveout_empty()) { 702 DAG.getMachineFunction().getRegInfo().addLiveOut(ARM::R0); 703 DAG.getMachineFunction().getRegInfo().addLiveOut(ARM::R1); 704 } 705 break; 706 } 707 708 //We must use RET_FLAG instead of BRIND because BRIND doesn't have a flag 709 return DAG.getNode(ARMISD::RET_FLAG, MVT::Other, Copy, Copy.getValue(1)); 710} 711 712// ConstantPool, JumpTable, GlobalAddress, and ExternalSymbol are lowered as 713// their target countpart wrapped in the ARMISD::Wrapper node. Suppose N is 714// one of the above mentioned nodes. It has to be wrapped because otherwise 715// Select(N) returns N. So the raw TargetGlobalAddress nodes, etc. can only 716// be used to form addressing mode. These wrapped nodes will be selected 717// into MOVi. 718static SDOperand LowerConstantPool(SDOperand Op, SelectionDAG &DAG) { 719 MVT::ValueType PtrVT = Op.getValueType(); 720 ConstantPoolSDNode *CP = cast<ConstantPoolSDNode>(Op); 721 SDOperand Res; 722 if (CP->isMachineConstantPoolEntry()) 723 Res = DAG.getTargetConstantPool(CP->getMachineCPVal(), PtrVT, 724 CP->getAlignment()); 725 else 726 Res = DAG.getTargetConstantPool(CP->getConstVal(), PtrVT, 727 CP->getAlignment()); 728 return DAG.getNode(ARMISD::Wrapper, MVT::i32, Res); 729} 730 731// Lower ISD::GlobalTLSAddress using the "general dynamic" model 732SDOperand 733ARMTargetLowering::LowerToTLSGeneralDynamicModel(GlobalAddressSDNode *GA, 734 SelectionDAG &DAG) { 735 MVT::ValueType PtrVT = getPointerTy(); 736 unsigned char PCAdj = Subtarget->isThumb() ? 4 : 8; 737 ARMConstantPoolValue *CPV = 738 new ARMConstantPoolValue(GA->getGlobal(), ARMPCLabelIndex, ARMCP::CPValue, 739 PCAdj, "tlsgd", true); 740 SDOperand Argument = DAG.getTargetConstantPool(CPV, PtrVT, 2); 741 Argument = DAG.getNode(ARMISD::Wrapper, MVT::i32, Argument); 742 Argument = DAG.getLoad(PtrVT, DAG.getEntryNode(), Argument, NULL, 0); 743 SDOperand Chain = Argument.getValue(1); 744 745 SDOperand PICLabel = DAG.getConstant(ARMPCLabelIndex++, MVT::i32); 746 Argument = DAG.getNode(ARMISD::PIC_ADD, PtrVT, Argument, PICLabel); 747 748 // call __tls_get_addr. 749 ArgListTy Args; 750 ArgListEntry Entry; 751 Entry.Node = Argument; 752 Entry.Ty = (const Type *) Type::Int32Ty; 753 Args.push_back(Entry); 754 std::pair<SDOperand, SDOperand> CallResult = 755 LowerCallTo(Chain, (const Type *) Type::Int32Ty, false, false, 756 CallingConv::C, false, 757 DAG.getExternalSymbol("__tls_get_addr", PtrVT), Args, DAG); 758 return CallResult.first; 759} 760 761// Lower ISD::GlobalTLSAddress using the "initial exec" or 762// "local exec" model. 763SDOperand 764ARMTargetLowering::LowerToTLSExecModels(GlobalAddressSDNode *GA, 765 SelectionDAG &DAG) { 766 GlobalValue *GV = GA->getGlobal(); 767 SDOperand Offset; 768 SDOperand Chain = DAG.getEntryNode(); 769 MVT::ValueType PtrVT = getPointerTy(); 770 // Get the Thread Pointer 771 SDOperand ThreadPointer = DAG.getNode(ARMISD::THREAD_POINTER, PtrVT); 772 773 if (GV->isDeclaration()){ 774 // initial exec model 775 unsigned char PCAdj = Subtarget->isThumb() ? 4 : 8; 776 ARMConstantPoolValue *CPV = 777 new ARMConstantPoolValue(GA->getGlobal(), ARMPCLabelIndex, ARMCP::CPValue, 778 PCAdj, "gottpoff", true); 779 Offset = DAG.getTargetConstantPool(CPV, PtrVT, 2); 780 Offset = DAG.getNode(ARMISD::Wrapper, MVT::i32, Offset); 781 Offset = DAG.getLoad(PtrVT, Chain, Offset, NULL, 0); 782 Chain = Offset.getValue(1); 783 784 SDOperand PICLabel = DAG.getConstant(ARMPCLabelIndex++, MVT::i32); 785 Offset = DAG.getNode(ARMISD::PIC_ADD, PtrVT, Offset, PICLabel); 786 787 Offset = DAG.getLoad(PtrVT, Chain, Offset, NULL, 0); 788 } else { 789 // local exec model 790 ARMConstantPoolValue *CPV = 791 new ARMConstantPoolValue(GV, ARMCP::CPValue, "tpoff"); 792 Offset = DAG.getTargetConstantPool(CPV, PtrVT, 2); 793 Offset = DAG.getNode(ARMISD::Wrapper, MVT::i32, Offset); 794 Offset = DAG.getLoad(PtrVT, Chain, Offset, NULL, 0); 795 } 796 797 // The address of the thread local variable is the add of the thread 798 // pointer with the offset of the variable. 799 return DAG.getNode(ISD::ADD, PtrVT, ThreadPointer, Offset); 800} 801 802SDOperand 803ARMTargetLowering::LowerGlobalTLSAddress(SDOperand Op, SelectionDAG &DAG) { 804 // TODO: implement the "local dynamic" model 805 assert(Subtarget->isTargetELF() && 806 "TLS not implemented for non-ELF targets"); 807 GlobalAddressSDNode *GA = cast<GlobalAddressSDNode>(Op); 808 // If the relocation model is PIC, use the "General Dynamic" TLS Model, 809 // otherwise use the "Local Exec" TLS Model 810 if (getTargetMachine().getRelocationModel() == Reloc::PIC_) 811 return LowerToTLSGeneralDynamicModel(GA, DAG); 812 else 813 return LowerToTLSExecModels(GA, DAG); 814} 815 816SDOperand ARMTargetLowering::LowerGlobalAddressELF(SDOperand Op, 817 SelectionDAG &DAG) { 818 MVT::ValueType PtrVT = getPointerTy(); 819 GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal(); 820 Reloc::Model RelocM = getTargetMachine().getRelocationModel(); 821 if (RelocM == Reloc::PIC_) { 822 bool UseGOTOFF = GV->hasInternalLinkage() || GV->hasHiddenVisibility(); 823 ARMConstantPoolValue *CPV = 824 new ARMConstantPoolValue(GV, ARMCP::CPValue, UseGOTOFF ? "GOTOFF":"GOT"); 825 SDOperand CPAddr = DAG.getTargetConstantPool(CPV, PtrVT, 2); 826 CPAddr = DAG.getNode(ARMISD::Wrapper, MVT::i32, CPAddr); 827 SDOperand Result = DAG.getLoad(PtrVT, DAG.getEntryNode(), CPAddr, NULL, 0); 828 SDOperand Chain = Result.getValue(1); 829 SDOperand GOT = DAG.getNode(ISD::GLOBAL_OFFSET_TABLE, PtrVT); 830 Result = DAG.getNode(ISD::ADD, PtrVT, Result, GOT); 831 if (!UseGOTOFF) 832 Result = DAG.getLoad(PtrVT, Chain, Result, NULL, 0); 833 return Result; 834 } else { 835 SDOperand CPAddr = DAG.getTargetConstantPool(GV, PtrVT, 2); 836 CPAddr = DAG.getNode(ARMISD::Wrapper, MVT::i32, CPAddr); 837 return DAG.getLoad(PtrVT, DAG.getEntryNode(), CPAddr, NULL, 0); 838 } 839} 840 841/// GVIsIndirectSymbol - true if the GV will be accessed via an indirect symbol 842/// even in non-static mode. 843static bool GVIsIndirectSymbol(GlobalValue *GV, Reloc::Model RelocM) { 844 return RelocM != Reloc::Static && 845 (GV->hasWeakLinkage() || GV->hasLinkOnceLinkage() || 846 (GV->isDeclaration() && !GV->hasNotBeenReadFromBitcode())); 847} 848 849SDOperand ARMTargetLowering::LowerGlobalAddressDarwin(SDOperand Op, 850 SelectionDAG &DAG) { 851 MVT::ValueType PtrVT = getPointerTy(); 852 GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal(); 853 Reloc::Model RelocM = getTargetMachine().getRelocationModel(); 854 bool IsIndirect = GVIsIndirectSymbol(GV, RelocM); 855 SDOperand CPAddr; 856 if (RelocM == Reloc::Static) 857 CPAddr = DAG.getTargetConstantPool(GV, PtrVT, 2); 858 else { 859 unsigned PCAdj = (RelocM != Reloc::PIC_) 860 ? 0 : (Subtarget->isThumb() ? 4 : 8); 861 ARMCP::ARMCPKind Kind = IsIndirect ? ARMCP::CPNonLazyPtr 862 : ARMCP::CPValue; 863 ARMConstantPoolValue *CPV = new ARMConstantPoolValue(GV, ARMPCLabelIndex, 864 Kind, PCAdj); 865 CPAddr = DAG.getTargetConstantPool(CPV, PtrVT, 2); 866 } 867 CPAddr = DAG.getNode(ARMISD::Wrapper, MVT::i32, CPAddr); 868 869 SDOperand Result = DAG.getLoad(PtrVT, DAG.getEntryNode(), CPAddr, NULL, 0); 870 SDOperand Chain = Result.getValue(1); 871 872 if (RelocM == Reloc::PIC_) { 873 SDOperand PICLabel = DAG.getConstant(ARMPCLabelIndex++, MVT::i32); 874 Result = DAG.getNode(ARMISD::PIC_ADD, PtrVT, Result, PICLabel); 875 } 876 if (IsIndirect) 877 Result = DAG.getLoad(PtrVT, Chain, Result, NULL, 0); 878 879 return Result; 880} 881 882SDOperand ARMTargetLowering::LowerGLOBAL_OFFSET_TABLE(SDOperand Op, 883 SelectionDAG &DAG){ 884 assert(Subtarget->isTargetELF() && 885 "GLOBAL OFFSET TABLE not implemented for non-ELF targets"); 886 MVT::ValueType PtrVT = getPointerTy(); 887 unsigned PCAdj = Subtarget->isThumb() ? 4 : 8; 888 ARMConstantPoolValue *CPV = new ARMConstantPoolValue("_GLOBAL_OFFSET_TABLE_", 889 ARMPCLabelIndex, 890 ARMCP::CPValue, PCAdj); 891 SDOperand CPAddr = DAG.getTargetConstantPool(CPV, PtrVT, 2); 892 CPAddr = DAG.getNode(ARMISD::Wrapper, MVT::i32, CPAddr); 893 SDOperand Result = DAG.getLoad(PtrVT, DAG.getEntryNode(), CPAddr, NULL, 0); 894 SDOperand PICLabel = DAG.getConstant(ARMPCLabelIndex++, MVT::i32); 895 return DAG.getNode(ARMISD::PIC_ADD, PtrVT, Result, PICLabel); 896} 897 898static SDOperand LowerINTRINSIC_WO_CHAIN(SDOperand Op, SelectionDAG &DAG) { 899 MVT::ValueType PtrVT = DAG.getTargetLoweringInfo().getPointerTy(); 900 unsigned IntNo = cast<ConstantSDNode>(Op.getOperand(0))->getValue(); 901 switch (IntNo) { 902 default: return SDOperand(); // Don't custom lower most intrinsics. 903 case Intrinsic::arm_thread_pointer: 904 return DAG.getNode(ARMISD::THREAD_POINTER, PtrVT); 905 } 906} 907 908static SDOperand LowerVASTART(SDOperand Op, SelectionDAG &DAG, 909 unsigned VarArgsFrameIndex) { 910 // vastart just stores the address of the VarArgsFrameIndex slot into the 911 // memory location argument. 912 MVT::ValueType PtrVT = DAG.getTargetLoweringInfo().getPointerTy(); 913 SDOperand FR = DAG.getFrameIndex(VarArgsFrameIndex, PtrVT); 914 SrcValueSDNode *SV = cast<SrcValueSDNode>(Op.getOperand(2)); 915 return DAG.getStore(Op.getOperand(0), FR, Op.getOperand(1), SV->getValue(), 916 SV->getOffset()); 917} 918 919static SDOperand LowerFORMAL_ARGUMENT(SDOperand Op, SelectionDAG &DAG, 920 unsigned *vRegs, unsigned ArgNo, 921 unsigned &NumGPRs, unsigned &ArgOffset) { 922 MachineFunction &MF = DAG.getMachineFunction(); 923 MVT::ValueType ObjectVT = Op.getValue(ArgNo).getValueType(); 924 SDOperand Root = Op.getOperand(0); 925 std::vector<SDOperand> ArgValues; 926 MachineRegisterInfo &RegInfo = MF.getRegInfo(); 927 928 static const unsigned GPRArgRegs[] = { 929 ARM::R0, ARM::R1, ARM::R2, ARM::R3 930 }; 931 932 unsigned ObjSize; 933 unsigned ObjGPRs; 934 unsigned GPRPad; 935 unsigned StackPad; 936 unsigned Flags = Op.getConstantOperandVal(ArgNo + 3); 937 HowToPassArgument(ObjectVT, NumGPRs, ArgOffset, ObjGPRs, 938 ObjSize, GPRPad, StackPad, Flags); 939 NumGPRs += GPRPad; 940 ArgOffset += StackPad; 941 942 SDOperand ArgValue; 943 if (ObjGPRs == 1) { 944 unsigned VReg = RegInfo.createVirtualRegister(&ARM::GPRRegClass); 945 RegInfo.addLiveIn(GPRArgRegs[NumGPRs], VReg); 946 vRegs[NumGPRs] = VReg; 947 ArgValue = DAG.getCopyFromReg(Root, VReg, MVT::i32); 948 if (ObjectVT == MVT::f32) 949 ArgValue = DAG.getNode(ISD::BIT_CONVERT, MVT::f32, ArgValue); 950 } else if (ObjGPRs == 2) { 951 unsigned VReg = RegInfo.createVirtualRegister(&ARM::GPRRegClass); 952 RegInfo.addLiveIn(GPRArgRegs[NumGPRs], VReg); 953 vRegs[NumGPRs] = VReg; 954 ArgValue = DAG.getCopyFromReg(Root, VReg, MVT::i32); 955 956 VReg = RegInfo.createVirtualRegister(&ARM::GPRRegClass); 957 RegInfo.addLiveIn(GPRArgRegs[NumGPRs+1], VReg); 958 vRegs[NumGPRs+1] = VReg; 959 SDOperand ArgValue2 = DAG.getCopyFromReg(Root, VReg, MVT::i32); 960 961 assert(ObjectVT != MVT::i64 && "i64 should already be lowered"); 962 ArgValue = DAG.getNode(ARMISD::FMDRR, MVT::f64, ArgValue, ArgValue2); 963 } 964 NumGPRs += ObjGPRs; 965 966 if (ObjSize) { 967 // If the argument is actually used, emit a load from the right stack 968 // slot. 969 if (!Op.Val->hasNUsesOfValue(0, ArgNo)) { 970 MachineFrameInfo *MFI = MF.getFrameInfo(); 971 int FI = MFI->CreateFixedObject(ObjSize, ArgOffset); 972 SDOperand FIN = DAG.getFrameIndex(FI, MVT::i32); 973 if (ObjGPRs == 0) 974 ArgValue = DAG.getLoad(ObjectVT, Root, FIN, NULL, 0); 975 else { 976 SDOperand ArgValue2 = DAG.getLoad(MVT::i32, Root, FIN, NULL, 0); 977 assert(ObjectVT != MVT::i64 && "i64 should already be lowered"); 978 ArgValue = DAG.getNode(ARMISD::FMDRR, MVT::f64, ArgValue, ArgValue2); 979 } 980 } else { 981 // Don't emit a dead load. 982 ArgValue = DAG.getNode(ISD::UNDEF, ObjectVT); 983 } 984 985 ArgOffset += ObjSize; // Move on to the next argument. 986 } 987 988 return ArgValue; 989} 990 991SDOperand 992ARMTargetLowering::LowerFORMAL_ARGUMENTS(SDOperand Op, SelectionDAG &DAG) { 993 std::vector<SDOperand> ArgValues; 994 SDOperand Root = Op.getOperand(0); 995 unsigned ArgOffset = 0; // Frame mechanisms handle retaddr slot 996 unsigned NumGPRs = 0; // GPRs used for parameter passing. 997 unsigned VRegs[4]; 998 999 unsigned NumArgs = Op.Val->getNumValues()-1; 1000 for (unsigned ArgNo = 0; ArgNo < NumArgs; ++ArgNo) 1001 ArgValues.push_back(LowerFORMAL_ARGUMENT(Op, DAG, VRegs, ArgNo, 1002 NumGPRs, ArgOffset)); 1003 1004 bool isVarArg = cast<ConstantSDNode>(Op.getOperand(2))->getValue() != 0; 1005 if (isVarArg) { 1006 static const unsigned GPRArgRegs[] = { 1007 ARM::R0, ARM::R1, ARM::R2, ARM::R3 1008 }; 1009 1010 MachineFunction &MF = DAG.getMachineFunction(); 1011 MachineRegisterInfo &RegInfo = MF.getRegInfo(); 1012 MachineFrameInfo *MFI = MF.getFrameInfo(); 1013 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>(); 1014 unsigned Align = MF.getTarget().getFrameInfo()->getStackAlignment(); 1015 unsigned VARegSize = (4 - NumGPRs) * 4; 1016 unsigned VARegSaveSize = (VARegSize + Align - 1) & ~(Align - 1); 1017 if (VARegSaveSize) { 1018 // If this function is vararg, store any remaining integer argument regs 1019 // to their spots on the stack so that they may be loaded by deferencing 1020 // the result of va_next. 1021 AFI->setVarArgsRegSaveSize(VARegSaveSize); 1022 VarArgsFrameIndex = MFI->CreateFixedObject(VARegSaveSize, ArgOffset + 1023 VARegSaveSize - VARegSize); 1024 SDOperand FIN = DAG.getFrameIndex(VarArgsFrameIndex, getPointerTy()); 1025 1026 SmallVector<SDOperand, 4> MemOps; 1027 for (; NumGPRs < 4; ++NumGPRs) { 1028 unsigned VReg = RegInfo.createVirtualRegister(&ARM::GPRRegClass); 1029 RegInfo.addLiveIn(GPRArgRegs[NumGPRs], VReg); 1030 SDOperand Val = DAG.getCopyFromReg(Root, VReg, MVT::i32); 1031 SDOperand Store = DAG.getStore(Val.getValue(1), Val, FIN, NULL, 0); 1032 MemOps.push_back(Store); 1033 FIN = DAG.getNode(ISD::ADD, getPointerTy(), FIN, 1034 DAG.getConstant(4, getPointerTy())); 1035 } 1036 if (!MemOps.empty()) 1037 Root = DAG.getNode(ISD::TokenFactor, MVT::Other, 1038 &MemOps[0], MemOps.size()); 1039 } else 1040 // This will point to the next argument passed via stack. 1041 VarArgsFrameIndex = MFI->CreateFixedObject(4, ArgOffset); 1042 } 1043 1044 ArgValues.push_back(Root); 1045 1046 // Return the new list of results. 1047 std::vector<MVT::ValueType> RetVT(Op.Val->value_begin(), 1048 Op.Val->value_end()); 1049 return DAG.getNode(ISD::MERGE_VALUES, RetVT, &ArgValues[0], ArgValues.size()); 1050} 1051 1052/// isFloatingPointZero - Return true if this is +0.0. 1053static bool isFloatingPointZero(SDOperand Op) { 1054 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(Op)) 1055 return CFP->getValueAPF().isPosZero(); 1056 else if (ISD::isEXTLoad(Op.Val) || ISD::isNON_EXTLoad(Op.Val)) { 1057 // Maybe this has already been legalized into the constant pool? 1058 if (Op.getOperand(1).getOpcode() == ARMISD::Wrapper) { 1059 SDOperand WrapperOp = Op.getOperand(1).getOperand(0); 1060 if (ConstantPoolSDNode *CP = dyn_cast<ConstantPoolSDNode>(WrapperOp)) 1061 if (ConstantFP *CFP = dyn_cast<ConstantFP>(CP->getConstVal())) 1062 return CFP->getValueAPF().isPosZero(); 1063 } 1064 } 1065 return false; 1066} 1067 1068static bool isLegalCmpImmediate(unsigned C, bool isThumb) { 1069 return ( isThumb && (C & ~255U) == 0) || 1070 (!isThumb && ARM_AM::getSOImmVal(C) != -1); 1071} 1072 1073/// Returns appropriate ARM CMP (cmp) and corresponding condition code for 1074/// the given operands. 1075static SDOperand getARMCmp(SDOperand LHS, SDOperand RHS, ISD::CondCode CC, 1076 SDOperand &ARMCC, SelectionDAG &DAG, bool isThumb) { 1077 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(RHS.Val)) { 1078 unsigned C = RHSC->getValue(); 1079 if (!isLegalCmpImmediate(C, isThumb)) { 1080 // Constant does not fit, try adjusting it by one? 1081 switch (CC) { 1082 default: break; 1083 case ISD::SETLT: 1084 case ISD::SETGE: 1085 if (isLegalCmpImmediate(C-1, isThumb)) { 1086 CC = (CC == ISD::SETLT) ? ISD::SETLE : ISD::SETGT; 1087 RHS = DAG.getConstant(C-1, MVT::i32); 1088 } 1089 break; 1090 case ISD::SETULT: 1091 case ISD::SETUGE: 1092 if (C > 0 && isLegalCmpImmediate(C-1, isThumb)) { 1093 CC = (CC == ISD::SETULT) ? ISD::SETULE : ISD::SETUGT; 1094 RHS = DAG.getConstant(C-1, MVT::i32); 1095 } 1096 break; 1097 case ISD::SETLE: 1098 case ISD::SETGT: 1099 if (isLegalCmpImmediate(C+1, isThumb)) { 1100 CC = (CC == ISD::SETLE) ? ISD::SETLT : ISD::SETGE; 1101 RHS = DAG.getConstant(C+1, MVT::i32); 1102 } 1103 break; 1104 case ISD::SETULE: 1105 case ISD::SETUGT: 1106 if (C < 0xffffffff && isLegalCmpImmediate(C+1, isThumb)) { 1107 CC = (CC == ISD::SETULE) ? ISD::SETULT : ISD::SETUGE; 1108 RHS = DAG.getConstant(C+1, MVT::i32); 1109 } 1110 break; 1111 } 1112 } 1113 } 1114 1115 ARMCC::CondCodes CondCode = IntCCToARMCC(CC); 1116 ARMISD::NodeType CompareType; 1117 switch (CondCode) { 1118 default: 1119 CompareType = ARMISD::CMP; 1120 break; 1121 case ARMCC::EQ: 1122 case ARMCC::NE: 1123 case ARMCC::MI: 1124 case ARMCC::PL: 1125 // Uses only N and Z Flags 1126 CompareType = ARMISD::CMPNZ; 1127 break; 1128 } 1129 ARMCC = DAG.getConstant(CondCode, MVT::i32); 1130 return DAG.getNode(CompareType, MVT::Flag, LHS, RHS); 1131} 1132 1133/// Returns a appropriate VFP CMP (fcmp{s|d}+fmstat) for the given operands. 1134static SDOperand getVFPCmp(SDOperand LHS, SDOperand RHS, SelectionDAG &DAG) { 1135 SDOperand Cmp; 1136 if (!isFloatingPointZero(RHS)) 1137 Cmp = DAG.getNode(ARMISD::CMPFP, MVT::Flag, LHS, RHS); 1138 else 1139 Cmp = DAG.getNode(ARMISD::CMPFPw0, MVT::Flag, LHS); 1140 return DAG.getNode(ARMISD::FMSTAT, MVT::Flag, Cmp); 1141} 1142 1143static SDOperand LowerSELECT_CC(SDOperand Op, SelectionDAG &DAG, 1144 const ARMSubtarget *ST) { 1145 MVT::ValueType VT = Op.getValueType(); 1146 SDOperand LHS = Op.getOperand(0); 1147 SDOperand RHS = Op.getOperand(1); 1148 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(4))->get(); 1149 SDOperand TrueVal = Op.getOperand(2); 1150 SDOperand FalseVal = Op.getOperand(3); 1151 1152 if (LHS.getValueType() == MVT::i32) { 1153 SDOperand ARMCC; 1154 SDOperand CCR = DAG.getRegister(ARM::CPSR, MVT::i32); 1155 SDOperand Cmp = getARMCmp(LHS, RHS, CC, ARMCC, DAG, ST->isThumb()); 1156 return DAG.getNode(ARMISD::CMOV, VT, FalseVal, TrueVal, ARMCC, CCR, Cmp); 1157 } 1158 1159 ARMCC::CondCodes CondCode, CondCode2; 1160 if (FPCCToARMCC(CC, CondCode, CondCode2)) 1161 std::swap(TrueVal, FalseVal); 1162 1163 SDOperand ARMCC = DAG.getConstant(CondCode, MVT::i32); 1164 SDOperand CCR = DAG.getRegister(ARM::CPSR, MVT::i32); 1165 SDOperand Cmp = getVFPCmp(LHS, RHS, DAG); 1166 SDOperand Result = DAG.getNode(ARMISD::CMOV, VT, FalseVal, TrueVal, 1167 ARMCC, CCR, Cmp); 1168 if (CondCode2 != ARMCC::AL) { 1169 SDOperand ARMCC2 = DAG.getConstant(CondCode2, MVT::i32); 1170 // FIXME: Needs another CMP because flag can have but one use. 1171 SDOperand Cmp2 = getVFPCmp(LHS, RHS, DAG); 1172 Result = DAG.getNode(ARMISD::CMOV, VT, Result, TrueVal, ARMCC2, CCR, Cmp2); 1173 } 1174 return Result; 1175} 1176 1177static SDOperand LowerBR_CC(SDOperand Op, SelectionDAG &DAG, 1178 const ARMSubtarget *ST) { 1179 SDOperand Chain = Op.getOperand(0); 1180 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(1))->get(); 1181 SDOperand LHS = Op.getOperand(2); 1182 SDOperand RHS = Op.getOperand(3); 1183 SDOperand Dest = Op.getOperand(4); 1184 1185 if (LHS.getValueType() == MVT::i32) { 1186 SDOperand ARMCC; 1187 SDOperand CCR = DAG.getRegister(ARM::CPSR, MVT::i32); 1188 SDOperand Cmp = getARMCmp(LHS, RHS, CC, ARMCC, DAG, ST->isThumb()); 1189 return DAG.getNode(ARMISD::BRCOND, MVT::Other, Chain, Dest, ARMCC, CCR,Cmp); 1190 } 1191 1192 assert(LHS.getValueType() == MVT::f32 || LHS.getValueType() == MVT::f64); 1193 ARMCC::CondCodes CondCode, CondCode2; 1194 if (FPCCToARMCC(CC, CondCode, CondCode2)) 1195 // Swap the LHS/RHS of the comparison if needed. 1196 std::swap(LHS, RHS); 1197 1198 SDOperand Cmp = getVFPCmp(LHS, RHS, DAG); 1199 SDOperand ARMCC = DAG.getConstant(CondCode, MVT::i32); 1200 SDOperand CCR = DAG.getRegister(ARM::CPSR, MVT::i32); 1201 SDVTList VTList = DAG.getVTList(MVT::Other, MVT::Flag); 1202 SDOperand Ops[] = { Chain, Dest, ARMCC, CCR, Cmp }; 1203 SDOperand Res = DAG.getNode(ARMISD::BRCOND, VTList, Ops, 5); 1204 if (CondCode2 != ARMCC::AL) { 1205 ARMCC = DAG.getConstant(CondCode2, MVT::i32); 1206 SDOperand Ops[] = { Res, Dest, ARMCC, CCR, Res.getValue(1) }; 1207 Res = DAG.getNode(ARMISD::BRCOND, VTList, Ops, 5); 1208 } 1209 return Res; 1210} 1211 1212SDOperand ARMTargetLowering::LowerBR_JT(SDOperand Op, SelectionDAG &DAG) { 1213 SDOperand Chain = Op.getOperand(0); 1214 SDOperand Table = Op.getOperand(1); 1215 SDOperand Index = Op.getOperand(2); 1216 1217 MVT::ValueType PTy = getPointerTy(); 1218 JumpTableSDNode *JT = cast<JumpTableSDNode>(Table); 1219 ARMFunctionInfo *AFI = DAG.getMachineFunction().getInfo<ARMFunctionInfo>(); 1220 SDOperand UId = DAG.getConstant(AFI->createJumpTableUId(), PTy); 1221 SDOperand JTI = DAG.getTargetJumpTable(JT->getIndex(), PTy); 1222 Table = DAG.getNode(ARMISD::WrapperJT, MVT::i32, JTI, UId); 1223 Index = DAG.getNode(ISD::MUL, PTy, Index, DAG.getConstant(4, PTy)); 1224 SDOperand Addr = DAG.getNode(ISD::ADD, PTy, Index, Table); 1225 bool isPIC = getTargetMachine().getRelocationModel() == Reloc::PIC_; 1226 Addr = DAG.getLoad(isPIC ? (MVT::ValueType)MVT::i32 : PTy, 1227 Chain, Addr, NULL, 0); 1228 Chain = Addr.getValue(1); 1229 if (isPIC) 1230 Addr = DAG.getNode(ISD::ADD, PTy, Addr, Table); 1231 return DAG.getNode(ARMISD::BR_JT, MVT::Other, Chain, Addr, JTI, UId); 1232} 1233 1234static SDOperand LowerFP_TO_INT(SDOperand Op, SelectionDAG &DAG) { 1235 unsigned Opc = 1236 Op.getOpcode() == ISD::FP_TO_SINT ? ARMISD::FTOSI : ARMISD::FTOUI; 1237 Op = DAG.getNode(Opc, MVT::f32, Op.getOperand(0)); 1238 return DAG.getNode(ISD::BIT_CONVERT, MVT::i32, Op); 1239} 1240 1241static SDOperand LowerINT_TO_FP(SDOperand Op, SelectionDAG &DAG) { 1242 MVT::ValueType VT = Op.getValueType(); 1243 unsigned Opc = 1244 Op.getOpcode() == ISD::SINT_TO_FP ? ARMISD::SITOF : ARMISD::UITOF; 1245 1246 Op = DAG.getNode(ISD::BIT_CONVERT, MVT::f32, Op.getOperand(0)); 1247 return DAG.getNode(Opc, VT, Op); 1248} 1249 1250static SDOperand LowerFCOPYSIGN(SDOperand Op, SelectionDAG &DAG) { 1251 // Implement fcopysign with a fabs and a conditional fneg. 1252 SDOperand Tmp0 = Op.getOperand(0); 1253 SDOperand Tmp1 = Op.getOperand(1); 1254 MVT::ValueType VT = Op.getValueType(); 1255 MVT::ValueType SrcVT = Tmp1.getValueType(); 1256 SDOperand AbsVal = DAG.getNode(ISD::FABS, VT, Tmp0); 1257 SDOperand Cmp = getVFPCmp(Tmp1, DAG.getConstantFP(0.0, SrcVT), DAG); 1258 SDOperand ARMCC = DAG.getConstant(ARMCC::LT, MVT::i32); 1259 SDOperand CCR = DAG.getRegister(ARM::CPSR, MVT::i32); 1260 return DAG.getNode(ARMISD::CNEG, VT, AbsVal, AbsVal, ARMCC, CCR, Cmp); 1261} 1262 1263SDOperand ARMTargetLowering::LowerMEMCPYInline(SDOperand Chain, 1264 SDOperand Dest, 1265 SDOperand Source, 1266 unsigned Size, 1267 unsigned Align, 1268 SelectionDAG &DAG) { 1269 // Do repeated 4-byte loads and stores. To be improved. 1270 assert((Align & 3) == 0 && "Expected 4-byte aligned addresses!"); 1271 unsigned BytesLeft = Size & 3; 1272 unsigned NumMemOps = Size >> 2; 1273 unsigned EmittedNumMemOps = 0; 1274 unsigned SrcOff = 0, DstOff = 0; 1275 MVT::ValueType VT = MVT::i32; 1276 unsigned VTSize = 4; 1277 unsigned i = 0; 1278 const unsigned MAX_LOADS_IN_LDM = 6; 1279 SDOperand TFOps[MAX_LOADS_IN_LDM]; 1280 SDOperand Loads[MAX_LOADS_IN_LDM]; 1281 1282 // Emit up to MAX_LOADS_IN_LDM loads, then a TokenFactor barrier, then the 1283 // same number of stores. The loads and stores will get combined into 1284 // ldm/stm later on. 1285 while (EmittedNumMemOps < NumMemOps) { 1286 for (i = 0; 1287 i < MAX_LOADS_IN_LDM && EmittedNumMemOps + i < NumMemOps; ++i) { 1288 Loads[i] = DAG.getLoad(VT, Chain, 1289 DAG.getNode(ISD::ADD, MVT::i32, Source, 1290 DAG.getConstant(SrcOff, MVT::i32)), 1291 NULL, 0); 1292 TFOps[i] = Loads[i].getValue(1); 1293 SrcOff += VTSize; 1294 } 1295 Chain = DAG.getNode(ISD::TokenFactor, MVT::Other, &TFOps[0], i); 1296 1297 for (i = 0; 1298 i < MAX_LOADS_IN_LDM && EmittedNumMemOps + i < NumMemOps; ++i) { 1299 TFOps[i] = DAG.getStore(Chain, Loads[i], 1300 DAG.getNode(ISD::ADD, MVT::i32, Dest, 1301 DAG.getConstant(DstOff, MVT::i32)), 1302 NULL, 0); 1303 DstOff += VTSize; 1304 } 1305 Chain = DAG.getNode(ISD::TokenFactor, MVT::Other, &TFOps[0], i); 1306 1307 EmittedNumMemOps += i; 1308 } 1309 1310 if (BytesLeft == 0) 1311 return Chain; 1312 1313 // Issue loads / stores for the trailing (1 - 3) bytes. 1314 unsigned BytesLeftSave = BytesLeft; 1315 i = 0; 1316 while (BytesLeft) { 1317 if (BytesLeft >= 2) { 1318 VT = MVT::i16; 1319 VTSize = 2; 1320 } else { 1321 VT = MVT::i8; 1322 VTSize = 1; 1323 } 1324 1325 Loads[i] = DAG.getLoad(VT, Chain, 1326 DAG.getNode(ISD::ADD, MVT::i32, Source, 1327 DAG.getConstant(SrcOff, MVT::i32)), 1328 NULL, 0); 1329 TFOps[i] = Loads[i].getValue(1); 1330 ++i; 1331 SrcOff += VTSize; 1332 BytesLeft -= VTSize; 1333 } 1334 Chain = DAG.getNode(ISD::TokenFactor, MVT::Other, &TFOps[0], i); 1335 1336 i = 0; 1337 BytesLeft = BytesLeftSave; 1338 while (BytesLeft) { 1339 if (BytesLeft >= 2) { 1340 VT = MVT::i16; 1341 VTSize = 2; 1342 } else { 1343 VT = MVT::i8; 1344 VTSize = 1; 1345 } 1346 1347 TFOps[i] = DAG.getStore(Chain, Loads[i], 1348 DAG.getNode(ISD::ADD, MVT::i32, Dest, 1349 DAG.getConstant(DstOff, MVT::i32)), 1350 NULL, 0); 1351 ++i; 1352 DstOff += VTSize; 1353 BytesLeft -= VTSize; 1354 } 1355 return DAG.getNode(ISD::TokenFactor, MVT::Other, &TFOps[0], i); 1356} 1357 1358static SDNode *ExpandBIT_CONVERT(SDNode *N, SelectionDAG &DAG) { 1359 // Turn f64->i64 into FMRRD. 1360 assert(N->getValueType(0) == MVT::i64 && 1361 N->getOperand(0).getValueType() == MVT::f64); 1362 1363 SDOperand Op = N->getOperand(0); 1364 SDOperand Cvt = DAG.getNode(ARMISD::FMRRD, DAG.getVTList(MVT::i32, MVT::i32), 1365 &Op, 1); 1366 1367 // Merge the pieces into a single i64 value. 1368 return DAG.getNode(ISD::BUILD_PAIR, MVT::i64, Cvt, Cvt.getValue(1)).Val; 1369} 1370 1371static SDNode *ExpandSRx(SDNode *N, SelectionDAG &DAG, const ARMSubtarget *ST) { 1372 assert(N->getValueType(0) == MVT::i64 && 1373 (N->getOpcode() == ISD::SRL || N->getOpcode() == ISD::SRA) && 1374 "Unknown shift to lower!"); 1375 1376 // We only lower SRA, SRL of 1 here, all others use generic lowering. 1377 if (!isa<ConstantSDNode>(N->getOperand(1)) || 1378 cast<ConstantSDNode>(N->getOperand(1))->getValue() != 1) 1379 return 0; 1380 1381 // If we are in thumb mode, we don't have RRX. 1382 if (ST->isThumb()) return 0; 1383 1384 // Okay, we have a 64-bit SRA or SRL of 1. Lower this to an RRX expr. 1385 SDOperand Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32, N->getOperand(0), 1386 DAG.getConstant(0, MVT::i32)); 1387 SDOperand Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32, N->getOperand(0), 1388 DAG.getConstant(1, MVT::i32)); 1389 1390 // First, build a SRA_FLAG/SRL_FLAG op, which shifts the top part by one and 1391 // captures the result into a carry flag. 1392 unsigned Opc = N->getOpcode() == ISD::SRL ? ARMISD::SRL_FLAG:ARMISD::SRA_FLAG; 1393 Hi = DAG.getNode(Opc, DAG.getVTList(MVT::i32, MVT::Flag), &Hi, 1); 1394 1395 // The low part is an ARMISD::RRX operand, which shifts the carry in. 1396 Lo = DAG.getNode(ARMISD::RRX, MVT::i32, Lo, Hi.getValue(1)); 1397 1398 // Merge the pieces into a single i64 value. 1399 return DAG.getNode(ISD::BUILD_PAIR, MVT::i64, Lo, Hi).Val; 1400} 1401 1402 1403SDOperand ARMTargetLowering::LowerOperation(SDOperand Op, SelectionDAG &DAG) { 1404 switch (Op.getOpcode()) { 1405 default: assert(0 && "Don't know how to custom lower this!"); abort(); 1406 case ISD::ConstantPool: return LowerConstantPool(Op, DAG); 1407 case ISD::GlobalAddress: 1408 return Subtarget->isTargetDarwin() ? LowerGlobalAddressDarwin(Op, DAG) : 1409 LowerGlobalAddressELF(Op, DAG); 1410 case ISD::GlobalTLSAddress: return LowerGlobalTLSAddress(Op, DAG); 1411 case ISD::CALL: return LowerCALL(Op, DAG); 1412 case ISD::RET: return LowerRET(Op, DAG); 1413 case ISD::SELECT_CC: return LowerSELECT_CC(Op, DAG, Subtarget); 1414 case ISD::BR_CC: return LowerBR_CC(Op, DAG, Subtarget); 1415 case ISD::BR_JT: return LowerBR_JT(Op, DAG); 1416 case ISD::VASTART: return LowerVASTART(Op, DAG, VarArgsFrameIndex); 1417 case ISD::SINT_TO_FP: 1418 case ISD::UINT_TO_FP: return LowerINT_TO_FP(Op, DAG); 1419 case ISD::FP_TO_SINT: 1420 case ISD::FP_TO_UINT: return LowerFP_TO_INT(Op, DAG); 1421 case ISD::FCOPYSIGN: return LowerFCOPYSIGN(Op, DAG); 1422 case ISD::FORMAL_ARGUMENTS: return LowerFORMAL_ARGUMENTS(Op, DAG); 1423 case ISD::RETURNADDR: break; 1424 case ISD::FRAMEADDR: break; 1425 case ISD::GLOBAL_OFFSET_TABLE: return LowerGLOBAL_OFFSET_TABLE(Op, DAG); 1426 case ISD::MEMCPY: return LowerMEMCPY(Op, DAG); 1427 case ISD::INTRINSIC_WO_CHAIN: return LowerINTRINSIC_WO_CHAIN(Op, DAG); 1428 1429 1430 // FIXME: Remove these when LegalizeDAGTypes lands. 1431 case ISD::BIT_CONVERT: return SDOperand(ExpandBIT_CONVERT(Op.Val, DAG), 0); 1432 case ISD::SRL: 1433 case ISD::SRA: return SDOperand(ExpandSRx(Op.Val, DAG,Subtarget),0); 1434 } 1435 return SDOperand(); 1436} 1437 1438 1439/// ExpandOperationResult - Provide custom lowering hooks for expanding 1440/// operations. 1441SDNode *ARMTargetLowering::ExpandOperationResult(SDNode *N, SelectionDAG &DAG) { 1442 switch (N->getOpcode()) { 1443 default: assert(0 && "Don't know how to custom expand this!"); abort(); 1444 case ISD::BIT_CONVERT: return ExpandBIT_CONVERT(N, DAG); 1445 case ISD::SRL: 1446 case ISD::SRA: return ExpandSRx(N, DAG, Subtarget); 1447 } 1448} 1449 1450 1451//===----------------------------------------------------------------------===// 1452// ARM Scheduler Hooks 1453//===----------------------------------------------------------------------===// 1454 1455MachineBasicBlock * 1456ARMTargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI, 1457 MachineBasicBlock *BB) { 1458 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); 1459 switch (MI->getOpcode()) { 1460 default: assert(false && "Unexpected instr type to insert"); 1461 case ARM::tMOVCCr: { 1462 // To "insert" a SELECT_CC instruction, we actually have to insert the 1463 // diamond control-flow pattern. The incoming instruction knows the 1464 // destination vreg to set, the condition code register to branch on, the 1465 // true/false values to select between, and a branch opcode to use. 1466 const BasicBlock *LLVM_BB = BB->getBasicBlock(); 1467 ilist<MachineBasicBlock>::iterator It = BB; 1468 ++It; 1469 1470 // thisMBB: 1471 // ... 1472 // TrueVal = ... 1473 // cmpTY ccX, r1, r2 1474 // bCC copy1MBB 1475 // fallthrough --> copy0MBB 1476 MachineBasicBlock *thisMBB = BB; 1477 MachineBasicBlock *copy0MBB = new MachineBasicBlock(LLVM_BB); 1478 MachineBasicBlock *sinkMBB = new MachineBasicBlock(LLVM_BB); 1479 BuildMI(BB, TII->get(ARM::tBcc)).addMBB(sinkMBB) 1480 .addImm(MI->getOperand(3).getImm()).addReg(MI->getOperand(4).getReg()); 1481 MachineFunction *F = BB->getParent(); 1482 F->getBasicBlockList().insert(It, copy0MBB); 1483 F->getBasicBlockList().insert(It, sinkMBB); 1484 // Update machine-CFG edges by first adding all successors of the current 1485 // block to the new block which will contain the Phi node for the select. 1486 for(MachineBasicBlock::succ_iterator i = BB->succ_begin(), 1487 e = BB->succ_end(); i != e; ++i) 1488 sinkMBB->addSuccessor(*i); 1489 // Next, remove all successors of the current block, and add the true 1490 // and fallthrough blocks as its successors. 1491 while(!BB->succ_empty()) 1492 BB->removeSuccessor(BB->succ_begin()); 1493 BB->addSuccessor(copy0MBB); 1494 BB->addSuccessor(sinkMBB); 1495 1496 // copy0MBB: 1497 // %FalseValue = ... 1498 // # fallthrough to sinkMBB 1499 BB = copy0MBB; 1500 1501 // Update machine-CFG edges 1502 BB->addSuccessor(sinkMBB); 1503 1504 // sinkMBB: 1505 // %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ] 1506 // ... 1507 BB = sinkMBB; 1508 BuildMI(BB, TII->get(ARM::PHI), MI->getOperand(0).getReg()) 1509 .addReg(MI->getOperand(1).getReg()).addMBB(copy0MBB) 1510 .addReg(MI->getOperand(2).getReg()).addMBB(thisMBB); 1511 1512 delete MI; // The pseudo instruction is gone now. 1513 return BB; 1514 } 1515 } 1516} 1517 1518//===----------------------------------------------------------------------===// 1519// ARM Optimization Hooks 1520//===----------------------------------------------------------------------===// 1521 1522/// PerformFMRRDCombine - Target-specific dag combine xforms for ARMISD::FMRRD. 1523static SDOperand PerformFMRRDCombine(SDNode *N, 1524 TargetLowering::DAGCombinerInfo &DCI) { 1525 // fmrrd(fmdrr x, y) -> x,y 1526 SDOperand InDouble = N->getOperand(0); 1527 if (InDouble.getOpcode() == ARMISD::FMDRR) 1528 return DCI.CombineTo(N, InDouble.getOperand(0), InDouble.getOperand(1)); 1529 return SDOperand(); 1530} 1531 1532SDOperand ARMTargetLowering::PerformDAGCombine(SDNode *N, 1533 DAGCombinerInfo &DCI) const { 1534 switch (N->getOpcode()) { 1535 default: break; 1536 case ARMISD::FMRRD: return PerformFMRRDCombine(N, DCI); 1537 } 1538 1539 return SDOperand(); 1540} 1541 1542 1543/// isLegalAddressImmediate - Return true if the integer value can be used 1544/// as the offset of the target addressing mode for load / store of the 1545/// given type. 1546static bool isLegalAddressImmediate(int64_t V, MVT::ValueType VT, 1547 const ARMSubtarget *Subtarget) { 1548 if (V == 0) 1549 return true; 1550 1551 if (Subtarget->isThumb()) { 1552 if (V < 0) 1553 return false; 1554 1555 unsigned Scale = 1; 1556 switch (VT) { 1557 default: return false; 1558 case MVT::i1: 1559 case MVT::i8: 1560 // Scale == 1; 1561 break; 1562 case MVT::i16: 1563 // Scale == 2; 1564 Scale = 2; 1565 break; 1566 case MVT::i32: 1567 // Scale == 4; 1568 Scale = 4; 1569 break; 1570 } 1571 1572 if ((V & (Scale - 1)) != 0) 1573 return false; 1574 V /= Scale; 1575 return V == V & ((1LL << 5) - 1); 1576 } 1577 1578 if (V < 0) 1579 V = - V; 1580 switch (VT) { 1581 default: return false; 1582 case MVT::i1: 1583 case MVT::i8: 1584 case MVT::i32: 1585 // +- imm12 1586 return V == V & ((1LL << 12) - 1); 1587 case MVT::i16: 1588 // +- imm8 1589 return V == V & ((1LL << 8) - 1); 1590 case MVT::f32: 1591 case MVT::f64: 1592 if (!Subtarget->hasVFP2()) 1593 return false; 1594 if ((V & 3) != 0) 1595 return false; 1596 V >>= 2; 1597 return V == V & ((1LL << 8) - 1); 1598 } 1599} 1600 1601/// isLegalAddressingMode - Return true if the addressing mode represented 1602/// by AM is legal for this target, for a load/store of the specified type. 1603bool ARMTargetLowering::isLegalAddressingMode(const AddrMode &AM, 1604 const Type *Ty) const { 1605 if (!isLegalAddressImmediate(AM.BaseOffs, getValueType(Ty), Subtarget)) 1606 return false; 1607 1608 // Can never fold addr of global into load/store. 1609 if (AM.BaseGV) 1610 return false; 1611 1612 switch (AM.Scale) { 1613 case 0: // no scale reg, must be "r+i" or "r", or "i". 1614 break; 1615 case 1: 1616 if (Subtarget->isThumb()) 1617 return false; 1618 // FALL THROUGH. 1619 default: 1620 // ARM doesn't support any R+R*scale+imm addr modes. 1621 if (AM.BaseOffs) 1622 return false; 1623 1624 int Scale = AM.Scale; 1625 switch (getValueType(Ty)) { 1626 default: return false; 1627 case MVT::i1: 1628 case MVT::i8: 1629 case MVT::i32: 1630 case MVT::i64: 1631 // This assumes i64 is legalized to a pair of i32. If not (i.e. 1632 // ldrd / strd are used, then its address mode is same as i16. 1633 // r + r 1634 if (Scale < 0) Scale = -Scale; 1635 if (Scale == 1) 1636 return true; 1637 // r + r << imm 1638 return isPowerOf2_32(Scale & ~1); 1639 case MVT::i16: 1640 // r + r 1641 if (((unsigned)AM.HasBaseReg + Scale) <= 2) 1642 return true; 1643 return false; 1644 1645 case MVT::isVoid: 1646 // Note, we allow "void" uses (basically, uses that aren't loads or 1647 // stores), because arm allows folding a scale into many arithmetic 1648 // operations. This should be made more precise and revisited later. 1649 1650 // Allow r << imm, but the imm has to be a multiple of two. 1651 if (AM.Scale & 1) return false; 1652 return isPowerOf2_32(AM.Scale); 1653 } 1654 break; 1655 } 1656 return true; 1657} 1658 1659 1660static bool getIndexedAddressParts(SDNode *Ptr, MVT::ValueType VT, 1661 bool isSEXTLoad, SDOperand &Base, 1662 SDOperand &Offset, bool &isInc, 1663 SelectionDAG &DAG) { 1664 if (Ptr->getOpcode() != ISD::ADD && Ptr->getOpcode() != ISD::SUB) 1665 return false; 1666 1667 if (VT == MVT::i16 || ((VT == MVT::i8 || VT == MVT::i1) && isSEXTLoad)) { 1668 // AddressingMode 3 1669 Base = Ptr->getOperand(0); 1670 if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(Ptr->getOperand(1))) { 1671 int RHSC = (int)RHS->getValue(); 1672 if (RHSC < 0 && RHSC > -256) { 1673 isInc = false; 1674 Offset = DAG.getConstant(-RHSC, RHS->getValueType(0)); 1675 return true; 1676 } 1677 } 1678 isInc = (Ptr->getOpcode() == ISD::ADD); 1679 Offset = Ptr->getOperand(1); 1680 return true; 1681 } else if (VT == MVT::i32 || VT == MVT::i8 || VT == MVT::i1) { 1682 // AddressingMode 2 1683 if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(Ptr->getOperand(1))) { 1684 int RHSC = (int)RHS->getValue(); 1685 if (RHSC < 0 && RHSC > -0x1000) { 1686 isInc = false; 1687 Offset = DAG.getConstant(-RHSC, RHS->getValueType(0)); 1688 Base = Ptr->getOperand(0); 1689 return true; 1690 } 1691 } 1692 1693 if (Ptr->getOpcode() == ISD::ADD) { 1694 isInc = true; 1695 ARM_AM::ShiftOpc ShOpcVal= ARM_AM::getShiftOpcForNode(Ptr->getOperand(0)); 1696 if (ShOpcVal != ARM_AM::no_shift) { 1697 Base = Ptr->getOperand(1); 1698 Offset = Ptr->getOperand(0); 1699 } else { 1700 Base = Ptr->getOperand(0); 1701 Offset = Ptr->getOperand(1); 1702 } 1703 return true; 1704 } 1705 1706 isInc = (Ptr->getOpcode() == ISD::ADD); 1707 Base = Ptr->getOperand(0); 1708 Offset = Ptr->getOperand(1); 1709 return true; 1710 } 1711 1712 // FIXME: Use FLDM / FSTM to emulate indexed FP load / store. 1713 return false; 1714} 1715 1716/// getPreIndexedAddressParts - returns true by value, base pointer and 1717/// offset pointer and addressing mode by reference if the node's address 1718/// can be legally represented as pre-indexed load / store address. 1719bool 1720ARMTargetLowering::getPreIndexedAddressParts(SDNode *N, SDOperand &Base, 1721 SDOperand &Offset, 1722 ISD::MemIndexedMode &AM, 1723 SelectionDAG &DAG) { 1724 if (Subtarget->isThumb()) 1725 return false; 1726 1727 MVT::ValueType VT; 1728 SDOperand Ptr; 1729 bool isSEXTLoad = false; 1730 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) { 1731 Ptr = LD->getBasePtr(); 1732 VT = LD->getMemoryVT(); 1733 isSEXTLoad = LD->getExtensionType() == ISD::SEXTLOAD; 1734 } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) { 1735 Ptr = ST->getBasePtr(); 1736 VT = ST->getMemoryVT(); 1737 } else 1738 return false; 1739 1740 bool isInc; 1741 bool isLegal = getIndexedAddressParts(Ptr.Val, VT, isSEXTLoad, Base, Offset, 1742 isInc, DAG); 1743 if (isLegal) { 1744 AM = isInc ? ISD::PRE_INC : ISD::PRE_DEC; 1745 return true; 1746 } 1747 return false; 1748} 1749 1750/// getPostIndexedAddressParts - returns true by value, base pointer and 1751/// offset pointer and addressing mode by reference if this node can be 1752/// combined with a load / store to form a post-indexed load / store. 1753bool ARMTargetLowering::getPostIndexedAddressParts(SDNode *N, SDNode *Op, 1754 SDOperand &Base, 1755 SDOperand &Offset, 1756 ISD::MemIndexedMode &AM, 1757 SelectionDAG &DAG) { 1758 if (Subtarget->isThumb()) 1759 return false; 1760 1761 MVT::ValueType VT; 1762 SDOperand Ptr; 1763 bool isSEXTLoad = false; 1764 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) { 1765 VT = LD->getMemoryVT(); 1766 isSEXTLoad = LD->getExtensionType() == ISD::SEXTLOAD; 1767 } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) { 1768 VT = ST->getMemoryVT(); 1769 } else 1770 return false; 1771 1772 bool isInc; 1773 bool isLegal = getIndexedAddressParts(Op, VT, isSEXTLoad, Base, Offset, 1774 isInc, DAG); 1775 if (isLegal) { 1776 AM = isInc ? ISD::POST_INC : ISD::POST_DEC; 1777 return true; 1778 } 1779 return false; 1780} 1781 1782void ARMTargetLowering::computeMaskedBitsForTargetNode(const SDOperand Op, 1783 uint64_t Mask, 1784 uint64_t &KnownZero, 1785 uint64_t &KnownOne, 1786 const SelectionDAG &DAG, 1787 unsigned Depth) const { 1788 KnownZero = 0; 1789 KnownOne = 0; 1790 switch (Op.getOpcode()) { 1791 default: break; 1792 case ARMISD::CMOV: { 1793 // Bits are known zero/one if known on the LHS and RHS. 1794 DAG.ComputeMaskedBits(Op.getOperand(0), Mask, KnownZero, KnownOne, Depth+1); 1795 if (KnownZero == 0 && KnownOne == 0) return; 1796 1797 uint64_t KnownZeroRHS, KnownOneRHS; 1798 DAG.ComputeMaskedBits(Op.getOperand(1), Mask, 1799 KnownZeroRHS, KnownOneRHS, Depth+1); 1800 KnownZero &= KnownZeroRHS; 1801 KnownOne &= KnownOneRHS; 1802 return; 1803 } 1804 } 1805} 1806 1807//===----------------------------------------------------------------------===// 1808// ARM Inline Assembly Support 1809//===----------------------------------------------------------------------===// 1810 1811/// getConstraintType - Given a constraint letter, return the type of 1812/// constraint it is for this target. 1813ARMTargetLowering::ConstraintType 1814ARMTargetLowering::getConstraintType(const std::string &Constraint) const { 1815 if (Constraint.size() == 1) { 1816 switch (Constraint[0]) { 1817 default: break; 1818 case 'l': return C_RegisterClass; 1819 case 'w': return C_RegisterClass; 1820 } 1821 } 1822 return TargetLowering::getConstraintType(Constraint); 1823} 1824 1825std::pair<unsigned, const TargetRegisterClass*> 1826ARMTargetLowering::getRegForInlineAsmConstraint(const std::string &Constraint, 1827 MVT::ValueType VT) const { 1828 if (Constraint.size() == 1) { 1829 // GCC RS6000 Constraint Letters 1830 switch (Constraint[0]) { 1831 case 'l': 1832 // FIXME: in thumb mode, 'l' is only low-regs. 1833 // FALL THROUGH. 1834 case 'r': 1835 return std::make_pair(0U, ARM::GPRRegisterClass); 1836 case 'w': 1837 if (VT == MVT::f32) 1838 return std::make_pair(0U, ARM::SPRRegisterClass); 1839 if (VT == MVT::f64) 1840 return std::make_pair(0U, ARM::DPRRegisterClass); 1841 break; 1842 } 1843 } 1844 return TargetLowering::getRegForInlineAsmConstraint(Constraint, VT); 1845} 1846 1847std::vector<unsigned> ARMTargetLowering:: 1848getRegClassForInlineAsmConstraint(const std::string &Constraint, 1849 MVT::ValueType VT) const { 1850 if (Constraint.size() != 1) 1851 return std::vector<unsigned>(); 1852 1853 switch (Constraint[0]) { // GCC ARM Constraint Letters 1854 default: break; 1855 case 'l': 1856 case 'r': 1857 return make_vector<unsigned>(ARM::R0, ARM::R1, ARM::R2, ARM::R3, 1858 ARM::R4, ARM::R5, ARM::R6, ARM::R7, 1859 ARM::R8, ARM::R9, ARM::R10, ARM::R11, 1860 ARM::R12, ARM::LR, 0); 1861 case 'w': 1862 if (VT == MVT::f32) 1863 return make_vector<unsigned>(ARM::S0, ARM::S1, ARM::S2, ARM::S3, 1864 ARM::S4, ARM::S5, ARM::S6, ARM::S7, 1865 ARM::S8, ARM::S9, ARM::S10, ARM::S11, 1866 ARM::S12,ARM::S13,ARM::S14,ARM::S15, 1867 ARM::S16,ARM::S17,ARM::S18,ARM::S19, 1868 ARM::S20,ARM::S21,ARM::S22,ARM::S23, 1869 ARM::S24,ARM::S25,ARM::S26,ARM::S27, 1870 ARM::S28,ARM::S29,ARM::S30,ARM::S31, 0); 1871 if (VT == MVT::f64) 1872 return make_vector<unsigned>(ARM::D0, ARM::D1, ARM::D2, ARM::D3, 1873 ARM::D4, ARM::D5, ARM::D6, ARM::D7, 1874 ARM::D8, ARM::D9, ARM::D10,ARM::D11, 1875 ARM::D12,ARM::D13,ARM::D14,ARM::D15, 0); 1876 break; 1877 } 1878 1879 return std::vector<unsigned>(); 1880} 1881