ARMISelLowering.cpp revision f5aeb1a8e4cf272c7348376d185ef8d8267653e0
1//===-- ARMISelLowering.cpp - ARM DAG Lowering Implementation -------------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file defines the interfaces that ARM uses to lower LLVM code into a 11// selection DAG. 12// 13//===----------------------------------------------------------------------===// 14 15#include "ARM.h" 16#include "ARMAddressingModes.h" 17#include "ARMConstantPoolValue.h" 18#include "ARMISelLowering.h" 19#include "ARMMachineFunctionInfo.h" 20#include "ARMRegisterInfo.h" 21#include "ARMSubtarget.h" 22#include "ARMTargetMachine.h" 23#include "llvm/CallingConv.h" 24#include "llvm/Constants.h" 25#include "llvm/Instruction.h" 26#include "llvm/Intrinsics.h" 27#include "llvm/GlobalValue.h" 28#include "llvm/CodeGen/MachineBasicBlock.h" 29#include "llvm/CodeGen/MachineFrameInfo.h" 30#include "llvm/CodeGen/MachineFunction.h" 31#include "llvm/CodeGen/MachineInstrBuilder.h" 32#include "llvm/CodeGen/MachineRegisterInfo.h" 33#include "llvm/CodeGen/SelectionDAG.h" 34#include "llvm/Target/TargetOptions.h" 35#include "llvm/ADT/VectorExtras.h" 36#include "llvm/Support/MathExtras.h" 37using namespace llvm; 38 39ARMTargetLowering::ARMTargetLowering(TargetMachine &TM) 40 : TargetLowering(TM), ARMPCLabelIndex(0) { 41 Subtarget = &TM.getSubtarget<ARMSubtarget>(); 42 43 if (Subtarget->isTargetDarwin()) { 44 // Don't have these. 45 setLibcallName(RTLIB::UINTTOFP_I64_F32, NULL); 46 setLibcallName(RTLIB::UINTTOFP_I64_F64, NULL); 47 48 // Uses VFP for Thumb libfuncs if available. 49 if (Subtarget->isThumb() && Subtarget->hasVFP2()) { 50 // Single-precision floating-point arithmetic. 51 setLibcallName(RTLIB::ADD_F32, "__addsf3vfp"); 52 setLibcallName(RTLIB::SUB_F32, "__subsf3vfp"); 53 setLibcallName(RTLIB::MUL_F32, "__mulsf3vfp"); 54 setLibcallName(RTLIB::DIV_F32, "__divsf3vfp"); 55 56 // Double-precision floating-point arithmetic. 57 setLibcallName(RTLIB::ADD_F64, "__adddf3vfp"); 58 setLibcallName(RTLIB::SUB_F64, "__subdf3vfp"); 59 setLibcallName(RTLIB::MUL_F64, "__muldf3vfp"); 60 setLibcallName(RTLIB::DIV_F64, "__divdf3vfp"); 61 62 // Single-precision comparisons. 63 setLibcallName(RTLIB::OEQ_F32, "__eqsf2vfp"); 64 setLibcallName(RTLIB::UNE_F32, "__nesf2vfp"); 65 setLibcallName(RTLIB::OLT_F32, "__ltsf2vfp"); 66 setLibcallName(RTLIB::OLE_F32, "__lesf2vfp"); 67 setLibcallName(RTLIB::OGE_F32, "__gesf2vfp"); 68 setLibcallName(RTLIB::OGT_F32, "__gtsf2vfp"); 69 setLibcallName(RTLIB::UO_F32, "__unordsf2vfp"); 70 setLibcallName(RTLIB::O_F32, "__unordsf2vfp"); 71 72 setCmpLibcallCC(RTLIB::OEQ_F32, ISD::SETNE); 73 setCmpLibcallCC(RTLIB::UNE_F32, ISD::SETNE); 74 setCmpLibcallCC(RTLIB::OLT_F32, ISD::SETNE); 75 setCmpLibcallCC(RTLIB::OLE_F32, ISD::SETNE); 76 setCmpLibcallCC(RTLIB::OGE_F32, ISD::SETNE); 77 setCmpLibcallCC(RTLIB::OGT_F32, ISD::SETNE); 78 setCmpLibcallCC(RTLIB::UO_F32, ISD::SETNE); 79 setCmpLibcallCC(RTLIB::O_F32, ISD::SETEQ); 80 81 // Double-precision comparisons. 82 setLibcallName(RTLIB::OEQ_F64, "__eqdf2vfp"); 83 setLibcallName(RTLIB::UNE_F64, "__nedf2vfp"); 84 setLibcallName(RTLIB::OLT_F64, "__ltdf2vfp"); 85 setLibcallName(RTLIB::OLE_F64, "__ledf2vfp"); 86 setLibcallName(RTLIB::OGE_F64, "__gedf2vfp"); 87 setLibcallName(RTLIB::OGT_F64, "__gtdf2vfp"); 88 setLibcallName(RTLIB::UO_F64, "__unorddf2vfp"); 89 setLibcallName(RTLIB::O_F64, "__unorddf2vfp"); 90 91 setCmpLibcallCC(RTLIB::OEQ_F64, ISD::SETNE); 92 setCmpLibcallCC(RTLIB::UNE_F64, ISD::SETNE); 93 setCmpLibcallCC(RTLIB::OLT_F64, ISD::SETNE); 94 setCmpLibcallCC(RTLIB::OLE_F64, ISD::SETNE); 95 setCmpLibcallCC(RTLIB::OGE_F64, ISD::SETNE); 96 setCmpLibcallCC(RTLIB::OGT_F64, ISD::SETNE); 97 setCmpLibcallCC(RTLIB::UO_F64, ISD::SETNE); 98 setCmpLibcallCC(RTLIB::O_F64, ISD::SETEQ); 99 100 // Floating-point to integer conversions. 101 // i64 conversions are done via library routines even when generating VFP 102 // instructions, so use the same ones. 103 setLibcallName(RTLIB::FPTOSINT_F64_I32, "__fixdfsivfp"); 104 setLibcallName(RTLIB::FPTOUINT_F64_I32, "__fixunsdfsivfp"); 105 setLibcallName(RTLIB::FPTOSINT_F32_I32, "__fixsfsivfp"); 106 setLibcallName(RTLIB::FPTOUINT_F32_I32, "__fixunssfsivfp"); 107 108 // Conversions between floating types. 109 setLibcallName(RTLIB::FPROUND_F64_F32, "__truncdfsf2vfp"); 110 setLibcallName(RTLIB::FPEXT_F32_F64, "__extendsfdf2vfp"); 111 112 // Integer to floating-point conversions. 113 // i64 conversions are done via library routines even when generating VFP 114 // instructions, so use the same ones. 115 // FIXME: There appears to be some naming inconsistency in ARM libgcc: e.g. 116 // __floatunsidf vs. __floatunssidfvfp. 117 setLibcallName(RTLIB::SINTTOFP_I32_F64, "__floatsidfvfp"); 118 setLibcallName(RTLIB::UINTTOFP_I32_F64, "__floatunssidfvfp"); 119 setLibcallName(RTLIB::SINTTOFP_I32_F32, "__floatsisfvfp"); 120 setLibcallName(RTLIB::UINTTOFP_I32_F32, "__floatunssisfvfp"); 121 } 122 } 123 124 addRegisterClass(MVT::i32, ARM::GPRRegisterClass); 125 if (!UseSoftFloat && Subtarget->hasVFP2() && !Subtarget->isThumb()) { 126 addRegisterClass(MVT::f32, ARM::SPRRegisterClass); 127 addRegisterClass(MVT::f64, ARM::DPRRegisterClass); 128 129 setTruncStoreAction(MVT::f64, MVT::f32, Expand); 130 } 131 computeRegisterProperties(); 132 133 // ARM does not have f32 extending load. 134 setLoadXAction(ISD::EXTLOAD, MVT::f32, Expand); 135 136 // ARM does not have i1 sign extending load. 137 setLoadXAction(ISD::SEXTLOAD, MVT::i1, Promote); 138 139 // ARM supports all 4 flavors of integer indexed load / store. 140 for (unsigned im = (unsigned)ISD::PRE_INC; 141 im != (unsigned)ISD::LAST_INDEXED_MODE; ++im) { 142 setIndexedLoadAction(im, MVT::i1, Legal); 143 setIndexedLoadAction(im, MVT::i8, Legal); 144 setIndexedLoadAction(im, MVT::i16, Legal); 145 setIndexedLoadAction(im, MVT::i32, Legal); 146 setIndexedStoreAction(im, MVT::i1, Legal); 147 setIndexedStoreAction(im, MVT::i8, Legal); 148 setIndexedStoreAction(im, MVT::i16, Legal); 149 setIndexedStoreAction(im, MVT::i32, Legal); 150 } 151 152 // i64 operation support. 153 if (Subtarget->isThumb()) { 154 setOperationAction(ISD::MUL, MVT::i64, Expand); 155 setOperationAction(ISD::MULHU, MVT::i32, Expand); 156 setOperationAction(ISD::MULHS, MVT::i32, Expand); 157 setOperationAction(ISD::UMUL_LOHI, MVT::i32, Expand); 158 setOperationAction(ISD::SMUL_LOHI, MVT::i32, Expand); 159 } else { 160 setOperationAction(ISD::MUL, MVT::i64, Expand); 161 setOperationAction(ISD::MULHU, MVT::i32, Expand); 162 if (!Subtarget->hasV6Ops()) 163 setOperationAction(ISD::MULHS, MVT::i32, Expand); 164 } 165 setOperationAction(ISD::SHL_PARTS, MVT::i32, Expand); 166 setOperationAction(ISD::SRA_PARTS, MVT::i32, Expand); 167 setOperationAction(ISD::SRL_PARTS, MVT::i32, Expand); 168 setOperationAction(ISD::SRL, MVT::i64, Custom); 169 setOperationAction(ISD::SRA, MVT::i64, Custom); 170 171 // ARM does not have ROTL. 172 setOperationAction(ISD::ROTL, MVT::i32, Expand); 173 setOperationAction(ISD::CTTZ , MVT::i32, Expand); 174 setOperationAction(ISD::CTPOP, MVT::i32, Expand); 175 if (!Subtarget->hasV5TOps() || Subtarget->isThumb()) 176 setOperationAction(ISD::CTLZ, MVT::i32, Expand); 177 178 // Only ARMv6 has BSWAP. 179 if (!Subtarget->hasV6Ops()) 180 setOperationAction(ISD::BSWAP, MVT::i32, Expand); 181 182 // These are expanded into libcalls. 183 setOperationAction(ISD::SDIV, MVT::i32, Expand); 184 setOperationAction(ISD::UDIV, MVT::i32, Expand); 185 setOperationAction(ISD::SREM, MVT::i32, Expand); 186 setOperationAction(ISD::UREM, MVT::i32, Expand); 187 setOperationAction(ISD::SDIVREM, MVT::i32, Expand); 188 setOperationAction(ISD::UDIVREM, MVT::i32, Expand); 189 190 // Support label based line numbers. 191 setOperationAction(ISD::DBG_STOPPOINT, MVT::Other, Expand); 192 setOperationAction(ISD::DEBUG_LOC, MVT::Other, Expand); 193 194 setOperationAction(ISD::RET, MVT::Other, Custom); 195 setOperationAction(ISD::GlobalAddress, MVT::i32, Custom); 196 setOperationAction(ISD::ConstantPool, MVT::i32, Custom); 197 setOperationAction(ISD::GLOBAL_OFFSET_TABLE, MVT::i32, Custom); 198 setOperationAction(ISD::GlobalTLSAddress, MVT::i32, Custom); 199 200 // Use the default implementation. 201 setOperationAction(ISD::VASTART , MVT::Other, Custom); 202 setOperationAction(ISD::VAARG , MVT::Other, Expand); 203 setOperationAction(ISD::VACOPY , MVT::Other, Expand); 204 setOperationAction(ISD::VAEND , MVT::Other, Expand); 205 setOperationAction(ISD::STACKSAVE, MVT::Other, Expand); 206 setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand); 207 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32 , Expand); 208 setOperationAction(ISD::MEMBARRIER , MVT::Other, Expand); 209 210 if (!Subtarget->hasV6Ops()) { 211 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16, Expand); 212 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8, Expand); 213 } 214 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand); 215 216 if (!UseSoftFloat && Subtarget->hasVFP2() && !Subtarget->isThumb()) 217 // Turn f64->i64 into FMRRD iff target supports vfp2. 218 setOperationAction(ISD::BIT_CONVERT, MVT::i64, Custom); 219 220 // We want to custom lower some of our intrinsics. 221 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom); 222 223 setOperationAction(ISD::SETCC , MVT::i32, Expand); 224 setOperationAction(ISD::SETCC , MVT::f32, Expand); 225 setOperationAction(ISD::SETCC , MVT::f64, Expand); 226 setOperationAction(ISD::SELECT , MVT::i32, Expand); 227 setOperationAction(ISD::SELECT , MVT::f32, Expand); 228 setOperationAction(ISD::SELECT , MVT::f64, Expand); 229 setOperationAction(ISD::SELECT_CC, MVT::i32, Custom); 230 setOperationAction(ISD::SELECT_CC, MVT::f32, Custom); 231 setOperationAction(ISD::SELECT_CC, MVT::f64, Custom); 232 233 setOperationAction(ISD::BRCOND , MVT::Other, Expand); 234 setOperationAction(ISD::BR_CC , MVT::i32, Custom); 235 setOperationAction(ISD::BR_CC , MVT::f32, Custom); 236 setOperationAction(ISD::BR_CC , MVT::f64, Custom); 237 setOperationAction(ISD::BR_JT , MVT::Other, Custom); 238 239 // We don't support sin/cos/fmod/copysign/pow 240 setOperationAction(ISD::FSIN , MVT::f64, Expand); 241 setOperationAction(ISD::FSIN , MVT::f32, Expand); 242 setOperationAction(ISD::FCOS , MVT::f32, Expand); 243 setOperationAction(ISD::FCOS , MVT::f64, Expand); 244 setOperationAction(ISD::FREM , MVT::f64, Expand); 245 setOperationAction(ISD::FREM , MVT::f32, Expand); 246 setOperationAction(ISD::FLOG , MVT::f64, Expand); 247 setOperationAction(ISD::FLOG , MVT::f32, Expand); 248 setOperationAction(ISD::FLOG2 , MVT::f64, Expand); 249 setOperationAction(ISD::FLOG2 , MVT::f32, Expand); 250 setOperationAction(ISD::FLOG10 , MVT::f64, Expand); 251 setOperationAction(ISD::FLOG10 , MVT::f32, Expand); 252 setOperationAction(ISD::FEXP , MVT::f64, Expand); 253 setOperationAction(ISD::FEXP , MVT::f32, Expand); 254 setOperationAction(ISD::FEXP2 , MVT::f64, Expand); 255 setOperationAction(ISD::FEXP2 , MVT::f32, Expand); 256 if (!UseSoftFloat && Subtarget->hasVFP2() && !Subtarget->isThumb()) { 257 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Custom); 258 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom); 259 } 260 setOperationAction(ISD::FPOW , MVT::f64, Expand); 261 setOperationAction(ISD::FPOW , MVT::f32, Expand); 262 263 // int <-> fp are custom expanded into bit_convert + ARMISD ops. 264 if (!UseSoftFloat && Subtarget->hasVFP2() && !Subtarget->isThumb()) { 265 setOperationAction(ISD::SINT_TO_FP, MVT::i32, Custom); 266 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Custom); 267 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Custom); 268 setOperationAction(ISD::FP_TO_SINT, MVT::i32, Custom); 269 } 270 271 // We have target-specific dag combine patterns for the following nodes: 272 // ARMISD::FMRRD - No need to call setTargetDAGCombine 273 274 setStackPointerRegisterToSaveRestore(ARM::SP); 275 setSchedulingPreference(SchedulingForRegPressure); 276 setIfCvtBlockSizeLimit(Subtarget->isThumb() ? 0 : 10); 277 setIfCvtDupBlockSizeLimit(Subtarget->isThumb() ? 0 : 2); 278 279 maxStoresPerMemcpy = 1; //// temporary - rewrite interface to use type 280} 281 282 283const char *ARMTargetLowering::getTargetNodeName(unsigned Opcode) const { 284 switch (Opcode) { 285 default: return 0; 286 case ARMISD::Wrapper: return "ARMISD::Wrapper"; 287 case ARMISD::WrapperJT: return "ARMISD::WrapperJT"; 288 case ARMISD::CALL: return "ARMISD::CALL"; 289 case ARMISD::CALL_PRED: return "ARMISD::CALL_PRED"; 290 case ARMISD::CALL_NOLINK: return "ARMISD::CALL_NOLINK"; 291 case ARMISD::tCALL: return "ARMISD::tCALL"; 292 case ARMISD::BRCOND: return "ARMISD::BRCOND"; 293 case ARMISD::BR_JT: return "ARMISD::BR_JT"; 294 case ARMISD::RET_FLAG: return "ARMISD::RET_FLAG"; 295 case ARMISD::PIC_ADD: return "ARMISD::PIC_ADD"; 296 case ARMISD::CMP: return "ARMISD::CMP"; 297 case ARMISD::CMPNZ: return "ARMISD::CMPNZ"; 298 case ARMISD::CMPFP: return "ARMISD::CMPFP"; 299 case ARMISD::CMPFPw0: return "ARMISD::CMPFPw0"; 300 case ARMISD::FMSTAT: return "ARMISD::FMSTAT"; 301 case ARMISD::CMOV: return "ARMISD::CMOV"; 302 case ARMISD::CNEG: return "ARMISD::CNEG"; 303 304 case ARMISD::FTOSI: return "ARMISD::FTOSI"; 305 case ARMISD::FTOUI: return "ARMISD::FTOUI"; 306 case ARMISD::SITOF: return "ARMISD::SITOF"; 307 case ARMISD::UITOF: return "ARMISD::UITOF"; 308 309 case ARMISD::SRL_FLAG: return "ARMISD::SRL_FLAG"; 310 case ARMISD::SRA_FLAG: return "ARMISD::SRA_FLAG"; 311 case ARMISD::RRX: return "ARMISD::RRX"; 312 313 case ARMISD::FMRRD: return "ARMISD::FMRRD"; 314 case ARMISD::FMDRR: return "ARMISD::FMDRR"; 315 316 case ARMISD::THREAD_POINTER:return "ARMISD::THREAD_POINTER"; 317 } 318} 319 320//===----------------------------------------------------------------------===// 321// Lowering Code 322//===----------------------------------------------------------------------===// 323 324 325/// IntCCToARMCC - Convert a DAG integer condition code to an ARM CC 326static ARMCC::CondCodes IntCCToARMCC(ISD::CondCode CC) { 327 switch (CC) { 328 default: assert(0 && "Unknown condition code!"); 329 case ISD::SETNE: return ARMCC::NE; 330 case ISD::SETEQ: return ARMCC::EQ; 331 case ISD::SETGT: return ARMCC::GT; 332 case ISD::SETGE: return ARMCC::GE; 333 case ISD::SETLT: return ARMCC::LT; 334 case ISD::SETLE: return ARMCC::LE; 335 case ISD::SETUGT: return ARMCC::HI; 336 case ISD::SETUGE: return ARMCC::HS; 337 case ISD::SETULT: return ARMCC::LO; 338 case ISD::SETULE: return ARMCC::LS; 339 } 340} 341 342/// FPCCToARMCC - Convert a DAG fp condition code to an ARM CC. It 343/// returns true if the operands should be inverted to form the proper 344/// comparison. 345static bool FPCCToARMCC(ISD::CondCode CC, ARMCC::CondCodes &CondCode, 346 ARMCC::CondCodes &CondCode2) { 347 bool Invert = false; 348 CondCode2 = ARMCC::AL; 349 switch (CC) { 350 default: assert(0 && "Unknown FP condition!"); 351 case ISD::SETEQ: 352 case ISD::SETOEQ: CondCode = ARMCC::EQ; break; 353 case ISD::SETGT: 354 case ISD::SETOGT: CondCode = ARMCC::GT; break; 355 case ISD::SETGE: 356 case ISD::SETOGE: CondCode = ARMCC::GE; break; 357 case ISD::SETOLT: CondCode = ARMCC::MI; break; 358 case ISD::SETOLE: CondCode = ARMCC::GT; Invert = true; break; 359 case ISD::SETONE: CondCode = ARMCC::MI; CondCode2 = ARMCC::GT; break; 360 case ISD::SETO: CondCode = ARMCC::VC; break; 361 case ISD::SETUO: CondCode = ARMCC::VS; break; 362 case ISD::SETUEQ: CondCode = ARMCC::EQ; CondCode2 = ARMCC::VS; break; 363 case ISD::SETUGT: CondCode = ARMCC::HI; break; 364 case ISD::SETUGE: CondCode = ARMCC::PL; break; 365 case ISD::SETLT: 366 case ISD::SETULT: CondCode = ARMCC::LT; break; 367 case ISD::SETLE: 368 case ISD::SETULE: CondCode = ARMCC::LE; break; 369 case ISD::SETNE: 370 case ISD::SETUNE: CondCode = ARMCC::NE; break; 371 } 372 return Invert; 373} 374 375static void 376HowToPassArgument(MVT ObjectVT, unsigned NumGPRs, 377 unsigned StackOffset, unsigned &NeededGPRs, 378 unsigned &NeededStackSize, unsigned &GPRPad, 379 unsigned &StackPad, ISD::ArgFlagsTy Flags) { 380 NeededStackSize = 0; 381 NeededGPRs = 0; 382 StackPad = 0; 383 GPRPad = 0; 384 unsigned align = Flags.getOrigAlign(); 385 GPRPad = NumGPRs % ((align + 3)/4); 386 StackPad = StackOffset % align; 387 unsigned firstGPR = NumGPRs + GPRPad; 388 switch (ObjectVT.getSimpleVT()) { 389 default: assert(0 && "Unhandled argument type!"); 390 case MVT::i32: 391 case MVT::f32: 392 if (firstGPR < 4) 393 NeededGPRs = 1; 394 else 395 NeededStackSize = 4; 396 break; 397 case MVT::i64: 398 case MVT::f64: 399 if (firstGPR < 3) 400 NeededGPRs = 2; 401 else if (firstGPR == 3) { 402 NeededGPRs = 1; 403 NeededStackSize = 4; 404 } else 405 NeededStackSize = 8; 406 } 407} 408 409/// LowerCALL - Lowering a ISD::CALL node into a callseq_start <- 410/// ARMISD:CALL <- callseq_end chain. Also add input and output parameter 411/// nodes. 412SDValue ARMTargetLowering::LowerCALL(SDValue Op, SelectionDAG &DAG) { 413 MVT RetVT= Op.getNode()->getValueType(0); 414 SDValue Chain = Op.getOperand(0); 415 unsigned CallConv = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue(); 416 assert((CallConv == CallingConv::C || 417 CallConv == CallingConv::Fast) && "unknown calling convention"); 418 SDValue Callee = Op.getOperand(4); 419 unsigned NumOps = (Op.getNumOperands() - 5) / 2; 420 unsigned ArgOffset = 0; // Frame mechanisms handle retaddr slot 421 unsigned NumGPRs = 0; // GPRs used for parameter passing. 422 423 // Count how many bytes are to be pushed on the stack. 424 unsigned NumBytes = 0; 425 426 // Add up all the space actually used. 427 for (unsigned i = 0; i < NumOps; ++i) { 428 unsigned ObjSize; 429 unsigned ObjGPRs; 430 unsigned StackPad; 431 unsigned GPRPad; 432 MVT ObjectVT = Op.getOperand(5+2*i).getValueType(); 433 ISD::ArgFlagsTy Flags = 434 cast<ARG_FLAGSSDNode>(Op.getOperand(5+2*i+1))->getArgFlags(); 435 HowToPassArgument(ObjectVT, NumGPRs, NumBytes, ObjGPRs, ObjSize, 436 GPRPad, StackPad, Flags); 437 NumBytes += ObjSize + StackPad; 438 NumGPRs += ObjGPRs + GPRPad; 439 } 440 441 // Adjust the stack pointer for the new arguments... 442 // These operations are automatically eliminated by the prolog/epilog pass 443 Chain = DAG.getCALLSEQ_START(Chain, 444 DAG.getConstant(NumBytes, MVT::i32)); 445 446 SDValue StackPtr = DAG.getRegister(ARM::SP, MVT::i32); 447 448 static const unsigned GPRArgRegs[] = { 449 ARM::R0, ARM::R1, ARM::R2, ARM::R3 450 }; 451 452 NumGPRs = 0; 453 std::vector<std::pair<unsigned, SDValue> > RegsToPass; 454 std::vector<SDValue> MemOpChains; 455 for (unsigned i = 0; i != NumOps; ++i) { 456 SDValue Arg = Op.getOperand(5+2*i); 457 ISD::ArgFlagsTy Flags = 458 cast<ARG_FLAGSSDNode>(Op.getOperand(5+2*i+1))->getArgFlags(); 459 MVT ArgVT = Arg.getValueType(); 460 461 unsigned ObjSize; 462 unsigned ObjGPRs; 463 unsigned GPRPad; 464 unsigned StackPad; 465 HowToPassArgument(ArgVT, NumGPRs, ArgOffset, ObjGPRs, 466 ObjSize, GPRPad, StackPad, Flags); 467 NumGPRs += GPRPad; 468 ArgOffset += StackPad; 469 if (ObjGPRs > 0) { 470 switch (ArgVT.getSimpleVT()) { 471 default: assert(0 && "Unexpected ValueType for argument!"); 472 case MVT::i32: 473 RegsToPass.push_back(std::make_pair(GPRArgRegs[NumGPRs], Arg)); 474 break; 475 case MVT::f32: 476 RegsToPass.push_back(std::make_pair(GPRArgRegs[NumGPRs], 477 DAG.getNode(ISD::BIT_CONVERT, MVT::i32, Arg))); 478 break; 479 case MVT::i64: { 480 SDValue Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32, Arg, 481 DAG.getConstant(0, getPointerTy())); 482 SDValue Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32, Arg, 483 DAG.getConstant(1, getPointerTy())); 484 RegsToPass.push_back(std::make_pair(GPRArgRegs[NumGPRs], Lo)); 485 if (ObjGPRs == 2) 486 RegsToPass.push_back(std::make_pair(GPRArgRegs[NumGPRs+1], Hi)); 487 else { 488 SDValue PtrOff= DAG.getConstant(ArgOffset, StackPtr.getValueType()); 489 PtrOff = DAG.getNode(ISD::ADD, MVT::i32, StackPtr, PtrOff); 490 MemOpChains.push_back(DAG.getStore(Chain, Hi, PtrOff, NULL, 0)); 491 } 492 break; 493 } 494 case MVT::f64: { 495 SDValue Cvt = DAG.getNode(ARMISD::FMRRD, 496 DAG.getVTList(MVT::i32, MVT::i32), 497 &Arg, 1); 498 RegsToPass.push_back(std::make_pair(GPRArgRegs[NumGPRs], Cvt)); 499 if (ObjGPRs == 2) 500 RegsToPass.push_back(std::make_pair(GPRArgRegs[NumGPRs+1], 501 Cvt.getValue(1))); 502 else { 503 SDValue PtrOff= DAG.getConstant(ArgOffset, StackPtr.getValueType()); 504 PtrOff = DAG.getNode(ISD::ADD, MVT::i32, StackPtr, PtrOff); 505 MemOpChains.push_back(DAG.getStore(Chain, Cvt.getValue(1), PtrOff, 506 NULL, 0)); 507 } 508 break; 509 } 510 } 511 } else { 512 assert(ObjSize != 0); 513 SDValue PtrOff = DAG.getConstant(ArgOffset, StackPtr.getValueType()); 514 PtrOff = DAG.getNode(ISD::ADD, MVT::i32, StackPtr, PtrOff); 515 MemOpChains.push_back(DAG.getStore(Chain, Arg, PtrOff, NULL, 0)); 516 } 517 518 NumGPRs += ObjGPRs; 519 ArgOffset += ObjSize; 520 } 521 522 if (!MemOpChains.empty()) 523 Chain = DAG.getNode(ISD::TokenFactor, MVT::Other, 524 &MemOpChains[0], MemOpChains.size()); 525 526 // Build a sequence of copy-to-reg nodes chained together with token chain 527 // and flag operands which copy the outgoing args into the appropriate regs. 528 SDValue InFlag; 529 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) { 530 Chain = DAG.getCopyToReg(Chain, RegsToPass[i].first, RegsToPass[i].second, 531 InFlag); 532 InFlag = Chain.getValue(1); 533 } 534 535 // If the callee is a GlobalAddress/ExternalSymbol node (quite common, every 536 // direct call is) turn it into a TargetGlobalAddress/TargetExternalSymbol 537 // node so that legalize doesn't hack it. 538 bool isDirect = false; 539 bool isARMFunc = false; 540 bool isLocalARMFunc = false; 541 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) { 542 GlobalValue *GV = G->getGlobal(); 543 isDirect = true; 544 bool isExt = (GV->isDeclaration() || GV->hasWeakLinkage() || 545 GV->hasLinkOnceLinkage()); 546 bool isStub = (isExt && Subtarget->isTargetDarwin()) && 547 getTargetMachine().getRelocationModel() != Reloc::Static; 548 isARMFunc = !Subtarget->isThumb() || isStub; 549 // ARM call to a local ARM function is predicable. 550 isLocalARMFunc = !Subtarget->isThumb() && !isExt; 551 // tBX takes a register source operand. 552 if (isARMFunc && Subtarget->isThumb() && !Subtarget->hasV5TOps()) { 553 ARMConstantPoolValue *CPV = new ARMConstantPoolValue(GV, ARMPCLabelIndex, 554 ARMCP::CPStub, 4); 555 SDValue CPAddr = DAG.getTargetConstantPool(CPV, getPointerTy(), 2); 556 CPAddr = DAG.getNode(ARMISD::Wrapper, MVT::i32, CPAddr); 557 Callee = DAG.getLoad(getPointerTy(), DAG.getEntryNode(), CPAddr, NULL, 0); 558 SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex++, MVT::i32); 559 Callee = DAG.getNode(ARMISD::PIC_ADD, getPointerTy(), Callee, PICLabel); 560 } else 561 Callee = DAG.getTargetGlobalAddress(GV, getPointerTy()); 562 } else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee)) { 563 isDirect = true; 564 bool isStub = Subtarget->isTargetDarwin() && 565 getTargetMachine().getRelocationModel() != Reloc::Static; 566 isARMFunc = !Subtarget->isThumb() || isStub; 567 // tBX takes a register source operand. 568 const char *Sym = S->getSymbol(); 569 if (isARMFunc && Subtarget->isThumb() && !Subtarget->hasV5TOps()) { 570 ARMConstantPoolValue *CPV = new ARMConstantPoolValue(Sym, ARMPCLabelIndex, 571 ARMCP::CPStub, 4); 572 SDValue CPAddr = DAG.getTargetConstantPool(CPV, getPointerTy(), 2); 573 CPAddr = DAG.getNode(ARMISD::Wrapper, MVT::i32, CPAddr); 574 Callee = DAG.getLoad(getPointerTy(), DAG.getEntryNode(), CPAddr, NULL, 0); 575 SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex++, MVT::i32); 576 Callee = DAG.getNode(ARMISD::PIC_ADD, getPointerTy(), Callee, PICLabel); 577 } else 578 Callee = DAG.getTargetExternalSymbol(Sym, getPointerTy()); 579 } 580 581 // FIXME: handle tail calls differently. 582 unsigned CallOpc; 583 if (Subtarget->isThumb()) { 584 if (!Subtarget->hasV5TOps() && (!isDirect || isARMFunc)) 585 CallOpc = ARMISD::CALL_NOLINK; 586 else 587 CallOpc = isARMFunc ? ARMISD::CALL : ARMISD::tCALL; 588 } else { 589 CallOpc = (isDirect || Subtarget->hasV5TOps()) 590 ? (isLocalARMFunc ? ARMISD::CALL_PRED : ARMISD::CALL) 591 : ARMISD::CALL_NOLINK; 592 } 593 if (CallOpc == ARMISD::CALL_NOLINK && !Subtarget->isThumb()) { 594 // implicit def LR - LR mustn't be allocated as GRP:$dst of CALL_NOLINK 595 Chain = DAG.getCopyToReg(Chain, ARM::LR, 596 DAG.getNode(ISD::UNDEF, MVT::i32), InFlag); 597 InFlag = Chain.getValue(1); 598 } 599 600 std::vector<SDValue> Ops; 601 Ops.push_back(Chain); 602 Ops.push_back(Callee); 603 604 // Add argument registers to the end of the list so that they are known live 605 // into the call. 606 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) 607 Ops.push_back(DAG.getRegister(RegsToPass[i].first, 608 RegsToPass[i].second.getValueType())); 609 610 if (InFlag.getNode()) 611 Ops.push_back(InFlag); 612 // Returns a chain and a flag for retval copy to use. 613 Chain = DAG.getNode(CallOpc, DAG.getVTList(MVT::Other, MVT::Flag), 614 &Ops[0], Ops.size()); 615 InFlag = Chain.getValue(1); 616 617 Chain = DAG.getCALLSEQ_END(Chain, 618 DAG.getConstant(NumBytes, MVT::i32), 619 DAG.getConstant(0, MVT::i32), 620 InFlag); 621 if (RetVT != MVT::Other) 622 InFlag = Chain.getValue(1); 623 624 std::vector<SDValue> ResultVals; 625 626 // If the call has results, copy the values out of the ret val registers. 627 switch (RetVT.getSimpleVT()) { 628 default: assert(0 && "Unexpected ret value!"); 629 case MVT::Other: 630 break; 631 case MVT::i32: 632 Chain = DAG.getCopyFromReg(Chain, ARM::R0, MVT::i32, InFlag).getValue(1); 633 ResultVals.push_back(Chain.getValue(0)); 634 if (Op.getNode()->getValueType(1) == MVT::i32) { 635 // Returns a i64 value. 636 Chain = DAG.getCopyFromReg(Chain, ARM::R1, MVT::i32, 637 Chain.getValue(2)).getValue(1); 638 ResultVals.push_back(Chain.getValue(0)); 639 } 640 break; 641 case MVT::f32: 642 Chain = DAG.getCopyFromReg(Chain, ARM::R0, MVT::i32, InFlag).getValue(1); 643 ResultVals.push_back(DAG.getNode(ISD::BIT_CONVERT, MVT::f32, 644 Chain.getValue(0))); 645 break; 646 case MVT::f64: { 647 SDValue Lo = DAG.getCopyFromReg(Chain, ARM::R0, MVT::i32, InFlag); 648 SDValue Hi = DAG.getCopyFromReg(Lo, ARM::R1, MVT::i32, Lo.getValue(2)); 649 ResultVals.push_back(DAG.getNode(ARMISD::FMDRR, MVT::f64, Lo, Hi)); 650 break; 651 } 652 } 653 654 if (ResultVals.empty()) 655 return Chain; 656 657 ResultVals.push_back(Chain); 658 SDValue Res = DAG.getMergeValues(&ResultVals[0], ResultVals.size()); 659 return Res.getValue(Op.getResNo()); 660} 661 662static SDValue LowerRET(SDValue Op, SelectionDAG &DAG) { 663 SDValue Copy; 664 SDValue Chain = Op.getOperand(0); 665 switch(Op.getNumOperands()) { 666 default: 667 assert(0 && "Do not know how to return this many arguments!"); 668 abort(); 669 case 1: { 670 SDValue LR = DAG.getRegister(ARM::LR, MVT::i32); 671 return DAG.getNode(ARMISD::RET_FLAG, MVT::Other, Chain); 672 } 673 case 3: 674 Op = Op.getOperand(1); 675 if (Op.getValueType() == MVT::f32) { 676 Op = DAG.getNode(ISD::BIT_CONVERT, MVT::i32, Op); 677 } else if (Op.getValueType() == MVT::f64) { 678 // Legalize ret f64 -> ret 2 x i32. We always have fmrrd if f64 is 679 // available. 680 Op = DAG.getNode(ARMISD::FMRRD, DAG.getVTList(MVT::i32, MVT::i32), &Op,1); 681 SDValue Sign = DAG.getConstant(0, MVT::i32); 682 return DAG.getNode(ISD::RET, MVT::Other, Chain, Op, Sign, 683 Op.getValue(1), Sign); 684 } 685 Copy = DAG.getCopyToReg(Chain, ARM::R0, Op, SDValue()); 686 if (DAG.getMachineFunction().getRegInfo().liveout_empty()) 687 DAG.getMachineFunction().getRegInfo().addLiveOut(ARM::R0); 688 break; 689 case 5: 690 Copy = DAG.getCopyToReg(Chain, ARM::R1, Op.getOperand(3), SDValue()); 691 Copy = DAG.getCopyToReg(Copy, ARM::R0, Op.getOperand(1), Copy.getValue(1)); 692 // If we haven't noted the R0+R1 are live out, do so now. 693 if (DAG.getMachineFunction().getRegInfo().liveout_empty()) { 694 DAG.getMachineFunction().getRegInfo().addLiveOut(ARM::R0); 695 DAG.getMachineFunction().getRegInfo().addLiveOut(ARM::R1); 696 } 697 break; 698 case 9: // i128 -> 4 regs 699 Copy = DAG.getCopyToReg(Chain, ARM::R3, Op.getOperand(7), SDValue()); 700 Copy = DAG.getCopyToReg(Copy , ARM::R2, Op.getOperand(5), Copy.getValue(1)); 701 Copy = DAG.getCopyToReg(Copy , ARM::R1, Op.getOperand(3), Copy.getValue(1)); 702 Copy = DAG.getCopyToReg(Copy , ARM::R0, Op.getOperand(1), Copy.getValue(1)); 703 // If we haven't noted the R0+R1 are live out, do so now. 704 if (DAG.getMachineFunction().getRegInfo().liveout_empty()) { 705 DAG.getMachineFunction().getRegInfo().addLiveOut(ARM::R0); 706 DAG.getMachineFunction().getRegInfo().addLiveOut(ARM::R1); 707 DAG.getMachineFunction().getRegInfo().addLiveOut(ARM::R2); 708 DAG.getMachineFunction().getRegInfo().addLiveOut(ARM::R3); 709 } 710 break; 711 712 } 713 714 //We must use RET_FLAG instead of BRIND because BRIND doesn't have a flag 715 return DAG.getNode(ARMISD::RET_FLAG, MVT::Other, Copy, Copy.getValue(1)); 716} 717 718// ConstantPool, JumpTable, GlobalAddress, and ExternalSymbol are lowered as 719// their target countpart wrapped in the ARMISD::Wrapper node. Suppose N is 720// one of the above mentioned nodes. It has to be wrapped because otherwise 721// Select(N) returns N. So the raw TargetGlobalAddress nodes, etc. can only 722// be used to form addressing mode. These wrapped nodes will be selected 723// into MOVi. 724static SDValue LowerConstantPool(SDValue Op, SelectionDAG &DAG) { 725 MVT PtrVT = Op.getValueType(); 726 ConstantPoolSDNode *CP = cast<ConstantPoolSDNode>(Op); 727 SDValue Res; 728 if (CP->isMachineConstantPoolEntry()) 729 Res = DAG.getTargetConstantPool(CP->getMachineCPVal(), PtrVT, 730 CP->getAlignment()); 731 else 732 Res = DAG.getTargetConstantPool(CP->getConstVal(), PtrVT, 733 CP->getAlignment()); 734 return DAG.getNode(ARMISD::Wrapper, MVT::i32, Res); 735} 736 737// Lower ISD::GlobalTLSAddress using the "general dynamic" model 738SDValue 739ARMTargetLowering::LowerToTLSGeneralDynamicModel(GlobalAddressSDNode *GA, 740 SelectionDAG &DAG) { 741 MVT PtrVT = getPointerTy(); 742 unsigned char PCAdj = Subtarget->isThumb() ? 4 : 8; 743 ARMConstantPoolValue *CPV = 744 new ARMConstantPoolValue(GA->getGlobal(), ARMPCLabelIndex, ARMCP::CPValue, 745 PCAdj, "tlsgd", true); 746 SDValue Argument = DAG.getTargetConstantPool(CPV, PtrVT, 2); 747 Argument = DAG.getNode(ARMISD::Wrapper, MVT::i32, Argument); 748 Argument = DAG.getLoad(PtrVT, DAG.getEntryNode(), Argument, NULL, 0); 749 SDValue Chain = Argument.getValue(1); 750 751 SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex++, MVT::i32); 752 Argument = DAG.getNode(ARMISD::PIC_ADD, PtrVT, Argument, PICLabel); 753 754 // call __tls_get_addr. 755 ArgListTy Args; 756 ArgListEntry Entry; 757 Entry.Node = Argument; 758 Entry.Ty = (const Type *) Type::Int32Ty; 759 Args.push_back(Entry); 760 std::pair<SDValue, SDValue> CallResult = 761 LowerCallTo(Chain, (const Type *) Type::Int32Ty, false, false, false, 762 CallingConv::C, false, 763 DAG.getExternalSymbol("__tls_get_addr", PtrVT), Args, DAG); 764 return CallResult.first; 765} 766 767// Lower ISD::GlobalTLSAddress using the "initial exec" or 768// "local exec" model. 769SDValue 770ARMTargetLowering::LowerToTLSExecModels(GlobalAddressSDNode *GA, 771 SelectionDAG &DAG) { 772 GlobalValue *GV = GA->getGlobal(); 773 SDValue Offset; 774 SDValue Chain = DAG.getEntryNode(); 775 MVT PtrVT = getPointerTy(); 776 // Get the Thread Pointer 777 SDValue ThreadPointer = DAG.getNode(ARMISD::THREAD_POINTER, PtrVT); 778 779 if (GV->isDeclaration()){ 780 // initial exec model 781 unsigned char PCAdj = Subtarget->isThumb() ? 4 : 8; 782 ARMConstantPoolValue *CPV = 783 new ARMConstantPoolValue(GA->getGlobal(), ARMPCLabelIndex, ARMCP::CPValue, 784 PCAdj, "gottpoff", true); 785 Offset = DAG.getTargetConstantPool(CPV, PtrVT, 2); 786 Offset = DAG.getNode(ARMISD::Wrapper, MVT::i32, Offset); 787 Offset = DAG.getLoad(PtrVT, Chain, Offset, NULL, 0); 788 Chain = Offset.getValue(1); 789 790 SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex++, MVT::i32); 791 Offset = DAG.getNode(ARMISD::PIC_ADD, PtrVT, Offset, PICLabel); 792 793 Offset = DAG.getLoad(PtrVT, Chain, Offset, NULL, 0); 794 } else { 795 // local exec model 796 ARMConstantPoolValue *CPV = 797 new ARMConstantPoolValue(GV, ARMCP::CPValue, "tpoff"); 798 Offset = DAG.getTargetConstantPool(CPV, PtrVT, 2); 799 Offset = DAG.getNode(ARMISD::Wrapper, MVT::i32, Offset); 800 Offset = DAG.getLoad(PtrVT, Chain, Offset, NULL, 0); 801 } 802 803 // The address of the thread local variable is the add of the thread 804 // pointer with the offset of the variable. 805 return DAG.getNode(ISD::ADD, PtrVT, ThreadPointer, Offset); 806} 807 808SDValue 809ARMTargetLowering::LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) { 810 // TODO: implement the "local dynamic" model 811 assert(Subtarget->isTargetELF() && 812 "TLS not implemented for non-ELF targets"); 813 GlobalAddressSDNode *GA = cast<GlobalAddressSDNode>(Op); 814 // If the relocation model is PIC, use the "General Dynamic" TLS Model, 815 // otherwise use the "Local Exec" TLS Model 816 if (getTargetMachine().getRelocationModel() == Reloc::PIC_) 817 return LowerToTLSGeneralDynamicModel(GA, DAG); 818 else 819 return LowerToTLSExecModels(GA, DAG); 820} 821 822SDValue ARMTargetLowering::LowerGlobalAddressELF(SDValue Op, 823 SelectionDAG &DAG) { 824 MVT PtrVT = getPointerTy(); 825 GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal(); 826 Reloc::Model RelocM = getTargetMachine().getRelocationModel(); 827 if (RelocM == Reloc::PIC_) { 828 bool UseGOTOFF = GV->hasInternalLinkage() || GV->hasHiddenVisibility(); 829 ARMConstantPoolValue *CPV = 830 new ARMConstantPoolValue(GV, ARMCP::CPValue, UseGOTOFF ? "GOTOFF":"GOT"); 831 SDValue CPAddr = DAG.getTargetConstantPool(CPV, PtrVT, 2); 832 CPAddr = DAG.getNode(ARMISD::Wrapper, MVT::i32, CPAddr); 833 SDValue Result = DAG.getLoad(PtrVT, DAG.getEntryNode(), CPAddr, NULL, 0); 834 SDValue Chain = Result.getValue(1); 835 SDValue GOT = DAG.getNode(ISD::GLOBAL_OFFSET_TABLE, PtrVT); 836 Result = DAG.getNode(ISD::ADD, PtrVT, Result, GOT); 837 if (!UseGOTOFF) 838 Result = DAG.getLoad(PtrVT, Chain, Result, NULL, 0); 839 return Result; 840 } else { 841 SDValue CPAddr = DAG.getTargetConstantPool(GV, PtrVT, 2); 842 CPAddr = DAG.getNode(ARMISD::Wrapper, MVT::i32, CPAddr); 843 return DAG.getLoad(PtrVT, DAG.getEntryNode(), CPAddr, NULL, 0); 844 } 845} 846 847/// GVIsIndirectSymbol - true if the GV will be accessed via an indirect symbol 848/// even in non-static mode. 849static bool GVIsIndirectSymbol(GlobalValue *GV, Reloc::Model RelocM) { 850 return RelocM != Reloc::Static && 851 (GV->hasWeakLinkage() || GV->hasLinkOnceLinkage() || 852 (GV->isDeclaration() && !GV->hasNotBeenReadFromBitcode())); 853} 854 855SDValue ARMTargetLowering::LowerGlobalAddressDarwin(SDValue Op, 856 SelectionDAG &DAG) { 857 MVT PtrVT = getPointerTy(); 858 GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal(); 859 Reloc::Model RelocM = getTargetMachine().getRelocationModel(); 860 bool IsIndirect = GVIsIndirectSymbol(GV, RelocM); 861 SDValue CPAddr; 862 if (RelocM == Reloc::Static) 863 CPAddr = DAG.getTargetConstantPool(GV, PtrVT, 2); 864 else { 865 unsigned PCAdj = (RelocM != Reloc::PIC_) 866 ? 0 : (Subtarget->isThumb() ? 4 : 8); 867 ARMCP::ARMCPKind Kind = IsIndirect ? ARMCP::CPNonLazyPtr 868 : ARMCP::CPValue; 869 ARMConstantPoolValue *CPV = new ARMConstantPoolValue(GV, ARMPCLabelIndex, 870 Kind, PCAdj); 871 CPAddr = DAG.getTargetConstantPool(CPV, PtrVT, 2); 872 } 873 CPAddr = DAG.getNode(ARMISD::Wrapper, MVT::i32, CPAddr); 874 875 SDValue Result = DAG.getLoad(PtrVT, DAG.getEntryNode(), CPAddr, NULL, 0); 876 SDValue Chain = Result.getValue(1); 877 878 if (RelocM == Reloc::PIC_) { 879 SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex++, MVT::i32); 880 Result = DAG.getNode(ARMISD::PIC_ADD, PtrVT, Result, PICLabel); 881 } 882 if (IsIndirect) 883 Result = DAG.getLoad(PtrVT, Chain, Result, NULL, 0); 884 885 return Result; 886} 887 888SDValue ARMTargetLowering::LowerGLOBAL_OFFSET_TABLE(SDValue Op, 889 SelectionDAG &DAG){ 890 assert(Subtarget->isTargetELF() && 891 "GLOBAL OFFSET TABLE not implemented for non-ELF targets"); 892 MVT PtrVT = getPointerTy(); 893 unsigned PCAdj = Subtarget->isThumb() ? 4 : 8; 894 ARMConstantPoolValue *CPV = new ARMConstantPoolValue("_GLOBAL_OFFSET_TABLE_", 895 ARMPCLabelIndex, 896 ARMCP::CPValue, PCAdj); 897 SDValue CPAddr = DAG.getTargetConstantPool(CPV, PtrVT, 2); 898 CPAddr = DAG.getNode(ARMISD::Wrapper, MVT::i32, CPAddr); 899 SDValue Result = DAG.getLoad(PtrVT, DAG.getEntryNode(), CPAddr, NULL, 0); 900 SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex++, MVT::i32); 901 return DAG.getNode(ARMISD::PIC_ADD, PtrVT, Result, PICLabel); 902} 903 904static SDValue LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) { 905 MVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy(); 906 unsigned IntNo = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue(); 907 switch (IntNo) { 908 default: return SDValue(); // Don't custom lower most intrinsics. 909 case Intrinsic::arm_thread_pointer: 910 return DAG.getNode(ARMISD::THREAD_POINTER, PtrVT); 911 } 912} 913 914static SDValue LowerVASTART(SDValue Op, SelectionDAG &DAG, 915 unsigned VarArgsFrameIndex) { 916 // vastart just stores the address of the VarArgsFrameIndex slot into the 917 // memory location argument. 918 MVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy(); 919 SDValue FR = DAG.getFrameIndex(VarArgsFrameIndex, PtrVT); 920 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue(); 921 return DAG.getStore(Op.getOperand(0), FR, Op.getOperand(1), SV, 0); 922} 923 924static SDValue LowerFORMAL_ARGUMENT(SDValue Op, SelectionDAG &DAG, 925 unsigned ArgNo, unsigned &NumGPRs, 926 unsigned &ArgOffset) { 927 MachineFunction &MF = DAG.getMachineFunction(); 928 MVT ObjectVT = Op.getValue(ArgNo).getValueType(); 929 SDValue Root = Op.getOperand(0); 930 MachineRegisterInfo &RegInfo = MF.getRegInfo(); 931 932 static const unsigned GPRArgRegs[] = { 933 ARM::R0, ARM::R1, ARM::R2, ARM::R3 934 }; 935 936 unsigned ObjSize; 937 unsigned ObjGPRs; 938 unsigned GPRPad; 939 unsigned StackPad; 940 ISD::ArgFlagsTy Flags = 941 cast<ARG_FLAGSSDNode>(Op.getOperand(ArgNo + 3))->getArgFlags(); 942 HowToPassArgument(ObjectVT, NumGPRs, ArgOffset, ObjGPRs, 943 ObjSize, GPRPad, StackPad, Flags); 944 NumGPRs += GPRPad; 945 ArgOffset += StackPad; 946 947 SDValue ArgValue; 948 if (ObjGPRs == 1) { 949 unsigned VReg = RegInfo.createVirtualRegister(&ARM::GPRRegClass); 950 RegInfo.addLiveIn(GPRArgRegs[NumGPRs], VReg); 951 ArgValue = DAG.getCopyFromReg(Root, VReg, MVT::i32); 952 if (ObjectVT == MVT::f32) 953 ArgValue = DAG.getNode(ISD::BIT_CONVERT, MVT::f32, ArgValue); 954 } else if (ObjGPRs == 2) { 955 unsigned VReg = RegInfo.createVirtualRegister(&ARM::GPRRegClass); 956 RegInfo.addLiveIn(GPRArgRegs[NumGPRs], VReg); 957 ArgValue = DAG.getCopyFromReg(Root, VReg, MVT::i32); 958 959 VReg = RegInfo.createVirtualRegister(&ARM::GPRRegClass); 960 RegInfo.addLiveIn(GPRArgRegs[NumGPRs+1], VReg); 961 SDValue ArgValue2 = DAG.getCopyFromReg(Root, VReg, MVT::i32); 962 963 assert(ObjectVT != MVT::i64 && "i64 should already be lowered"); 964 ArgValue = DAG.getNode(ARMISD::FMDRR, MVT::f64, ArgValue, ArgValue2); 965 } 966 NumGPRs += ObjGPRs; 967 968 if (ObjSize) { 969 MachineFrameInfo *MFI = MF.getFrameInfo(); 970 int FI = MFI->CreateFixedObject(ObjSize, ArgOffset); 971 SDValue FIN = DAG.getFrameIndex(FI, MVT::i32); 972 if (ObjGPRs == 0) 973 ArgValue = DAG.getLoad(ObjectVT, Root, FIN, NULL, 0); 974 else { 975 SDValue ArgValue2 = DAG.getLoad(MVT::i32, Root, FIN, NULL, 0); 976 assert(ObjectVT != MVT::i64 && "i64 should already be lowered"); 977 ArgValue = DAG.getNode(ARMISD::FMDRR, MVT::f64, ArgValue, ArgValue2); 978 } 979 980 ArgOffset += ObjSize; // Move on to the next argument. 981 } 982 983 return ArgValue; 984} 985 986SDValue 987ARMTargetLowering::LowerFORMAL_ARGUMENTS(SDValue Op, SelectionDAG &DAG) { 988 std::vector<SDValue> ArgValues; 989 SDValue Root = Op.getOperand(0); 990 unsigned ArgOffset = 0; // Frame mechanisms handle retaddr slot 991 unsigned NumGPRs = 0; // GPRs used for parameter passing. 992 993 unsigned NumArgs = Op.getNode()->getNumValues()-1; 994 for (unsigned ArgNo = 0; ArgNo < NumArgs; ++ArgNo) 995 ArgValues.push_back(LowerFORMAL_ARGUMENT(Op, DAG, ArgNo, 996 NumGPRs, ArgOffset)); 997 998 bool isVarArg = cast<ConstantSDNode>(Op.getOperand(2))->getZExtValue() != 0; 999 if (isVarArg) { 1000 static const unsigned GPRArgRegs[] = { 1001 ARM::R0, ARM::R1, ARM::R2, ARM::R3 1002 }; 1003 1004 MachineFunction &MF = DAG.getMachineFunction(); 1005 MachineRegisterInfo &RegInfo = MF.getRegInfo(); 1006 MachineFrameInfo *MFI = MF.getFrameInfo(); 1007 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>(); 1008 unsigned Align = MF.getTarget().getFrameInfo()->getStackAlignment(); 1009 unsigned VARegSize = (4 - NumGPRs) * 4; 1010 unsigned VARegSaveSize = (VARegSize + Align - 1) & ~(Align - 1); 1011 if (VARegSaveSize) { 1012 // If this function is vararg, store any remaining integer argument regs 1013 // to their spots on the stack so that they may be loaded by deferencing 1014 // the result of va_next. 1015 AFI->setVarArgsRegSaveSize(VARegSaveSize); 1016 VarArgsFrameIndex = MFI->CreateFixedObject(VARegSaveSize, ArgOffset + 1017 VARegSaveSize - VARegSize); 1018 SDValue FIN = DAG.getFrameIndex(VarArgsFrameIndex, getPointerTy()); 1019 1020 SmallVector<SDValue, 4> MemOps; 1021 for (; NumGPRs < 4; ++NumGPRs) { 1022 unsigned VReg = RegInfo.createVirtualRegister(&ARM::GPRRegClass); 1023 RegInfo.addLiveIn(GPRArgRegs[NumGPRs], VReg); 1024 SDValue Val = DAG.getCopyFromReg(Root, VReg, MVT::i32); 1025 SDValue Store = DAG.getStore(Val.getValue(1), Val, FIN, NULL, 0); 1026 MemOps.push_back(Store); 1027 FIN = DAG.getNode(ISD::ADD, getPointerTy(), FIN, 1028 DAG.getConstant(4, getPointerTy())); 1029 } 1030 if (!MemOps.empty()) 1031 Root = DAG.getNode(ISD::TokenFactor, MVT::Other, 1032 &MemOps[0], MemOps.size()); 1033 } else 1034 // This will point to the next argument passed via stack. 1035 VarArgsFrameIndex = MFI->CreateFixedObject(4, ArgOffset); 1036 } 1037 1038 ArgValues.push_back(Root); 1039 1040 // Return the new list of results. 1041 return DAG.getMergeValues(Op.getNode()->getVTList(), &ArgValues[0], 1042 ArgValues.size()); 1043} 1044 1045/// isFloatingPointZero - Return true if this is +0.0. 1046static bool isFloatingPointZero(SDValue Op) { 1047 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(Op)) 1048 return CFP->getValueAPF().isPosZero(); 1049 else if (ISD::isEXTLoad(Op.getNode()) || ISD::isNON_EXTLoad(Op.getNode())) { 1050 // Maybe this has already been legalized into the constant pool? 1051 if (Op.getOperand(1).getOpcode() == ARMISD::Wrapper) { 1052 SDValue WrapperOp = Op.getOperand(1).getOperand(0); 1053 if (ConstantPoolSDNode *CP = dyn_cast<ConstantPoolSDNode>(WrapperOp)) 1054 if (ConstantFP *CFP = dyn_cast<ConstantFP>(CP->getConstVal())) 1055 return CFP->getValueAPF().isPosZero(); 1056 } 1057 } 1058 return false; 1059} 1060 1061static bool isLegalCmpImmediate(unsigned C, bool isThumb) { 1062 return ( isThumb && (C & ~255U) == 0) || 1063 (!isThumb && ARM_AM::getSOImmVal(C) != -1); 1064} 1065 1066/// Returns appropriate ARM CMP (cmp) and corresponding condition code for 1067/// the given operands. 1068static SDValue getARMCmp(SDValue LHS, SDValue RHS, ISD::CondCode CC, 1069 SDValue &ARMCC, SelectionDAG &DAG, bool isThumb) { 1070 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(RHS.getNode())) { 1071 unsigned C = RHSC->getZExtValue(); 1072 if (!isLegalCmpImmediate(C, isThumb)) { 1073 // Constant does not fit, try adjusting it by one? 1074 switch (CC) { 1075 default: break; 1076 case ISD::SETLT: 1077 case ISD::SETGE: 1078 if (isLegalCmpImmediate(C-1, isThumb)) { 1079 CC = (CC == ISD::SETLT) ? ISD::SETLE : ISD::SETGT; 1080 RHS = DAG.getConstant(C-1, MVT::i32); 1081 } 1082 break; 1083 case ISD::SETULT: 1084 case ISD::SETUGE: 1085 if (C > 0 && isLegalCmpImmediate(C-1, isThumb)) { 1086 CC = (CC == ISD::SETULT) ? ISD::SETULE : ISD::SETUGT; 1087 RHS = DAG.getConstant(C-1, MVT::i32); 1088 } 1089 break; 1090 case ISD::SETLE: 1091 case ISD::SETGT: 1092 if (isLegalCmpImmediate(C+1, isThumb)) { 1093 CC = (CC == ISD::SETLE) ? ISD::SETLT : ISD::SETGE; 1094 RHS = DAG.getConstant(C+1, MVT::i32); 1095 } 1096 break; 1097 case ISD::SETULE: 1098 case ISD::SETUGT: 1099 if (C < 0xffffffff && isLegalCmpImmediate(C+1, isThumb)) { 1100 CC = (CC == ISD::SETULE) ? ISD::SETULT : ISD::SETUGE; 1101 RHS = DAG.getConstant(C+1, MVT::i32); 1102 } 1103 break; 1104 } 1105 } 1106 } 1107 1108 ARMCC::CondCodes CondCode = IntCCToARMCC(CC); 1109 ARMISD::NodeType CompareType; 1110 switch (CondCode) { 1111 default: 1112 CompareType = ARMISD::CMP; 1113 break; 1114 case ARMCC::EQ: 1115 case ARMCC::NE: 1116 case ARMCC::MI: 1117 case ARMCC::PL: 1118 // Uses only N and Z Flags 1119 CompareType = ARMISD::CMPNZ; 1120 break; 1121 } 1122 ARMCC = DAG.getConstant(CondCode, MVT::i32); 1123 return DAG.getNode(CompareType, MVT::Flag, LHS, RHS); 1124} 1125 1126/// Returns a appropriate VFP CMP (fcmp{s|d}+fmstat) for the given operands. 1127static SDValue getVFPCmp(SDValue LHS, SDValue RHS, SelectionDAG &DAG) { 1128 SDValue Cmp; 1129 if (!isFloatingPointZero(RHS)) 1130 Cmp = DAG.getNode(ARMISD::CMPFP, MVT::Flag, LHS, RHS); 1131 else 1132 Cmp = DAG.getNode(ARMISD::CMPFPw0, MVT::Flag, LHS); 1133 return DAG.getNode(ARMISD::FMSTAT, MVT::Flag, Cmp); 1134} 1135 1136static SDValue LowerSELECT_CC(SDValue Op, SelectionDAG &DAG, 1137 const ARMSubtarget *ST) { 1138 MVT VT = Op.getValueType(); 1139 SDValue LHS = Op.getOperand(0); 1140 SDValue RHS = Op.getOperand(1); 1141 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(4))->get(); 1142 SDValue TrueVal = Op.getOperand(2); 1143 SDValue FalseVal = Op.getOperand(3); 1144 1145 if (LHS.getValueType() == MVT::i32) { 1146 SDValue ARMCC; 1147 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32); 1148 SDValue Cmp = getARMCmp(LHS, RHS, CC, ARMCC, DAG, ST->isThumb()); 1149 return DAG.getNode(ARMISD::CMOV, VT, FalseVal, TrueVal, ARMCC, CCR, Cmp); 1150 } 1151 1152 ARMCC::CondCodes CondCode, CondCode2; 1153 if (FPCCToARMCC(CC, CondCode, CondCode2)) 1154 std::swap(TrueVal, FalseVal); 1155 1156 SDValue ARMCC = DAG.getConstant(CondCode, MVT::i32); 1157 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32); 1158 SDValue Cmp = getVFPCmp(LHS, RHS, DAG); 1159 SDValue Result = DAG.getNode(ARMISD::CMOV, VT, FalseVal, TrueVal, 1160 ARMCC, CCR, Cmp); 1161 if (CondCode2 != ARMCC::AL) { 1162 SDValue ARMCC2 = DAG.getConstant(CondCode2, MVT::i32); 1163 // FIXME: Needs another CMP because flag can have but one use. 1164 SDValue Cmp2 = getVFPCmp(LHS, RHS, DAG); 1165 Result = DAG.getNode(ARMISD::CMOV, VT, Result, TrueVal, ARMCC2, CCR, Cmp2); 1166 } 1167 return Result; 1168} 1169 1170static SDValue LowerBR_CC(SDValue Op, SelectionDAG &DAG, 1171 const ARMSubtarget *ST) { 1172 SDValue Chain = Op.getOperand(0); 1173 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(1))->get(); 1174 SDValue LHS = Op.getOperand(2); 1175 SDValue RHS = Op.getOperand(3); 1176 SDValue Dest = Op.getOperand(4); 1177 1178 if (LHS.getValueType() == MVT::i32) { 1179 SDValue ARMCC; 1180 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32); 1181 SDValue Cmp = getARMCmp(LHS, RHS, CC, ARMCC, DAG, ST->isThumb()); 1182 return DAG.getNode(ARMISD::BRCOND, MVT::Other, Chain, Dest, ARMCC, CCR,Cmp); 1183 } 1184 1185 assert(LHS.getValueType() == MVT::f32 || LHS.getValueType() == MVT::f64); 1186 ARMCC::CondCodes CondCode, CondCode2; 1187 if (FPCCToARMCC(CC, CondCode, CondCode2)) 1188 // Swap the LHS/RHS of the comparison if needed. 1189 std::swap(LHS, RHS); 1190 1191 SDValue Cmp = getVFPCmp(LHS, RHS, DAG); 1192 SDValue ARMCC = DAG.getConstant(CondCode, MVT::i32); 1193 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32); 1194 SDVTList VTList = DAG.getVTList(MVT::Other, MVT::Flag); 1195 SDValue Ops[] = { Chain, Dest, ARMCC, CCR, Cmp }; 1196 SDValue Res = DAG.getNode(ARMISD::BRCOND, VTList, Ops, 5); 1197 if (CondCode2 != ARMCC::AL) { 1198 ARMCC = DAG.getConstant(CondCode2, MVT::i32); 1199 SDValue Ops[] = { Res, Dest, ARMCC, CCR, Res.getValue(1) }; 1200 Res = DAG.getNode(ARMISD::BRCOND, VTList, Ops, 5); 1201 } 1202 return Res; 1203} 1204 1205SDValue ARMTargetLowering::LowerBR_JT(SDValue Op, SelectionDAG &DAG) { 1206 SDValue Chain = Op.getOperand(0); 1207 SDValue Table = Op.getOperand(1); 1208 SDValue Index = Op.getOperand(2); 1209 1210 MVT PTy = getPointerTy(); 1211 JumpTableSDNode *JT = cast<JumpTableSDNode>(Table); 1212 ARMFunctionInfo *AFI = DAG.getMachineFunction().getInfo<ARMFunctionInfo>(); 1213 SDValue UId = DAG.getConstant(AFI->createJumpTableUId(), PTy); 1214 SDValue JTI = DAG.getTargetJumpTable(JT->getIndex(), PTy); 1215 Table = DAG.getNode(ARMISD::WrapperJT, MVT::i32, JTI, UId); 1216 Index = DAG.getNode(ISD::MUL, PTy, Index, DAG.getConstant(4, PTy)); 1217 SDValue Addr = DAG.getNode(ISD::ADD, PTy, Index, Table); 1218 bool isPIC = getTargetMachine().getRelocationModel() == Reloc::PIC_; 1219 Addr = DAG.getLoad(isPIC ? (MVT)MVT::i32 : PTy, 1220 Chain, Addr, NULL, 0); 1221 Chain = Addr.getValue(1); 1222 if (isPIC) 1223 Addr = DAG.getNode(ISD::ADD, PTy, Addr, Table); 1224 return DAG.getNode(ARMISD::BR_JT, MVT::Other, Chain, Addr, JTI, UId); 1225} 1226 1227static SDValue LowerFP_TO_INT(SDValue Op, SelectionDAG &DAG) { 1228 unsigned Opc = 1229 Op.getOpcode() == ISD::FP_TO_SINT ? ARMISD::FTOSI : ARMISD::FTOUI; 1230 Op = DAG.getNode(Opc, MVT::f32, Op.getOperand(0)); 1231 return DAG.getNode(ISD::BIT_CONVERT, MVT::i32, Op); 1232} 1233 1234static SDValue LowerINT_TO_FP(SDValue Op, SelectionDAG &DAG) { 1235 MVT VT = Op.getValueType(); 1236 unsigned Opc = 1237 Op.getOpcode() == ISD::SINT_TO_FP ? ARMISD::SITOF : ARMISD::UITOF; 1238 1239 Op = DAG.getNode(ISD::BIT_CONVERT, MVT::f32, Op.getOperand(0)); 1240 return DAG.getNode(Opc, VT, Op); 1241} 1242 1243static SDValue LowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG) { 1244 // Implement fcopysign with a fabs and a conditional fneg. 1245 SDValue Tmp0 = Op.getOperand(0); 1246 SDValue Tmp1 = Op.getOperand(1); 1247 MVT VT = Op.getValueType(); 1248 MVT SrcVT = Tmp1.getValueType(); 1249 SDValue AbsVal = DAG.getNode(ISD::FABS, VT, Tmp0); 1250 SDValue Cmp = getVFPCmp(Tmp1, DAG.getConstantFP(0.0, SrcVT), DAG); 1251 SDValue ARMCC = DAG.getConstant(ARMCC::LT, MVT::i32); 1252 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32); 1253 return DAG.getNode(ARMISD::CNEG, VT, AbsVal, AbsVal, ARMCC, CCR, Cmp); 1254} 1255 1256SDValue 1257ARMTargetLowering::EmitTargetCodeForMemcpy(SelectionDAG &DAG, 1258 SDValue Chain, 1259 SDValue Dst, SDValue Src, 1260 SDValue Size, unsigned Align, 1261 bool AlwaysInline, 1262 const Value *DstSV, uint64_t DstSVOff, 1263 const Value *SrcSV, uint64_t SrcSVOff){ 1264 // Do repeated 4-byte loads and stores. To be improved. 1265 // This requires 4-byte alignment. 1266 if ((Align & 3) != 0) 1267 return SDValue(); 1268 // This requires the copy size to be a constant, preferrably 1269 // within a subtarget-specific limit. 1270 ConstantSDNode *ConstantSize = dyn_cast<ConstantSDNode>(Size); 1271 if (!ConstantSize) 1272 return SDValue(); 1273 uint64_t SizeVal = ConstantSize->getZExtValue(); 1274 if (!AlwaysInline && SizeVal > getSubtarget()->getMaxInlineSizeThreshold()) 1275 return SDValue(); 1276 1277 unsigned BytesLeft = SizeVal & 3; 1278 unsigned NumMemOps = SizeVal >> 2; 1279 unsigned EmittedNumMemOps = 0; 1280 MVT VT = MVT::i32; 1281 unsigned VTSize = 4; 1282 unsigned i = 0; 1283 const unsigned MAX_LOADS_IN_LDM = 6; 1284 SDValue TFOps[MAX_LOADS_IN_LDM]; 1285 SDValue Loads[MAX_LOADS_IN_LDM]; 1286 uint64_t SrcOff = 0, DstOff = 0; 1287 1288 // Emit up to MAX_LOADS_IN_LDM loads, then a TokenFactor barrier, then the 1289 // same number of stores. The loads and stores will get combined into 1290 // ldm/stm later on. 1291 while (EmittedNumMemOps < NumMemOps) { 1292 for (i = 0; 1293 i < MAX_LOADS_IN_LDM && EmittedNumMemOps + i < NumMemOps; ++i) { 1294 Loads[i] = DAG.getLoad(VT, Chain, 1295 DAG.getNode(ISD::ADD, MVT::i32, Src, 1296 DAG.getConstant(SrcOff, MVT::i32)), 1297 SrcSV, SrcSVOff + SrcOff); 1298 TFOps[i] = Loads[i].getValue(1); 1299 SrcOff += VTSize; 1300 } 1301 Chain = DAG.getNode(ISD::TokenFactor, MVT::Other, &TFOps[0], i); 1302 1303 for (i = 0; 1304 i < MAX_LOADS_IN_LDM && EmittedNumMemOps + i < NumMemOps; ++i) { 1305 TFOps[i] = DAG.getStore(Chain, Loads[i], 1306 DAG.getNode(ISD::ADD, MVT::i32, Dst, 1307 DAG.getConstant(DstOff, MVT::i32)), 1308 DstSV, DstSVOff + DstOff); 1309 DstOff += VTSize; 1310 } 1311 Chain = DAG.getNode(ISD::TokenFactor, MVT::Other, &TFOps[0], i); 1312 1313 EmittedNumMemOps += i; 1314 } 1315 1316 if (BytesLeft == 0) 1317 return Chain; 1318 1319 // Issue loads / stores for the trailing (1 - 3) bytes. 1320 unsigned BytesLeftSave = BytesLeft; 1321 i = 0; 1322 while (BytesLeft) { 1323 if (BytesLeft >= 2) { 1324 VT = MVT::i16; 1325 VTSize = 2; 1326 } else { 1327 VT = MVT::i8; 1328 VTSize = 1; 1329 } 1330 1331 Loads[i] = DAG.getLoad(VT, Chain, 1332 DAG.getNode(ISD::ADD, MVT::i32, Src, 1333 DAG.getConstant(SrcOff, MVT::i32)), 1334 SrcSV, SrcSVOff + SrcOff); 1335 TFOps[i] = Loads[i].getValue(1); 1336 ++i; 1337 SrcOff += VTSize; 1338 BytesLeft -= VTSize; 1339 } 1340 Chain = DAG.getNode(ISD::TokenFactor, MVT::Other, &TFOps[0], i); 1341 1342 i = 0; 1343 BytesLeft = BytesLeftSave; 1344 while (BytesLeft) { 1345 if (BytesLeft >= 2) { 1346 VT = MVT::i16; 1347 VTSize = 2; 1348 } else { 1349 VT = MVT::i8; 1350 VTSize = 1; 1351 } 1352 1353 TFOps[i] = DAG.getStore(Chain, Loads[i], 1354 DAG.getNode(ISD::ADD, MVT::i32, Dst, 1355 DAG.getConstant(DstOff, MVT::i32)), 1356 DstSV, DstSVOff + DstOff); 1357 ++i; 1358 DstOff += VTSize; 1359 BytesLeft -= VTSize; 1360 } 1361 return DAG.getNode(ISD::TokenFactor, MVT::Other, &TFOps[0], i); 1362} 1363 1364static SDNode *ExpandBIT_CONVERT(SDNode *N, SelectionDAG &DAG) { 1365 // Turn f64->i64 into FMRRD. 1366 assert(N->getValueType(0) == MVT::i64 && 1367 N->getOperand(0).getValueType() == MVT::f64); 1368 1369 SDValue Op = N->getOperand(0); 1370 SDValue Cvt = DAG.getNode(ARMISD::FMRRD, DAG.getVTList(MVT::i32, MVT::i32), 1371 &Op, 1); 1372 1373 // Merge the pieces into a single i64 value. 1374 return DAG.getNode(ISD::BUILD_PAIR, MVT::i64, Cvt, Cvt.getValue(1)).getNode(); 1375} 1376 1377static SDNode *ExpandSRx(SDNode *N, SelectionDAG &DAG, const ARMSubtarget *ST) { 1378 assert(N->getValueType(0) == MVT::i64 && 1379 (N->getOpcode() == ISD::SRL || N->getOpcode() == ISD::SRA) && 1380 "Unknown shift to lower!"); 1381 1382 // We only lower SRA, SRL of 1 here, all others use generic lowering. 1383 if (!isa<ConstantSDNode>(N->getOperand(1)) || 1384 cast<ConstantSDNode>(N->getOperand(1))->getZExtValue() != 1) 1385 return 0; 1386 1387 // If we are in thumb mode, we don't have RRX. 1388 if (ST->isThumb()) return 0; 1389 1390 // Okay, we have a 64-bit SRA or SRL of 1. Lower this to an RRX expr. 1391 SDValue Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32, N->getOperand(0), 1392 DAG.getConstant(0, MVT::i32)); 1393 SDValue Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32, N->getOperand(0), 1394 DAG.getConstant(1, MVT::i32)); 1395 1396 // First, build a SRA_FLAG/SRL_FLAG op, which shifts the top part by one and 1397 // captures the result into a carry flag. 1398 unsigned Opc = N->getOpcode() == ISD::SRL ? ARMISD::SRL_FLAG:ARMISD::SRA_FLAG; 1399 Hi = DAG.getNode(Opc, DAG.getVTList(MVT::i32, MVT::Flag), &Hi, 1); 1400 1401 // The low part is an ARMISD::RRX operand, which shifts the carry in. 1402 Lo = DAG.getNode(ARMISD::RRX, MVT::i32, Lo, Hi.getValue(1)); 1403 1404 // Merge the pieces into a single i64 value. 1405 return DAG.getNode(ISD::BUILD_PAIR, MVT::i64, Lo, Hi).getNode(); 1406} 1407 1408 1409SDValue ARMTargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) { 1410 switch (Op.getOpcode()) { 1411 default: assert(0 && "Don't know how to custom lower this!"); abort(); 1412 case ISD::ConstantPool: return LowerConstantPool(Op, DAG); 1413 case ISD::GlobalAddress: 1414 return Subtarget->isTargetDarwin() ? LowerGlobalAddressDarwin(Op, DAG) : 1415 LowerGlobalAddressELF(Op, DAG); 1416 case ISD::GlobalTLSAddress: return LowerGlobalTLSAddress(Op, DAG); 1417 case ISD::CALL: return LowerCALL(Op, DAG); 1418 case ISD::RET: return LowerRET(Op, DAG); 1419 case ISD::SELECT_CC: return LowerSELECT_CC(Op, DAG, Subtarget); 1420 case ISD::BR_CC: return LowerBR_CC(Op, DAG, Subtarget); 1421 case ISD::BR_JT: return LowerBR_JT(Op, DAG); 1422 case ISD::VASTART: return LowerVASTART(Op, DAG, VarArgsFrameIndex); 1423 case ISD::SINT_TO_FP: 1424 case ISD::UINT_TO_FP: return LowerINT_TO_FP(Op, DAG); 1425 case ISD::FP_TO_SINT: 1426 case ISD::FP_TO_UINT: return LowerFP_TO_INT(Op, DAG); 1427 case ISD::FCOPYSIGN: return LowerFCOPYSIGN(Op, DAG); 1428 case ISD::FORMAL_ARGUMENTS: return LowerFORMAL_ARGUMENTS(Op, DAG); 1429 case ISD::RETURNADDR: break; 1430 case ISD::FRAMEADDR: break; 1431 case ISD::GLOBAL_OFFSET_TABLE: return LowerGLOBAL_OFFSET_TABLE(Op, DAG); 1432 case ISD::INTRINSIC_WO_CHAIN: return LowerINTRINSIC_WO_CHAIN(Op, DAG); 1433 1434 1435 // FIXME: Remove these when LegalizeDAGTypes lands. 1436 case ISD::BIT_CONVERT: return SDValue(ExpandBIT_CONVERT(Op.getNode(), DAG), 0); 1437 case ISD::SRL: 1438 case ISD::SRA: return SDValue(ExpandSRx(Op.getNode(), DAG,Subtarget),0); 1439 } 1440 return SDValue(); 1441} 1442 1443 1444/// ReplaceNodeResults - Provide custom lowering hooks for nodes with illegal 1445/// result types. 1446SDNode *ARMTargetLowering::ReplaceNodeResults(SDNode *N, SelectionDAG &DAG) { 1447 switch (N->getOpcode()) { 1448 default: assert(0 && "Don't know how to custom expand this!"); abort(); 1449 case ISD::BIT_CONVERT: return ExpandBIT_CONVERT(N, DAG); 1450 case ISD::SRL: 1451 case ISD::SRA: return ExpandSRx(N, DAG, Subtarget); 1452 } 1453} 1454 1455 1456//===----------------------------------------------------------------------===// 1457// ARM Scheduler Hooks 1458//===----------------------------------------------------------------------===// 1459 1460MachineBasicBlock * 1461ARMTargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI, 1462 MachineBasicBlock *BB) { 1463 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); 1464 switch (MI->getOpcode()) { 1465 default: assert(false && "Unexpected instr type to insert"); 1466 case ARM::tMOVCCr: { 1467 // To "insert" a SELECT_CC instruction, we actually have to insert the 1468 // diamond control-flow pattern. The incoming instruction knows the 1469 // destination vreg to set, the condition code register to branch on, the 1470 // true/false values to select between, and a branch opcode to use. 1471 const BasicBlock *LLVM_BB = BB->getBasicBlock(); 1472 MachineFunction::iterator It = BB; 1473 ++It; 1474 1475 // thisMBB: 1476 // ... 1477 // TrueVal = ... 1478 // cmpTY ccX, r1, r2 1479 // bCC copy1MBB 1480 // fallthrough --> copy0MBB 1481 MachineBasicBlock *thisMBB = BB; 1482 MachineFunction *F = BB->getParent(); 1483 MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB); 1484 MachineBasicBlock *sinkMBB = F->CreateMachineBasicBlock(LLVM_BB); 1485 BuildMI(BB, TII->get(ARM::tBcc)).addMBB(sinkMBB) 1486 .addImm(MI->getOperand(3).getImm()).addReg(MI->getOperand(4).getReg()); 1487 F->insert(It, copy0MBB); 1488 F->insert(It, sinkMBB); 1489 // Update machine-CFG edges by first adding all successors of the current 1490 // block to the new block which will contain the Phi node for the select. 1491 for(MachineBasicBlock::succ_iterator i = BB->succ_begin(), 1492 e = BB->succ_end(); i != e; ++i) 1493 sinkMBB->addSuccessor(*i); 1494 // Next, remove all successors of the current block, and add the true 1495 // and fallthrough blocks as its successors. 1496 while(!BB->succ_empty()) 1497 BB->removeSuccessor(BB->succ_begin()); 1498 BB->addSuccessor(copy0MBB); 1499 BB->addSuccessor(sinkMBB); 1500 1501 // copy0MBB: 1502 // %FalseValue = ... 1503 // # fallthrough to sinkMBB 1504 BB = copy0MBB; 1505 1506 // Update machine-CFG edges 1507 BB->addSuccessor(sinkMBB); 1508 1509 // sinkMBB: 1510 // %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ] 1511 // ... 1512 BB = sinkMBB; 1513 BuildMI(BB, TII->get(ARM::PHI), MI->getOperand(0).getReg()) 1514 .addReg(MI->getOperand(1).getReg()).addMBB(copy0MBB) 1515 .addReg(MI->getOperand(2).getReg()).addMBB(thisMBB); 1516 1517 F->DeleteMachineInstr(MI); // The pseudo instruction is gone now. 1518 return BB; 1519 } 1520 } 1521} 1522 1523//===----------------------------------------------------------------------===// 1524// ARM Optimization Hooks 1525//===----------------------------------------------------------------------===// 1526 1527/// PerformFMRRDCombine - Target-specific dag combine xforms for ARMISD::FMRRD. 1528static SDValue PerformFMRRDCombine(SDNode *N, 1529 TargetLowering::DAGCombinerInfo &DCI) { 1530 // fmrrd(fmdrr x, y) -> x,y 1531 SDValue InDouble = N->getOperand(0); 1532 if (InDouble.getOpcode() == ARMISD::FMDRR) 1533 return DCI.CombineTo(N, InDouble.getOperand(0), InDouble.getOperand(1)); 1534 return SDValue(); 1535} 1536 1537SDValue ARMTargetLowering::PerformDAGCombine(SDNode *N, 1538 DAGCombinerInfo &DCI) const { 1539 switch (N->getOpcode()) { 1540 default: break; 1541 case ARMISD::FMRRD: return PerformFMRRDCombine(N, DCI); 1542 } 1543 1544 return SDValue(); 1545} 1546 1547 1548/// isLegalAddressImmediate - Return true if the integer value can be used 1549/// as the offset of the target addressing mode for load / store of the 1550/// given type. 1551static bool isLegalAddressImmediate(int64_t V, MVT VT, 1552 const ARMSubtarget *Subtarget) { 1553 if (V == 0) 1554 return true; 1555 1556 if (Subtarget->isThumb()) { 1557 if (V < 0) 1558 return false; 1559 1560 unsigned Scale = 1; 1561 switch (VT.getSimpleVT()) { 1562 default: return false; 1563 case MVT::i1: 1564 case MVT::i8: 1565 // Scale == 1; 1566 break; 1567 case MVT::i16: 1568 // Scale == 2; 1569 Scale = 2; 1570 break; 1571 case MVT::i32: 1572 // Scale == 4; 1573 Scale = 4; 1574 break; 1575 } 1576 1577 if ((V & (Scale - 1)) != 0) 1578 return false; 1579 V /= Scale; 1580 return V == (V & ((1LL << 5) - 1)); 1581 } 1582 1583 if (V < 0) 1584 V = - V; 1585 switch (VT.getSimpleVT()) { 1586 default: return false; 1587 case MVT::i1: 1588 case MVT::i8: 1589 case MVT::i32: 1590 // +- imm12 1591 return V == (V & ((1LL << 12) - 1)); 1592 case MVT::i16: 1593 // +- imm8 1594 return V == (V & ((1LL << 8) - 1)); 1595 case MVT::f32: 1596 case MVT::f64: 1597 if (!Subtarget->hasVFP2()) 1598 return false; 1599 if ((V & 3) != 0) 1600 return false; 1601 V >>= 2; 1602 return V == (V & ((1LL << 8) - 1)); 1603 } 1604} 1605 1606/// isLegalAddressingMode - Return true if the addressing mode represented 1607/// by AM is legal for this target, for a load/store of the specified type. 1608bool ARMTargetLowering::isLegalAddressingMode(const AddrMode &AM, 1609 const Type *Ty) const { 1610 if (!isLegalAddressImmediate(AM.BaseOffs, getValueType(Ty, true), Subtarget)) 1611 return false; 1612 1613 // Can never fold addr of global into load/store. 1614 if (AM.BaseGV) 1615 return false; 1616 1617 switch (AM.Scale) { 1618 case 0: // no scale reg, must be "r+i" or "r", or "i". 1619 break; 1620 case 1: 1621 if (Subtarget->isThumb()) 1622 return false; 1623 // FALL THROUGH. 1624 default: 1625 // ARM doesn't support any R+R*scale+imm addr modes. 1626 if (AM.BaseOffs) 1627 return false; 1628 1629 int Scale = AM.Scale; 1630 switch (getValueType(Ty).getSimpleVT()) { 1631 default: return false; 1632 case MVT::i1: 1633 case MVT::i8: 1634 case MVT::i32: 1635 case MVT::i64: 1636 // This assumes i64 is legalized to a pair of i32. If not (i.e. 1637 // ldrd / strd are used, then its address mode is same as i16. 1638 // r + r 1639 if (Scale < 0) Scale = -Scale; 1640 if (Scale == 1) 1641 return true; 1642 // r + r << imm 1643 return isPowerOf2_32(Scale & ~1); 1644 case MVT::i16: 1645 // r + r 1646 if (((unsigned)AM.HasBaseReg + Scale) <= 2) 1647 return true; 1648 return false; 1649 1650 case MVT::isVoid: 1651 // Note, we allow "void" uses (basically, uses that aren't loads or 1652 // stores), because arm allows folding a scale into many arithmetic 1653 // operations. This should be made more precise and revisited later. 1654 1655 // Allow r << imm, but the imm has to be a multiple of two. 1656 if (AM.Scale & 1) return false; 1657 return isPowerOf2_32(AM.Scale); 1658 } 1659 break; 1660 } 1661 return true; 1662} 1663 1664 1665static bool getIndexedAddressParts(SDNode *Ptr, MVT VT, 1666 bool isSEXTLoad, SDValue &Base, 1667 SDValue &Offset, bool &isInc, 1668 SelectionDAG &DAG) { 1669 if (Ptr->getOpcode() != ISD::ADD && Ptr->getOpcode() != ISD::SUB) 1670 return false; 1671 1672 if (VT == MVT::i16 || ((VT == MVT::i8 || VT == MVT::i1) && isSEXTLoad)) { 1673 // AddressingMode 3 1674 Base = Ptr->getOperand(0); 1675 if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(Ptr->getOperand(1))) { 1676 int RHSC = (int)RHS->getZExtValue(); 1677 if (RHSC < 0 && RHSC > -256) { 1678 isInc = false; 1679 Offset = DAG.getConstant(-RHSC, RHS->getValueType(0)); 1680 return true; 1681 } 1682 } 1683 isInc = (Ptr->getOpcode() == ISD::ADD); 1684 Offset = Ptr->getOperand(1); 1685 return true; 1686 } else if (VT == MVT::i32 || VT == MVT::i8 || VT == MVT::i1) { 1687 // AddressingMode 2 1688 if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(Ptr->getOperand(1))) { 1689 int RHSC = (int)RHS->getZExtValue(); 1690 if (RHSC < 0 && RHSC > -0x1000) { 1691 isInc = false; 1692 Offset = DAG.getConstant(-RHSC, RHS->getValueType(0)); 1693 Base = Ptr->getOperand(0); 1694 return true; 1695 } 1696 } 1697 1698 if (Ptr->getOpcode() == ISD::ADD) { 1699 isInc = true; 1700 ARM_AM::ShiftOpc ShOpcVal= ARM_AM::getShiftOpcForNode(Ptr->getOperand(0)); 1701 if (ShOpcVal != ARM_AM::no_shift) { 1702 Base = Ptr->getOperand(1); 1703 Offset = Ptr->getOperand(0); 1704 } else { 1705 Base = Ptr->getOperand(0); 1706 Offset = Ptr->getOperand(1); 1707 } 1708 return true; 1709 } 1710 1711 isInc = (Ptr->getOpcode() == ISD::ADD); 1712 Base = Ptr->getOperand(0); 1713 Offset = Ptr->getOperand(1); 1714 return true; 1715 } 1716 1717 // FIXME: Use FLDM / FSTM to emulate indexed FP load / store. 1718 return false; 1719} 1720 1721/// getPreIndexedAddressParts - returns true by value, base pointer and 1722/// offset pointer and addressing mode by reference if the node's address 1723/// can be legally represented as pre-indexed load / store address. 1724bool 1725ARMTargetLowering::getPreIndexedAddressParts(SDNode *N, SDValue &Base, 1726 SDValue &Offset, 1727 ISD::MemIndexedMode &AM, 1728 SelectionDAG &DAG) { 1729 if (Subtarget->isThumb()) 1730 return false; 1731 1732 MVT VT; 1733 SDValue Ptr; 1734 bool isSEXTLoad = false; 1735 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) { 1736 Ptr = LD->getBasePtr(); 1737 VT = LD->getMemoryVT(); 1738 isSEXTLoad = LD->getExtensionType() == ISD::SEXTLOAD; 1739 } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) { 1740 Ptr = ST->getBasePtr(); 1741 VT = ST->getMemoryVT(); 1742 } else 1743 return false; 1744 1745 bool isInc; 1746 bool isLegal = getIndexedAddressParts(Ptr.getNode(), VT, isSEXTLoad, Base, Offset, 1747 isInc, DAG); 1748 if (isLegal) { 1749 AM = isInc ? ISD::PRE_INC : ISD::PRE_DEC; 1750 return true; 1751 } 1752 return false; 1753} 1754 1755/// getPostIndexedAddressParts - returns true by value, base pointer and 1756/// offset pointer and addressing mode by reference if this node can be 1757/// combined with a load / store to form a post-indexed load / store. 1758bool ARMTargetLowering::getPostIndexedAddressParts(SDNode *N, SDNode *Op, 1759 SDValue &Base, 1760 SDValue &Offset, 1761 ISD::MemIndexedMode &AM, 1762 SelectionDAG &DAG) { 1763 if (Subtarget->isThumb()) 1764 return false; 1765 1766 MVT VT; 1767 SDValue Ptr; 1768 bool isSEXTLoad = false; 1769 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) { 1770 VT = LD->getMemoryVT(); 1771 isSEXTLoad = LD->getExtensionType() == ISD::SEXTLOAD; 1772 } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) { 1773 VT = ST->getMemoryVT(); 1774 } else 1775 return false; 1776 1777 bool isInc; 1778 bool isLegal = getIndexedAddressParts(Op, VT, isSEXTLoad, Base, Offset, 1779 isInc, DAG); 1780 if (isLegal) { 1781 AM = isInc ? ISD::POST_INC : ISD::POST_DEC; 1782 return true; 1783 } 1784 return false; 1785} 1786 1787void ARMTargetLowering::computeMaskedBitsForTargetNode(const SDValue Op, 1788 const APInt &Mask, 1789 APInt &KnownZero, 1790 APInt &KnownOne, 1791 const SelectionDAG &DAG, 1792 unsigned Depth) const { 1793 KnownZero = KnownOne = APInt(Mask.getBitWidth(), 0); 1794 switch (Op.getOpcode()) { 1795 default: break; 1796 case ARMISD::CMOV: { 1797 // Bits are known zero/one if known on the LHS and RHS. 1798 DAG.ComputeMaskedBits(Op.getOperand(0), Mask, KnownZero, KnownOne, Depth+1); 1799 if (KnownZero == 0 && KnownOne == 0) return; 1800 1801 APInt KnownZeroRHS, KnownOneRHS; 1802 DAG.ComputeMaskedBits(Op.getOperand(1), Mask, 1803 KnownZeroRHS, KnownOneRHS, Depth+1); 1804 KnownZero &= KnownZeroRHS; 1805 KnownOne &= KnownOneRHS; 1806 return; 1807 } 1808 } 1809} 1810 1811//===----------------------------------------------------------------------===// 1812// ARM Inline Assembly Support 1813//===----------------------------------------------------------------------===// 1814 1815/// getConstraintType - Given a constraint letter, return the type of 1816/// constraint it is for this target. 1817ARMTargetLowering::ConstraintType 1818ARMTargetLowering::getConstraintType(const std::string &Constraint) const { 1819 if (Constraint.size() == 1) { 1820 switch (Constraint[0]) { 1821 default: break; 1822 case 'l': return C_RegisterClass; 1823 case 'w': return C_RegisterClass; 1824 } 1825 } 1826 return TargetLowering::getConstraintType(Constraint); 1827} 1828 1829std::pair<unsigned, const TargetRegisterClass*> 1830ARMTargetLowering::getRegForInlineAsmConstraint(const std::string &Constraint, 1831 MVT VT) const { 1832 if (Constraint.size() == 1) { 1833 // GCC RS6000 Constraint Letters 1834 switch (Constraint[0]) { 1835 case 'l': 1836 // FIXME: in thumb mode, 'l' is only low-regs. 1837 // FALL THROUGH. 1838 case 'r': 1839 return std::make_pair(0U, ARM::GPRRegisterClass); 1840 case 'w': 1841 if (VT == MVT::f32) 1842 return std::make_pair(0U, ARM::SPRRegisterClass); 1843 if (VT == MVT::f64) 1844 return std::make_pair(0U, ARM::DPRRegisterClass); 1845 break; 1846 } 1847 } 1848 return TargetLowering::getRegForInlineAsmConstraint(Constraint, VT); 1849} 1850 1851std::vector<unsigned> ARMTargetLowering:: 1852getRegClassForInlineAsmConstraint(const std::string &Constraint, 1853 MVT VT) const { 1854 if (Constraint.size() != 1) 1855 return std::vector<unsigned>(); 1856 1857 switch (Constraint[0]) { // GCC ARM Constraint Letters 1858 default: break; 1859 case 'l': 1860 case 'r': 1861 return make_vector<unsigned>(ARM::R0, ARM::R1, ARM::R2, ARM::R3, 1862 ARM::R4, ARM::R5, ARM::R6, ARM::R7, 1863 ARM::R8, ARM::R9, ARM::R10, ARM::R11, 1864 ARM::R12, ARM::LR, 0); 1865 case 'w': 1866 if (VT == MVT::f32) 1867 return make_vector<unsigned>(ARM::S0, ARM::S1, ARM::S2, ARM::S3, 1868 ARM::S4, ARM::S5, ARM::S6, ARM::S7, 1869 ARM::S8, ARM::S9, ARM::S10, ARM::S11, 1870 ARM::S12,ARM::S13,ARM::S14,ARM::S15, 1871 ARM::S16,ARM::S17,ARM::S18,ARM::S19, 1872 ARM::S20,ARM::S21,ARM::S22,ARM::S23, 1873 ARM::S24,ARM::S25,ARM::S26,ARM::S27, 1874 ARM::S28,ARM::S29,ARM::S30,ARM::S31, 0); 1875 if (VT == MVT::f64) 1876 return make_vector<unsigned>(ARM::D0, ARM::D1, ARM::D2, ARM::D3, 1877 ARM::D4, ARM::D5, ARM::D6, ARM::D7, 1878 ARM::D8, ARM::D9, ARM::D10,ARM::D11, 1879 ARM::D12,ARM::D13,ARM::D14,ARM::D15, 0); 1880 break; 1881 } 1882 1883 return std::vector<unsigned>(); 1884} 1885