ARMISelLowering.cpp revision fb2e752e4175920d0531f2afc93a23d0cdf4db14 
1//===-- ARMISelLowering.cpp - ARM DAG Lowering Implementation -------------===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file defines the interfaces that ARM uses to lower LLVM code into a
11// selection DAG.
12//
13//===----------------------------------------------------------------------===//
14
15#include "ARM.h"
16#include "ARMAddressingModes.h"
17#include "ARMConstantPoolValue.h"
18#include "ARMISelLowering.h"
19#include "ARMMachineFunctionInfo.h"
20#include "ARMPerfectShuffle.h"
21#include "ARMRegisterInfo.h"
22#include "ARMSubtarget.h"
23#include "ARMTargetMachine.h"
24#include "ARMTargetObjectFile.h"
25#include "llvm/CallingConv.h"
26#include "llvm/Constants.h"
27#include "llvm/Function.h"
28#include "llvm/Instruction.h"
29#include "llvm/Intrinsics.h"
30#include "llvm/GlobalValue.h"
31#include "llvm/CodeGen/CallingConvLower.h"
32#include "llvm/CodeGen/MachineBasicBlock.h"
33#include "llvm/CodeGen/MachineFrameInfo.h"
34#include "llvm/CodeGen/MachineFunction.h"
35#include "llvm/CodeGen/MachineInstrBuilder.h"
36#include "llvm/CodeGen/MachineRegisterInfo.h"
37#include "llvm/CodeGen/PseudoSourceValue.h"
38#include "llvm/CodeGen/SelectionDAG.h"
39#include "llvm/Target/TargetOptions.h"
40#include "llvm/ADT/VectorExtras.h"
41#include "llvm/Support/ErrorHandling.h"
42#include "llvm/Support/MathExtras.h"
43#include <sstream>
44using namespace llvm;
45
46static bool CC_ARM_APCS_Custom_f64(unsigned &ValNo, EVT &ValVT, EVT &LocVT,
47                                   CCValAssign::LocInfo &LocInfo,
48                                   ISD::ArgFlagsTy &ArgFlags,
49                                   CCState &State);
50static bool CC_ARM_AAPCS_Custom_f64(unsigned &ValNo, EVT &ValVT, EVT &LocVT,
51                                    CCValAssign::LocInfo &LocInfo,
52                                    ISD::ArgFlagsTy &ArgFlags,
53                                    CCState &State);
54static bool RetCC_ARM_APCS_Custom_f64(unsigned &ValNo, EVT &ValVT, EVT &LocVT,
55                                      CCValAssign::LocInfo &LocInfo,
56                                      ISD::ArgFlagsTy &ArgFlags,
57                                      CCState &State);
58static bool RetCC_ARM_AAPCS_Custom_f64(unsigned &ValNo, EVT &ValVT, EVT &LocVT,
59                                       CCValAssign::LocInfo &LocInfo,
60                                       ISD::ArgFlagsTy &ArgFlags,
61                                       CCState &State);
62
63void ARMTargetLowering::addTypeForNEON(EVT VT, EVT PromotedLdStVT,
64                                       EVT PromotedBitwiseVT) {
65  if (VT != PromotedLdStVT) {
66    setOperationAction(ISD::LOAD, VT.getSimpleVT(), Promote);
67    AddPromotedToType (ISD::LOAD, VT.getSimpleVT(),
68                       PromotedLdStVT.getSimpleVT());
69
70    setOperationAction(ISD::STORE, VT.getSimpleVT(), Promote);
71    AddPromotedToType (ISD::STORE, VT.getSimpleVT(),
72                       PromotedLdStVT.getSimpleVT());
73  }
74
75  EVT ElemTy = VT.getVectorElementType();
76  if (ElemTy != MVT::i64 && ElemTy != MVT::f64)
77    setOperationAction(ISD::VSETCC, VT.getSimpleVT(), Custom);
78  if (ElemTy == MVT::i8 || ElemTy == MVT::i16)
79    setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT.getSimpleVT(), Custom);
80  if (ElemTy != MVT::i32) {
81    setOperationAction(ISD::SINT_TO_FP, VT.getSimpleVT(), Expand);
82    setOperationAction(ISD::UINT_TO_FP, VT.getSimpleVT(), Expand);
83    setOperationAction(ISD::FP_TO_SINT, VT.getSimpleVT(), Expand);
84    setOperationAction(ISD::FP_TO_UINT, VT.getSimpleVT(), Expand);
85  }
86  setOperationAction(ISD::BUILD_VECTOR, VT.getSimpleVT(), Custom);
87  setOperationAction(ISD::VECTOR_SHUFFLE, VT.getSimpleVT(), Custom);
88  setOperationAction(ISD::CONCAT_VECTORS, VT.getSimpleVT(), Custom);
89  setOperationAction(ISD::EXTRACT_SUBVECTOR, VT.getSimpleVT(), Expand);
90  if (VT.isInteger()) {
91    setOperationAction(ISD::SHL, VT.getSimpleVT(), Custom);
92    setOperationAction(ISD::SRA, VT.getSimpleVT(), Custom);
93    setOperationAction(ISD::SRL, VT.getSimpleVT(), Custom);
94  }
95
96  // Promote all bit-wise operations.
97  if (VT.isInteger() && VT != PromotedBitwiseVT) {
98    setOperationAction(ISD::AND, VT.getSimpleVT(), Promote);
99    AddPromotedToType (ISD::AND, VT.getSimpleVT(),
100                       PromotedBitwiseVT.getSimpleVT());
101    setOperationAction(ISD::OR,  VT.getSimpleVT(), Promote);
102    AddPromotedToType (ISD::OR,  VT.getSimpleVT(),
103                       PromotedBitwiseVT.getSimpleVT());
104    setOperationAction(ISD::XOR, VT.getSimpleVT(), Promote);
105    AddPromotedToType (ISD::XOR, VT.getSimpleVT(),
106                       PromotedBitwiseVT.getSimpleVT());
107  }
108
109  // Neon does not support vector divide/remainder operations.
110  setOperationAction(ISD::SDIV, VT.getSimpleVT(), Expand);
111  setOperationAction(ISD::UDIV, VT.getSimpleVT(), Expand);
112  setOperationAction(ISD::FDIV, VT.getSimpleVT(), Expand);
113  setOperationAction(ISD::SREM, VT.getSimpleVT(), Expand);
114  setOperationAction(ISD::UREM, VT.getSimpleVT(), Expand);
115  setOperationAction(ISD::FREM, VT.getSimpleVT(), Expand);
116}
117
118void ARMTargetLowering::addDRTypeForNEON(EVT VT) {
119  addRegisterClass(VT, ARM::DPRRegisterClass);
120  addTypeForNEON(VT, MVT::f64, MVT::v2i32);
121}
122
123void ARMTargetLowering::addQRTypeForNEON(EVT VT) {
124  addRegisterClass(VT, ARM::QPRRegisterClass);
125  addTypeForNEON(VT, MVT::v2f64, MVT::v4i32);
126}
127
128static TargetLoweringObjectFile *createTLOF(TargetMachine &TM) {
129  if (TM.getSubtarget<ARMSubtarget>().isTargetDarwin())
130    return new TargetLoweringObjectFileMachO();
131  return new ARMElfTargetObjectFile();
132}
133
134ARMTargetLowering::ARMTargetLowering(TargetMachine &TM)
135    : TargetLowering(TM, createTLOF(TM)), ARMPCLabelIndex(0) {
136  Subtarget = &TM.getSubtarget<ARMSubtarget>();
137
138  if (Subtarget->isTargetDarwin()) {
139    // Uses VFP for Thumb libfuncs if available.
140    if (Subtarget->isThumb() && Subtarget->hasVFP2()) {
141      // Single-precision floating-point arithmetic.
142      setLibcallName(RTLIB::ADD_F32, "__addsf3vfp");
143      setLibcallName(RTLIB::SUB_F32, "__subsf3vfp");
144      setLibcallName(RTLIB::MUL_F32, "__mulsf3vfp");
145      setLibcallName(RTLIB::DIV_F32, "__divsf3vfp");
146
147      // Double-precision floating-point arithmetic.
148      setLibcallName(RTLIB::ADD_F64, "__adddf3vfp");
149      setLibcallName(RTLIB::SUB_F64, "__subdf3vfp");
150      setLibcallName(RTLIB::MUL_F64, "__muldf3vfp");
151      setLibcallName(RTLIB::DIV_F64, "__divdf3vfp");
152
153      // Single-precision comparisons.
154      setLibcallName(RTLIB::OEQ_F32, "__eqsf2vfp");
155      setLibcallName(RTLIB::UNE_F32, "__nesf2vfp");
156      setLibcallName(RTLIB::OLT_F32, "__ltsf2vfp");
157      setLibcallName(RTLIB::OLE_F32, "__lesf2vfp");
158      setLibcallName(RTLIB::OGE_F32, "__gesf2vfp");
159      setLibcallName(RTLIB::OGT_F32, "__gtsf2vfp");
160      setLibcallName(RTLIB::UO_F32,  "__unordsf2vfp");
161      setLibcallName(RTLIB::O_F32,   "__unordsf2vfp");
162
163      setCmpLibcallCC(RTLIB::OEQ_F32, ISD::SETNE);
164      setCmpLibcallCC(RTLIB::UNE_F32, ISD::SETNE);
165      setCmpLibcallCC(RTLIB::OLT_F32, ISD::SETNE);
166      setCmpLibcallCC(RTLIB::OLE_F32, ISD::SETNE);
167      setCmpLibcallCC(RTLIB::OGE_F32, ISD::SETNE);
168      setCmpLibcallCC(RTLIB::OGT_F32, ISD::SETNE);
169      setCmpLibcallCC(RTLIB::UO_F32,  ISD::SETNE);
170      setCmpLibcallCC(RTLIB::O_F32,   ISD::SETEQ);
171
172      // Double-precision comparisons.
173      setLibcallName(RTLIB::OEQ_F64, "__eqdf2vfp");
174      setLibcallName(RTLIB::UNE_F64, "__nedf2vfp");
175      setLibcallName(RTLIB::OLT_F64, "__ltdf2vfp");
176      setLibcallName(RTLIB::OLE_F64, "__ledf2vfp");
177      setLibcallName(RTLIB::OGE_F64, "__gedf2vfp");
178      setLibcallName(RTLIB::OGT_F64, "__gtdf2vfp");
179      setLibcallName(RTLIB::UO_F64,  "__unorddf2vfp");
180      setLibcallName(RTLIB::O_F64,   "__unorddf2vfp");
181
182      setCmpLibcallCC(RTLIB::OEQ_F64, ISD::SETNE);
183      setCmpLibcallCC(RTLIB::UNE_F64, ISD::SETNE);
184      setCmpLibcallCC(RTLIB::OLT_F64, ISD::SETNE);
185      setCmpLibcallCC(RTLIB::OLE_F64, ISD::SETNE);
186      setCmpLibcallCC(RTLIB::OGE_F64, ISD::SETNE);
187      setCmpLibcallCC(RTLIB::OGT_F64, ISD::SETNE);
188      setCmpLibcallCC(RTLIB::UO_F64,  ISD::SETNE);
189      setCmpLibcallCC(RTLIB::O_F64,   ISD::SETEQ);
190
191      // Floating-point to integer conversions.
192      // i64 conversions are done via library routines even when generating VFP
193      // instructions, so use the same ones.
194      setLibcallName(RTLIB::FPTOSINT_F64_I32, "__fixdfsivfp");
195      setLibcallName(RTLIB::FPTOUINT_F64_I32, "__fixunsdfsivfp");
196      setLibcallName(RTLIB::FPTOSINT_F32_I32, "__fixsfsivfp");
197      setLibcallName(RTLIB::FPTOUINT_F32_I32, "__fixunssfsivfp");
198
199      // Conversions between floating types.
200      setLibcallName(RTLIB::FPROUND_F64_F32, "__truncdfsf2vfp");
201      setLibcallName(RTLIB::FPEXT_F32_F64,   "__extendsfdf2vfp");
202
203      // Integer to floating-point conversions.
204      // i64 conversions are done via library routines even when generating VFP
205      // instructions, so use the same ones.
206      // FIXME: There appears to be some naming inconsistency in ARM libgcc:
207      // e.g., __floatunsidf vs. __floatunssidfvfp.
208      setLibcallName(RTLIB::SINTTOFP_I32_F64, "__floatsidfvfp");
209      setLibcallName(RTLIB::UINTTOFP_I32_F64, "__floatunssidfvfp");
210      setLibcallName(RTLIB::SINTTOFP_I32_F32, "__floatsisfvfp");
211      setLibcallName(RTLIB::UINTTOFP_I32_F32, "__floatunssisfvfp");
212    }
213  }
214
215  // These libcalls are not available in 32-bit.
216  setLibcallName(RTLIB::SHL_I128, 0);
217  setLibcallName(RTLIB::SRL_I128, 0);
218  setLibcallName(RTLIB::SRA_I128, 0);
219
220  // Libcalls should use the AAPCS base standard ABI, even if hard float
221  // is in effect, as per the ARM RTABI specification, section 4.1.2.
222  if (Subtarget->isAAPCS_ABI()) {
223    for (int i = 0; i < RTLIB::UNKNOWN_LIBCALL; ++i) {
224      setLibcallCallingConv(static_cast<RTLIB::Libcall>(i),
225                            CallingConv::ARM_AAPCS);
226    }
227  }
228
229  if (Subtarget->isThumb1Only())
230    addRegisterClass(MVT::i32, ARM::tGPRRegisterClass);
231  else
232    addRegisterClass(MVT::i32, ARM::GPRRegisterClass);
233  if (!UseSoftFloat && Subtarget->hasVFP2() && !Subtarget->isThumb1Only()) {
234    addRegisterClass(MVT::f32, ARM::SPRRegisterClass);
235    addRegisterClass(MVT::f64, ARM::DPRRegisterClass);
236
237    setTruncStoreAction(MVT::f64, MVT::f32, Expand);
238  }
239
240  if (Subtarget->hasNEON()) {
241    addDRTypeForNEON(MVT::v2f32);
242    addDRTypeForNEON(MVT::v8i8);
243    addDRTypeForNEON(MVT::v4i16);
244    addDRTypeForNEON(MVT::v2i32);
245    addDRTypeForNEON(MVT::v1i64);
246
247    addQRTypeForNEON(MVT::v4f32);
248    addQRTypeForNEON(MVT::v2f64);
249    addQRTypeForNEON(MVT::v16i8);
250    addQRTypeForNEON(MVT::v8i16);
251    addQRTypeForNEON(MVT::v4i32);
252    addQRTypeForNEON(MVT::v2i64);
253
254    // v2f64 is legal so that QR subregs can be extracted as f64 elements, but
255    // neither Neon nor VFP support any arithmetic operations on it.
256    setOperationAction(ISD::FADD, MVT::v2f64, Expand);
257    setOperationAction(ISD::FSUB, MVT::v2f64, Expand);
258    setOperationAction(ISD::FMUL, MVT::v2f64, Expand);
259    setOperationAction(ISD::FDIV, MVT::v2f64, Expand);
260    setOperationAction(ISD::FREM, MVT::v2f64, Expand);
261    setOperationAction(ISD::FCOPYSIGN, MVT::v2f64, Expand);
262    setOperationAction(ISD::VSETCC, MVT::v2f64, Expand);
263    setOperationAction(ISD::FNEG, MVT::v2f64, Expand);
264    setOperationAction(ISD::FABS, MVT::v2f64, Expand);
265    setOperationAction(ISD::FSQRT, MVT::v2f64, Expand);
266    setOperationAction(ISD::FSIN, MVT::v2f64, Expand);
267    setOperationAction(ISD::FCOS, MVT::v2f64, Expand);
268    setOperationAction(ISD::FPOWI, MVT::v2f64, Expand);
269    setOperationAction(ISD::FPOW, MVT::v2f64, Expand);
270    setOperationAction(ISD::FLOG, MVT::v2f64, Expand);
271    setOperationAction(ISD::FLOG2, MVT::v2f64, Expand);
272    setOperationAction(ISD::FLOG10, MVT::v2f64, Expand);
273    setOperationAction(ISD::FEXP, MVT::v2f64, Expand);
274    setOperationAction(ISD::FEXP2, MVT::v2f64, Expand);
275    setOperationAction(ISD::FCEIL, MVT::v2f64, Expand);
276    setOperationAction(ISD::FTRUNC, MVT::v2f64, Expand);
277    setOperationAction(ISD::FRINT, MVT::v2f64, Expand);
278    setOperationAction(ISD::FNEARBYINT, MVT::v2f64, Expand);
279    setOperationAction(ISD::FFLOOR, MVT::v2f64, Expand);
280
281    // Neon does not support some operations on v1i64 and v2i64 types.
282    setOperationAction(ISD::MUL, MVT::v1i64, Expand);
283    setOperationAction(ISD::MUL, MVT::v2i64, Expand);
284    setOperationAction(ISD::VSETCC, MVT::v1i64, Expand);
285    setOperationAction(ISD::VSETCC, MVT::v2i64, Expand);
286
287    setTargetDAGCombine(ISD::INTRINSIC_WO_CHAIN);
288    setTargetDAGCombine(ISD::SHL);
289    setTargetDAGCombine(ISD::SRL);
290    setTargetDAGCombine(ISD::SRA);
291    setTargetDAGCombine(ISD::SIGN_EXTEND);
292    setTargetDAGCombine(ISD::ZERO_EXTEND);
293    setTargetDAGCombine(ISD::ANY_EXTEND);
294  }
295
296  computeRegisterProperties();
297
298  // ARM does not have f32 extending load.
299  setLoadExtAction(ISD::EXTLOAD, MVT::f32, Expand);
300
301  // ARM does not have i1 sign extending load.
302  setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote);
303
304  // ARM supports all 4 flavors of integer indexed load / store.
305  if (!Subtarget->isThumb1Only()) {
306    for (unsigned im = (unsigned)ISD::PRE_INC;
307         im != (unsigned)ISD::LAST_INDEXED_MODE; ++im) {
308      setIndexedLoadAction(im,  MVT::i1,  Legal);
309      setIndexedLoadAction(im,  MVT::i8,  Legal);
310      setIndexedLoadAction(im,  MVT::i16, Legal);
311      setIndexedLoadAction(im,  MVT::i32, Legal);
312      setIndexedStoreAction(im, MVT::i1,  Legal);
313      setIndexedStoreAction(im, MVT::i8,  Legal);
314      setIndexedStoreAction(im, MVT::i16, Legal);
315      setIndexedStoreAction(im, MVT::i32, Legal);
316    }
317  }
318
319  // i64 operation support.
320  if (Subtarget->isThumb1Only()) {
321    setOperationAction(ISD::MUL,     MVT::i64, Expand);
322    setOperationAction(ISD::MULHU,   MVT::i32, Expand);
323    setOperationAction(ISD::MULHS,   MVT::i32, Expand);
324    setOperationAction(ISD::UMUL_LOHI, MVT::i32, Expand);
325    setOperationAction(ISD::SMUL_LOHI, MVT::i32, Expand);
326  } else {
327    setOperationAction(ISD::MUL,     MVT::i64, Expand);
328    setOperationAction(ISD::MULHU,   MVT::i32, Expand);
329    if (!Subtarget->hasV6Ops())
330      setOperationAction(ISD::MULHS, MVT::i32, Expand);
331  }
332  setOperationAction(ISD::SHL_PARTS, MVT::i32, Expand);
333  setOperationAction(ISD::SRA_PARTS, MVT::i32, Expand);
334  setOperationAction(ISD::SRL_PARTS, MVT::i32, Expand);
335  setOperationAction(ISD::SRL,       MVT::i64, Custom);
336  setOperationAction(ISD::SRA,       MVT::i64, Custom);
337
338  // ARM does not have ROTL.
339  setOperationAction(ISD::ROTL,  MVT::i32, Expand);
340  setOperationAction(ISD::CTTZ,  MVT::i32, Expand);
341  setOperationAction(ISD::CTPOP, MVT::i32, Expand);
342  if (!Subtarget->hasV5TOps() || Subtarget->isThumb1Only())
343    setOperationAction(ISD::CTLZ, MVT::i32, Expand);
344
345  // Only ARMv6 has BSWAP.
346  if (!Subtarget->hasV6Ops())
347    setOperationAction(ISD::BSWAP, MVT::i32, Expand);
348
349  // These are expanded into libcalls.
350  setOperationAction(ISD::SDIV,  MVT::i32, Expand);
351  setOperationAction(ISD::UDIV,  MVT::i32, Expand);
352  setOperationAction(ISD::SREM,  MVT::i32, Expand);
353  setOperationAction(ISD::UREM,  MVT::i32, Expand);
354  setOperationAction(ISD::SDIVREM, MVT::i32, Expand);
355  setOperationAction(ISD::UDIVREM, MVT::i32, Expand);
356
357  // Support label based line numbers.
358  setOperationAction(ISD::DBG_STOPPOINT, MVT::Other, Expand);
359  setOperationAction(ISD::DEBUG_LOC, MVT::Other, Expand);
360
361  setOperationAction(ISD::GlobalAddress, MVT::i32,   Custom);
362  setOperationAction(ISD::ConstantPool,  MVT::i32,   Custom);
363  setOperationAction(ISD::GLOBAL_OFFSET_TABLE, MVT::i32, Custom);
364  setOperationAction(ISD::GlobalTLSAddress, MVT::i32, Custom);
365
366  // Use the default implementation.
367  setOperationAction(ISD::VASTART,            MVT::Other, Custom);
368  setOperationAction(ISD::VAARG,              MVT::Other, Expand);
369  setOperationAction(ISD::VACOPY,             MVT::Other, Expand);
370  setOperationAction(ISD::VAEND,              MVT::Other, Expand);
371  setOperationAction(ISD::STACKSAVE,          MVT::Other, Expand);
372  setOperationAction(ISD::STACKRESTORE,       MVT::Other, Expand);
373  setOperationAction(ISD::EHSELECTION,        MVT::i32,   Expand);
374  // FIXME: Shouldn't need this, since no register is used, but the legalizer
375  // doesn't yet know how to not do that for SjLj.
376  setExceptionSelectorRegister(ARM::R0);
377  if (Subtarget->isThumb())
378    setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32, Custom);
379  else
380    setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32, Expand);
381  setOperationAction(ISD::MEMBARRIER,         MVT::Other, Expand);
382
383  if (!Subtarget->hasV6Ops() && !Subtarget->isThumb2()) {
384    setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16, Expand);
385    setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8,  Expand);
386  }
387  setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand);
388
389  if (!UseSoftFloat && Subtarget->hasVFP2() && !Subtarget->isThumb1Only())
390    // Turn f64->i64 into FMRRD, i64 -> f64 to FMDRR iff target supports vfp2.
391    setOperationAction(ISD::BIT_CONVERT, MVT::i64, Custom);
392
393  // We want to custom lower some of our intrinsics.
394  setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom);
395  setOperationAction(ISD::INTRINSIC_W_CHAIN, MVT::Other, Custom);
396  setOperationAction(ISD::INTRINSIC_VOID, MVT::Other, Custom);
397
398  setOperationAction(ISD::SETCC,     MVT::i32, Expand);
399  setOperationAction(ISD::SETCC,     MVT::f32, Expand);
400  setOperationAction(ISD::SETCC,     MVT::f64, Expand);
401  setOperationAction(ISD::SELECT,    MVT::i32, Expand);
402  setOperationAction(ISD::SELECT,    MVT::f32, Expand);
403  setOperationAction(ISD::SELECT,    MVT::f64, Expand);
404  setOperationAction(ISD::SELECT_CC, MVT::i32, Custom);
405  setOperationAction(ISD::SELECT_CC, MVT::f32, Custom);
406  setOperationAction(ISD::SELECT_CC, MVT::f64, Custom);
407
408  setOperationAction(ISD::BRCOND,    MVT::Other, Expand);
409  setOperationAction(ISD::BR_CC,     MVT::i32,   Custom);
410  setOperationAction(ISD::BR_CC,     MVT::f32,   Custom);
411  setOperationAction(ISD::BR_CC,     MVT::f64,   Custom);
412  setOperationAction(ISD::BR_JT,     MVT::Other, Custom);
413
414  // We don't support sin/cos/fmod/copysign/pow
415  setOperationAction(ISD::FSIN,      MVT::f64, Expand);
416  setOperationAction(ISD::FSIN,      MVT::f32, Expand);
417  setOperationAction(ISD::FCOS,      MVT::f32, Expand);
418  setOperationAction(ISD::FCOS,      MVT::f64, Expand);
419  setOperationAction(ISD::FREM,      MVT::f64, Expand);
420  setOperationAction(ISD::FREM,      MVT::f32, Expand);
421  if (!UseSoftFloat && Subtarget->hasVFP2() && !Subtarget->isThumb1Only()) {
422    setOperationAction(ISD::FCOPYSIGN, MVT::f64, Custom);
423    setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom);
424  }
425  setOperationAction(ISD::FPOW,      MVT::f64, Expand);
426  setOperationAction(ISD::FPOW,      MVT::f32, Expand);
427
428  // int <-> fp are custom expanded into bit_convert + ARMISD ops.
429  if (!UseSoftFloat && Subtarget->hasVFP2() && !Subtarget->isThumb1Only()) {
430    setOperationAction(ISD::SINT_TO_FP, MVT::i32, Custom);
431    setOperationAction(ISD::UINT_TO_FP, MVT::i32, Custom);
432    setOperationAction(ISD::FP_TO_UINT, MVT::i32, Custom);
433    setOperationAction(ISD::FP_TO_SINT, MVT::i32, Custom);
434  }
435
436  // We have target-specific dag combine patterns for the following nodes:
437  // ARMISD::FMRRD  - No need to call setTargetDAGCombine
438  setTargetDAGCombine(ISD::ADD);
439  setTargetDAGCombine(ISD::SUB);
440
441  setStackPointerRegisterToSaveRestore(ARM::SP);
442  setSchedulingPreference(SchedulingForRegPressure);
443
444  // FIXME: If-converter should use instruction latency to determine
445  // profitability rather than relying on fixed limits.
446  if (Subtarget->getCPUString() == "generic") {
447    // Generic (and overly aggressive) if-conversion limits.
448    setIfCvtBlockSizeLimit(10);
449    setIfCvtDupBlockSizeLimit(2);
450  } else if (Subtarget->hasV6Ops()) {
451    setIfCvtBlockSizeLimit(2);
452    setIfCvtDupBlockSizeLimit(1);
453  } else {
454    setIfCvtBlockSizeLimit(3);
455    setIfCvtDupBlockSizeLimit(2);
456  }
457
458  maxStoresPerMemcpy = 1;   //// temporary - rewrite interface to use type
459  // Do not enable CodePlacementOpt for now: it currently runs after the
460  // ARMConstantIslandPass and messes up branch relaxation and placement
461  // of constant islands.
462  // benefitFromCodePlacementOpt = true;
463}
464
465const char *ARMTargetLowering::getTargetNodeName(unsigned Opcode) const {
466  switch (Opcode) {
467  default: return 0;
468  case ARMISD::Wrapper:       return "ARMISD::Wrapper";
469  case ARMISD::WrapperJT:     return "ARMISD::WrapperJT";
470  case ARMISD::CALL:          return "ARMISD::CALL";
471  case ARMISD::CALL_PRED:     return "ARMISD::CALL_PRED";
472  case ARMISD::CALL_NOLINK:   return "ARMISD::CALL_NOLINK";
473  case ARMISD::tCALL:         return "ARMISD::tCALL";
474  case ARMISD::BRCOND:        return "ARMISD::BRCOND";
475  case ARMISD::BR_JT:         return "ARMISD::BR_JT";
476  case ARMISD::BR2_JT:        return "ARMISD::BR2_JT";
477  case ARMISD::RET_FLAG:      return "ARMISD::RET_FLAG";
478  case ARMISD::PIC_ADD:       return "ARMISD::PIC_ADD";
479  case ARMISD::CMP:           return "ARMISD::CMP";
480  case ARMISD::CMPZ:          return "ARMISD::CMPZ";
481  case ARMISD::CMPFP:         return "ARMISD::CMPFP";
482  case ARMISD::CMPFPw0:       return "ARMISD::CMPFPw0";
483  case ARMISD::FMSTAT:        return "ARMISD::FMSTAT";
484  case ARMISD::CMOV:          return "ARMISD::CMOV";
485  case ARMISD::CNEG:          return "ARMISD::CNEG";
486
487  case ARMISD::FTOSI:         return "ARMISD::FTOSI";
488  case ARMISD::FTOUI:         return "ARMISD::FTOUI";
489  case ARMISD::SITOF:         return "ARMISD::SITOF";
490  case ARMISD::UITOF:         return "ARMISD::UITOF";
491
492  case ARMISD::SRL_FLAG:      return "ARMISD::SRL_FLAG";
493  case ARMISD::SRA_FLAG:      return "ARMISD::SRA_FLAG";
494  case ARMISD::RRX:           return "ARMISD::RRX";
495
496  case ARMISD::FMRRD:         return "ARMISD::FMRRD";
497  case ARMISD::FMDRR:         return "ARMISD::FMDRR";
498
499  case ARMISD::THREAD_POINTER:return "ARMISD::THREAD_POINTER";
500
501  case ARMISD::DYN_ALLOC:     return "ARMISD::DYN_ALLOC";
502
503  case ARMISD::VCEQ:          return "ARMISD::VCEQ";
504  case ARMISD::VCGE:          return "ARMISD::VCGE";
505  case ARMISD::VCGEU:         return "ARMISD::VCGEU";
506  case ARMISD::VCGT:          return "ARMISD::VCGT";
507  case ARMISD::VCGTU:         return "ARMISD::VCGTU";
508  case ARMISD::VTST:          return "ARMISD::VTST";
509
510  case ARMISD::VSHL:          return "ARMISD::VSHL";
511  case ARMISD::VSHRs:         return "ARMISD::VSHRs";
512  case ARMISD::VSHRu:         return "ARMISD::VSHRu";
513  case ARMISD::VSHLLs:        return "ARMISD::VSHLLs";
514  case ARMISD::VSHLLu:        return "ARMISD::VSHLLu";
515  case ARMISD::VSHLLi:        return "ARMISD::VSHLLi";
516  case ARMISD::VSHRN:         return "ARMISD::VSHRN";
517  case ARMISD::VRSHRs:        return "ARMISD::VRSHRs";
518  case ARMISD::VRSHRu:        return "ARMISD::VRSHRu";
519  case ARMISD::VRSHRN:        return "ARMISD::VRSHRN";
520  case ARMISD::VQSHLs:        return "ARMISD::VQSHLs";
521  case ARMISD::VQSHLu:        return "ARMISD::VQSHLu";
522  case ARMISD::VQSHLsu:       return "ARMISD::VQSHLsu";
523  case ARMISD::VQSHRNs:       return "ARMISD::VQSHRNs";
524  case ARMISD::VQSHRNu:       return "ARMISD::VQSHRNu";
525  case ARMISD::VQSHRNsu:      return "ARMISD::VQSHRNsu";
526  case ARMISD::VQRSHRNs:      return "ARMISD::VQRSHRNs";
527  case ARMISD::VQRSHRNu:      return "ARMISD::VQRSHRNu";
528  case ARMISD::VQRSHRNsu:     return "ARMISD::VQRSHRNsu";
529  case ARMISD::VGETLANEu:     return "ARMISD::VGETLANEu";
530  case ARMISD::VGETLANEs:     return "ARMISD::VGETLANEs";
531  case ARMISD::VDUP:          return "ARMISD::VDUP";
532  case ARMISD::VDUPLANE:      return "ARMISD::VDUPLANE";
533  case ARMISD::VEXT:          return "ARMISD::VEXT";
534  case ARMISD::VREV64:        return "ARMISD::VREV64";
535  case ARMISD::VREV32:        return "ARMISD::VREV32";
536  case ARMISD::VREV16:        return "ARMISD::VREV16";
537  case ARMISD::VZIP:          return "ARMISD::VZIP";
538  case ARMISD::VUZP:          return "ARMISD::VUZP";
539  case ARMISD::VTRN:          return "ARMISD::VTRN";
540  }
541}
542
543/// getFunctionAlignment - Return the Log2 alignment of this function.
544unsigned ARMTargetLowering::getFunctionAlignment(const Function *F) const {
545  return getTargetMachine().getSubtarget<ARMSubtarget>().isThumb() ? 1 : 2;
546}
547
548//===----------------------------------------------------------------------===//
549// Lowering Code
550//===----------------------------------------------------------------------===//
551
552/// IntCCToARMCC - Convert a DAG integer condition code to an ARM CC
553static ARMCC::CondCodes IntCCToARMCC(ISD::CondCode CC) {
554  switch (CC) {
555  default: llvm_unreachable("Unknown condition code!");
556  case ISD::SETNE:  return ARMCC::NE;
557  case ISD::SETEQ:  return ARMCC::EQ;
558  case ISD::SETGT:  return ARMCC::GT;
559  case ISD::SETGE:  return ARMCC::GE;
560  case ISD::SETLT:  return ARMCC::LT;
561  case ISD::SETLE:  return ARMCC::LE;
562  case ISD::SETUGT: return ARMCC::HI;
563  case ISD::SETUGE: return ARMCC::HS;
564  case ISD::SETULT: return ARMCC::LO;
565  case ISD::SETULE: return ARMCC::LS;
566  }
567}
568
569/// FPCCToARMCC - Convert a DAG fp condition code to an ARM CC.
570static void FPCCToARMCC(ISD::CondCode CC, ARMCC::CondCodes &CondCode,
571                        ARMCC::CondCodes &CondCode2) {
572  CondCode2 = ARMCC::AL;
573  switch (CC) {
574  default: llvm_unreachable("Unknown FP condition!");
575  case ISD::SETEQ:
576  case ISD::SETOEQ: CondCode = ARMCC::EQ; break;
577  case ISD::SETGT:
578  case ISD::SETOGT: CondCode = ARMCC::GT; break;
579  case ISD::SETGE:
580  case ISD::SETOGE: CondCode = ARMCC::GE; break;
581  case ISD::SETOLT: CondCode = ARMCC::MI; break;
582  case ISD::SETOLE: CondCode = ARMCC::LS; break;
583  case ISD::SETONE: CondCode = ARMCC::MI; CondCode2 = ARMCC::GT; break;
584  case ISD::SETO:   CondCode = ARMCC::VC; break;
585  case ISD::SETUO:  CondCode = ARMCC::VS; break;
586  case ISD::SETUEQ: CondCode = ARMCC::EQ; CondCode2 = ARMCC::VS; break;
587  case ISD::SETUGT: CondCode = ARMCC::HI; break;
588  case ISD::SETUGE: CondCode = ARMCC::PL; break;
589  case ISD::SETLT:
590  case ISD::SETULT: CondCode = ARMCC::LT; break;
591  case ISD::SETLE:
592  case ISD::SETULE: CondCode = ARMCC::LE; break;
593  case ISD::SETNE:
594  case ISD::SETUNE: CondCode = ARMCC::NE; break;
595  }
596}
597
598//===----------------------------------------------------------------------===//
599//                      Calling Convention Implementation
600//===----------------------------------------------------------------------===//
601
602#include "ARMGenCallingConv.inc"
603
604// APCS f64 is in register pairs, possibly split to stack
605static bool f64AssignAPCS(unsigned &ValNo, EVT &ValVT, EVT &LocVT,
606                          CCValAssign::LocInfo &LocInfo,
607                          CCState &State, bool CanFail) {
608  static const unsigned RegList[] = { ARM::R0, ARM::R1, ARM::R2, ARM::R3 };
609
610  // Try to get the first register.
611  if (unsigned Reg = State.AllocateReg(RegList, 4))
612    State.addLoc(CCValAssign::getCustomReg(ValNo, ValVT, Reg, LocVT, LocInfo));
613  else {
614    // For the 2nd half of a v2f64, do not fail.
615    if (CanFail)
616      return false;
617
618    // Put the whole thing on the stack.
619    State.addLoc(CCValAssign::getCustomMem(ValNo, ValVT,
620                                           State.AllocateStack(8, 4),
621                                           LocVT, LocInfo));
622    return true;
623  }
624
625  // Try to get the second register.
626  if (unsigned Reg = State.AllocateReg(RegList, 4))
627    State.addLoc(CCValAssign::getCustomReg(ValNo, ValVT, Reg, LocVT, LocInfo));
628  else
629    State.addLoc(CCValAssign::getCustomMem(ValNo, ValVT,
630                                           State.AllocateStack(4, 4),
631                                           LocVT, LocInfo));
632  return true;
633}
634
635static bool CC_ARM_APCS_Custom_f64(unsigned &ValNo, EVT &ValVT, EVT &LocVT,
636                                   CCValAssign::LocInfo &LocInfo,
637                                   ISD::ArgFlagsTy &ArgFlags,
638                                   CCState &State) {
639  if (!f64AssignAPCS(ValNo, ValVT, LocVT, LocInfo, State, true))
640    return false;
641  if (LocVT == MVT::v2f64 &&
642      !f64AssignAPCS(ValNo, ValVT, LocVT, LocInfo, State, false))
643    return false;
644  return true;  // we handled it
645}
646
647// AAPCS f64 is in aligned register pairs
648static bool f64AssignAAPCS(unsigned &ValNo, EVT &ValVT, EVT &LocVT,
649                           CCValAssign::LocInfo &LocInfo,
650                           CCState &State, bool CanFail) {
651  static const unsigned HiRegList[] = { ARM::R0, ARM::R2 };
652  static const unsigned LoRegList[] = { ARM::R1, ARM::R3 };
653
654  unsigned Reg = State.AllocateReg(HiRegList, LoRegList, 2);
655  if (Reg == 0) {
656    // For the 2nd half of a v2f64, do not just fail.
657    if (CanFail)
658      return false;
659
660    // Put the whole thing on the stack.
661    State.addLoc(CCValAssign::getCustomMem(ValNo, ValVT,
662                                           State.AllocateStack(8, 8),
663                                           LocVT, LocInfo));
664    return true;
665  }
666
667  unsigned i;
668  for (i = 0; i < 2; ++i)
669    if (HiRegList[i] == Reg)
670      break;
671
672  State.addLoc(CCValAssign::getCustomReg(ValNo, ValVT, Reg, LocVT, LocInfo));
673  State.addLoc(CCValAssign::getCustomReg(ValNo, ValVT, LoRegList[i],
674                                         LocVT, LocInfo));
675  return true;
676}
677
678static bool CC_ARM_AAPCS_Custom_f64(unsigned &ValNo, EVT &ValVT, EVT &LocVT,
679                                    CCValAssign::LocInfo &LocInfo,
680                                    ISD::ArgFlagsTy &ArgFlags,
681                                    CCState &State) {
682  if (!f64AssignAAPCS(ValNo, ValVT, LocVT, LocInfo, State, true))
683    return false;
684  if (LocVT == MVT::v2f64 &&
685      !f64AssignAAPCS(ValNo, ValVT, LocVT, LocInfo, State, false))
686    return false;
687  return true;  // we handled it
688}
689
690static bool f64RetAssign(unsigned &ValNo, EVT &ValVT, EVT &LocVT,
691                         CCValAssign::LocInfo &LocInfo, CCState &State) {
692  static const unsigned HiRegList[] = { ARM::R0, ARM::R2 };
693  static const unsigned LoRegList[] = { ARM::R1, ARM::R3 };
694
695  unsigned Reg = State.AllocateReg(HiRegList, LoRegList, 2);
696  if (Reg == 0)
697    return false; // we didn't handle it
698
699  unsigned i;
700  for (i = 0; i < 2; ++i)
701    if (HiRegList[i] == Reg)
702      break;
703
704  State.addLoc(CCValAssign::getCustomReg(ValNo, ValVT, Reg, LocVT, LocInfo));
705  State.addLoc(CCValAssign::getCustomReg(ValNo, ValVT, LoRegList[i],
706                                         LocVT, LocInfo));
707  return true;
708}
709
710static bool RetCC_ARM_APCS_Custom_f64(unsigned &ValNo, EVT &ValVT, EVT &LocVT,
711                                      CCValAssign::LocInfo &LocInfo,
712                                      ISD::ArgFlagsTy &ArgFlags,
713                                      CCState &State) {
714  if (!f64RetAssign(ValNo, ValVT, LocVT, LocInfo, State))
715    return false;
716  if (LocVT == MVT::v2f64 && !f64RetAssign(ValNo, ValVT, LocVT, LocInfo, State))
717    return false;
718  return true;  // we handled it
719}
720
721static bool RetCC_ARM_AAPCS_Custom_f64(unsigned &ValNo, EVT &ValVT, EVT &LocVT,
722                                       CCValAssign::LocInfo &LocInfo,
723                                       ISD::ArgFlagsTy &ArgFlags,
724                                       CCState &State) {
725  return RetCC_ARM_APCS_Custom_f64(ValNo, ValVT, LocVT, LocInfo, ArgFlags,
726                                   State);
727}
728
729/// CCAssignFnForNode - Selects the correct CCAssignFn for a the
730/// given CallingConvention value.
731CCAssignFn *ARMTargetLowering::CCAssignFnForNode(CallingConv::ID CC,
732                                                 bool Return,
733                                                 bool isVarArg) const {
734  switch (CC) {
735  default:
736    llvm_unreachable("Unsupported calling convention");
737  case CallingConv::C:
738  case CallingConv::Fast:
739    // Use target triple & subtarget features to do actual dispatch.
740    if (Subtarget->isAAPCS_ABI()) {
741      if (Subtarget->hasVFP2() &&
742          FloatABIType == FloatABI::Hard && !isVarArg)
743        return (Return ? RetCC_ARM_AAPCS_VFP: CC_ARM_AAPCS_VFP);
744      else
745        return (Return ? RetCC_ARM_AAPCS: CC_ARM_AAPCS);
746    } else
747        return (Return ? RetCC_ARM_APCS: CC_ARM_APCS);
748  case CallingConv::ARM_AAPCS_VFP:
749    return (Return ? RetCC_ARM_AAPCS_VFP: CC_ARM_AAPCS_VFP);
750  case CallingConv::ARM_AAPCS:
751    return (Return ? RetCC_ARM_AAPCS: CC_ARM_AAPCS);
752  case CallingConv::ARM_APCS:
753    return (Return ? RetCC_ARM_APCS: CC_ARM_APCS);
754  }
755}
756
757/// LowerCallResult - Lower the result values of a call into the
758/// appropriate copies out of appropriate physical registers.
759SDValue
760ARMTargetLowering::LowerCallResult(SDValue Chain, SDValue InFlag,
761                                   CallingConv::ID CallConv, bool isVarArg,
762                                   const SmallVectorImpl<ISD::InputArg> &Ins,
763                                   DebugLoc dl, SelectionDAG &DAG,
764                                   SmallVectorImpl<SDValue> &InVals) {
765
766  // Assign locations to each value returned by this call.
767  SmallVector<CCValAssign, 16> RVLocs;
768  CCState CCInfo(CallConv, isVarArg, getTargetMachine(),
769                 RVLocs, *DAG.getContext());
770  CCInfo.AnalyzeCallResult(Ins,
771                           CCAssignFnForNode(CallConv, /* Return*/ true,
772                                             isVarArg));
773
774  // Copy all of the result registers out of their specified physreg.
775  for (unsigned i = 0; i != RVLocs.size(); ++i) {
776    CCValAssign VA = RVLocs[i];
777
778    SDValue Val;
779    if (VA.needsCustom()) {
780      // Handle f64 or half of a v2f64.
781      SDValue Lo = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), MVT::i32,
782                                      InFlag);
783      Chain = Lo.getValue(1);
784      InFlag = Lo.getValue(2);
785      VA = RVLocs[++i]; // skip ahead to next loc
786      SDValue Hi = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), MVT::i32,
787                                      InFlag);
788      Chain = Hi.getValue(1);
789      InFlag = Hi.getValue(2);
790      Val = DAG.getNode(ARMISD::FMDRR, dl, MVT::f64, Lo, Hi);
791
792      if (VA.getLocVT() == MVT::v2f64) {
793        SDValue Vec = DAG.getNode(ISD::UNDEF, dl, MVT::v2f64);
794        Vec = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v2f64, Vec, Val,
795                          DAG.getConstant(0, MVT::i32));
796
797        VA = RVLocs[++i]; // skip ahead to next loc
798        Lo = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), MVT::i32, InFlag);
799        Chain = Lo.getValue(1);
800        InFlag = Lo.getValue(2);
801        VA = RVLocs[++i]; // skip ahead to next loc
802        Hi = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), MVT::i32, InFlag);
803        Chain = Hi.getValue(1);
804        InFlag = Hi.getValue(2);
805        Val = DAG.getNode(ARMISD::FMDRR, dl, MVT::f64, Lo, Hi);
806        Val = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v2f64, Vec, Val,
807                          DAG.getConstant(1, MVT::i32));
808      }
809    } else {
810      Val = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), VA.getLocVT(),
811                               InFlag);
812      Chain = Val.getValue(1);
813      InFlag = Val.getValue(2);
814    }
815
816    switch (VA.getLocInfo()) {
817    default: llvm_unreachable("Unknown loc info!");
818    case CCValAssign::Full: break;
819    case CCValAssign::BCvt:
820      Val = DAG.getNode(ISD::BIT_CONVERT, dl, VA.getValVT(), Val);
821      break;
822    }
823
824    InVals.push_back(Val);
825  }
826
827  return Chain;
828}
829
830/// CreateCopyOfByValArgument - Make a copy of an aggregate at address specified
831/// by "Src" to address "Dst" of size "Size".  Alignment information is
832/// specified by the specific parameter attribute.  The copy will be passed as
833/// a byval function parameter.
834/// Sometimes what we are copying is the end of a larger object, the part that
835/// does not fit in registers.
836static SDValue
837CreateCopyOfByValArgument(SDValue Src, SDValue Dst, SDValue Chain,
838                          ISD::ArgFlagsTy Flags, SelectionDAG &DAG,
839                          DebugLoc dl) {
840  SDValue SizeNode = DAG.getConstant(Flags.getByValSize(), MVT::i32);
841  return DAG.getMemcpy(Chain, dl, Dst, Src, SizeNode, Flags.getByValAlign(),
842                       /*AlwaysInline=*/false, NULL, 0, NULL, 0);
843}
844
845/// LowerMemOpCallTo - Store the argument to the stack.
846SDValue
847ARMTargetLowering::LowerMemOpCallTo(SDValue Chain,
848                                    SDValue StackPtr, SDValue Arg,
849                                    DebugLoc dl, SelectionDAG &DAG,
850                                    const CCValAssign &VA,
851                                    ISD::ArgFlagsTy Flags) {
852  unsigned LocMemOffset = VA.getLocMemOffset();
853  SDValue PtrOff = DAG.getIntPtrConstant(LocMemOffset);
854  PtrOff = DAG.getNode(ISD::ADD, dl, getPointerTy(), StackPtr, PtrOff);
855  if (Flags.isByVal()) {
856    return CreateCopyOfByValArgument(Arg, PtrOff, Chain, Flags, DAG, dl);
857  }
858  return DAG.getStore(Chain, dl, Arg, PtrOff,
859                      PseudoSourceValue::getStack(), LocMemOffset);
860}
861
862void ARMTargetLowering::PassF64ArgInRegs(DebugLoc dl, SelectionDAG &DAG,
863                                         SDValue Chain, SDValue &Arg,
864                                         RegsToPassVector &RegsToPass,
865                                         CCValAssign &VA, CCValAssign &NextVA,
866                                         SDValue &StackPtr,
867                                         SmallVector<SDValue, 8> &MemOpChains,
868                                         ISD::ArgFlagsTy Flags) {
869
870  SDValue fmrrd = DAG.getNode(ARMISD::FMRRD, dl,
871                              DAG.getVTList(MVT::i32, MVT::i32), Arg);
872  RegsToPass.push_back(std::make_pair(VA.getLocReg(), fmrrd));
873
874  if (NextVA.isRegLoc())
875    RegsToPass.push_back(std::make_pair(NextVA.getLocReg(), fmrrd.getValue(1)));
876  else {
877    assert(NextVA.isMemLoc());
878    if (StackPtr.getNode() == 0)
879      StackPtr = DAG.getCopyFromReg(Chain, dl, ARM::SP, getPointerTy());
880
881    MemOpChains.push_back(LowerMemOpCallTo(Chain, StackPtr, fmrrd.getValue(1),
882                                           dl, DAG, NextVA,
883                                           Flags));
884  }
885}
886
887/// LowerCall - Lowering a call into a callseq_start <-
888/// ARMISD:CALL <- callseq_end chain. Also add input and output parameter
889/// nodes.
890SDValue
891ARMTargetLowering::LowerCall(SDValue Chain, SDValue Callee,
892                             CallingConv::ID CallConv, bool isVarArg,
893                             bool isTailCall,
894                             const SmallVectorImpl<ISD::OutputArg> &Outs,
895                             const SmallVectorImpl<ISD::InputArg> &Ins,
896                             DebugLoc dl, SelectionDAG &DAG,
897                             SmallVectorImpl<SDValue> &InVals) {
898
899  // Analyze operands of the call, assigning locations to each operand.
900  SmallVector<CCValAssign, 16> ArgLocs;
901  CCState CCInfo(CallConv, isVarArg, getTargetMachine(), ArgLocs,
902                 *DAG.getContext());
903  CCInfo.AnalyzeCallOperands(Outs,
904                             CCAssignFnForNode(CallConv, /* Return*/ false,
905                                               isVarArg));
906
907  // Get a count of how many bytes are to be pushed on the stack.
908  unsigned NumBytes = CCInfo.getNextStackOffset();
909
910  // Adjust the stack pointer for the new arguments...
911  // These operations are automatically eliminated by the prolog/epilog pass
912  Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(NumBytes, true));
913
914  SDValue StackPtr = DAG.getRegister(ARM::SP, MVT::i32);
915
916  RegsToPassVector RegsToPass;
917  SmallVector<SDValue, 8> MemOpChains;
918
919  // Walk the register/memloc assignments, inserting copies/loads.  In the case
920  // of tail call optimization, arguments are handled later.
921  for (unsigned i = 0, realArgIdx = 0, e = ArgLocs.size();
922       i != e;
923       ++i, ++realArgIdx) {
924    CCValAssign &VA = ArgLocs[i];
925    SDValue Arg = Outs[realArgIdx].Val;
926    ISD::ArgFlagsTy Flags = Outs[realArgIdx].Flags;
927
928    // Promote the value if needed.
929    switch (VA.getLocInfo()) {
930    default: llvm_unreachable("Unknown loc info!");
931    case CCValAssign::Full: break;
932    case CCValAssign::SExt:
933      Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), Arg);
934      break;
935    case CCValAssign::ZExt:
936      Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, VA.getLocVT(), Arg);
937      break;
938    case CCValAssign::AExt:
939      Arg = DAG.getNode(ISD::ANY_EXTEND, dl, VA.getLocVT(), Arg);
940      break;
941    case CCValAssign::BCvt:
942      Arg = DAG.getNode(ISD::BIT_CONVERT, dl, VA.getLocVT(), Arg);
943      break;
944    }
945
946    // f64 and v2f64 might be passed in i32 pairs and must be split into pieces
947    if (VA.needsCustom()) {
948      if (VA.getLocVT() == MVT::v2f64) {
949        SDValue Op0 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, Arg,
950                                  DAG.getConstant(0, MVT::i32));
951        SDValue Op1 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, Arg,
952                                  DAG.getConstant(1, MVT::i32));
953
954        PassF64ArgInRegs(dl, DAG, Chain, Op0, RegsToPass,
955                         VA, ArgLocs[++i], StackPtr, MemOpChains, Flags);
956
957        VA = ArgLocs[++i]; // skip ahead to next loc
958        if (VA.isRegLoc()) {
959          PassF64ArgInRegs(dl, DAG, Chain, Op1, RegsToPass,
960                           VA, ArgLocs[++i], StackPtr, MemOpChains, Flags);
961        } else {
962          assert(VA.isMemLoc());
963          if (StackPtr.getNode() == 0)
964            StackPtr = DAG.getCopyFromReg(Chain, dl, ARM::SP, getPointerTy());
965
966          MemOpChains.push_back(LowerMemOpCallTo(Chain, StackPtr, Op1,
967                                                 dl, DAG, VA, Flags));
968        }
969      } else {
970        PassF64ArgInRegs(dl, DAG, Chain, Arg, RegsToPass, VA, ArgLocs[++i],
971                         StackPtr, MemOpChains, Flags);
972      }
973    } else if (VA.isRegLoc()) {
974      RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
975    } else {
976      assert(VA.isMemLoc());
977      if (StackPtr.getNode() == 0)
978        StackPtr = DAG.getCopyFromReg(Chain, dl, ARM::SP, getPointerTy());
979
980      MemOpChains.push_back(LowerMemOpCallTo(Chain, StackPtr, Arg,
981                                             dl, DAG, VA, Flags));
982    }
983  }
984
985  if (!MemOpChains.empty())
986    Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
987                        &MemOpChains[0], MemOpChains.size());
988
989  // Build a sequence of copy-to-reg nodes chained together with token chain
990  // and flag operands which copy the outgoing args into the appropriate regs.
991  SDValue InFlag;
992  for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
993    Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
994                             RegsToPass[i].second, InFlag);
995    InFlag = Chain.getValue(1);
996  }
997
998  // If the callee is a GlobalAddress/ExternalSymbol node (quite common, every
999  // direct call is) turn it into a TargetGlobalAddress/TargetExternalSymbol
1000  // node so that legalize doesn't hack it.
1001  bool isDirect = false;
1002  bool isARMFunc = false;
1003  bool isLocalARMFunc = false;
1004  if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) {
1005    GlobalValue *GV = G->getGlobal();
1006    isDirect = true;
1007    bool isExt = GV->isDeclaration() || GV->isWeakForLinker();
1008    bool isStub = (isExt && Subtarget->isTargetDarwin()) &&
1009                   getTargetMachine().getRelocationModel() != Reloc::Static;
1010    isARMFunc = !Subtarget->isThumb() || isStub;
1011    // ARM call to a local ARM function is predicable.
1012    isLocalARMFunc = !Subtarget->isThumb() && !isExt;
1013    // tBX takes a register source operand.
1014    if (isARMFunc && Subtarget->isThumb1Only() && !Subtarget->hasV5TOps()) {
1015      ARMConstantPoolValue *CPV = new ARMConstantPoolValue(GV,
1016                                                           ARMPCLabelIndex,
1017                                                           ARMCP::CPValue, 4);
1018      SDValue CPAddr = DAG.getTargetConstantPool(CPV, getPointerTy(), 4);
1019      CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr);
1020      Callee = DAG.getLoad(getPointerTy(), dl,
1021                           DAG.getEntryNode(), CPAddr, NULL, 0);
1022      SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex++, MVT::i32);
1023      Callee = DAG.getNode(ARMISD::PIC_ADD, dl,
1024                           getPointerTy(), Callee, PICLabel);
1025   } else
1026      Callee = DAG.getTargetGlobalAddress(GV, getPointerTy());
1027  } else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee)) {
1028    isDirect = true;
1029    bool isStub = Subtarget->isTargetDarwin() &&
1030                  getTargetMachine().getRelocationModel() != Reloc::Static;
1031    isARMFunc = !Subtarget->isThumb() || isStub;
1032    // tBX takes a register source operand.
1033    const char *Sym = S->getSymbol();
1034    if (isARMFunc && Subtarget->isThumb1Only() && !Subtarget->hasV5TOps()) {
1035      ARMConstantPoolValue *CPV = new ARMConstantPoolValue(*DAG.getContext(),
1036                                                       Sym, ARMPCLabelIndex, 4);
1037      SDValue CPAddr = DAG.getTargetConstantPool(CPV, getPointerTy(), 4);
1038      CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr);
1039      Callee = DAG.getLoad(getPointerTy(), dl,
1040                           DAG.getEntryNode(), CPAddr, NULL, 0);
1041      SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex++, MVT::i32);
1042      Callee = DAG.getNode(ARMISD::PIC_ADD, dl,
1043                           getPointerTy(), Callee, PICLabel);
1044    } else
1045      Callee = DAG.getTargetExternalSymbol(Sym, getPointerTy());
1046  }
1047
1048  // FIXME: handle tail calls differently.
1049  unsigned CallOpc;
1050  if (Subtarget->isThumb()) {
1051    if ((!isDirect || isARMFunc) && !Subtarget->hasV5TOps())
1052      CallOpc = ARMISD::CALL_NOLINK;
1053    else
1054      CallOpc = isARMFunc ? ARMISD::CALL : ARMISD::tCALL;
1055  } else {
1056    CallOpc = (isDirect || Subtarget->hasV5TOps())
1057      ? (isLocalARMFunc ? ARMISD::CALL_PRED : ARMISD::CALL)
1058      : ARMISD::CALL_NOLINK;
1059  }
1060  if (CallOpc == ARMISD::CALL_NOLINK && !Subtarget->isThumb1Only()) {
1061    // implicit def LR - LR mustn't be allocated as GRP:$dst of CALL_NOLINK
1062    Chain = DAG.getCopyToReg(Chain, dl, ARM::LR, DAG.getUNDEF(MVT::i32),InFlag);
1063    InFlag = Chain.getValue(1);
1064  }
1065
1066  std::vector<SDValue> Ops;
1067  Ops.push_back(Chain);
1068  Ops.push_back(Callee);
1069
1070  // Add argument registers to the end of the list so that they are known live
1071  // into the call.
1072  for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i)
1073    Ops.push_back(DAG.getRegister(RegsToPass[i].first,
1074                                  RegsToPass[i].second.getValueType()));
1075
1076  if (InFlag.getNode())
1077    Ops.push_back(InFlag);
1078  // Returns a chain and a flag for retval copy to use.
1079  Chain = DAG.getNode(CallOpc, dl, DAG.getVTList(MVT::Other, MVT::Flag),
1080                      &Ops[0], Ops.size());
1081  InFlag = Chain.getValue(1);
1082
1083  Chain = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(NumBytes, true),
1084                             DAG.getIntPtrConstant(0, true), InFlag);
1085  if (!Ins.empty())
1086    InFlag = Chain.getValue(1);
1087
1088  // Handle result values, copying them out of physregs into vregs that we
1089  // return.
1090  return LowerCallResult(Chain, InFlag, CallConv, isVarArg, Ins,
1091                         dl, DAG, InVals);
1092}
1093
1094SDValue
1095ARMTargetLowering::LowerReturn(SDValue Chain,
1096                               CallingConv::ID CallConv, bool isVarArg,
1097                               const SmallVectorImpl<ISD::OutputArg> &Outs,
1098                               DebugLoc dl, SelectionDAG &DAG) {
1099
1100  // CCValAssign - represent the assignment of the return value to a location.
1101  SmallVector<CCValAssign, 16> RVLocs;
1102
1103  // CCState - Info about the registers and stack slots.
1104  CCState CCInfo(CallConv, isVarArg, getTargetMachine(), RVLocs,
1105                 *DAG.getContext());
1106
1107  // Analyze outgoing return values.
1108  CCInfo.AnalyzeReturn(Outs, CCAssignFnForNode(CallConv, /* Return */ true,
1109                                               isVarArg));
1110
1111  // If this is the first return lowered for this function, add
1112  // the regs to the liveout set for the function.
1113  if (DAG.getMachineFunction().getRegInfo().liveout_empty()) {
1114    for (unsigned i = 0; i != RVLocs.size(); ++i)
1115      if (RVLocs[i].isRegLoc())
1116        DAG.getMachineFunction().getRegInfo().addLiveOut(RVLocs[i].getLocReg());
1117  }
1118
1119  SDValue Flag;
1120
1121  // Copy the result values into the output registers.
1122  for (unsigned i = 0, realRVLocIdx = 0;
1123       i != RVLocs.size();
1124       ++i, ++realRVLocIdx) {
1125    CCValAssign &VA = RVLocs[i];
1126    assert(VA.isRegLoc() && "Can only return in registers!");
1127
1128    SDValue Arg = Outs[realRVLocIdx].Val;
1129
1130    switch (VA.getLocInfo()) {
1131    default: llvm_unreachable("Unknown loc info!");
1132    case CCValAssign::Full: break;
1133    case CCValAssign::BCvt:
1134      Arg = DAG.getNode(ISD::BIT_CONVERT, dl, VA.getLocVT(), Arg);
1135      break;
1136    }
1137
1138    if (VA.needsCustom()) {
1139      if (VA.getLocVT() == MVT::v2f64) {
1140        // Extract the first half and return it in two registers.
1141        SDValue Half = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, Arg,
1142                                   DAG.getConstant(0, MVT::i32));
1143        SDValue HalfGPRs = DAG.getNode(ARMISD::FMRRD, dl,
1144                                       DAG.getVTList(MVT::i32, MVT::i32), Half);
1145
1146        Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), HalfGPRs, Flag);
1147        Flag = Chain.getValue(1);
1148        VA = RVLocs[++i]; // skip ahead to next loc
1149        Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(),
1150                                 HalfGPRs.getValue(1), Flag);
1151        Flag = Chain.getValue(1);
1152        VA = RVLocs[++i]; // skip ahead to next loc
1153
1154        // Extract the 2nd half and fall through to handle it as an f64 value.
1155        Arg = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, Arg,
1156                          DAG.getConstant(1, MVT::i32));
1157      }
1158      // Legalize ret f64 -> ret 2 x i32.  We always have fmrrd if f64 is
1159      // available.
1160      SDValue fmrrd = DAG.getNode(ARMISD::FMRRD, dl,
1161                                  DAG.getVTList(MVT::i32, MVT::i32), &Arg, 1);
1162      Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), fmrrd, Flag);
1163      Flag = Chain.getValue(1);
1164      VA = RVLocs[++i]; // skip ahead to next loc
1165      Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), fmrrd.getValue(1),
1166                               Flag);
1167    } else
1168      Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), Arg, Flag);
1169
1170    // Guarantee that all emitted copies are
1171    // stuck together, avoiding something bad.
1172    Flag = Chain.getValue(1);
1173  }
1174
1175  SDValue result;
1176  if (Flag.getNode())
1177    result = DAG.getNode(ARMISD::RET_FLAG, dl, MVT::Other, Chain, Flag);
1178  else // Return Void
1179    result = DAG.getNode(ARMISD::RET_FLAG, dl, MVT::Other, Chain);
1180
1181  return result;
1182}
1183
1184// ConstantPool, JumpTable, GlobalAddress, and ExternalSymbol are lowered as
1185// their target counterpart wrapped in the ARMISD::Wrapper node. Suppose N is
1186// one of the above mentioned nodes. It has to be wrapped because otherwise
1187// Select(N) returns N. So the raw TargetGlobalAddress nodes, etc. can only
1188// be used to form addressing mode. These wrapped nodes will be selected
1189// into MOVi.
1190static SDValue LowerConstantPool(SDValue Op, SelectionDAG &DAG) {
1191  EVT PtrVT = Op.getValueType();
1192  // FIXME there is no actual debug info here
1193  DebugLoc dl = Op.getDebugLoc();
1194  ConstantPoolSDNode *CP = cast<ConstantPoolSDNode>(Op);
1195  SDValue Res;
1196  if (CP->isMachineConstantPoolEntry())
1197    Res = DAG.getTargetConstantPool(CP->getMachineCPVal(), PtrVT,
1198                                    CP->getAlignment());
1199  else
1200    Res = DAG.getTargetConstantPool(CP->getConstVal(), PtrVT,
1201                                    CP->getAlignment());
1202  return DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, Res);
1203}
1204
1205// Lower ISD::GlobalTLSAddress using the "general dynamic" model
1206SDValue
1207ARMTargetLowering::LowerToTLSGeneralDynamicModel(GlobalAddressSDNode *GA,
1208                                                 SelectionDAG &DAG) {
1209  DebugLoc dl = GA->getDebugLoc();
1210  EVT PtrVT = getPointerTy();
1211  unsigned char PCAdj = Subtarget->isThumb() ? 4 : 8;
1212  ARMConstantPoolValue *CPV =
1213    new ARMConstantPoolValue(GA->getGlobal(), ARMPCLabelIndex,
1214                             ARMCP::CPValue, PCAdj, "tlsgd", true);
1215  SDValue Argument = DAG.getTargetConstantPool(CPV, PtrVT, 4);
1216  Argument = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, Argument);
1217  Argument = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), Argument, NULL, 0);
1218  SDValue Chain = Argument.getValue(1);
1219
1220  SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex++, MVT::i32);
1221  Argument = DAG.getNode(ARMISD::PIC_ADD, dl, PtrVT, Argument, PICLabel);
1222
1223  // call __tls_get_addr.
1224  ArgListTy Args;
1225  ArgListEntry Entry;
1226  Entry.Node = Argument;
1227  Entry.Ty = (const Type *) Type::getInt32Ty(*DAG.getContext());
1228  Args.push_back(Entry);
1229  // FIXME: is there useful debug info available here?
1230  std::pair<SDValue, SDValue> CallResult =
1231    LowerCallTo(Chain, (const Type *) Type::getInt32Ty(*DAG.getContext()),
1232                false, false, false, false,
1233                0, CallingConv::C, false, /*isReturnValueUsed=*/true,
1234                DAG.getExternalSymbol("__tls_get_addr", PtrVT), Args, DAG, dl);
1235  return CallResult.first;
1236}
1237
1238// Lower ISD::GlobalTLSAddress using the "initial exec" or
1239// "local exec" model.
1240SDValue
1241ARMTargetLowering::LowerToTLSExecModels(GlobalAddressSDNode *GA,
1242                                        SelectionDAG &DAG) {
1243  GlobalValue *GV = GA->getGlobal();
1244  DebugLoc dl = GA->getDebugLoc();
1245  SDValue Offset;
1246  SDValue Chain = DAG.getEntryNode();
1247  EVT PtrVT = getPointerTy();
1248  // Get the Thread Pointer
1249  SDValue ThreadPointer = DAG.getNode(ARMISD::THREAD_POINTER, dl, PtrVT);
1250
1251  if (GV->isDeclaration()) {
1252    // initial exec model
1253    unsigned char PCAdj = Subtarget->isThumb() ? 4 : 8;
1254    ARMConstantPoolValue *CPV =
1255      new ARMConstantPoolValue(GA->getGlobal(), ARMPCLabelIndex,
1256                               ARMCP::CPValue, PCAdj, "gottpoff", true);
1257    Offset = DAG.getTargetConstantPool(CPV, PtrVT, 4);
1258    Offset = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, Offset);
1259    Offset = DAG.getLoad(PtrVT, dl, Chain, Offset, NULL, 0);
1260    Chain = Offset.getValue(1);
1261
1262    SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex++, MVT::i32);
1263    Offset = DAG.getNode(ARMISD::PIC_ADD, dl, PtrVT, Offset, PICLabel);
1264
1265    Offset = DAG.getLoad(PtrVT, dl, Chain, Offset, NULL, 0);
1266  } else {
1267    // local exec model
1268    ARMConstantPoolValue *CPV = new ARMConstantPoolValue(GV, "tpoff");
1269    Offset = DAG.getTargetConstantPool(CPV, PtrVT, 4);
1270    Offset = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, Offset);
1271    Offset = DAG.getLoad(PtrVT, dl, Chain, Offset, NULL, 0);
1272  }
1273
1274  // The address of the thread local variable is the add of the thread
1275  // pointer with the offset of the variable.
1276  return DAG.getNode(ISD::ADD, dl, PtrVT, ThreadPointer, Offset);
1277}
1278
1279SDValue
1280ARMTargetLowering::LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) {
1281  // TODO: implement the "local dynamic" model
1282  assert(Subtarget->isTargetELF() &&
1283         "TLS not implemented for non-ELF targets");
1284  GlobalAddressSDNode *GA = cast<GlobalAddressSDNode>(Op);
1285  // If the relocation model is PIC, use the "General Dynamic" TLS Model,
1286  // otherwise use the "Local Exec" TLS Model
1287  if (getTargetMachine().getRelocationModel() == Reloc::PIC_)
1288    return LowerToTLSGeneralDynamicModel(GA, DAG);
1289  else
1290    return LowerToTLSExecModels(GA, DAG);
1291}
1292
1293SDValue ARMTargetLowering::LowerGlobalAddressELF(SDValue Op,
1294                                                 SelectionDAG &DAG) {
1295  EVT PtrVT = getPointerTy();
1296  DebugLoc dl = Op.getDebugLoc();
1297  GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
1298  Reloc::Model RelocM = getTargetMachine().getRelocationModel();
1299  if (RelocM == Reloc::PIC_) {
1300    bool UseGOTOFF = GV->hasLocalLinkage() || GV->hasHiddenVisibility();
1301    ARMConstantPoolValue *CPV =
1302      new ARMConstantPoolValue(GV, UseGOTOFF ? "GOTOFF" : "GOT");
1303    SDValue CPAddr = DAG.getTargetConstantPool(CPV, PtrVT, 4);
1304    CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr);
1305    SDValue Result = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(),
1306                                 CPAddr, NULL, 0);
1307    SDValue Chain = Result.getValue(1);
1308    SDValue GOT = DAG.getGLOBAL_OFFSET_TABLE(PtrVT);
1309    Result = DAG.getNode(ISD::ADD, dl, PtrVT, Result, GOT);
1310    if (!UseGOTOFF)
1311      Result = DAG.getLoad(PtrVT, dl, Chain, Result, NULL, 0);
1312    return Result;
1313  } else {
1314    SDValue CPAddr = DAG.getTargetConstantPool(GV, PtrVT, 4);
1315    CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr);
1316    return DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), CPAddr, NULL, 0);
1317  }
1318}
1319
1320SDValue ARMTargetLowering::LowerGlobalAddressDarwin(SDValue Op,
1321                                                    SelectionDAG &DAG) {
1322  EVT PtrVT = getPointerTy();
1323  DebugLoc dl = Op.getDebugLoc();
1324  GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
1325  Reloc::Model RelocM = getTargetMachine().getRelocationModel();
1326  SDValue CPAddr;
1327  if (RelocM == Reloc::Static)
1328    CPAddr = DAG.getTargetConstantPool(GV, PtrVT, 4);
1329  else {
1330    unsigned PCAdj = (RelocM != Reloc::PIC_) ? 0 : (Subtarget->isThumb()?4:8);
1331    ARMConstantPoolValue *CPV =
1332      new ARMConstantPoolValue(GV, ARMPCLabelIndex, ARMCP::CPValue, PCAdj);
1333    CPAddr = DAG.getTargetConstantPool(CPV, PtrVT, 4);
1334  }
1335  CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr);
1336
1337  SDValue Result = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), CPAddr, NULL, 0);
1338  SDValue Chain = Result.getValue(1);
1339
1340  if (RelocM == Reloc::PIC_) {
1341    SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex++, MVT::i32);
1342    Result = DAG.getNode(ARMISD::PIC_ADD, dl, PtrVT, Result, PICLabel);
1343  }
1344
1345  if (Subtarget->GVIsIndirectSymbol(GV, RelocM))
1346    Result = DAG.getLoad(PtrVT, dl, Chain, Result, NULL, 0);
1347
1348  return Result;
1349}
1350
1351SDValue ARMTargetLowering::LowerGLOBAL_OFFSET_TABLE(SDValue Op,
1352                                                    SelectionDAG &DAG){
1353  assert(Subtarget->isTargetELF() &&
1354         "GLOBAL OFFSET TABLE not implemented for non-ELF targets");
1355  EVT PtrVT = getPointerTy();
1356  DebugLoc dl = Op.getDebugLoc();
1357  unsigned PCAdj = Subtarget->isThumb() ? 4 : 8;
1358  ARMConstantPoolValue *CPV = new ARMConstantPoolValue(*DAG.getContext(),
1359                                                       "_GLOBAL_OFFSET_TABLE_",
1360                                                       ARMPCLabelIndex, PCAdj);
1361  SDValue CPAddr = DAG.getTargetConstantPool(CPV, PtrVT, 4);
1362  CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr);
1363  SDValue Result = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), CPAddr, NULL, 0);
1364  SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex++, MVT::i32);
1365  return DAG.getNode(ARMISD::PIC_ADD, dl, PtrVT, Result, PICLabel);
1366}
1367
1368static SDValue LowerNeonVLDIntrinsic(SDValue Op, SelectionDAG &DAG,
1369                                     unsigned NumVecs) {
1370  SDNode *Node = Op.getNode();
1371  EVT VT = Node->getValueType(0);
1372
1373  // No expansion needed for 64-bit vectors.
1374  if (VT.is64BitVector())
1375    return SDValue();
1376
1377  // FIXME: We need to expand VLD3 and VLD4 of 128-bit vectors into separate
1378  // operations to load the even and odd registers.
1379  return SDValue();
1380}
1381
1382static SDValue LowerNeonVSTIntrinsic(SDValue Op, SelectionDAG &DAG,
1383                                     unsigned NumVecs) {
1384  SDNode *Node = Op.getNode();
1385  EVT VT = Node->getOperand(3).getValueType();
1386
1387  // No expansion needed for 64-bit vectors.
1388  if (VT.is64BitVector())
1389    return SDValue();
1390
1391  // FIXME: We need to expand VST3 and VST4 of 128-bit vectors into separate
1392  // operations to store the even and odd registers.
1393  return SDValue();
1394}
1395
1396static SDValue LowerNeonVLDLaneIntrinsic(SDValue Op, SelectionDAG &DAG,
1397                                         unsigned NumVecs) {
1398  SDNode *Node = Op.getNode();
1399  EVT VT = Node->getValueType(0);
1400
1401  if (!VT.is64BitVector())
1402    return SDValue(); // unimplemented
1403
1404  // Change the lane number operand to be a TargetConstant; otherwise it
1405  // will be legalized into a register.
1406  ConstantSDNode *Lane = dyn_cast<ConstantSDNode>(Node->getOperand(NumVecs+3));
1407  if (!Lane) {
1408    assert(false && "vld lane number must be a constant");
1409    return SDValue();
1410  }
1411  SmallVector<SDValue, 8> Ops(Node->op_begin(), Node->op_end());
1412  Ops[NumVecs+3] = DAG.getTargetConstant(Lane->getZExtValue(), MVT::i32);
1413  return DAG.UpdateNodeOperands(Op, &Ops[0], Ops.size());
1414}
1415
1416static SDValue LowerNeonVSTLaneIntrinsic(SDValue Op, SelectionDAG &DAG,
1417                                         unsigned NumVecs) {
1418  SDNode *Node = Op.getNode();
1419  EVT VT = Node->getOperand(3).getValueType();
1420
1421  if (!VT.is64BitVector())
1422    return SDValue(); // unimplemented
1423
1424  // Change the lane number operand to be a TargetConstant; otherwise it
1425  // will be legalized into a register.
1426  ConstantSDNode *Lane = dyn_cast<ConstantSDNode>(Node->getOperand(NumVecs+3));
1427  if (!Lane) {
1428    assert(false && "vst lane number must be a constant");
1429    return SDValue();
1430  }
1431  SmallVector<SDValue, 8> Ops(Node->op_begin(), Node->op_end());
1432  Ops[NumVecs+3] = DAG.getTargetConstant(Lane->getZExtValue(), MVT::i32);
1433  return DAG.UpdateNodeOperands(Op, &Ops[0], Ops.size());
1434}
1435
1436SDValue
1437ARMTargetLowering::LowerINTRINSIC_W_CHAIN(SDValue Op, SelectionDAG &DAG) {
1438  unsigned IntNo = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
1439  switch (IntNo) {
1440  case Intrinsic::arm_neon_vld3:
1441    return LowerNeonVLDIntrinsic(Op, DAG, 3);
1442  case Intrinsic::arm_neon_vld4:
1443    return LowerNeonVLDIntrinsic(Op, DAG, 4);
1444  case Intrinsic::arm_neon_vld2lane:
1445    return LowerNeonVLDLaneIntrinsic(Op, DAG, 2);
1446  case Intrinsic::arm_neon_vld3lane:
1447    return LowerNeonVLDLaneIntrinsic(Op, DAG, 3);
1448  case Intrinsic::arm_neon_vld4lane:
1449    return LowerNeonVLDLaneIntrinsic(Op, DAG, 4);
1450  case Intrinsic::arm_neon_vst3:
1451    return LowerNeonVSTIntrinsic(Op, DAG, 3);
1452  case Intrinsic::arm_neon_vst4:
1453    return LowerNeonVSTIntrinsic(Op, DAG, 4);
1454  case Intrinsic::arm_neon_vst2lane:
1455    return LowerNeonVSTLaneIntrinsic(Op, DAG, 2);
1456  case Intrinsic::arm_neon_vst3lane:
1457    return LowerNeonVSTLaneIntrinsic(Op, DAG, 3);
1458  case Intrinsic::arm_neon_vst4lane:
1459    return LowerNeonVSTLaneIntrinsic(Op, DAG, 4);
1460  default: return SDValue();    // Don't custom lower most intrinsics.
1461  }
1462}
1463
1464SDValue
1465ARMTargetLowering::LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) {
1466  unsigned IntNo = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
1467  DebugLoc dl = Op.getDebugLoc();
1468  switch (IntNo) {
1469  default: return SDValue();    // Don't custom lower most intrinsics.
1470  case Intrinsic::arm_thread_pointer: {
1471    EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
1472    return DAG.getNode(ARMISD::THREAD_POINTER, dl, PtrVT);
1473  }
1474  case Intrinsic::eh_sjlj_lsda: {
1475    MachineFunction &MF = DAG.getMachineFunction();
1476    EVT PtrVT = getPointerTy();
1477    DebugLoc dl = Op.getDebugLoc();
1478    Reloc::Model RelocM = getTargetMachine().getRelocationModel();
1479    SDValue CPAddr;
1480    unsigned PCAdj = (RelocM != Reloc::PIC_)
1481      ? 0 : (Subtarget->isThumb() ? 4 : 8);
1482    ARMConstantPoolValue *CPV =
1483      new ARMConstantPoolValue(MF.getFunction(), ARMPCLabelIndex,
1484                               ARMCP::CPLSDA, PCAdj);
1485    CPAddr = DAG.getTargetConstantPool(CPV, PtrVT, 4);
1486    CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr);
1487    SDValue Result =
1488      DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), CPAddr, NULL, 0);
1489    SDValue Chain = Result.getValue(1);
1490
1491    if (RelocM == Reloc::PIC_) {
1492      SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex++, MVT::i32);
1493      Result = DAG.getNode(ARMISD::PIC_ADD, dl, PtrVT, Result, PICLabel);
1494    }
1495    return Result;
1496  }
1497  case Intrinsic::eh_sjlj_setjmp:
1498    return DAG.getNode(ARMISD::EH_SJLJ_SETJMP, dl, MVT::i32, Op.getOperand(1));
1499  }
1500}
1501
1502static SDValue LowerVASTART(SDValue Op, SelectionDAG &DAG,
1503                            unsigned VarArgsFrameIndex) {
1504  // vastart just stores the address of the VarArgsFrameIndex slot into the
1505  // memory location argument.
1506  DebugLoc dl = Op.getDebugLoc();
1507  EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
1508  SDValue FR = DAG.getFrameIndex(VarArgsFrameIndex, PtrVT);
1509  const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
1510  return DAG.getStore(Op.getOperand(0), dl, FR, Op.getOperand(1), SV, 0);
1511}
1512
1513SDValue
1514ARMTargetLowering::LowerDYNAMIC_STACKALLOC(SDValue Op, SelectionDAG &DAG) {
1515  SDNode *Node = Op.getNode();
1516  DebugLoc dl = Node->getDebugLoc();
1517  EVT VT = Node->getValueType(0);
1518  SDValue Chain = Op.getOperand(0);
1519  SDValue Size  = Op.getOperand(1);
1520  SDValue Align = Op.getOperand(2);
1521
1522  // Chain the dynamic stack allocation so that it doesn't modify the stack
1523  // pointer when other instructions are using the stack.
1524  Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(0, true));
1525
1526  unsigned AlignVal = cast<ConstantSDNode>(Align)->getZExtValue();
1527  unsigned StackAlign = getTargetMachine().getFrameInfo()->getStackAlignment();
1528  if (AlignVal > StackAlign)
1529    // Do this now since selection pass cannot introduce new target
1530    // independent node.
1531    Align = DAG.getConstant(-(uint64_t)AlignVal, VT);
1532
1533  // In Thumb1 mode, there isn't a "sub r, sp, r" instruction, we will end up
1534  // using a "add r, sp, r" instead. Negate the size now so we don't have to
1535  // do even more horrible hack later.
1536  MachineFunction &MF = DAG.getMachineFunction();
1537  ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
1538  if (AFI->isThumb1OnlyFunction()) {
1539    bool Negate = true;
1540    ConstantSDNode *C = dyn_cast<ConstantSDNode>(Size);
1541    if (C) {
1542      uint32_t Val = C->getZExtValue();
1543      if (Val <= 508 && ((Val & 3) == 0))
1544        Negate = false;
1545    }
1546    if (Negate)
1547      Size = DAG.getNode(ISD::SUB, dl, VT, DAG.getConstant(0, VT), Size);
1548  }
1549
1550  SDVTList VTList = DAG.getVTList(VT, MVT::Other);
1551  SDValue Ops1[] = { Chain, Size, Align };
1552  SDValue Res = DAG.getNode(ARMISD::DYN_ALLOC, dl, VTList, Ops1, 3);
1553  Chain = Res.getValue(1);
1554  Chain = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(0, true),
1555                             DAG.getIntPtrConstant(0, true), SDValue());
1556  SDValue Ops2[] = { Res, Chain };
1557  return DAG.getMergeValues(Ops2, 2, dl);
1558}
1559
1560SDValue
1561ARMTargetLowering::GetF64FormalArgument(CCValAssign &VA, CCValAssign &NextVA,
1562                                        SDValue &Root, SelectionDAG &DAG,
1563                                        DebugLoc dl) {
1564  MachineFunction &MF = DAG.getMachineFunction();
1565  ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
1566
1567  TargetRegisterClass *RC;
1568  if (AFI->isThumb1OnlyFunction())
1569    RC = ARM::tGPRRegisterClass;
1570  else
1571    RC = ARM::GPRRegisterClass;
1572
1573  // Transform the arguments stored in physical registers into virtual ones.
1574  unsigned Reg = MF.addLiveIn(VA.getLocReg(), RC);
1575  SDValue ArgValue = DAG.getCopyFromReg(Root, dl, Reg, MVT::i32);
1576
1577  SDValue ArgValue2;
1578  if (NextVA.isMemLoc()) {
1579    unsigned ArgSize = NextVA.getLocVT().getSizeInBits()/8;
1580    MachineFrameInfo *MFI = MF.getFrameInfo();
1581    int FI = MFI->CreateFixedObject(ArgSize, NextVA.getLocMemOffset());
1582
1583    // Create load node to retrieve arguments from the stack.
1584    SDValue FIN = DAG.getFrameIndex(FI, getPointerTy());
1585    ArgValue2 = DAG.getLoad(MVT::i32, dl, Root, FIN, NULL, 0);
1586  } else {
1587    Reg = MF.addLiveIn(NextVA.getLocReg(), RC);
1588    ArgValue2 = DAG.getCopyFromReg(Root, dl, Reg, MVT::i32);
1589  }
1590
1591  return DAG.getNode(ARMISD::FMDRR, dl, MVT::f64, ArgValue, ArgValue2);
1592}
1593
1594SDValue
1595ARMTargetLowering::LowerFormalArguments(SDValue Chain,
1596                                        CallingConv::ID CallConv, bool isVarArg,
1597                                        const SmallVectorImpl<ISD::InputArg>
1598                                          &Ins,
1599                                        DebugLoc dl, SelectionDAG &DAG,
1600                                        SmallVectorImpl<SDValue> &InVals) {
1601
1602  MachineFunction &MF = DAG.getMachineFunction();
1603  MachineFrameInfo *MFI = MF.getFrameInfo();
1604
1605  ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
1606
1607  // Assign locations to all of the incoming arguments.
1608  SmallVector<CCValAssign, 16> ArgLocs;
1609  CCState CCInfo(CallConv, isVarArg, getTargetMachine(), ArgLocs,
1610                 *DAG.getContext());
1611  CCInfo.AnalyzeFormalArguments(Ins,
1612                                CCAssignFnForNode(CallConv, /* Return*/ false,
1613                                                  isVarArg));
1614
1615  SmallVector<SDValue, 16> ArgValues;
1616
1617  for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
1618    CCValAssign &VA = ArgLocs[i];
1619
1620    // Arguments stored in registers.
1621    if (VA.isRegLoc()) {
1622      EVT RegVT = VA.getLocVT();
1623
1624      SDValue ArgValue;
1625      if (VA.needsCustom()) {
1626        // f64 and vector types are split up into multiple registers or
1627        // combinations of registers and stack slots.
1628        RegVT = MVT::i32;
1629
1630        if (VA.getLocVT() == MVT::v2f64) {
1631          SDValue ArgValue1 = GetF64FormalArgument(VA, ArgLocs[++i],
1632                                                   Chain, DAG, dl);
1633          VA = ArgLocs[++i]; // skip ahead to next loc
1634          SDValue ArgValue2 = GetF64FormalArgument(VA, ArgLocs[++i],
1635                                                   Chain, DAG, dl);
1636          ArgValue = DAG.getNode(ISD::UNDEF, dl, MVT::v2f64);
1637          ArgValue = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v2f64,
1638                                 ArgValue, ArgValue1, DAG.getIntPtrConstant(0));
1639          ArgValue = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v2f64,
1640                                 ArgValue, ArgValue2, DAG.getIntPtrConstant(1));
1641        } else
1642          ArgValue = GetF64FormalArgument(VA, ArgLocs[++i], Chain, DAG, dl);
1643
1644      } else {
1645        TargetRegisterClass *RC;
1646
1647        if (RegVT == MVT::f32)
1648          RC = ARM::SPRRegisterClass;
1649        else if (RegVT == MVT::f64)
1650          RC = ARM::DPRRegisterClass;
1651        else if (RegVT == MVT::v2f64)
1652          RC = ARM::QPRRegisterClass;
1653        else if (RegVT == MVT::i32)
1654          RC = (AFI->isThumb1OnlyFunction() ?
1655                ARM::tGPRRegisterClass : ARM::GPRRegisterClass);
1656        else
1657          llvm_unreachable("RegVT not supported by FORMAL_ARGUMENTS Lowering");
1658
1659        // Transform the arguments in physical registers into virtual ones.
1660        unsigned Reg = MF.addLiveIn(VA.getLocReg(), RC);
1661        ArgValue = DAG.getCopyFromReg(Chain, dl, Reg, RegVT);
1662      }
1663
1664      // If this is an 8 or 16-bit value, it is really passed promoted
1665      // to 32 bits.  Insert an assert[sz]ext to capture this, then
1666      // truncate to the right size.
1667      switch (VA.getLocInfo()) {
1668      default: llvm_unreachable("Unknown loc info!");
1669      case CCValAssign::Full: break;
1670      case CCValAssign::BCvt:
1671        ArgValue = DAG.getNode(ISD::BIT_CONVERT, dl, VA.getValVT(), ArgValue);
1672        break;
1673      case CCValAssign::SExt:
1674        ArgValue = DAG.getNode(ISD::AssertSext, dl, RegVT, ArgValue,
1675                               DAG.getValueType(VA.getValVT()));
1676        ArgValue = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), ArgValue);
1677        break;
1678      case CCValAssign::ZExt:
1679        ArgValue = DAG.getNode(ISD::AssertZext, dl, RegVT, ArgValue,
1680                               DAG.getValueType(VA.getValVT()));
1681        ArgValue = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), ArgValue);
1682        break;
1683      }
1684
1685      InVals.push_back(ArgValue);
1686
1687    } else { // VA.isRegLoc()
1688
1689      // sanity check
1690      assert(VA.isMemLoc());
1691      assert(VA.getValVT() != MVT::i64 && "i64 should already be lowered");
1692
1693      unsigned ArgSize = VA.getLocVT().getSizeInBits()/8;
1694      int FI = MFI->CreateFixedObject(ArgSize, VA.getLocMemOffset());
1695
1696      // Create load nodes to retrieve arguments from the stack.
1697      SDValue FIN = DAG.getFrameIndex(FI, getPointerTy());
1698      InVals.push_back(DAG.getLoad(VA.getValVT(), dl, Chain, FIN, NULL, 0));
1699    }
1700  }
1701
1702  // varargs
1703  if (isVarArg) {
1704    static const unsigned GPRArgRegs[] = {
1705      ARM::R0, ARM::R1, ARM::R2, ARM::R3
1706    };
1707
1708    unsigned NumGPRs = CCInfo.getFirstUnallocated
1709      (GPRArgRegs, sizeof(GPRArgRegs) / sizeof(GPRArgRegs[0]));
1710
1711    unsigned Align = MF.getTarget().getFrameInfo()->getStackAlignment();
1712    unsigned VARegSize = (4 - NumGPRs) * 4;
1713    unsigned VARegSaveSize = (VARegSize + Align - 1) & ~(Align - 1);
1714    unsigned ArgOffset = 0;
1715    if (VARegSaveSize) {
1716      // If this function is vararg, store any remaining integer argument regs
1717      // to their spots on the stack so that they may be loaded by deferencing
1718      // the result of va_next.
1719      AFI->setVarArgsRegSaveSize(VARegSaveSize);
1720      ArgOffset = CCInfo.getNextStackOffset();
1721      VarArgsFrameIndex = MFI->CreateFixedObject(VARegSaveSize, ArgOffset +
1722                                                 VARegSaveSize - VARegSize);
1723      SDValue FIN = DAG.getFrameIndex(VarArgsFrameIndex, getPointerTy());
1724
1725      SmallVector<SDValue, 4> MemOps;
1726      for (; NumGPRs < 4; ++NumGPRs) {
1727        TargetRegisterClass *RC;
1728        if (AFI->isThumb1OnlyFunction())
1729          RC = ARM::tGPRRegisterClass;
1730        else
1731          RC = ARM::GPRRegisterClass;
1732
1733        unsigned VReg = MF.addLiveIn(GPRArgRegs[NumGPRs], RC);
1734        SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, MVT::i32);
1735        SDValue Store = DAG.getStore(Val.getValue(1), dl, Val, FIN, NULL, 0);
1736        MemOps.push_back(Store);
1737        FIN = DAG.getNode(ISD::ADD, dl, getPointerTy(), FIN,
1738                          DAG.getConstant(4, getPointerTy()));
1739      }
1740      if (!MemOps.empty())
1741        Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
1742                            &MemOps[0], MemOps.size());
1743    } else
1744      // This will point to the next argument passed via stack.
1745      VarArgsFrameIndex = MFI->CreateFixedObject(4, ArgOffset);
1746  }
1747
1748  return Chain;
1749}
1750
1751/// isFloatingPointZero - Return true if this is +0.0.
1752static bool isFloatingPointZero(SDValue Op) {
1753  if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(Op))
1754    return CFP->getValueAPF().isPosZero();
1755  else if (ISD::isEXTLoad(Op.getNode()) || ISD::isNON_EXTLoad(Op.getNode())) {
1756    // Maybe this has already been legalized into the constant pool?
1757    if (Op.getOperand(1).getOpcode() == ARMISD::Wrapper) {
1758      SDValue WrapperOp = Op.getOperand(1).getOperand(0);
1759      if (ConstantPoolSDNode *CP = dyn_cast<ConstantPoolSDNode>(WrapperOp))
1760        if (ConstantFP *CFP = dyn_cast<ConstantFP>(CP->getConstVal()))
1761          return CFP->getValueAPF().isPosZero();
1762    }
1763  }
1764  return false;
1765}
1766
1767static bool isLegalCmpImmediate(unsigned C, bool isThumb1Only) {
1768  return ( isThumb1Only && (C & ~255U) == 0) ||
1769         (!isThumb1Only && ARM_AM::getSOImmVal(C) != -1);
1770}
1771
1772/// Returns appropriate ARM CMP (cmp) and corresponding condition code for
1773/// the given operands.
1774static SDValue getARMCmp(SDValue LHS, SDValue RHS, ISD::CondCode CC,
1775                         SDValue &ARMCC, SelectionDAG &DAG, bool isThumb1Only,
1776                         DebugLoc dl) {
1777  if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(RHS.getNode())) {
1778    unsigned C = RHSC->getZExtValue();
1779    if (!isLegalCmpImmediate(C, isThumb1Only)) {
1780      // Constant does not fit, try adjusting it by one?
1781      switch (CC) {
1782      default: break;
1783      case ISD::SETLT:
1784      case ISD::SETGE:
1785        if (isLegalCmpImmediate(C-1, isThumb1Only)) {
1786          CC = (CC == ISD::SETLT) ? ISD::SETLE : ISD::SETGT;
1787          RHS = DAG.getConstant(C-1, MVT::i32);
1788        }
1789        break;
1790      case ISD::SETULT:
1791      case ISD::SETUGE:
1792        if (C > 0 && isLegalCmpImmediate(C-1, isThumb1Only)) {
1793          CC = (CC == ISD::SETULT) ? ISD::SETULE : ISD::SETUGT;
1794          RHS = DAG.getConstant(C-1, MVT::i32);
1795        }
1796        break;
1797      case ISD::SETLE:
1798      case ISD::SETGT:
1799        if (isLegalCmpImmediate(C+1, isThumb1Only)) {
1800          CC = (CC == ISD::SETLE) ? ISD::SETLT : ISD::SETGE;
1801          RHS = DAG.getConstant(C+1, MVT::i32);
1802        }
1803        break;
1804      case ISD::SETULE:
1805      case ISD::SETUGT:
1806        if (C < 0xffffffff && isLegalCmpImmediate(C+1, isThumb1Only)) {
1807          CC = (CC == ISD::SETULE) ? ISD::SETULT : ISD::SETUGE;
1808          RHS = DAG.getConstant(C+1, MVT::i32);
1809        }
1810        break;
1811      }
1812    }
1813  }
1814
1815  ARMCC::CondCodes CondCode = IntCCToARMCC(CC);
1816  ARMISD::NodeType CompareType;
1817  switch (CondCode) {
1818  default:
1819    CompareType = ARMISD::CMP;
1820    break;
1821  case ARMCC::EQ:
1822  case ARMCC::NE:
1823    // Uses only Z Flag
1824    CompareType = ARMISD::CMPZ;
1825    break;
1826  }
1827  ARMCC = DAG.getConstant(CondCode, MVT::i32);
1828  return DAG.getNode(CompareType, dl, MVT::Flag, LHS, RHS);
1829}
1830
1831/// Returns a appropriate VFP CMP (fcmp{s|d}+fmstat) for the given operands.
1832static SDValue getVFPCmp(SDValue LHS, SDValue RHS, SelectionDAG &DAG,
1833                         DebugLoc dl) {
1834  SDValue Cmp;
1835  if (!isFloatingPointZero(RHS))
1836    Cmp = DAG.getNode(ARMISD::CMPFP, dl, MVT::Flag, LHS, RHS);
1837  else
1838    Cmp = DAG.getNode(ARMISD::CMPFPw0, dl, MVT::Flag, LHS);
1839  return DAG.getNode(ARMISD::FMSTAT, dl, MVT::Flag, Cmp);
1840}
1841
1842static SDValue LowerSELECT_CC(SDValue Op, SelectionDAG &DAG,
1843                              const ARMSubtarget *ST) {
1844  EVT VT = Op.getValueType();
1845  SDValue LHS = Op.getOperand(0);
1846  SDValue RHS = Op.getOperand(1);
1847  ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(4))->get();
1848  SDValue TrueVal = Op.getOperand(2);
1849  SDValue FalseVal = Op.getOperand(3);
1850  DebugLoc dl = Op.getDebugLoc();
1851
1852  if (LHS.getValueType() == MVT::i32) {
1853    SDValue ARMCC;
1854    SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
1855    SDValue Cmp = getARMCmp(LHS, RHS, CC, ARMCC, DAG, ST->isThumb1Only(), dl);
1856    return DAG.getNode(ARMISD::CMOV, dl, VT, FalseVal, TrueVal, ARMCC, CCR,Cmp);
1857  }
1858
1859  ARMCC::CondCodes CondCode, CondCode2;
1860  FPCCToARMCC(CC, CondCode, CondCode2);
1861
1862  SDValue ARMCC = DAG.getConstant(CondCode, MVT::i32);
1863  SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
1864  SDValue Cmp = getVFPCmp(LHS, RHS, DAG, dl);
1865  SDValue Result = DAG.getNode(ARMISD::CMOV, dl, VT, FalseVal, TrueVal,
1866                                 ARMCC, CCR, Cmp);
1867  if (CondCode2 != ARMCC::AL) {
1868    SDValue ARMCC2 = DAG.getConstant(CondCode2, MVT::i32);
1869    // FIXME: Needs another CMP because flag can have but one use.
1870    SDValue Cmp2 = getVFPCmp(LHS, RHS, DAG, dl);
1871    Result = DAG.getNode(ARMISD::CMOV, dl, VT,
1872                         Result, TrueVal, ARMCC2, CCR, Cmp2);
1873  }
1874  return Result;
1875}
1876
1877static SDValue LowerBR_CC(SDValue Op, SelectionDAG &DAG,
1878                          const ARMSubtarget *ST) {
1879  SDValue  Chain = Op.getOperand(0);
1880  ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(1))->get();
1881  SDValue    LHS = Op.getOperand(2);
1882  SDValue    RHS = Op.getOperand(3);
1883  SDValue   Dest = Op.getOperand(4);
1884  DebugLoc dl = Op.getDebugLoc();
1885
1886  if (LHS.getValueType() == MVT::i32) {
1887    SDValue ARMCC;
1888    SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
1889    SDValue Cmp = getARMCmp(LHS, RHS, CC, ARMCC, DAG, ST->isThumb1Only(), dl);
1890    return DAG.getNode(ARMISD::BRCOND, dl, MVT::Other,
1891                       Chain, Dest, ARMCC, CCR,Cmp);
1892  }
1893
1894  assert(LHS.getValueType() == MVT::f32 || LHS.getValueType() == MVT::f64);
1895  ARMCC::CondCodes CondCode, CondCode2;
1896  FPCCToARMCC(CC, CondCode, CondCode2);
1897
1898  SDValue Cmp = getVFPCmp(LHS, RHS, DAG, dl);
1899  SDValue ARMCC = DAG.getConstant(CondCode, MVT::i32);
1900  SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
1901  SDVTList VTList = DAG.getVTList(MVT::Other, MVT::Flag);
1902  SDValue Ops[] = { Chain, Dest, ARMCC, CCR, Cmp };
1903  SDValue Res = DAG.getNode(ARMISD::BRCOND, dl, VTList, Ops, 5);
1904  if (CondCode2 != ARMCC::AL) {
1905    ARMCC = DAG.getConstant(CondCode2, MVT::i32);
1906    SDValue Ops[] = { Res, Dest, ARMCC, CCR, Res.getValue(1) };
1907    Res = DAG.getNode(ARMISD::BRCOND, dl, VTList, Ops, 5);
1908  }
1909  return Res;
1910}
1911
1912SDValue ARMTargetLowering::LowerBR_JT(SDValue Op, SelectionDAG &DAG) {
1913  SDValue Chain = Op.getOperand(0);
1914  SDValue Table = Op.getOperand(1);
1915  SDValue Index = Op.getOperand(2);
1916  DebugLoc dl = Op.getDebugLoc();
1917
1918  EVT PTy = getPointerTy();
1919  JumpTableSDNode *JT = cast<JumpTableSDNode>(Table);
1920  ARMFunctionInfo *AFI = DAG.getMachineFunction().getInfo<ARMFunctionInfo>();
1921  SDValue UId = DAG.getConstant(AFI->createJumpTableUId(), PTy);
1922  SDValue JTI = DAG.getTargetJumpTable(JT->getIndex(), PTy);
1923  Table = DAG.getNode(ARMISD::WrapperJT, dl, MVT::i32, JTI, UId);
1924  Index = DAG.getNode(ISD::MUL, dl, PTy, Index, DAG.getConstant(4, PTy));
1925  SDValue Addr = DAG.getNode(ISD::ADD, dl, PTy, Index, Table);
1926  if (Subtarget->isThumb2()) {
1927    // Thumb2 uses a two-level jump. That is, it jumps into the jump table
1928    // which does another jump to the destination. This also makes it easier
1929    // to translate it to TBB / TBH later.
1930    // FIXME: This might not work if the function is extremely large.
1931    return DAG.getNode(ARMISD::BR2_JT, dl, MVT::Other, Chain,
1932                       Addr, Op.getOperand(2), JTI, UId);
1933  }
1934  if (getTargetMachine().getRelocationModel() == Reloc::PIC_) {
1935    Addr = DAG.getLoad((EVT)MVT::i32, dl, Chain, Addr, NULL, 0);
1936    Chain = Addr.getValue(1);
1937    Addr = DAG.getNode(ISD::ADD, dl, PTy, Addr, Table);
1938    return DAG.getNode(ARMISD::BR_JT, dl, MVT::Other, Chain, Addr, JTI, UId);
1939  } else {
1940    Addr = DAG.getLoad(PTy, dl, Chain, Addr, NULL, 0);
1941    Chain = Addr.getValue(1);
1942    return DAG.getNode(ARMISD::BR_JT, dl, MVT::Other, Chain, Addr, JTI, UId);
1943  }
1944}
1945
1946static SDValue LowerFP_TO_INT(SDValue Op, SelectionDAG &DAG) {
1947  DebugLoc dl = Op.getDebugLoc();
1948  unsigned Opc =
1949    Op.getOpcode() == ISD::FP_TO_SINT ? ARMISD::FTOSI : ARMISD::FTOUI;
1950  Op = DAG.getNode(Opc, dl, MVT::f32, Op.getOperand(0));
1951  return DAG.getNode(ISD::BIT_CONVERT, dl, MVT::i32, Op);
1952}
1953
1954static SDValue LowerINT_TO_FP(SDValue Op, SelectionDAG &DAG) {
1955  EVT VT = Op.getValueType();
1956  DebugLoc dl = Op.getDebugLoc();
1957  unsigned Opc =
1958    Op.getOpcode() == ISD::SINT_TO_FP ? ARMISD::SITOF : ARMISD::UITOF;
1959
1960  Op = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::f32, Op.getOperand(0));
1961  return DAG.getNode(Opc, dl, VT, Op);
1962}
1963
1964static SDValue LowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG) {
1965  // Implement fcopysign with a fabs and a conditional fneg.
1966  SDValue Tmp0 = Op.getOperand(0);
1967  SDValue Tmp1 = Op.getOperand(1);
1968  DebugLoc dl = Op.getDebugLoc();
1969  EVT VT = Op.getValueType();
1970  EVT SrcVT = Tmp1.getValueType();
1971  SDValue AbsVal = DAG.getNode(ISD::FABS, dl, VT, Tmp0);
1972  SDValue Cmp = getVFPCmp(Tmp1, DAG.getConstantFP(0.0, SrcVT), DAG, dl);
1973  SDValue ARMCC = DAG.getConstant(ARMCC::LT, MVT::i32);
1974  SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
1975  return DAG.getNode(ARMISD::CNEG, dl, VT, AbsVal, AbsVal, ARMCC, CCR, Cmp);
1976}
1977
1978SDValue ARMTargetLowering::LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) {
1979  MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
1980  MFI->setFrameAddressIsTaken(true);
1981  EVT VT = Op.getValueType();
1982  DebugLoc dl = Op.getDebugLoc();  // FIXME probably not meaningful
1983  unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
1984  unsigned FrameReg = (Subtarget->isThumb() || Subtarget->isTargetDarwin())
1985    ? ARM::R7 : ARM::R11;
1986  SDValue FrameAddr = DAG.getCopyFromReg(DAG.getEntryNode(), dl, FrameReg, VT);
1987  while (Depth--)
1988    FrameAddr = DAG.getLoad(VT, dl, DAG.getEntryNode(), FrameAddr, NULL, 0);
1989  return FrameAddr;
1990}
1991
1992SDValue
1993ARMTargetLowering::EmitTargetCodeForMemcpy(SelectionDAG &DAG, DebugLoc dl,
1994                                           SDValue Chain,
1995                                           SDValue Dst, SDValue Src,
1996                                           SDValue Size, unsigned Align,
1997                                           bool AlwaysInline,
1998                                         const Value *DstSV, uint64_t DstSVOff,
1999                                         const Value *SrcSV, uint64_t SrcSVOff){
2000  // Do repeated 4-byte loads and stores. To be improved.
2001  // This requires 4-byte alignment.
2002  if ((Align & 3) != 0)
2003    return SDValue();
2004  // This requires the copy size to be a constant, preferrably
2005  // within a subtarget-specific limit.
2006  ConstantSDNode *ConstantSize = dyn_cast<ConstantSDNode>(Size);
2007  if (!ConstantSize)
2008    return SDValue();
2009  uint64_t SizeVal = ConstantSize->getZExtValue();
2010  if (!AlwaysInline && SizeVal > getSubtarget()->getMaxInlineSizeThreshold())
2011    return SDValue();
2012
2013  unsigned BytesLeft = SizeVal & 3;
2014  unsigned NumMemOps = SizeVal >> 2;
2015  unsigned EmittedNumMemOps = 0;
2016  EVT VT = MVT::i32;
2017  unsigned VTSize = 4;
2018  unsigned i = 0;
2019  const unsigned MAX_LOADS_IN_LDM = 6;
2020  SDValue TFOps[MAX_LOADS_IN_LDM];
2021  SDValue Loads[MAX_LOADS_IN_LDM];
2022  uint64_t SrcOff = 0, DstOff = 0;
2023
2024  // Emit up to MAX_LOADS_IN_LDM loads, then a TokenFactor barrier, then the
2025  // same number of stores.  The loads and stores will get combined into
2026  // ldm/stm later on.
2027  while (EmittedNumMemOps < NumMemOps) {
2028    for (i = 0;
2029         i < MAX_LOADS_IN_LDM && EmittedNumMemOps + i < NumMemOps; ++i) {
2030      Loads[i] = DAG.getLoad(VT, dl, Chain,
2031                             DAG.getNode(ISD::ADD, dl, MVT::i32, Src,
2032                                         DAG.getConstant(SrcOff, MVT::i32)),
2033                             SrcSV, SrcSVOff + SrcOff);
2034      TFOps[i] = Loads[i].getValue(1);
2035      SrcOff += VTSize;
2036    }
2037    Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, &TFOps[0], i);
2038
2039    for (i = 0;
2040         i < MAX_LOADS_IN_LDM && EmittedNumMemOps + i < NumMemOps; ++i) {
2041      TFOps[i] = DAG.getStore(Chain, dl, Loads[i],
2042                           DAG.getNode(ISD::ADD, dl, MVT::i32, Dst,
2043                                       DAG.getConstant(DstOff, MVT::i32)),
2044                           DstSV, DstSVOff + DstOff);
2045      DstOff += VTSize;
2046    }
2047    Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, &TFOps[0], i);
2048
2049    EmittedNumMemOps += i;
2050  }
2051
2052  if (BytesLeft == 0)
2053    return Chain;
2054
2055  // Issue loads / stores for the trailing (1 - 3) bytes.
2056  unsigned BytesLeftSave = BytesLeft;
2057  i = 0;
2058  while (BytesLeft) {
2059    if (BytesLeft >= 2) {
2060      VT = MVT::i16;
2061      VTSize = 2;
2062    } else {
2063      VT = MVT::i8;
2064      VTSize = 1;
2065    }
2066
2067    Loads[i] = DAG.getLoad(VT, dl, Chain,
2068                           DAG.getNode(ISD::ADD, dl, MVT::i32, Src,
2069                                       DAG.getConstant(SrcOff, MVT::i32)),
2070                           SrcSV, SrcSVOff + SrcOff);
2071    TFOps[i] = Loads[i].getValue(1);
2072    ++i;
2073    SrcOff += VTSize;
2074    BytesLeft -= VTSize;
2075  }
2076  Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, &TFOps[0], i);
2077
2078  i = 0;
2079  BytesLeft = BytesLeftSave;
2080  while (BytesLeft) {
2081    if (BytesLeft >= 2) {
2082      VT = MVT::i16;
2083      VTSize = 2;
2084    } else {
2085      VT = MVT::i8;
2086      VTSize = 1;
2087    }
2088
2089    TFOps[i] = DAG.getStore(Chain, dl, Loads[i],
2090                            DAG.getNode(ISD::ADD, dl, MVT::i32, Dst,
2091                                        DAG.getConstant(DstOff, MVT::i32)),
2092                            DstSV, DstSVOff + DstOff);
2093    ++i;
2094    DstOff += VTSize;
2095    BytesLeft -= VTSize;
2096  }
2097  return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, &TFOps[0], i);
2098}
2099
2100static SDValue ExpandBIT_CONVERT(SDNode *N, SelectionDAG &DAG) {
2101  SDValue Op = N->getOperand(0);
2102  DebugLoc dl = N->getDebugLoc();
2103  if (N->getValueType(0) == MVT::f64) {
2104    // Turn i64->f64 into FMDRR.
2105    SDValue Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, Op,
2106                             DAG.getConstant(0, MVT::i32));
2107    SDValue Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, Op,
2108                             DAG.getConstant(1, MVT::i32));
2109    return DAG.getNode(ARMISD::FMDRR, dl, MVT::f64, Lo, Hi);
2110  }
2111
2112  // Turn f64->i64 into FMRRD.
2113  SDValue Cvt = DAG.getNode(ARMISD::FMRRD, dl,
2114                            DAG.getVTList(MVT::i32, MVT::i32), &Op, 1);
2115
2116  // Merge the pieces into a single i64 value.
2117  return DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, Cvt, Cvt.getValue(1));
2118}
2119
2120/// getZeroVector - Returns a vector of specified type with all zero elements.
2121///
2122static SDValue getZeroVector(EVT VT, SelectionDAG &DAG, DebugLoc dl) {
2123  assert(VT.isVector() && "Expected a vector type");
2124
2125  // Zero vectors are used to represent vector negation and in those cases
2126  // will be implemented with the NEON VNEG instruction.  However, VNEG does
2127  // not support i64 elements, so sometimes the zero vectors will need to be
2128  // explicitly constructed.  For those cases, and potentially other uses in
2129  // the future, always build zero vectors as <16 x i8> or <8 x i8> bitcasted
2130  // to their dest type.  This ensures they get CSE'd.
2131  SDValue Vec;
2132  SDValue Cst = DAG.getTargetConstant(0, MVT::i8);
2133  SmallVector<SDValue, 8> Ops;
2134  MVT TVT;
2135
2136  if (VT.getSizeInBits() == 64) {
2137    Ops.assign(8, Cst); TVT = MVT::v8i8;
2138  } else {
2139    Ops.assign(16, Cst); TVT = MVT::v16i8;
2140  }
2141  Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, TVT, &Ops[0], Ops.size());
2142
2143  return DAG.getNode(ISD::BIT_CONVERT, dl, VT, Vec);
2144}
2145
2146/// getOnesVector - Returns a vector of specified type with all bits set.
2147///
2148static SDValue getOnesVector(EVT VT, SelectionDAG &DAG, DebugLoc dl) {
2149  assert(VT.isVector() && "Expected a vector type");
2150
2151  // Always build ones vectors as <16 x i32> or <8 x i32> bitcasted to their
2152  // dest type. This ensures they get CSE'd.
2153  SDValue Vec;
2154  SDValue Cst = DAG.getTargetConstant(0xFF, MVT::i8);
2155  SmallVector<SDValue, 8> Ops;
2156  MVT TVT;
2157
2158  if (VT.getSizeInBits() == 64) {
2159    Ops.assign(8, Cst); TVT = MVT::v8i8;
2160  } else {
2161    Ops.assign(16, Cst); TVT = MVT::v16i8;
2162  }
2163  Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, TVT, &Ops[0], Ops.size());
2164
2165  return DAG.getNode(ISD::BIT_CONVERT, dl, VT, Vec);
2166}
2167
2168static SDValue LowerShift(SDNode *N, SelectionDAG &DAG,
2169                          const ARMSubtarget *ST) {
2170  EVT VT = N->getValueType(0);
2171  DebugLoc dl = N->getDebugLoc();
2172
2173  // Lower vector shifts on NEON to use VSHL.
2174  if (VT.isVector()) {
2175    assert(ST->hasNEON() && "unexpected vector shift");
2176
2177    // Left shifts translate directly to the vshiftu intrinsic.
2178    if (N->getOpcode() == ISD::SHL)
2179      return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
2180                         DAG.getConstant(Intrinsic::arm_neon_vshiftu, MVT::i32),
2181                         N->getOperand(0), N->getOperand(1));
2182
2183    assert((N->getOpcode() == ISD::SRA ||
2184            N->getOpcode() == ISD::SRL) && "unexpected vector shift opcode");
2185
2186    // NEON uses the same intrinsics for both left and right shifts.  For
2187    // right shifts, the shift amounts are negative, so negate the vector of
2188    // shift amounts.
2189    EVT ShiftVT = N->getOperand(1).getValueType();
2190    SDValue NegatedCount = DAG.getNode(ISD::SUB, dl, ShiftVT,
2191                                       getZeroVector(ShiftVT, DAG, dl),
2192                                       N->getOperand(1));
2193    Intrinsic::ID vshiftInt = (N->getOpcode() == ISD::SRA ?
2194                               Intrinsic::arm_neon_vshifts :
2195                               Intrinsic::arm_neon_vshiftu);
2196    return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
2197                       DAG.getConstant(vshiftInt, MVT::i32),
2198                       N->getOperand(0), NegatedCount);
2199  }
2200
2201  // We can get here for a node like i32 = ISD::SHL i32, i64
2202  if (VT != MVT::i64)
2203    return SDValue();
2204
2205  assert((N->getOpcode() == ISD::SRL || N->getOpcode() == ISD::SRA) &&
2206         "Unknown shift to lower!");
2207
2208  // We only lower SRA, SRL of 1 here, all others use generic lowering.
2209  if (!isa<ConstantSDNode>(N->getOperand(1)) ||
2210      cast<ConstantSDNode>(N->getOperand(1))->getZExtValue() != 1)
2211    return SDValue();
2212
2213  // If we are in thumb mode, we don't have RRX.
2214  if (ST->isThumb1Only()) return SDValue();
2215
2216  // Okay, we have a 64-bit SRA or SRL of 1.  Lower this to an RRX expr.
2217  SDValue Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, N->getOperand(0),
2218                             DAG.getConstant(0, MVT::i32));
2219  SDValue Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, N->getOperand(0),
2220                             DAG.getConstant(1, MVT::i32));
2221
2222  // First, build a SRA_FLAG/SRL_FLAG op, which shifts the top part by one and
2223  // captures the result into a carry flag.
2224  unsigned Opc = N->getOpcode() == ISD::SRL ? ARMISD::SRL_FLAG:ARMISD::SRA_FLAG;
2225  Hi = DAG.getNode(Opc, dl, DAG.getVTList(MVT::i32, MVT::Flag), &Hi, 1);
2226
2227  // The low part is an ARMISD::RRX operand, which shifts the carry in.
2228  Lo = DAG.getNode(ARMISD::RRX, dl, MVT::i32, Lo, Hi.getValue(1));
2229
2230  // Merge the pieces into a single i64 value.
2231 return DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, Lo, Hi);
2232}
2233
2234static SDValue LowerVSETCC(SDValue Op, SelectionDAG &DAG) {
2235  SDValue TmpOp0, TmpOp1;
2236  bool Invert = false;
2237  bool Swap = false;
2238  unsigned Opc = 0;
2239
2240  SDValue Op0 = Op.getOperand(0);
2241  SDValue Op1 = Op.getOperand(1);
2242  SDValue CC = Op.getOperand(2);
2243  EVT VT = Op.getValueType();
2244  ISD::CondCode SetCCOpcode = cast<CondCodeSDNode>(CC)->get();
2245  DebugLoc dl = Op.getDebugLoc();
2246
2247  if (Op.getOperand(1).getValueType().isFloatingPoint()) {
2248    switch (SetCCOpcode) {
2249    default: llvm_unreachable("Illegal FP comparison"); break;
2250    case ISD::SETUNE:
2251    case ISD::SETNE:  Invert = true; // Fallthrough
2252    case ISD::SETOEQ:
2253    case ISD::SETEQ:  Opc = ARMISD::VCEQ; break;
2254    case ISD::SETOLT:
2255    case ISD::SETLT: Swap = true; // Fallthrough
2256    case ISD::SETOGT:
2257    case ISD::SETGT:  Opc = ARMISD::VCGT; break;
2258    case ISD::SETOLE:
2259    case ISD::SETLE:  Swap = true; // Fallthrough
2260    case ISD::SETOGE:
2261    case ISD::SETGE: Opc = ARMISD::VCGE; break;
2262    case ISD::SETUGE: Swap = true; // Fallthrough
2263    case ISD::SETULE: Invert = true; Opc = ARMISD::VCGT; break;
2264    case ISD::SETUGT: Swap = true; // Fallthrough
2265    case ISD::SETULT: Invert = true; Opc = ARMISD::VCGE; break;
2266    case ISD::SETUEQ: Invert = true; // Fallthrough
2267    case ISD::SETONE:
2268      // Expand this to (OLT | OGT).
2269      TmpOp0 = Op0;
2270      TmpOp1 = Op1;
2271      Opc = ISD::OR;
2272      Op0 = DAG.getNode(ARMISD::VCGT, dl, VT, TmpOp1, TmpOp0);
2273      Op1 = DAG.getNode(ARMISD::VCGT, dl, VT, TmpOp0, TmpOp1);
2274      break;
2275    case ISD::SETUO: Invert = true; // Fallthrough
2276    case ISD::SETO:
2277      // Expand this to (OLT | OGE).
2278      TmpOp0 = Op0;
2279      TmpOp1 = Op1;
2280      Opc = ISD::OR;
2281      Op0 = DAG.getNode(ARMISD::VCGT, dl, VT, TmpOp1, TmpOp0);
2282      Op1 = DAG.getNode(ARMISD::VCGE, dl, VT, TmpOp0, TmpOp1);
2283      break;
2284    }
2285  } else {
2286    // Integer comparisons.
2287    switch (SetCCOpcode) {
2288    default: llvm_unreachable("Illegal integer comparison"); break;
2289    case ISD::SETNE:  Invert = true;
2290    case ISD::SETEQ:  Opc = ARMISD::VCEQ; break;
2291    case ISD::SETLT:  Swap = true;
2292    case ISD::SETGT:  Opc = ARMISD::VCGT; break;
2293    case ISD::SETLE:  Swap = true;
2294    case ISD::SETGE:  Opc = ARMISD::VCGE; break;
2295    case ISD::SETULT: Swap = true;
2296    case ISD::SETUGT: Opc = ARMISD::VCGTU; break;
2297    case ISD::SETULE: Swap = true;
2298    case ISD::SETUGE: Opc = ARMISD::VCGEU; break;
2299    }
2300
2301    // Detect VTST (Vector Test Bits) = icmp ne (and (op0, op1), zero).
2302    if (Opc == ARMISD::VCEQ) {
2303
2304      SDValue AndOp;
2305      if (ISD::isBuildVectorAllZeros(Op1.getNode()))
2306        AndOp = Op0;
2307      else if (ISD::isBuildVectorAllZeros(Op0.getNode()))
2308        AndOp = Op1;
2309
2310      // Ignore bitconvert.
2311      if (AndOp.getNode() && AndOp.getOpcode() == ISD::BIT_CONVERT)
2312        AndOp = AndOp.getOperand(0);
2313
2314      if (AndOp.getNode() && AndOp.getOpcode() == ISD::AND) {
2315        Opc = ARMISD::VTST;
2316        Op0 = DAG.getNode(ISD::BIT_CONVERT, dl, VT, AndOp.getOperand(0));
2317        Op1 = DAG.getNode(ISD::BIT_CONVERT, dl, VT, AndOp.getOperand(1));
2318        Invert = !Invert;
2319      }
2320    }
2321  }
2322
2323  if (Swap)
2324    std::swap(Op0, Op1);
2325
2326  SDValue Result = DAG.getNode(Opc, dl, VT, Op0, Op1);
2327
2328  if (Invert)
2329    Result = DAG.getNOT(dl, Result, VT);
2330
2331  return Result;
2332}
2333
2334/// isVMOVSplat - Check if the specified splat value corresponds to an immediate
2335/// VMOV instruction, and if so, return the constant being splatted.
2336static SDValue isVMOVSplat(uint64_t SplatBits, uint64_t SplatUndef,
2337                           unsigned SplatBitSize, SelectionDAG &DAG) {
2338  switch (SplatBitSize) {
2339  case 8:
2340    // Any 1-byte value is OK.
2341    assert((SplatBits & ~0xff) == 0 && "one byte splat value is too big");
2342    return DAG.getTargetConstant(SplatBits, MVT::i8);
2343
2344  case 16:
2345    // NEON's 16-bit VMOV supports splat values where only one byte is nonzero.
2346    if ((SplatBits & ~0xff) == 0 ||
2347        (SplatBits & ~0xff00) == 0)
2348      return DAG.getTargetConstant(SplatBits, MVT::i16);
2349    break;
2350
2351  case 32:
2352    // NEON's 32-bit VMOV supports splat values where:
2353    // * only one byte is nonzero, or
2354    // * the least significant byte is 0xff and the second byte is nonzero, or
2355    // * the least significant 2 bytes are 0xff and the third is nonzero.
2356    if ((SplatBits & ~0xff) == 0 ||
2357        (SplatBits & ~0xff00) == 0 ||
2358        (SplatBits & ~0xff0000) == 0 ||
2359        (SplatBits & ~0xff000000) == 0)
2360      return DAG.getTargetConstant(SplatBits, MVT::i32);
2361
2362    if ((SplatBits & ~0xffff) == 0 &&
2363        ((SplatBits | SplatUndef) & 0xff) == 0xff)
2364      return DAG.getTargetConstant(SplatBits | 0xff, MVT::i32);
2365
2366    if ((SplatBits & ~0xffffff) == 0 &&
2367        ((SplatBits | SplatUndef) & 0xffff) == 0xffff)
2368      return DAG.getTargetConstant(SplatBits | 0xffff, MVT::i32);
2369
2370    // Note: there are a few 32-bit splat values (specifically: 00ffff00,
2371    // ff000000, ff0000ff, and ffff00ff) that are valid for VMOV.I64 but not
2372    // VMOV.I32.  A (very) minor optimization would be to replicate the value
2373    // and fall through here to test for a valid 64-bit splat.  But, then the
2374    // caller would also need to check and handle the change in size.
2375    break;
2376
2377  case 64: {
2378    // NEON has a 64-bit VMOV splat where each byte is either 0 or 0xff.
2379    uint64_t BitMask = 0xff;
2380    uint64_t Val = 0;
2381    for (int ByteNum = 0; ByteNum < 8; ++ByteNum) {
2382      if (((SplatBits | SplatUndef) & BitMask) == BitMask)
2383        Val |= BitMask;
2384      else if ((SplatBits & BitMask) != 0)
2385        return SDValue();
2386      BitMask <<= 8;
2387    }
2388    return DAG.getTargetConstant(Val, MVT::i64);
2389  }
2390
2391  default:
2392    llvm_unreachable("unexpected size for isVMOVSplat");
2393    break;
2394  }
2395
2396  return SDValue();
2397}
2398
2399/// getVMOVImm - If this is a build_vector of constants which can be
2400/// formed by using a VMOV instruction of the specified element size,
2401/// return the constant being splatted.  The ByteSize field indicates the
2402/// number of bytes of each element [1248].
2403SDValue ARM::getVMOVImm(SDNode *N, unsigned ByteSize, SelectionDAG &DAG) {
2404  BuildVectorSDNode *BVN = dyn_cast<BuildVectorSDNode>(N);
2405  APInt SplatBits, SplatUndef;
2406  unsigned SplatBitSize;
2407  bool HasAnyUndefs;
2408  if (! BVN || ! BVN->isConstantSplat(SplatBits, SplatUndef, SplatBitSize,
2409                                      HasAnyUndefs, ByteSize * 8))
2410    return SDValue();
2411
2412  if (SplatBitSize > ByteSize * 8)
2413    return SDValue();
2414
2415  return isVMOVSplat(SplatBits.getZExtValue(), SplatUndef.getZExtValue(),
2416                     SplatBitSize, DAG);
2417}
2418
2419static bool isVEXTMask(const SmallVectorImpl<int> &M, EVT VT,
2420                       bool &ReverseVEXT, unsigned &Imm) {
2421  unsigned NumElts = VT.getVectorNumElements();
2422  ReverseVEXT = false;
2423  Imm = M[0];
2424
2425  // If this is a VEXT shuffle, the immediate value is the index of the first
2426  // element.  The other shuffle indices must be the successive elements after
2427  // the first one.
2428  unsigned ExpectedElt = Imm;
2429  for (unsigned i = 1; i < NumElts; ++i) {
2430    // Increment the expected index.  If it wraps around, it may still be
2431    // a VEXT but the source vectors must be swapped.
2432    ExpectedElt += 1;
2433    if (ExpectedElt == NumElts * 2) {
2434      ExpectedElt = 0;
2435      ReverseVEXT = true;
2436    }
2437
2438    if (ExpectedElt != static_cast<unsigned>(M[i]))
2439      return false;
2440  }
2441
2442  // Adjust the index value if the source operands will be swapped.
2443  if (ReverseVEXT)
2444    Imm -= NumElts;
2445
2446  return true;
2447}
2448
2449/// isVREVMask - Check if a vector shuffle corresponds to a VREV
2450/// instruction with the specified blocksize.  (The order of the elements
2451/// within each block of the vector is reversed.)
2452static bool isVREVMask(const SmallVectorImpl<int> &M, EVT VT,
2453                       unsigned BlockSize) {
2454  assert((BlockSize==16 || BlockSize==32 || BlockSize==64) &&
2455         "Only possible block sizes for VREV are: 16, 32, 64");
2456
2457  unsigned NumElts = VT.getVectorNumElements();
2458  unsigned EltSz = VT.getVectorElementType().getSizeInBits();
2459  unsigned BlockElts = M[0] + 1;
2460
2461  if (BlockSize <= EltSz || BlockSize != BlockElts * EltSz)
2462    return false;
2463
2464  for (unsigned i = 0; i < NumElts; ++i) {
2465    if ((unsigned) M[i] !=
2466        (i - i%BlockElts) + (BlockElts - 1 - i%BlockElts))
2467      return false;
2468  }
2469
2470  return true;
2471}
2472
2473static bool isVTRNMask(const SmallVectorImpl<int> &M, EVT VT,
2474                       unsigned &WhichResult) {
2475  unsigned NumElts = VT.getVectorNumElements();
2476  WhichResult = (M[0] == 0 ? 0 : 1);
2477  for (unsigned i = 0; i < NumElts; i += 2) {
2478    if ((unsigned) M[i] != i + WhichResult ||
2479        (unsigned) M[i+1] != i + NumElts + WhichResult)
2480      return false;
2481  }
2482  return true;
2483}
2484
2485static bool isVUZPMask(const SmallVectorImpl<int> &M, EVT VT,
2486                       unsigned &WhichResult) {
2487  unsigned NumElts = VT.getVectorNumElements();
2488  WhichResult = (M[0] == 0 ? 0 : 1);
2489  for (unsigned i = 0; i != NumElts; ++i) {
2490    if ((unsigned) M[i] != 2 * i + WhichResult)
2491      return false;
2492  }
2493
2494  // VUZP.32 for 64-bit vectors is a pseudo-instruction alias for VTRN.32.
2495  if (VT.is64BitVector() && VT.getVectorElementType().getSizeInBits() == 32)
2496    return false;
2497
2498  return true;
2499}
2500
2501static bool isVZIPMask(const SmallVectorImpl<int> &M, EVT VT,
2502                       unsigned &WhichResult) {
2503  unsigned NumElts = VT.getVectorNumElements();
2504  WhichResult = (M[0] == 0 ? 0 : 1);
2505  unsigned Idx = WhichResult * NumElts / 2;
2506  for (unsigned i = 0; i != NumElts; i += 2) {
2507    if ((unsigned) M[i] != Idx ||
2508        (unsigned) M[i+1] != Idx + NumElts)
2509      return false;
2510    Idx += 1;
2511  }
2512
2513  // VZIP.32 for 64-bit vectors is a pseudo-instruction alias for VTRN.32.
2514  if (VT.is64BitVector() && VT.getVectorElementType().getSizeInBits() == 32)
2515    return false;
2516
2517  return true;
2518}
2519
2520static SDValue BuildSplat(SDValue Val, EVT VT, SelectionDAG &DAG, DebugLoc dl) {
2521  // Canonicalize all-zeros and all-ones vectors.
2522  ConstantSDNode *ConstVal = cast<ConstantSDNode>(Val.getNode());
2523  if (ConstVal->isNullValue())
2524    return getZeroVector(VT, DAG, dl);
2525  if (ConstVal->isAllOnesValue())
2526    return getOnesVector(VT, DAG, dl);
2527
2528  EVT CanonicalVT;
2529  if (VT.is64BitVector()) {
2530    switch (Val.getValueType().getSizeInBits()) {
2531    case 8:  CanonicalVT = MVT::v8i8; break;
2532    case 16: CanonicalVT = MVT::v4i16; break;
2533    case 32: CanonicalVT = MVT::v2i32; break;
2534    case 64: CanonicalVT = MVT::v1i64; break;
2535    default: llvm_unreachable("unexpected splat element type"); break;
2536    }
2537  } else {
2538    assert(VT.is128BitVector() && "unknown splat vector size");
2539    switch (Val.getValueType().getSizeInBits()) {
2540    case 8:  CanonicalVT = MVT::v16i8; break;
2541    case 16: CanonicalVT = MVT::v8i16; break;
2542    case 32: CanonicalVT = MVT::v4i32; break;
2543    case 64: CanonicalVT = MVT::v2i64; break;
2544    default: llvm_unreachable("unexpected splat element type"); break;
2545    }
2546  }
2547
2548  // Build a canonical splat for this value.
2549  SmallVector<SDValue, 8> Ops;
2550  Ops.assign(CanonicalVT.getVectorNumElements(), Val);
2551  SDValue Res = DAG.getNode(ISD::BUILD_VECTOR, dl, CanonicalVT, &Ops[0],
2552                            Ops.size());
2553  return DAG.getNode(ISD::BIT_CONVERT, dl, VT, Res);
2554}
2555
2556// If this is a case we can't handle, return null and let the default
2557// expansion code take care of it.
2558static SDValue LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG) {
2559  BuildVectorSDNode *BVN = cast<BuildVectorSDNode>(Op.getNode());
2560  DebugLoc dl = Op.getDebugLoc();
2561  EVT VT = Op.getValueType();
2562
2563  APInt SplatBits, SplatUndef;
2564  unsigned SplatBitSize;
2565  bool HasAnyUndefs;
2566  if (BVN->isConstantSplat(SplatBits, SplatUndef, SplatBitSize, HasAnyUndefs)) {
2567    if (SplatBitSize <= 64) {
2568      SDValue Val = isVMOVSplat(SplatBits.getZExtValue(),
2569                                SplatUndef.getZExtValue(), SplatBitSize, DAG);
2570      if (Val.getNode())
2571        return BuildSplat(Val, VT, DAG, dl);
2572    }
2573  }
2574
2575  // If there are only 2 elements in a 128-bit vector, insert them into an
2576  // undef vector.  This handles the common case for 128-bit vector argument
2577  // passing, where the insertions should be translated to subreg accesses
2578  // with no real instructions.
2579  if (VT.is128BitVector() && Op.getNumOperands() == 2) {
2580    SDValue Val = DAG.getUNDEF(VT);
2581    SDValue Op0 = Op.getOperand(0);
2582    SDValue Op1 = Op.getOperand(1);
2583    if (Op0.getOpcode() != ISD::UNDEF)
2584      Val = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, Val, Op0,
2585                        DAG.getIntPtrConstant(0));
2586    if (Op1.getOpcode() != ISD::UNDEF)
2587      Val = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, Val, Op1,
2588                        DAG.getIntPtrConstant(1));
2589    return Val;
2590  }
2591
2592  return SDValue();
2593}
2594
2595/// isShuffleMaskLegal - Targets can use this to indicate that they only
2596/// support *some* VECTOR_SHUFFLE operations, those with specific masks.
2597/// By default, if a target supports the VECTOR_SHUFFLE node, all mask values
2598/// are assumed to be legal.
2599bool
2600ARMTargetLowering::isShuffleMaskLegal(const SmallVectorImpl<int> &M,
2601                                      EVT VT) const {
2602  if (VT.getVectorNumElements() == 4 &&
2603      (VT.is128BitVector() || VT.is64BitVector())) {
2604    unsigned PFIndexes[4];
2605    for (unsigned i = 0; i != 4; ++i) {
2606      if (M[i] < 0)
2607        PFIndexes[i] = 8;
2608      else
2609        PFIndexes[i] = M[i];
2610    }
2611
2612    // Compute the index in the perfect shuffle table.
2613    unsigned PFTableIndex =
2614      PFIndexes[0]*9*9*9+PFIndexes[1]*9*9+PFIndexes[2]*9+PFIndexes[3];
2615    unsigned PFEntry = PerfectShuffleTable[PFTableIndex];
2616    unsigned Cost = (PFEntry >> 30);
2617
2618    if (Cost <= 4)
2619      return true;
2620  }
2621
2622  bool ReverseVEXT;
2623  unsigned Imm, WhichResult;
2624
2625  return (ShuffleVectorSDNode::isSplatMask(&M[0], VT) ||
2626          isVREVMask(M, VT, 64) ||
2627          isVREVMask(M, VT, 32) ||
2628          isVREVMask(M, VT, 16) ||
2629          isVEXTMask(M, VT, ReverseVEXT, Imm) ||
2630          isVTRNMask(M, VT, WhichResult) ||
2631          isVUZPMask(M, VT, WhichResult) ||
2632          isVZIPMask(M, VT, WhichResult));
2633}
2634
2635/// GeneratePerfectShuffle - Given an entry in the perfect-shuffle table, emit
2636/// the specified operations to build the shuffle.
2637static SDValue GeneratePerfectShuffle(unsigned PFEntry, SDValue LHS,
2638                                      SDValue RHS, SelectionDAG &DAG,
2639                                      DebugLoc dl) {
2640  unsigned OpNum = (PFEntry >> 26) & 0x0F;
2641  unsigned LHSID = (PFEntry >> 13) & ((1 << 13)-1);
2642  unsigned RHSID = (PFEntry >>  0) & ((1 << 13)-1);
2643
2644  enum {
2645    OP_COPY = 0, // Copy, used for things like <u,u,u,3> to say it is <0,1,2,3>
2646    OP_VREV,
2647    OP_VDUP0,
2648    OP_VDUP1,
2649    OP_VDUP2,
2650    OP_VDUP3,
2651    OP_VEXT1,
2652    OP_VEXT2,
2653    OP_VEXT3,
2654    OP_VUZPL, // VUZP, left result
2655    OP_VUZPR, // VUZP, right result
2656    OP_VZIPL, // VZIP, left result
2657    OP_VZIPR, // VZIP, right result
2658    OP_VTRNL, // VTRN, left result
2659    OP_VTRNR  // VTRN, right result
2660  };
2661
2662  if (OpNum == OP_COPY) {
2663    if (LHSID == (1*9+2)*9+3) return LHS;
2664    assert(LHSID == ((4*9+5)*9+6)*9+7 && "Illegal OP_COPY!");
2665    return RHS;
2666  }
2667
2668  SDValue OpLHS, OpRHS;
2669  OpLHS = GeneratePerfectShuffle(PerfectShuffleTable[LHSID], LHS, RHS, DAG, dl);
2670  OpRHS = GeneratePerfectShuffle(PerfectShuffleTable[RHSID], LHS, RHS, DAG, dl);
2671  EVT VT = OpLHS.getValueType();
2672
2673  switch (OpNum) {
2674  default: llvm_unreachable("Unknown shuffle opcode!");
2675  case OP_VREV:
2676    return DAG.getNode(ARMISD::VREV64, dl, VT, OpLHS);
2677  case OP_VDUP0:
2678  case OP_VDUP1:
2679  case OP_VDUP2:
2680  case OP_VDUP3:
2681    return DAG.getNode(ARMISD::VDUPLANE, dl, VT,
2682                       OpLHS, DAG.getConstant(OpNum-OP_VDUP0, MVT::i32));
2683  case OP_VEXT1:
2684  case OP_VEXT2:
2685  case OP_VEXT3:
2686    return DAG.getNode(ARMISD::VEXT, dl, VT,
2687                       OpLHS, OpRHS,
2688                       DAG.getConstant(OpNum-OP_VEXT1+1, MVT::i32));
2689  case OP_VUZPL:
2690  case OP_VUZPR:
2691    return DAG.getNode(ARMISD::VUZP, dl, DAG.getVTList(VT, VT),
2692                       OpLHS, OpRHS).getValue(OpNum-OP_VUZPL);
2693  case OP_VZIPL:
2694  case OP_VZIPR:
2695    return DAG.getNode(ARMISD::VZIP, dl, DAG.getVTList(VT, VT),
2696                       OpLHS, OpRHS).getValue(OpNum-OP_VZIPL);
2697  case OP_VTRNL:
2698  case OP_VTRNR:
2699    return DAG.getNode(ARMISD::VTRN, dl, DAG.getVTList(VT, VT),
2700                       OpLHS, OpRHS).getValue(OpNum-OP_VTRNL);
2701  }
2702}
2703
2704static SDValue LowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG) {
2705  SDValue V1 = Op.getOperand(0);
2706  SDValue V2 = Op.getOperand(1);
2707  DebugLoc dl = Op.getDebugLoc();
2708  EVT VT = Op.getValueType();
2709  ShuffleVectorSDNode *SVN = cast<ShuffleVectorSDNode>(Op.getNode());
2710  SmallVector<int, 8> ShuffleMask;
2711
2712  // Convert shuffles that are directly supported on NEON to target-specific
2713  // DAG nodes, instead of keeping them as shuffles and matching them again
2714  // during code selection.  This is more efficient and avoids the possibility
2715  // of inconsistencies between legalization and selection.
2716  // FIXME: floating-point vectors should be canonicalized to integer vectors
2717  // of the same time so that they get CSEd properly.
2718  SVN->getMask(ShuffleMask);
2719
2720  if (ShuffleVectorSDNode::isSplatMask(&ShuffleMask[0], VT)) {
2721    int Lane = SVN->getSplatIndex();
2722    if (Lane == 0 && V1.getOpcode() == ISD::SCALAR_TO_VECTOR) {
2723      return DAG.getNode(ARMISD::VDUP, dl, VT, V1.getOperand(0));
2724    }
2725    return DAG.getNode(ARMISD::VDUPLANE, dl, VT, V1,
2726                       DAG.getConstant(Lane, MVT::i32));
2727  }
2728
2729  bool ReverseVEXT;
2730  unsigned Imm;
2731  if (isVEXTMask(ShuffleMask, VT, ReverseVEXT, Imm)) {
2732    if (ReverseVEXT)
2733      std::swap(V1, V2);
2734    return DAG.getNode(ARMISD::VEXT, dl, VT, V1, V2,
2735                       DAG.getConstant(Imm, MVT::i32));
2736  }
2737
2738  if (isVREVMask(ShuffleMask, VT, 64))
2739    return DAG.getNode(ARMISD::VREV64, dl, VT, V1);
2740  if (isVREVMask(ShuffleMask, VT, 32))
2741    return DAG.getNode(ARMISD::VREV32, dl, VT, V1);
2742  if (isVREVMask(ShuffleMask, VT, 16))
2743    return DAG.getNode(ARMISD::VREV16, dl, VT, V1);
2744
2745  // Check for Neon shuffles that modify both input vectors in place.
2746  // If both results are used, i.e., if there are two shuffles with the same
2747  // source operands and with masks corresponding to both results of one of
2748  // these operations, DAG memoization will ensure that a single node is
2749  // used for both shuffles.
2750  unsigned WhichResult;
2751  if (isVTRNMask(ShuffleMask, VT, WhichResult))
2752    return DAG.getNode(ARMISD::VTRN, dl, DAG.getVTList(VT, VT),
2753                       V1, V2).getValue(WhichResult);
2754  if (isVUZPMask(ShuffleMask, VT, WhichResult))
2755    return DAG.getNode(ARMISD::VUZP, dl, DAG.getVTList(VT, VT),
2756                       V1, V2).getValue(WhichResult);
2757  if (isVZIPMask(ShuffleMask, VT, WhichResult))
2758    return DAG.getNode(ARMISD::VZIP, dl, DAG.getVTList(VT, VT),
2759                       V1, V2).getValue(WhichResult);
2760
2761  // If the shuffle is not directly supported and it has 4 elements, use
2762  // the PerfectShuffle-generated table to synthesize it from other shuffles.
2763  if (VT.getVectorNumElements() == 4 &&
2764      (VT.is128BitVector() || VT.is64BitVector())) {
2765    unsigned PFIndexes[4];
2766    for (unsigned i = 0; i != 4; ++i) {
2767      if (ShuffleMask[i] < 0)
2768        PFIndexes[i] = 8;
2769      else
2770        PFIndexes[i] = ShuffleMask[i];
2771    }
2772
2773    // Compute the index in the perfect shuffle table.
2774    unsigned PFTableIndex =
2775      PFIndexes[0]*9*9*9+PFIndexes[1]*9*9+PFIndexes[2]*9+PFIndexes[3];
2776
2777    unsigned PFEntry = PerfectShuffleTable[PFTableIndex];
2778    unsigned Cost = (PFEntry >> 30);
2779
2780    if (Cost <= 4)
2781      return GeneratePerfectShuffle(PFEntry, V1, V2, DAG, dl);
2782  }
2783
2784  return SDValue();
2785}
2786
2787static SDValue LowerEXTRACT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) {
2788  EVT VT = Op.getValueType();
2789  DebugLoc dl = Op.getDebugLoc();
2790  SDValue Vec = Op.getOperand(0);
2791  SDValue Lane = Op.getOperand(1);
2792
2793  // FIXME: This is invalid for 8 and 16-bit elements - the information about
2794  // sign / zero extension is lost!
2795  Op = DAG.getNode(ARMISD::VGETLANEu, dl, MVT::i32, Vec, Lane);
2796  Op = DAG.getNode(ISD::AssertZext, dl, MVT::i32, Op, DAG.getValueType(VT));
2797
2798  if (VT.bitsLT(MVT::i32))
2799    Op = DAG.getNode(ISD::TRUNCATE, dl, VT, Op);
2800  else if (VT.bitsGT(MVT::i32))
2801    Op = DAG.getNode(ISD::ANY_EXTEND, dl, VT, Op);
2802
2803  return Op;
2804}
2805
2806static SDValue LowerCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG) {
2807  // The only time a CONCAT_VECTORS operation can have legal types is when
2808  // two 64-bit vectors are concatenated to a 128-bit vector.
2809  assert(Op.getValueType().is128BitVector() && Op.getNumOperands() == 2 &&
2810         "unexpected CONCAT_VECTORS");
2811  DebugLoc dl = Op.getDebugLoc();
2812  SDValue Val = DAG.getUNDEF(MVT::v2f64);
2813  SDValue Op0 = Op.getOperand(0);
2814  SDValue Op1 = Op.getOperand(1);
2815  if (Op0.getOpcode() != ISD::UNDEF)
2816    Val = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v2f64, Val,
2817                      DAG.getNode(ISD::BIT_CONVERT, dl, MVT::f64, Op0),
2818                      DAG.getIntPtrConstant(0));
2819  if (Op1.getOpcode() != ISD::UNDEF)
2820    Val = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v2f64, Val,
2821                      DAG.getNode(ISD::BIT_CONVERT, dl, MVT::f64, Op1),
2822                      DAG.getIntPtrConstant(1));
2823  return DAG.getNode(ISD::BIT_CONVERT, dl, Op.getValueType(), Val);
2824}
2825
2826SDValue ARMTargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) {
2827  switch (Op.getOpcode()) {
2828  default: llvm_unreachable("Don't know how to custom lower this!");
2829  case ISD::ConstantPool:  return LowerConstantPool(Op, DAG);
2830  case ISD::GlobalAddress:
2831    return Subtarget->isTargetDarwin() ? LowerGlobalAddressDarwin(Op, DAG) :
2832      LowerGlobalAddressELF(Op, DAG);
2833  case ISD::GlobalTLSAddress:   return LowerGlobalTLSAddress(Op, DAG);
2834  case ISD::SELECT_CC:     return LowerSELECT_CC(Op, DAG, Subtarget);
2835  case ISD::BR_CC:         return LowerBR_CC(Op, DAG, Subtarget);
2836  case ISD::BR_JT:         return LowerBR_JT(Op, DAG);
2837  case ISD::DYNAMIC_STACKALLOC: return LowerDYNAMIC_STACKALLOC(Op, DAG);
2838  case ISD::VASTART:       return LowerVASTART(Op, DAG, VarArgsFrameIndex);
2839  case ISD::SINT_TO_FP:
2840  case ISD::UINT_TO_FP:    return LowerINT_TO_FP(Op, DAG);
2841  case ISD::FP_TO_SINT:
2842  case ISD::FP_TO_UINT:    return LowerFP_TO_INT(Op, DAG);
2843  case ISD::FCOPYSIGN:     return LowerFCOPYSIGN(Op, DAG);
2844  case ISD::RETURNADDR:    break;
2845  case ISD::FRAMEADDR:     return LowerFRAMEADDR(Op, DAG);
2846  case ISD::GLOBAL_OFFSET_TABLE: return LowerGLOBAL_OFFSET_TABLE(Op, DAG);
2847  case ISD::INTRINSIC_VOID:
2848  case ISD::INTRINSIC_W_CHAIN: return LowerINTRINSIC_W_CHAIN(Op, DAG);
2849  case ISD::INTRINSIC_WO_CHAIN: return LowerINTRINSIC_WO_CHAIN(Op, DAG);
2850  case ISD::BIT_CONVERT:   return ExpandBIT_CONVERT(Op.getNode(), DAG);
2851  case ISD::SHL:
2852  case ISD::SRL:
2853  case ISD::SRA:           return LowerShift(Op.getNode(), DAG, Subtarget);
2854  case ISD::VSETCC:        return LowerVSETCC(Op, DAG);
2855  case ISD::BUILD_VECTOR:  return LowerBUILD_VECTOR(Op, DAG);
2856  case ISD::VECTOR_SHUFFLE: return LowerVECTOR_SHUFFLE(Op, DAG);
2857  case ISD::EXTRACT_VECTOR_ELT: return LowerEXTRACT_VECTOR_ELT(Op, DAG);
2858  case ISD::CONCAT_VECTORS: return LowerCONCAT_VECTORS(Op, DAG);
2859  }
2860  return SDValue();
2861}
2862
2863/// ReplaceNodeResults - Replace the results of node with an illegal result
2864/// type with new values built out of custom code.
2865void ARMTargetLowering::ReplaceNodeResults(SDNode *N,
2866                                           SmallVectorImpl<SDValue>&Results,
2867                                           SelectionDAG &DAG) {
2868  switch (N->getOpcode()) {
2869  default:
2870    llvm_unreachable("Don't know how to custom expand this!");
2871    return;
2872  case ISD::BIT_CONVERT:
2873    Results.push_back(ExpandBIT_CONVERT(N, DAG));
2874    return;
2875  case ISD::SRL:
2876  case ISD::SRA: {
2877    SDValue Res = LowerShift(N, DAG, Subtarget);
2878    if (Res.getNode())
2879      Results.push_back(Res);
2880    return;
2881  }
2882  }
2883}
2884
2885//===----------------------------------------------------------------------===//
2886//                           ARM Scheduler Hooks
2887//===----------------------------------------------------------------------===//
2888
2889MachineBasicBlock *
2890ARMTargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
2891                                               MachineBasicBlock *BB,
2892                   DenseMap<MachineBasicBlock*, MachineBasicBlock*> *EM) const {
2893  const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
2894  DebugLoc dl = MI->getDebugLoc();
2895  switch (MI->getOpcode()) {
2896  default:
2897    llvm_unreachable("Unexpected instr type to insert");
2898  case ARM::tMOVCCr_pseudo: {
2899    // To "insert" a SELECT_CC instruction, we actually have to insert the
2900    // diamond control-flow pattern.  The incoming instruction knows the
2901    // destination vreg to set, the condition code register to branch on, the
2902    // true/false values to select between, and a branch opcode to use.
2903    const BasicBlock *LLVM_BB = BB->getBasicBlock();
2904    MachineFunction::iterator It = BB;
2905    ++It;
2906
2907    //  thisMBB:
2908    //  ...
2909    //   TrueVal = ...
2910    //   cmpTY ccX, r1, r2
2911    //   bCC copy1MBB
2912    //   fallthrough --> copy0MBB
2913    MachineBasicBlock *thisMBB  = BB;
2914    MachineFunction *F = BB->getParent();
2915    MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB);
2916    MachineBasicBlock *sinkMBB  = F->CreateMachineBasicBlock(LLVM_BB);
2917    BuildMI(BB, dl, TII->get(ARM::tBcc)).addMBB(sinkMBB)
2918      .addImm(MI->getOperand(3).getImm()).addReg(MI->getOperand(4).getReg());
2919    F->insert(It, copy0MBB);
2920    F->insert(It, sinkMBB);
2921    // Update machine-CFG edges by first adding all successors of the current
2922    // block to the new block which will contain the Phi node for the select.
2923    for(MachineBasicBlock::succ_iterator i = BB->succ_begin(),
2924        e = BB->succ_end(); i != e; ++i)
2925      sinkMBB->addSuccessor(*i);
2926    // Next, remove all successors of the current block, and add the true
2927    // and fallthrough blocks as its successors.
2928    while(!BB->succ_empty())
2929      BB->removeSuccessor(BB->succ_begin());
2930    BB->addSuccessor(copy0MBB);
2931    BB->addSuccessor(sinkMBB);
2932
2933    //  copy0MBB:
2934    //   %FalseValue = ...
2935    //   # fallthrough to sinkMBB
2936    BB = copy0MBB;
2937
2938    // Update machine-CFG edges
2939    BB->addSuccessor(sinkMBB);
2940
2941    //  sinkMBB:
2942    //   %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ]
2943    //  ...
2944    BB = sinkMBB;
2945    BuildMI(BB, dl, TII->get(ARM::PHI), MI->getOperand(0).getReg())
2946      .addReg(MI->getOperand(1).getReg()).addMBB(copy0MBB)
2947      .addReg(MI->getOperand(2).getReg()).addMBB(thisMBB);
2948
2949    F->DeleteMachineInstr(MI);   // The pseudo instruction is gone now.
2950    return BB;
2951  }
2952
2953  case ARM::tANDsp:
2954  case ARM::tADDspr_:
2955  case ARM::tSUBspi_:
2956  case ARM::t2SUBrSPi_:
2957  case ARM::t2SUBrSPi12_:
2958  case ARM::t2SUBrSPs_: {
2959    MachineFunction *MF = BB->getParent();
2960    unsigned DstReg = MI->getOperand(0).getReg();
2961    unsigned SrcReg = MI->getOperand(1).getReg();
2962    bool DstIsDead = MI->getOperand(0).isDead();
2963    bool SrcIsKill = MI->getOperand(1).isKill();
2964
2965    if (SrcReg != ARM::SP) {
2966      // Copy the source to SP from virtual register.
2967      const TargetRegisterClass *RC = MF->getRegInfo().getRegClass(SrcReg);
2968      unsigned CopyOpc = (RC == ARM::tGPRRegisterClass)
2969        ? ARM::tMOVtgpr2gpr : ARM::tMOVgpr2gpr;
2970      BuildMI(BB, dl, TII->get(CopyOpc), ARM::SP)
2971        .addReg(SrcReg, getKillRegState(SrcIsKill));
2972    }
2973
2974    unsigned OpOpc = 0;
2975    bool NeedPred = false, NeedCC = false, NeedOp3 = false;
2976    switch (MI->getOpcode()) {
2977    default:
2978      llvm_unreachable("Unexpected pseudo instruction!");
2979    case ARM::tANDsp:
2980      OpOpc = ARM::tAND;
2981      NeedPred = true;
2982      break;
2983    case ARM::tADDspr_:
2984      OpOpc = ARM::tADDspr;
2985      break;
2986    case ARM::tSUBspi_:
2987      OpOpc = ARM::tSUBspi;
2988      break;
2989    case ARM::t2SUBrSPi_:
2990      OpOpc = ARM::t2SUBrSPi;
2991      NeedPred = true; NeedCC = true;
2992      break;
2993    case ARM::t2SUBrSPi12_:
2994      OpOpc = ARM::t2SUBrSPi12;
2995      NeedPred = true;
2996      break;
2997    case ARM::t2SUBrSPs_:
2998      OpOpc = ARM::t2SUBrSPs;
2999      NeedPred = true; NeedCC = true; NeedOp3 = true;
3000      break;
3001    }
3002    MachineInstrBuilder MIB = BuildMI(BB, dl, TII->get(OpOpc), ARM::SP);
3003    if (OpOpc == ARM::tAND)
3004      AddDefaultT1CC(MIB);
3005    MIB.addReg(ARM::SP);
3006    MIB.addOperand(MI->getOperand(2));
3007    if (NeedOp3)
3008      MIB.addOperand(MI->getOperand(3));
3009    if (NeedPred)
3010      AddDefaultPred(MIB);
3011    if (NeedCC)
3012      AddDefaultCC(MIB);
3013
3014    // Copy the result from SP to virtual register.
3015    const TargetRegisterClass *RC = MF->getRegInfo().getRegClass(DstReg);
3016    unsigned CopyOpc = (RC == ARM::tGPRRegisterClass)
3017      ? ARM::tMOVgpr2tgpr : ARM::tMOVgpr2gpr;
3018    BuildMI(BB, dl, TII->get(CopyOpc))
3019      .addReg(DstReg, getDefRegState(true) | getDeadRegState(DstIsDead))
3020      .addReg(ARM::SP);
3021    MF->DeleteMachineInstr(MI);   // The pseudo instruction is gone now.
3022    return BB;
3023  }
3024  }
3025}
3026
3027//===----------------------------------------------------------------------===//
3028//                           ARM Optimization Hooks
3029//===----------------------------------------------------------------------===//
3030
3031static
3032SDValue combineSelectAndUse(SDNode *N, SDValue Slct, SDValue OtherOp,
3033                            TargetLowering::DAGCombinerInfo &DCI) {
3034  SelectionDAG &DAG = DCI.DAG;
3035  const TargetLowering &TLI = DAG.getTargetLoweringInfo();
3036  EVT VT = N->getValueType(0);
3037  unsigned Opc = N->getOpcode();
3038  bool isSlctCC = Slct.getOpcode() == ISD::SELECT_CC;
3039  SDValue LHS = isSlctCC ? Slct.getOperand(2) : Slct.getOperand(1);
3040  SDValue RHS = isSlctCC ? Slct.getOperand(3) : Slct.getOperand(2);
3041  ISD::CondCode CC = ISD::SETCC_INVALID;
3042
3043  if (isSlctCC) {
3044    CC = cast<CondCodeSDNode>(Slct.getOperand(4))->get();
3045  } else {
3046    SDValue CCOp = Slct.getOperand(0);
3047    if (CCOp.getOpcode() == ISD::SETCC)
3048      CC = cast<CondCodeSDNode>(CCOp.getOperand(2))->get();
3049  }
3050
3051  bool DoXform = false;
3052  bool InvCC = false;
3053  assert ((Opc == ISD::ADD || (Opc == ISD::SUB && Slct == N->getOperand(1))) &&
3054          "Bad input!");
3055
3056  if (LHS.getOpcode() == ISD::Constant &&
3057      cast<ConstantSDNode>(LHS)->isNullValue()) {
3058    DoXform = true;
3059  } else if (CC != ISD::SETCC_INVALID &&
3060             RHS.getOpcode() == ISD::Constant &&
3061             cast<ConstantSDNode>(RHS)->isNullValue()) {
3062    std::swap(LHS, RHS);
3063    SDValue Op0 = Slct.getOperand(0);
3064    EVT OpVT = isSlctCC ? Op0.getValueType() :
3065                          Op0.getOperand(0).getValueType();
3066    bool isInt = OpVT.isInteger();
3067    CC = ISD::getSetCCInverse(CC, isInt);
3068
3069    if (!TLI.isCondCodeLegal(CC, OpVT))
3070      return SDValue();         // Inverse operator isn't legal.
3071
3072    DoXform = true;
3073    InvCC = true;
3074  }
3075
3076  if (DoXform) {
3077    SDValue Result = DAG.getNode(Opc, RHS.getDebugLoc(), VT, OtherOp, RHS);
3078    if (isSlctCC)
3079      return DAG.getSelectCC(N->getDebugLoc(), OtherOp, Result,
3080                             Slct.getOperand(0), Slct.getOperand(1), CC);
3081    SDValue CCOp = Slct.getOperand(0);
3082    if (InvCC)
3083      CCOp = DAG.getSetCC(Slct.getDebugLoc(), CCOp.getValueType(),
3084                          CCOp.getOperand(0), CCOp.getOperand(1), CC);
3085    return DAG.getNode(ISD::SELECT, N->getDebugLoc(), VT,
3086                       CCOp, OtherOp, Result);
3087  }
3088  return SDValue();
3089}
3090
3091/// PerformADDCombine - Target-specific dag combine xforms for ISD::ADD.
3092static SDValue PerformADDCombine(SDNode *N,
3093                                 TargetLowering::DAGCombinerInfo &DCI) {
3094  // added by evan in r37685 with no testcase.
3095  SDValue N0 = N->getOperand(0), N1 = N->getOperand(1);
3096
3097  // fold (add (select cc, 0, c), x) -> (select cc, x, (add, x, c))
3098  if (N0.getOpcode() == ISD::SELECT && N0.getNode()->hasOneUse()) {
3099    SDValue Result = combineSelectAndUse(N, N0, N1, DCI);
3100    if (Result.getNode()) return Result;
3101  }
3102  if (N1.getOpcode() == ISD::SELECT && N1.getNode()->hasOneUse()) {
3103    SDValue Result = combineSelectAndUse(N, N1, N0, DCI);
3104    if (Result.getNode()) return Result;
3105  }
3106
3107  return SDValue();
3108}
3109
3110/// PerformSUBCombine - Target-specific dag combine xforms for ISD::SUB.
3111static SDValue PerformSUBCombine(SDNode *N,
3112                                 TargetLowering::DAGCombinerInfo &DCI) {
3113  // added by evan in r37685 with no testcase.
3114  SDValue N0 = N->getOperand(0), N1 = N->getOperand(1);
3115
3116  // fold (sub x, (select cc, 0, c)) -> (select cc, x, (sub, x, c))
3117  if (N1.getOpcode() == ISD::SELECT && N1.getNode()->hasOneUse()) {
3118    SDValue Result = combineSelectAndUse(N, N1, N0, DCI);
3119    if (Result.getNode()) return Result;
3120  }
3121
3122  return SDValue();
3123}
3124
3125
3126/// PerformFMRRDCombine - Target-specific dag combine xforms for ARMISD::FMRRD.
3127static SDValue PerformFMRRDCombine(SDNode *N,
3128                                   TargetLowering::DAGCombinerInfo &DCI) {
3129  // fmrrd(fmdrr x, y) -> x,y
3130  SDValue InDouble = N->getOperand(0);
3131  if (InDouble.getOpcode() == ARMISD::FMDRR)
3132    return DCI.CombineTo(N, InDouble.getOperand(0), InDouble.getOperand(1));
3133  return SDValue();
3134}
3135
3136/// getVShiftImm - Check if this is a valid build_vector for the immediate
3137/// operand of a vector shift operation, where all the elements of the
3138/// build_vector must have the same constant integer value.
3139static bool getVShiftImm(SDValue Op, unsigned ElementBits, int64_t &Cnt) {
3140  // Ignore bit_converts.
3141  while (Op.getOpcode() == ISD::BIT_CONVERT)
3142    Op = Op.getOperand(0);
3143  BuildVectorSDNode *BVN = dyn_cast<BuildVectorSDNode>(Op.getNode());
3144  APInt SplatBits, SplatUndef;
3145  unsigned SplatBitSize;
3146  bool HasAnyUndefs;
3147  if (! BVN || ! BVN->isConstantSplat(SplatBits, SplatUndef, SplatBitSize,
3148                                      HasAnyUndefs, ElementBits) ||
3149      SplatBitSize > ElementBits)
3150    return false;
3151  Cnt = SplatBits.getSExtValue();
3152  return true;
3153}
3154
3155/// isVShiftLImm - Check if this is a valid build_vector for the immediate
3156/// operand of a vector shift left operation.  That value must be in the range:
3157///   0 <= Value < ElementBits for a left shift; or
3158///   0 <= Value <= ElementBits for a long left shift.
3159static bool isVShiftLImm(SDValue Op, EVT VT, bool isLong, int64_t &Cnt) {
3160  assert(VT.isVector() && "vector shift count is not a vector type");
3161  unsigned ElementBits = VT.getVectorElementType().getSizeInBits();
3162  if (! getVShiftImm(Op, ElementBits, Cnt))
3163    return false;
3164  return (Cnt >= 0 && (isLong ? Cnt-1 : Cnt) < ElementBits);
3165}
3166
3167/// isVShiftRImm - Check if this is a valid build_vector for the immediate
3168/// operand of a vector shift right operation.  For a shift opcode, the value
3169/// is positive, but for an intrinsic the value count must be negative. The
3170/// absolute value must be in the range:
3171///   1 <= |Value| <= ElementBits for a right shift; or
3172///   1 <= |Value| <= ElementBits/2 for a narrow right shift.
3173static bool isVShiftRImm(SDValue Op, EVT VT, bool isNarrow, bool isIntrinsic,
3174                         int64_t &Cnt) {
3175  assert(VT.isVector() && "vector shift count is not a vector type");
3176  unsigned ElementBits = VT.getVectorElementType().getSizeInBits();
3177  if (! getVShiftImm(Op, ElementBits, Cnt))
3178    return false;
3179  if (isIntrinsic)
3180    Cnt = -Cnt;
3181  return (Cnt >= 1 && Cnt <= (isNarrow ? ElementBits/2 : ElementBits));
3182}
3183
3184/// PerformIntrinsicCombine - ARM-specific DAG combining for intrinsics.
3185static SDValue PerformIntrinsicCombine(SDNode *N, SelectionDAG &DAG) {
3186  unsigned IntNo = cast<ConstantSDNode>(N->getOperand(0))->getZExtValue();
3187  switch (IntNo) {
3188  default:
3189    // Don't do anything for most intrinsics.
3190    break;
3191
3192  // Vector shifts: check for immediate versions and lower them.
3193  // Note: This is done during DAG combining instead of DAG legalizing because
3194  // the build_vectors for 64-bit vector element shift counts are generally
3195  // not legal, and it is hard to see their values after they get legalized to
3196  // loads from a constant pool.
3197  case Intrinsic::arm_neon_vshifts:
3198  case Intrinsic::arm_neon_vshiftu:
3199  case Intrinsic::arm_neon_vshiftls:
3200  case Intrinsic::arm_neon_vshiftlu:
3201  case Intrinsic::arm_neon_vshiftn:
3202  case Intrinsic::arm_neon_vrshifts:
3203  case Intrinsic::arm_neon_vrshiftu:
3204  case Intrinsic::arm_neon_vrshiftn:
3205  case Intrinsic::arm_neon_vqshifts:
3206  case Intrinsic::arm_neon_vqshiftu:
3207  case Intrinsic::arm_neon_vqshiftsu:
3208  case Intrinsic::arm_neon_vqshiftns:
3209  case Intrinsic::arm_neon_vqshiftnu:
3210  case Intrinsic::arm_neon_vqshiftnsu:
3211  case Intrinsic::arm_neon_vqrshiftns:
3212  case Intrinsic::arm_neon_vqrshiftnu:
3213  case Intrinsic::arm_neon_vqrshiftnsu: {
3214    EVT VT = N->getOperand(1).getValueType();
3215    int64_t Cnt;
3216    unsigned VShiftOpc = 0;
3217
3218    switch (IntNo) {
3219    case Intrinsic::arm_neon_vshifts:
3220    case Intrinsic::arm_neon_vshiftu:
3221      if (isVShiftLImm(N->getOperand(2), VT, false, Cnt)) {
3222        VShiftOpc = ARMISD::VSHL;
3223        break;
3224      }
3225      if (isVShiftRImm(N->getOperand(2), VT, false, true, Cnt)) {
3226        VShiftOpc = (IntNo == Intrinsic::arm_neon_vshifts ?
3227                     ARMISD::VSHRs : ARMISD::VSHRu);
3228        break;
3229      }
3230      return SDValue();
3231
3232    case Intrinsic::arm_neon_vshiftls:
3233    case Intrinsic::arm_neon_vshiftlu:
3234      if (isVShiftLImm(N->getOperand(2), VT, true, Cnt))
3235        break;
3236      llvm_unreachable("invalid shift count for vshll intrinsic");
3237
3238    case Intrinsic::arm_neon_vrshifts:
3239    case Intrinsic::arm_neon_vrshiftu:
3240      if (isVShiftRImm(N->getOperand(2), VT, false, true, Cnt))
3241        break;
3242      return SDValue();
3243
3244    case Intrinsic::arm_neon_vqshifts:
3245    case Intrinsic::arm_neon_vqshiftu:
3246      if (isVShiftLImm(N->getOperand(2), VT, false, Cnt))
3247        break;
3248      return SDValue();
3249
3250    case Intrinsic::arm_neon_vqshiftsu:
3251      if (isVShiftLImm(N->getOperand(2), VT, false, Cnt))
3252        break;
3253      llvm_unreachable("invalid shift count for vqshlu intrinsic");
3254
3255    case Intrinsic::arm_neon_vshiftn:
3256    case Intrinsic::arm_neon_vrshiftn:
3257    case Intrinsic::arm_neon_vqshiftns:
3258    case Intrinsic::arm_neon_vqshiftnu:
3259    case Intrinsic::arm_neon_vqshiftnsu:
3260    case Intrinsic::arm_neon_vqrshiftns:
3261    case Intrinsic::arm_neon_vqrshiftnu:
3262    case Intrinsic::arm_neon_vqrshiftnsu:
3263      // Narrowing shifts require an immediate right shift.
3264      if (isVShiftRImm(N->getOperand(2), VT, true, true, Cnt))
3265        break;
3266      llvm_unreachable("invalid shift count for narrowing vector shift intrinsic");
3267
3268    default:
3269      llvm_unreachable("unhandled vector shift");
3270    }
3271
3272    switch (IntNo) {
3273    case Intrinsic::arm_neon_vshifts:
3274    case Intrinsic::arm_neon_vshiftu:
3275      // Opcode already set above.
3276      break;
3277    case Intrinsic::arm_neon_vshiftls:
3278    case Intrinsic::arm_neon_vshiftlu:
3279      if (Cnt == VT.getVectorElementType().getSizeInBits())
3280        VShiftOpc = ARMISD::VSHLLi;
3281      else
3282        VShiftOpc = (IntNo == Intrinsic::arm_neon_vshiftls ?
3283                     ARMISD::VSHLLs : ARMISD::VSHLLu);
3284      break;
3285    case Intrinsic::arm_neon_vshiftn:
3286      VShiftOpc = ARMISD::VSHRN; break;
3287    case Intrinsic::arm_neon_vrshifts:
3288      VShiftOpc = ARMISD::VRSHRs; break;
3289    case Intrinsic::arm_neon_vrshiftu:
3290      VShiftOpc = ARMISD::VRSHRu; break;
3291    case Intrinsic::arm_neon_vrshiftn:
3292      VShiftOpc = ARMISD::VRSHRN; break;
3293    case Intrinsic::arm_neon_vqshifts:
3294      VShiftOpc = ARMISD::VQSHLs; break;
3295    case Intrinsic::arm_neon_vqshiftu:
3296      VShiftOpc = ARMISD::VQSHLu; break;
3297    case Intrinsic::arm_neon_vqshiftsu:
3298      VShiftOpc = ARMISD::VQSHLsu; break;
3299    case Intrinsic::arm_neon_vqshiftns:
3300      VShiftOpc = ARMISD::VQSHRNs; break;
3301    case Intrinsic::arm_neon_vqshiftnu:
3302      VShiftOpc = ARMISD::VQSHRNu; break;
3303    case Intrinsic::arm_neon_vqshiftnsu:
3304      VShiftOpc = ARMISD::VQSHRNsu; break;
3305    case Intrinsic::arm_neon_vqrshiftns:
3306      VShiftOpc = ARMISD::VQRSHRNs; break;
3307    case Intrinsic::arm_neon_vqrshiftnu:
3308      VShiftOpc = ARMISD::VQRSHRNu; break;
3309    case Intrinsic::arm_neon_vqrshiftnsu:
3310      VShiftOpc = ARMISD::VQRSHRNsu; break;
3311    }
3312
3313    return DAG.getNode(VShiftOpc, N->getDebugLoc(), N->getValueType(0),
3314                       N->getOperand(1), DAG.getConstant(Cnt, MVT::i32));
3315  }
3316
3317  case Intrinsic::arm_neon_vshiftins: {
3318    EVT VT = N->getOperand(1).getValueType();
3319    int64_t Cnt;
3320    unsigned VShiftOpc = 0;
3321
3322    if (isVShiftLImm(N->getOperand(3), VT, false, Cnt))
3323      VShiftOpc = ARMISD::VSLI;
3324    else if (isVShiftRImm(N->getOperand(3), VT, false, true, Cnt))
3325      VShiftOpc = ARMISD::VSRI;
3326    else {
3327      llvm_unreachable("invalid shift count for vsli/vsri intrinsic");
3328    }
3329
3330    return DAG.getNode(VShiftOpc, N->getDebugLoc(), N->getValueType(0),
3331                       N->getOperand(1), N->getOperand(2),
3332                       DAG.getConstant(Cnt, MVT::i32));
3333  }
3334
3335  case Intrinsic::arm_neon_vqrshifts:
3336  case Intrinsic::arm_neon_vqrshiftu:
3337    // No immediate versions of these to check for.
3338    break;
3339  }
3340
3341  return SDValue();
3342}
3343
3344/// PerformShiftCombine - Checks for immediate versions of vector shifts and
3345/// lowers them.  As with the vector shift intrinsics, this is done during DAG
3346/// combining instead of DAG legalizing because the build_vectors for 64-bit
3347/// vector element shift counts are generally not legal, and it is hard to see
3348/// their values after they get legalized to loads from a constant pool.
3349static SDValue PerformShiftCombine(SDNode *N, SelectionDAG &DAG,
3350                                   const ARMSubtarget *ST) {
3351  EVT VT = N->getValueType(0);
3352
3353  // Nothing to be done for scalar shifts.
3354  if (! VT.isVector())
3355    return SDValue();
3356
3357  assert(ST->hasNEON() && "unexpected vector shift");
3358  int64_t Cnt;
3359
3360  switch (N->getOpcode()) {
3361  default: llvm_unreachable("unexpected shift opcode");
3362
3363  case ISD::SHL:
3364    if (isVShiftLImm(N->getOperand(1), VT, false, Cnt))
3365      return DAG.getNode(ARMISD::VSHL, N->getDebugLoc(), VT, N->getOperand(0),
3366                         DAG.getConstant(Cnt, MVT::i32));
3367    break;
3368
3369  case ISD::SRA:
3370  case ISD::SRL:
3371    if (isVShiftRImm(N->getOperand(1), VT, false, false, Cnt)) {
3372      unsigned VShiftOpc = (N->getOpcode() == ISD::SRA ?
3373                            ARMISD::VSHRs : ARMISD::VSHRu);
3374      return DAG.getNode(VShiftOpc, N->getDebugLoc(), VT, N->getOperand(0),
3375                         DAG.getConstant(Cnt, MVT::i32));
3376    }
3377  }
3378  return SDValue();
3379}
3380
3381/// PerformExtendCombine - Target-specific DAG combining for ISD::SIGN_EXTEND,
3382/// ISD::ZERO_EXTEND, and ISD::ANY_EXTEND.
3383static SDValue PerformExtendCombine(SDNode *N, SelectionDAG &DAG,
3384                                    const ARMSubtarget *ST) {
3385  SDValue N0 = N->getOperand(0);
3386
3387  // Check for sign- and zero-extensions of vector extract operations of 8-
3388  // and 16-bit vector elements.  NEON supports these directly.  They are
3389  // handled during DAG combining because type legalization will promote them
3390  // to 32-bit types and it is messy to recognize the operations after that.
3391  if (ST->hasNEON() && N0.getOpcode() == ISD::EXTRACT_VECTOR_ELT) {
3392    SDValue Vec = N0.getOperand(0);
3393    SDValue Lane = N0.getOperand(1);
3394    EVT VT = N->getValueType(0);
3395    EVT EltVT = N0.getValueType();
3396    const TargetLowering &TLI = DAG.getTargetLoweringInfo();
3397
3398    if (VT == MVT::i32 &&
3399        (EltVT == MVT::i8 || EltVT == MVT::i16) &&
3400        TLI.isTypeLegal(Vec.getValueType())) {
3401
3402      unsigned Opc = 0;
3403      switch (N->getOpcode()) {
3404      default: llvm_unreachable("unexpected opcode");
3405      case ISD::SIGN_EXTEND:
3406        Opc = ARMISD::VGETLANEs;
3407        break;
3408      case ISD::ZERO_EXTEND:
3409      case ISD::ANY_EXTEND:
3410        Opc = ARMISD::VGETLANEu;
3411        break;
3412      }
3413      return DAG.getNode(Opc, N->getDebugLoc(), VT, Vec, Lane);
3414    }
3415  }
3416
3417  return SDValue();
3418}
3419
3420SDValue ARMTargetLowering::PerformDAGCombine(SDNode *N,
3421                                             DAGCombinerInfo &DCI) const {
3422  switch (N->getOpcode()) {
3423  default: break;
3424  case ISD::ADD:      return PerformADDCombine(N, DCI);
3425  case ISD::SUB:      return PerformSUBCombine(N, DCI);
3426  case ARMISD::FMRRD: return PerformFMRRDCombine(N, DCI);
3427  case ISD::INTRINSIC_WO_CHAIN:
3428    return PerformIntrinsicCombine(N, DCI.DAG);
3429  case ISD::SHL:
3430  case ISD::SRA:
3431  case ISD::SRL:
3432    return PerformShiftCombine(N, DCI.DAG, Subtarget);
3433  case ISD::SIGN_EXTEND:
3434  case ISD::ZERO_EXTEND:
3435  case ISD::ANY_EXTEND:
3436    return PerformExtendCombine(N, DCI.DAG, Subtarget);
3437  }
3438  return SDValue();
3439}
3440
3441bool ARMTargetLowering::allowsUnalignedMemoryAccesses(EVT VT) const {
3442  if (!Subtarget->hasV6Ops())
3443    // Pre-v6 does not support unaligned mem access.
3444    return false;
3445  else if (!Subtarget->hasV6Ops()) {
3446    // v6 may or may not support unaligned mem access.
3447    if (!Subtarget->isTargetDarwin())
3448      return false;
3449  }
3450
3451  switch (VT.getSimpleVT().SimpleTy) {
3452  default:
3453    return false;
3454  case MVT::i8:
3455  case MVT::i16:
3456  case MVT::i32:
3457    return true;
3458  // FIXME: VLD1 etc with standard alignment is legal.
3459  }
3460}
3461
3462static bool isLegalT1AddressImmediate(int64_t V, EVT VT) {
3463  if (V < 0)
3464    return false;
3465
3466  unsigned Scale = 1;
3467  switch (VT.getSimpleVT().SimpleTy) {
3468  default: return false;
3469  case MVT::i1:
3470  case MVT::i8:
3471    // Scale == 1;
3472    break;
3473  case MVT::i16:
3474    // Scale == 2;
3475    Scale = 2;
3476    break;
3477  case MVT::i32:
3478    // Scale == 4;
3479    Scale = 4;
3480    break;
3481  }
3482
3483  if ((V & (Scale - 1)) != 0)
3484    return false;
3485  V /= Scale;
3486  return V == (V & ((1LL << 5) - 1));
3487}
3488
3489static bool isLegalT2AddressImmediate(int64_t V, EVT VT,
3490                                      const ARMSubtarget *Subtarget) {
3491  bool isNeg = false;
3492  if (V < 0) {
3493    isNeg = true;
3494    V = - V;
3495  }
3496
3497  switch (VT.getSimpleVT().SimpleTy) {
3498  default: return false;
3499  case MVT::i1:
3500  case MVT::i8:
3501  case MVT::i16:
3502  case MVT::i32:
3503    // + imm12 or - imm8
3504    if (isNeg)
3505      return V == (V & ((1LL << 8) - 1));
3506    return V == (V & ((1LL << 12) - 1));
3507  case MVT::f32:
3508  case MVT::f64:
3509    // Same as ARM mode. FIXME: NEON?
3510    if (!Subtarget->hasVFP2())
3511      return false;
3512    if ((V & 3) != 0)
3513      return false;
3514    V >>= 2;
3515    return V == (V & ((1LL << 8) - 1));
3516  }
3517}
3518
3519/// isLegalAddressImmediate - Return true if the integer value can be used
3520/// as the offset of the target addressing mode for load / store of the
3521/// given type.
3522static bool isLegalAddressImmediate(int64_t V, EVT VT,
3523                                    const ARMSubtarget *Subtarget) {
3524  if (V == 0)
3525    return true;
3526
3527  if (!VT.isSimple())
3528    return false;
3529
3530  if (Subtarget->isThumb1Only())
3531    return isLegalT1AddressImmediate(V, VT);
3532  else if (Subtarget->isThumb2())
3533    return isLegalT2AddressImmediate(V, VT, Subtarget);
3534
3535  // ARM mode.
3536  if (V < 0)
3537    V = - V;
3538  switch (VT.getSimpleVT().SimpleTy) {
3539  default: return false;
3540  case MVT::i1:
3541  case MVT::i8:
3542  case MVT::i32:
3543    // +- imm12
3544    return V == (V & ((1LL << 12) - 1));
3545  case MVT::i16:
3546    // +- imm8
3547    return V == (V & ((1LL << 8) - 1));
3548  case MVT::f32:
3549  case MVT::f64:
3550    if (!Subtarget->hasVFP2()) // FIXME: NEON?
3551      return false;
3552    if ((V & 3) != 0)
3553      return false;
3554    V >>= 2;
3555    return V == (V & ((1LL << 8) - 1));
3556  }
3557}
3558
3559bool ARMTargetLowering::isLegalT2ScaledAddressingMode(const AddrMode &AM,
3560                                                      EVT VT) const {
3561  int Scale = AM.Scale;
3562  if (Scale < 0)
3563    return false;
3564
3565  switch (VT.getSimpleVT().SimpleTy) {
3566  default: return false;
3567  case MVT::i1:
3568  case MVT::i8:
3569  case MVT::i16:
3570  case MVT::i32:
3571    if (Scale == 1)
3572      return true;
3573    // r + r << imm
3574    Scale = Scale & ~1;
3575    return Scale == 2 || Scale == 4 || Scale == 8;
3576  case MVT::i64:
3577    // r + r
3578    if (((unsigned)AM.HasBaseReg + Scale) <= 2)
3579      return true;
3580    return false;
3581  case MVT::isVoid:
3582    // Note, we allow "void" uses (basically, uses that aren't loads or
3583    // stores), because arm allows folding a scale into many arithmetic
3584    // operations.  This should be made more precise and revisited later.
3585
3586    // Allow r << imm, but the imm has to be a multiple of two.
3587    if (Scale & 1) return false;
3588    return isPowerOf2_32(Scale);
3589  }
3590}
3591
3592/// isLegalAddressingMode - Return true if the addressing mode represented
3593/// by AM is legal for this target, for a load/store of the specified type.
3594bool ARMTargetLowering::isLegalAddressingMode(const AddrMode &AM,
3595                                              const Type *Ty) const {
3596  EVT VT = getValueType(Ty, true);
3597  if (!isLegalAddressImmediate(AM.BaseOffs, VT, Subtarget))
3598    return false;
3599
3600  // Can never fold addr of global into load/store.
3601  if (AM.BaseGV)
3602    return false;
3603
3604  switch (AM.Scale) {
3605  case 0:  // no scale reg, must be "r+i" or "r", or "i".
3606    break;
3607  case 1:
3608    if (Subtarget->isThumb1Only())
3609      return false;
3610    // FALL THROUGH.
3611  default:
3612    // ARM doesn't support any R+R*scale+imm addr modes.
3613    if (AM.BaseOffs)
3614      return false;
3615
3616    if (!VT.isSimple())
3617      return false;
3618
3619    if (Subtarget->isThumb2())
3620      return isLegalT2ScaledAddressingMode(AM, VT);
3621
3622    int Scale = AM.Scale;
3623    switch (VT.getSimpleVT().SimpleTy) {
3624    default: return false;
3625    case MVT::i1:
3626    case MVT::i8:
3627    case MVT::i32:
3628      if (Scale < 0) Scale = -Scale;
3629      if (Scale == 1)
3630        return true;
3631      // r + r << imm
3632      return isPowerOf2_32(Scale & ~1);
3633    case MVT::i16:
3634    case MVT::i64:
3635      // r + r
3636      if (((unsigned)AM.HasBaseReg + Scale) <= 2)
3637        return true;
3638      return false;
3639
3640    case MVT::isVoid:
3641      // Note, we allow "void" uses (basically, uses that aren't loads or
3642      // stores), because arm allows folding a scale into many arithmetic
3643      // operations.  This should be made more precise and revisited later.
3644
3645      // Allow r << imm, but the imm has to be a multiple of two.
3646      if (Scale & 1) return false;
3647      return isPowerOf2_32(Scale);
3648    }
3649    break;
3650  }
3651  return true;
3652}
3653
3654static bool getARMIndexedAddressParts(SDNode *Ptr, EVT VT,
3655                                      bool isSEXTLoad, SDValue &Base,
3656                                      SDValue &Offset, bool &isInc,
3657                                      SelectionDAG &DAG) {
3658  if (Ptr->getOpcode() != ISD::ADD && Ptr->getOpcode() != ISD::SUB)
3659    return false;
3660
3661  if (VT == MVT::i16 || ((VT == MVT::i8 || VT == MVT::i1) && isSEXTLoad)) {
3662    // AddressingMode 3
3663    Base = Ptr->getOperand(0);
3664    if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(Ptr->getOperand(1))) {
3665      int RHSC = (int)RHS->getZExtValue();
3666      if (RHSC < 0 && RHSC > -256) {
3667        assert(Ptr->getOpcode() == ISD::ADD);
3668        isInc = false;
3669        Offset = DAG.getConstant(-RHSC, RHS->getValueType(0));
3670        return true;
3671      }
3672    }
3673    isInc = (Ptr->getOpcode() == ISD::ADD);
3674    Offset = Ptr->getOperand(1);
3675    return true;
3676  } else if (VT == MVT::i32 || VT == MVT::i8 || VT == MVT::i1) {
3677    // AddressingMode 2
3678    if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(Ptr->getOperand(1))) {
3679      int RHSC = (int)RHS->getZExtValue();
3680      if (RHSC < 0 && RHSC > -0x1000) {
3681        assert(Ptr->getOpcode() == ISD::ADD);
3682        isInc = false;
3683        Offset = DAG.getConstant(-RHSC, RHS->getValueType(0));
3684        Base = Ptr->getOperand(0);
3685        return true;
3686      }
3687    }
3688
3689    if (Ptr->getOpcode() == ISD::ADD) {
3690      isInc = true;
3691      ARM_AM::ShiftOpc ShOpcVal= ARM_AM::getShiftOpcForNode(Ptr->getOperand(0));
3692      if (ShOpcVal != ARM_AM::no_shift) {
3693        Base = Ptr->getOperand(1);
3694        Offset = Ptr->getOperand(0);
3695      } else {
3696        Base = Ptr->getOperand(0);
3697        Offset = Ptr->getOperand(1);
3698      }
3699      return true;
3700    }
3701
3702    isInc = (Ptr->getOpcode() == ISD::ADD);
3703    Base = Ptr->getOperand(0);
3704    Offset = Ptr->getOperand(1);
3705    return true;
3706  }
3707
3708  // FIXME: Use FLDM / FSTM to emulate indexed FP load / store.
3709  return false;
3710}
3711
3712static bool getT2IndexedAddressParts(SDNode *Ptr, EVT VT,
3713                                     bool isSEXTLoad, SDValue &Base,
3714                                     SDValue &Offset, bool &isInc,
3715                                     SelectionDAG &DAG) {
3716  if (Ptr->getOpcode() != ISD::ADD && Ptr->getOpcode() != ISD::SUB)
3717    return false;
3718
3719  Base = Ptr->getOperand(0);
3720  if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(Ptr->getOperand(1))) {
3721    int RHSC = (int)RHS->getZExtValue();
3722    if (RHSC < 0 && RHSC > -0x100) { // 8 bits.
3723      assert(Ptr->getOpcode() == ISD::ADD);
3724      isInc = false;
3725      Offset = DAG.getConstant(-RHSC, RHS->getValueType(0));
3726      return true;
3727    } else if (RHSC > 0 && RHSC < 0x100) { // 8 bit, no zero.
3728      isInc = Ptr->getOpcode() == ISD::ADD;
3729      Offset = DAG.getConstant(RHSC, RHS->getValueType(0));
3730      return true;
3731    }
3732  }
3733
3734  return false;
3735}
3736
3737/// getPreIndexedAddressParts - returns true by value, base pointer and
3738/// offset pointer and addressing mode by reference if the node's address
3739/// can be legally represented as pre-indexed load / store address.
3740bool
3741ARMTargetLowering::getPreIndexedAddressParts(SDNode *N, SDValue &Base,
3742                                             SDValue &Offset,
3743                                             ISD::MemIndexedMode &AM,
3744                                             SelectionDAG &DAG) const {
3745  if (Subtarget->isThumb1Only())
3746    return false;
3747
3748  EVT VT;
3749  SDValue Ptr;
3750  bool isSEXTLoad = false;
3751  if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) {
3752    Ptr = LD->getBasePtr();
3753    VT  = LD->getMemoryVT();
3754    isSEXTLoad = LD->getExtensionType() == ISD::SEXTLOAD;
3755  } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) {
3756    Ptr = ST->getBasePtr();
3757    VT  = ST->getMemoryVT();
3758  } else
3759    return false;
3760
3761  bool isInc;
3762  bool isLegal = false;
3763  if (Subtarget->isThumb2())
3764    isLegal = getT2IndexedAddressParts(Ptr.getNode(), VT, isSEXTLoad, Base,
3765                                       Offset, isInc, DAG);
3766  else
3767    isLegal = getARMIndexedAddressParts(Ptr.getNode(), VT, isSEXTLoad, Base,
3768                                        Offset, isInc, DAG);
3769  if (!isLegal)
3770    return false;
3771
3772  AM = isInc ? ISD::PRE_INC : ISD::PRE_DEC;
3773  return true;
3774}
3775
3776/// getPostIndexedAddressParts - returns true by value, base pointer and
3777/// offset pointer and addressing mode by reference if this node can be
3778/// combined with a load / store to form a post-indexed load / store.
3779bool ARMTargetLowering::getPostIndexedAddressParts(SDNode *N, SDNode *Op,
3780                                                   SDValue &Base,
3781                                                   SDValue &Offset,
3782                                                   ISD::MemIndexedMode &AM,
3783                                                   SelectionDAG &DAG) const {
3784  if (Subtarget->isThumb1Only())
3785    return false;
3786
3787  EVT VT;
3788  SDValue Ptr;
3789  bool isSEXTLoad = false;
3790  if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) {
3791    VT  = LD->getMemoryVT();
3792    isSEXTLoad = LD->getExtensionType() == ISD::SEXTLOAD;
3793  } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) {
3794    VT  = ST->getMemoryVT();
3795  } else
3796    return false;
3797
3798  bool isInc;
3799  bool isLegal = false;
3800  if (Subtarget->isThumb2())
3801    isLegal = getT2IndexedAddressParts(Op, VT, isSEXTLoad, Base, Offset,
3802                                        isInc, DAG);
3803  else
3804    isLegal = getARMIndexedAddressParts(Op, VT, isSEXTLoad, Base, Offset,
3805                                        isInc, DAG);
3806  if (!isLegal)
3807    return false;
3808
3809  AM = isInc ? ISD::POST_INC : ISD::POST_DEC;
3810  return true;
3811}
3812
3813void ARMTargetLowering::computeMaskedBitsForTargetNode(const SDValue Op,
3814                                                       const APInt &Mask,
3815                                                       APInt &KnownZero,
3816                                                       APInt &KnownOne,
3817                                                       const SelectionDAG &DAG,
3818                                                       unsigned Depth) const {
3819  KnownZero = KnownOne = APInt(Mask.getBitWidth(), 0);
3820  switch (Op.getOpcode()) {
3821  default: break;
3822  case ARMISD::CMOV: {
3823    // Bits are known zero/one if known on the LHS and RHS.
3824    DAG.ComputeMaskedBits(Op.getOperand(0), Mask, KnownZero, KnownOne, Depth+1);
3825    if (KnownZero == 0 && KnownOne == 0) return;
3826
3827    APInt KnownZeroRHS, KnownOneRHS;
3828    DAG.ComputeMaskedBits(Op.getOperand(1), Mask,
3829                          KnownZeroRHS, KnownOneRHS, Depth+1);
3830    KnownZero &= KnownZeroRHS;
3831    KnownOne  &= KnownOneRHS;
3832    return;
3833  }
3834  }
3835}
3836
3837//===----------------------------------------------------------------------===//
3838//                           ARM Inline Assembly Support
3839//===----------------------------------------------------------------------===//
3840
3841/// getConstraintType - Given a constraint letter, return the type of
3842/// constraint it is for this target.
3843ARMTargetLowering::ConstraintType
3844ARMTargetLowering::getConstraintType(const std::string &Constraint) const {
3845  if (Constraint.size() == 1) {
3846    switch (Constraint[0]) {
3847    default:  break;
3848    case 'l': return C_RegisterClass;
3849    case 'w': return C_RegisterClass;
3850    }
3851  }
3852  return TargetLowering::getConstraintType(Constraint);
3853}
3854
3855std::pair<unsigned, const TargetRegisterClass*>
3856ARMTargetLowering::getRegForInlineAsmConstraint(const std::string &Constraint,
3857                                                EVT VT) const {
3858  if (Constraint.size() == 1) {
3859    // GCC RS6000 Constraint Letters
3860    switch (Constraint[0]) {
3861    case 'l':
3862      if (Subtarget->isThumb1Only())
3863        return std::make_pair(0U, ARM::tGPRRegisterClass);
3864      else
3865        return std::make_pair(0U, ARM::GPRRegisterClass);
3866    case 'r':
3867      return std::make_pair(0U, ARM::GPRRegisterClass);
3868    case 'w':
3869      if (VT == MVT::f32)
3870        return std::make_pair(0U, ARM::SPRRegisterClass);
3871      if (VT == MVT::f64)
3872        return std::make_pair(0U, ARM::DPRRegisterClass);
3873      break;
3874    }
3875  }
3876  return TargetLowering::getRegForInlineAsmConstraint(Constraint, VT);
3877}
3878
3879std::vector<unsigned> ARMTargetLowering::
3880getRegClassForInlineAsmConstraint(const std::string &Constraint,
3881                                  EVT VT) const {
3882  if (Constraint.size() != 1)
3883    return std::vector<unsigned>();
3884
3885  switch (Constraint[0]) {      // GCC ARM Constraint Letters
3886  default: break;
3887  case 'l':
3888    return make_vector<unsigned>(ARM::R0, ARM::R1, ARM::R2, ARM::R3,
3889                                 ARM::R4, ARM::R5, ARM::R6, ARM::R7,
3890                                 0);
3891  case 'r':
3892    return make_vector<unsigned>(ARM::R0, ARM::R1, ARM::R2, ARM::R3,
3893                                 ARM::R4, ARM::R5, ARM::R6, ARM::R7,
3894                                 ARM::R8, ARM::R9, ARM::R10, ARM::R11,
3895                                 ARM::R12, ARM::LR, 0);
3896  case 'w':
3897    if (VT == MVT::f32)
3898      return make_vector<unsigned>(ARM::S0, ARM::S1, ARM::S2, ARM::S3,
3899                                   ARM::S4, ARM::S5, ARM::S6, ARM::S7,
3900                                   ARM::S8, ARM::S9, ARM::S10, ARM::S11,
3901                                   ARM::S12,ARM::S13,ARM::S14,ARM::S15,
3902                                   ARM::S16,ARM::S17,ARM::S18,ARM::S19,
3903                                   ARM::S20,ARM::S21,ARM::S22,ARM::S23,
3904                                   ARM::S24,ARM::S25,ARM::S26,ARM::S27,
3905                                   ARM::S28,ARM::S29,ARM::S30,ARM::S31, 0);
3906    if (VT == MVT::f64)
3907      return make_vector<unsigned>(ARM::D0, ARM::D1, ARM::D2, ARM::D3,
3908                                   ARM::D4, ARM::D5, ARM::D6, ARM::D7,
3909                                   ARM::D8, ARM::D9, ARM::D10,ARM::D11,
3910                                   ARM::D12,ARM::D13,ARM::D14,ARM::D15, 0);
3911      break;
3912  }
3913
3914  return std::vector<unsigned>();
3915}
3916
3917/// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
3918/// vector.  If it is invalid, don't add anything to Ops.
3919void ARMTargetLowering::LowerAsmOperandForConstraint(SDValue Op,
3920                                                     char Constraint,
3921                                                     bool hasMemory,
3922                                                     std::vector<SDValue>&Ops,
3923                                                     SelectionDAG &DAG) const {
3924  SDValue Result(0, 0);
3925
3926  switch (Constraint) {
3927  default: break;
3928  case 'I': case 'J': case 'K': case 'L':
3929  case 'M': case 'N': case 'O':
3930    ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op);
3931    if (!C)
3932      return;
3933
3934    int64_t CVal64 = C->getSExtValue();
3935    int CVal = (int) CVal64;
3936    // None of these constraints allow values larger than 32 bits.  Check
3937    // that the value fits in an int.
3938    if (CVal != CVal64)
3939      return;
3940
3941    switch (Constraint) {
3942      case 'I':
3943        if (Subtarget->isThumb1Only()) {
3944          // This must be a constant between 0 and 255, for ADD
3945          // immediates.
3946          if (CVal >= 0 && CVal <= 255)
3947            break;
3948        } else if (Subtarget->isThumb2()) {
3949          // A constant that can be used as an immediate value in a
3950          // data-processing instruction.
3951          if (ARM_AM::getT2SOImmVal(CVal) != -1)
3952            break;
3953        } else {
3954          // A constant that can be used as an immediate value in a
3955          // data-processing instruction.
3956          if (ARM_AM::getSOImmVal(CVal) != -1)
3957            break;
3958        }
3959        return;
3960
3961      case 'J':
3962        if (Subtarget->isThumb()) {  // FIXME thumb2
3963          // This must be a constant between -255 and -1, for negated ADD
3964          // immediates. This can be used in GCC with an "n" modifier that
3965          // prints the negated value, for use with SUB instructions. It is
3966          // not useful otherwise but is implemented for compatibility.
3967          if (CVal >= -255 && CVal <= -1)
3968            break;
3969        } else {
3970          // This must be a constant between -4095 and 4095. It is not clear
3971          // what this constraint is intended for. Implemented for
3972          // compatibility with GCC.
3973          if (CVal >= -4095 && CVal <= 4095)
3974            break;
3975        }
3976        return;
3977
3978      case 'K':
3979        if (Subtarget->isThumb1Only()) {
3980          // A 32-bit value where only one byte has a nonzero value. Exclude
3981          // zero to match GCC. This constraint is used by GCC internally for
3982          // constants that can be loaded with a move/shift combination.
3983          // It is not useful otherwise but is implemented for compatibility.
3984          if (CVal != 0 && ARM_AM::isThumbImmShiftedVal(CVal))
3985            break;
3986        } else if (Subtarget->isThumb2()) {
3987          // A constant whose bitwise inverse can be used as an immediate
3988          // value in a data-processing instruction. This can be used in GCC
3989          // with a "B" modifier that prints the inverted value, for use with
3990          // BIC and MVN instructions. It is not useful otherwise but is
3991          // implemented for compatibility.
3992          if (ARM_AM::getT2SOImmVal(~CVal) != -1)
3993            break;
3994        } else {
3995          // A constant whose bitwise inverse can be used as an immediate
3996          // value in a data-processing instruction. This can be used in GCC
3997          // with a "B" modifier that prints the inverted value, for use with
3998          // BIC and MVN instructions. It is not useful otherwise but is
3999          // implemented for compatibility.
4000          if (ARM_AM::getSOImmVal(~CVal) != -1)
4001            break;
4002        }
4003        return;
4004
4005      case 'L':
4006        if (Subtarget->isThumb1Only()) {
4007          // This must be a constant between -7 and 7,
4008          // for 3-operand ADD/SUB immediate instructions.
4009          if (CVal >= -7 && CVal < 7)
4010            break;
4011        } else if (Subtarget->isThumb2()) {
4012          // A constant whose negation can be used as an immediate value in a
4013          // data-processing instruction. This can be used in GCC with an "n"
4014          // modifier that prints the negated value, for use with SUB
4015          // instructions. It is not useful otherwise but is implemented for
4016          // compatibility.
4017          if (ARM_AM::getT2SOImmVal(-CVal) != -1)
4018            break;
4019        } else {
4020          // A constant whose negation can be used as an immediate value in a
4021          // data-processing instruction. This can be used in GCC with an "n"
4022          // modifier that prints the negated value, for use with SUB
4023          // instructions. It is not useful otherwise but is implemented for
4024          // compatibility.
4025          if (ARM_AM::getSOImmVal(-CVal) != -1)
4026            break;
4027        }
4028        return;
4029
4030      case 'M':
4031        if (Subtarget->isThumb()) { // FIXME thumb2
4032          // This must be a multiple of 4 between 0 and 1020, for
4033          // ADD sp + immediate.
4034          if ((CVal >= 0 && CVal <= 1020) && ((CVal & 3) == 0))
4035            break;
4036        } else {
4037          // A power of two or a constant between 0 and 32.  This is used in
4038          // GCC for the shift amount on shifted register operands, but it is
4039          // useful in general for any shift amounts.
4040          if ((CVal >= 0 && CVal <= 32) || ((CVal & (CVal - 1)) == 0))
4041            break;
4042        }
4043        return;
4044
4045      case 'N':
4046        if (Subtarget->isThumb()) {  // FIXME thumb2
4047          // This must be a constant between 0 and 31, for shift amounts.
4048          if (CVal >= 0 && CVal <= 31)
4049            break;
4050        }
4051        return;
4052
4053      case 'O':
4054        if (Subtarget->isThumb()) {  // FIXME thumb2
4055          // This must be a multiple of 4 between -508 and 508, for
4056          // ADD/SUB sp = sp + immediate.
4057          if ((CVal >= -508 && CVal <= 508) && ((CVal & 3) == 0))
4058            break;
4059        }
4060        return;
4061    }
4062    Result = DAG.getTargetConstant(CVal, Op.getValueType());
4063    break;
4064  }
4065
4066  if (Result.getNode()) {
4067    Ops.push_back(Result);
4068    return;
4069  }
4070  return TargetLowering::LowerAsmOperandForConstraint(Op, Constraint, hasMemory,
4071                                                      Ops, DAG);
4072}
4073