ARMISelLowering.h revision 022d9e1cef7586a80a96446ae8691a37def9bbf4
1a8e2989ece6dc46df59b0768184028257f913843Evan Cheng//===-- ARMISelLowering.h - ARM DAG Lowering Interface ----------*- C++ -*-===// 2a8e2989ece6dc46df59b0768184028257f913843Evan Cheng// 3a8e2989ece6dc46df59b0768184028257f913843Evan Cheng// The LLVM Compiler Infrastructure 4a8e2989ece6dc46df59b0768184028257f913843Evan Cheng// 54ee451de366474b9c228b4e5fa573795a715216dChris Lattner// This file is distributed under the University of Illinois Open Source 64ee451de366474b9c228b4e5fa573795a715216dChris Lattner// License. See LICENSE.TXT for details. 7a8e2989ece6dc46df59b0768184028257f913843Evan Cheng// 8a8e2989ece6dc46df59b0768184028257f913843Evan Cheng//===----------------------------------------------------------------------===// 9a8e2989ece6dc46df59b0768184028257f913843Evan Cheng// 10a8e2989ece6dc46df59b0768184028257f913843Evan Cheng// This file defines the interfaces that ARM uses to lower LLVM code into a 11a8e2989ece6dc46df59b0768184028257f913843Evan Cheng// selection DAG. 12a8e2989ece6dc46df59b0768184028257f913843Evan Cheng// 13a8e2989ece6dc46df59b0768184028257f913843Evan Cheng//===----------------------------------------------------------------------===// 14a8e2989ece6dc46df59b0768184028257f913843Evan Cheng 15a8e2989ece6dc46df59b0768184028257f913843Evan Cheng#ifndef ARMISELLOWERING_H 16a8e2989ece6dc46df59b0768184028257f913843Evan Cheng#define ARMISELLOWERING_H 17a8e2989ece6dc46df59b0768184028257f913843Evan Cheng 18f1ba1cad387dc52f3c2c5afc665edf9caad00992Rafael Espindola#include "ARMSubtarget.h" 19a8e2989ece6dc46df59b0768184028257f913843Evan Cheng#include "llvm/Target/TargetLowering.h" 20a8e2989ece6dc46df59b0768184028257f913843Evan Cheng#include "llvm/CodeGen/SelectionDAG.h" 211f595bb42950088ccb8246e6b065a96027b46ec6Bob Wilson#include "llvm/CodeGen/CallingConvLower.h" 22a8e2989ece6dc46df59b0768184028257f913843Evan Cheng#include <vector> 23a8e2989ece6dc46df59b0768184028257f913843Evan Cheng 24a8e2989ece6dc46df59b0768184028257f913843Evan Chengnamespace llvm { 25a8e2989ece6dc46df59b0768184028257f913843Evan Cheng class ARMConstantPoolValue; 26a8e2989ece6dc46df59b0768184028257f913843Evan Cheng 27a8e2989ece6dc46df59b0768184028257f913843Evan Cheng namespace ARMISD { 28a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // ARM Specific DAG Nodes 29a8e2989ece6dc46df59b0768184028257f913843Evan Cheng enum NodeType { 306aa7197fb5aa478a5c813d41a11689bb6d8f7abcJim Grosbach // Start the numbering where the builtin ops and target ops leave off. 310ba2bcfcc3149a25d08aa8aa00fb6c34a4e25bddDan Gohman FIRST_NUMBER = ISD::BUILTIN_OP_END, 32a8e2989ece6dc46df59b0768184028257f913843Evan Cheng 33a8e2989ece6dc46df59b0768184028257f913843Evan Cheng Wrapper, // Wrapper - A wrapper node for TargetConstantPool, 34a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // TargetExternalSymbol, and TargetGlobalAddress. 35a8e2989ece6dc46df59b0768184028257f913843Evan Cheng WrapperJT, // WrapperJT - A wrapper node for TargetJumpTable 366aa7197fb5aa478a5c813d41a11689bb6d8f7abcJim Grosbach 37a8e2989ece6dc46df59b0768184028257f913843Evan Cheng CALL, // Function call. 38277f0741c5ea123b30360c382a153df238c31caeEvan Cheng CALL_PRED, // Function call that's predicable. 39a8e2989ece6dc46df59b0768184028257f913843Evan Cheng CALL_NOLINK, // Function call with branch not branch-and-link. 40a8e2989ece6dc46df59b0768184028257f913843Evan Cheng tCALL, // Thumb function call. 41a8e2989ece6dc46df59b0768184028257f913843Evan Cheng BRCOND, // Conditional branch. 42a8e2989ece6dc46df59b0768184028257f913843Evan Cheng BR_JT, // Jumptable branch. 435657c01949dca6c012ac60d242d1a8d2ffdf5603Evan Cheng BR2_JT, // Jumptable branch (2 level - jumptable entry is a jump). 44a8e2989ece6dc46df59b0768184028257f913843Evan Cheng RET_FLAG, // Return with a flag operand. 45a8e2989ece6dc46df59b0768184028257f913843Evan Cheng 46a8e2989ece6dc46df59b0768184028257f913843Evan Cheng PIC_ADD, // Add with a PC operand and a PIC label. 47a8e2989ece6dc46df59b0768184028257f913843Evan Cheng 48a8e2989ece6dc46df59b0768184028257f913843Evan Cheng CMP, // ARM compare instructions. 49c0309b48b560f119982c02a81416c8c1fd208648David Goodwin CMPZ, // ARM compare that sets only Z flag. 50a8e2989ece6dc46df59b0768184028257f913843Evan Cheng CMPFP, // ARM VFP compare instruction, sets FPSCR. 51a8e2989ece6dc46df59b0768184028257f913843Evan Cheng CMPFPw0, // ARM VFP compare against zero instruction, sets FPSCR. 52a8e2989ece6dc46df59b0768184028257f913843Evan Cheng FMSTAT, // ARM fmstat instruction. 53a8e2989ece6dc46df59b0768184028257f913843Evan Cheng CMOV, // ARM conditional move instructions. 54a8e2989ece6dc46df59b0768184028257f913843Evan Cheng CNEG, // ARM conditional negate instructions. 556aa7197fb5aa478a5c813d41a11689bb6d8f7abcJim Grosbach 563482c8003ad0c88469b7333aaf658036e3fd0468Jim Grosbach RBIT, // ARM bitreverse instruction 573482c8003ad0c88469b7333aaf658036e3fd0468Jim Grosbach 58a8e2989ece6dc46df59b0768184028257f913843Evan Cheng FTOSI, // FP to sint within a FP register. 59a8e2989ece6dc46df59b0768184028257f913843Evan Cheng FTOUI, // FP to uint within a FP register. 60a8e2989ece6dc46df59b0768184028257f913843Evan Cheng SITOF, // sint to FP within a FP register. 61a8e2989ece6dc46df59b0768184028257f913843Evan Cheng UITOF, // uint to FP within a FP register. 62a8e2989ece6dc46df59b0768184028257f913843Evan Cheng 63a8e2989ece6dc46df59b0768184028257f913843Evan Cheng SRL_FLAG, // V,Flag = srl_flag X -> srl X, 1 + save carry out. 64a8e2989ece6dc46df59b0768184028257f913843Evan Cheng SRA_FLAG, // V,Flag = sra_flag X -> sra X, 1 + save carry out. 65a8e2989ece6dc46df59b0768184028257f913843Evan Cheng RRX, // V = RRX X, Flag -> srl X, 1 + shift in carry flag. 666aa7197fb5aa478a5c813d41a11689bb6d8f7abcJim Grosbach 67e5165490b7ba24bb2f3043399e0d60e7f3bcf8a5Jim Grosbach VMOVRRD, // double to two gprs. 68e5165490b7ba24bb2f3043399e0d60e7f3bcf8a5Jim Grosbach VMOVDRR, // Two gprs to double. 6964f4fa5e0eb505eec3a72041bec6b3a7f7739dedLauro Ramos Venancio 70861986401e05e437cb33bfd8320d510b956fe41eEvan Cheng EH_SJLJ_SETJMP, // SjLj exception handling setjmp. 71861986401e05e437cb33bfd8320d510b956fe41eEvan Cheng EH_SJLJ_LONGJMP, // SjLj exception handling longjmp. 720e0da734bbdfa1d3f55cd04db31d83b97e4556f7Jim Grosbach 735bafff36c798608a189c517d37527e4a38863071Bob Wilson THREAD_POINTER, 745bafff36c798608a189c517d37527e4a38863071Bob Wilson 75861986401e05e437cb33bfd8320d510b956fe41eEvan Cheng DYN_ALLOC, // Dynamic allocation on the stack. 76861986401e05e437cb33bfd8320d510b956fe41eEvan Cheng 773728e96a6c0f68f4f5b656c2372e9cbbe6e74d86Jim Grosbach MEMBARRIER, // Memory barrier 783728e96a6c0f68f4f5b656c2372e9cbbe6e74d86Jim Grosbach SYNCBARRIER, // Memory sync barrier 793728e96a6c0f68f4f5b656c2372e9cbbe6e74d86Jim Grosbach 805bafff36c798608a189c517d37527e4a38863071Bob Wilson VCEQ, // Vector compare equal. 815bafff36c798608a189c517d37527e4a38863071Bob Wilson VCGE, // Vector compare greater than or equal. 825bafff36c798608a189c517d37527e4a38863071Bob Wilson VCGEU, // Vector compare unsigned greater than or equal. 835bafff36c798608a189c517d37527e4a38863071Bob Wilson VCGT, // Vector compare greater than. 845bafff36c798608a189c517d37527e4a38863071Bob Wilson VCGTU, // Vector compare unsigned greater than. 855bafff36c798608a189c517d37527e4a38863071Bob Wilson VTST, // Vector test bits. 865bafff36c798608a189c517d37527e4a38863071Bob Wilson 875bafff36c798608a189c517d37527e4a38863071Bob Wilson // Vector shift by immediate: 885bafff36c798608a189c517d37527e4a38863071Bob Wilson VSHL, // ...left 895bafff36c798608a189c517d37527e4a38863071Bob Wilson VSHRs, // ...right (signed) 905bafff36c798608a189c517d37527e4a38863071Bob Wilson VSHRu, // ...right (unsigned) 915bafff36c798608a189c517d37527e4a38863071Bob Wilson VSHLLs, // ...left long (signed) 925bafff36c798608a189c517d37527e4a38863071Bob Wilson VSHLLu, // ...left long (unsigned) 935bafff36c798608a189c517d37527e4a38863071Bob Wilson VSHLLi, // ...left long (with maximum shift count) 945bafff36c798608a189c517d37527e4a38863071Bob Wilson VSHRN, // ...right narrow 955bafff36c798608a189c517d37527e4a38863071Bob Wilson 965bafff36c798608a189c517d37527e4a38863071Bob Wilson // Vector rounding shift by immediate: 975bafff36c798608a189c517d37527e4a38863071Bob Wilson VRSHRs, // ...right (signed) 985bafff36c798608a189c517d37527e4a38863071Bob Wilson VRSHRu, // ...right (unsigned) 995bafff36c798608a189c517d37527e4a38863071Bob Wilson VRSHRN, // ...right narrow 1005bafff36c798608a189c517d37527e4a38863071Bob Wilson 1015bafff36c798608a189c517d37527e4a38863071Bob Wilson // Vector saturating shift by immediate: 1025bafff36c798608a189c517d37527e4a38863071Bob Wilson VQSHLs, // ...left (signed) 1035bafff36c798608a189c517d37527e4a38863071Bob Wilson VQSHLu, // ...left (unsigned) 1045bafff36c798608a189c517d37527e4a38863071Bob Wilson VQSHLsu, // ...left (signed to unsigned) 1055bafff36c798608a189c517d37527e4a38863071Bob Wilson VQSHRNs, // ...right narrow (signed) 1065bafff36c798608a189c517d37527e4a38863071Bob Wilson VQSHRNu, // ...right narrow (unsigned) 1075bafff36c798608a189c517d37527e4a38863071Bob Wilson VQSHRNsu, // ...right narrow (signed to unsigned) 1085bafff36c798608a189c517d37527e4a38863071Bob Wilson 1095bafff36c798608a189c517d37527e4a38863071Bob Wilson // Vector saturating rounding shift by immediate: 1105bafff36c798608a189c517d37527e4a38863071Bob Wilson VQRSHRNs, // ...right narrow (signed) 1115bafff36c798608a189c517d37527e4a38863071Bob Wilson VQRSHRNu, // ...right narrow (unsigned) 1125bafff36c798608a189c517d37527e4a38863071Bob Wilson VQRSHRNsu, // ...right narrow (signed to unsigned) 1135bafff36c798608a189c517d37527e4a38863071Bob Wilson 1145bafff36c798608a189c517d37527e4a38863071Bob Wilson // Vector shift and insert: 1155bafff36c798608a189c517d37527e4a38863071Bob Wilson VSLI, // ...left 1165bafff36c798608a189c517d37527e4a38863071Bob Wilson VSRI, // ...right 1175bafff36c798608a189c517d37527e4a38863071Bob Wilson 1185bafff36c798608a189c517d37527e4a38863071Bob Wilson // Vector get lane (VMOV scalar to ARM core register) 1195bafff36c798608a189c517d37527e4a38863071Bob Wilson // (These are used for 8- and 16-bit element types only.) 1205bafff36c798608a189c517d37527e4a38863071Bob Wilson VGETLANEu, // zero-extend vector extract element 1215bafff36c798608a189c517d37527e4a38863071Bob Wilson VGETLANEs, // sign-extend vector extract element 1225bafff36c798608a189c517d37527e4a38863071Bob Wilson 123c1d287b4b73487b6ab094a253a7357addc1d8b84Bob Wilson // Vector duplicate: 124c1d287b4b73487b6ab094a253a7357addc1d8b84Bob Wilson VDUP, 1250ce371082565330672c276f76297f46b362d74b7Bob Wilson VDUPLANE, 126a599bff101095e528198ae85739fe8b97ffba82bBob Wilson 127d8e1757eacbcbae6657558f40fdada4279a9d1edBob Wilson // Vector shuffles: 128de95c1b88be44d4af916af8fba9d7940b7e98e32Bob Wilson VEXT, // extract 129d8e1757eacbcbae6657558f40fdada4279a9d1edBob Wilson VREV64, // reverse elements within 64-bit doublewords 130d8e1757eacbcbae6657558f40fdada4279a9d1edBob Wilson VREV32, // reverse elements within 32-bit words 1311c8e581832440a114c9587d41473d107de4cac74Anton Korobeynikov VREV16, // reverse elements within 16-bit halfwords 132c692cb77aaa8b16bcc7fe0c70d47adce94c43911Bob Wilson VZIP, // zip (interleave) 133c692cb77aaa8b16bcc7fe0c70d47adce94c43911Bob Wilson VUZP, // unzip (deinterleave) 134051cfd683f698b0061656fbff01d3971d2f3d58cAnton Korobeynikov VTRN // transpose 135a8e2989ece6dc46df59b0768184028257f913843Evan Cheng }; 136a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } 137a8e2989ece6dc46df59b0768184028257f913843Evan Cheng 1385bafff36c798608a189c517d37527e4a38863071Bob Wilson /// Define some predicates that are used for node matching. 1395bafff36c798608a189c517d37527e4a38863071Bob Wilson namespace ARM { 1405bafff36c798608a189c517d37527e4a38863071Bob Wilson /// getVMOVImm - If this is a build_vector of constants which can be 1415bafff36c798608a189c517d37527e4a38863071Bob Wilson /// formed by using a VMOV instruction of the specified element size, 1425bafff36c798608a189c517d37527e4a38863071Bob Wilson /// return the constant being splatted. The ByteSize field indicates the 1435bafff36c798608a189c517d37527e4a38863071Bob Wilson /// number of bytes of each element [1248]. 1445bafff36c798608a189c517d37527e4a38863071Bob Wilson SDValue getVMOVImm(SDNode *N, unsigned ByteSize, SelectionDAG &DAG); 14539382427f1095f089d73a7dd3d9a371dea75b781Evan Cheng 14639382427f1095f089d73a7dd3d9a371dea75b781Evan Cheng /// getVFPf32Imm / getVFPf64Imm - If the given fp immediate can be 14739382427f1095f089d73a7dd3d9a371dea75b781Evan Cheng /// materialized with a VMOV.f32 / VMOV.f64 (i.e. fconsts / fconstd) 14839382427f1095f089d73a7dd3d9a371dea75b781Evan Cheng /// instruction, returns its 8-bit integer representation. Otherwise, 14939382427f1095f089d73a7dd3d9a371dea75b781Evan Cheng /// returns -1. 15039382427f1095f089d73a7dd3d9a371dea75b781Evan Cheng int getVFPf32Imm(const APFloat &FPImm); 15139382427f1095f089d73a7dd3d9a371dea75b781Evan Cheng int getVFPf64Imm(const APFloat &FPImm); 1525bafff36c798608a189c517d37527e4a38863071Bob Wilson } 1535bafff36c798608a189c517d37527e4a38863071Bob Wilson 154261f2a2337990bc7cc3d9e20d3338de54b26c74cBob Wilson //===--------------------------------------------------------------------===// 15580dae195c75a3ef38854645ae3cf41f8ae835644Dale Johannesen // ARMTargetLowering - ARM Implementation of the TargetLowering interface 1566aa7197fb5aa478a5c813d41a11689bb6d8f7abcJim Grosbach 157a8e2989ece6dc46df59b0768184028257f913843Evan Cheng class ARMTargetLowering : public TargetLowering { 158a8e2989ece6dc46df59b0768184028257f913843Evan Cheng int VarArgsFrameIndex; // FrameIndex for start of varargs area. 159a8e2989ece6dc46df59b0768184028257f913843Evan Cheng public: 16061e729e2e9517ab2d8887bab86fb377900fa1081Dan Gohman explicit ARMTargetLowering(TargetMachine &TM); 161a8e2989ece6dc46df59b0768184028257f913843Evan Cheng 162475871a144eb604ddaf37503397ba0941442e5fbDan Gohman virtual SDValue LowerOperation(SDValue Op, SelectionDAG &DAG); 1631607f05cb7d77d01ce521a30232faa389dbed4e2Duncan Sands 1641607f05cb7d77d01ce521a30232faa389dbed4e2Duncan Sands /// ReplaceNodeResults - Replace the results of node with an illegal result 1651607f05cb7d77d01ce521a30232faa389dbed4e2Duncan Sands /// type with new values built out of custom code. 1661607f05cb7d77d01ce521a30232faa389dbed4e2Duncan Sands /// 1671607f05cb7d77d01ce521a30232faa389dbed4e2Duncan Sands virtual void ReplaceNodeResults(SDNode *N, SmallVectorImpl<SDValue>&Results, 1681607f05cb7d77d01ce521a30232faa389dbed4e2Duncan Sands SelectionDAG &DAG); 1691607f05cb7d77d01ce521a30232faa389dbed4e2Duncan Sands 170475871a144eb604ddaf37503397ba0941442e5fbDan Gohman virtual SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const; 1716aa7197fb5aa478a5c813d41a11689bb6d8f7abcJim Grosbach 172a8e2989ece6dc46df59b0768184028257f913843Evan Cheng virtual const char *getTargetNodeName(unsigned Opcode) const; 173a8e2989ece6dc46df59b0768184028257f913843Evan Cheng 174ff9b373e8f5006c629af81e2619778b4c4f5249eEvan Cheng virtual MachineBasicBlock *EmitInstrWithCustomInserter(MachineInstr *MI, 175fb2e752e4175920d0531f2afc93a23d0cdf4db14Evan Cheng MachineBasicBlock *MBB, 176fb2e752e4175920d0531f2afc93a23d0cdf4db14Evan Cheng DenseMap<MachineBasicBlock*, MachineBasicBlock*>*) const; 177a8e2989ece6dc46df59b0768184028257f913843Evan Cheng 178af5663405834ca7cf4a847f2efa2d624ce99b1d8Bill Wendling /// allowsUnalignedMemoryAccesses - Returns true if the target allows 179af5663405834ca7cf4a847f2efa2d624ce99b1d8Bill Wendling /// unaligned memory accesses. of the specified type. 180af5663405834ca7cf4a847f2efa2d624ce99b1d8Bill Wendling /// FIXME: Add getOptimalMemOpType to implement memcpy with NEON? 181af5663405834ca7cf4a847f2efa2d624ce99b1d8Bill Wendling virtual bool allowsUnalignedMemoryAccesses(EVT VT) const; 182af5663405834ca7cf4a847f2efa2d624ce99b1d8Bill Wendling 183c9addb74883fef318140272768422656a694341fChris Lattner /// isLegalAddressingMode - Return true if the addressing mode represented 184c9addb74883fef318140272768422656a694341fChris Lattner /// by AM is legal for this target, for a load/store of the specified type. 185c9addb74883fef318140272768422656a694341fChris Lattner virtual bool isLegalAddressingMode(const AddrMode &AM, const Type *Ty)const; 186e6c835f42418c0fae6b63908d3c576a26d64cab2Evan Cheng bool isLegalT2ScaledAddressingMode(const AddrMode &AM, EVT VT) const; 1876aa7197fb5aa478a5c813d41a11689bb6d8f7abcJim Grosbach 18877e4751011da2d6afa930ab91f7baee39e7c7e89Evan Cheng /// isLegalICmpImmediate - Return true if the specified immediate is legal 18977e4751011da2d6afa930ab91f7baee39e7c7e89Evan Cheng /// icmp immediate, that is the target has icmp instructions which can compare 19077e4751011da2d6afa930ab91f7baee39e7c7e89Evan Cheng /// a register against the immediate without having to materialize the 19177e4751011da2d6afa930ab91f7baee39e7c7e89Evan Cheng /// immediate into a register. 19206b53c0d51f029eb754b40350faf5ba4b33c4bcbEvan Cheng virtual bool isLegalICmpImmediate(int64_t Imm) const; 19377e4751011da2d6afa930ab91f7baee39e7c7e89Evan Cheng 194a8e2989ece6dc46df59b0768184028257f913843Evan Cheng /// getPreIndexedAddressParts - returns true by value, base pointer and 195a8e2989ece6dc46df59b0768184028257f913843Evan Cheng /// offset pointer and addressing mode by reference if the node's address 196a8e2989ece6dc46df59b0768184028257f913843Evan Cheng /// can be legally represented as pre-indexed load / store address. 197475871a144eb604ddaf37503397ba0941442e5fbDan Gohman virtual bool getPreIndexedAddressParts(SDNode *N, SDValue &Base, 198475871a144eb604ddaf37503397ba0941442e5fbDan Gohman SDValue &Offset, 199a8e2989ece6dc46df59b0768184028257f913843Evan Cheng ISD::MemIndexedMode &AM, 20073e0914848662404cf2aa18eb049ff5aae543388Dan Gohman SelectionDAG &DAG) const; 201a8e2989ece6dc46df59b0768184028257f913843Evan Cheng 202a8e2989ece6dc46df59b0768184028257f913843Evan Cheng /// getPostIndexedAddressParts - returns true by value, base pointer and 203a8e2989ece6dc46df59b0768184028257f913843Evan Cheng /// offset pointer and addressing mode by reference if this node can be 204a8e2989ece6dc46df59b0768184028257f913843Evan Cheng /// combined with a load / store to form a post-indexed load / store. 205a8e2989ece6dc46df59b0768184028257f913843Evan Cheng virtual bool getPostIndexedAddressParts(SDNode *N, SDNode *Op, 206475871a144eb604ddaf37503397ba0941442e5fbDan Gohman SDValue &Base, SDValue &Offset, 207a8e2989ece6dc46df59b0768184028257f913843Evan Cheng ISD::MemIndexedMode &AM, 20873e0914848662404cf2aa18eb049ff5aae543388Dan Gohman SelectionDAG &DAG) const; 209a8e2989ece6dc46df59b0768184028257f913843Evan Cheng 210475871a144eb604ddaf37503397ba0941442e5fbDan Gohman virtual void computeMaskedBitsForTargetNode(const SDValue Op, 211977a76fbb6ea1b87dfd7fbbe2ae2afb63e982ff3Dan Gohman const APInt &Mask, 2126aa7197fb5aa478a5c813d41a11689bb6d8f7abcJim Grosbach APInt &KnownZero, 213fd29e0eb060ea8b4d490860329234d2ae5f5952eDan Gohman APInt &KnownOne, 214ea859be53ca13a1547c4675549946b74dc3c6f41Dan Gohman const SelectionDAG &DAG, 215a8e2989ece6dc46df59b0768184028257f913843Evan Cheng unsigned Depth) const; 216af5663405834ca7cf4a847f2efa2d624ce99b1d8Bill Wendling 217af5663405834ca7cf4a847f2efa2d624ce99b1d8Bill Wendling 2184234f57fa02b1f04a9f52a7b3c2aa22d32ac521cChris Lattner ConstraintType getConstraintType(const std::string &Constraint) const; 2196aa7197fb5aa478a5c813d41a11689bb6d8f7abcJim Grosbach std::pair<unsigned, const TargetRegisterClass*> 220a8e2989ece6dc46df59b0768184028257f913843Evan Cheng getRegForInlineAsmConstraint(const std::string &Constraint, 221e50ed30282bb5b4a9ed952580523f2dda16215acOwen Anderson EVT VT) const; 222a8e2989ece6dc46df59b0768184028257f913843Evan Cheng std::vector<unsigned> 223a8e2989ece6dc46df59b0768184028257f913843Evan Cheng getRegClassForInlineAsmConstraint(const std::string &Constraint, 224e50ed30282bb5b4a9ed952580523f2dda16215acOwen Anderson EVT VT) const; 225f1ba1cad387dc52f3c2c5afc665edf9caad00992Rafael Espindola 226bf6396bed0597238110aad5b680fd18a4f8769faBob Wilson /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops 227bf6396bed0597238110aad5b680fd18a4f8769faBob Wilson /// vector. If it is invalid, don't add anything to Ops. If hasMemory is 228bf6396bed0597238110aad5b680fd18a4f8769faBob Wilson /// true it means one of the asm constraint of the inline asm instruction 229bf6396bed0597238110aad5b680fd18a4f8769faBob Wilson /// being processed is 'm'. 230bf6396bed0597238110aad5b680fd18a4f8769faBob Wilson virtual void LowerAsmOperandForConstraint(SDValue Op, 231bf6396bed0597238110aad5b680fd18a4f8769faBob Wilson char ConstraintLetter, 232bf6396bed0597238110aad5b680fd18a4f8769faBob Wilson bool hasMemory, 233bf6396bed0597238110aad5b680fd18a4f8769faBob Wilson std::vector<SDValue> &Ops, 234bf6396bed0597238110aad5b680fd18a4f8769faBob Wilson SelectionDAG &DAG) const; 2356aa7197fb5aa478a5c813d41a11689bb6d8f7abcJim Grosbach 236707e0184233f27e0e9f9aee0309f2daab8cfe7f8Dan Gohman virtual const ARMSubtarget* getSubtarget() { 237707e0184233f27e0e9f9aee0309f2daab8cfe7f8Dan Gohman return Subtarget; 238f1ba1cad387dc52f3c2c5afc665edf9caad00992Rafael Espindola } 239f1ba1cad387dc52f3c2c5afc665edf9caad00992Rafael Espindola 240b4202b84d7e54efe5e144885c7da63e6cc465f80Bill Wendling /// getFunctionAlignment - Return the Log2 alignment of this function. 24120c568f366be211323eeaf0e45ef053278ec9ddcBill Wendling virtual unsigned getFunctionAlignment(const Function *F) const; 24220c568f366be211323eeaf0e45ef053278ec9ddcBill Wendling 243d0ac234b1b3a88946ad8bb52677764f3e3eeb8b3Anton Korobeynikov bool isShuffleMaskLegal(const SmallVectorImpl<int> &M, EVT VT) const; 24448e19352840a5f7012493ead894e81a2dbec1778Anton Korobeynikov bool isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const; 24539382427f1095f089d73a7dd3d9a371dea75b781Evan Cheng 24639382427f1095f089d73a7dd3d9a371dea75b781Evan Cheng /// isFPImmLegal - Returns true if the target can instruction select the 24739382427f1095f089d73a7dd3d9a371dea75b781Evan Cheng /// specified FP immediate natively. If false, the legalizer will 24839382427f1095f089d73a7dd3d9a371dea75b781Evan Cheng /// materialize the FP immediate as a load from a constant pool. 24939382427f1095f089d73a7dd3d9a371dea75b781Evan Cheng virtual bool isFPImmLegal(const APFloat &Imm, EVT VT) const; 25039382427f1095f089d73a7dd3d9a371dea75b781Evan Cheng 251a8e2989ece6dc46df59b0768184028257f913843Evan Cheng private: 252a8e2989ece6dc46df59b0768184028257f913843Evan Cheng /// Subtarget - Keep a pointer to the ARMSubtarget around so that we can 253a8e2989ece6dc46df59b0768184028257f913843Evan Cheng /// make the right decision when generating code for different targets. 254a8e2989ece6dc46df59b0768184028257f913843Evan Cheng const ARMSubtarget *Subtarget; 255a8e2989ece6dc46df59b0768184028257f913843Evan Cheng 256d2559bf3f30cc7400483825414489ec0fb36481aBob Wilson /// ARMPCLabelIndex - Keep track of the number of ARM PC labels created. 257a8e2989ece6dc46df59b0768184028257f913843Evan Cheng /// 258a8e2989ece6dc46df59b0768184028257f913843Evan Cheng unsigned ARMPCLabelIndex; 259a8e2989ece6dc46df59b0768184028257f913843Evan Cheng 260e50ed30282bb5b4a9ed952580523f2dda16215acOwen Anderson void addTypeForNEON(EVT VT, EVT PromotedLdStVT, EVT PromotedBitwiseVT); 261e50ed30282bb5b4a9ed952580523f2dda16215acOwen Anderson void addDRTypeForNEON(EVT VT); 262e50ed30282bb5b4a9ed952580523f2dda16215acOwen Anderson void addQRTypeForNEON(EVT VT); 2635bafff36c798608a189c517d37527e4a38863071Bob Wilson 2645bafff36c798608a189c517d37527e4a38863071Bob Wilson typedef SmallVector<std::pair<unsigned, SDValue>, 8> RegsToPassVector; 26598ca4f2a325f72374a477f9deba7d09e8999c29bDan Gohman void PassF64ArgInRegs(DebugLoc dl, SelectionDAG &DAG, 2665bafff36c798608a189c517d37527e4a38863071Bob Wilson SDValue Chain, SDValue &Arg, 2675bafff36c798608a189c517d37527e4a38863071Bob Wilson RegsToPassVector &RegsToPass, 2685bafff36c798608a189c517d37527e4a38863071Bob Wilson CCValAssign &VA, CCValAssign &NextVA, 2695bafff36c798608a189c517d37527e4a38863071Bob Wilson SDValue &StackPtr, 2705bafff36c798608a189c517d37527e4a38863071Bob Wilson SmallVector<SDValue, 8> &MemOpChains, 2715bafff36c798608a189c517d37527e4a38863071Bob Wilson ISD::ArgFlagsTy Flags); 2725bafff36c798608a189c517d37527e4a38863071Bob Wilson SDValue GetF64FormalArgument(CCValAssign &VA, CCValAssign &NextVA, 2735bafff36c798608a189c517d37527e4a38863071Bob Wilson SDValue &Root, SelectionDAG &DAG, DebugLoc dl); 2745bafff36c798608a189c517d37527e4a38863071Bob Wilson 27565c3c8f323198b99b88b109654194540cf9b3fa5Sandeep Patel CCAssignFn *CCAssignFnForNode(CallingConv::ID CC, bool Return, bool isVarArg) const; 27698ca4f2a325f72374a477f9deba7d09e8999c29bDan Gohman SDValue LowerMemOpCallTo(SDValue Chain, SDValue StackPtr, SDValue Arg, 27798ca4f2a325f72374a477f9deba7d09e8999c29bDan Gohman DebugLoc dl, SelectionDAG &DAG, 27898ca4f2a325f72374a477f9deba7d09e8999c29bDan Gohman const CCValAssign &VA, 27998ca4f2a325f72374a477f9deba7d09e8999c29bDan Gohman ISD::ArgFlagsTy Flags); 280a599bff101095e528198ae85739fe8b97ffba82bBob Wilson SDValue LowerINTRINSIC_W_CHAIN(SDValue Op, SelectionDAG &DAG); 2810e0da734bbdfa1d3f55cd04db31d83b97e4556f7Jim Grosbach SDValue LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG); 282ddb16df91257e4c4d2be5343e2c7c7ecbfbe8bf4Bob Wilson SDValue LowerBlockAddress(SDValue Op, SelectionDAG &DAG); 283475871a144eb604ddaf37503397ba0941442e5fbDan Gohman SDValue LowerGlobalAddressDarwin(SDValue Op, SelectionDAG &DAG); 284475871a144eb604ddaf37503397ba0941442e5fbDan Gohman SDValue LowerGlobalAddressELF(SDValue Op, SelectionDAG &DAG); 285475871a144eb604ddaf37503397ba0941442e5fbDan Gohman SDValue LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG); 286475871a144eb604ddaf37503397ba0941442e5fbDan Gohman SDValue LowerToTLSGeneralDynamicModel(GlobalAddressSDNode *GA, 28764f4fa5e0eb505eec3a72041bec6b3a7f7739dedLauro Ramos Venancio SelectionDAG &DAG); 288475871a144eb604ddaf37503397ba0941442e5fbDan Gohman SDValue LowerToTLSExecModels(GlobalAddressSDNode *GA, 2894102eb57bbeecbbf5b5b5122ed1ecd4cd5487878Evan Cheng SelectionDAG &DAG); 290475871a144eb604ddaf37503397ba0941442e5fbDan Gohman SDValue LowerGLOBAL_OFFSET_TABLE(SDValue Op, SelectionDAG &DAG); 291475871a144eb604ddaf37503397ba0941442e5fbDan Gohman SDValue LowerBR_JT(SDValue Op, SelectionDAG &DAG); 29206b53c0d51f029eb754b40350faf5ba4b33c4bcbEvan Cheng SDValue LowerSELECT_CC(SDValue Op, SelectionDAG &DAG); 29306b53c0d51f029eb754b40350faf5ba4b33c4bcbEvan Cheng SDValue LowerBR_CC(SDValue Op, SelectionDAG &DAG); 2940e0da734bbdfa1d3f55cd04db31d83b97e4556f7Jim Grosbach SDValue LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG); 295861986401e05e437cb33bfd8320d510b956fe41eEvan Cheng SDValue LowerDYNAMIC_STACKALLOC(SDValue Op, SelectionDAG &DAG); 29606b53c0d51f029eb754b40350faf5ba4b33c4bcbEvan Cheng SDValue LowerShiftRightParts(SDValue Op, SelectionDAG &DAG); 29706b53c0d51f029eb754b40350faf5ba4b33c4bcbEvan Cheng SDValue LowerShiftLeftParts(SDValue Op, SelectionDAG &DAG); 298475871a144eb604ddaf37503397ba0941442e5fbDan Gohman 2990f502f6f44f2756f5cb7b17d8f1d8eae000d51b4Dale Johannesen SDValue EmitTargetCodeForMemcpy(SelectionDAG &DAG, DebugLoc dl, 300475871a144eb604ddaf37503397ba0941442e5fbDan Gohman SDValue Chain, 301475871a144eb604ddaf37503397ba0941442e5fbDan Gohman SDValue Dst, SDValue Src, 302475871a144eb604ddaf37503397ba0941442e5fbDan Gohman SDValue Size, unsigned Align, 303707e0184233f27e0e9f9aee0309f2daab8cfe7f8Dan Gohman bool AlwaysInline, 3041f13c686df75ddbbe15b208606ece4846d7479a8Dan Gohman const Value *DstSV, uint64_t DstSVOff, 3051f13c686df75ddbbe15b208606ece4846d7479a8Dan Gohman const Value *SrcSV, uint64_t SrcSVOff); 30698ca4f2a325f72374a477f9deba7d09e8999c29bDan Gohman SDValue LowerCallResult(SDValue Chain, SDValue InFlag, 30765c3c8f323198b99b88b109654194540cf9b3fa5Sandeep Patel CallingConv::ID CallConv, bool isVarArg, 30898ca4f2a325f72374a477f9deba7d09e8999c29bDan Gohman const SmallVectorImpl<ISD::InputArg> &Ins, 30998ca4f2a325f72374a477f9deba7d09e8999c29bDan Gohman DebugLoc dl, SelectionDAG &DAG, 31098ca4f2a325f72374a477f9deba7d09e8999c29bDan Gohman SmallVectorImpl<SDValue> &InVals); 31198ca4f2a325f72374a477f9deba7d09e8999c29bDan Gohman 31298ca4f2a325f72374a477f9deba7d09e8999c29bDan Gohman virtual SDValue 31398ca4f2a325f72374a477f9deba7d09e8999c29bDan Gohman LowerFormalArguments(SDValue Chain, 31465c3c8f323198b99b88b109654194540cf9b3fa5Sandeep Patel CallingConv::ID CallConv, bool isVarArg, 31598ca4f2a325f72374a477f9deba7d09e8999c29bDan Gohman const SmallVectorImpl<ISD::InputArg> &Ins, 31698ca4f2a325f72374a477f9deba7d09e8999c29bDan Gohman DebugLoc dl, SelectionDAG &DAG, 31798ca4f2a325f72374a477f9deba7d09e8999c29bDan Gohman SmallVectorImpl<SDValue> &InVals); 31898ca4f2a325f72374a477f9deba7d09e8999c29bDan Gohman 31998ca4f2a325f72374a477f9deba7d09e8999c29bDan Gohman virtual SDValue 320022d9e1cef7586a80a96446ae8691a37def9bbf4Evan Cheng LowerCall(SDValue Chain, SDValue Callee, 32165c3c8f323198b99b88b109654194540cf9b3fa5Sandeep Patel CallingConv::ID CallConv, bool isVarArg, 3220c439eb2c8397996cbccaf2798e598052d9982c8Evan Cheng bool &isTailCall, 32398ca4f2a325f72374a477f9deba7d09e8999c29bDan Gohman const SmallVectorImpl<ISD::OutputArg> &Outs, 32498ca4f2a325f72374a477f9deba7d09e8999c29bDan Gohman const SmallVectorImpl<ISD::InputArg> &Ins, 32598ca4f2a325f72374a477f9deba7d09e8999c29bDan Gohman DebugLoc dl, SelectionDAG &DAG, 32698ca4f2a325f72374a477f9deba7d09e8999c29bDan Gohman SmallVectorImpl<SDValue> &InVals); 32798ca4f2a325f72374a477f9deba7d09e8999c29bDan Gohman 32898ca4f2a325f72374a477f9deba7d09e8999c29bDan Gohman virtual SDValue 32998ca4f2a325f72374a477f9deba7d09e8999c29bDan Gohman LowerReturn(SDValue Chain, 33065c3c8f323198b99b88b109654194540cf9b3fa5Sandeep Patel CallingConv::ID CallConv, bool isVarArg, 33198ca4f2a325f72374a477f9deba7d09e8999c29bDan Gohman const SmallVectorImpl<ISD::OutputArg> &Outs, 33298ca4f2a325f72374a477f9deba7d09e8999c29bDan Gohman DebugLoc dl, SelectionDAG &DAG); 33306b53c0d51f029eb754b40350faf5ba4b33c4bcbEvan Cheng 33406b53c0d51f029eb754b40350faf5ba4b33c4bcbEvan Cheng SDValue getARMCmp(SDValue LHS, SDValue RHS, ISD::CondCode CC, 33506b53c0d51f029eb754b40350faf5ba4b33c4bcbEvan Cheng SDValue &ARMCC, SelectionDAG &DAG, DebugLoc dl); 3365278eb802fae2ee1a7b2a428596bc364d8bcd9dbJim Grosbach 337e801dc4a7b89f68f40ff2753de988c482d4d117fJim Grosbach MachineBasicBlock *EmitAtomicCmpSwap(MachineInstr *MI, 338e801dc4a7b89f68f40ff2753de988c482d4d117fJim Grosbach MachineBasicBlock *BB, 339e801dc4a7b89f68f40ff2753de988c482d4d117fJim Grosbach unsigned Size) const; 340e801dc4a7b89f68f40ff2753de988c482d4d117fJim Grosbach MachineBasicBlock *EmitAtomicBinary(MachineInstr *MI, 341e801dc4a7b89f68f40ff2753de988c482d4d117fJim Grosbach MachineBasicBlock *BB, 342e801dc4a7b89f68f40ff2753de988c482d4d117fJim Grosbach unsigned Size, 343e801dc4a7b89f68f40ff2753de988c482d4d117fJim Grosbach unsigned BinOpcode) const; 3445278eb802fae2ee1a7b2a428596bc364d8bcd9dbJim Grosbach 345a8e2989ece6dc46df59b0768184028257f913843Evan Cheng }; 346a8e2989ece6dc46df59b0768184028257f913843Evan Cheng} 347a8e2989ece6dc46df59b0768184028257f913843Evan Cheng 348a8e2989ece6dc46df59b0768184028257f913843Evan Cheng#endif // ARMISELLOWERING_H 349