ARMISelLowering.h revision 218977b53eb215e5534db2f727d109ab18817cc1
1a8e2989ece6dc46df59b0768184028257f913843Evan Cheng//===-- ARMISelLowering.h - ARM DAG Lowering Interface ----------*- C++ -*-===// 2a8e2989ece6dc46df59b0768184028257f913843Evan Cheng// 3a8e2989ece6dc46df59b0768184028257f913843Evan Cheng// The LLVM Compiler Infrastructure 4a8e2989ece6dc46df59b0768184028257f913843Evan Cheng// 54ee451de366474b9c228b4e5fa573795a715216dChris Lattner// This file is distributed under the University of Illinois Open Source 64ee451de366474b9c228b4e5fa573795a715216dChris Lattner// License. See LICENSE.TXT for details. 7a8e2989ece6dc46df59b0768184028257f913843Evan Cheng// 8a8e2989ece6dc46df59b0768184028257f913843Evan Cheng//===----------------------------------------------------------------------===// 9a8e2989ece6dc46df59b0768184028257f913843Evan Cheng// 10a8e2989ece6dc46df59b0768184028257f913843Evan Cheng// This file defines the interfaces that ARM uses to lower LLVM code into a 11a8e2989ece6dc46df59b0768184028257f913843Evan Cheng// selection DAG. 12a8e2989ece6dc46df59b0768184028257f913843Evan Cheng// 13a8e2989ece6dc46df59b0768184028257f913843Evan Cheng//===----------------------------------------------------------------------===// 14a8e2989ece6dc46df59b0768184028257f913843Evan Cheng 15a8e2989ece6dc46df59b0768184028257f913843Evan Cheng#ifndef ARMISELLOWERING_H 16a8e2989ece6dc46df59b0768184028257f913843Evan Cheng#define ARMISELLOWERING_H 17a8e2989ece6dc46df59b0768184028257f913843Evan Cheng 18f1ba1cad387dc52f3c2c5afc665edf9caad00992Rafael Espindola#include "ARMSubtarget.h" 19a8e2989ece6dc46df59b0768184028257f913843Evan Cheng#include "llvm/Target/TargetLowering.h" 20a8e2989ece6dc46df59b0768184028257f913843Evan Cheng#include "llvm/CodeGen/SelectionDAG.h" 211f595bb42950088ccb8246e6b065a96027b46ec6Bob Wilson#include "llvm/CodeGen/CallingConvLower.h" 22a8e2989ece6dc46df59b0768184028257f913843Evan Cheng#include <vector> 23a8e2989ece6dc46df59b0768184028257f913843Evan Cheng 24a8e2989ece6dc46df59b0768184028257f913843Evan Chengnamespace llvm { 25a8e2989ece6dc46df59b0768184028257f913843Evan Cheng class ARMConstantPoolValue; 26a8e2989ece6dc46df59b0768184028257f913843Evan Cheng 27a8e2989ece6dc46df59b0768184028257f913843Evan Cheng namespace ARMISD { 28a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // ARM Specific DAG Nodes 29a8e2989ece6dc46df59b0768184028257f913843Evan Cheng enum NodeType { 306aa7197fb5aa478a5c813d41a11689bb6d8f7abcJim Grosbach // Start the numbering where the builtin ops and target ops leave off. 310ba2bcfcc3149a25d08aa8aa00fb6c34a4e25bddDan Gohman FIRST_NUMBER = ISD::BUILTIN_OP_END, 32a8e2989ece6dc46df59b0768184028257f913843Evan Cheng 33a8e2989ece6dc46df59b0768184028257f913843Evan Cheng Wrapper, // Wrapper - A wrapper node for TargetConstantPool, 34a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // TargetExternalSymbol, and TargetGlobalAddress. 35a8e2989ece6dc46df59b0768184028257f913843Evan Cheng WrapperJT, // WrapperJT - A wrapper node for TargetJumpTable 366aa7197fb5aa478a5c813d41a11689bb6d8f7abcJim Grosbach 37a8e2989ece6dc46df59b0768184028257f913843Evan Cheng CALL, // Function call. 38277f0741c5ea123b30360c382a153df238c31caeEvan Cheng CALL_PRED, // Function call that's predicable. 39a8e2989ece6dc46df59b0768184028257f913843Evan Cheng CALL_NOLINK, // Function call with branch not branch-and-link. 40a8e2989ece6dc46df59b0768184028257f913843Evan Cheng tCALL, // Thumb function call. 41a8e2989ece6dc46df59b0768184028257f913843Evan Cheng BRCOND, // Conditional branch. 42a8e2989ece6dc46df59b0768184028257f913843Evan Cheng BR_JT, // Jumptable branch. 435657c01949dca6c012ac60d242d1a8d2ffdf5603Evan Cheng BR2_JT, // Jumptable branch (2 level - jumptable entry is a jump). 44a8e2989ece6dc46df59b0768184028257f913843Evan Cheng RET_FLAG, // Return with a flag operand. 45a8e2989ece6dc46df59b0768184028257f913843Evan Cheng 46a8e2989ece6dc46df59b0768184028257f913843Evan Cheng PIC_ADD, // Add with a PC operand and a PIC label. 47a8e2989ece6dc46df59b0768184028257f913843Evan Cheng 48a8e2989ece6dc46df59b0768184028257f913843Evan Cheng CMP, // ARM compare instructions. 49c0309b48b560f119982c02a81416c8c1fd208648David Goodwin CMPZ, // ARM compare that sets only Z flag. 50a8e2989ece6dc46df59b0768184028257f913843Evan Cheng CMPFP, // ARM VFP compare instruction, sets FPSCR. 51a8e2989ece6dc46df59b0768184028257f913843Evan Cheng CMPFPw0, // ARM VFP compare against zero instruction, sets FPSCR. 52a8e2989ece6dc46df59b0768184028257f913843Evan Cheng FMSTAT, // ARM fmstat instruction. 53a8e2989ece6dc46df59b0768184028257f913843Evan Cheng CMOV, // ARM conditional move instructions. 54a8e2989ece6dc46df59b0768184028257f913843Evan Cheng CNEG, // ARM conditional negate instructions. 556aa7197fb5aa478a5c813d41a11689bb6d8f7abcJim Grosbach 56218977b53eb215e5534db2f727d109ab18817cc1Evan Cheng BCC_i64, 57218977b53eb215e5534db2f727d109ab18817cc1Evan Cheng 583482c8003ad0c88469b7333aaf658036e3fd0468Jim Grosbach RBIT, // ARM bitreverse instruction 593482c8003ad0c88469b7333aaf658036e3fd0468Jim Grosbach 6076a312b7d1c2b41394696510506967cd0794b831Bob Wilson FTOSI, // FP to sint within a FP register. 6176a312b7d1c2b41394696510506967cd0794b831Bob Wilson FTOUI, // FP to uint within a FP register. 6276a312b7d1c2b41394696510506967cd0794b831Bob Wilson SITOF, // sint to FP within a FP register. 6376a312b7d1c2b41394696510506967cd0794b831Bob Wilson UITOF, // uint to FP within a FP register. 6476a312b7d1c2b41394696510506967cd0794b831Bob Wilson 65a8e2989ece6dc46df59b0768184028257f913843Evan Cheng SRL_FLAG, // V,Flag = srl_flag X -> srl X, 1 + save carry out. 66a8e2989ece6dc46df59b0768184028257f913843Evan Cheng SRA_FLAG, // V,Flag = sra_flag X -> sra X, 1 + save carry out. 67a8e2989ece6dc46df59b0768184028257f913843Evan Cheng RRX, // V = RRX X, Flag -> srl X, 1 + shift in carry flag. 686aa7197fb5aa478a5c813d41a11689bb6d8f7abcJim Grosbach 69e5165490b7ba24bb2f3043399e0d60e7f3bcf8a5Jim Grosbach VMOVRRD, // double to two gprs. 70e5165490b7ba24bb2f3043399e0d60e7f3bcf8a5Jim Grosbach VMOVDRR, // Two gprs to double. 7164f4fa5e0eb505eec3a72041bec6b3a7f7739dedLauro Ramos Venancio 72861986401e05e437cb33bfd8320d510b956fe41eEvan Cheng EH_SJLJ_SETJMP, // SjLj exception handling setjmp. 73861986401e05e437cb33bfd8320d510b956fe41eEvan Cheng EH_SJLJ_LONGJMP, // SjLj exception handling longjmp. 740e0da734bbdfa1d3f55cd04db31d83b97e4556f7Jim Grosbach 7551e28e634880849ed9f7c02e93c08d25dd70291bDale Johannesen TC_RETURN, // Tail call return pseudo. 7651e28e634880849ed9f7c02e93c08d25dd70291bDale Johannesen 775bafff36c798608a189c517d37527e4a38863071Bob Wilson THREAD_POINTER, 785bafff36c798608a189c517d37527e4a38863071Bob Wilson 79861986401e05e437cb33bfd8320d510b956fe41eEvan Cheng DYN_ALLOC, // Dynamic allocation on the stack. 80861986401e05e437cb33bfd8320d510b956fe41eEvan Cheng 813728e96a6c0f68f4f5b656c2372e9cbbe6e74d86Jim Grosbach MEMBARRIER, // Memory barrier 823728e96a6c0f68f4f5b656c2372e9cbbe6e74d86Jim Grosbach SYNCBARRIER, // Memory sync barrier 833728e96a6c0f68f4f5b656c2372e9cbbe6e74d86Jim Grosbach 845bafff36c798608a189c517d37527e4a38863071Bob Wilson VCEQ, // Vector compare equal. 855bafff36c798608a189c517d37527e4a38863071Bob Wilson VCGE, // Vector compare greater than or equal. 865bafff36c798608a189c517d37527e4a38863071Bob Wilson VCGEU, // Vector compare unsigned greater than or equal. 875bafff36c798608a189c517d37527e4a38863071Bob Wilson VCGT, // Vector compare greater than. 885bafff36c798608a189c517d37527e4a38863071Bob Wilson VCGTU, // Vector compare unsigned greater than. 895bafff36c798608a189c517d37527e4a38863071Bob Wilson VTST, // Vector test bits. 905bafff36c798608a189c517d37527e4a38863071Bob Wilson 915bafff36c798608a189c517d37527e4a38863071Bob Wilson // Vector shift by immediate: 925bafff36c798608a189c517d37527e4a38863071Bob Wilson VSHL, // ...left 935bafff36c798608a189c517d37527e4a38863071Bob Wilson VSHRs, // ...right (signed) 945bafff36c798608a189c517d37527e4a38863071Bob Wilson VSHRu, // ...right (unsigned) 955bafff36c798608a189c517d37527e4a38863071Bob Wilson VSHLLs, // ...left long (signed) 965bafff36c798608a189c517d37527e4a38863071Bob Wilson VSHLLu, // ...left long (unsigned) 975bafff36c798608a189c517d37527e4a38863071Bob Wilson VSHLLi, // ...left long (with maximum shift count) 985bafff36c798608a189c517d37527e4a38863071Bob Wilson VSHRN, // ...right narrow 995bafff36c798608a189c517d37527e4a38863071Bob Wilson 1005bafff36c798608a189c517d37527e4a38863071Bob Wilson // Vector rounding shift by immediate: 1015bafff36c798608a189c517d37527e4a38863071Bob Wilson VRSHRs, // ...right (signed) 1025bafff36c798608a189c517d37527e4a38863071Bob Wilson VRSHRu, // ...right (unsigned) 1035bafff36c798608a189c517d37527e4a38863071Bob Wilson VRSHRN, // ...right narrow 1045bafff36c798608a189c517d37527e4a38863071Bob Wilson 1055bafff36c798608a189c517d37527e4a38863071Bob Wilson // Vector saturating shift by immediate: 1065bafff36c798608a189c517d37527e4a38863071Bob Wilson VQSHLs, // ...left (signed) 1075bafff36c798608a189c517d37527e4a38863071Bob Wilson VQSHLu, // ...left (unsigned) 1085bafff36c798608a189c517d37527e4a38863071Bob Wilson VQSHLsu, // ...left (signed to unsigned) 1095bafff36c798608a189c517d37527e4a38863071Bob Wilson VQSHRNs, // ...right narrow (signed) 1105bafff36c798608a189c517d37527e4a38863071Bob Wilson VQSHRNu, // ...right narrow (unsigned) 1115bafff36c798608a189c517d37527e4a38863071Bob Wilson VQSHRNsu, // ...right narrow (signed to unsigned) 1125bafff36c798608a189c517d37527e4a38863071Bob Wilson 1135bafff36c798608a189c517d37527e4a38863071Bob Wilson // Vector saturating rounding shift by immediate: 1145bafff36c798608a189c517d37527e4a38863071Bob Wilson VQRSHRNs, // ...right narrow (signed) 1155bafff36c798608a189c517d37527e4a38863071Bob Wilson VQRSHRNu, // ...right narrow (unsigned) 1165bafff36c798608a189c517d37527e4a38863071Bob Wilson VQRSHRNsu, // ...right narrow (signed to unsigned) 1175bafff36c798608a189c517d37527e4a38863071Bob Wilson 1185bafff36c798608a189c517d37527e4a38863071Bob Wilson // Vector shift and insert: 1195bafff36c798608a189c517d37527e4a38863071Bob Wilson VSLI, // ...left 1205bafff36c798608a189c517d37527e4a38863071Bob Wilson VSRI, // ...right 1215bafff36c798608a189c517d37527e4a38863071Bob Wilson 1225bafff36c798608a189c517d37527e4a38863071Bob Wilson // Vector get lane (VMOV scalar to ARM core register) 1235bafff36c798608a189c517d37527e4a38863071Bob Wilson // (These are used for 8- and 16-bit element types only.) 1245bafff36c798608a189c517d37527e4a38863071Bob Wilson VGETLANEu, // zero-extend vector extract element 1255bafff36c798608a189c517d37527e4a38863071Bob Wilson VGETLANEs, // sign-extend vector extract element 1265bafff36c798608a189c517d37527e4a38863071Bob Wilson 127c1d287b4b73487b6ab094a253a7357addc1d8b84Bob Wilson // Vector duplicate: 128c1d287b4b73487b6ab094a253a7357addc1d8b84Bob Wilson VDUP, 1290ce371082565330672c276f76297f46b362d74b7Bob Wilson VDUPLANE, 130a599bff101095e528198ae85739fe8b97ffba82bBob Wilson 131d8e1757eacbcbae6657558f40fdada4279a9d1edBob Wilson // Vector shuffles: 132de95c1b88be44d4af916af8fba9d7940b7e98e32Bob Wilson VEXT, // extract 133d8e1757eacbcbae6657558f40fdada4279a9d1edBob Wilson VREV64, // reverse elements within 64-bit doublewords 134d8e1757eacbcbae6657558f40fdada4279a9d1edBob Wilson VREV32, // reverse elements within 32-bit words 1351c8e581832440a114c9587d41473d107de4cac74Anton Korobeynikov VREV16, // reverse elements within 16-bit halfwords 136c692cb77aaa8b16bcc7fe0c70d47adce94c43911Bob Wilson VZIP, // zip (interleave) 137c692cb77aaa8b16bcc7fe0c70d47adce94c43911Bob Wilson VUZP, // unzip (deinterleave) 1389f6c4c141ffa9c8b13e90dce2f2285c4479ff403Bob Wilson VTRN, // transpose 1399f6c4c141ffa9c8b13e90dce2f2285c4479ff403Bob Wilson 14040cbe7d5d41d22d32e8ce773548f510fd1ee0ed9Bob Wilson // Operands of the standard BUILD_VECTOR node are not legalized, which 14140cbe7d5d41d22d32e8ce773548f510fd1ee0ed9Bob Wilson // is fine if BUILD_VECTORs are always lowered to shuffles or other 14240cbe7d5d41d22d32e8ce773548f510fd1ee0ed9Bob Wilson // operations, but for ARM some BUILD_VECTORs are legal as-is and their 14340cbe7d5d41d22d32e8ce773548f510fd1ee0ed9Bob Wilson // operands need to be legalized. Define an ARM-specific version of 14440cbe7d5d41d22d32e8ce773548f510fd1ee0ed9Bob Wilson // BUILD_VECTOR for this purpose. 14540cbe7d5d41d22d32e8ce773548f510fd1ee0ed9Bob Wilson BUILD_VECTOR, 14640cbe7d5d41d22d32e8ce773548f510fd1ee0ed9Bob Wilson 1479f6c4c141ffa9c8b13e90dce2f2285c4479ff403Bob Wilson // Floating-point max and min: 1489f6c4c141ffa9c8b13e90dce2f2285c4479ff403Bob Wilson FMAX, 1499f6c4c141ffa9c8b13e90dce2f2285c4479ff403Bob Wilson FMIN 150a8e2989ece6dc46df59b0768184028257f913843Evan Cheng }; 151a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } 152a8e2989ece6dc46df59b0768184028257f913843Evan Cheng 1535bafff36c798608a189c517d37527e4a38863071Bob Wilson /// Define some predicates that are used for node matching. 1545bafff36c798608a189c517d37527e4a38863071Bob Wilson namespace ARM { 155d3c4284849ccfbc501483ec3c0810d1d9ef853b6Bob Wilson /// getNEONModImm - If this is a valid vector constant for a NEON 156d3c4284849ccfbc501483ec3c0810d1d9ef853b6Bob Wilson /// instruction with a "modified immediate" operand (e.g., VMOV) of the 157d3c4284849ccfbc501483ec3c0810d1d9ef853b6Bob Wilson /// specified element size, return the encoded value for that immediate. 158d3c4284849ccfbc501483ec3c0810d1d9ef853b6Bob Wilson /// The ByteSize field indicates the number of bytes of each element [1248]. 159827b2106fe39c4195f5f5393b6bab70cc297657dBob Wilson SDValue getNEONModImm(SDNode *N, unsigned ByteSize, bool isVMOV, 160827b2106fe39c4195f5f5393b6bab70cc297657dBob Wilson SelectionDAG &DAG); 16139382427f1095f089d73a7dd3d9a371dea75b781Evan Cheng 16239382427f1095f089d73a7dd3d9a371dea75b781Evan Cheng /// getVFPf32Imm / getVFPf64Imm - If the given fp immediate can be 16339382427f1095f089d73a7dd3d9a371dea75b781Evan Cheng /// materialized with a VMOV.f32 / VMOV.f64 (i.e. fconsts / fconstd) 16439382427f1095f089d73a7dd3d9a371dea75b781Evan Cheng /// instruction, returns its 8-bit integer representation. Otherwise, 16539382427f1095f089d73a7dd3d9a371dea75b781Evan Cheng /// returns -1. 16639382427f1095f089d73a7dd3d9a371dea75b781Evan Cheng int getVFPf32Imm(const APFloat &FPImm); 16739382427f1095f089d73a7dd3d9a371dea75b781Evan Cheng int getVFPf64Imm(const APFloat &FPImm); 1685bafff36c798608a189c517d37527e4a38863071Bob Wilson } 1695bafff36c798608a189c517d37527e4a38863071Bob Wilson 170261f2a2337990bc7cc3d9e20d3338de54b26c74cBob Wilson //===--------------------------------------------------------------------===// 17180dae195c75a3ef38854645ae3cf41f8ae835644Dale Johannesen // ARMTargetLowering - ARM Implementation of the TargetLowering interface 1726aa7197fb5aa478a5c813d41a11689bb6d8f7abcJim Grosbach 173a8e2989ece6dc46df59b0768184028257f913843Evan Cheng class ARMTargetLowering : public TargetLowering { 174a8e2989ece6dc46df59b0768184028257f913843Evan Cheng public: 17561e729e2e9517ab2d8887bab86fb377900fa1081Dan Gohman explicit ARMTargetLowering(TargetMachine &TM); 176a8e2989ece6dc46df59b0768184028257f913843Evan Cheng 177d858e90f039f5fcdc2fa93035e911a5a9505cc50Dan Gohman virtual SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const; 1781607f05cb7d77d01ce521a30232faa389dbed4e2Duncan Sands 1791607f05cb7d77d01ce521a30232faa389dbed4e2Duncan Sands /// ReplaceNodeResults - Replace the results of node with an illegal result 1801607f05cb7d77d01ce521a30232faa389dbed4e2Duncan Sands /// type with new values built out of custom code. 1811607f05cb7d77d01ce521a30232faa389dbed4e2Duncan Sands /// 1821607f05cb7d77d01ce521a30232faa389dbed4e2Duncan Sands virtual void ReplaceNodeResults(SDNode *N, SmallVectorImpl<SDValue>&Results, 183d858e90f039f5fcdc2fa93035e911a5a9505cc50Dan Gohman SelectionDAG &DAG) const; 1841607f05cb7d77d01ce521a30232faa389dbed4e2Duncan Sands 185475871a144eb604ddaf37503397ba0941442e5fbDan Gohman virtual SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const; 1866aa7197fb5aa478a5c813d41a11689bb6d8f7abcJim Grosbach 187a8e2989ece6dc46df59b0768184028257f913843Evan Cheng virtual const char *getTargetNodeName(unsigned Opcode) const; 188a8e2989ece6dc46df59b0768184028257f913843Evan Cheng 189af1d8ca44a18f304f207e209b3bdb94b590f86ffDan Gohman virtual MachineBasicBlock * 190af1d8ca44a18f304f207e209b3bdb94b590f86ffDan Gohman EmitInstrWithCustomInserter(MachineInstr *MI, 191af1d8ca44a18f304f207e209b3bdb94b590f86ffDan Gohman MachineBasicBlock *MBB) const; 192a8e2989ece6dc46df59b0768184028257f913843Evan Cheng 193af5663405834ca7cf4a847f2efa2d624ce99b1d8Bill Wendling /// allowsUnalignedMemoryAccesses - Returns true if the target allows 194af5663405834ca7cf4a847f2efa2d624ce99b1d8Bill Wendling /// unaligned memory accesses. of the specified type. 195af5663405834ca7cf4a847f2efa2d624ce99b1d8Bill Wendling /// FIXME: Add getOptimalMemOpType to implement memcpy with NEON? 196af5663405834ca7cf4a847f2efa2d624ce99b1d8Bill Wendling virtual bool allowsUnalignedMemoryAccesses(EVT VT) const; 197af5663405834ca7cf4a847f2efa2d624ce99b1d8Bill Wendling 198c9addb74883fef318140272768422656a694341fChris Lattner /// isLegalAddressingMode - Return true if the addressing mode represented 199c9addb74883fef318140272768422656a694341fChris Lattner /// by AM is legal for this target, for a load/store of the specified type. 200c9addb74883fef318140272768422656a694341fChris Lattner virtual bool isLegalAddressingMode(const AddrMode &AM, const Type *Ty)const; 201e6c835f42418c0fae6b63908d3c576a26d64cab2Evan Cheng bool isLegalT2ScaledAddressingMode(const AddrMode &AM, EVT VT) const; 2026aa7197fb5aa478a5c813d41a11689bb6d8f7abcJim Grosbach 20377e4751011da2d6afa930ab91f7baee39e7c7e89Evan Cheng /// isLegalICmpImmediate - Return true if the specified immediate is legal 20418f30e6f5e80787808fe1455742452a5210afe07Jim Grosbach /// icmp immediate, that is the target has icmp instructions which can 20518f30e6f5e80787808fe1455742452a5210afe07Jim Grosbach /// compare a register against the immediate without having to materialize 20618f30e6f5e80787808fe1455742452a5210afe07Jim Grosbach /// the immediate into a register. 20706b53c0d51f029eb754b40350faf5ba4b33c4bcbEvan Cheng virtual bool isLegalICmpImmediate(int64_t Imm) const; 20877e4751011da2d6afa930ab91f7baee39e7c7e89Evan Cheng 209a8e2989ece6dc46df59b0768184028257f913843Evan Cheng /// getPreIndexedAddressParts - returns true by value, base pointer and 210a8e2989ece6dc46df59b0768184028257f913843Evan Cheng /// offset pointer and addressing mode by reference if the node's address 211a8e2989ece6dc46df59b0768184028257f913843Evan Cheng /// can be legally represented as pre-indexed load / store address. 212475871a144eb604ddaf37503397ba0941442e5fbDan Gohman virtual bool getPreIndexedAddressParts(SDNode *N, SDValue &Base, 213475871a144eb604ddaf37503397ba0941442e5fbDan Gohman SDValue &Offset, 214a8e2989ece6dc46df59b0768184028257f913843Evan Cheng ISD::MemIndexedMode &AM, 21573e0914848662404cf2aa18eb049ff5aae543388Dan Gohman SelectionDAG &DAG) const; 216a8e2989ece6dc46df59b0768184028257f913843Evan Cheng 217a8e2989ece6dc46df59b0768184028257f913843Evan Cheng /// getPostIndexedAddressParts - returns true by value, base pointer and 218a8e2989ece6dc46df59b0768184028257f913843Evan Cheng /// offset pointer and addressing mode by reference if this node can be 219a8e2989ece6dc46df59b0768184028257f913843Evan Cheng /// combined with a load / store to form a post-indexed load / store. 220a8e2989ece6dc46df59b0768184028257f913843Evan Cheng virtual bool getPostIndexedAddressParts(SDNode *N, SDNode *Op, 221475871a144eb604ddaf37503397ba0941442e5fbDan Gohman SDValue &Base, SDValue &Offset, 222a8e2989ece6dc46df59b0768184028257f913843Evan Cheng ISD::MemIndexedMode &AM, 22373e0914848662404cf2aa18eb049ff5aae543388Dan Gohman SelectionDAG &DAG) const; 224a8e2989ece6dc46df59b0768184028257f913843Evan Cheng 225475871a144eb604ddaf37503397ba0941442e5fbDan Gohman virtual void computeMaskedBitsForTargetNode(const SDValue Op, 226977a76fbb6ea1b87dfd7fbbe2ae2afb63e982ff3Dan Gohman const APInt &Mask, 2276aa7197fb5aa478a5c813d41a11689bb6d8f7abcJim Grosbach APInt &KnownZero, 228fd29e0eb060ea8b4d490860329234d2ae5f5952eDan Gohman APInt &KnownOne, 229ea859be53ca13a1547c4675549946b74dc3c6f41Dan Gohman const SelectionDAG &DAG, 230a8e2989ece6dc46df59b0768184028257f913843Evan Cheng unsigned Depth) const; 231af5663405834ca7cf4a847f2efa2d624ce99b1d8Bill Wendling 232af5663405834ca7cf4a847f2efa2d624ce99b1d8Bill Wendling 2334234f57fa02b1f04a9f52a7b3c2aa22d32ac521cChris Lattner ConstraintType getConstraintType(const std::string &Constraint) const; 2346aa7197fb5aa478a5c813d41a11689bb6d8f7abcJim Grosbach std::pair<unsigned, const TargetRegisterClass*> 235a8e2989ece6dc46df59b0768184028257f913843Evan Cheng getRegForInlineAsmConstraint(const std::string &Constraint, 236e50ed30282bb5b4a9ed952580523f2dda16215acOwen Anderson EVT VT) const; 237a8e2989ece6dc46df59b0768184028257f913843Evan Cheng std::vector<unsigned> 238a8e2989ece6dc46df59b0768184028257f913843Evan Cheng getRegClassForInlineAsmConstraint(const std::string &Constraint, 239e50ed30282bb5b4a9ed952580523f2dda16215acOwen Anderson EVT VT) const; 240f1ba1cad387dc52f3c2c5afc665edf9caad00992Rafael Espindola 241bf6396bed0597238110aad5b680fd18a4f8769faBob Wilson /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops 242bf6396bed0597238110aad5b680fd18a4f8769faBob Wilson /// vector. If it is invalid, don't add anything to Ops. If hasMemory is 243bf6396bed0597238110aad5b680fd18a4f8769faBob Wilson /// true it means one of the asm constraint of the inline asm instruction 244bf6396bed0597238110aad5b680fd18a4f8769faBob Wilson /// being processed is 'm'. 245bf6396bed0597238110aad5b680fd18a4f8769faBob Wilson virtual void LowerAsmOperandForConstraint(SDValue Op, 246bf6396bed0597238110aad5b680fd18a4f8769faBob Wilson char ConstraintLetter, 247bf6396bed0597238110aad5b680fd18a4f8769faBob Wilson std::vector<SDValue> &Ops, 248bf6396bed0597238110aad5b680fd18a4f8769faBob Wilson SelectionDAG &DAG) const; 2496aa7197fb5aa478a5c813d41a11689bb6d8f7abcJim Grosbach 250419e4f92635cfaa409282691437aff99062e4e0bDan Gohman const ARMSubtarget* getSubtarget() const { 251707e0184233f27e0e9f9aee0309f2daab8cfe7f8Dan Gohman return Subtarget; 252f1ba1cad387dc52f3c2c5afc665edf9caad00992Rafael Espindola } 253f1ba1cad387dc52f3c2c5afc665edf9caad00992Rafael Espindola 25406b666c7056376b8aaf40be0dc00b97b2cfceb6cEvan Cheng /// getRegClassFor - Return the register class that should be used for the 25506b666c7056376b8aaf40be0dc00b97b2cfceb6cEvan Cheng /// specified value type. 25606b666c7056376b8aaf40be0dc00b97b2cfceb6cEvan Cheng virtual TargetRegisterClass *getRegClassFor(EVT VT) const; 25706b666c7056376b8aaf40be0dc00b97b2cfceb6cEvan Cheng 258b4202b84d7e54efe5e144885c7da63e6cc465f80Bill Wendling /// getFunctionAlignment - Return the Log2 alignment of this function. 25920c568f366be211323eeaf0e45ef053278ec9ddcBill Wendling virtual unsigned getFunctionAlignment(const Function *F) const; 26020c568f366be211323eeaf0e45ef053278ec9ddcBill Wendling 2611cc3984148be113c6e5e470f23c9ddbd37679c5fEvan Cheng Sched::Preference getSchedulingPreference(SDNode *N) const; 2621cc3984148be113c6e5e470f23c9ddbd37679c5fEvan Cheng 263d0ac234b1b3a88946ad8bb52677764f3e3eeb8b3Anton Korobeynikov bool isShuffleMaskLegal(const SmallVectorImpl<int> &M, EVT VT) const; 26448e19352840a5f7012493ead894e81a2dbec1778Anton Korobeynikov bool isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const; 26539382427f1095f089d73a7dd3d9a371dea75b781Evan Cheng 26639382427f1095f089d73a7dd3d9a371dea75b781Evan Cheng /// isFPImmLegal - Returns true if the target can instruction select the 26739382427f1095f089d73a7dd3d9a371dea75b781Evan Cheng /// specified FP immediate natively. If false, the legalizer will 26839382427f1095f089d73a7dd3d9a371dea75b781Evan Cheng /// materialize the FP immediate as a load from a constant pool. 26939382427f1095f089d73a7dd3d9a371dea75b781Evan Cheng virtual bool isFPImmLegal(const APFloat &Imm, EVT VT) const; 27039382427f1095f089d73a7dd3d9a371dea75b781Evan Cheng 271a8e2989ece6dc46df59b0768184028257f913843Evan Cheng private: 272a8e2989ece6dc46df59b0768184028257f913843Evan Cheng /// Subtarget - Keep a pointer to the ARMSubtarget around so that we can 273a8e2989ece6dc46df59b0768184028257f913843Evan Cheng /// make the right decision when generating code for different targets. 274a8e2989ece6dc46df59b0768184028257f913843Evan Cheng const ARMSubtarget *Subtarget; 275a8e2989ece6dc46df59b0768184028257f913843Evan Cheng 276d2559bf3f30cc7400483825414489ec0fb36481aBob Wilson /// ARMPCLabelIndex - Keep track of the number of ARM PC labels created. 277a8e2989ece6dc46df59b0768184028257f913843Evan Cheng /// 278a8e2989ece6dc46df59b0768184028257f913843Evan Cheng unsigned ARMPCLabelIndex; 279a8e2989ece6dc46df59b0768184028257f913843Evan Cheng 280e50ed30282bb5b4a9ed952580523f2dda16215acOwen Anderson void addTypeForNEON(EVT VT, EVT PromotedLdStVT, EVT PromotedBitwiseVT); 281e50ed30282bb5b4a9ed952580523f2dda16215acOwen Anderson void addDRTypeForNEON(EVT VT); 282e50ed30282bb5b4a9ed952580523f2dda16215acOwen Anderson void addQRTypeForNEON(EVT VT); 2835bafff36c798608a189c517d37527e4a38863071Bob Wilson 2845bafff36c798608a189c517d37527e4a38863071Bob Wilson typedef SmallVector<std::pair<unsigned, SDValue>, 8> RegsToPassVector; 28598ca4f2a325f72374a477f9deba7d09e8999c29bDan Gohman void PassF64ArgInRegs(DebugLoc dl, SelectionDAG &DAG, 2865bafff36c798608a189c517d37527e4a38863071Bob Wilson SDValue Chain, SDValue &Arg, 2875bafff36c798608a189c517d37527e4a38863071Bob Wilson RegsToPassVector &RegsToPass, 2885bafff36c798608a189c517d37527e4a38863071Bob Wilson CCValAssign &VA, CCValAssign &NextVA, 2895bafff36c798608a189c517d37527e4a38863071Bob Wilson SDValue &StackPtr, 2905bafff36c798608a189c517d37527e4a38863071Bob Wilson SmallVector<SDValue, 8> &MemOpChains, 291d858e90f039f5fcdc2fa93035e911a5a9505cc50Dan Gohman ISD::ArgFlagsTy Flags) const; 2925bafff36c798608a189c517d37527e4a38863071Bob Wilson SDValue GetF64FormalArgument(CCValAssign &VA, CCValAssign &NextVA, 293d858e90f039f5fcdc2fa93035e911a5a9505cc50Dan Gohman SDValue &Root, SelectionDAG &DAG, 294d858e90f039f5fcdc2fa93035e911a5a9505cc50Dan Gohman DebugLoc dl) const; 2955bafff36c798608a189c517d37527e4a38863071Bob Wilson 29618f30e6f5e80787808fe1455742452a5210afe07Jim Grosbach CCAssignFn *CCAssignFnForNode(CallingConv::ID CC, bool Return, 29718f30e6f5e80787808fe1455742452a5210afe07Jim Grosbach bool isVarArg) const; 29898ca4f2a325f72374a477f9deba7d09e8999c29bDan Gohman SDValue LowerMemOpCallTo(SDValue Chain, SDValue StackPtr, SDValue Arg, 29998ca4f2a325f72374a477f9deba7d09e8999c29bDan Gohman DebugLoc dl, SelectionDAG &DAG, 30098ca4f2a325f72374a477f9deba7d09e8999c29bDan Gohman const CCValAssign &VA, 301d858e90f039f5fcdc2fa93035e911a5a9505cc50Dan Gohman ISD::ArgFlagsTy Flags) const; 30223ff7cff52702a8bff904d8ab4c9ca67cc19d6caJim Grosbach SDValue LowerEH_SJLJ_SETJMP(SDValue Op, SelectionDAG &DAG) const; 3035eb195153950bc7ebfc30649494a78b2096b5ef8Jim Grosbach SDValue LowerEH_SJLJ_LONGJMP(SDValue Op, SelectionDAG &DAG) const; 304a87ded2695e5bce30dbd0d2d2ac10c571bf1d161Jim Grosbach SDValue LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG, 305d858e90f039f5fcdc2fa93035e911a5a9505cc50Dan Gohman const ARMSubtarget *Subtarget) const; 306d858e90f039f5fcdc2fa93035e911a5a9505cc50Dan Gohman SDValue LowerBlockAddress(SDValue Op, SelectionDAG &DAG) const; 307d858e90f039f5fcdc2fa93035e911a5a9505cc50Dan Gohman SDValue LowerGlobalAddressDarwin(SDValue Op, SelectionDAG &DAG) const; 308d858e90f039f5fcdc2fa93035e911a5a9505cc50Dan Gohman SDValue LowerGlobalAddressELF(SDValue Op, SelectionDAG &DAG) const; 309d858e90f039f5fcdc2fa93035e911a5a9505cc50Dan Gohman SDValue LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const; 310475871a144eb604ddaf37503397ba0941442e5fbDan Gohman SDValue LowerToTLSGeneralDynamicModel(GlobalAddressSDNode *GA, 311d858e90f039f5fcdc2fa93035e911a5a9505cc50Dan Gohman SelectionDAG &DAG) const; 312475871a144eb604ddaf37503397ba0941442e5fbDan Gohman SDValue LowerToTLSExecModels(GlobalAddressSDNode *GA, 313d858e90f039f5fcdc2fa93035e911a5a9505cc50Dan Gohman SelectionDAG &DAG) const; 314d858e90f039f5fcdc2fa93035e911a5a9505cc50Dan Gohman SDValue LowerGLOBAL_OFFSET_TABLE(SDValue Op, SelectionDAG &DAG) const; 315d858e90f039f5fcdc2fa93035e911a5a9505cc50Dan Gohman SDValue LowerBR_JT(SDValue Op, SelectionDAG &DAG) const; 316d858e90f039f5fcdc2fa93035e911a5a9505cc50Dan Gohman SDValue LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const; 317d858e90f039f5fcdc2fa93035e911a5a9505cc50Dan Gohman SDValue LowerBR_CC(SDValue Op, SelectionDAG &DAG) const; 318515fe3a58877c745a922252a4492e866a2f1e42eEvan Cheng SDValue LowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG) const; 3192457f2c66184e978d4ed8fa9e2128effff26cb0bEvan Cheng SDValue LowerRETURNADDR(SDValue Op, SelectionDAG &DAG) const; 320d858e90f039f5fcdc2fa93035e911a5a9505cc50Dan Gohman SDValue LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const; 321d858e90f039f5fcdc2fa93035e911a5a9505cc50Dan Gohman SDValue LowerDYNAMIC_STACKALLOC(SDValue Op, SelectionDAG &DAG) const; 322d858e90f039f5fcdc2fa93035e911a5a9505cc50Dan Gohman SDValue LowerShiftRightParts(SDValue Op, SelectionDAG &DAG) const; 323d858e90f039f5fcdc2fa93035e911a5a9505cc50Dan Gohman SDValue LowerShiftLeftParts(SDValue Op, SelectionDAG &DAG) const; 324475871a144eb604ddaf37503397ba0941442e5fbDan Gohman 32598ca4f2a325f72374a477f9deba7d09e8999c29bDan Gohman SDValue LowerCallResult(SDValue Chain, SDValue InFlag, 32665c3c8f323198b99b88b109654194540cf9b3fa5Sandeep Patel CallingConv::ID CallConv, bool isVarArg, 32798ca4f2a325f72374a477f9deba7d09e8999c29bDan Gohman const SmallVectorImpl<ISD::InputArg> &Ins, 32898ca4f2a325f72374a477f9deba7d09e8999c29bDan Gohman DebugLoc dl, SelectionDAG &DAG, 329d858e90f039f5fcdc2fa93035e911a5a9505cc50Dan Gohman SmallVectorImpl<SDValue> &InVals) const; 33098ca4f2a325f72374a477f9deba7d09e8999c29bDan Gohman 33198ca4f2a325f72374a477f9deba7d09e8999c29bDan Gohman virtual SDValue 33298ca4f2a325f72374a477f9deba7d09e8999c29bDan Gohman LowerFormalArguments(SDValue Chain, 33365c3c8f323198b99b88b109654194540cf9b3fa5Sandeep Patel CallingConv::ID CallConv, bool isVarArg, 33498ca4f2a325f72374a477f9deba7d09e8999c29bDan Gohman const SmallVectorImpl<ISD::InputArg> &Ins, 33598ca4f2a325f72374a477f9deba7d09e8999c29bDan Gohman DebugLoc dl, SelectionDAG &DAG, 336d858e90f039f5fcdc2fa93035e911a5a9505cc50Dan Gohman SmallVectorImpl<SDValue> &InVals) const; 33798ca4f2a325f72374a477f9deba7d09e8999c29bDan Gohman 33898ca4f2a325f72374a477f9deba7d09e8999c29bDan Gohman virtual SDValue 339022d9e1cef7586a80a96446ae8691a37def9bbf4Evan Cheng LowerCall(SDValue Chain, SDValue Callee, 34065c3c8f323198b99b88b109654194540cf9b3fa5Sandeep Patel CallingConv::ID CallConv, bool isVarArg, 3410c439eb2c8397996cbccaf2798e598052d9982c8Evan Cheng bool &isTailCall, 34298ca4f2a325f72374a477f9deba7d09e8999c29bDan Gohman const SmallVectorImpl<ISD::OutputArg> &Outs, 343c9403659a98bf6487ab6fbf40b81628b5695c02eDan Gohman const SmallVectorImpl<SDValue> &OutVals, 34498ca4f2a325f72374a477f9deba7d09e8999c29bDan Gohman const SmallVectorImpl<ISD::InputArg> &Ins, 34598ca4f2a325f72374a477f9deba7d09e8999c29bDan Gohman DebugLoc dl, SelectionDAG &DAG, 346d858e90f039f5fcdc2fa93035e911a5a9505cc50Dan Gohman SmallVectorImpl<SDValue> &InVals) const; 34798ca4f2a325f72374a477f9deba7d09e8999c29bDan Gohman 34851e28e634880849ed9f7c02e93c08d25dd70291bDale Johannesen /// IsEligibleForTailCallOptimization - Check whether the call is eligible 34951e28e634880849ed9f7c02e93c08d25dd70291bDale Johannesen /// for tail call optimization. Targets which want to do tail call 35051e28e634880849ed9f7c02e93c08d25dd70291bDale Johannesen /// optimization should implement this function. 35151e28e634880849ed9f7c02e93c08d25dd70291bDale Johannesen bool IsEligibleForTailCallOptimization(SDValue Callee, 35251e28e634880849ed9f7c02e93c08d25dd70291bDale Johannesen CallingConv::ID CalleeCC, 35351e28e634880849ed9f7c02e93c08d25dd70291bDale Johannesen bool isVarArg, 35451e28e634880849ed9f7c02e93c08d25dd70291bDale Johannesen bool isCalleeStructRet, 35551e28e634880849ed9f7c02e93c08d25dd70291bDale Johannesen bool isCallerStructRet, 35651e28e634880849ed9f7c02e93c08d25dd70291bDale Johannesen const SmallVectorImpl<ISD::OutputArg> &Outs, 357c9403659a98bf6487ab6fbf40b81628b5695c02eDan Gohman const SmallVectorImpl<SDValue> &OutVals, 35851e28e634880849ed9f7c02e93c08d25dd70291bDale Johannesen const SmallVectorImpl<ISD::InputArg> &Ins, 35951e28e634880849ed9f7c02e93c08d25dd70291bDale Johannesen SelectionDAG& DAG) const; 36098ca4f2a325f72374a477f9deba7d09e8999c29bDan Gohman virtual SDValue 36198ca4f2a325f72374a477f9deba7d09e8999c29bDan Gohman LowerReturn(SDValue Chain, 36265c3c8f323198b99b88b109654194540cf9b3fa5Sandeep Patel CallingConv::ID CallConv, bool isVarArg, 36398ca4f2a325f72374a477f9deba7d09e8999c29bDan Gohman const SmallVectorImpl<ISD::OutputArg> &Outs, 364c9403659a98bf6487ab6fbf40b81628b5695c02eDan Gohman const SmallVectorImpl<SDValue> &OutVals, 365d858e90f039f5fcdc2fa93035e911a5a9505cc50Dan Gohman DebugLoc dl, SelectionDAG &DAG) const; 36606b53c0d51f029eb754b40350faf5ba4b33c4bcbEvan Cheng 36706b53c0d51f029eb754b40350faf5ba4b33c4bcbEvan Cheng SDValue getARMCmp(SDValue LHS, SDValue RHS, ISD::CondCode CC, 368218977b53eb215e5534db2f727d109ab18817cc1Evan Cheng SDValue &ARMcc, SelectionDAG &DAG, DebugLoc dl) const; 369218977b53eb215e5534db2f727d109ab18817cc1Evan Cheng SDValue getVFPCmp(SDValue LHS, SDValue RHS, 370218977b53eb215e5534db2f727d109ab18817cc1Evan Cheng SelectionDAG &DAG, DebugLoc dl) const; 371218977b53eb215e5534db2f727d109ab18817cc1Evan Cheng 372218977b53eb215e5534db2f727d109ab18817cc1Evan Cheng SDValue OptimizeVFPBrcond(SDValue Op, SelectionDAG &DAG) const; 3735278eb802fae2ee1a7b2a428596bc364d8bcd9dbJim Grosbach 374e801dc4a7b89f68f40ff2753de988c482d4d117fJim Grosbach MachineBasicBlock *EmitAtomicCmpSwap(MachineInstr *MI, 375e801dc4a7b89f68f40ff2753de988c482d4d117fJim Grosbach MachineBasicBlock *BB, 376e801dc4a7b89f68f40ff2753de988c482d4d117fJim Grosbach unsigned Size) const; 377e801dc4a7b89f68f40ff2753de988c482d4d117fJim Grosbach MachineBasicBlock *EmitAtomicBinary(MachineInstr *MI, 378e801dc4a7b89f68f40ff2753de988c482d4d117fJim Grosbach MachineBasicBlock *BB, 379e801dc4a7b89f68f40ff2753de988c482d4d117fJim Grosbach unsigned Size, 380e801dc4a7b89f68f40ff2753de988c482d4d117fJim Grosbach unsigned BinOpcode) const; 3815278eb802fae2ee1a7b2a428596bc364d8bcd9dbJim Grosbach 382a8e2989ece6dc46df59b0768184028257f913843Evan Cheng }; 383a8e2989ece6dc46df59b0768184028257f913843Evan Cheng} 384a8e2989ece6dc46df59b0768184028257f913843Evan Cheng 385a8e2989ece6dc46df59b0768184028257f913843Evan Cheng#endif // ARMISELLOWERING_H 386