ARMISelLowering.h revision bba9390fc6c0d536172c6bb4a9c93db557c1aff4
1a8e2989ece6dc46df59b0768184028257f913843Evan Cheng//===-- ARMISelLowering.h - ARM DAG Lowering Interface ----------*- C++ -*-===// 2a8e2989ece6dc46df59b0768184028257f913843Evan Cheng// 3a8e2989ece6dc46df59b0768184028257f913843Evan Cheng// The LLVM Compiler Infrastructure 4a8e2989ece6dc46df59b0768184028257f913843Evan Cheng// 54ee451de366474b9c228b4e5fa573795a715216dChris Lattner// This file is distributed under the University of Illinois Open Source 64ee451de366474b9c228b4e5fa573795a715216dChris Lattner// License. See LICENSE.TXT for details. 7a8e2989ece6dc46df59b0768184028257f913843Evan Cheng// 8a8e2989ece6dc46df59b0768184028257f913843Evan Cheng//===----------------------------------------------------------------------===// 9a8e2989ece6dc46df59b0768184028257f913843Evan Cheng// 10a8e2989ece6dc46df59b0768184028257f913843Evan Cheng// This file defines the interfaces that ARM uses to lower LLVM code into a 11a8e2989ece6dc46df59b0768184028257f913843Evan Cheng// selection DAG. 12a8e2989ece6dc46df59b0768184028257f913843Evan Cheng// 13a8e2989ece6dc46df59b0768184028257f913843Evan Cheng//===----------------------------------------------------------------------===// 14a8e2989ece6dc46df59b0768184028257f913843Evan Cheng 15a8e2989ece6dc46df59b0768184028257f913843Evan Cheng#ifndef ARMISELLOWERING_H 16a8e2989ece6dc46df59b0768184028257f913843Evan Cheng#define ARMISELLOWERING_H 17a8e2989ece6dc46df59b0768184028257f913843Evan Cheng 18c1f6f42049696e7357fb4837e1b25dabbaed3fe6Craig Topper#include "ARM.h" 19f1ba1cad387dc52f3c2c5afc665edf9caad00992Rafael Espindola#include "ARMSubtarget.h" 20a1514e24cc24b050f53a12650e047799358833a1Chandler Carruth#include "llvm/CodeGen/CallingConvLower.h" 21ab695889c67fb499bd902e8a969d0ff02ce66788Eric Christopher#include "llvm/CodeGen/FastISel.h" 22a8e2989ece6dc46df59b0768184028257f913843Evan Cheng#include "llvm/CodeGen/SelectionDAG.h" 23a1514e24cc24b050f53a12650e047799358833a1Chandler Carruth#include "llvm/Target/TargetLowering.h" 24a1514e24cc24b050f53a12650e047799358833a1Chandler Carruth#include "llvm/Target/TargetRegisterInfo.h" 25a8e2989ece6dc46df59b0768184028257f913843Evan Cheng#include <vector> 26a8e2989ece6dc46df59b0768184028257f913843Evan Cheng 27a8e2989ece6dc46df59b0768184028257f913843Evan Chengnamespace llvm { 28a8e2989ece6dc46df59b0768184028257f913843Evan Cheng class ARMConstantPoolValue; 29a8e2989ece6dc46df59b0768184028257f913843Evan Cheng 30a8e2989ece6dc46df59b0768184028257f913843Evan Cheng namespace ARMISD { 31a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // ARM Specific DAG Nodes 32a8e2989ece6dc46df59b0768184028257f913843Evan Cheng enum NodeType { 336aa7197fb5aa478a5c813d41a11689bb6d8f7abcJim Grosbach // Start the numbering where the builtin ops and target ops leave off. 340ba2bcfcc3149a25d08aa8aa00fb6c34a4e25bddDan Gohman FIRST_NUMBER = ISD::BUILTIN_OP_END, 35a8e2989ece6dc46df59b0768184028257f913843Evan Cheng 36a8e2989ece6dc46df59b0768184028257f913843Evan Cheng Wrapper, // Wrapper - A wrapper node for TargetConstantPool, 37a8e2989ece6dc46df59b0768184028257f913843Evan Cheng // TargetExternalSymbol, and TargetGlobalAddress. 3853519f015e3e84e9f57b677cc8724805a6009b73Evan Cheng WrapperDYN, // WrapperDYN - A wrapper node for TargetGlobalAddress in 3953519f015e3e84e9f57b677cc8724805a6009b73Evan Cheng // DYN mode. 405de5d4b6d0eb3fd379fa571d82f6fa764460b3b8Evan Cheng WrapperPIC, // WrapperPIC - A wrapper node for TargetGlobalAddress in 415de5d4b6d0eb3fd379fa571d82f6fa764460b3b8Evan Cheng // PIC mode. 42a8e2989ece6dc46df59b0768184028257f913843Evan Cheng WrapperJT, // WrapperJT - A wrapper node for TargetJumpTable 436aa7197fb5aa478a5c813d41a11689bb6d8f7abcJim Grosbach 44763a75dbf719242e7f99c6447d20b9bffb75dfa2Manman Ren // Add pseudo op to model memcpy for struct byval. 45763a75dbf719242e7f99c6447d20b9bffb75dfa2Manman Ren COPY_STRUCT_BYVAL, 46763a75dbf719242e7f99c6447d20b9bffb75dfa2Manman Ren 47a8e2989ece6dc46df59b0768184028257f913843Evan Cheng CALL, // Function call. 48277f0741c5ea123b30360c382a153df238c31caeEvan Cheng CALL_PRED, // Function call that's predicable. 49a8e2989ece6dc46df59b0768184028257f913843Evan Cheng CALL_NOLINK, // Function call with branch not branch-and-link. 50a8e2989ece6dc46df59b0768184028257f913843Evan Cheng tCALL, // Thumb function call. 51a8e2989ece6dc46df59b0768184028257f913843Evan Cheng BRCOND, // Conditional branch. 52a8e2989ece6dc46df59b0768184028257f913843Evan Cheng BR_JT, // Jumptable branch. 535657c01949dca6c012ac60d242d1a8d2ffdf5603Evan Cheng BR2_JT, // Jumptable branch (2 level - jumptable entry is a jump). 54a8e2989ece6dc46df59b0768184028257f913843Evan Cheng RET_FLAG, // Return with a flag operand. 55bba9390fc6c0d536172c6bb4a9c93db557c1aff4Tim Northover INTRET_FLAG, // Interrupt return with an LR-offset and a flag operand. 56a8e2989ece6dc46df59b0768184028257f913843Evan Cheng 57a8e2989ece6dc46df59b0768184028257f913843Evan Cheng PIC_ADD, // Add with a PC operand and a PIC label. 58a8e2989ece6dc46df59b0768184028257f913843Evan Cheng 59a8e2989ece6dc46df59b0768184028257f913843Evan Cheng CMP, // ARM compare instructions. 60ad5c8808923ed5b24b586cec544e45cee539e529Bill Wendling CMN, // ARM CMN instructions. 61c0309b48b560f119982c02a81416c8c1fd208648David Goodwin CMPZ, // ARM compare that sets only Z flag. 62a8e2989ece6dc46df59b0768184028257f913843Evan Cheng CMPFP, // ARM VFP compare instruction, sets FPSCR. 63a8e2989ece6dc46df59b0768184028257f913843Evan Cheng CMPFPw0, // ARM VFP compare against zero instruction, sets FPSCR. 64a8e2989ece6dc46df59b0768184028257f913843Evan Cheng FMSTAT, // ARM fmstat instruction. 65c892aeb26601cc5109490d30c7e170cb07f84428Evan Cheng 66a8e2989ece6dc46df59b0768184028257f913843Evan Cheng CMOV, // ARM conditional move instructions. 676aa7197fb5aa478a5c813d41a11689bb6d8f7abcJim Grosbach 68218977b53eb215e5534db2f727d109ab18817cc1Evan Cheng BCC_i64, 69218977b53eb215e5534db2f727d109ab18817cc1Evan Cheng 703482c8003ad0c88469b7333aaf658036e3fd0468Jim Grosbach RBIT, // ARM bitreverse instruction 713482c8003ad0c88469b7333aaf658036e3fd0468Jim Grosbach 7276a312b7d1c2b41394696510506967cd0794b831Bob Wilson FTOSI, // FP to sint within a FP register. 7376a312b7d1c2b41394696510506967cd0794b831Bob Wilson FTOUI, // FP to uint within a FP register. 7476a312b7d1c2b41394696510506967cd0794b831Bob Wilson SITOF, // sint to FP within a FP register. 7576a312b7d1c2b41394696510506967cd0794b831Bob Wilson UITOF, // uint to FP within a FP register. 7676a312b7d1c2b41394696510506967cd0794b831Bob Wilson 77a8e2989ece6dc46df59b0768184028257f913843Evan Cheng SRL_FLAG, // V,Flag = srl_flag X -> srl X, 1 + save carry out. 78a8e2989ece6dc46df59b0768184028257f913843Evan Cheng SRA_FLAG, // V,Flag = sra_flag X -> sra X, 1 + save carry out. 79a8e2989ece6dc46df59b0768184028257f913843Evan Cheng RRX, // V = RRX X, Flag -> srl X, 1 + shift in carry flag. 806aa7197fb5aa478a5c813d41a11689bb6d8f7abcJim Grosbach 81342e3161d9dd4fa485b47788aa0266f9c91c3832Evan Cheng ADDC, // Add with carry 82342e3161d9dd4fa485b47788aa0266f9c91c3832Evan Cheng ADDE, // Add using carry 83342e3161d9dd4fa485b47788aa0266f9c91c3832Evan Cheng SUBC, // Sub with carry 84342e3161d9dd4fa485b47788aa0266f9c91c3832Evan Cheng SUBE, // Sub using carry 85342e3161d9dd4fa485b47788aa0266f9c91c3832Evan Cheng 86e5165490b7ba24bb2f3043399e0d60e7f3bcf8a5Jim Grosbach VMOVRRD, // double to two gprs. 87e5165490b7ba24bb2f3043399e0d60e7f3bcf8a5Jim Grosbach VMOVDRR, // Two gprs to double. 8864f4fa5e0eb505eec3a72041bec6b3a7f7739dedLauro Ramos Venancio 89e4ad387a5a88dae20f0f7578e55170bbc8eee2a9Jim Grosbach EH_SJLJ_SETJMP, // SjLj exception handling setjmp. 90e4ad387a5a88dae20f0f7578e55170bbc8eee2a9Jim Grosbach EH_SJLJ_LONGJMP, // SjLj exception handling longjmp. 910e0da734bbdfa1d3f55cd04db31d83b97e4556f7Jim Grosbach 9251e28e634880849ed9f7c02e93c08d25dd70291bDale Johannesen TC_RETURN, // Tail call return pseudo. 9351e28e634880849ed9f7c02e93c08d25dd70291bDale Johannesen 945bafff36c798608a189c517d37527e4a38863071Bob Wilson THREAD_POINTER, 955bafff36c798608a189c517d37527e4a38863071Bob Wilson 96861986401e05e437cb33bfd8320d510b956fe41eEvan Cheng DYN_ALLOC, // Dynamic allocation on the stack. 97861986401e05e437cb33bfd8320d510b956fe41eEvan Cheng 98f74a4298163a7d0b500c7f7a818829c153dc942eBob Wilson MEMBARRIER_MCR, // Memory barrier (MCR) 99dfed19fe2c34c1209108afa58e8ab014ffd894e2Evan Cheng 100dfed19fe2c34c1209108afa58e8ab014ffd894e2Evan Cheng PRELOAD, // Preload 1015adfba283dc0795ba005545ce38fa5b0ada14511Andrew Trick 1025bafff36c798608a189c517d37527e4a38863071Bob Wilson VCEQ, // Vector compare equal. 103c24cb3551ed66830b53362f593269873cb53a0c4Owen Anderson VCEQZ, // Vector compare equal to zero. 1045bafff36c798608a189c517d37527e4a38863071Bob Wilson VCGE, // Vector compare greater than or equal. 105c24cb3551ed66830b53362f593269873cb53a0c4Owen Anderson VCGEZ, // Vector compare greater than or equal to zero. 106c24cb3551ed66830b53362f593269873cb53a0c4Owen Anderson VCLEZ, // Vector compare less than or equal to zero. 1075bafff36c798608a189c517d37527e4a38863071Bob Wilson VCGEU, // Vector compare unsigned greater than or equal. 1085bafff36c798608a189c517d37527e4a38863071Bob Wilson VCGT, // Vector compare greater than. 109c24cb3551ed66830b53362f593269873cb53a0c4Owen Anderson VCGTZ, // Vector compare greater than zero. 110c24cb3551ed66830b53362f593269873cb53a0c4Owen Anderson VCLTZ, // Vector compare less than zero. 1115bafff36c798608a189c517d37527e4a38863071Bob Wilson VCGTU, // Vector compare unsigned greater than. 1125bafff36c798608a189c517d37527e4a38863071Bob Wilson VTST, // Vector test bits. 1135bafff36c798608a189c517d37527e4a38863071Bob Wilson 1145bafff36c798608a189c517d37527e4a38863071Bob Wilson // Vector shift by immediate: 1155bafff36c798608a189c517d37527e4a38863071Bob Wilson VSHL, // ...left 1165bafff36c798608a189c517d37527e4a38863071Bob Wilson VSHRs, // ...right (signed) 1175bafff36c798608a189c517d37527e4a38863071Bob Wilson VSHRu, // ...right (unsigned) 1185bafff36c798608a189c517d37527e4a38863071Bob Wilson VSHLLs, // ...left long (signed) 1195bafff36c798608a189c517d37527e4a38863071Bob Wilson VSHLLu, // ...left long (unsigned) 1205bafff36c798608a189c517d37527e4a38863071Bob Wilson VSHLLi, // ...left long (with maximum shift count) 1215bafff36c798608a189c517d37527e4a38863071Bob Wilson VSHRN, // ...right narrow 1225bafff36c798608a189c517d37527e4a38863071Bob Wilson 1235bafff36c798608a189c517d37527e4a38863071Bob Wilson // Vector rounding shift by immediate: 1245bafff36c798608a189c517d37527e4a38863071Bob Wilson VRSHRs, // ...right (signed) 1255bafff36c798608a189c517d37527e4a38863071Bob Wilson VRSHRu, // ...right (unsigned) 1265bafff36c798608a189c517d37527e4a38863071Bob Wilson VRSHRN, // ...right narrow 1275bafff36c798608a189c517d37527e4a38863071Bob Wilson 1285bafff36c798608a189c517d37527e4a38863071Bob Wilson // Vector saturating shift by immediate: 1295bafff36c798608a189c517d37527e4a38863071Bob Wilson VQSHLs, // ...left (signed) 1305bafff36c798608a189c517d37527e4a38863071Bob Wilson VQSHLu, // ...left (unsigned) 1315bafff36c798608a189c517d37527e4a38863071Bob Wilson VQSHLsu, // ...left (signed to unsigned) 1325bafff36c798608a189c517d37527e4a38863071Bob Wilson VQSHRNs, // ...right narrow (signed) 1335bafff36c798608a189c517d37527e4a38863071Bob Wilson VQSHRNu, // ...right narrow (unsigned) 1345bafff36c798608a189c517d37527e4a38863071Bob Wilson VQSHRNsu, // ...right narrow (signed to unsigned) 1355bafff36c798608a189c517d37527e4a38863071Bob Wilson 1365bafff36c798608a189c517d37527e4a38863071Bob Wilson // Vector saturating rounding shift by immediate: 1375bafff36c798608a189c517d37527e4a38863071Bob Wilson VQRSHRNs, // ...right narrow (signed) 1385bafff36c798608a189c517d37527e4a38863071Bob Wilson VQRSHRNu, // ...right narrow (unsigned) 1395bafff36c798608a189c517d37527e4a38863071Bob Wilson VQRSHRNsu, // ...right narrow (signed to unsigned) 1405bafff36c798608a189c517d37527e4a38863071Bob Wilson 1415bafff36c798608a189c517d37527e4a38863071Bob Wilson // Vector shift and insert: 1425bafff36c798608a189c517d37527e4a38863071Bob Wilson VSLI, // ...left 1435bafff36c798608a189c517d37527e4a38863071Bob Wilson VSRI, // ...right 1445bafff36c798608a189c517d37527e4a38863071Bob Wilson 1455bafff36c798608a189c517d37527e4a38863071Bob Wilson // Vector get lane (VMOV scalar to ARM core register) 1465bafff36c798608a189c517d37527e4a38863071Bob Wilson // (These are used for 8- and 16-bit element types only.) 1475bafff36c798608a189c517d37527e4a38863071Bob Wilson VGETLANEu, // zero-extend vector extract element 1485bafff36c798608a189c517d37527e4a38863071Bob Wilson VGETLANEs, // sign-extend vector extract element 1495bafff36c798608a189c517d37527e4a38863071Bob Wilson 1507e3f0d26908b82bc6a3699251e0d38821610bca7Bob Wilson // Vector move immediate and move negated immediate: 151cba270d042862bca213b812656a2181b0de0578eBob Wilson VMOVIMM, 1527e3f0d26908b82bc6a3699251e0d38821610bca7Bob Wilson VMVNIMM, 1537e3f0d26908b82bc6a3699251e0d38821610bca7Bob Wilson 154eaa192af18677c4dc5894e049514d8a6b1d6d7c2Evan Cheng // Vector move f32 immediate: 155eaa192af18677c4dc5894e049514d8a6b1d6d7c2Evan Cheng VMOVFPIMM, 156eaa192af18677c4dc5894e049514d8a6b1d6d7c2Evan Cheng 1577e3f0d26908b82bc6a3699251e0d38821610bca7Bob Wilson // Vector duplicate: 158c1d287b4b73487b6ab094a253a7357addc1d8b84Bob Wilson VDUP, 1590ce371082565330672c276f76297f46b362d74b7Bob Wilson VDUPLANE, 160a599bff101095e528198ae85739fe8b97ffba82bBob Wilson 161d8e1757eacbcbae6657558f40fdada4279a9d1edBob Wilson // Vector shuffles: 162de95c1b88be44d4af916af8fba9d7940b7e98e32Bob Wilson VEXT, // extract 163d8e1757eacbcbae6657558f40fdada4279a9d1edBob Wilson VREV64, // reverse elements within 64-bit doublewords 164d8e1757eacbcbae6657558f40fdada4279a9d1edBob Wilson VREV32, // reverse elements within 32-bit words 1651c8e581832440a114c9587d41473d107de4cac74Anton Korobeynikov VREV16, // reverse elements within 16-bit halfwords 166c692cb77aaa8b16bcc7fe0c70d47adce94c43911Bob Wilson VZIP, // zip (interleave) 167c692cb77aaa8b16bcc7fe0c70d47adce94c43911Bob Wilson VUZP, // unzip (deinterleave) 1689f6c4c141ffa9c8b13e90dce2f2285c4479ff403Bob Wilson VTRN, // transpose 16969a05a7b9205fd4628ed614d1845f3879f6be949Bill Wendling VTBL1, // 1-register shuffle with mask 17069a05a7b9205fd4628ed614d1845f3879f6be949Bill Wendling VTBL2, // 2-register shuffle with mask 1719f6c4c141ffa9c8b13e90dce2f2285c4479ff403Bob Wilson 172d0b69cf1198dadbb7bdfc385334b67f60f756539Bob Wilson // Vector multiply long: 173d0b69cf1198dadbb7bdfc385334b67f60f756539Bob Wilson VMULLs, // ...signed 174d0b69cf1198dadbb7bdfc385334b67f60f756539Bob Wilson VMULLu, // ...unsigned 175d0b69cf1198dadbb7bdfc385334b67f60f756539Bob Wilson 17667514e90669ec9ffd954c1fcb6f8979bafcabe8aArnold Schwaighofer UMLAL, // 64bit Unsigned Accumulate Multiply 17767514e90669ec9ffd954c1fcb6f8979bafcabe8aArnold Schwaighofer SMLAL, // 64bit Signed Accumulate Multiply 17867514e90669ec9ffd954c1fcb6f8979bafcabe8aArnold Schwaighofer 17940cbe7d5d41d22d32e8ce773548f510fd1ee0ed9Bob Wilson // Operands of the standard BUILD_VECTOR node are not legalized, which 18040cbe7d5d41d22d32e8ce773548f510fd1ee0ed9Bob Wilson // is fine if BUILD_VECTORs are always lowered to shuffles or other 18140cbe7d5d41d22d32e8ce773548f510fd1ee0ed9Bob Wilson // operations, but for ARM some BUILD_VECTORs are legal as-is and their 18240cbe7d5d41d22d32e8ce773548f510fd1ee0ed9Bob Wilson // operands need to be legalized. Define an ARM-specific version of 18340cbe7d5d41d22d32e8ce773548f510fd1ee0ed9Bob Wilson // BUILD_VECTOR for this purpose. 18440cbe7d5d41d22d32e8ce773548f510fd1ee0ed9Bob Wilson BUILD_VECTOR, 18540cbe7d5d41d22d32e8ce773548f510fd1ee0ed9Bob Wilson 1869f6c4c141ffa9c8b13e90dce2f2285c4479ff403Bob Wilson // Floating-point max and min: 1879f6c4c141ffa9c8b13e90dce2f2285c4479ff403Bob Wilson FMAX, 188469bbdb597f27d6900c95b6d8ae20a45b79ce91bJim Grosbach FMIN, 189a0b2d332c114571716746ba90c815cfb6f68d4abJoey Gouly VMAXNM, 190a0b2d332c114571716746ba90c815cfb6f68d4abJoey Gouly VMINNM, 191469bbdb597f27d6900c95b6d8ae20a45b79ce91bJim Grosbach 192469bbdb597f27d6900c95b6d8ae20a45b79ce91bJim Grosbach // Bit-field insert 193d966817f3cb87897cbec29c967b974924fe939baOwen Anderson BFI, 1945adfba283dc0795ba005545ce38fa5b0ada14511Andrew Trick 195d966817f3cb87897cbec29c967b974924fe939baOwen Anderson // Vector OR with immediate 196080c09229739ec2b13f7bccc361994a8d26b4ed2Owen Anderson VORRIMM, 197080c09229739ec2b13f7bccc361994a8d26b4ed2Owen Anderson // Vector AND with NOT of immediate 198b1dfa7a8e0c1972231bee636afd5239b009ba4daBob Wilson VBICIMM, 199b1dfa7a8e0c1972231bee636afd5239b009ba4daBob Wilson 200c0e6d780cd7a0935f545a0ec0a9ad4a6ae8db2a9Cameron Zwarich // Vector bitwise select 201c0e6d780cd7a0935f545a0ec0a9ad4a6ae8db2a9Cameron Zwarich VBSL, 202c0e6d780cd7a0935f545a0ec0a9ad4a6ae8db2a9Cameron Zwarich 203b1dfa7a8e0c1972231bee636afd5239b009ba4daBob Wilson // Vector load N-element structure to all lanes: 204b1dfa7a8e0c1972231bee636afd5239b009ba4daBob Wilson VLD2DUP = ISD::FIRST_TARGET_MEMORY_OPCODE, 205b1dfa7a8e0c1972231bee636afd5239b009ba4daBob Wilson VLD3DUP, 2061c3ef90cab9a563427bdd3c2fcd875c717750562Bob Wilson VLD4DUP, 2071c3ef90cab9a563427bdd3c2fcd875c717750562Bob Wilson 2081c3ef90cab9a563427bdd3c2fcd875c717750562Bob Wilson // NEON loads with post-increment base updates: 2091c3ef90cab9a563427bdd3c2fcd875c717750562Bob Wilson VLD1_UPD, 2101c3ef90cab9a563427bdd3c2fcd875c717750562Bob Wilson VLD2_UPD, 2111c3ef90cab9a563427bdd3c2fcd875c717750562Bob Wilson VLD3_UPD, 2121c3ef90cab9a563427bdd3c2fcd875c717750562Bob Wilson VLD4_UPD, 2131c3ef90cab9a563427bdd3c2fcd875c717750562Bob Wilson VLD2LN_UPD, 2141c3ef90cab9a563427bdd3c2fcd875c717750562Bob Wilson VLD3LN_UPD, 2151c3ef90cab9a563427bdd3c2fcd875c717750562Bob Wilson VLD4LN_UPD, 2161c3ef90cab9a563427bdd3c2fcd875c717750562Bob Wilson VLD2DUP_UPD, 2171c3ef90cab9a563427bdd3c2fcd875c717750562Bob Wilson VLD3DUP_UPD, 2181c3ef90cab9a563427bdd3c2fcd875c717750562Bob Wilson VLD4DUP_UPD, 2191c3ef90cab9a563427bdd3c2fcd875c717750562Bob Wilson 2201c3ef90cab9a563427bdd3c2fcd875c717750562Bob Wilson // NEON stores with post-increment base updates: 2211c3ef90cab9a563427bdd3c2fcd875c717750562Bob Wilson VST1_UPD, 2221c3ef90cab9a563427bdd3c2fcd875c717750562Bob Wilson VST2_UPD, 2231c3ef90cab9a563427bdd3c2fcd875c717750562Bob Wilson VST3_UPD, 2241c3ef90cab9a563427bdd3c2fcd875c717750562Bob Wilson VST4_UPD, 2251c3ef90cab9a563427bdd3c2fcd875c717750562Bob Wilson VST2LN_UPD, 2261c3ef90cab9a563427bdd3c2fcd875c717750562Bob Wilson VST3LN_UPD, 227268c743a3ba44ada364938bc5ff9b1be219df54fAmara Emerson VST4LN_UPD 228a8e2989ece6dc46df59b0768184028257f913843Evan Cheng }; 229a8e2989ece6dc46df59b0768184028257f913843Evan Cheng } 230a8e2989ece6dc46df59b0768184028257f913843Evan Cheng 2315bafff36c798608a189c517d37527e4a38863071Bob Wilson /// Define some predicates that are used for node matching. 2325bafff36c798608a189c517d37527e4a38863071Bob Wilson namespace ARM { 233469bbdb597f27d6900c95b6d8ae20a45b79ce91bJim Grosbach bool isBitFieldInvertedMask(unsigned v); 2345bafff36c798608a189c517d37527e4a38863071Bob Wilson } 2355bafff36c798608a189c517d37527e4a38863071Bob Wilson 236261f2a2337990bc7cc3d9e20d3338de54b26c74cBob Wilson //===--------------------------------------------------------------------===// 23780dae195c75a3ef38854645ae3cf41f8ae835644Dale Johannesen // ARMTargetLowering - ARM Implementation of the TargetLowering interface 2386aa7197fb5aa478a5c813d41a11689bb6d8f7abcJim Grosbach 239a8e2989ece6dc46df59b0768184028257f913843Evan Cheng class ARMTargetLowering : public TargetLowering { 240a8e2989ece6dc46df59b0768184028257f913843Evan Cheng public: 24161e729e2e9517ab2d8887bab86fb377900fa1081Dan Gohman explicit ARMTargetLowering(TargetMachine &TM); 242a8e2989ece6dc46df59b0768184028257f913843Evan Cheng 24379c07d2a36282b09b9c5d0aa65ebf4bff017621bDmitri Gribenko virtual unsigned getJumpTableEncoding() const; 244e1102caf86c8e09387ac7ee83aae4e69d2d35fc4Jim Grosbach 245d858e90f039f5fcdc2fa93035e911a5a9505cc50Dan Gohman virtual SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const; 2461607f05cb7d77d01ce521a30232faa389dbed4e2Duncan Sands 2471607f05cb7d77d01ce521a30232faa389dbed4e2Duncan Sands /// ReplaceNodeResults - Replace the results of node with an illegal result 2481607f05cb7d77d01ce521a30232faa389dbed4e2Duncan Sands /// type with new values built out of custom code. 2491607f05cb7d77d01ce521a30232faa389dbed4e2Duncan Sands /// 2501607f05cb7d77d01ce521a30232faa389dbed4e2Duncan Sands virtual void ReplaceNodeResults(SDNode *N, SmallVectorImpl<SDValue>&Results, 251d858e90f039f5fcdc2fa93035e911a5a9505cc50Dan Gohman SelectionDAG &DAG) const; 2521607f05cb7d77d01ce521a30232faa389dbed4e2Duncan Sands 253a8e2989ece6dc46df59b0768184028257f913843Evan Cheng virtual const char *getTargetNodeName(unsigned Opcode) const; 254a8e2989ece6dc46df59b0768184028257f913843Evan Cheng 2559f40cb32ac31283f8636d516e7b10f3ad921955cNadav Rotem virtual bool isSelectSupported(SelectSupportKind Kind) const { 2569f40cb32ac31283f8636d516e7b10f3ad921955cNadav Rotem // ARM does not support scalar condition selects on vectors. 2579f40cb32ac31283f8636d516e7b10f3ad921955cNadav Rotem return (Kind != ScalarCondVectorVal); 2589f40cb32ac31283f8636d516e7b10f3ad921955cNadav Rotem } 2599f40cb32ac31283f8636d516e7b10f3ad921955cNadav Rotem 26028b77e968d2b01fc9da724762bd8ddcd80650e32Duncan Sands /// getSetCCResultType - Return the value type to use for ISD::SETCC. 261225ed7069caae9ece32d8bd3d15c6e41e21cc04bMatt Arsenault virtual EVT getSetCCResultType(LLVMContext &Context, EVT VT) const; 26228b77e968d2b01fc9da724762bd8ddcd80650e32Duncan Sands 263af1d8ca44a18f304f207e209b3bdb94b590f86ffDan Gohman virtual MachineBasicBlock * 264af1d8ca44a18f304f207e209b3bdb94b590f86ffDan Gohman EmitInstrWithCustomInserter(MachineInstr *MI, 265af1d8ca44a18f304f207e209b3bdb94b590f86ffDan Gohman MachineBasicBlock *MBB) const; 266a8e2989ece6dc46df59b0768184028257f913843Evan Cheng 26737fefc20d3a1e3934a377567d54a141f67752227Evan Cheng virtual void 26837fefc20d3a1e3934a377567d54a141f67752227Evan Cheng AdjustInstrPostInstrSelection(MachineInstr *MI, SDNode *Node) const; 26937fefc20d3a1e3934a377567d54a141f67752227Evan Cheng 270e721f5c8d3ea2cc2cc8c3c308ce8bdd8a3fc3b32Evan Cheng SDValue PerformCMOVCombine(SDNode *N, SelectionDAG &DAG) const; 27131959b19a72608051888160514977875a8027dfcEvan Cheng virtual SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const; 27231959b19a72608051888160514977875a8027dfcEvan Cheng 27331959b19a72608051888160514977875a8027dfcEvan Cheng bool isDesirableToTransformToIntegerOp(unsigned Opc, EVT VT) const; 27431959b19a72608051888160514977875a8027dfcEvan Cheng 275af5663405834ca7cf4a847f2efa2d624ce99b1d8Bill Wendling /// allowsUnalignedMemoryAccesses - Returns true if the target allows 276376642ed620ecae05b68c7bc81f79aeb2065abe0Evan Cheng /// unaligned memory accesses of the specified type. Returns whether it 277376642ed620ecae05b68c7bc81f79aeb2065abe0Evan Cheng /// is "fast" by reference in the second argument. 278376642ed620ecae05b68c7bc81f79aeb2065abe0Evan Cheng virtual bool allowsUnalignedMemoryAccesses(EVT VT, bool *Fast) const; 279af5663405834ca7cf4a847f2efa2d624ce99b1d8Bill Wendling 2801a1d1fcc0b955420cdbe0b94bd01c46d4e96b429Lang Hames virtual EVT getOptimalMemOpType(uint64_t Size, 2811a1d1fcc0b955420cdbe0b94bd01c46d4e96b429Lang Hames unsigned DstAlign, unsigned SrcAlign, 282946a3a9f22c967d5432eaab5fa464b91343477cdEvan Cheng bool IsMemset, bool ZeroMemset, 2831a1d1fcc0b955420cdbe0b94bd01c46d4e96b429Lang Hames bool MemcpyStrSrc, 2841a1d1fcc0b955420cdbe0b94bd01c46d4e96b429Lang Hames MachineFunction &MF) const; 2851a1d1fcc0b955420cdbe0b94bd01c46d4e96b429Lang Hames 286c4e8ddff0c29bfc2eb1d5bf13e947bd04d4454ffMatt Beaumont-Gay using TargetLowering::isZExtFree; 2872766a47310b05228e9bbc536d9f3a593fc31cd12Evan Cheng virtual bool isZExtFree(SDValue Val, EVT VT2) const; 2882766a47310b05228e9bbc536d9f3a593fc31cd12Evan Cheng 2898775a51d94b277ca6ebe12a1d20bfc2bc5a53960Tim Northover virtual bool allowTruncateForTailCall(Type *Ty1, Type *Ty2) const; 2908775a51d94b277ca6ebe12a1d20bfc2bc5a53960Tim Northover 2918775a51d94b277ca6ebe12a1d20bfc2bc5a53960Tim Northover 292c9addb74883fef318140272768422656a694341fChris Lattner /// isLegalAddressingMode - Return true if the addressing mode represented 293c9addb74883fef318140272768422656a694341fChris Lattner /// by AM is legal for this target, for a load/store of the specified type. 294db125cfaf57cc83e7dd7453de2d509bc8efd0e5eChris Lattner virtual bool isLegalAddressingMode(const AddrMode &AM, Type *Ty)const; 295e6c835f42418c0fae6b63908d3c576a26d64cab2Evan Cheng bool isLegalT2ScaledAddressingMode(const AddrMode &AM, EVT VT) const; 2966aa7197fb5aa478a5c813d41a11689bb6d8f7abcJim Grosbach 29777e4751011da2d6afa930ab91f7baee39e7c7e89Evan Cheng /// isLegalICmpImmediate - Return true if the specified immediate is legal 29818f30e6f5e80787808fe1455742452a5210afe07Jim Grosbach /// icmp immediate, that is the target has icmp instructions which can 29918f30e6f5e80787808fe1455742452a5210afe07Jim Grosbach /// compare a register against the immediate without having to materialize 30018f30e6f5e80787808fe1455742452a5210afe07Jim Grosbach /// the immediate into a register. 30106b53c0d51f029eb754b40350faf5ba4b33c4bcbEvan Cheng virtual bool isLegalICmpImmediate(int64_t Imm) const; 30277e4751011da2d6afa930ab91f7baee39e7c7e89Evan Cheng 303cca82149adef8306a295abdc963213ae3b11bbb6Dan Gohman /// isLegalAddImmediate - Return true if the specified immediate is legal 304cca82149adef8306a295abdc963213ae3b11bbb6Dan Gohman /// add immediate, that is the target has add instructions which can 305cca82149adef8306a295abdc963213ae3b11bbb6Dan Gohman /// add a register and the immediate without having to materialize 306cca82149adef8306a295abdc963213ae3b11bbb6Dan Gohman /// the immediate into a register. 307cca82149adef8306a295abdc963213ae3b11bbb6Dan Gohman virtual bool isLegalAddImmediate(int64_t Imm) const; 308cca82149adef8306a295abdc963213ae3b11bbb6Dan Gohman 309a8e2989ece6dc46df59b0768184028257f913843Evan Cheng /// getPreIndexedAddressParts - returns true by value, base pointer and 310a8e2989ece6dc46df59b0768184028257f913843Evan Cheng /// offset pointer and addressing mode by reference if the node's address 311a8e2989ece6dc46df59b0768184028257f913843Evan Cheng /// can be legally represented as pre-indexed load / store address. 312475871a144eb604ddaf37503397ba0941442e5fbDan Gohman virtual bool getPreIndexedAddressParts(SDNode *N, SDValue &Base, 313475871a144eb604ddaf37503397ba0941442e5fbDan Gohman SDValue &Offset, 314a8e2989ece6dc46df59b0768184028257f913843Evan Cheng ISD::MemIndexedMode &AM, 31573e0914848662404cf2aa18eb049ff5aae543388Dan Gohman SelectionDAG &DAG) const; 316a8e2989ece6dc46df59b0768184028257f913843Evan Cheng 317a8e2989ece6dc46df59b0768184028257f913843Evan Cheng /// getPostIndexedAddressParts - returns true by value, base pointer and 318a8e2989ece6dc46df59b0768184028257f913843Evan Cheng /// offset pointer and addressing mode by reference if this node can be 319a8e2989ece6dc46df59b0768184028257f913843Evan Cheng /// combined with a load / store to form a post-indexed load / store. 320a8e2989ece6dc46df59b0768184028257f913843Evan Cheng virtual bool getPostIndexedAddressParts(SDNode *N, SDNode *Op, 321475871a144eb604ddaf37503397ba0941442e5fbDan Gohman SDValue &Base, SDValue &Offset, 322a8e2989ece6dc46df59b0768184028257f913843Evan Cheng ISD::MemIndexedMode &AM, 32373e0914848662404cf2aa18eb049ff5aae543388Dan Gohman SelectionDAG &DAG) const; 324a8e2989ece6dc46df59b0768184028257f913843Evan Cheng 325475871a144eb604ddaf37503397ba0941442e5fbDan Gohman virtual void computeMaskedBitsForTargetNode(const SDValue Op, 3266aa7197fb5aa478a5c813d41a11689bb6d8f7abcJim Grosbach APInt &KnownZero, 327fd29e0eb060ea8b4d490860329234d2ae5f5952eDan Gohman APInt &KnownOne, 328ea859be53ca13a1547c4675549946b74dc3c6f41Dan Gohman const SelectionDAG &DAG, 329a8e2989ece6dc46df59b0768184028257f913843Evan Cheng unsigned Depth) const; 330af5663405834ca7cf4a847f2efa2d624ce99b1d8Bill Wendling 331af5663405834ca7cf4a847f2efa2d624ce99b1d8Bill Wendling 33255d42003368c57d3a41c5f464d39b8440050d558Evan Cheng virtual bool ExpandInlineAsm(CallInst *CI) const; 33355d42003368c57d3a41c5f464d39b8440050d558Evan Cheng 3344234f57fa02b1f04a9f52a7b3c2aa22d32ac521cChris Lattner ConstraintType getConstraintType(const std::string &Constraint) const; 33544ab89eb376af838d1123293a79975aede501464John Thompson 33644ab89eb376af838d1123293a79975aede501464John Thompson /// Examine constraint string and operand type and determine a weight value. 33744ab89eb376af838d1123293a79975aede501464John Thompson /// The operand object must already have been set up with the operand type. 33844ab89eb376af838d1123293a79975aede501464John Thompson ConstraintWeight getSingleConstraintMatchWeight( 33944ab89eb376af838d1123293a79975aede501464John Thompson AsmOperandInfo &info, const char *constraint) const; 34044ab89eb376af838d1123293a79975aede501464John Thompson 3416aa7197fb5aa478a5c813d41a11689bb6d8f7abcJim Grosbach std::pair<unsigned, const TargetRegisterClass*> 342a8e2989ece6dc46df59b0768184028257f913843Evan Cheng getRegForInlineAsmConstraint(const std::string &Constraint, 3435b3fca50a08865f0db55fc92ad1c037a04e12177Chad Rosier MVT VT) const; 344f1ba1cad387dc52f3c2c5afc665edf9caad00992Rafael Espindola 345bf6396bed0597238110aad5b680fd18a4f8769faBob Wilson /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops 346bf6396bed0597238110aad5b680fd18a4f8769faBob Wilson /// vector. If it is invalid, don't add anything to Ops. If hasMemory is 347bf6396bed0597238110aad5b680fd18a4f8769faBob Wilson /// true it means one of the asm constraint of the inline asm instruction 348bf6396bed0597238110aad5b680fd18a4f8769faBob Wilson /// being processed is 'm'. 349bf6396bed0597238110aad5b680fd18a4f8769faBob Wilson virtual void LowerAsmOperandForConstraint(SDValue Op, 350100c83341676d8aae8fc34b5452563ed08b14f3eEric Christopher std::string &Constraint, 351bf6396bed0597238110aad5b680fd18a4f8769faBob Wilson std::vector<SDValue> &Ops, 352bf6396bed0597238110aad5b680fd18a4f8769faBob Wilson SelectionDAG &DAG) const; 3536aa7197fb5aa478a5c813d41a11689bb6d8f7abcJim Grosbach 354419e4f92635cfaa409282691437aff99062e4e0bDan Gohman const ARMSubtarget* getSubtarget() const { 355707e0184233f27e0e9f9aee0309f2daab8cfe7f8Dan Gohman return Subtarget; 356f1ba1cad387dc52f3c2c5afc665edf9caad00992Rafael Espindola } 357f1ba1cad387dc52f3c2c5afc665edf9caad00992Rafael Espindola 35806b666c7056376b8aaf40be0dc00b97b2cfceb6cEvan Cheng /// getRegClassFor - Return the register class that should be used for the 35906b666c7056376b8aaf40be0dc00b97b2cfceb6cEvan Cheng /// specified value type. 360a61b17c18a67f1b3faef2f2108379c4337ce9bb7Patrik Hagglund virtual const TargetRegisterClass *getRegClassFor(MVT VT) const; 36106b666c7056376b8aaf40be0dc00b97b2cfceb6cEvan Cheng 362cec36f4c1118dc8388910d4753fe7cbf88d2d793Anton Korobeynikov /// getMaximalGlobalOffset - Returns the maximal possible offset which can 363cec36f4c1118dc8388910d4753fe7cbf88d2d793Anton Korobeynikov /// be used for loads / stores from the global. 364cec36f4c1118dc8388910d4753fe7cbf88d2d793Anton Korobeynikov virtual unsigned getMaximalGlobalOffset() const; 365cec36f4c1118dc8388910d4753fe7cbf88d2d793Anton Korobeynikov 366ab695889c67fb499bd902e8a969d0ff02ce66788Eric Christopher /// createFastISel - This method returns a target specific FastISel object, 367ab695889c67fb499bd902e8a969d0ff02ce66788Eric Christopher /// or null if the target does not support "fast" ISel. 368d49edb7ab098fa0c82f59efbcf1b4eb2958f8dc3Bob Wilson virtual FastISel *createFastISel(FunctionLoweringInfo &funcInfo, 369d49edb7ab098fa0c82f59efbcf1b4eb2958f8dc3Bob Wilson const TargetLibraryInfo *libInfo) const; 370ab695889c67fb499bd902e8a969d0ff02ce66788Eric Christopher 3711cc3984148be113c6e5e470f23c9ddbd37679c5fEvan Cheng Sched::Preference getSchedulingPreference(SDNode *N) const; 3721cc3984148be113c6e5e470f23c9ddbd37679c5fEvan Cheng 373d0ac234b1b3a88946ad8bb52677764f3e3eeb8b3Anton Korobeynikov bool isShuffleMaskLegal(const SmallVectorImpl<int> &M, EVT VT) const; 37448e19352840a5f7012493ead894e81a2dbec1778Anton Korobeynikov bool isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const; 37539382427f1095f089d73a7dd3d9a371dea75b781Evan Cheng 37639382427f1095f089d73a7dd3d9a371dea75b781Evan Cheng /// isFPImmLegal - Returns true if the target can instruction select the 37739382427f1095f089d73a7dd3d9a371dea75b781Evan Cheng /// specified FP immediate natively. If false, the legalizer will 37839382427f1095f089d73a7dd3d9a371dea75b781Evan Cheng /// materialize the FP immediate as a load from a constant pool. 37939382427f1095f089d73a7dd3d9a371dea75b781Evan Cheng virtual bool isFPImmLegal(const APFloat &Imm, EVT VT) const; 38039382427f1095f089d73a7dd3d9a371dea75b781Evan Cheng 38165ffec49f73d1f8856211b107712c58cc9636b78Bob Wilson virtual bool getTgtMemIntrinsic(IntrinsicInfo &Info, 38265ffec49f73d1f8856211b107712c58cc9636b78Bob Wilson const CallInst &I, 38365ffec49f73d1f8856211b107712c58cc9636b78Bob Wilson unsigned Intrinsic) const; 384d70f57b254114841892425a40944268d38ae0bcdEvan Cheng protected: 3854f6b4674be5473319ac5e70c76fd5cb964da2128Evan Cheng std::pair<const TargetRegisterClass*, uint8_t> 3860340557fb830e3669c4c48a2cd99d7703bdda452Patrik Hagglund findRepresentativeClass(MVT VT) const; 387d70f57b254114841892425a40944268d38ae0bcdEvan Cheng 388a8e2989ece6dc46df59b0768184028257f913843Evan Cheng private: 389a8e2989ece6dc46df59b0768184028257f913843Evan Cheng /// Subtarget - Keep a pointer to the ARMSubtarget around so that we can 390a8e2989ece6dc46df59b0768184028257f913843Evan Cheng /// make the right decision when generating code for different targets. 391a8e2989ece6dc46df59b0768184028257f913843Evan Cheng const ARMSubtarget *Subtarget; 392a8e2989ece6dc46df59b0768184028257f913843Evan Cheng 3933144687df78731ac4ddbc716a24b951678a73f57Evan Cheng const TargetRegisterInfo *RegInfo; 3943144687df78731ac4ddbc716a24b951678a73f57Evan Cheng 3953ef1c8759a20167457eb7fd82ebcaffe7ccaa1d1Evan Cheng const InstrItineraryData *Itins; 3963ef1c8759a20167457eb7fd82ebcaffe7ccaa1d1Evan Cheng 397d2559bf3f30cc7400483825414489ec0fb36481aBob Wilson /// ARMPCLabelIndex - Keep track of the number of ARM PC labels created. 398a8e2989ece6dc46df59b0768184028257f913843Evan Cheng /// 399a8e2989ece6dc46df59b0768184028257f913843Evan Cheng unsigned ARMPCLabelIndex; 400a8e2989ece6dc46df59b0768184028257f913843Evan Cheng 4010faf46c640c6747f1add89ba06631cebc4fa3afdCraig Topper void addTypeForNEON(MVT VT, MVT PromotedLdStVT, MVT PromotedBitwiseVT); 4020faf46c640c6747f1add89ba06631cebc4fa3afdCraig Topper void addDRTypeForNEON(MVT VT); 4030faf46c640c6747f1add89ba06631cebc4fa3afdCraig Topper void addQRTypeForNEON(MVT VT); 4045bafff36c798608a189c517d37527e4a38863071Bob Wilson 4055bafff36c798608a189c517d37527e4a38863071Bob Wilson typedef SmallVector<std::pair<unsigned, SDValue>, 8> RegsToPassVector; 406ac6d9bec671252dd1e596fa71180ff6b39d06b5dAndrew Trick void PassF64ArgInRegs(SDLoc dl, SelectionDAG &DAG, 4075bafff36c798608a189c517d37527e4a38863071Bob Wilson SDValue Chain, SDValue &Arg, 4085bafff36c798608a189c517d37527e4a38863071Bob Wilson RegsToPassVector &RegsToPass, 4095bafff36c798608a189c517d37527e4a38863071Bob Wilson CCValAssign &VA, CCValAssign &NextVA, 4105bafff36c798608a189c517d37527e4a38863071Bob Wilson SDValue &StackPtr, 411a0ec3f9b7b826b9b40b80199923b664bad808cceCraig Topper SmallVectorImpl<SDValue> &MemOpChains, 412d858e90f039f5fcdc2fa93035e911a5a9505cc50Dan Gohman ISD::ArgFlagsTy Flags) const; 4135bafff36c798608a189c517d37527e4a38863071Bob Wilson SDValue GetF64FormalArgument(CCValAssign &VA, CCValAssign &NextVA, 414d858e90f039f5fcdc2fa93035e911a5a9505cc50Dan Gohman SDValue &Root, SelectionDAG &DAG, 415ac6d9bec671252dd1e596fa71180ff6b39d06b5dAndrew Trick SDLoc dl) const; 4165bafff36c798608a189c517d37527e4a38863071Bob Wilson 41718f30e6f5e80787808fe1455742452a5210afe07Jim Grosbach CCAssignFn *CCAssignFnForNode(CallingConv::ID CC, bool Return, 41818f30e6f5e80787808fe1455742452a5210afe07Jim Grosbach bool isVarArg) const; 41998ca4f2a325f72374a477f9deba7d09e8999c29bDan Gohman SDValue LowerMemOpCallTo(SDValue Chain, SDValue StackPtr, SDValue Arg, 420ac6d9bec671252dd1e596fa71180ff6b39d06b5dAndrew Trick SDLoc dl, SelectionDAG &DAG, 42198ca4f2a325f72374a477f9deba7d09e8999c29bDan Gohman const CCValAssign &VA, 422d858e90f039f5fcdc2fa93035e911a5a9505cc50Dan Gohman ISD::ArgFlagsTy Flags) const; 42323ff7cff52702a8bff904d8ab4c9ca67cc19d6caJim Grosbach SDValue LowerEH_SJLJ_SETJMP(SDValue Op, SelectionDAG &DAG) const; 4245eb195153950bc7ebfc30649494a78b2096b5ef8Jim Grosbach SDValue LowerEH_SJLJ_LONGJMP(SDValue Op, SelectionDAG &DAG) const; 425a87ded2695e5bce30dbd0d2d2ac10c571bf1d161Jim Grosbach SDValue LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG, 426d858e90f039f5fcdc2fa93035e911a5a9505cc50Dan Gohman const ARMSubtarget *Subtarget) const; 427d858e90f039f5fcdc2fa93035e911a5a9505cc50Dan Gohman SDValue LowerBlockAddress(SDValue Op, SelectionDAG &DAG) const; 428d858e90f039f5fcdc2fa93035e911a5a9505cc50Dan Gohman SDValue LowerGlobalAddressDarwin(SDValue Op, SelectionDAG &DAG) const; 429d858e90f039f5fcdc2fa93035e911a5a9505cc50Dan Gohman SDValue LowerGlobalAddressELF(SDValue Op, SelectionDAG &DAG) const; 430d858e90f039f5fcdc2fa93035e911a5a9505cc50Dan Gohman SDValue LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const; 431475871a144eb604ddaf37503397ba0941442e5fbDan Gohman SDValue LowerToTLSGeneralDynamicModel(GlobalAddressSDNode *GA, 432d858e90f039f5fcdc2fa93035e911a5a9505cc50Dan Gohman SelectionDAG &DAG) const; 433475871a144eb604ddaf37503397ba0941442e5fbDan Gohman SDValue LowerToTLSExecModels(GlobalAddressSDNode *GA, 434fd5abd546e8e035755005a654d60d6f5f74cfe2cHans Wennborg SelectionDAG &DAG, 435fd5abd546e8e035755005a654d60d6f5f74cfe2cHans Wennborg TLSModel::Model model) const; 436d858e90f039f5fcdc2fa93035e911a5a9505cc50Dan Gohman SDValue LowerGLOBAL_OFFSET_TABLE(SDValue Op, SelectionDAG &DAG) const; 437d858e90f039f5fcdc2fa93035e911a5a9505cc50Dan Gohman SDValue LowerBR_JT(SDValue Op, SelectionDAG &DAG) const; 438de2b151dbf125af49717807b9cfc1f6f7a5b9ea6Bill Wendling SDValue LowerSELECT(SDValue Op, SelectionDAG &DAG) const; 439d858e90f039f5fcdc2fa93035e911a5a9505cc50Dan Gohman SDValue LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const; 440d858e90f039f5fcdc2fa93035e911a5a9505cc50Dan Gohman SDValue LowerBR_CC(SDValue Op, SelectionDAG &DAG) const; 441515fe3a58877c745a922252a4492e866a2f1e42eEvan Cheng SDValue LowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG) const; 4422457f2c66184e978d4ed8fa9e2128effff26cb0bEvan Cheng SDValue LowerRETURNADDR(SDValue Op, SelectionDAG &DAG) const; 443d858e90f039f5fcdc2fa93035e911a5a9505cc50Dan Gohman SDValue LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const; 444d858e90f039f5fcdc2fa93035e911a5a9505cc50Dan Gohman SDValue LowerShiftRightParts(SDValue Op, SelectionDAG &DAG) const; 445d858e90f039f5fcdc2fa93035e911a5a9505cc50Dan Gohman SDValue LowerShiftLeftParts(SDValue Op, SelectionDAG &DAG) const; 446d1fb583128c6682bb8a7c74eafa810a9270cc8dfNate Begeman SDValue LowerFLT_ROUNDS_(SDValue Op, SelectionDAG &DAG) const; 44745b5f88938f59c495209512b545f289bf2cca90aLang Hames SDValue LowerConstantFP(SDValue Op, SelectionDAG &DAG, 44845b5f88938f59c495209512b545f289bf2cca90aLang Hames const ARMSubtarget *ST) const; 4495adfba283dc0795ba005545ce38fa5b0ada14511Andrew Trick SDValue LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG, 45011a1dfffc8b6bbe0c0936c2c70681bc74bb5cd56Bob Wilson const ARMSubtarget *ST) const; 451103ba845f09252d90a05109af7174f54bf412dafRenato Golin SDValue LowerDivRem(SDValue Op, SelectionDAG &DAG) const; 45211a1dfffc8b6bbe0c0936c2c70681bc74bb5cd56Bob Wilson 4539ddfe5ea6f46448cf01e114c971e6bd7ac6ad06cStephen Lin /// isFMAFasterThanFMulAndFAdd - Return true if an FMA operation is faster 4549ddfe5ea6f46448cf01e114c971e6bd7ac6ad06cStephen Lin /// than a pair of fmul and fadd instructions. fmuladd intrinsics will be 4559ddfe5ea6f46448cf01e114c971e6bd7ac6ad06cStephen Lin /// expanded to FMAs when this method returns true, otherwise fmuladd is 4569ddfe5ea6f46448cf01e114c971e6bd7ac6ad06cStephen Lin /// expanded to fmul + fadd. 4579ddfe5ea6f46448cf01e114c971e6bd7ac6ad06cStephen Lin /// 4589ddfe5ea6f46448cf01e114c971e6bd7ac6ad06cStephen Lin /// ARM supports both fused and unfused multiply-add operations; we already 459ea870a53a5a0c644e5b15af5ae59d8a4378a4d2aStephen Lin /// lower a pair of fmul and fadd to the latter so it's not clear that there 4609ddfe5ea6f46448cf01e114c971e6bd7ac6ad06cStephen Lin /// would be a gain or that the gain would be worthwhile enough to risk 4619ddfe5ea6f46448cf01e114c971e6bd7ac6ad06cStephen Lin /// correctness bugs. 4629ddfe5ea6f46448cf01e114c971e6bd7ac6ad06cStephen Lin virtual bool isFMAFasterThanFMulAndFAdd(EVT VT) const { return false; } 4639ddfe5ea6f46448cf01e114c971e6bd7ac6ad06cStephen Lin 46411a1dfffc8b6bbe0c0936c2c70681bc74bb5cd56Bob Wilson SDValue ReconstructShuffle(SDValue Op, SelectionDAG &DAG) const; 465475871a144eb604ddaf37503397ba0941442e5fbDan Gohman 46698ca4f2a325f72374a477f9deba7d09e8999c29bDan Gohman SDValue LowerCallResult(SDValue Chain, SDValue InFlag, 46765c3c8f323198b99b88b109654194540cf9b3fa5Sandeep Patel CallingConv::ID CallConv, bool isVarArg, 46898ca4f2a325f72374a477f9deba7d09e8999c29bDan Gohman const SmallVectorImpl<ISD::InputArg> &Ins, 469ac6d9bec671252dd1e596fa71180ff6b39d06b5dAndrew Trick SDLoc dl, SelectionDAG &DAG, 470456ca048af35163b9f52187e92a23ee0a9f059e8Stephen Lin SmallVectorImpl<SDValue> &InVals, 471456ca048af35163b9f52187e92a23ee0a9f059e8Stephen Lin bool isThisReturn, SDValue ThisVal) const; 47298ca4f2a325f72374a477f9deba7d09e8999c29bDan Gohman 47398ca4f2a325f72374a477f9deba7d09e8999c29bDan Gohman virtual SDValue 47498ca4f2a325f72374a477f9deba7d09e8999c29bDan Gohman LowerFormalArguments(SDValue Chain, 47565c3c8f323198b99b88b109654194540cf9b3fa5Sandeep Patel CallingConv::ID CallConv, bool isVarArg, 47698ca4f2a325f72374a477f9deba7d09e8999c29bDan Gohman const SmallVectorImpl<ISD::InputArg> &Ins, 477ac6d9bec671252dd1e596fa71180ff6b39d06b5dAndrew Trick SDLoc dl, SelectionDAG &DAG, 478d858e90f039f5fcdc2fa93035e911a5a9505cc50Dan Gohman SmallVectorImpl<SDValue> &InVals) const; 47998ca4f2a325f72374a477f9deba7d09e8999c29bDan Gohman 480f65e4932f83ac0c36594d97fca73dc9a9fd26672Stepan Dyatkovskiy int StoreByValRegs(CCState &CCInfo, SelectionDAG &DAG, 481ac6d9bec671252dd1e596fa71180ff6b39d06b5dAndrew Trick SDLoc dl, SDValue &Chain, 482f65e4932f83ac0c36594d97fca73dc9a9fd26672Stepan Dyatkovskiy const Value *OrigArg, 48346abfcf4187432da728cbe452c32143da077e07fStepan Dyatkovskiy unsigned InRegsParamRecordIdx, 484f65e4932f83ac0c36594d97fca73dc9a9fd26672Stepan Dyatkovskiy unsigned OffsetFromOrigArg, 485f65e4932f83ac0c36594d97fca73dc9a9fd26672Stepan Dyatkovskiy unsigned ArgOffset, 486083bc97344d618884ef04bc1ba1fc4ddf14d867dStepan Dyatkovskiy unsigned ArgSize, 487f65e4932f83ac0c36594d97fca73dc9a9fd26672Stepan Dyatkovskiy bool ForceMutable) const; 488f65e4932f83ac0c36594d97fca73dc9a9fd26672Stepan Dyatkovskiy 489c73158730d43e7c8bdef32b2107566a6e78a8538Stuart Hastings void VarArgStyleRegisters(CCState &CCInfo, SelectionDAG &DAG, 490ac6d9bec671252dd1e596fa71180ff6b39d06b5dAndrew Trick SDLoc dl, SDValue &Chain, 4910d3c8d5d16caa4c4f1310699722aa2cbe2844f21Stepan Dyatkovskiy unsigned ArgOffset, 492f65e4932f83ac0c36594d97fca73dc9a9fd26672Stepan Dyatkovskiy bool ForceMutable = false) const; 493c73158730d43e7c8bdef32b2107566a6e78a8538Stuart Hastings 494c73158730d43e7c8bdef32b2107566a6e78a8538Stuart Hastings void computeRegArea(CCState &CCInfo, MachineFunction &MF, 49546abfcf4187432da728cbe452c32143da077e07fStepan Dyatkovskiy unsigned InRegsParamRecordIdx, 496083bc97344d618884ef04bc1ba1fc4ddf14d867dStepan Dyatkovskiy unsigned ArgSize, 497f65e4932f83ac0c36594d97fca73dc9a9fd26672Stepan Dyatkovskiy unsigned &ArgRegsSize, 498f65e4932f83ac0c36594d97fca73dc9a9fd26672Stepan Dyatkovskiy unsigned &ArgRegsSaveSize) const; 499c73158730d43e7c8bdef32b2107566a6e78a8538Stuart Hastings 50098ca4f2a325f72374a477f9deba7d09e8999c29bDan Gohman virtual SDValue 501d2ea0e10cbd158c93fb870cdd03001b9cd1156b8Justin Holewinski LowerCall(TargetLowering::CallLoweringInfo &CLI, 502d858e90f039f5fcdc2fa93035e911a5a9505cc50Dan Gohman SmallVectorImpl<SDValue> &InVals) const; 50398ca4f2a325f72374a477f9deba7d09e8999c29bDan Gohman 504f222e595c0137b8a9571408257f7000c2fb95473Stuart Hastings /// HandleByVal - Target-specific cleanup for ByVal support. 505b52ba9f8a896b6717d6395ad59f6550e1fa475b0Stepan Dyatkovskiy virtual void HandleByVal(CCState *, unsigned &, unsigned) const; 506f222e595c0137b8a9571408257f7000c2fb95473Stuart Hastings 50751e28e634880849ed9f7c02e93c08d25dd70291bDale Johannesen /// IsEligibleForTailCallOptimization - Check whether the call is eligible 50851e28e634880849ed9f7c02e93c08d25dd70291bDale Johannesen /// for tail call optimization. Targets which want to do tail call 50951e28e634880849ed9f7c02e93c08d25dd70291bDale Johannesen /// optimization should implement this function. 51051e28e634880849ed9f7c02e93c08d25dd70291bDale Johannesen bool IsEligibleForTailCallOptimization(SDValue Callee, 51151e28e634880849ed9f7c02e93c08d25dd70291bDale Johannesen CallingConv::ID CalleeCC, 51251e28e634880849ed9f7c02e93c08d25dd70291bDale Johannesen bool isVarArg, 51351e28e634880849ed9f7c02e93c08d25dd70291bDale Johannesen bool isCalleeStructRet, 51451e28e634880849ed9f7c02e93c08d25dd70291bDale Johannesen bool isCallerStructRet, 51551e28e634880849ed9f7c02e93c08d25dd70291bDale Johannesen const SmallVectorImpl<ISD::OutputArg> &Outs, 516c9403659a98bf6487ab6fbf40b81628b5695c02eDan Gohman const SmallVectorImpl<SDValue> &OutVals, 51751e28e634880849ed9f7c02e93c08d25dd70291bDale Johannesen const SmallVectorImpl<ISD::InputArg> &Ins, 51851e28e634880849ed9f7c02e93c08d25dd70291bDale Johannesen SelectionDAG& DAG) const; 519350c00843bad22c5391e33e9e39a78d5d0983c8cBenjamin Kramer 520350c00843bad22c5391e33e9e39a78d5d0983c8cBenjamin Kramer virtual bool CanLowerReturn(CallingConv::ID CallConv, 521350c00843bad22c5391e33e9e39a78d5d0983c8cBenjamin Kramer MachineFunction &MF, bool isVarArg, 522350c00843bad22c5391e33e9e39a78d5d0983c8cBenjamin Kramer const SmallVectorImpl<ISD::OutputArg> &Outs, 523350c00843bad22c5391e33e9e39a78d5d0983c8cBenjamin Kramer LLVMContext &Context) const; 524350c00843bad22c5391e33e9e39a78d5d0983c8cBenjamin Kramer 52598ca4f2a325f72374a477f9deba7d09e8999c29bDan Gohman virtual SDValue 52698ca4f2a325f72374a477f9deba7d09e8999c29bDan Gohman LowerReturn(SDValue Chain, 52765c3c8f323198b99b88b109654194540cf9b3fa5Sandeep Patel CallingConv::ID CallConv, bool isVarArg, 52898ca4f2a325f72374a477f9deba7d09e8999c29bDan Gohman const SmallVectorImpl<ISD::OutputArg> &Outs, 529c9403659a98bf6487ab6fbf40b81628b5695c02eDan Gohman const SmallVectorImpl<SDValue> &OutVals, 530ac6d9bec671252dd1e596fa71180ff6b39d06b5dAndrew Trick SDLoc dl, SelectionDAG &DAG) const; 53106b53c0d51f029eb754b40350faf5ba4b33c4bcbEvan Cheng 532bf010eb9110009d745382bf15131fbe556562ffeEvan Cheng virtual bool isUsedByReturnOnly(SDNode *N, SDValue &Chain) const; 5333d2125c9dbac695c93f42c0f59fd040e413fd711Evan Cheng 534485fafc8406db8552ba5e3ff871a6ee32694ad90Evan Cheng virtual bool mayBeEmittedAsTailCall(CallInst *CI) const; 535485fafc8406db8552ba5e3ff871a6ee32694ad90Evan Cheng 53606b53c0d51f029eb754b40350faf5ba4b33c4bcbEvan Cheng SDValue getARMCmp(SDValue LHS, SDValue RHS, ISD::CondCode CC, 537ac6d9bec671252dd1e596fa71180ff6b39d06b5dAndrew Trick SDValue &ARMcc, SelectionDAG &DAG, SDLoc dl) const; 538218977b53eb215e5534db2f727d109ab18817cc1Evan Cheng SDValue getVFPCmp(SDValue LHS, SDValue RHS, 539ac6d9bec671252dd1e596fa71180ff6b39d06b5dAndrew Trick SelectionDAG &DAG, SDLoc dl) const; 54079f56c9618e60c390932a6866929b82c9a6d6f96Bob Wilson SDValue duplicateCmp(SDValue Cmp, SelectionDAG &DAG) const; 541218977b53eb215e5534db2f727d109ab18817cc1Evan Cheng 542218977b53eb215e5534db2f727d109ab18817cc1Evan Cheng SDValue OptimizeVFPBrcond(SDValue Op, SelectionDAG &DAG) const; 5435278eb802fae2ee1a7b2a428596bc364d8bcd9dbJim Grosbach 544e801dc4a7b89f68f40ff2753de988c482d4d117fJim Grosbach MachineBasicBlock *EmitAtomicCmpSwap(MachineInstr *MI, 545e801dc4a7b89f68f40ff2753de988c482d4d117fJim Grosbach MachineBasicBlock *BB, 546e801dc4a7b89f68f40ff2753de988c482d4d117fJim Grosbach unsigned Size) const; 547e801dc4a7b89f68f40ff2753de988c482d4d117fJim Grosbach MachineBasicBlock *EmitAtomicBinary(MachineInstr *MI, 548e801dc4a7b89f68f40ff2753de988c482d4d117fJim Grosbach MachineBasicBlock *BB, 549e801dc4a7b89f68f40ff2753de988c482d4d117fJim Grosbach unsigned Size, 550e801dc4a7b89f68f40ff2753de988c482d4d117fJim Grosbach unsigned BinOpcode) const; 5512bdffe488203a08a2ca98548a157e0eaf39d4b2dEli Friedman MachineBasicBlock *EmitAtomicBinary64(MachineInstr *MI, 5522bdffe488203a08a2ca98548a157e0eaf39d4b2dEli Friedman MachineBasicBlock *BB, 5532bdffe488203a08a2ca98548a157e0eaf39d4b2dEli Friedman unsigned Op1, 5542bdffe488203a08a2ca98548a157e0eaf39d4b2dEli Friedman unsigned Op2, 5554d3f3294535a3b622c715f2d9675d4f3e86c3378Eli Friedman bool NeedsCarry = false, 55635b3df6e31f9aac70fb471d74e39f899dfbd689fSilviu Baranga bool IsCmpxchg = false, 55735b3df6e31f9aac70fb471d74e39f899dfbd689fSilviu Baranga bool IsMinMax = false, 55835b3df6e31f9aac70fb471d74e39f899dfbd689fSilviu Baranga ARMCC::CondCodes CC = ARMCC::AL) const; 559f7da8821b4c491b1c2ce7ac2374e46d8abdba518Jim Grosbach MachineBasicBlock * EmitAtomicBinaryMinMax(MachineInstr *MI, 560f7da8821b4c491b1c2ce7ac2374e46d8abdba518Jim Grosbach MachineBasicBlock *BB, 561f7da8821b4c491b1c2ce7ac2374e46d8abdba518Jim Grosbach unsigned Size, 562f7da8821b4c491b1c2ce7ac2374e46d8abdba518Jim Grosbach bool signExtend, 563f7da8821b4c491b1c2ce7ac2374e46d8abdba518Jim Grosbach ARMCC::CondCodes Cond) const; 564268c743a3ba44ada364938bc5ff9b1be219df54fAmara Emerson MachineBasicBlock *EmitAtomicLoad64(MachineInstr *MI, 565268c743a3ba44ada364938bc5ff9b1be219df54fAmara Emerson MachineBasicBlock *BB) const; 5665278eb802fae2ee1a7b2a428596bc364d8bcd9dbJim Grosbach 567e29fa1df55584b6f07290a91e33bf742f1c549e4Bill Wendling void SetupEntryBlockForSjLj(MachineInstr *MI, 568e29fa1df55584b6f07290a91e33bf742f1c549e4Bill Wendling MachineBasicBlock *MBB, 569e29fa1df55584b6f07290a91e33bf742f1c549e4Bill Wendling MachineBasicBlock *DispatchBB, int FI) const; 570e29fa1df55584b6f07290a91e33bf742f1c549e4Bill Wendling 571f7e4aefd0f78441bef3b9eb683ecccbed9582b8aBill Wendling MachineBasicBlock *EmitSjLjDispatchBlock(MachineInstr *MI, 572f7e4aefd0f78441bef3b9eb683ecccbed9582b8aBill Wendling MachineBasicBlock *MBB) const; 573f7e4aefd0f78441bef3b9eb683ecccbed9582b8aBill Wendling 5741c3af779fc6b184204efd7e98dc16e475c251e7fAndrew Trick bool RemapAddSubWithFlags(MachineInstr *MI, MachineBasicBlock *BB) const; 57568f25571e759c1fcf2da206109647259f49f7416Manman Ren 57668f25571e759c1fcf2da206109647259f49f7416Manman Ren MachineBasicBlock *EmitStructByval(MachineInstr *MI, 57768f25571e759c1fcf2da206109647259f49f7416Manman Ren MachineBasicBlock *MBB) const; 578a8e2989ece6dc46df59b0768184028257f913843Evan Cheng }; 5795adfba283dc0795ba005545ce38fa5b0ada14511Andrew Trick 58036fa3ea566c66b42e4dd7b4394be2f1e071647b8Owen Anderson enum NEONModImmType { 58136fa3ea566c66b42e4dd7b4394be2f1e071647b8Owen Anderson VMOVModImm, 58236fa3ea566c66b42e4dd7b4394be2f1e071647b8Owen Anderson VMVNModImm, 58336fa3ea566c66b42e4dd7b4394be2f1e071647b8Owen Anderson OtherModImm 58436fa3ea566c66b42e4dd7b4394be2f1e071647b8Owen Anderson }; 5855adfba283dc0795ba005545ce38fa5b0ada14511Andrew Trick 5865adfba283dc0795ba005545ce38fa5b0ada14511Andrew Trick 587ab695889c67fb499bd902e8a969d0ff02ce66788Eric Christopher namespace ARM { 588d49edb7ab098fa0c82f59efbcf1b4eb2958f8dc3Bob Wilson FastISel *createFastISel(FunctionLoweringInfo &funcInfo, 589d49edb7ab098fa0c82f59efbcf1b4eb2958f8dc3Bob Wilson const TargetLibraryInfo *libInfo); 590ab695889c67fb499bd902e8a969d0ff02ce66788Eric Christopher } 591a8e2989ece6dc46df59b0768184028257f913843Evan Cheng} 592a8e2989ece6dc46df59b0768184028257f913843Evan Cheng 593a8e2989ece6dc46df59b0768184028257f913843Evan Cheng#endif // ARMISELLOWERING_H 594