ARMISelLowering.h revision 36b56886974eae4f9c5ebc96befd3e7bfe5de338
1//===-- ARMISelLowering.h - ARM DAG Lowering Interface ----------*- C++ -*-===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file defines the interfaces that ARM uses to lower LLVM code into a 11// selection DAG. 12// 13//===----------------------------------------------------------------------===// 14 15#ifndef ARMISELLOWERING_H 16#define ARMISELLOWERING_H 17 18#include "MCTargetDesc/ARMBaseInfo.h" 19#include "llvm/CodeGen/CallingConvLower.h" 20#include "llvm/CodeGen/SelectionDAG.h" 21#include "llvm/Target/TargetLowering.h" 22#include <vector> 23 24namespace llvm { 25 class ARMConstantPoolValue; 26 class ARMSubtarget; 27 28 namespace ARMISD { 29 // ARM Specific DAG Nodes 30 enum NodeType { 31 // Start the numbering where the builtin ops and target ops leave off. 32 FIRST_NUMBER = ISD::BUILTIN_OP_END, 33 34 Wrapper, // Wrapper - A wrapper node for TargetConstantPool, 35 // TargetExternalSymbol, and TargetGlobalAddress. 36 WrapperPIC, // WrapperPIC - A wrapper node for TargetGlobalAddress in 37 // PIC mode. 38 WrapperJT, // WrapperJT - A wrapper node for TargetJumpTable 39 40 // Add pseudo op to model memcpy for struct byval. 41 COPY_STRUCT_BYVAL, 42 43 CALL, // Function call. 44 CALL_PRED, // Function call that's predicable. 45 CALL_NOLINK, // Function call with branch not branch-and-link. 46 tCALL, // Thumb function call. 47 BRCOND, // Conditional branch. 48 BR_JT, // Jumptable branch. 49 BR2_JT, // Jumptable branch (2 level - jumptable entry is a jump). 50 RET_FLAG, // Return with a flag operand. 51 INTRET_FLAG, // Interrupt return with an LR-offset and a flag operand. 52 53 PIC_ADD, // Add with a PC operand and a PIC label. 54 55 CMP, // ARM compare instructions. 56 CMN, // ARM CMN instructions. 57 CMPZ, // ARM compare that sets only Z flag. 58 CMPFP, // ARM VFP compare instruction, sets FPSCR. 59 CMPFPw0, // ARM VFP compare against zero instruction, sets FPSCR. 60 FMSTAT, // ARM fmstat instruction. 61 62 CMOV, // ARM conditional move instructions. 63 64 BCC_i64, 65 66 RBIT, // ARM bitreverse instruction 67 68 FTOSI, // FP to sint within a FP register. 69 FTOUI, // FP to uint within a FP register. 70 SITOF, // sint to FP within a FP register. 71 UITOF, // uint to FP within a FP register. 72 73 SRL_FLAG, // V,Flag = srl_flag X -> srl X, 1 + save carry out. 74 SRA_FLAG, // V,Flag = sra_flag X -> sra X, 1 + save carry out. 75 RRX, // V = RRX X, Flag -> srl X, 1 + shift in carry flag. 76 77 ADDC, // Add with carry 78 ADDE, // Add using carry 79 SUBC, // Sub with carry 80 SUBE, // Sub using carry 81 82 VMOVRRD, // double to two gprs. 83 VMOVDRR, // Two gprs to double. 84 85 EH_SJLJ_SETJMP, // SjLj exception handling setjmp. 86 EH_SJLJ_LONGJMP, // SjLj exception handling longjmp. 87 88 TC_RETURN, // Tail call return pseudo. 89 90 THREAD_POINTER, 91 92 DYN_ALLOC, // Dynamic allocation on the stack. 93 94 MEMBARRIER_MCR, // Memory barrier (MCR) 95 96 PRELOAD, // Preload 97 98 VCEQ, // Vector compare equal. 99 VCEQZ, // Vector compare equal to zero. 100 VCGE, // Vector compare greater than or equal. 101 VCGEZ, // Vector compare greater than or equal to zero. 102 VCLEZ, // Vector compare less than or equal to zero. 103 VCGEU, // Vector compare unsigned greater than or equal. 104 VCGT, // Vector compare greater than. 105 VCGTZ, // Vector compare greater than zero. 106 VCLTZ, // Vector compare less than zero. 107 VCGTU, // Vector compare unsigned greater than. 108 VTST, // Vector test bits. 109 110 // Vector shift by immediate: 111 VSHL, // ...left 112 VSHRs, // ...right (signed) 113 VSHRu, // ...right (unsigned) 114 115 // Vector rounding shift by immediate: 116 VRSHRs, // ...right (signed) 117 VRSHRu, // ...right (unsigned) 118 VRSHRN, // ...right narrow 119 120 // Vector saturating shift by immediate: 121 VQSHLs, // ...left (signed) 122 VQSHLu, // ...left (unsigned) 123 VQSHLsu, // ...left (signed to unsigned) 124 VQSHRNs, // ...right narrow (signed) 125 VQSHRNu, // ...right narrow (unsigned) 126 VQSHRNsu, // ...right narrow (signed to unsigned) 127 128 // Vector saturating rounding shift by immediate: 129 VQRSHRNs, // ...right narrow (signed) 130 VQRSHRNu, // ...right narrow (unsigned) 131 VQRSHRNsu, // ...right narrow (signed to unsigned) 132 133 // Vector shift and insert: 134 VSLI, // ...left 135 VSRI, // ...right 136 137 // Vector get lane (VMOV scalar to ARM core register) 138 // (These are used for 8- and 16-bit element types only.) 139 VGETLANEu, // zero-extend vector extract element 140 VGETLANEs, // sign-extend vector extract element 141 142 // Vector move immediate and move negated immediate: 143 VMOVIMM, 144 VMVNIMM, 145 146 // Vector move f32 immediate: 147 VMOVFPIMM, 148 149 // Vector duplicate: 150 VDUP, 151 VDUPLANE, 152 153 // Vector shuffles: 154 VEXT, // extract 155 VREV64, // reverse elements within 64-bit doublewords 156 VREV32, // reverse elements within 32-bit words 157 VREV16, // reverse elements within 16-bit halfwords 158 VZIP, // zip (interleave) 159 VUZP, // unzip (deinterleave) 160 VTRN, // transpose 161 VTBL1, // 1-register shuffle with mask 162 VTBL2, // 2-register shuffle with mask 163 164 // Vector multiply long: 165 VMULLs, // ...signed 166 VMULLu, // ...unsigned 167 168 UMLAL, // 64bit Unsigned Accumulate Multiply 169 SMLAL, // 64bit Signed Accumulate Multiply 170 171 // Operands of the standard BUILD_VECTOR node are not legalized, which 172 // is fine if BUILD_VECTORs are always lowered to shuffles or other 173 // operations, but for ARM some BUILD_VECTORs are legal as-is and their 174 // operands need to be legalized. Define an ARM-specific version of 175 // BUILD_VECTOR for this purpose. 176 BUILD_VECTOR, 177 178 // Floating-point max and min: 179 FMAX, 180 FMIN, 181 VMAXNM, 182 VMINNM, 183 184 // Bit-field insert 185 BFI, 186 187 // Vector OR with immediate 188 VORRIMM, 189 // Vector AND with NOT of immediate 190 VBICIMM, 191 192 // Vector bitwise select 193 VBSL, 194 195 // Vector load N-element structure to all lanes: 196 VLD2DUP = ISD::FIRST_TARGET_MEMORY_OPCODE, 197 VLD3DUP, 198 VLD4DUP, 199 200 // NEON loads with post-increment base updates: 201 VLD1_UPD, 202 VLD2_UPD, 203 VLD3_UPD, 204 VLD4_UPD, 205 VLD2LN_UPD, 206 VLD3LN_UPD, 207 VLD4LN_UPD, 208 VLD2DUP_UPD, 209 VLD3DUP_UPD, 210 VLD4DUP_UPD, 211 212 // NEON stores with post-increment base updates: 213 VST1_UPD, 214 VST2_UPD, 215 VST3_UPD, 216 VST4_UPD, 217 VST2LN_UPD, 218 VST3LN_UPD, 219 VST4LN_UPD 220 }; 221 } 222 223 /// Define some predicates that are used for node matching. 224 namespace ARM { 225 bool isBitFieldInvertedMask(unsigned v); 226 } 227 228 //===--------------------------------------------------------------------===// 229 // ARMTargetLowering - ARM Implementation of the TargetLowering interface 230 231 class ARMTargetLowering : public TargetLowering { 232 public: 233 explicit ARMTargetLowering(TargetMachine &TM); 234 235 unsigned getJumpTableEncoding() const override; 236 237 SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override; 238 239 /// ReplaceNodeResults - Replace the results of node with an illegal result 240 /// type with new values built out of custom code. 241 /// 242 void ReplaceNodeResults(SDNode *N, SmallVectorImpl<SDValue>&Results, 243 SelectionDAG &DAG) const override; 244 245 const char *getTargetNodeName(unsigned Opcode) const override; 246 247 bool isSelectSupported(SelectSupportKind Kind) const override { 248 // ARM does not support scalar condition selects on vectors. 249 return (Kind != ScalarCondVectorVal); 250 } 251 252 /// getSetCCResultType - Return the value type to use for ISD::SETCC. 253 EVT getSetCCResultType(LLVMContext &Context, EVT VT) const override; 254 255 MachineBasicBlock * 256 EmitInstrWithCustomInserter(MachineInstr *MI, 257 MachineBasicBlock *MBB) const override; 258 259 void AdjustInstrPostInstrSelection(MachineInstr *MI, 260 SDNode *Node) const override; 261 262 SDValue PerformCMOVCombine(SDNode *N, SelectionDAG &DAG) const; 263 SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const override; 264 265 bool isDesirableToTransformToIntegerOp(unsigned Opc, EVT VT) const override; 266 267 /// allowsUnalignedMemoryAccesses - Returns true if the target allows 268 /// unaligned memory accesses of the specified type. Returns whether it 269 /// is "fast" by reference in the second argument. 270 bool allowsUnalignedMemoryAccesses(EVT VT, unsigned AddrSpace, 271 bool *Fast) const override; 272 273 EVT getOptimalMemOpType(uint64_t Size, 274 unsigned DstAlign, unsigned SrcAlign, 275 bool IsMemset, bool ZeroMemset, 276 bool MemcpyStrSrc, 277 MachineFunction &MF) const override; 278 279 using TargetLowering::isZExtFree; 280 bool isZExtFree(SDValue Val, EVT VT2) const override; 281 282 bool allowTruncateForTailCall(Type *Ty1, Type *Ty2) const override; 283 284 285 /// isLegalAddressingMode - Return true if the addressing mode represented 286 /// by AM is legal for this target, for a load/store of the specified type. 287 bool isLegalAddressingMode(const AddrMode &AM, Type *Ty) const override; 288 bool isLegalT2ScaledAddressingMode(const AddrMode &AM, EVT VT) const; 289 290 /// isLegalICmpImmediate - Return true if the specified immediate is legal 291 /// icmp immediate, that is the target has icmp instructions which can 292 /// compare a register against the immediate without having to materialize 293 /// the immediate into a register. 294 bool isLegalICmpImmediate(int64_t Imm) const override; 295 296 /// isLegalAddImmediate - Return true if the specified immediate is legal 297 /// add immediate, that is the target has add instructions which can 298 /// add a register and the immediate without having to materialize 299 /// the immediate into a register. 300 bool isLegalAddImmediate(int64_t Imm) const override; 301 302 /// getPreIndexedAddressParts - returns true by value, base pointer and 303 /// offset pointer and addressing mode by reference if the node's address 304 /// can be legally represented as pre-indexed load / store address. 305 bool getPreIndexedAddressParts(SDNode *N, SDValue &Base, SDValue &Offset, 306 ISD::MemIndexedMode &AM, 307 SelectionDAG &DAG) const override; 308 309 /// getPostIndexedAddressParts - returns true by value, base pointer and 310 /// offset pointer and addressing mode by reference if this node can be 311 /// combined with a load / store to form a post-indexed load / store. 312 bool getPostIndexedAddressParts(SDNode *N, SDNode *Op, SDValue &Base, 313 SDValue &Offset, ISD::MemIndexedMode &AM, 314 SelectionDAG &DAG) const override; 315 316 void computeMaskedBitsForTargetNode(const SDValue Op, APInt &KnownZero, 317 APInt &KnownOne, 318 const SelectionDAG &DAG, 319 unsigned Depth) const override; 320 321 322 bool ExpandInlineAsm(CallInst *CI) const override; 323 324 ConstraintType 325 getConstraintType(const std::string &Constraint) const override; 326 327 /// Examine constraint string and operand type and determine a weight value. 328 /// The operand object must already have been set up with the operand type. 329 ConstraintWeight getSingleConstraintMatchWeight( 330 AsmOperandInfo &info, const char *constraint) const override; 331 332 std::pair<unsigned, const TargetRegisterClass*> 333 getRegForInlineAsmConstraint(const std::string &Constraint, 334 MVT VT) const override; 335 336 /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops 337 /// vector. If it is invalid, don't add anything to Ops. If hasMemory is 338 /// true it means one of the asm constraint of the inline asm instruction 339 /// being processed is 'm'. 340 void LowerAsmOperandForConstraint(SDValue Op, std::string &Constraint, 341 std::vector<SDValue> &Ops, 342 SelectionDAG &DAG) const override; 343 344 const ARMSubtarget* getSubtarget() const { 345 return Subtarget; 346 } 347 348 /// getRegClassFor - Return the register class that should be used for the 349 /// specified value type. 350 const TargetRegisterClass *getRegClassFor(MVT VT) const override; 351 352 /// getMaximalGlobalOffset - Returns the maximal possible offset which can 353 /// be used for loads / stores from the global. 354 unsigned getMaximalGlobalOffset() const override; 355 356 /// Returns true if a cast between SrcAS and DestAS is a noop. 357 bool isNoopAddrSpaceCast(unsigned SrcAS, unsigned DestAS) const override { 358 // Addrspacecasts are always noops. 359 return true; 360 } 361 362 /// createFastISel - This method returns a target specific FastISel object, 363 /// or null if the target does not support "fast" ISel. 364 FastISel *createFastISel(FunctionLoweringInfo &funcInfo, 365 const TargetLibraryInfo *libInfo) const override; 366 367 Sched::Preference getSchedulingPreference(SDNode *N) const override; 368 369 bool 370 isShuffleMaskLegal(const SmallVectorImpl<int> &M, EVT VT) const override; 371 bool isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const override; 372 373 /// isFPImmLegal - Returns true if the target can instruction select the 374 /// specified FP immediate natively. If false, the legalizer will 375 /// materialize the FP immediate as a load from a constant pool. 376 bool isFPImmLegal(const APFloat &Imm, EVT VT) const override; 377 378 bool getTgtMemIntrinsic(IntrinsicInfo &Info, 379 const CallInst &I, 380 unsigned Intrinsic) const override; 381 382 /// \brief Returns true if it is beneficial to convert a load of a constant 383 /// to just the constant itself. 384 bool shouldConvertConstantLoadToIntImm(const APInt &Imm, 385 Type *Ty) const override; 386 387 protected: 388 std::pair<const TargetRegisterClass*, uint8_t> 389 findRepresentativeClass(MVT VT) const override; 390 391 private: 392 /// Subtarget - Keep a pointer to the ARMSubtarget around so that we can 393 /// make the right decision when generating code for different targets. 394 const ARMSubtarget *Subtarget; 395 396 const TargetRegisterInfo *RegInfo; 397 398 const InstrItineraryData *Itins; 399 400 /// ARMPCLabelIndex - Keep track of the number of ARM PC labels created. 401 /// 402 unsigned ARMPCLabelIndex; 403 404 void addTypeForNEON(MVT VT, MVT PromotedLdStVT, MVT PromotedBitwiseVT); 405 void addDRTypeForNEON(MVT VT); 406 void addQRTypeForNEON(MVT VT); 407 408 typedef SmallVector<std::pair<unsigned, SDValue>, 8> RegsToPassVector; 409 void PassF64ArgInRegs(SDLoc dl, SelectionDAG &DAG, 410 SDValue Chain, SDValue &Arg, 411 RegsToPassVector &RegsToPass, 412 CCValAssign &VA, CCValAssign &NextVA, 413 SDValue &StackPtr, 414 SmallVectorImpl<SDValue> &MemOpChains, 415 ISD::ArgFlagsTy Flags) const; 416 SDValue GetF64FormalArgument(CCValAssign &VA, CCValAssign &NextVA, 417 SDValue &Root, SelectionDAG &DAG, 418 SDLoc dl) const; 419 420 CCAssignFn *CCAssignFnForNode(CallingConv::ID CC, bool Return, 421 bool isVarArg) const; 422 SDValue LowerMemOpCallTo(SDValue Chain, SDValue StackPtr, SDValue Arg, 423 SDLoc dl, SelectionDAG &DAG, 424 const CCValAssign &VA, 425 ISD::ArgFlagsTy Flags) const; 426 SDValue LowerEH_SJLJ_SETJMP(SDValue Op, SelectionDAG &DAG) const; 427 SDValue LowerEH_SJLJ_LONGJMP(SDValue Op, SelectionDAG &DAG) const; 428 SDValue LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG, 429 const ARMSubtarget *Subtarget) const; 430 SDValue LowerBlockAddress(SDValue Op, SelectionDAG &DAG) const; 431 SDValue LowerGlobalAddressDarwin(SDValue Op, SelectionDAG &DAG) const; 432 SDValue LowerGlobalAddressELF(SDValue Op, SelectionDAG &DAG) const; 433 SDValue LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const; 434 SDValue LowerToTLSGeneralDynamicModel(GlobalAddressSDNode *GA, 435 SelectionDAG &DAG) const; 436 SDValue LowerToTLSExecModels(GlobalAddressSDNode *GA, 437 SelectionDAG &DAG, 438 TLSModel::Model model) const; 439 SDValue LowerGLOBAL_OFFSET_TABLE(SDValue Op, SelectionDAG &DAG) const; 440 SDValue LowerBR_JT(SDValue Op, SelectionDAG &DAG) const; 441 SDValue LowerSELECT(SDValue Op, SelectionDAG &DAG) const; 442 SDValue LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const; 443 SDValue LowerBR_CC(SDValue Op, SelectionDAG &DAG) const; 444 SDValue LowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG) const; 445 SDValue LowerRETURNADDR(SDValue Op, SelectionDAG &DAG) const; 446 SDValue LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const; 447 SDValue LowerShiftRightParts(SDValue Op, SelectionDAG &DAG) const; 448 SDValue LowerShiftLeftParts(SDValue Op, SelectionDAG &DAG) const; 449 SDValue LowerFLT_ROUNDS_(SDValue Op, SelectionDAG &DAG) const; 450 SDValue LowerConstantFP(SDValue Op, SelectionDAG &DAG, 451 const ARMSubtarget *ST) const; 452 SDValue LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG, 453 const ARMSubtarget *ST) const; 454 SDValue LowerFSINCOS(SDValue Op, SelectionDAG &DAG) const; 455 SDValue LowerDivRem(SDValue Op, SelectionDAG &DAG) const; 456 457 /// isFMAFasterThanFMulAndFAdd - Return true if an FMA operation is faster 458 /// than a pair of fmul and fadd instructions. fmuladd intrinsics will be 459 /// expanded to FMAs when this method returns true, otherwise fmuladd is 460 /// expanded to fmul + fadd. 461 /// 462 /// ARM supports both fused and unfused multiply-add operations; we already 463 /// lower a pair of fmul and fadd to the latter so it's not clear that there 464 /// would be a gain or that the gain would be worthwhile enough to risk 465 /// correctness bugs. 466 bool isFMAFasterThanFMulAndFAdd(EVT VT) const override { return false; } 467 468 SDValue ReconstructShuffle(SDValue Op, SelectionDAG &DAG) const; 469 470 SDValue LowerCallResult(SDValue Chain, SDValue InFlag, 471 CallingConv::ID CallConv, bool isVarArg, 472 const SmallVectorImpl<ISD::InputArg> &Ins, 473 SDLoc dl, SelectionDAG &DAG, 474 SmallVectorImpl<SDValue> &InVals, 475 bool isThisReturn, SDValue ThisVal) const; 476 477 SDValue 478 LowerFormalArguments(SDValue Chain, 479 CallingConv::ID CallConv, bool isVarArg, 480 const SmallVectorImpl<ISD::InputArg> &Ins, 481 SDLoc dl, SelectionDAG &DAG, 482 SmallVectorImpl<SDValue> &InVals) const override; 483 484 int StoreByValRegs(CCState &CCInfo, SelectionDAG &DAG, 485 SDLoc dl, SDValue &Chain, 486 const Value *OrigArg, 487 unsigned InRegsParamRecordIdx, 488 unsigned OffsetFromOrigArg, 489 unsigned ArgOffset, 490 unsigned ArgSize, 491 bool ForceMutable, 492 unsigned ByValStoreOffset, 493 unsigned TotalArgRegsSaveSize) const; 494 495 void VarArgStyleRegisters(CCState &CCInfo, SelectionDAG &DAG, 496 SDLoc dl, SDValue &Chain, 497 unsigned ArgOffset, 498 unsigned TotalArgRegsSaveSize, 499 bool ForceMutable = false) const; 500 501 void computeRegArea(CCState &CCInfo, MachineFunction &MF, 502 unsigned InRegsParamRecordIdx, 503 unsigned ArgSize, 504 unsigned &ArgRegsSize, 505 unsigned &ArgRegsSaveSize) const; 506 507 SDValue 508 LowerCall(TargetLowering::CallLoweringInfo &CLI, 509 SmallVectorImpl<SDValue> &InVals) const override; 510 511 /// HandleByVal - Target-specific cleanup for ByVal support. 512 void HandleByVal(CCState *, unsigned &, unsigned) const override; 513 514 /// IsEligibleForTailCallOptimization - Check whether the call is eligible 515 /// for tail call optimization. Targets which want to do tail call 516 /// optimization should implement this function. 517 bool IsEligibleForTailCallOptimization(SDValue Callee, 518 CallingConv::ID CalleeCC, 519 bool isVarArg, 520 bool isCalleeStructRet, 521 bool isCallerStructRet, 522 const SmallVectorImpl<ISD::OutputArg> &Outs, 523 const SmallVectorImpl<SDValue> &OutVals, 524 const SmallVectorImpl<ISD::InputArg> &Ins, 525 SelectionDAG& DAG) const; 526 527 bool CanLowerReturn(CallingConv::ID CallConv, 528 MachineFunction &MF, bool isVarArg, 529 const SmallVectorImpl<ISD::OutputArg> &Outs, 530 LLVMContext &Context) const override; 531 532 SDValue 533 LowerReturn(SDValue Chain, 534 CallingConv::ID CallConv, bool isVarArg, 535 const SmallVectorImpl<ISD::OutputArg> &Outs, 536 const SmallVectorImpl<SDValue> &OutVals, 537 SDLoc dl, SelectionDAG &DAG) const override; 538 539 bool isUsedByReturnOnly(SDNode *N, SDValue &Chain) const override; 540 541 bool mayBeEmittedAsTailCall(CallInst *CI) const override; 542 543 SDValue getARMCmp(SDValue LHS, SDValue RHS, ISD::CondCode CC, 544 SDValue &ARMcc, SelectionDAG &DAG, SDLoc dl) const; 545 SDValue getVFPCmp(SDValue LHS, SDValue RHS, 546 SelectionDAG &DAG, SDLoc dl) const; 547 SDValue duplicateCmp(SDValue Cmp, SelectionDAG &DAG) const; 548 549 SDValue OptimizeVFPBrcond(SDValue Op, SelectionDAG &DAG) const; 550 551 void SetupEntryBlockForSjLj(MachineInstr *MI, 552 MachineBasicBlock *MBB, 553 MachineBasicBlock *DispatchBB, int FI) const; 554 555 MachineBasicBlock *EmitSjLjDispatchBlock(MachineInstr *MI, 556 MachineBasicBlock *MBB) const; 557 558 bool RemapAddSubWithFlags(MachineInstr *MI, MachineBasicBlock *BB) const; 559 560 MachineBasicBlock *EmitStructByval(MachineInstr *MI, 561 MachineBasicBlock *MBB) const; 562 }; 563 564 enum NEONModImmType { 565 VMOVModImm, 566 VMVNModImm, 567 OtherModImm 568 }; 569 570 571 namespace ARM { 572 FastISel *createFastISel(FunctionLoweringInfo &funcInfo, 573 const TargetLibraryInfo *libInfo); 574 } 575} 576 577#endif // ARMISELLOWERING_H 578