ARMISelLowering.h revision 64f2e2acdc30017773ef58eb46f1a1be2a8cdb41
1//===-- ARMISelLowering.h - ARM DAG Lowering Interface ----------*- C++ -*-===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file defines the interfaces that ARM uses to lower LLVM code into a 11// selection DAG. 12// 13//===----------------------------------------------------------------------===// 14 15#ifndef ARMISELLOWERING_H 16#define ARMISELLOWERING_H 17 18#include "ARMSubtarget.h" 19#include "llvm/Target/TargetLowering.h" 20#include "llvm/Target/TargetRegisterInfo.h" 21#include "llvm/CodeGen/FastISel.h" 22#include "llvm/CodeGen/SelectionDAG.h" 23#include "llvm/CodeGen/CallingConvLower.h" 24#include <vector> 25 26namespace llvm { 27 class ARMConstantPoolValue; 28 29 namespace ARMISD { 30 // ARM Specific DAG Nodes 31 enum NodeType { 32 // Start the numbering where the builtin ops and target ops leave off. 33 FIRST_NUMBER = ISD::BUILTIN_OP_END, 34 35 Wrapper, // Wrapper - A wrapper node for TargetConstantPool, 36 // TargetExternalSymbol, and TargetGlobalAddress. 37 WrapperJT, // WrapperJT - A wrapper node for TargetJumpTable 38 39 CALL, // Function call. 40 CALL_PRED, // Function call that's predicable. 41 CALL_NOLINK, // Function call with branch not branch-and-link. 42 tCALL, // Thumb function call. 43 BRCOND, // Conditional branch. 44 BR_JT, // Jumptable branch. 45 BR2_JT, // Jumptable branch (2 level - jumptable entry is a jump). 46 RET_FLAG, // Return with a flag operand. 47 48 PIC_ADD, // Add with a PC operand and a PIC label. 49 50 AND, // ARM "and" instruction that sets the 's' flag in CPSR. 51 52 CMP, // ARM compare instructions. 53 CMPZ, // ARM compare that sets only Z flag. 54 CMPFP, // ARM VFP compare instruction, sets FPSCR. 55 CMPFPw0, // ARM VFP compare against zero instruction, sets FPSCR. 56 FMSTAT, // ARM fmstat instruction. 57 CMOV, // ARM conditional move instructions. 58 CNEG, // ARM conditional negate instructions. 59 60 BCC_i64, 61 62 RBIT, // ARM bitreverse instruction 63 64 FTOSI, // FP to sint within a FP register. 65 FTOUI, // FP to uint within a FP register. 66 SITOF, // sint to FP within a FP register. 67 UITOF, // uint to FP within a FP register. 68 69 SRL_FLAG, // V,Flag = srl_flag X -> srl X, 1 + save carry out. 70 SRA_FLAG, // V,Flag = sra_flag X -> sra X, 1 + save carry out. 71 RRX, // V = RRX X, Flag -> srl X, 1 + shift in carry flag. 72 73 VMOVRRD, // double to two gprs. 74 VMOVDRR, // Two gprs to double. 75 76 EH_SJLJ_SETJMP, // SjLj exception handling setjmp. 77 EH_SJLJ_LONGJMP, // SjLj exception handling longjmp. 78 79 TC_RETURN, // Tail call return pseudo. 80 81 THREAD_POINTER, 82 83 DYN_ALLOC, // Dynamic allocation on the stack. 84 85 MEMBARRIER, // Memory barrier 86 SYNCBARRIER, // Memory sync barrier 87 88 VCEQ, // Vector compare equal. 89 VCGE, // Vector compare greater than or equal. 90 VCGEU, // Vector compare unsigned greater than or equal. 91 VCGT, // Vector compare greater than. 92 VCGTU, // Vector compare unsigned greater than. 93 VTST, // Vector test bits. 94 95 // Vector shift by immediate: 96 VSHL, // ...left 97 VSHRs, // ...right (signed) 98 VSHRu, // ...right (unsigned) 99 VSHLLs, // ...left long (signed) 100 VSHLLu, // ...left long (unsigned) 101 VSHLLi, // ...left long (with maximum shift count) 102 VSHRN, // ...right narrow 103 104 // Vector rounding shift by immediate: 105 VRSHRs, // ...right (signed) 106 VRSHRu, // ...right (unsigned) 107 VRSHRN, // ...right narrow 108 109 // Vector saturating shift by immediate: 110 VQSHLs, // ...left (signed) 111 VQSHLu, // ...left (unsigned) 112 VQSHLsu, // ...left (signed to unsigned) 113 VQSHRNs, // ...right narrow (signed) 114 VQSHRNu, // ...right narrow (unsigned) 115 VQSHRNsu, // ...right narrow (signed to unsigned) 116 117 // Vector saturating rounding shift by immediate: 118 VQRSHRNs, // ...right narrow (signed) 119 VQRSHRNu, // ...right narrow (unsigned) 120 VQRSHRNsu, // ...right narrow (signed to unsigned) 121 122 // Vector shift and insert: 123 VSLI, // ...left 124 VSRI, // ...right 125 126 // Vector get lane (VMOV scalar to ARM core register) 127 // (These are used for 8- and 16-bit element types only.) 128 VGETLANEu, // zero-extend vector extract element 129 VGETLANEs, // sign-extend vector extract element 130 131 // Vector move immediate and move negated immediate: 132 VMOVIMM, 133 VMVNIMM, 134 135 // Vector duplicate: 136 VDUP, 137 VDUPLANE, 138 139 // Vector shuffles: 140 VEXT, // extract 141 VREV64, // reverse elements within 64-bit doublewords 142 VREV32, // reverse elements within 32-bit words 143 VREV16, // reverse elements within 16-bit halfwords 144 VZIP, // zip (interleave) 145 VUZP, // unzip (deinterleave) 146 VTRN, // transpose 147 148 // Operands of the standard BUILD_VECTOR node are not legalized, which 149 // is fine if BUILD_VECTORs are always lowered to shuffles or other 150 // operations, but for ARM some BUILD_VECTORs are legal as-is and their 151 // operands need to be legalized. Define an ARM-specific version of 152 // BUILD_VECTOR for this purpose. 153 BUILD_VECTOR, 154 155 // Floating-point max and min: 156 FMAX, 157 FMIN, 158 159 // Bit-field insert 160 BFI 161 }; 162 } 163 164 /// Define some predicates that are used for node matching. 165 namespace ARM { 166 /// getVFPf32Imm / getVFPf64Imm - If the given fp immediate can be 167 /// materialized with a VMOV.f32 / VMOV.f64 (i.e. fconsts / fconstd) 168 /// instruction, returns its 8-bit integer representation. Otherwise, 169 /// returns -1. 170 int getVFPf32Imm(const APFloat &FPImm); 171 int getVFPf64Imm(const APFloat &FPImm); 172 bool isBitFieldInvertedMask(unsigned v); 173 } 174 175 //===--------------------------------------------------------------------===// 176 // ARMTargetLowering - ARM Implementation of the TargetLowering interface 177 178 class ARMTargetLowering : public TargetLowering { 179 public: 180 explicit ARMTargetLowering(TargetMachine &TM); 181 182 virtual unsigned getJumpTableEncoding(void) const; 183 184 virtual SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const; 185 186 /// ReplaceNodeResults - Replace the results of node with an illegal result 187 /// type with new values built out of custom code. 188 /// 189 virtual void ReplaceNodeResults(SDNode *N, SmallVectorImpl<SDValue>&Results, 190 SelectionDAG &DAG) const; 191 192 virtual SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const; 193 194 virtual const char *getTargetNodeName(unsigned Opcode) const; 195 196 virtual MachineBasicBlock * 197 EmitInstrWithCustomInserter(MachineInstr *MI, 198 MachineBasicBlock *MBB) const; 199 200 /// allowsUnalignedMemoryAccesses - Returns true if the target allows 201 /// unaligned memory accesses. of the specified type. 202 /// FIXME: Add getOptimalMemOpType to implement memcpy with NEON? 203 virtual bool allowsUnalignedMemoryAccesses(EVT VT) const; 204 205 /// isLegalAddressingMode - Return true if the addressing mode represented 206 /// by AM is legal for this target, for a load/store of the specified type. 207 virtual bool isLegalAddressingMode(const AddrMode &AM, const Type *Ty)const; 208 bool isLegalT2ScaledAddressingMode(const AddrMode &AM, EVT VT) const; 209 210 /// isLegalICmpImmediate - Return true if the specified immediate is legal 211 /// icmp immediate, that is the target has icmp instructions which can 212 /// compare a register against the immediate without having to materialize 213 /// the immediate into a register. 214 virtual bool isLegalICmpImmediate(int64_t Imm) const; 215 216 /// getPreIndexedAddressParts - returns true by value, base pointer and 217 /// offset pointer and addressing mode by reference if the node's address 218 /// can be legally represented as pre-indexed load / store address. 219 virtual bool getPreIndexedAddressParts(SDNode *N, SDValue &Base, 220 SDValue &Offset, 221 ISD::MemIndexedMode &AM, 222 SelectionDAG &DAG) const; 223 224 /// getPostIndexedAddressParts - returns true by value, base pointer and 225 /// offset pointer and addressing mode by reference if this node can be 226 /// combined with a load / store to form a post-indexed load / store. 227 virtual bool getPostIndexedAddressParts(SDNode *N, SDNode *Op, 228 SDValue &Base, SDValue &Offset, 229 ISD::MemIndexedMode &AM, 230 SelectionDAG &DAG) const; 231 232 virtual void computeMaskedBitsForTargetNode(const SDValue Op, 233 const APInt &Mask, 234 APInt &KnownZero, 235 APInt &KnownOne, 236 const SelectionDAG &DAG, 237 unsigned Depth) const; 238 239 240 ConstraintType getConstraintType(const std::string &Constraint) const; 241 std::pair<unsigned, const TargetRegisterClass*> 242 getRegForInlineAsmConstraint(const std::string &Constraint, 243 EVT VT) const; 244 std::vector<unsigned> 245 getRegClassForInlineAsmConstraint(const std::string &Constraint, 246 EVT VT) const; 247 248 /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops 249 /// vector. If it is invalid, don't add anything to Ops. If hasMemory is 250 /// true it means one of the asm constraint of the inline asm instruction 251 /// being processed is 'm'. 252 virtual void LowerAsmOperandForConstraint(SDValue Op, 253 char ConstraintLetter, 254 std::vector<SDValue> &Ops, 255 SelectionDAG &DAG) const; 256 257 const ARMSubtarget* getSubtarget() const { 258 return Subtarget; 259 } 260 261 /// getRegClassFor - Return the register class that should be used for the 262 /// specified value type. 263 virtual TargetRegisterClass *getRegClassFor(EVT VT) const; 264 265 /// getFunctionAlignment - Return the Log2 alignment of this function. 266 virtual unsigned getFunctionAlignment(const Function *F) const; 267 268 /// getMaximalGlobalOffset - Returns the maximal possible offset which can 269 /// be used for loads / stores from the global. 270 virtual unsigned getMaximalGlobalOffset() const; 271 272 /// createFastISel - This method returns a target specific FastISel object, 273 /// or null if the target does not support "fast" ISel. 274 virtual FastISel *createFastISel(FunctionLoweringInfo &funcInfo) const; 275 276 Sched::Preference getSchedulingPreference(SDNode *N) const; 277 278 unsigned getRegPressureLimit(const TargetRegisterClass *RC, 279 MachineFunction &MF) const; 280 281 bool isShuffleMaskLegal(const SmallVectorImpl<int> &M, EVT VT) const; 282 bool isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const; 283 284 /// isFPImmLegal - Returns true if the target can instruction select the 285 /// specified FP immediate natively. If false, the legalizer will 286 /// materialize the FP immediate as a load from a constant pool. 287 virtual bool isFPImmLegal(const APFloat &Imm, EVT VT) const; 288 289 protected: 290 std::pair<const TargetRegisterClass*, uint8_t> 291 findRepresentativeClass(EVT VT) const; 292 293 private: 294 /// Subtarget - Keep a pointer to the ARMSubtarget around so that we can 295 /// make the right decision when generating code for different targets. 296 const ARMSubtarget *Subtarget; 297 298 const TargetRegisterInfo *RegInfo; 299 300 /// ARMPCLabelIndex - Keep track of the number of ARM PC labels created. 301 /// 302 unsigned ARMPCLabelIndex; 303 304 void addTypeForNEON(EVT VT, EVT PromotedLdStVT, EVT PromotedBitwiseVT); 305 void addDRTypeForNEON(EVT VT); 306 void addQRTypeForNEON(EVT VT); 307 308 typedef SmallVector<std::pair<unsigned, SDValue>, 8> RegsToPassVector; 309 void PassF64ArgInRegs(DebugLoc dl, SelectionDAG &DAG, 310 SDValue Chain, SDValue &Arg, 311 RegsToPassVector &RegsToPass, 312 CCValAssign &VA, CCValAssign &NextVA, 313 SDValue &StackPtr, 314 SmallVector<SDValue, 8> &MemOpChains, 315 ISD::ArgFlagsTy Flags) const; 316 SDValue GetF64FormalArgument(CCValAssign &VA, CCValAssign &NextVA, 317 SDValue &Root, SelectionDAG &DAG, 318 DebugLoc dl) const; 319 320 CCAssignFn *CCAssignFnForNode(CallingConv::ID CC, bool Return, 321 bool isVarArg) const; 322 SDValue LowerMemOpCallTo(SDValue Chain, SDValue StackPtr, SDValue Arg, 323 DebugLoc dl, SelectionDAG &DAG, 324 const CCValAssign &VA, 325 ISD::ArgFlagsTy Flags) const; 326 SDValue LowerEH_SJLJ_SETJMP(SDValue Op, SelectionDAG &DAG) const; 327 SDValue LowerEH_SJLJ_LONGJMP(SDValue Op, SelectionDAG &DAG) const; 328 SDValue LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG, 329 const ARMSubtarget *Subtarget) const; 330 SDValue LowerBlockAddress(SDValue Op, SelectionDAG &DAG) const; 331 SDValue LowerGlobalAddressDarwin(SDValue Op, SelectionDAG &DAG) const; 332 SDValue LowerGlobalAddressELF(SDValue Op, SelectionDAG &DAG) const; 333 SDValue LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const; 334 SDValue LowerToTLSGeneralDynamicModel(GlobalAddressSDNode *GA, 335 SelectionDAG &DAG) const; 336 SDValue LowerToTLSExecModels(GlobalAddressSDNode *GA, 337 SelectionDAG &DAG) const; 338 SDValue LowerGLOBAL_OFFSET_TABLE(SDValue Op, SelectionDAG &DAG) const; 339 SDValue LowerBR_JT(SDValue Op, SelectionDAG &DAG) const; 340 SDValue LowerSELECT(SDValue Op, SelectionDAG &DAG) const; 341 SDValue LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const; 342 SDValue LowerBR_CC(SDValue Op, SelectionDAG &DAG) const; 343 SDValue LowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG) const; 344 SDValue LowerRETURNADDR(SDValue Op, SelectionDAG &DAG) const; 345 SDValue LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const; 346 SDValue LowerShiftRightParts(SDValue Op, SelectionDAG &DAG) const; 347 SDValue LowerShiftLeftParts(SDValue Op, SelectionDAG &DAG) const; 348 SDValue LowerFLT_ROUNDS_(SDValue Op, SelectionDAG &DAG) const; 349 350 SDValue LowerCallResult(SDValue Chain, SDValue InFlag, 351 CallingConv::ID CallConv, bool isVarArg, 352 const SmallVectorImpl<ISD::InputArg> &Ins, 353 DebugLoc dl, SelectionDAG &DAG, 354 SmallVectorImpl<SDValue> &InVals) const; 355 356 virtual SDValue 357 LowerFormalArguments(SDValue Chain, 358 CallingConv::ID CallConv, bool isVarArg, 359 const SmallVectorImpl<ISD::InputArg> &Ins, 360 DebugLoc dl, SelectionDAG &DAG, 361 SmallVectorImpl<SDValue> &InVals) const; 362 363 virtual SDValue 364 LowerCall(SDValue Chain, SDValue Callee, 365 CallingConv::ID CallConv, bool isVarArg, 366 bool &isTailCall, 367 const SmallVectorImpl<ISD::OutputArg> &Outs, 368 const SmallVectorImpl<SDValue> &OutVals, 369 const SmallVectorImpl<ISD::InputArg> &Ins, 370 DebugLoc dl, SelectionDAG &DAG, 371 SmallVectorImpl<SDValue> &InVals) const; 372 373 /// IsEligibleForTailCallOptimization - Check whether the call is eligible 374 /// for tail call optimization. Targets which want to do tail call 375 /// optimization should implement this function. 376 bool IsEligibleForTailCallOptimization(SDValue Callee, 377 CallingConv::ID CalleeCC, 378 bool isVarArg, 379 bool isCalleeStructRet, 380 bool isCallerStructRet, 381 const SmallVectorImpl<ISD::OutputArg> &Outs, 382 const SmallVectorImpl<SDValue> &OutVals, 383 const SmallVectorImpl<ISD::InputArg> &Ins, 384 SelectionDAG& DAG) const; 385 virtual SDValue 386 LowerReturn(SDValue Chain, 387 CallingConv::ID CallConv, bool isVarArg, 388 const SmallVectorImpl<ISD::OutputArg> &Outs, 389 const SmallVectorImpl<SDValue> &OutVals, 390 DebugLoc dl, SelectionDAG &DAG) const; 391 392 SDValue getARMCmp(SDValue LHS, SDValue RHS, ISD::CondCode CC, 393 SDValue &ARMcc, SelectionDAG &DAG, DebugLoc dl) const; 394 SDValue getVFPCmp(SDValue LHS, SDValue RHS, 395 SelectionDAG &DAG, DebugLoc dl) const; 396 397 SDValue OptimizeVFPBrcond(SDValue Op, SelectionDAG &DAG) const; 398 399 MachineBasicBlock *EmitAtomicCmpSwap(MachineInstr *MI, 400 MachineBasicBlock *BB, 401 unsigned Size) const; 402 MachineBasicBlock *EmitAtomicBinary(MachineInstr *MI, 403 MachineBasicBlock *BB, 404 unsigned Size, 405 unsigned BinOpcode) const; 406 407 }; 408 409 namespace ARM { 410 FastISel *createFastISel(FunctionLoweringInfo &funcInfo); 411 } 412} 413 414#endif // ARMISELLOWERING_H 415