ARMISelLowering.h revision ff9b373e8f5006c629af81e2619778b4c4f5249e 
1//===-- ARMISelLowering.h - ARM DAG Lowering Interface ----------*- C++ -*-===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file defines the interfaces that ARM uses to lower LLVM code into a
11// selection DAG.
12//
13//===----------------------------------------------------------------------===//
14
15#ifndef ARMISELLOWERING_H
16#define ARMISELLOWERING_H
17
18#include "ARMSubtarget.h"
19#include "llvm/Target/TargetLowering.h"
20#include "llvm/CodeGen/SelectionDAG.h"
21#include <vector>
22
23namespace llvm {
24  class ARMConstantPoolValue;
25
26  namespace ARMISD {
27    // ARM Specific DAG Nodes
28    enum NodeType {
29      // Start the numbering where the builting ops and target ops leave off.
30      FIRST_NUMBER = ISD::BUILTIN_OP_END+ARM::INSTRUCTION_LIST_END,
31
32      Wrapper,      // Wrapper - A wrapper node for TargetConstantPool,
33                    // TargetExternalSymbol, and TargetGlobalAddress.
34      WrapperJT,    // WrapperJT - A wrapper node for TargetJumpTable
35
36      CALL,         // Function call.
37      CALL_PRED,    // Function call that's predicable.
38      CALL_NOLINK,  // Function call with branch not branch-and-link.
39      tCALL,        // Thumb function call.
40      BRCOND,       // Conditional branch.
41      BR_JT,        // Jumptable branch.
42      RET_FLAG,     // Return with a flag operand.
43
44      PIC_ADD,      // Add with a PC operand and a PIC label.
45
46      CMP,          // ARM compare instructions.
47      CMPNZ,        // ARM compare that uses only N or Z flags.
48      CMPFP,        // ARM VFP compare instruction, sets FPSCR.
49      CMPFPw0,      // ARM VFP compare against zero instruction, sets FPSCR.
50      FMSTAT,       // ARM fmstat instruction.
51      CMOV,         // ARM conditional move instructions.
52      CNEG,         // ARM conditional negate instructions.
53
54      FTOSI,        // FP to sint within a FP register.
55      FTOUI,        // FP to uint within a FP register.
56      SITOF,        // sint to FP within a FP register.
57      UITOF,        // uint to FP within a FP register.
58
59      SRL_FLAG,     // V,Flag = srl_flag X -> srl X, 1 + save carry out.
60      SRA_FLAG,     // V,Flag = sra_flag X -> sra X, 1 + save carry out.
61      RRX,          // V = RRX X, Flag     -> srl X, 1 + shift in carry flag.
62
63      FMRRD,        // double to two gprs.
64      FMDRR,         // Two gprs to double.
65
66      THREAD_POINTER
67    };
68  }
69
70  //===----------------------------------------------------------------------===//
71  //  ARMTargetLowering - ARM Implementation of the TargetLowering interface
72
73  class ARMTargetLowering : public TargetLowering {
74    int VarArgsFrameIndex;            // FrameIndex for start of varargs area.
75  public:
76    explicit ARMTargetLowering(TargetMachine &TM);
77
78    virtual SDOperand LowerOperation(SDOperand Op, SelectionDAG &DAG);
79    virtual SDNode *ExpandOperationResult(SDNode *N, SelectionDAG &DAG);
80
81    SDOperand PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const;
82
83    virtual const char *getTargetNodeName(unsigned Opcode) const;
84
85    virtual MachineBasicBlock *EmitInstrWithCustomInserter(MachineInstr *MI,
86                                                       MachineBasicBlock *MBB);
87
88    /// isLegalAddressingMode - Return true if the addressing mode represented
89    /// by AM is legal for this target, for a load/store of the specified type.
90    virtual bool isLegalAddressingMode(const AddrMode &AM, const Type *Ty)const;
91
92    /// getPreIndexedAddressParts - returns true by value, base pointer and
93    /// offset pointer and addressing mode by reference if the node's address
94    /// can be legally represented as pre-indexed load / store address.
95    virtual bool getPreIndexedAddressParts(SDNode *N, SDOperand &Base,
96                                           SDOperand &Offset,
97                                           ISD::MemIndexedMode &AM,
98                                           SelectionDAG &DAG);
99
100    /// getPostIndexedAddressParts - returns true by value, base pointer and
101    /// offset pointer and addressing mode by reference if this node can be
102    /// combined with a load / store to form a post-indexed load / store.
103    virtual bool getPostIndexedAddressParts(SDNode *N, SDNode *Op,
104                                            SDOperand &Base, SDOperand &Offset,
105                                            ISD::MemIndexedMode &AM,
106                                            SelectionDAG &DAG);
107
108    virtual void computeMaskedBitsForTargetNode(const SDOperand Op,
109                                                uint64_t Mask,
110                                                uint64_t &KnownZero,
111                                                uint64_t &KnownOne,
112                                                const SelectionDAG &DAG,
113                                                unsigned Depth) const;
114    ConstraintType getConstraintType(const std::string &Constraint) const;
115    std::pair<unsigned, const TargetRegisterClass*>
116      getRegForInlineAsmConstraint(const std::string &Constraint,
117                                   MVT::ValueType VT) const;
118    std::vector<unsigned>
119    getRegClassForInlineAsmConstraint(const std::string &Constraint,
120                                      MVT::ValueType VT) const;
121
122    virtual const TargetSubtarget* getSubtarget() {
123      return static_cast<const TargetSubtarget*>(Subtarget);
124    }
125
126  private:
127    /// Subtarget - Keep a pointer to the ARMSubtarget around so that we can
128    /// make the right decision when generating code for different targets.
129    const ARMSubtarget *Subtarget;
130
131    /// ARMPCLabelIndex - Keep track the number of ARM PC labels created.
132    ///
133    unsigned ARMPCLabelIndex;
134
135    SDOperand LowerCALL(SDOperand Op, SelectionDAG &DAG);
136    SDOperand LowerGlobalAddressDarwin(SDOperand Op, SelectionDAG &DAG);
137    SDOperand LowerGlobalAddressELF(SDOperand Op, SelectionDAG &DAG);
138    SDOperand LowerGlobalTLSAddress(SDOperand Op, SelectionDAG &DAG);
139    SDOperand LowerToTLSGeneralDynamicModel(GlobalAddressSDNode *GA,
140                                            SelectionDAG &DAG);
141    SDOperand LowerToTLSExecModels(GlobalAddressSDNode *GA,
142                                   SelectionDAG &DAG);
143    SDOperand LowerGLOBAL_OFFSET_TABLE(SDOperand Op, SelectionDAG &DAG);
144    SDOperand LowerFORMAL_ARGUMENTS(SDOperand Op, SelectionDAG &DAG);
145    SDOperand LowerBR_JT(SDOperand Op, SelectionDAG &DAG);
146    SDOperand LowerMEMCPYInline(SDOperand Chain, SDOperand Dest,
147                                SDOperand Source, unsigned Size,
148                                unsigned Align, SelectionDAG &DAG);
149
150
151  };
152}
153
154#endif  // ARMISELLOWERING_H
155