ARMInstrInfo.cpp revision ab588a132ffea11835b45631aec173569c97f6da 
1//===- ARMInstrInfo.cpp - ARM Instruction Information -----------*- C++ -*-===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file contains the ARM implementation of the TargetInstrInfo class.
11//
12//===----------------------------------------------------------------------===//
13
14#include "ARMInstrInfo.h"
15#include "ARM.h"
16#include "ARMAddressingModes.h"
17#include "ARMGenInstrInfo.inc"
18#include "ARMMachineFunctionInfo.h"
19#include "llvm/ADT/STLExtras.h"
20#include "llvm/CodeGen/LiveVariables.h"
21#include "llvm/CodeGen/MachineFrameInfo.h"
22#include "llvm/CodeGen/MachineInstrBuilder.h"
23#include "llvm/CodeGen/MachineJumpTableInfo.h"
24#include "llvm/Target/TargetAsmInfo.h"
25#include "llvm/Support/CommandLine.h"
26using namespace llvm;
27
28static cl::opt<bool> EnableARM3Addr("enable-arm-3-addr-conv", cl::Hidden,
29                                  cl::desc("Enable ARM 2-addr to 3-addr conv"));
30
31static inline
32const MachineInstrBuilder &AddDefaultPred(const MachineInstrBuilder &MIB) {
33  return MIB.addImm((int64_t)ARMCC::AL).addReg(0);
34}
35
36static inline
37const MachineInstrBuilder &AddDefaultCC(const MachineInstrBuilder &MIB) {
38  return MIB.addReg(0);
39}
40
41ARMInstrInfo::ARMInstrInfo(const ARMSubtarget &STI)
42  : TargetInstrInfoImpl(ARMInsts, array_lengthof(ARMInsts)),
43    RI(*this, STI) {
44}
45
46
47/// Return true if the instruction is a register to register move and
48/// leave the source and dest operands in the passed parameters.
49///
50bool ARMInstrInfo::isMoveInstr(const MachineInstr &MI,
51                               unsigned &SrcReg, unsigned &DstReg,
52                               unsigned& SrcSubIdx, unsigned& DstSubIdx) const {
53  SrcSubIdx = DstSubIdx = 0; // No sub-registers.
54
55  unsigned oc = MI.getOpcode();
56  switch (oc) {
57  default:
58    return false;
59  case ARM::FCPYS:
60  case ARM::FCPYD:
61    SrcReg = MI.getOperand(1).getReg();
62    DstReg = MI.getOperand(0).getReg();
63    return true;
64  case ARM::MOVr:
65  case ARM::tMOVr:
66    assert(MI.getDesc().getNumOperands() >= 2 &&
67           MI.getOperand(0).isReg() &&
68           MI.getOperand(1).isReg() &&
69           "Invalid ARM MOV instruction");
70    SrcReg = MI.getOperand(1).getReg();
71    DstReg = MI.getOperand(0).getReg();
72    return true;
73  }
74}
75
76unsigned ARMInstrInfo::isLoadFromStackSlot(const MachineInstr *MI,
77                                           int &FrameIndex) const {
78  switch (MI->getOpcode()) {
79  default: break;
80  case ARM::LDR:
81    if (MI->getOperand(1).isFI() &&
82        MI->getOperand(2).isReg() &&
83        MI->getOperand(3).isImm() &&
84        MI->getOperand(2).getReg() == 0 &&
85        MI->getOperand(3).getImm() == 0) {
86      FrameIndex = MI->getOperand(1).getIndex();
87      return MI->getOperand(0).getReg();
88    }
89    break;
90  case ARM::FLDD:
91  case ARM::FLDS:
92    if (MI->getOperand(1).isFI() &&
93        MI->getOperand(2).isImm() &&
94        MI->getOperand(2).getImm() == 0) {
95      FrameIndex = MI->getOperand(1).getIndex();
96      return MI->getOperand(0).getReg();
97    }
98    break;
99  case ARM::tRestore:
100    if (MI->getOperand(1).isFI() &&
101        MI->getOperand(2).isImm() &&
102        MI->getOperand(2).getImm() == 0) {
103      FrameIndex = MI->getOperand(1).getIndex();
104      return MI->getOperand(0).getReg();
105    }
106    break;
107  }
108  return 0;
109}
110
111unsigned ARMInstrInfo::isStoreToStackSlot(const MachineInstr *MI,
112                                          int &FrameIndex) const {
113  switch (MI->getOpcode()) {
114  default: break;
115  case ARM::STR:
116    if (MI->getOperand(1).isFI() &&
117        MI->getOperand(2).isReg() &&
118        MI->getOperand(3).isImm() &&
119        MI->getOperand(2).getReg() == 0 &&
120        MI->getOperand(3).getImm() == 0) {
121      FrameIndex = MI->getOperand(1).getIndex();
122      return MI->getOperand(0).getReg();
123    }
124    break;
125  case ARM::FSTD:
126  case ARM::FSTS:
127    if (MI->getOperand(1).isFI() &&
128        MI->getOperand(2).isImm() &&
129        MI->getOperand(2).getImm() == 0) {
130      FrameIndex = MI->getOperand(1).getIndex();
131      return MI->getOperand(0).getReg();
132    }
133    break;
134  case ARM::tSpill:
135    if (MI->getOperand(1).isFI() &&
136        MI->getOperand(2).isImm() &&
137        MI->getOperand(2).getImm() == 0) {
138      FrameIndex = MI->getOperand(1).getIndex();
139      return MI->getOperand(0).getReg();
140    }
141    break;
142  }
143  return 0;
144}
145
146void ARMInstrInfo::reMaterialize(MachineBasicBlock &MBB,
147                                 MachineBasicBlock::iterator I,
148                                 unsigned DestReg,
149                                 const MachineInstr *Orig) const {
150  DebugLoc dl = Orig->getDebugLoc();
151  if (Orig->getOpcode() == ARM::MOVi2pieces) {
152    RI.emitLoadConstPool(MBB, I, DestReg, Orig->getOperand(1).getImm(),
153                         Orig->getOperand(2).getImm(),
154                         Orig->getOperand(3).getReg(), this, false, dl);
155    return;
156  }
157
158  MachineInstr *MI = MBB.getParent()->CloneMachineInstr(Orig);
159  MI->getOperand(0).setReg(DestReg);
160  MBB.insert(I, MI);
161}
162
163static unsigned getUnindexedOpcode(unsigned Opc) {
164  switch (Opc) {
165  default: break;
166  case ARM::LDR_PRE:
167  case ARM::LDR_POST:
168    return ARM::LDR;
169  case ARM::LDRH_PRE:
170  case ARM::LDRH_POST:
171    return ARM::LDRH;
172  case ARM::LDRB_PRE:
173  case ARM::LDRB_POST:
174    return ARM::LDRB;
175  case ARM::LDRSH_PRE:
176  case ARM::LDRSH_POST:
177    return ARM::LDRSH;
178  case ARM::LDRSB_PRE:
179  case ARM::LDRSB_POST:
180    return ARM::LDRSB;
181  case ARM::STR_PRE:
182  case ARM::STR_POST:
183    return ARM::STR;
184  case ARM::STRH_PRE:
185  case ARM::STRH_POST:
186    return ARM::STRH;
187  case ARM::STRB_PRE:
188  case ARM::STRB_POST:
189    return ARM::STRB;
190  }
191  return 0;
192}
193
194MachineInstr *
195ARMInstrInfo::convertToThreeAddress(MachineFunction::iterator &MFI,
196                                    MachineBasicBlock::iterator &MBBI,
197                                    LiveVariables *LV) const {
198  if (!EnableARM3Addr)
199    return NULL;
200
201  MachineInstr *MI = MBBI;
202  MachineFunction &MF = *MI->getParent()->getParent();
203  unsigned TSFlags = MI->getDesc().TSFlags;
204  bool isPre = false;
205  switch ((TSFlags & ARMII::IndexModeMask) >> ARMII::IndexModeShift) {
206  default: return NULL;
207  case ARMII::IndexModePre:
208    isPre = true;
209    break;
210  case ARMII::IndexModePost:
211    break;
212  }
213
214  // Try splitting an indexed load/store to an un-indexed one plus an add/sub
215  // operation.
216  unsigned MemOpc = getUnindexedOpcode(MI->getOpcode());
217  if (MemOpc == 0)
218    return NULL;
219
220  MachineInstr *UpdateMI = NULL;
221  MachineInstr *MemMI = NULL;
222  unsigned AddrMode = (TSFlags & ARMII::AddrModeMask);
223  const TargetInstrDesc &TID = MI->getDesc();
224  unsigned NumOps = TID.getNumOperands();
225  bool isLoad = !TID.mayStore();
226  const MachineOperand &WB = isLoad ? MI->getOperand(1) : MI->getOperand(0);
227  const MachineOperand &Base = MI->getOperand(2);
228  const MachineOperand &Offset = MI->getOperand(NumOps-3);
229  unsigned WBReg = WB.getReg();
230  unsigned BaseReg = Base.getReg();
231  unsigned OffReg = Offset.getReg();
232  unsigned OffImm = MI->getOperand(NumOps-2).getImm();
233  ARMCC::CondCodes Pred = (ARMCC::CondCodes)MI->getOperand(NumOps-1).getImm();
234  switch (AddrMode) {
235  default:
236    assert(false && "Unknown indexed op!");
237    return NULL;
238  case ARMII::AddrMode2: {
239    bool isSub = ARM_AM::getAM2Op(OffImm) == ARM_AM::sub;
240    unsigned Amt = ARM_AM::getAM2Offset(OffImm);
241    if (OffReg == 0) {
242      int SOImmVal = ARM_AM::getSOImmVal(Amt);
243      if (SOImmVal == -1)
244        // Can't encode it in a so_imm operand. This transformation will
245        // add more than 1 instruction. Abandon!
246        return NULL;
247      UpdateMI = BuildMI(MF, MI->getDebugLoc(),
248                         get(isSub ? ARM::SUBri : ARM::ADDri), WBReg)
249        .addReg(BaseReg).addImm(SOImmVal)
250        .addImm(Pred).addReg(0).addReg(0);
251    } else if (Amt != 0) {
252      ARM_AM::ShiftOpc ShOpc = ARM_AM::getAM2ShiftOpc(OffImm);
253      unsigned SOOpc = ARM_AM::getSORegOpc(ShOpc, Amt);
254      UpdateMI = BuildMI(MF, MI->getDebugLoc(),
255                         get(isSub ? ARM::SUBrs : ARM::ADDrs), WBReg)
256        .addReg(BaseReg).addReg(OffReg).addReg(0).addImm(SOOpc)
257        .addImm(Pred).addReg(0).addReg(0);
258    } else
259      UpdateMI = BuildMI(MF, MI->getDebugLoc(),
260                         get(isSub ? ARM::SUBrr : ARM::ADDrr), WBReg)
261        .addReg(BaseReg).addReg(OffReg)
262        .addImm(Pred).addReg(0).addReg(0);
263    break;
264  }
265  case ARMII::AddrMode3 : {
266    bool isSub = ARM_AM::getAM3Op(OffImm) == ARM_AM::sub;
267    unsigned Amt = ARM_AM::getAM3Offset(OffImm);
268    if (OffReg == 0)
269      // Immediate is 8-bits. It's guaranteed to fit in a so_imm operand.
270      UpdateMI = BuildMI(MF, MI->getDebugLoc(),
271                         get(isSub ? ARM::SUBri : ARM::ADDri), WBReg)
272        .addReg(BaseReg).addImm(Amt)
273        .addImm(Pred).addReg(0).addReg(0);
274    else
275      UpdateMI = BuildMI(MF, MI->getDebugLoc(),
276                         get(isSub ? ARM::SUBrr : ARM::ADDrr), WBReg)
277        .addReg(BaseReg).addReg(OffReg)
278        .addImm(Pred).addReg(0).addReg(0);
279    break;
280  }
281  }
282
283  std::vector<MachineInstr*> NewMIs;
284  if (isPre) {
285    if (isLoad)
286      MemMI = BuildMI(MF, MI->getDebugLoc(),
287                      get(MemOpc), MI->getOperand(0).getReg())
288        .addReg(WBReg).addReg(0).addImm(0).addImm(Pred);
289    else
290      MemMI = BuildMI(MF, MI->getDebugLoc(),
291                      get(MemOpc)).addReg(MI->getOperand(1).getReg())
292        .addReg(WBReg).addReg(0).addImm(0).addImm(Pred);
293    NewMIs.push_back(MemMI);
294    NewMIs.push_back(UpdateMI);
295  } else {
296    if (isLoad)
297      MemMI = BuildMI(MF, MI->getDebugLoc(),
298                      get(MemOpc), MI->getOperand(0).getReg())
299        .addReg(BaseReg).addReg(0).addImm(0).addImm(Pred);
300    else
301      MemMI = BuildMI(MF, MI->getDebugLoc(),
302                      get(MemOpc)).addReg(MI->getOperand(1).getReg())
303        .addReg(BaseReg).addReg(0).addImm(0).addImm(Pred);
304    if (WB.isDead())
305      UpdateMI->getOperand(0).setIsDead();
306    NewMIs.push_back(UpdateMI);
307    NewMIs.push_back(MemMI);
308  }
309
310  // Transfer LiveVariables states, kill / dead info.
311  if (LV) {
312    for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
313      MachineOperand &MO = MI->getOperand(i);
314      if (MO.isReg() && MO.getReg() &&
315          TargetRegisterInfo::isVirtualRegister(MO.getReg())) {
316        unsigned Reg = MO.getReg();
317
318        LiveVariables::VarInfo &VI = LV->getVarInfo(Reg);
319        if (MO.isDef()) {
320          MachineInstr *NewMI = (Reg == WBReg) ? UpdateMI : MemMI;
321          if (MO.isDead())
322            LV->addVirtualRegisterDead(Reg, NewMI);
323        }
324        if (MO.isUse() && MO.isKill()) {
325          for (unsigned j = 0; j < 2; ++j) {
326            // Look at the two new MI's in reverse order.
327            MachineInstr *NewMI = NewMIs[j];
328            if (!NewMI->readsRegister(Reg))
329              continue;
330            LV->addVirtualRegisterKilled(Reg, NewMI);
331            if (VI.removeKill(MI))
332              VI.Kills.push_back(NewMI);
333            break;
334          }
335        }
336      }
337    }
338  }
339
340  MFI->insert(MBBI, NewMIs[1]);
341  MFI->insert(MBBI, NewMIs[0]);
342  return NewMIs[0];
343}
344
345// Branch analysis.
346bool ARMInstrInfo::AnalyzeBranch(MachineBasicBlock &MBB,MachineBasicBlock *&TBB,
347                                 MachineBasicBlock *&FBB,
348                                 SmallVectorImpl<MachineOperand> &Cond,
349                                 bool AllowModify) const {
350  // If the block has no terminators, it just falls into the block after it.
351  MachineBasicBlock::iterator I = MBB.end();
352  if (I == MBB.begin() || !isUnpredicatedTerminator(--I))
353    return false;
354
355  // Get the last instruction in the block.
356  MachineInstr *LastInst = I;
357
358  // If there is only one terminator instruction, process it.
359  unsigned LastOpc = LastInst->getOpcode();
360  if (I == MBB.begin() || !isUnpredicatedTerminator(--I)) {
361    if (LastOpc == ARM::B || LastOpc == ARM::tB) {
362      TBB = LastInst->getOperand(0).getMBB();
363      return false;
364    }
365    if (LastOpc == ARM::Bcc || LastOpc == ARM::tBcc) {
366      // Block ends with fall-through condbranch.
367      TBB = LastInst->getOperand(0).getMBB();
368      Cond.push_back(LastInst->getOperand(1));
369      Cond.push_back(LastInst->getOperand(2));
370      return false;
371    }
372    return true;  // Can't handle indirect branch.
373  }
374
375  // Get the instruction before it if it is a terminator.
376  MachineInstr *SecondLastInst = I;
377
378  // If there are three terminators, we don't know what sort of block this is.
379  if (SecondLastInst && I != MBB.begin() && isUnpredicatedTerminator(--I))
380    return true;
381
382  // If the block ends with ARM::B/ARM::tB and a ARM::Bcc/ARM::tBcc, handle it.
383  unsigned SecondLastOpc = SecondLastInst->getOpcode();
384  if ((SecondLastOpc == ARM::Bcc && LastOpc == ARM::B) ||
385      (SecondLastOpc == ARM::tBcc && LastOpc == ARM::tB)) {
386    TBB =  SecondLastInst->getOperand(0).getMBB();
387    Cond.push_back(SecondLastInst->getOperand(1));
388    Cond.push_back(SecondLastInst->getOperand(2));
389    FBB = LastInst->getOperand(0).getMBB();
390    return false;
391  }
392
393  // If the block ends with two unconditional branches, handle it.  The second
394  // one is not executed, so remove it.
395  if ((SecondLastOpc == ARM::B || SecondLastOpc==ARM::tB) &&
396      (LastOpc == ARM::B || LastOpc == ARM::tB)) {
397    TBB = SecondLastInst->getOperand(0).getMBB();
398    I = LastInst;
399    if (AllowModify)
400      I->eraseFromParent();
401    return false;
402  }
403
404  // ...likewise if it ends with a branch table followed by an unconditional
405  // branch. The branch folder can create these, and we must get rid of them for
406  // correctness of Thumb constant islands.
407  if ((SecondLastOpc == ARM::BR_JTr || SecondLastOpc==ARM::BR_JTm ||
408       SecondLastOpc == ARM::BR_JTadd || SecondLastOpc==ARM::tBR_JTr) &&
409      (LastOpc == ARM::B || LastOpc == ARM::tB)) {
410    I = LastInst;
411    if (AllowModify)
412      I->eraseFromParent();
413    return true;
414  }
415
416  // Otherwise, can't handle this.
417  return true;
418}
419
420
421unsigned ARMInstrInfo::RemoveBranch(MachineBasicBlock &MBB) const {
422  MachineFunction &MF = *MBB.getParent();
423  ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
424  int BOpc   = AFI->isThumbFunction() ? ARM::tB : ARM::B;
425  int BccOpc = AFI->isThumbFunction() ? ARM::tBcc : ARM::Bcc;
426
427  MachineBasicBlock::iterator I = MBB.end();
428  if (I == MBB.begin()) return 0;
429  --I;
430  if (I->getOpcode() != BOpc && I->getOpcode() != BccOpc)
431    return 0;
432
433  // Remove the branch.
434  I->eraseFromParent();
435
436  I = MBB.end();
437
438  if (I == MBB.begin()) return 1;
439  --I;
440  if (I->getOpcode() != BccOpc)
441    return 1;
442
443  // Remove the branch.
444  I->eraseFromParent();
445  return 2;
446}
447
448unsigned ARMInstrInfo::InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
449                                MachineBasicBlock *FBB,
450                            const SmallVectorImpl<MachineOperand> &Cond) const {
451  // FIXME this should probably have a DebugLoc argument
452  DebugLoc dl = DebugLoc::getUnknownLoc();
453  MachineFunction &MF = *MBB.getParent();
454  ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
455  int BOpc   = AFI->isThumbFunction() ? ARM::tB : ARM::B;
456  int BccOpc = AFI->isThumbFunction() ? ARM::tBcc : ARM::Bcc;
457
458  // Shouldn't be a fall through.
459  assert(TBB && "InsertBranch must not be told to insert a fallthrough");
460  assert((Cond.size() == 2 || Cond.size() == 0) &&
461         "ARM branch conditions have two components!");
462
463  if (FBB == 0) {
464    if (Cond.empty()) // Unconditional branch?
465      BuildMI(&MBB, dl, get(BOpc)).addMBB(TBB);
466    else
467      BuildMI(&MBB, dl, get(BccOpc)).addMBB(TBB)
468        .addImm(Cond[0].getImm()).addReg(Cond[1].getReg());
469    return 1;
470  }
471
472  // Two-way conditional branch.
473  BuildMI(&MBB, dl, get(BccOpc)).addMBB(TBB)
474    .addImm(Cond[0].getImm()).addReg(Cond[1].getReg());
475  BuildMI(&MBB, dl, get(BOpc)).addMBB(FBB);
476  return 2;
477}
478
479bool ARMInstrInfo::copyRegToReg(MachineBasicBlock &MBB,
480                                   MachineBasicBlock::iterator I,
481                                   unsigned DestReg, unsigned SrcReg,
482                                   const TargetRegisterClass *DestRC,
483                                   const TargetRegisterClass *SrcRC) const {
484  if (DestRC != SrcRC) {
485    // Not yet supported!
486    return false;
487  }
488
489  DebugLoc DL = DebugLoc::getUnknownLoc();
490  if (I != MBB.end()) DL = I->getDebugLoc();
491
492  if (DestRC == ARM::GPRRegisterClass) {
493    MachineFunction &MF = *MBB.getParent();
494    ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
495    if (AFI->isThumbFunction())
496      BuildMI(MBB, I, DL, get(ARM::tMOVr), DestReg).addReg(SrcReg);
497    else
498      AddDefaultCC(AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::MOVr), DestReg)
499                                  .addReg(SrcReg)));
500  } else if (DestRC == ARM::SPRRegisterClass)
501    AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::FCPYS), DestReg)
502                   .addReg(SrcReg));
503  else if (DestRC == ARM::DPRRegisterClass)
504    AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::FCPYD), DestReg)
505                   .addReg(SrcReg));
506  else
507    return false;
508
509  return true;
510}
511
512void ARMInstrInfo::
513storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
514                    unsigned SrcReg, bool isKill, int FI,
515                    const TargetRegisterClass *RC) const {
516  DebugLoc DL = DebugLoc::getUnknownLoc();
517  if (I != MBB.end()) DL = I->getDebugLoc();
518
519  if (RC == ARM::GPRRegisterClass) {
520    MachineFunction &MF = *MBB.getParent();
521    ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
522    if (AFI->isThumbFunction())
523      BuildMI(MBB, I, DL, get(ARM::tSpill))
524        .addReg(SrcReg, false, false, isKill)
525        .addFrameIndex(FI).addImm(0);
526    else
527      AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::STR))
528                     .addReg(SrcReg, false, false, isKill)
529                     .addFrameIndex(FI).addReg(0).addImm(0));
530  } else if (RC == ARM::DPRRegisterClass) {
531    AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::FSTD))
532                   .addReg(SrcReg, false, false, isKill)
533                   .addFrameIndex(FI).addImm(0));
534  } else {
535    assert(RC == ARM::SPRRegisterClass && "Unknown regclass!");
536    AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::FSTS))
537                   .addReg(SrcReg, false, false, isKill)
538                   .addFrameIndex(FI).addImm(0));
539  }
540}
541
542void ARMInstrInfo::storeRegToAddr(MachineFunction &MF, unsigned SrcReg,
543                                  bool isKill,
544                                  SmallVectorImpl<MachineOperand> &Addr,
545                                  const TargetRegisterClass *RC,
546                                  SmallVectorImpl<MachineInstr*> &NewMIs) const{
547  DebugLoc DL = DebugLoc::getUnknownLoc();
548  unsigned Opc = 0;
549  if (RC == ARM::GPRRegisterClass) {
550    ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
551    if (AFI->isThumbFunction()) {
552      Opc = Addr[0].isFI() ? ARM::tSpill : ARM::tSTR;
553      MachineInstrBuilder MIB =
554        BuildMI(MF, DL,  get(Opc)).addReg(SrcReg, false, false, isKill);
555      for (unsigned i = 0, e = Addr.size(); i != e; ++i)
556        MIB.addOperand(Addr[i]);
557      NewMIs.push_back(MIB);
558      return;
559    }
560    Opc = ARM::STR;
561  } else if (RC == ARM::DPRRegisterClass) {
562    Opc = ARM::FSTD;
563  } else {
564    assert(RC == ARM::SPRRegisterClass && "Unknown regclass!");
565    Opc = ARM::FSTS;
566  }
567
568  MachineInstrBuilder MIB =
569    BuildMI(MF, DL, get(Opc)).addReg(SrcReg, false, false, isKill);
570  for (unsigned i = 0, e = Addr.size(); i != e; ++i)
571    MIB.addOperand(Addr[i]);
572  AddDefaultPred(MIB);
573  NewMIs.push_back(MIB);
574  return;
575}
576
577void ARMInstrInfo::
578loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
579                     unsigned DestReg, int FI,
580                     const TargetRegisterClass *RC) const {
581  DebugLoc DL = DebugLoc::getUnknownLoc();
582  if (I != MBB.end()) DL = I->getDebugLoc();
583
584  if (RC == ARM::GPRRegisterClass) {
585    MachineFunction &MF = *MBB.getParent();
586    ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
587    if (AFI->isThumbFunction())
588      BuildMI(MBB, I, DL, get(ARM::tRestore), DestReg)
589        .addFrameIndex(FI).addImm(0);
590    else
591      AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::LDR), DestReg)
592                     .addFrameIndex(FI).addReg(0).addImm(0));
593  } else if (RC == ARM::DPRRegisterClass) {
594    AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::FLDD), DestReg)
595                   .addFrameIndex(FI).addImm(0));
596  } else {
597    assert(RC == ARM::SPRRegisterClass && "Unknown regclass!");
598    AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::FLDS), DestReg)
599                   .addFrameIndex(FI).addImm(0));
600  }
601}
602
603void ARMInstrInfo::loadRegFromAddr(MachineFunction &MF, unsigned DestReg,
604                                   SmallVectorImpl<MachineOperand> &Addr,
605                                   const TargetRegisterClass *RC,
606                                 SmallVectorImpl<MachineInstr*> &NewMIs) const {
607  DebugLoc DL = DebugLoc::getUnknownLoc();
608  unsigned Opc = 0;
609  if (RC == ARM::GPRRegisterClass) {
610    ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
611    if (AFI->isThumbFunction()) {
612      Opc = Addr[0].isFI() ? ARM::tRestore : ARM::tLDR;
613      MachineInstrBuilder MIB = BuildMI(MF, DL, get(Opc), DestReg);
614      for (unsigned i = 0, e = Addr.size(); i != e; ++i)
615        MIB.addOperand(Addr[i]);
616      NewMIs.push_back(MIB);
617      return;
618    }
619    Opc = ARM::LDR;
620  } else if (RC == ARM::DPRRegisterClass) {
621    Opc = ARM::FLDD;
622  } else {
623    assert(RC == ARM::SPRRegisterClass && "Unknown regclass!");
624    Opc = ARM::FLDS;
625  }
626
627  MachineInstrBuilder MIB =  BuildMI(MF, DL, get(Opc), DestReg);
628  for (unsigned i = 0, e = Addr.size(); i != e; ++i)
629    MIB.addOperand(Addr[i]);
630  AddDefaultPred(MIB);
631  NewMIs.push_back(MIB);
632  return;
633}
634
635bool ARMInstrInfo::spillCalleeSavedRegisters(MachineBasicBlock &MBB,
636                                                MachineBasicBlock::iterator MI,
637                                const std::vector<CalleeSavedInfo> &CSI) const {
638  MachineFunction &MF = *MBB.getParent();
639  ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
640  if (!AFI->isThumbFunction() || CSI.empty())
641    return false;
642
643  DebugLoc DL = DebugLoc::getUnknownLoc();
644  if (MI != MBB.end()) DL = MI->getDebugLoc();
645
646  MachineInstrBuilder MIB = BuildMI(MBB, MI, DL, get(ARM::tPUSH));
647  for (unsigned i = CSI.size(); i != 0; --i) {
648    unsigned Reg = CSI[i-1].getReg();
649    // Add the callee-saved register as live-in. It's killed at the spill.
650    MBB.addLiveIn(Reg);
651    MIB.addReg(Reg, false/*isDef*/,false/*isImp*/,true/*isKill*/);
652  }
653  return true;
654}
655
656bool ARMInstrInfo::restoreCalleeSavedRegisters(MachineBasicBlock &MBB,
657                                                 MachineBasicBlock::iterator MI,
658                                const std::vector<CalleeSavedInfo> &CSI) const {
659  MachineFunction &MF = *MBB.getParent();
660  ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
661  if (!AFI->isThumbFunction() || CSI.empty())
662    return false;
663
664  bool isVarArg = AFI->getVarArgsRegSaveSize() > 0;
665  MachineInstr *PopMI = MF.CreateMachineInstr(get(ARM::tPOP),MI->getDebugLoc());
666  MBB.insert(MI, PopMI);
667  for (unsigned i = CSI.size(); i != 0; --i) {
668    unsigned Reg = CSI[i-1].getReg();
669    if (Reg == ARM::LR) {
670      // Special epilogue for vararg functions. See emitEpilogue
671      if (isVarArg)
672        continue;
673      Reg = ARM::PC;
674      PopMI->setDesc(get(ARM::tPOP_RET));
675      MBB.erase(MI);
676    }
677    PopMI->addOperand(MachineOperand::CreateReg(Reg, true));
678  }
679  return true;
680}
681
682MachineInstr *ARMInstrInfo::foldMemoryOperandImpl(MachineFunction &MF,
683                                                  MachineInstr *MI,
684                                        const SmallVectorImpl<unsigned> &Ops,
685                                                  int FI) const {
686  if (Ops.size() != 1) return NULL;
687
688  unsigned OpNum = Ops[0];
689  unsigned Opc = MI->getOpcode();
690  MachineInstr *NewMI = NULL;
691  switch (Opc) {
692  default: break;
693  case ARM::MOVr: {
694    if (MI->getOperand(4).getReg() == ARM::CPSR)
695      // If it is updating CPSR, then it cannot be folded.
696      break;
697    unsigned Pred = MI->getOperand(2).getImm();
698    unsigned PredReg = MI->getOperand(3).getReg();
699    if (OpNum == 0) { // move -> store
700      unsigned SrcReg = MI->getOperand(1).getReg();
701      bool isKill = MI->getOperand(1).isKill();
702      NewMI = BuildMI(MF, MI->getDebugLoc(), get(ARM::STR))
703        .addReg(SrcReg, false, false, isKill)
704        .addFrameIndex(FI).addReg(0).addImm(0).addImm(Pred).addReg(PredReg);
705    } else {          // move -> load
706      unsigned DstReg = MI->getOperand(0).getReg();
707      bool isDead = MI->getOperand(0).isDead();
708      NewMI = BuildMI(MF, MI->getDebugLoc(), get(ARM::LDR))
709        .addReg(DstReg, true, false, false, isDead)
710        .addFrameIndex(FI).addReg(0).addImm(0).addImm(Pred).addReg(PredReg);
711    }
712    break;
713  }
714  case ARM::tMOVr: {
715    if (OpNum == 0) { // move -> store
716      unsigned SrcReg = MI->getOperand(1).getReg();
717      bool isKill = MI->getOperand(1).isKill();
718      if (RI.isPhysicalRegister(SrcReg) && !RI.isLowRegister(SrcReg))
719        // tSpill cannot take a high register operand.
720        break;
721      NewMI = BuildMI(MF, MI->getDebugLoc(), get(ARM::tSpill))
722        .addReg(SrcReg, false, false, isKill)
723        .addFrameIndex(FI).addImm(0);
724    } else {          // move -> load
725      unsigned DstReg = MI->getOperand(0).getReg();
726      if (RI.isPhysicalRegister(DstReg) && !RI.isLowRegister(DstReg))
727        // tRestore cannot target a high register operand.
728        break;
729      bool isDead = MI->getOperand(0).isDead();
730      NewMI = BuildMI(MF, MI->getDebugLoc(), get(ARM::tRestore))
731        .addReg(DstReg, true, false, false, isDead)
732        .addFrameIndex(FI).addImm(0);
733    }
734    break;
735  }
736  case ARM::FCPYS: {
737    unsigned Pred = MI->getOperand(2).getImm();
738    unsigned PredReg = MI->getOperand(3).getReg();
739    if (OpNum == 0) { // move -> store
740      unsigned SrcReg = MI->getOperand(1).getReg();
741      NewMI = BuildMI(MF, MI->getDebugLoc(), get(ARM::FSTS))
742        .addReg(SrcReg).addFrameIndex(FI)
743        .addImm(0).addImm(Pred).addReg(PredReg);
744    } else {          // move -> load
745      unsigned DstReg = MI->getOperand(0).getReg();
746      NewMI = BuildMI(MF, MI->getDebugLoc(), get(ARM::FLDS), DstReg)
747        .addFrameIndex(FI)
748        .addImm(0).addImm(Pred).addReg(PredReg);
749    }
750    break;
751  }
752  case ARM::FCPYD: {
753    unsigned Pred = MI->getOperand(2).getImm();
754    unsigned PredReg = MI->getOperand(3).getReg();
755    if (OpNum == 0) { // move -> store
756      unsigned SrcReg = MI->getOperand(1).getReg();
757      bool isKill = MI->getOperand(1).isKill();
758      NewMI = BuildMI(MF, MI->getDebugLoc(), get(ARM::FSTD))
759        .addReg(SrcReg, false, false, isKill)
760        .addFrameIndex(FI).addImm(0).addImm(Pred).addReg(PredReg);
761    } else {          // move -> load
762      unsigned DstReg = MI->getOperand(0).getReg();
763      bool isDead = MI->getOperand(0).isDead();
764      NewMI = BuildMI(MF, MI->getDebugLoc(), get(ARM::FLDD))
765        .addReg(DstReg, true, false, false, isDead)
766        .addFrameIndex(FI).addImm(0).addImm(Pred).addReg(PredReg);
767    }
768    break;
769  }
770  }
771
772  return NewMI;
773}
774
775bool ARMInstrInfo::canFoldMemoryOperand(const MachineInstr *MI,
776                                  const SmallVectorImpl<unsigned> &Ops) const {
777  if (Ops.size() != 1) return false;
778
779  unsigned OpNum = Ops[0];
780  unsigned Opc = MI->getOpcode();
781  switch (Opc) {
782  default: break;
783  case ARM::MOVr:
784    // If it is updating CPSR, then it cannot be folded.
785    return MI->getOperand(4).getReg() != ARM::CPSR;
786  case ARM::tMOVr: {
787    if (OpNum == 0) { // move -> store
788      unsigned SrcReg = MI->getOperand(1).getReg();
789      if (RI.isPhysicalRegister(SrcReg) && !RI.isLowRegister(SrcReg))
790        // tSpill cannot take a high register operand.
791        return false;
792    } else {          // move -> load
793      unsigned DstReg = MI->getOperand(0).getReg();
794      if (RI.isPhysicalRegister(DstReg) && !RI.isLowRegister(DstReg))
795        // tRestore cannot target a high register operand.
796        return false;
797    }
798    return true;
799  }
800  case ARM::FCPYS:
801  case ARM::FCPYD:
802    return true;
803  }
804
805  return false;
806}
807
808bool ARMInstrInfo::BlockHasNoFallThrough(const MachineBasicBlock &MBB) const {
809  if (MBB.empty()) return false;
810
811  switch (MBB.back().getOpcode()) {
812  case ARM::BX_RET:   // Return.
813  case ARM::LDM_RET:
814  case ARM::tBX_RET:
815  case ARM::tBX_RET_vararg:
816  case ARM::tPOP_RET:
817  case ARM::B:
818  case ARM::tB:       // Uncond branch.
819  case ARM::tBR_JTr:
820  case ARM::BR_JTr:   // Jumptable branch.
821  case ARM::BR_JTm:   // Jumptable branch through mem.
822  case ARM::BR_JTadd: // Jumptable branch add to pc.
823    return true;
824  default: return false;
825  }
826}
827
828bool ARMInstrInfo::
829ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const {
830  ARMCC::CondCodes CC = (ARMCC::CondCodes)(int)Cond[0].getImm();
831  Cond[0].setImm(ARMCC::getOppositeCondition(CC));
832  return false;
833}
834
835bool ARMInstrInfo::isPredicated(const MachineInstr *MI) const {
836  int PIdx = MI->findFirstPredOperandIdx();
837  return PIdx != -1 && MI->getOperand(PIdx).getImm() != ARMCC::AL;
838}
839
840bool ARMInstrInfo::PredicateInstruction(MachineInstr *MI,
841                            const SmallVectorImpl<MachineOperand> &Pred) const {
842  unsigned Opc = MI->getOpcode();
843  if (Opc == ARM::B || Opc == ARM::tB) {
844    MI->setDesc(get(Opc == ARM::B ? ARM::Bcc : ARM::tBcc));
845    MI->addOperand(MachineOperand::CreateImm(Pred[0].getImm()));
846    MI->addOperand(MachineOperand::CreateReg(Pred[1].getReg(), false));
847    return true;
848  }
849
850  int PIdx = MI->findFirstPredOperandIdx();
851  if (PIdx != -1) {
852    MachineOperand &PMO = MI->getOperand(PIdx);
853    PMO.setImm(Pred[0].getImm());
854    MI->getOperand(PIdx+1).setReg(Pred[1].getReg());
855    return true;
856  }
857  return false;
858}
859
860bool
861ARMInstrInfo::SubsumesPredicate(const SmallVectorImpl<MachineOperand> &Pred1,
862                            const SmallVectorImpl<MachineOperand> &Pred2) const{
863  if (Pred1.size() > 2 || Pred2.size() > 2)
864    return false;
865
866  ARMCC::CondCodes CC1 = (ARMCC::CondCodes)Pred1[0].getImm();
867  ARMCC::CondCodes CC2 = (ARMCC::CondCodes)Pred2[0].getImm();
868  if (CC1 == CC2)
869    return true;
870
871  switch (CC1) {
872  default:
873    return false;
874  case ARMCC::AL:
875    return true;
876  case ARMCC::HS:
877    return CC2 == ARMCC::HI;
878  case ARMCC::LS:
879    return CC2 == ARMCC::LO || CC2 == ARMCC::EQ;
880  case ARMCC::GE:
881    return CC2 == ARMCC::GT;
882  case ARMCC::LE:
883    return CC2 == ARMCC::LT;
884  }
885}
886
887bool ARMInstrInfo::DefinesPredicate(MachineInstr *MI,
888                                    std::vector<MachineOperand> &Pred) const {
889  const TargetInstrDesc &TID = MI->getDesc();
890  if (!TID.getImplicitDefs() && !TID.hasOptionalDef())
891    return false;
892
893  bool Found = false;
894  for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
895    const MachineOperand &MO = MI->getOperand(i);
896    if (MO.isReg() && MO.getReg() == ARM::CPSR) {
897      Pred.push_back(MO);
898      Found = true;
899    }
900  }
901
902  return Found;
903}
904
905
906/// FIXME: Works around a gcc miscompilation with -fstrict-aliasing
907static unsigned getNumJTEntries(const std::vector<MachineJumpTableEntry> &JT,
908                                unsigned JTI) DISABLE_INLINE;
909static unsigned getNumJTEntries(const std::vector<MachineJumpTableEntry> &JT,
910                                unsigned JTI) {
911  return JT[JTI].MBBs.size();
912}
913
914/// GetInstSize - Return the size of the specified MachineInstr.
915///
916unsigned ARMInstrInfo::GetInstSizeInBytes(const MachineInstr *MI) const {
917  const MachineBasicBlock &MBB = *MI->getParent();
918  const MachineFunction *MF = MBB.getParent();
919  const TargetAsmInfo *TAI = MF->getTarget().getTargetAsmInfo();
920
921  // Basic size info comes from the TSFlags field.
922  const TargetInstrDesc &TID = MI->getDesc();
923  unsigned TSFlags = TID.TSFlags;
924
925  switch ((TSFlags & ARMII::SizeMask) >> ARMII::SizeShift) {
926  default: {
927    // If this machine instr is an inline asm, measure it.
928    if (MI->getOpcode() == ARM::INLINEASM)
929      return TAI->getInlineAsmLength(MI->getOperand(0).getSymbolName());
930    if (MI->isLabel())
931      return 0;
932    switch (MI->getOpcode()) {
933    default:
934      assert(0 && "Unknown or unset size field for instr!");
935      break;
936    case TargetInstrInfo::IMPLICIT_DEF:
937    case TargetInstrInfo::DECLARE:
938    case TargetInstrInfo::DBG_LABEL:
939    case TargetInstrInfo::EH_LABEL:
940      return 0;
941    }
942    break;
943  }
944  case ARMII::Size8Bytes: return 8;          // Arm instruction x 2.
945  case ARMII::Size4Bytes: return 4;          // Arm instruction.
946  case ARMII::Size2Bytes: return 2;          // Thumb instruction.
947  case ARMII::SizeSpecial: {
948    switch (MI->getOpcode()) {
949    case ARM::CONSTPOOL_ENTRY:
950      // If this machine instr is a constant pool entry, its size is recorded as
951      // operand #2.
952      return MI->getOperand(2).getImm();
953    case ARM::BR_JTr:
954    case ARM::BR_JTm:
955    case ARM::BR_JTadd:
956    case ARM::tBR_JTr: {
957      // These are jumptable branches, i.e. a branch followed by an inlined
958      // jumptable. The size is 4 + 4 * number of entries.
959      unsigned NumOps = TID.getNumOperands();
960      MachineOperand JTOP =
961        MI->getOperand(NumOps - (TID.isPredicable() ? 3 : 2));
962      unsigned JTI = JTOP.getIndex();
963      const MachineJumpTableInfo *MJTI = MF->getJumpTableInfo();
964      const std::vector<MachineJumpTableEntry> &JT = MJTI->getJumpTables();
965      assert(JTI < JT.size());
966      // Thumb instructions are 2 byte aligned, but JT entries are 4 byte
967      // 4 aligned. The assembler / linker may add 2 byte padding just before
968      // the JT entries.  The size does not include this padding; the
969      // constant islands pass does separate bookkeeping for it.
970      // FIXME: If we know the size of the function is less than (1 << 16) *2
971      // bytes, we can use 16-bit entries instead. Then there won't be an
972      // alignment issue.
973      return getNumJTEntries(JT, JTI) * 4 +
974             (MI->getOpcode()==ARM::tBR_JTr ? 2 : 4);
975    }
976    default:
977      // Otherwise, pseudo-instruction sizes are zero.
978      return 0;
979    }
980  }
981  }
982  return 0; // Not reached
983}
984