ARMInstrInfo.cpp revision d57cdd5683ea926e489067364fb7ffe5fd5d35ee 
1//===- ARMInstrInfo.cpp - ARM Instruction Information -----------*- C++ -*-===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file contains the ARM implementation of the TargetInstrInfo class.
11//
12//===----------------------------------------------------------------------===//
13
14#include "ARMInstrInfo.h"
15#include "ARM.h"
16#include "ARMAddressingModes.h"
17#include "ARMGenInstrInfo.inc"
18#include "ARMMachineFunctionInfo.h"
19#include "llvm/ADT/STLExtras.h"
20#include "llvm/CodeGen/LiveVariables.h"
21#include "llvm/CodeGen/MachineFrameInfo.h"
22#include "llvm/CodeGen/MachineInstrBuilder.h"
23#include "llvm/CodeGen/MachineJumpTableInfo.h"
24#include "llvm/MC/MCAsmInfo.h"
25using namespace llvm;
26
27ARMInstrInfo::ARMInstrInfo(const ARMSubtarget &STI)
28  : ARMBaseInstrInfo(STI), RI(*this, STI) {
29}
30
31unsigned ARMInstrInfo::getUnindexedOpcode(unsigned Opc) const {
32  switch (Opc) {
33  default: break;
34  case ARM::LDR_PRE:
35  case ARM::LDR_POST:
36    return ARM::LDR;
37  case ARM::LDRH_PRE:
38  case ARM::LDRH_POST:
39    return ARM::LDRH;
40  case ARM::LDRB_PRE:
41  case ARM::LDRB_POST:
42    return ARM::LDRB;
43  case ARM::LDRSH_PRE:
44  case ARM::LDRSH_POST:
45    return ARM::LDRSH;
46  case ARM::LDRSB_PRE:
47  case ARM::LDRSB_POST:
48    return ARM::LDRSB;
49  case ARM::STR_PRE:
50  case ARM::STR_POST:
51    return ARM::STR;
52  case ARM::STRH_PRE:
53  case ARM::STRH_POST:
54    return ARM::STRH;
55  case ARM::STRB_PRE:
56  case ARM::STRB_POST:
57    return ARM::STRB;
58  }
59
60  return 0;
61}
62
63bool ARMInstrInfo::BlockHasNoFallThrough(const MachineBasicBlock &MBB) const {
64  if (MBB.empty()) return false;
65
66  switch (MBB.back().getOpcode()) {
67  case ARM::BX_RET:   // Return.
68  case ARM::LDM_RET:
69  case ARM::B:
70  case ARM::BRIND:
71  case ARM::BR_JTr:   // Jumptable branch.
72  case ARM::BR_JTm:   // Jumptable branch through mem.
73  case ARM::BR_JTadd: // Jumptable branch add to pc.
74    return true;
75  default:
76    break;
77  }
78
79  return false;
80}
81
82void ARMInstrInfo::
83reMaterialize(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
84              unsigned DestReg, unsigned SubIdx, const MachineInstr *Orig,
85              const TargetRegisterInfo *TRI) const {
86  DebugLoc dl = Orig->getDebugLoc();
87  unsigned Opcode = Orig->getOpcode();
88  switch (Opcode) {
89  default:
90    break;
91  case ARM::MOVi2pieces: {
92    RI.emitLoadConstPool(MBB, I, dl,
93                         DestReg, SubIdx,
94                         Orig->getOperand(1).getImm(),
95                         (ARMCC::CondCodes)Orig->getOperand(2).getImm(),
96                         Orig->getOperand(3).getReg());
97    MachineInstr *NewMI = prior(I);
98    NewMI->getOperand(0).setSubReg(SubIdx);
99    return;
100  }
101  }
102
103  return ARMBaseInstrInfo::reMaterialize(MBB, I, DestReg, SubIdx, Orig, TRI);
104}
105
106