ARMInstrNEON.td revision 2105b90ab62c2b09b380f7b89a4383fe07f8a19e
1//===- ARMInstrNEON.td - NEON support for ARM -----------------------------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file describes the ARM NEON instruction set. 11// 12//===----------------------------------------------------------------------===// 13 14//===----------------------------------------------------------------------===// 15// NEON-specific DAG Nodes. 16//===----------------------------------------------------------------------===// 17 18def SDTARMVCMP : SDTypeProfile<1, 2, [SDTCisInt<0>, SDTCisSameAs<1, 2>]>; 19 20def NEONvceq : SDNode<"ARMISD::VCEQ", SDTARMVCMP>; 21def NEONvcge : SDNode<"ARMISD::VCGE", SDTARMVCMP>; 22def NEONvcgeu : SDNode<"ARMISD::VCGEU", SDTARMVCMP>; 23def NEONvcgt : SDNode<"ARMISD::VCGT", SDTARMVCMP>; 24def NEONvcgtu : SDNode<"ARMISD::VCGTU", SDTARMVCMP>; 25def NEONvtst : SDNode<"ARMISD::VTST", SDTARMVCMP>; 26 27// Types for vector shift by immediates. The "SHX" version is for long and 28// narrow operations where the source and destination vectors have different 29// types. The "SHINS" version is for shift and insert operations. 30def SDTARMVSH : SDTypeProfile<1, 2, [SDTCisInt<0>, SDTCisSameAs<0, 1>, 31 SDTCisVT<2, i32>]>; 32def SDTARMVSHX : SDTypeProfile<1, 2, [SDTCisInt<0>, SDTCisInt<1>, 33 SDTCisVT<2, i32>]>; 34def SDTARMVSHINS : SDTypeProfile<1, 3, [SDTCisInt<0>, SDTCisSameAs<0, 1>, 35 SDTCisSameAs<0, 2>, SDTCisVT<3, i32>]>; 36 37def NEONvshl : SDNode<"ARMISD::VSHL", SDTARMVSH>; 38def NEONvshrs : SDNode<"ARMISD::VSHRs", SDTARMVSH>; 39def NEONvshru : SDNode<"ARMISD::VSHRu", SDTARMVSH>; 40def NEONvshlls : SDNode<"ARMISD::VSHLLs", SDTARMVSHX>; 41def NEONvshllu : SDNode<"ARMISD::VSHLLu", SDTARMVSHX>; 42def NEONvshlli : SDNode<"ARMISD::VSHLLi", SDTARMVSHX>; 43def NEONvshrn : SDNode<"ARMISD::VSHRN", SDTARMVSHX>; 44 45def NEONvrshrs : SDNode<"ARMISD::VRSHRs", SDTARMVSH>; 46def NEONvrshru : SDNode<"ARMISD::VRSHRu", SDTARMVSH>; 47def NEONvrshrn : SDNode<"ARMISD::VRSHRN", SDTARMVSHX>; 48 49def NEONvqshls : SDNode<"ARMISD::VQSHLs", SDTARMVSH>; 50def NEONvqshlu : SDNode<"ARMISD::VQSHLu", SDTARMVSH>; 51def NEONvqshlsu : SDNode<"ARMISD::VQSHLsu", SDTARMVSH>; 52def NEONvqshrns : SDNode<"ARMISD::VQSHRNs", SDTARMVSHX>; 53def NEONvqshrnu : SDNode<"ARMISD::VQSHRNu", SDTARMVSHX>; 54def NEONvqshrnsu : SDNode<"ARMISD::VQSHRNsu", SDTARMVSHX>; 55 56def NEONvqrshrns : SDNode<"ARMISD::VQRSHRNs", SDTARMVSHX>; 57def NEONvqrshrnu : SDNode<"ARMISD::VQRSHRNu", SDTARMVSHX>; 58def NEONvqrshrnsu : SDNode<"ARMISD::VQRSHRNsu", SDTARMVSHX>; 59 60def NEONvsli : SDNode<"ARMISD::VSLI", SDTARMVSHINS>; 61def NEONvsri : SDNode<"ARMISD::VSRI", SDTARMVSHINS>; 62 63def SDTARMVGETLN : SDTypeProfile<1, 2, [SDTCisVT<0, i32>, SDTCisInt<1>, 64 SDTCisVT<2, i32>]>; 65def NEONvgetlaneu : SDNode<"ARMISD::VGETLANEu", SDTARMVGETLN>; 66def NEONvgetlanes : SDNode<"ARMISD::VGETLANEs", SDTARMVGETLN>; 67 68def NEONvduplaneq : SDNode<"ARMISD::VDUPLANEQ", 69 SDTypeProfile<1, 2, [SDTCisVT<2, i32>]>>; 70 71def SDTARMVLD2 : SDTypeProfile<2, 1, [SDTCisSameAs<0, 1>, SDTCisPtrTy<2>]>; 72def SDTARMVLD3 : SDTypeProfile<3, 1, [SDTCisSameAs<0, 1>, 73 SDTCisSameAs<0, 2>, SDTCisPtrTy<3>]>; 74def SDTARMVLD4 : SDTypeProfile<4, 1, [SDTCisSameAs<0, 1>, 75 SDTCisSameAs<0, 2>, 76 SDTCisSameAs<0, 3>, SDTCisPtrTy<4>]>; 77def NEONvld2d : SDNode<"ARMISD::VLD2D", SDTARMVLD2, 78 [SDNPHasChain, SDNPMayLoad]>; 79def NEONvld3d : SDNode<"ARMISD::VLD3D", SDTARMVLD3, 80 [SDNPHasChain, SDNPMayLoad]>; 81def NEONvld4d : SDNode<"ARMISD::VLD4D", SDTARMVLD4, 82 [SDNPHasChain, SDNPMayLoad]>; 83 84//===----------------------------------------------------------------------===// 85// NEON operand definitions 86//===----------------------------------------------------------------------===// 87 88// addrmode_neonldstm := reg 89// 90/* TODO: Take advantage of vldm. 91def addrmode_neonldstm : Operand<i32>, 92 ComplexPattern<i32, 2, "SelectAddrModeNeonLdStM", []> { 93 let PrintMethod = "printAddrNeonLdStMOperand"; 94 let MIOperandInfo = (ops GPR, i32imm); 95} 96*/ 97 98//===----------------------------------------------------------------------===// 99// NEON load / store instructions 100//===----------------------------------------------------------------------===// 101 102/* TODO: Take advantage of vldm. 103let mayLoad = 1 in { 104def VLDMD : NI<(outs), 105 (ins addrmode_neonldstm:$addr, reglist:$dst1, variable_ops), 106 "vldm${addr:submode} ${addr:base}, $dst1", 107 []> { 108 let Inst{27-25} = 0b110; 109 let Inst{20} = 1; 110 let Inst{11-9} = 0b101; 111} 112 113def VLDMS : NI<(outs), 114 (ins addrmode_neonldstm:$addr, reglist:$dst1, variable_ops), 115 "vldm${addr:submode} ${addr:base}, $dst1", 116 []> { 117 let Inst{27-25} = 0b110; 118 let Inst{20} = 1; 119 let Inst{11-9} = 0b101; 120} 121} 122*/ 123 124// Use vldmia to load a Q register as a D register pair. 125def VLDRQ : NI<(outs QPR:$dst), (ins GPR:$addr), 126 "vldmia $addr, ${dst:dregpair}", 127 [(set QPR:$dst, (v2f64 (load GPR:$addr)))]> { 128 let Inst{27-25} = 0b110; 129 let Inst{24} = 0; // P bit 130 let Inst{23} = 1; // U bit 131 let Inst{20} = 1; 132 let Inst{11-9} = 0b101; 133} 134 135// Use vstmia to store a Q register as a D register pair. 136def VSTRQ : NI<(outs), (ins QPR:$src, GPR:$addr), 137 "vstmia $addr, ${src:dregpair}", 138 [(store (v2f64 QPR:$src), GPR:$addr)]> { 139 let Inst{27-25} = 0b110; 140 let Inst{24} = 0; // P bit 141 let Inst{23} = 1; // U bit 142 let Inst{20} = 0; 143 let Inst{11-9} = 0b101; 144} 145 146 147// VLD1 : Vector Load (multiple single elements) 148class VLD1D<string OpcodeStr, ValueType Ty, Intrinsic IntOp> 149 : NLdSt<(outs DPR:$dst), (ins addrmode6:$addr), 150 !strconcat(OpcodeStr, "\t\\{$dst\\}, $addr"), 151 [(set DPR:$dst, (Ty (IntOp addrmode6:$addr)))]>; 152class VLD1Q<string OpcodeStr, ValueType Ty, Intrinsic IntOp> 153 : NLdSt<(outs QPR:$dst), (ins addrmode6:$addr), 154 !strconcat(OpcodeStr, "\t${dst:dregpair}, $addr"), 155 [(set QPR:$dst, (Ty (IntOp addrmode6:$addr)))]>; 156 157def VLD1d8 : VLD1D<"vld1.8", v8i8, int_arm_neon_vld1i>; 158def VLD1d16 : VLD1D<"vld1.16", v4i16, int_arm_neon_vld1i>; 159def VLD1d32 : VLD1D<"vld1.32", v2i32, int_arm_neon_vld1i>; 160def VLD1df : VLD1D<"vld1.32", v2f32, int_arm_neon_vld1f>; 161def VLD1d64 : VLD1D<"vld1.64", v1i64, int_arm_neon_vld1i>; 162 163def VLD1q8 : VLD1Q<"vld1.8", v16i8, int_arm_neon_vld1i>; 164def VLD1q16 : VLD1Q<"vld1.16", v8i16, int_arm_neon_vld1i>; 165def VLD1q32 : VLD1Q<"vld1.32", v4i32, int_arm_neon_vld1i>; 166def VLD1qf : VLD1Q<"vld1.32", v4f32, int_arm_neon_vld1f>; 167def VLD1q64 : VLD1Q<"vld1.64", v2i64, int_arm_neon_vld1i>; 168 169// VST1 : Vector Store (multiple single elements) 170class VST1D<string OpcodeStr, ValueType Ty, Intrinsic IntOp> 171 : NLdSt<(outs), (ins addrmode6:$addr, DPR:$src), 172 !strconcat(OpcodeStr, "\t\\{$src\\}, $addr"), 173 [(IntOp addrmode6:$addr, (Ty DPR:$src))]>; 174class VST1Q<string OpcodeStr, ValueType Ty, Intrinsic IntOp> 175 : NLdSt<(outs), (ins addrmode6:$addr, QPR:$src), 176 !strconcat(OpcodeStr, "\t${src:dregpair}, $addr"), 177 [(IntOp addrmode6:$addr, (Ty QPR:$src))]>; 178 179def VST1d8 : VST1D<"vst1.8", v8i8, int_arm_neon_vst1i>; 180def VST1d16 : VST1D<"vst1.16", v4i16, int_arm_neon_vst1i>; 181def VST1d32 : VST1D<"vst1.32", v2i32, int_arm_neon_vst1i>; 182def VST1df : VST1D<"vst1.32", v2f32, int_arm_neon_vst1f>; 183def VST1d64 : VST1D<"vst1.64", v1i64, int_arm_neon_vst1i>; 184 185def VST1q8 : VST1Q<"vst1.8", v16i8, int_arm_neon_vst1i>; 186def VST1q16 : VST1Q<"vst1.16", v8i16, int_arm_neon_vst1i>; 187def VST1q32 : VST1Q<"vst1.32", v4i32, int_arm_neon_vst1i>; 188def VST1qf : VST1Q<"vst1.32", v4f32, int_arm_neon_vst1f>; 189def VST1q64 : VST1Q<"vst1.64", v2i64, int_arm_neon_vst1i>; 190 191// VLD2 : Vector Load (multiple 2-element structures) 192class VLD2D<string OpcodeStr> 193 : NLdSt<(outs DPR:$dst1, DPR:$dst2), (ins addrmode6:$addr), 194 !strconcat(OpcodeStr, "\t\\{$dst1,$dst2\\}, $addr"), []>; 195 196def VLD2d8 : VLD2D<"vld2.8">; 197def VLD2d16 : VLD2D<"vld2.16">; 198def VLD2d32 : VLD2D<"vld2.32">; 199def VLD2d64 : VLD2D<"vld2.64">; 200 201// VLD3 : Vector Load (multiple 3-element structures) 202class VLD3D<string OpcodeStr> 203 : NLdSt<(outs DPR:$dst1, DPR:$dst2, DPR:$dst3), (ins addrmode6:$addr), 204 !strconcat(OpcodeStr, "\t\\{$dst1,$dst2,$dst3\\}, $addr"), []>; 205 206def VLD3d8 : VLD3D<"vld3.8">; 207def VLD3d16 : VLD3D<"vld3.16">; 208def VLD3d32 : VLD3D<"vld3.32">; 209def VLD3d64 : VLD3D<"vld3.64">; 210 211// VLD4 : Vector Load (multiple 4-element structures) 212class VLD4D<string OpcodeStr> 213 : NLdSt<(outs DPR:$dst1, DPR:$dst2, DPR:$dst3, DPR:$dst4), 214 (ins addrmode6:$addr), 215 !strconcat(OpcodeStr, "\t\\{$dst1,$dst2,$dst3,$dst4\\}, $addr"), []>; 216 217def VLD4d8 : VLD4D<"vld4.8">; 218def VLD4d16 : VLD4D<"vld4.16">; 219def VLD4d32 : VLD4D<"vld4.32">; 220def VLD4d64 : VLD4D<"vld4.64">; 221 222 223//===----------------------------------------------------------------------===// 224// NEON pattern fragments 225//===----------------------------------------------------------------------===// 226 227// Extract D sub-registers of Q registers. 228// (arm_dsubreg_0 is 5; arm_dsubreg_1 is 6) 229def SubReg_i8_reg : SDNodeXForm<imm, [{ 230 return CurDAG->getTargetConstant(5 + N->getZExtValue() / 8, MVT::i32); 231}]>; 232def SubReg_i16_reg : SDNodeXForm<imm, [{ 233 return CurDAG->getTargetConstant(5 + N->getZExtValue() / 4, MVT::i32); 234}]>; 235def SubReg_i32_reg : SDNodeXForm<imm, [{ 236 return CurDAG->getTargetConstant(5 + N->getZExtValue() / 2, MVT::i32); 237}]>; 238def SubReg_f64_reg : SDNodeXForm<imm, [{ 239 return CurDAG->getTargetConstant(5 + N->getZExtValue(), MVT::i32); 240}]>; 241 242// Translate lane numbers from Q registers to D subregs. 243def SubReg_i8_lane : SDNodeXForm<imm, [{ 244 return CurDAG->getTargetConstant(N->getZExtValue() & 7, MVT::i32); 245}]>; 246def SubReg_i16_lane : SDNodeXForm<imm, [{ 247 return CurDAG->getTargetConstant(N->getZExtValue() & 3, MVT::i32); 248}]>; 249def SubReg_i32_lane : SDNodeXForm<imm, [{ 250 return CurDAG->getTargetConstant(N->getZExtValue() & 1, MVT::i32); 251}]>; 252 253//===----------------------------------------------------------------------===// 254// Instruction Classes 255//===----------------------------------------------------------------------===// 256 257// Basic 2-register operations, both double- and quad-register. 258class N2VD<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18, 259 bits<2> op17_16, bits<5> op11_7, bit op4, string OpcodeStr, 260 ValueType ResTy, ValueType OpTy, SDNode OpNode> 261 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, 0, op4, (outs DPR:$dst), 262 (ins DPR:$src), !strconcat(OpcodeStr, "\t$dst, $src"), "", 263 [(set DPR:$dst, (ResTy (OpNode (OpTy DPR:$src))))]>; 264class N2VQ<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18, 265 bits<2> op17_16, bits<5> op11_7, bit op4, string OpcodeStr, 266 ValueType ResTy, ValueType OpTy, SDNode OpNode> 267 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, 1, op4, (outs QPR:$dst), 268 (ins QPR:$src), !strconcat(OpcodeStr, "\t$dst, $src"), "", 269 [(set QPR:$dst, (ResTy (OpNode (OpTy QPR:$src))))]>; 270 271// Basic 2-register intrinsics, both double- and quad-register. 272class N2VDInt<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18, 273 bits<2> op17_16, bits<5> op11_7, bit op4, string OpcodeStr, 274 ValueType ResTy, ValueType OpTy, Intrinsic IntOp> 275 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, 0, op4, (outs DPR:$dst), 276 (ins DPR:$src), !strconcat(OpcodeStr, "\t$dst, $src"), "", 277 [(set DPR:$dst, (ResTy (IntOp (OpTy DPR:$src))))]>; 278class N2VQInt<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18, 279 bits<2> op17_16, bits<5> op11_7, bit op4, string OpcodeStr, 280 ValueType ResTy, ValueType OpTy, Intrinsic IntOp> 281 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, 1, op4, (outs QPR:$dst), 282 (ins QPR:$src), !strconcat(OpcodeStr, "\t$dst, $src"), "", 283 [(set QPR:$dst, (ResTy (IntOp (OpTy QPR:$src))))]>; 284 285// Basic 2-register operations, scalar single-precision 286class N2VDInts<SDNode OpNode, NeonI Inst> 287 : NEONFPPat<(f32 (OpNode SPR:$a)), 288 (EXTRACT_SUBREG (COPY_TO_REGCLASS 289 (Inst (INSERT_SUBREG (v2f32 (IMPLICIT_DEF)), 290 SPR:$a, arm_ssubreg_0)), 291 DPR_VFP2), 292 arm_ssubreg_0)>; 293 294// Narrow 2-register intrinsics. 295class N2VNInt<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18, 296 bits<2> op17_16, bits<5> op11_7, bit op6, bit op4, 297 string OpcodeStr, ValueType TyD, ValueType TyQ, Intrinsic IntOp> 298 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, op6, op4, (outs DPR:$dst), 299 (ins QPR:$src), !strconcat(OpcodeStr, "\t$dst, $src"), "", 300 [(set DPR:$dst, (TyD (IntOp (TyQ QPR:$src))))]>; 301 302// Long 2-register intrinsics. (This is currently only used for VMOVL and is 303// derived from N2VImm instead of N2V because of the way the size is encoded.) 304class N2VLInt<bit op24, bit op23, bits<6> op21_16, bits<4> op11_8, bit op7, 305 bit op6, bit op4, string OpcodeStr, ValueType TyQ, ValueType TyD, 306 Intrinsic IntOp> 307 : N2VImm<op24, op23, op21_16, op11_8, op7, op6, op4, (outs QPR:$dst), 308 (ins DPR:$src), !strconcat(OpcodeStr, "\t$dst, $src"), "", 309 [(set QPR:$dst, (TyQ (IntOp (TyD DPR:$src))))]>; 310 311// Basic 3-register operations, both double- and quad-register. 312class N3VD<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4, 313 string OpcodeStr, ValueType ResTy, ValueType OpTy, 314 SDNode OpNode, bit Commutable> 315 : N3V<op24, op23, op21_20, op11_8, 0, op4, 316 (outs DPR:$dst), (ins DPR:$src1, DPR:$src2), 317 !strconcat(OpcodeStr, "\t$dst, $src1, $src2"), "", 318 [(set DPR:$dst, (ResTy (OpNode (OpTy DPR:$src1), (OpTy DPR:$src2))))]> { 319 let isCommutable = Commutable; 320} 321class N3VQ<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4, 322 string OpcodeStr, ValueType ResTy, ValueType OpTy, 323 SDNode OpNode, bit Commutable> 324 : N3V<op24, op23, op21_20, op11_8, 1, op4, 325 (outs QPR:$dst), (ins QPR:$src1, QPR:$src2), 326 !strconcat(OpcodeStr, "\t$dst, $src1, $src2"), "", 327 [(set QPR:$dst, (ResTy (OpNode (OpTy QPR:$src1), (OpTy QPR:$src2))))]> { 328 let isCommutable = Commutable; 329} 330 331// Basic 3-register operations, scalar single-precision 332class N3VDs<SDNode OpNode, NeonI Inst> 333 : NEONFPPat<(f32 (OpNode SPR:$a, SPR:$b)), 334 (EXTRACT_SUBREG (COPY_TO_REGCLASS 335 (Inst (INSERT_SUBREG (v2f32 (IMPLICIT_DEF)), 336 SPR:$a, arm_ssubreg_0), 337 (INSERT_SUBREG (v2f32 (IMPLICIT_DEF)), 338 SPR:$b, arm_ssubreg_0)), 339 DPR_VFP2), 340 arm_ssubreg_0)>; 341 342// Basic 3-register intrinsics, both double- and quad-register. 343class N3VDInt<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4, 344 string OpcodeStr, ValueType ResTy, ValueType OpTy, 345 Intrinsic IntOp, bit Commutable> 346 : N3V<op24, op23, op21_20, op11_8, 0, op4, 347 (outs DPR:$dst), (ins DPR:$src1, DPR:$src2), 348 !strconcat(OpcodeStr, "\t$dst, $src1, $src2"), "", 349 [(set DPR:$dst, (ResTy (IntOp (OpTy DPR:$src1), (OpTy DPR:$src2))))]> { 350 let isCommutable = Commutable; 351} 352class N3VQInt<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4, 353 string OpcodeStr, ValueType ResTy, ValueType OpTy, 354 Intrinsic IntOp, bit Commutable> 355 : N3V<op24, op23, op21_20, op11_8, 1, op4, 356 (outs QPR:$dst), (ins QPR:$src1, QPR:$src2), 357 !strconcat(OpcodeStr, "\t$dst, $src1, $src2"), "", 358 [(set QPR:$dst, (ResTy (IntOp (OpTy QPR:$src1), (OpTy QPR:$src2))))]> { 359 let isCommutable = Commutable; 360} 361 362// Multiply-Add/Sub operations, both double- and quad-register. 363class N3VDMulOp<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4, 364 string OpcodeStr, ValueType Ty, SDNode MulOp, SDNode OpNode> 365 : N3V<op24, op23, op21_20, op11_8, 0, op4, 366 (outs DPR:$dst), (ins DPR:$src1, DPR:$src2, DPR:$src3), 367 !strconcat(OpcodeStr, "\t$dst, $src2, $src3"), "$src1 = $dst", 368 [(set DPR:$dst, (Ty (OpNode DPR:$src1, 369 (Ty (MulOp DPR:$src2, DPR:$src3)))))]>; 370class N3VQMulOp<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4, 371 string OpcodeStr, ValueType Ty, SDNode MulOp, SDNode OpNode> 372 : N3V<op24, op23, op21_20, op11_8, 1, op4, 373 (outs QPR:$dst), (ins QPR:$src1, QPR:$src2, QPR:$src3), 374 !strconcat(OpcodeStr, "\t$dst, $src2, $src3"), "$src1 = $dst", 375 [(set QPR:$dst, (Ty (OpNode QPR:$src1, 376 (Ty (MulOp QPR:$src2, QPR:$src3)))))]>; 377 378// Multiply-Add/Sub operations, scalar single-precision 379class N3VDMulOps<SDNode MulNode, SDNode OpNode, NeonI Inst> 380 : NEONFPPat<(f32 (OpNode SPR:$acc, 381 (f32 (MulNode SPR:$a, SPR:$b)))), 382 (EXTRACT_SUBREG (COPY_TO_REGCLASS 383 (Inst (INSERT_SUBREG (v2f32 (IMPLICIT_DEF)), 384 SPR:$acc, arm_ssubreg_0), 385 (INSERT_SUBREG (v2f32 (IMPLICIT_DEF)), 386 SPR:$a, arm_ssubreg_0), 387 (INSERT_SUBREG (v2f32 (IMPLICIT_DEF)), 388 SPR:$b, arm_ssubreg_0)), 389 DPR_VFP2), 390 arm_ssubreg_0)>; 391 392// Neon 3-argument intrinsics, both double- and quad-register. 393// The destination register is also used as the first source operand register. 394class N3VDInt3<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4, 395 string OpcodeStr, ValueType ResTy, ValueType OpTy, 396 Intrinsic IntOp> 397 : N3V<op24, op23, op21_20, op11_8, 0, op4, 398 (outs DPR:$dst), (ins DPR:$src1, DPR:$src2, DPR:$src3), 399 !strconcat(OpcodeStr, "\t$dst, $src2, $src3"), "$src1 = $dst", 400 [(set DPR:$dst, (ResTy (IntOp (OpTy DPR:$src1), 401 (OpTy DPR:$src2), (OpTy DPR:$src3))))]>; 402class N3VQInt3<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4, 403 string OpcodeStr, ValueType ResTy, ValueType OpTy, 404 Intrinsic IntOp> 405 : N3V<op24, op23, op21_20, op11_8, 1, op4, 406 (outs QPR:$dst), (ins QPR:$src1, QPR:$src2, QPR:$src3), 407 !strconcat(OpcodeStr, "\t$dst, $src2, $src3"), "$src1 = $dst", 408 [(set QPR:$dst, (ResTy (IntOp (OpTy QPR:$src1), 409 (OpTy QPR:$src2), (OpTy QPR:$src3))))]>; 410 411// Neon Long 3-argument intrinsic. The destination register is 412// a quad-register and is also used as the first source operand register. 413class N3VLInt3<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4, 414 string OpcodeStr, ValueType TyQ, ValueType TyD, Intrinsic IntOp> 415 : N3V<op24, op23, op21_20, op11_8, 0, op4, 416 (outs QPR:$dst), (ins QPR:$src1, DPR:$src2, DPR:$src3), 417 !strconcat(OpcodeStr, "\t$dst, $src2, $src3"), "$src1 = $dst", 418 [(set QPR:$dst, 419 (TyQ (IntOp (TyQ QPR:$src1), (TyD DPR:$src2), (TyD DPR:$src3))))]>; 420 421// Narrowing 3-register intrinsics. 422class N3VNInt<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4, 423 string OpcodeStr, ValueType TyD, ValueType TyQ, 424 Intrinsic IntOp, bit Commutable> 425 : N3V<op24, op23, op21_20, op11_8, 0, op4, 426 (outs DPR:$dst), (ins QPR:$src1, QPR:$src2), 427 !strconcat(OpcodeStr, "\t$dst, $src1, $src2"), "", 428 [(set DPR:$dst, (TyD (IntOp (TyQ QPR:$src1), (TyQ QPR:$src2))))]> { 429 let isCommutable = Commutable; 430} 431 432// Long 3-register intrinsics. 433class N3VLInt<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4, 434 string OpcodeStr, ValueType TyQ, ValueType TyD, 435 Intrinsic IntOp, bit Commutable> 436 : N3V<op24, op23, op21_20, op11_8, 0, op4, 437 (outs QPR:$dst), (ins DPR:$src1, DPR:$src2), 438 !strconcat(OpcodeStr, "\t$dst, $src1, $src2"), "", 439 [(set QPR:$dst, (TyQ (IntOp (TyD DPR:$src1), (TyD DPR:$src2))))]> { 440 let isCommutable = Commutable; 441} 442 443// Wide 3-register intrinsics. 444class N3VWInt<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4, 445 string OpcodeStr, ValueType TyQ, ValueType TyD, 446 Intrinsic IntOp, bit Commutable> 447 : N3V<op24, op23, op21_20, op11_8, 0, op4, 448 (outs QPR:$dst), (ins QPR:$src1, DPR:$src2), 449 !strconcat(OpcodeStr, "\t$dst, $src1, $src2"), "", 450 [(set QPR:$dst, (TyQ (IntOp (TyQ QPR:$src1), (TyD DPR:$src2))))]> { 451 let isCommutable = Commutable; 452} 453 454// Pairwise long 2-register intrinsics, both double- and quad-register. 455class N2VDPLInt<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18, 456 bits<2> op17_16, bits<5> op11_7, bit op4, string OpcodeStr, 457 ValueType ResTy, ValueType OpTy, Intrinsic IntOp> 458 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, 0, op4, (outs DPR:$dst), 459 (ins DPR:$src), !strconcat(OpcodeStr, "\t$dst, $src"), "", 460 [(set DPR:$dst, (ResTy (IntOp (OpTy DPR:$src))))]>; 461class N2VQPLInt<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18, 462 bits<2> op17_16, bits<5> op11_7, bit op4, string OpcodeStr, 463 ValueType ResTy, ValueType OpTy, Intrinsic IntOp> 464 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, 1, op4, (outs QPR:$dst), 465 (ins QPR:$src), !strconcat(OpcodeStr, "\t$dst, $src"), "", 466 [(set QPR:$dst, (ResTy (IntOp (OpTy QPR:$src))))]>; 467 468// Pairwise long 2-register accumulate intrinsics, 469// both double- and quad-register. 470// The destination register is also used as the first source operand register. 471class N2VDPLInt2<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18, 472 bits<2> op17_16, bits<5> op11_7, bit op4, string OpcodeStr, 473 ValueType ResTy, ValueType OpTy, Intrinsic IntOp> 474 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, 0, op4, 475 (outs DPR:$dst), (ins DPR:$src1, DPR:$src2), 476 !strconcat(OpcodeStr, "\t$dst, $src2"), "$src1 = $dst", 477 [(set DPR:$dst, (ResTy (IntOp (ResTy DPR:$src1), (OpTy DPR:$src2))))]>; 478class N2VQPLInt2<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18, 479 bits<2> op17_16, bits<5> op11_7, bit op4, string OpcodeStr, 480 ValueType ResTy, ValueType OpTy, Intrinsic IntOp> 481 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, 1, op4, 482 (outs QPR:$dst), (ins QPR:$src1, QPR:$src2), 483 !strconcat(OpcodeStr, "\t$dst, $src2"), "$src1 = $dst", 484 [(set QPR:$dst, (ResTy (IntOp (ResTy QPR:$src1), (OpTy QPR:$src2))))]>; 485 486// Shift by immediate, 487// both double- and quad-register. 488class N2VDSh<bit op24, bit op23, bits<6> op21_16, bits<4> op11_8, bit op7, 489 bit op4, string OpcodeStr, ValueType Ty, SDNode OpNode> 490 : N2VImm<op24, op23, op21_16, op11_8, op7, 0, op4, 491 (outs DPR:$dst), (ins DPR:$src, i32imm:$SIMM), 492 !strconcat(OpcodeStr, "\t$dst, $src, $SIMM"), "", 493 [(set DPR:$dst, (Ty (OpNode (Ty DPR:$src), (i32 imm:$SIMM))))]>; 494class N2VQSh<bit op24, bit op23, bits<6> op21_16, bits<4> op11_8, bit op7, 495 bit op4, string OpcodeStr, ValueType Ty, SDNode OpNode> 496 : N2VImm<op24, op23, op21_16, op11_8, op7, 1, op4, 497 (outs QPR:$dst), (ins QPR:$src, i32imm:$SIMM), 498 !strconcat(OpcodeStr, "\t$dst, $src, $SIMM"), "", 499 [(set QPR:$dst, (Ty (OpNode (Ty QPR:$src), (i32 imm:$SIMM))))]>; 500 501// Long shift by immediate. 502class N2VLSh<bit op24, bit op23, bits<6> op21_16, bits<4> op11_8, bit op7, 503 bit op6, bit op4, string OpcodeStr, ValueType ResTy, 504 ValueType OpTy, SDNode OpNode> 505 : N2VImm<op24, op23, op21_16, op11_8, op7, op6, op4, 506 (outs QPR:$dst), (ins DPR:$src, i32imm:$SIMM), 507 !strconcat(OpcodeStr, "\t$dst, $src, $SIMM"), "", 508 [(set QPR:$dst, (ResTy (OpNode (OpTy DPR:$src), 509 (i32 imm:$SIMM))))]>; 510 511// Narrow shift by immediate. 512class N2VNSh<bit op24, bit op23, bits<6> op21_16, bits<4> op11_8, bit op7, 513 bit op6, bit op4, string OpcodeStr, ValueType ResTy, 514 ValueType OpTy, SDNode OpNode> 515 : N2VImm<op24, op23, op21_16, op11_8, op7, op6, op4, 516 (outs DPR:$dst), (ins QPR:$src, i32imm:$SIMM), 517 !strconcat(OpcodeStr, "\t$dst, $src, $SIMM"), "", 518 [(set DPR:$dst, (ResTy (OpNode (OpTy QPR:$src), 519 (i32 imm:$SIMM))))]>; 520 521// Shift right by immediate and accumulate, 522// both double- and quad-register. 523class N2VDShAdd<bit op24, bit op23, bits<6> op21_16, bits<4> op11_8, bit op7, 524 bit op4, string OpcodeStr, ValueType Ty, SDNode ShOp> 525 : N2VImm<op24, op23, op21_16, op11_8, op7, 0, op4, 526 (outs DPR:$dst), (ins DPR:$src1, DPR:$src2, i32imm:$SIMM), 527 !strconcat(OpcodeStr, "\t$dst, $src2, $SIMM"), "$src1 = $dst", 528 [(set DPR:$dst, (Ty (add DPR:$src1, 529 (Ty (ShOp DPR:$src2, (i32 imm:$SIMM))))))]>; 530class N2VQShAdd<bit op24, bit op23, bits<6> op21_16, bits<4> op11_8, bit op7, 531 bit op4, string OpcodeStr, ValueType Ty, SDNode ShOp> 532 : N2VImm<op24, op23, op21_16, op11_8, op7, 1, op4, 533 (outs QPR:$dst), (ins QPR:$src1, QPR:$src2, i32imm:$SIMM), 534 !strconcat(OpcodeStr, "\t$dst, $src2, $SIMM"), "$src1 = $dst", 535 [(set QPR:$dst, (Ty (add QPR:$src1, 536 (Ty (ShOp QPR:$src2, (i32 imm:$SIMM))))))]>; 537 538// Shift by immediate and insert, 539// both double- and quad-register. 540class N2VDShIns<bit op24, bit op23, bits<6> op21_16, bits<4> op11_8, bit op7, 541 bit op4, string OpcodeStr, ValueType Ty, SDNode ShOp> 542 : N2VImm<op24, op23, op21_16, op11_8, op7, 0, op4, 543 (outs DPR:$dst), (ins DPR:$src1, DPR:$src2, i32imm:$SIMM), 544 !strconcat(OpcodeStr, "\t$dst, $src2, $SIMM"), "$src1 = $dst", 545 [(set DPR:$dst, (Ty (ShOp DPR:$src1, DPR:$src2, (i32 imm:$SIMM))))]>; 546class N2VQShIns<bit op24, bit op23, bits<6> op21_16, bits<4> op11_8, bit op7, 547 bit op4, string OpcodeStr, ValueType Ty, SDNode ShOp> 548 : N2VImm<op24, op23, op21_16, op11_8, op7, 1, op4, 549 (outs QPR:$dst), (ins QPR:$src1, QPR:$src2, i32imm:$SIMM), 550 !strconcat(OpcodeStr, "\t$dst, $src2, $SIMM"), "$src1 = $dst", 551 [(set QPR:$dst, (Ty (ShOp QPR:$src1, QPR:$src2, (i32 imm:$SIMM))))]>; 552 553// Convert, with fractional bits immediate, 554// both double- and quad-register. 555class N2VCvtD<bit op24, bit op23, bits<6> op21_16, bits<4> op11_8, bit op7, 556 bit op4, string OpcodeStr, ValueType ResTy, ValueType OpTy, 557 Intrinsic IntOp> 558 : N2VImm<op24, op23, op21_16, op11_8, op7, 0, op4, 559 (outs DPR:$dst), (ins DPR:$src, i32imm:$SIMM), 560 !strconcat(OpcodeStr, "\t$dst, $src, $SIMM"), "", 561 [(set DPR:$dst, (ResTy (IntOp (OpTy DPR:$src), (i32 imm:$SIMM))))]>; 562class N2VCvtQ<bit op24, bit op23, bits<6> op21_16, bits<4> op11_8, bit op7, 563 bit op4, string OpcodeStr, ValueType ResTy, ValueType OpTy, 564 Intrinsic IntOp> 565 : N2VImm<op24, op23, op21_16, op11_8, op7, 1, op4, 566 (outs QPR:$dst), (ins QPR:$src, i32imm:$SIMM), 567 !strconcat(OpcodeStr, "\t$dst, $src, $SIMM"), "", 568 [(set QPR:$dst, (ResTy (IntOp (OpTy QPR:$src), (i32 imm:$SIMM))))]>; 569 570//===----------------------------------------------------------------------===// 571// Multiclasses 572//===----------------------------------------------------------------------===// 573 574// Neon 3-register vector operations. 575 576// First with only element sizes of 8, 16 and 32 bits: 577multiclass N3V_QHS<bit op24, bit op23, bits<4> op11_8, bit op4, 578 string OpcodeStr, SDNode OpNode, bit Commutable = 0> { 579 // 64-bit vector types. 580 def v8i8 : N3VD<op24, op23, 0b00, op11_8, op4, !strconcat(OpcodeStr, "8"), 581 v8i8, v8i8, OpNode, Commutable>; 582 def v4i16 : N3VD<op24, op23, 0b01, op11_8, op4, !strconcat(OpcodeStr, "16"), 583 v4i16, v4i16, OpNode, Commutable>; 584 def v2i32 : N3VD<op24, op23, 0b10, op11_8, op4, !strconcat(OpcodeStr, "32"), 585 v2i32, v2i32, OpNode, Commutable>; 586 587 // 128-bit vector types. 588 def v16i8 : N3VQ<op24, op23, 0b00, op11_8, op4, !strconcat(OpcodeStr, "8"), 589 v16i8, v16i8, OpNode, Commutable>; 590 def v8i16 : N3VQ<op24, op23, 0b01, op11_8, op4, !strconcat(OpcodeStr, "16"), 591 v8i16, v8i16, OpNode, Commutable>; 592 def v4i32 : N3VQ<op24, op23, 0b10, op11_8, op4, !strconcat(OpcodeStr, "32"), 593 v4i32, v4i32, OpNode, Commutable>; 594} 595 596// ....then also with element size 64 bits: 597multiclass N3V_QHSD<bit op24, bit op23, bits<4> op11_8, bit op4, 598 string OpcodeStr, SDNode OpNode, bit Commutable = 0> 599 : N3V_QHS<op24, op23, op11_8, op4, OpcodeStr, OpNode, Commutable> { 600 def v1i64 : N3VD<op24, op23, 0b11, op11_8, op4, !strconcat(OpcodeStr, "64"), 601 v1i64, v1i64, OpNode, Commutable>; 602 def v2i64 : N3VQ<op24, op23, 0b11, op11_8, op4, !strconcat(OpcodeStr, "64"), 603 v2i64, v2i64, OpNode, Commutable>; 604} 605 606 607// Neon Narrowing 2-register vector intrinsics, 608// source operand element sizes of 16, 32 and 64 bits: 609multiclass N2VNInt_HSD<bits<2> op24_23, bits<2> op21_20, bits<2> op17_16, 610 bits<5> op11_7, bit op6, bit op4, string OpcodeStr, 611 Intrinsic IntOp> { 612 def v8i8 : N2VNInt<op24_23, op21_20, 0b00, op17_16, op11_7, op6, op4, 613 !strconcat(OpcodeStr, "16"), v8i8, v8i16, IntOp>; 614 def v4i16 : N2VNInt<op24_23, op21_20, 0b01, op17_16, op11_7, op6, op4, 615 !strconcat(OpcodeStr, "32"), v4i16, v4i32, IntOp>; 616 def v2i32 : N2VNInt<op24_23, op21_20, 0b10, op17_16, op11_7, op6, op4, 617 !strconcat(OpcodeStr, "64"), v2i32, v2i64, IntOp>; 618} 619 620 621// Neon Lengthening 2-register vector intrinsic (currently specific to VMOVL). 622// source operand element sizes of 16, 32 and 64 bits: 623multiclass N2VLInt_QHS<bit op24, bit op23, bits<4> op11_8, bit op7, bit op6, 624 bit op4, string OpcodeStr, Intrinsic IntOp> { 625 def v8i16 : N2VLInt<op24, op23, 0b001000, op11_8, op7, op6, op4, 626 !strconcat(OpcodeStr, "8"), v8i16, v8i8, IntOp>; 627 def v4i32 : N2VLInt<op24, op23, 0b010000, op11_8, op7, op6, op4, 628 !strconcat(OpcodeStr, "16"), v4i32, v4i16, IntOp>; 629 def v2i64 : N2VLInt<op24, op23, 0b100000, op11_8, op7, op6, op4, 630 !strconcat(OpcodeStr, "32"), v2i64, v2i32, IntOp>; 631} 632 633 634// Neon 3-register vector intrinsics. 635 636// First with only element sizes of 16 and 32 bits: 637multiclass N3VInt_HS<bit op24, bit op23, bits<4> op11_8, bit op4, 638 string OpcodeStr, Intrinsic IntOp, bit Commutable = 0> { 639 // 64-bit vector types. 640 def v4i16 : N3VDInt<op24, op23, 0b01, op11_8, op4, !strconcat(OpcodeStr,"16"), 641 v4i16, v4i16, IntOp, Commutable>; 642 def v2i32 : N3VDInt<op24, op23, 0b10, op11_8, op4, !strconcat(OpcodeStr,"32"), 643 v2i32, v2i32, IntOp, Commutable>; 644 645 // 128-bit vector types. 646 def v8i16 : N3VQInt<op24, op23, 0b01, op11_8, op4, !strconcat(OpcodeStr,"16"), 647 v8i16, v8i16, IntOp, Commutable>; 648 def v4i32 : N3VQInt<op24, op23, 0b10, op11_8, op4, !strconcat(OpcodeStr,"32"), 649 v4i32, v4i32, IntOp, Commutable>; 650} 651 652// ....then also with element size of 8 bits: 653multiclass N3VInt_QHS<bit op24, bit op23, bits<4> op11_8, bit op4, 654 string OpcodeStr, Intrinsic IntOp, bit Commutable = 0> 655 : N3VInt_HS<op24, op23, op11_8, op4, OpcodeStr, IntOp, Commutable> { 656 def v8i8 : N3VDInt<op24, op23, 0b00, op11_8, op4, !strconcat(OpcodeStr, "8"), 657 v8i8, v8i8, IntOp, Commutable>; 658 def v16i8 : N3VQInt<op24, op23, 0b00, op11_8, op4, !strconcat(OpcodeStr, "8"), 659 v16i8, v16i8, IntOp, Commutable>; 660} 661 662// ....then also with element size of 64 bits: 663multiclass N3VInt_QHSD<bit op24, bit op23, bits<4> op11_8, bit op4, 664 string OpcodeStr, Intrinsic IntOp, bit Commutable = 0> 665 : N3VInt_QHS<op24, op23, op11_8, op4, OpcodeStr, IntOp, Commutable> { 666 def v1i64 : N3VDInt<op24, op23, 0b11, op11_8, op4, !strconcat(OpcodeStr,"64"), 667 v1i64, v1i64, IntOp, Commutable>; 668 def v2i64 : N3VQInt<op24, op23, 0b11, op11_8, op4, !strconcat(OpcodeStr,"64"), 669 v2i64, v2i64, IntOp, Commutable>; 670} 671 672 673// Neon Narrowing 3-register vector intrinsics, 674// source operand element sizes of 16, 32 and 64 bits: 675multiclass N3VNInt_HSD<bit op24, bit op23, bits<4> op11_8, bit op4, 676 string OpcodeStr, Intrinsic IntOp, bit Commutable = 0> { 677 def v8i8 : N3VNInt<op24, op23, 0b00, op11_8, op4, !strconcat(OpcodeStr,"16"), 678 v8i8, v8i16, IntOp, Commutable>; 679 def v4i16 : N3VNInt<op24, op23, 0b01, op11_8, op4, !strconcat(OpcodeStr,"32"), 680 v4i16, v4i32, IntOp, Commutable>; 681 def v2i32 : N3VNInt<op24, op23, 0b10, op11_8, op4, !strconcat(OpcodeStr,"64"), 682 v2i32, v2i64, IntOp, Commutable>; 683} 684 685 686// Neon Long 3-register vector intrinsics. 687 688// First with only element sizes of 16 and 32 bits: 689multiclass N3VLInt_HS<bit op24, bit op23, bits<4> op11_8, bit op4, 690 string OpcodeStr, Intrinsic IntOp, bit Commutable = 0> { 691 def v4i32 : N3VLInt<op24, op23, 0b01, op11_8, op4, !strconcat(OpcodeStr,"16"), 692 v4i32, v4i16, IntOp, Commutable>; 693 def v2i64 : N3VLInt<op24, op23, 0b10, op11_8, op4, !strconcat(OpcodeStr,"32"), 694 v2i64, v2i32, IntOp, Commutable>; 695} 696 697// ....then also with element size of 8 bits: 698multiclass N3VLInt_QHS<bit op24, bit op23, bits<4> op11_8, bit op4, 699 string OpcodeStr, Intrinsic IntOp, bit Commutable = 0> 700 : N3VLInt_HS<op24, op23, op11_8, op4, OpcodeStr, IntOp, Commutable> { 701 def v8i16 : N3VLInt<op24, op23, 0b00, op11_8, op4, !strconcat(OpcodeStr, "8"), 702 v8i16, v8i8, IntOp, Commutable>; 703} 704 705 706// Neon Wide 3-register vector intrinsics, 707// source operand element sizes of 8, 16 and 32 bits: 708multiclass N3VWInt_QHS<bit op24, bit op23, bits<4> op11_8, bit op4, 709 string OpcodeStr, Intrinsic IntOp, bit Commutable = 0> { 710 def v8i16 : N3VWInt<op24, op23, 0b00, op11_8, op4, !strconcat(OpcodeStr, "8"), 711 v8i16, v8i8, IntOp, Commutable>; 712 def v4i32 : N3VWInt<op24, op23, 0b01, op11_8, op4, !strconcat(OpcodeStr,"16"), 713 v4i32, v4i16, IntOp, Commutable>; 714 def v2i64 : N3VWInt<op24, op23, 0b10, op11_8, op4, !strconcat(OpcodeStr,"32"), 715 v2i64, v2i32, IntOp, Commutable>; 716} 717 718 719// Neon Multiply-Op vector operations, 720// element sizes of 8, 16 and 32 bits: 721multiclass N3VMulOp_QHS<bit op24, bit op23, bits<4> op11_8, bit op4, 722 string OpcodeStr, SDNode OpNode> { 723 // 64-bit vector types. 724 def v8i8 : N3VDMulOp<op24, op23, 0b00, op11_8, op4, 725 !strconcat(OpcodeStr, "8"), v8i8, mul, OpNode>; 726 def v4i16 : N3VDMulOp<op24, op23, 0b01, op11_8, op4, 727 !strconcat(OpcodeStr, "16"), v4i16, mul, OpNode>; 728 def v2i32 : N3VDMulOp<op24, op23, 0b10, op11_8, op4, 729 !strconcat(OpcodeStr, "32"), v2i32, mul, OpNode>; 730 731 // 128-bit vector types. 732 def v16i8 : N3VQMulOp<op24, op23, 0b00, op11_8, op4, 733 !strconcat(OpcodeStr, "8"), v16i8, mul, OpNode>; 734 def v8i16 : N3VQMulOp<op24, op23, 0b01, op11_8, op4, 735 !strconcat(OpcodeStr, "16"), v8i16, mul, OpNode>; 736 def v4i32 : N3VQMulOp<op24, op23, 0b10, op11_8, op4, 737 !strconcat(OpcodeStr, "32"), v4i32, mul, OpNode>; 738} 739 740 741// Neon 3-argument intrinsics, 742// element sizes of 8, 16 and 32 bits: 743multiclass N3VInt3_QHS<bit op24, bit op23, bits<4> op11_8, bit op4, 744 string OpcodeStr, Intrinsic IntOp> { 745 // 64-bit vector types. 746 def v8i8 : N3VDInt3<op24, op23, 0b00, op11_8, op4, 747 !strconcat(OpcodeStr, "8"), v8i8, v8i8, IntOp>; 748 def v4i16 : N3VDInt3<op24, op23, 0b01, op11_8, op4, 749 !strconcat(OpcodeStr, "16"), v4i16, v4i16, IntOp>; 750 def v2i32 : N3VDInt3<op24, op23, 0b10, op11_8, op4, 751 !strconcat(OpcodeStr, "32"), v2i32, v2i32, IntOp>; 752 753 // 128-bit vector types. 754 def v16i8 : N3VQInt3<op24, op23, 0b00, op11_8, op4, 755 !strconcat(OpcodeStr, "8"), v16i8, v16i8, IntOp>; 756 def v8i16 : N3VQInt3<op24, op23, 0b01, op11_8, op4, 757 !strconcat(OpcodeStr, "16"), v8i16, v8i16, IntOp>; 758 def v4i32 : N3VQInt3<op24, op23, 0b10, op11_8, op4, 759 !strconcat(OpcodeStr, "32"), v4i32, v4i32, IntOp>; 760} 761 762 763// Neon Long 3-argument intrinsics. 764 765// First with only element sizes of 16 and 32 bits: 766multiclass N3VLInt3_HS<bit op24, bit op23, bits<4> op11_8, bit op4, 767 string OpcodeStr, Intrinsic IntOp> { 768 def v4i32 : N3VLInt3<op24, op23, 0b01, op11_8, op4, 769 !strconcat(OpcodeStr, "16"), v4i32, v4i16, IntOp>; 770 def v2i64 : N3VLInt3<op24, op23, 0b10, op11_8, op4, 771 !strconcat(OpcodeStr, "32"), v2i64, v2i32, IntOp>; 772} 773 774// ....then also with element size of 8 bits: 775multiclass N3VLInt3_QHS<bit op24, bit op23, bits<4> op11_8, bit op4, 776 string OpcodeStr, Intrinsic IntOp> 777 : N3VLInt3_HS<op24, op23, op11_8, op4, OpcodeStr, IntOp> { 778 def v8i16 : N3VLInt3<op24, op23, 0b01, op11_8, op4, 779 !strconcat(OpcodeStr, "8"), v8i16, v8i8, IntOp>; 780} 781 782 783// Neon 2-register vector intrinsics, 784// element sizes of 8, 16 and 32 bits: 785multiclass N2VInt_QHS<bits<2> op24_23, bits<2> op21_20, bits<2> op17_16, 786 bits<5> op11_7, bit op4, string OpcodeStr, 787 Intrinsic IntOp> { 788 // 64-bit vector types. 789 def v8i8 : N2VDInt<op24_23, op21_20, 0b00, op17_16, op11_7, op4, 790 !strconcat(OpcodeStr, "8"), v8i8, v8i8, IntOp>; 791 def v4i16 : N2VDInt<op24_23, op21_20, 0b01, op17_16, op11_7, op4, 792 !strconcat(OpcodeStr, "16"), v4i16, v4i16, IntOp>; 793 def v2i32 : N2VDInt<op24_23, op21_20, 0b10, op17_16, op11_7, op4, 794 !strconcat(OpcodeStr, "32"), v2i32, v2i32, IntOp>; 795 796 // 128-bit vector types. 797 def v16i8 : N2VQInt<op24_23, op21_20, 0b00, op17_16, op11_7, op4, 798 !strconcat(OpcodeStr, "8"), v16i8, v16i8, IntOp>; 799 def v8i16 : N2VQInt<op24_23, op21_20, 0b01, op17_16, op11_7, op4, 800 !strconcat(OpcodeStr, "16"), v8i16, v8i16, IntOp>; 801 def v4i32 : N2VQInt<op24_23, op21_20, 0b10, op17_16, op11_7, op4, 802 !strconcat(OpcodeStr, "32"), v4i32, v4i32, IntOp>; 803} 804 805 806// Neon Pairwise long 2-register intrinsics, 807// element sizes of 8, 16 and 32 bits: 808multiclass N2VPLInt_QHS<bits<2> op24_23, bits<2> op21_20, bits<2> op17_16, 809 bits<5> op11_7, bit op4, 810 string OpcodeStr, Intrinsic IntOp> { 811 // 64-bit vector types. 812 def v8i8 : N2VDPLInt<op24_23, op21_20, 0b00, op17_16, op11_7, op4, 813 !strconcat(OpcodeStr, "8"), v4i16, v8i8, IntOp>; 814 def v4i16 : N2VDPLInt<op24_23, op21_20, 0b01, op17_16, op11_7, op4, 815 !strconcat(OpcodeStr, "16"), v2i32, v4i16, IntOp>; 816 def v2i32 : N2VDPLInt<op24_23, op21_20, 0b10, op17_16, op11_7, op4, 817 !strconcat(OpcodeStr, "32"), v1i64, v2i32, IntOp>; 818 819 // 128-bit vector types. 820 def v16i8 : N2VQPLInt<op24_23, op21_20, 0b00, op17_16, op11_7, op4, 821 !strconcat(OpcodeStr, "8"), v8i16, v16i8, IntOp>; 822 def v8i16 : N2VQPLInt<op24_23, op21_20, 0b01, op17_16, op11_7, op4, 823 !strconcat(OpcodeStr, "16"), v4i32, v8i16, IntOp>; 824 def v4i32 : N2VQPLInt<op24_23, op21_20, 0b10, op17_16, op11_7, op4, 825 !strconcat(OpcodeStr, "32"), v2i64, v4i32, IntOp>; 826} 827 828 829// Neon Pairwise long 2-register accumulate intrinsics, 830// element sizes of 8, 16 and 32 bits: 831multiclass N2VPLInt2_QHS<bits<2> op24_23, bits<2> op21_20, bits<2> op17_16, 832 bits<5> op11_7, bit op4, 833 string OpcodeStr, Intrinsic IntOp> { 834 // 64-bit vector types. 835 def v8i8 : N2VDPLInt2<op24_23, op21_20, 0b00, op17_16, op11_7, op4, 836 !strconcat(OpcodeStr, "8"), v4i16, v8i8, IntOp>; 837 def v4i16 : N2VDPLInt2<op24_23, op21_20, 0b01, op17_16, op11_7, op4, 838 !strconcat(OpcodeStr, "16"), v2i32, v4i16, IntOp>; 839 def v2i32 : N2VDPLInt2<op24_23, op21_20, 0b10, op17_16, op11_7, op4, 840 !strconcat(OpcodeStr, "32"), v1i64, v2i32, IntOp>; 841 842 // 128-bit vector types. 843 def v16i8 : N2VQPLInt2<op24_23, op21_20, 0b00, op17_16, op11_7, op4, 844 !strconcat(OpcodeStr, "8"), v8i16, v16i8, IntOp>; 845 def v8i16 : N2VQPLInt2<op24_23, op21_20, 0b01, op17_16, op11_7, op4, 846 !strconcat(OpcodeStr, "16"), v4i32, v8i16, IntOp>; 847 def v4i32 : N2VQPLInt2<op24_23, op21_20, 0b10, op17_16, op11_7, op4, 848 !strconcat(OpcodeStr, "32"), v2i64, v4i32, IntOp>; 849} 850 851 852// Neon 2-register vector shift by immediate, 853// element sizes of 8, 16, 32 and 64 bits: 854multiclass N2VSh_QHSD<bit op24, bit op23, bits<4> op11_8, bit op4, 855 string OpcodeStr, SDNode OpNode> { 856 // 64-bit vector types. 857 def v8i8 : N2VDSh<op24, op23, 0b001000, op11_8, 0, op4, 858 !strconcat(OpcodeStr, "8"), v8i8, OpNode>; 859 def v4i16 : N2VDSh<op24, op23, 0b010000, op11_8, 0, op4, 860 !strconcat(OpcodeStr, "16"), v4i16, OpNode>; 861 def v2i32 : N2VDSh<op24, op23, 0b100000, op11_8, 0, op4, 862 !strconcat(OpcodeStr, "32"), v2i32, OpNode>; 863 def v1i64 : N2VDSh<op24, op23, 0b000000, op11_8, 1, op4, 864 !strconcat(OpcodeStr, "64"), v1i64, OpNode>; 865 866 // 128-bit vector types. 867 def v16i8 : N2VQSh<op24, op23, 0b001000, op11_8, 0, op4, 868 !strconcat(OpcodeStr, "8"), v16i8, OpNode>; 869 def v8i16 : N2VQSh<op24, op23, 0b010000, op11_8, 0, op4, 870 !strconcat(OpcodeStr, "16"), v8i16, OpNode>; 871 def v4i32 : N2VQSh<op24, op23, 0b100000, op11_8, 0, op4, 872 !strconcat(OpcodeStr, "32"), v4i32, OpNode>; 873 def v2i64 : N2VQSh<op24, op23, 0b000000, op11_8, 1, op4, 874 !strconcat(OpcodeStr, "64"), v2i64, OpNode>; 875} 876 877 878// Neon Shift-Accumulate vector operations, 879// element sizes of 8, 16, 32 and 64 bits: 880multiclass N2VShAdd_QHSD<bit op24, bit op23, bits<4> op11_8, bit op4, 881 string OpcodeStr, SDNode ShOp> { 882 // 64-bit vector types. 883 def v8i8 : N2VDShAdd<op24, op23, 0b001000, op11_8, 0, op4, 884 !strconcat(OpcodeStr, "8"), v8i8, ShOp>; 885 def v4i16 : N2VDShAdd<op24, op23, 0b010000, op11_8, 0, op4, 886 !strconcat(OpcodeStr, "16"), v4i16, ShOp>; 887 def v2i32 : N2VDShAdd<op24, op23, 0b100000, op11_8, 0, op4, 888 !strconcat(OpcodeStr, "32"), v2i32, ShOp>; 889 def v1i64 : N2VDShAdd<op24, op23, 0b000000, op11_8, 1, op4, 890 !strconcat(OpcodeStr, "64"), v1i64, ShOp>; 891 892 // 128-bit vector types. 893 def v16i8 : N2VQShAdd<op24, op23, 0b001000, op11_8, 0, op4, 894 !strconcat(OpcodeStr, "8"), v16i8, ShOp>; 895 def v8i16 : N2VQShAdd<op24, op23, 0b010000, op11_8, 0, op4, 896 !strconcat(OpcodeStr, "16"), v8i16, ShOp>; 897 def v4i32 : N2VQShAdd<op24, op23, 0b100000, op11_8, 0, op4, 898 !strconcat(OpcodeStr, "32"), v4i32, ShOp>; 899 def v2i64 : N2VQShAdd<op24, op23, 0b000000, op11_8, 1, op4, 900 !strconcat(OpcodeStr, "64"), v2i64, ShOp>; 901} 902 903 904// Neon Shift-Insert vector operations, 905// element sizes of 8, 16, 32 and 64 bits: 906multiclass N2VShIns_QHSD<bit op24, bit op23, bits<4> op11_8, bit op4, 907 string OpcodeStr, SDNode ShOp> { 908 // 64-bit vector types. 909 def v8i8 : N2VDShIns<op24, op23, 0b001000, op11_8, 0, op4, 910 !strconcat(OpcodeStr, "8"), v8i8, ShOp>; 911 def v4i16 : N2VDShIns<op24, op23, 0b010000, op11_8, 0, op4, 912 !strconcat(OpcodeStr, "16"), v4i16, ShOp>; 913 def v2i32 : N2VDShIns<op24, op23, 0b100000, op11_8, 0, op4, 914 !strconcat(OpcodeStr, "32"), v2i32, ShOp>; 915 def v1i64 : N2VDShIns<op24, op23, 0b000000, op11_8, 1, op4, 916 !strconcat(OpcodeStr, "64"), v1i64, ShOp>; 917 918 // 128-bit vector types. 919 def v16i8 : N2VQShIns<op24, op23, 0b001000, op11_8, 0, op4, 920 !strconcat(OpcodeStr, "8"), v16i8, ShOp>; 921 def v8i16 : N2VQShIns<op24, op23, 0b010000, op11_8, 0, op4, 922 !strconcat(OpcodeStr, "16"), v8i16, ShOp>; 923 def v4i32 : N2VQShIns<op24, op23, 0b100000, op11_8, 0, op4, 924 !strconcat(OpcodeStr, "32"), v4i32, ShOp>; 925 def v2i64 : N2VQShIns<op24, op23, 0b000000, op11_8, 1, op4, 926 !strconcat(OpcodeStr, "64"), v2i64, ShOp>; 927} 928 929//===----------------------------------------------------------------------===// 930// Instruction Definitions. 931//===----------------------------------------------------------------------===// 932 933// Vector Add Operations. 934 935// VADD : Vector Add (integer and floating-point) 936defm VADD : N3V_QHSD<0, 0, 0b1000, 0, "vadd.i", add, 1>; 937def VADDfd : N3VD<0, 0, 0b00, 0b1101, 0, "vadd.f32", v2f32, v2f32, fadd, 1>; 938def VADDfq : N3VQ<0, 0, 0b00, 0b1101, 0, "vadd.f32", v4f32, v4f32, fadd, 1>; 939// VADDL : Vector Add Long (Q = D + D) 940defm VADDLs : N3VLInt_QHS<0,1,0b0000,0, "vaddl.s", int_arm_neon_vaddls, 1>; 941defm VADDLu : N3VLInt_QHS<1,1,0b0000,0, "vaddl.u", int_arm_neon_vaddlu, 1>; 942// VADDW : Vector Add Wide (Q = Q + D) 943defm VADDWs : N3VWInt_QHS<0,1,0b0001,0, "vaddw.s", int_arm_neon_vaddws, 0>; 944defm VADDWu : N3VWInt_QHS<1,1,0b0001,0, "vaddw.u", int_arm_neon_vaddwu, 0>; 945// VHADD : Vector Halving Add 946defm VHADDs : N3VInt_QHS<0,0,0b0000,0, "vhadd.s", int_arm_neon_vhadds, 1>; 947defm VHADDu : N3VInt_QHS<1,0,0b0000,0, "vhadd.u", int_arm_neon_vhaddu, 1>; 948// VRHADD : Vector Rounding Halving Add 949defm VRHADDs : N3VInt_QHS<0,0,0b0001,0, "vrhadd.s", int_arm_neon_vrhadds, 1>; 950defm VRHADDu : N3VInt_QHS<1,0,0b0001,0, "vrhadd.u", int_arm_neon_vrhaddu, 1>; 951// VQADD : Vector Saturating Add 952defm VQADDs : N3VInt_QHSD<0,0,0b0000,1, "vqadd.s", int_arm_neon_vqadds, 1>; 953defm VQADDu : N3VInt_QHSD<1,0,0b0000,1, "vqadd.u", int_arm_neon_vqaddu, 1>; 954// VADDHN : Vector Add and Narrow Returning High Half (D = Q + Q) 955defm VADDHN : N3VNInt_HSD<0,1,0b0100,0, "vaddhn.i", int_arm_neon_vaddhn, 1>; 956// VRADDHN : Vector Rounding Add and Narrow Returning High Half (D = Q + Q) 957defm VRADDHN : N3VNInt_HSD<1,1,0b0100,0, "vraddhn.i", int_arm_neon_vraddhn, 1>; 958 959// Vector Add Operations used for single-precision FP 960def : N3VDs<fadd, VADDfd>; 961 962// Vector Multiply Operations. 963 964// VMUL : Vector Multiply (integer, polynomial and floating-point) 965defm VMUL : N3V_QHS<0, 0, 0b1001, 1, "vmul.i", mul, 1>; 966def VMULpd : N3VDInt<1, 0, 0b00, 0b1001, 1, "vmul.p8", v8i8, v8i8, 967 int_arm_neon_vmulp, 1>; 968def VMULpq : N3VQInt<1, 0, 0b00, 0b1001, 1, "vmul.p8", v16i8, v16i8, 969 int_arm_neon_vmulp, 1>; 970def VMULfd : N3VD<1, 0, 0b00, 0b1101, 1, "vmul.f32", v2f32, v2f32, fmul, 1>; 971def VMULfq : N3VQ<1, 0, 0b00, 0b1101, 1, "vmul.f32", v4f32, v4f32, fmul, 1>; 972// VQDMULH : Vector Saturating Doubling Multiply Returning High Half 973defm VQDMULH : N3VInt_HS<0,0,0b1011,0, "vqdmulh.s", int_arm_neon_vqdmulh, 1>; 974// VQRDMULH : Vector Rounding Saturating Doubling Multiply Returning High Half 975defm VQRDMULH : N3VInt_HS<1,0,0b1011,0, "vqrdmulh.s", int_arm_neon_vqrdmulh, 1>; 976// VMULL : Vector Multiply Long (integer and polynomial) (Q = D * D) 977defm VMULLs : N3VLInt_QHS<0,1,0b1100,0, "vmull.s", int_arm_neon_vmulls, 1>; 978defm VMULLu : N3VLInt_QHS<1,1,0b1100,0, "vmull.u", int_arm_neon_vmullu, 1>; 979def VMULLp : N3VLInt<0, 1, 0b00, 0b1110, 0, "vmull.p8", v8i16, v8i8, 980 int_arm_neon_vmullp, 1>; 981// VQDMULL : Vector Saturating Doubling Multiply Long (Q = D * D) 982defm VQDMULL : N3VLInt_HS<0,1,0b1101,0, "vqdmull.s", int_arm_neon_vqdmull, 1>; 983 984// Vector Multiply Operations used for single-precision FP 985def : N3VDs<fmul, VMULfd>; 986 987// Vector Multiply-Accumulate and Multiply-Subtract Operations. 988 989// VMLA : Vector Multiply Accumulate (integer and floating-point) 990defm VMLA : N3VMulOp_QHS<0, 0, 0b1001, 0, "vmla.i", add>; 991def VMLAfd : N3VDMulOp<0, 0, 0b00, 0b1101, 1, "vmla.f32", v2f32, fmul, fadd>; 992def VMLAfq : N3VQMulOp<0, 0, 0b00, 0b1101, 1, "vmla.f32", v4f32, fmul, fadd>; 993// VMLAL : Vector Multiply Accumulate Long (Q += D * D) 994defm VMLALs : N3VLInt3_QHS<0,1,0b1000,0, "vmlal.s", int_arm_neon_vmlals>; 995defm VMLALu : N3VLInt3_QHS<1,1,0b1000,0, "vmlal.u", int_arm_neon_vmlalu>; 996// VQDMLAL : Vector Saturating Doubling Multiply Accumulate Long (Q += D * D) 997defm VQDMLAL : N3VLInt3_HS<0, 1, 0b1001, 0, "vqdmlal.s", int_arm_neon_vqdmlal>; 998// VMLS : Vector Multiply Subtract (integer and floating-point) 999defm VMLS : N3VMulOp_QHS<0, 0, 0b1001, 0, "vmls.i", sub>; 1000def VMLSfd : N3VDMulOp<0, 0, 0b10, 0b1101, 1, "vmls.f32", v2f32, fmul, fsub>; 1001def VMLSfq : N3VQMulOp<0, 0, 0b10, 0b1101, 1, "vmls.f32", v4f32, fmul, fsub>; 1002// VMLSL : Vector Multiply Subtract Long (Q -= D * D) 1003defm VMLSLs : N3VLInt3_QHS<0,1,0b1010,0, "vmlsl.s", int_arm_neon_vmlsls>; 1004defm VMLSLu : N3VLInt3_QHS<1,1,0b1010,0, "vmlsl.u", int_arm_neon_vmlslu>; 1005// VQDMLSL : Vector Saturating Doubling Multiply Subtract Long (Q -= D * D) 1006defm VQDMLSL : N3VLInt3_HS<0, 1, 0b1011, 0, "vqdmlsl.s", int_arm_neon_vqdmlsl>; 1007 1008// Vector Multiply-Accumulate/Subtract used for single-precision FP 1009def : N3VDMulOps<fmul, fadd, VMLAfd>; 1010def : N3VDMulOps<fmul, fsub, VMLSfd>; 1011 1012// Vector Subtract Operations. 1013 1014// VSUB : Vector Subtract (integer and floating-point) 1015defm VSUB : N3V_QHSD<1, 0, 0b1000, 0, "vsub.i", sub, 0>; 1016def VSUBfd : N3VD<0, 0, 0b10, 0b1101, 0, "vsub.f32", v2f32, v2f32, fsub, 0>; 1017def VSUBfq : N3VQ<0, 0, 0b10, 0b1101, 0, "vsub.f32", v4f32, v4f32, fsub, 0>; 1018// VSUBL : Vector Subtract Long (Q = D - D) 1019defm VSUBLs : N3VLInt_QHS<0,1,0b0010,0, "vsubl.s", int_arm_neon_vsubls, 1>; 1020defm VSUBLu : N3VLInt_QHS<1,1,0b0010,0, "vsubl.u", int_arm_neon_vsublu, 1>; 1021// VSUBW : Vector Subtract Wide (Q = Q - D) 1022defm VSUBWs : N3VWInt_QHS<0,1,0b0011,0, "vsubw.s", int_arm_neon_vsubws, 0>; 1023defm VSUBWu : N3VWInt_QHS<1,1,0b0011,0, "vsubw.u", int_arm_neon_vsubwu, 0>; 1024// VHSUB : Vector Halving Subtract 1025defm VHSUBs : N3VInt_QHS<0, 0, 0b0010, 0, "vhsub.s", int_arm_neon_vhsubs, 0>; 1026defm VHSUBu : N3VInt_QHS<1, 0, 0b0010, 0, "vhsub.u", int_arm_neon_vhsubu, 0>; 1027// VQSUB : Vector Saturing Subtract 1028defm VQSUBs : N3VInt_QHSD<0, 0, 0b0010, 1, "vqsub.s", int_arm_neon_vqsubs, 0>; 1029defm VQSUBu : N3VInt_QHSD<1, 0, 0b0010, 1, "vqsub.u", int_arm_neon_vqsubu, 0>; 1030// VSUBHN : Vector Subtract and Narrow Returning High Half (D = Q - Q) 1031defm VSUBHN : N3VNInt_HSD<0,1,0b0110,0, "vsubhn.i", int_arm_neon_vsubhn, 0>; 1032// VRSUBHN : Vector Rounding Subtract and Narrow Returning High Half (D=Q-Q) 1033defm VRSUBHN : N3VNInt_HSD<1,1,0b0110,0, "vrsubhn.i", int_arm_neon_vrsubhn, 0>; 1034 1035// Vector Sub Operations used for single-precision FP 1036def : N3VDs<fsub, VSUBfd>; 1037 1038// Vector Comparisons. 1039 1040// VCEQ : Vector Compare Equal 1041defm VCEQ : N3V_QHS<1, 0, 0b1000, 1, "vceq.i", NEONvceq, 1>; 1042def VCEQfd : N3VD<0,0,0b00,0b1110,0, "vceq.f32", v2i32, v2f32, NEONvceq, 1>; 1043def VCEQfq : N3VQ<0,0,0b00,0b1110,0, "vceq.f32", v4i32, v4f32, NEONvceq, 1>; 1044// VCGE : Vector Compare Greater Than or Equal 1045defm VCGEs : N3V_QHS<0, 0, 0b0011, 1, "vcge.s", NEONvcge, 0>; 1046defm VCGEu : N3V_QHS<1, 0, 0b0011, 1, "vcge.u", NEONvcgeu, 0>; 1047def VCGEfd : N3VD<1,0,0b00,0b1110,0, "vcge.f32", v2i32, v2f32, NEONvcge, 0>; 1048def VCGEfq : N3VQ<1,0,0b00,0b1110,0, "vcge.f32", v4i32, v4f32, NEONvcge, 0>; 1049// VCGT : Vector Compare Greater Than 1050defm VCGTs : N3V_QHS<0, 0, 0b0011, 0, "vcgt.s", NEONvcgt, 0>; 1051defm VCGTu : N3V_QHS<1, 0, 0b0011, 0, "vcgt.u", NEONvcgtu, 0>; 1052def VCGTfd : N3VD<1,0,0b10,0b1110,0, "vcgt.f32", v2i32, v2f32, NEONvcgt, 0>; 1053def VCGTfq : N3VQ<1,0,0b10,0b1110,0, "vcgt.f32", v4i32, v4f32, NEONvcgt, 0>; 1054// VACGE : Vector Absolute Compare Greater Than or Equal (aka VCAGE) 1055def VACGEd : N3VDInt<1, 0, 0b00, 0b1110, 1, "vacge.f32", v2i32, v2f32, 1056 int_arm_neon_vacged, 0>; 1057def VACGEq : N3VQInt<1, 0, 0b00, 0b1110, 1, "vacge.f32", v4i32, v4f32, 1058 int_arm_neon_vacgeq, 0>; 1059// VACGT : Vector Absolute Compare Greater Than (aka VCAGT) 1060def VACGTd : N3VDInt<1, 0, 0b10, 0b1110, 1, "vacgt.f32", v2i32, v2f32, 1061 int_arm_neon_vacgtd, 0>; 1062def VACGTq : N3VQInt<1, 0, 0b10, 0b1110, 1, "vacgt.f32", v4i32, v4f32, 1063 int_arm_neon_vacgtq, 0>; 1064// VTST : Vector Test Bits 1065defm VTST : N3V_QHS<0, 0, 0b1000, 1, "vtst.i", NEONvtst, 1>; 1066 1067// Vector Bitwise Operations. 1068 1069// VAND : Vector Bitwise AND 1070def VANDd : N3VD<0, 0, 0b00, 0b0001, 1, "vand", v2i32, v2i32, and, 1>; 1071def VANDq : N3VQ<0, 0, 0b00, 0b0001, 1, "vand", v4i32, v4i32, and, 1>; 1072 1073// VEOR : Vector Bitwise Exclusive OR 1074def VEORd : N3VD<1, 0, 0b00, 0b0001, 1, "veor", v2i32, v2i32, xor, 1>; 1075def VEORq : N3VQ<1, 0, 0b00, 0b0001, 1, "veor", v4i32, v4i32, xor, 1>; 1076 1077// VORR : Vector Bitwise OR 1078def VORRd : N3VD<0, 0, 0b10, 0b0001, 1, "vorr", v2i32, v2i32, or, 1>; 1079def VORRq : N3VQ<0, 0, 0b10, 0b0001, 1, "vorr", v4i32, v4i32, or, 1>; 1080 1081// VBIC : Vector Bitwise Bit Clear (AND NOT) 1082def VBICd : N3V<0, 0, 0b01, 0b0001, 0, 1, (outs DPR:$dst), 1083 (ins DPR:$src1, DPR:$src2), "vbic\t$dst, $src1, $src2", "", 1084 [(set DPR:$dst, (v2i32 (and DPR:$src1,(vnot DPR:$src2))))]>; 1085def VBICq : N3V<0, 0, 0b01, 0b0001, 1, 1, (outs QPR:$dst), 1086 (ins QPR:$src1, QPR:$src2), "vbic\t$dst, $src1, $src2", "", 1087 [(set QPR:$dst, (v4i32 (and QPR:$src1,(vnot QPR:$src2))))]>; 1088 1089// VORN : Vector Bitwise OR NOT 1090def VORNd : N3V<0, 0, 0b11, 0b0001, 0, 1, (outs DPR:$dst), 1091 (ins DPR:$src1, DPR:$src2), "vorn\t$dst, $src1, $src2", "", 1092 [(set DPR:$dst, (v2i32 (or DPR:$src1, (vnot DPR:$src2))))]>; 1093def VORNq : N3V<0, 0, 0b11, 0b0001, 1, 1, (outs QPR:$dst), 1094 (ins QPR:$src1, QPR:$src2), "vorn\t$dst, $src1, $src2", "", 1095 [(set QPR:$dst, (v4i32 (or QPR:$src1, (vnot QPR:$src2))))]>; 1096 1097// VMVN : Vector Bitwise NOT 1098def VMVNd : N2V<0b11, 0b11, 0b00, 0b00, 0b01011, 0, 0, 1099 (outs DPR:$dst), (ins DPR:$src), "vmvn\t$dst, $src", "", 1100 [(set DPR:$dst, (v2i32 (vnot DPR:$src)))]>; 1101def VMVNq : N2V<0b11, 0b11, 0b00, 0b00, 0b01011, 1, 0, 1102 (outs QPR:$dst), (ins QPR:$src), "vmvn\t$dst, $src", "", 1103 [(set QPR:$dst, (v4i32 (vnot QPR:$src)))]>; 1104def : Pat<(v2i32 (vnot_conv DPR:$src)), (VMVNd DPR:$src)>; 1105def : Pat<(v4i32 (vnot_conv QPR:$src)), (VMVNq QPR:$src)>; 1106 1107// VBSL : Vector Bitwise Select 1108def VBSLd : N3V<1, 0, 0b01, 0b0001, 0, 1, (outs DPR:$dst), 1109 (ins DPR:$src1, DPR:$src2, DPR:$src3), 1110 "vbsl\t$dst, $src2, $src3", "$src1 = $dst", 1111 [(set DPR:$dst, 1112 (v2i32 (or (and DPR:$src2, DPR:$src1), 1113 (and DPR:$src3, (vnot DPR:$src1)))))]>; 1114def VBSLq : N3V<1, 0, 0b01, 0b0001, 1, 1, (outs QPR:$dst), 1115 (ins QPR:$src1, QPR:$src2, QPR:$src3), 1116 "vbsl\t$dst, $src2, $src3", "$src1 = $dst", 1117 [(set QPR:$dst, 1118 (v4i32 (or (and QPR:$src2, QPR:$src1), 1119 (and QPR:$src3, (vnot QPR:$src1)))))]>; 1120 1121// VBIF : Vector Bitwise Insert if False 1122// like VBSL but with: "vbif\t$dst, $src3, $src1", "$src2 = $dst", 1123// VBIT : Vector Bitwise Insert if True 1124// like VBSL but with: "vbit\t$dst, $src2, $src1", "$src3 = $dst", 1125// These are not yet implemented. The TwoAddress pass will not go looking 1126// for equivalent operations with different register constraints; it just 1127// inserts copies. 1128 1129// Vector Absolute Differences. 1130 1131// VABD : Vector Absolute Difference 1132defm VABDs : N3VInt_QHS<0, 0, 0b0111, 0, "vabd.s", int_arm_neon_vabds, 0>; 1133defm VABDu : N3VInt_QHS<1, 0, 0b0111, 0, "vabd.u", int_arm_neon_vabdu, 0>; 1134def VABDfd : N3VDInt<1, 0, 0b10, 0b1101, 0, "vabd.f32", v2f32, v2f32, 1135 int_arm_neon_vabdf, 0>; 1136def VABDfq : N3VQInt<1, 0, 0b10, 0b1101, 0, "vabd.f32", v4f32, v4f32, 1137 int_arm_neon_vabdf, 0>; 1138 1139// VABDL : Vector Absolute Difference Long (Q = | D - D |) 1140defm VABDLs : N3VLInt_QHS<0,1,0b0111,0, "vabdl.s", int_arm_neon_vabdls, 0>; 1141defm VABDLu : N3VLInt_QHS<1,1,0b0111,0, "vabdl.u", int_arm_neon_vabdlu, 0>; 1142 1143// VABA : Vector Absolute Difference and Accumulate 1144defm VABAs : N3VInt3_QHS<0,1,0b0101,0, "vaba.s", int_arm_neon_vabas>; 1145defm VABAu : N3VInt3_QHS<1,1,0b0101,0, "vaba.u", int_arm_neon_vabau>; 1146 1147// VABAL : Vector Absolute Difference and Accumulate Long (Q += | D - D |) 1148defm VABALs : N3VLInt3_QHS<0,1,0b0101,0, "vabal.s", int_arm_neon_vabals>; 1149defm VABALu : N3VLInt3_QHS<1,1,0b0101,0, "vabal.u", int_arm_neon_vabalu>; 1150 1151// Vector Maximum and Minimum. 1152 1153// VMAX : Vector Maximum 1154defm VMAXs : N3VInt_QHS<0, 0, 0b0110, 0, "vmax.s", int_arm_neon_vmaxs, 1>; 1155defm VMAXu : N3VInt_QHS<1, 0, 0b0110, 0, "vmax.u", int_arm_neon_vmaxu, 1>; 1156def VMAXfd : N3VDInt<0, 0, 0b00, 0b1111, 0, "vmax.f32", v2f32, v2f32, 1157 int_arm_neon_vmaxf, 1>; 1158def VMAXfq : N3VQInt<0, 0, 0b00, 0b1111, 0, "vmax.f32", v4f32, v4f32, 1159 int_arm_neon_vmaxf, 1>; 1160 1161// VMIN : Vector Minimum 1162defm VMINs : N3VInt_QHS<0, 0, 0b0110, 1, "vmin.s", int_arm_neon_vmins, 1>; 1163defm VMINu : N3VInt_QHS<1, 0, 0b0110, 1, "vmin.u", int_arm_neon_vminu, 1>; 1164def VMINfd : N3VDInt<0, 0, 0b10, 0b1111, 0, "vmin.f32", v2f32, v2f32, 1165 int_arm_neon_vminf, 1>; 1166def VMINfq : N3VQInt<0, 0, 0b10, 0b1111, 0, "vmin.f32", v4f32, v4f32, 1167 int_arm_neon_vminf, 1>; 1168 1169// Vector Pairwise Operations. 1170 1171// VPADD : Vector Pairwise Add 1172def VPADDi8 : N3VDInt<0, 0, 0b00, 0b1011, 1, "vpadd.i8", v8i8, v8i8, 1173 int_arm_neon_vpaddi, 0>; 1174def VPADDi16 : N3VDInt<0, 0, 0b01, 0b1011, 1, "vpadd.i16", v4i16, v4i16, 1175 int_arm_neon_vpaddi, 0>; 1176def VPADDi32 : N3VDInt<0, 0, 0b10, 0b1011, 1, "vpadd.i32", v2i32, v2i32, 1177 int_arm_neon_vpaddi, 0>; 1178def VPADDf : N3VDInt<1, 0, 0b00, 0b1101, 0, "vpadd.f32", v2f32, v2f32, 1179 int_arm_neon_vpaddf, 0>; 1180 1181// VPADDL : Vector Pairwise Add Long 1182defm VPADDLs : N2VPLInt_QHS<0b11, 0b11, 0b00, 0b00100, 0, "vpaddl.s", 1183 int_arm_neon_vpaddls>; 1184defm VPADDLu : N2VPLInt_QHS<0b11, 0b11, 0b00, 0b00101, 0, "vpaddl.u", 1185 int_arm_neon_vpaddlu>; 1186 1187// VPADAL : Vector Pairwise Add and Accumulate Long 1188defm VPADALs : N2VPLInt2_QHS<0b11, 0b11, 0b00, 0b00100, 0, "vpadal.s", 1189 int_arm_neon_vpadals>; 1190defm VPADALu : N2VPLInt2_QHS<0b11, 0b11, 0b00, 0b00101, 0, "vpadal.u", 1191 int_arm_neon_vpadalu>; 1192 1193// VPMAX : Vector Pairwise Maximum 1194def VPMAXs8 : N3VDInt<0, 0, 0b00, 0b1010, 0, "vpmax.s8", v8i8, v8i8, 1195 int_arm_neon_vpmaxs, 0>; 1196def VPMAXs16 : N3VDInt<0, 0, 0b01, 0b1010, 0, "vpmax.s16", v4i16, v4i16, 1197 int_arm_neon_vpmaxs, 0>; 1198def VPMAXs32 : N3VDInt<0, 0, 0b10, 0b1010, 0, "vpmax.s32", v2i32, v2i32, 1199 int_arm_neon_vpmaxs, 0>; 1200def VPMAXu8 : N3VDInt<1, 0, 0b00, 0b1010, 0, "vpmax.u8", v8i8, v8i8, 1201 int_arm_neon_vpmaxu, 0>; 1202def VPMAXu16 : N3VDInt<1, 0, 0b01, 0b1010, 0, "vpmax.u16", v4i16, v4i16, 1203 int_arm_neon_vpmaxu, 0>; 1204def VPMAXu32 : N3VDInt<1, 0, 0b10, 0b1010, 0, "vpmax.u32", v2i32, v2i32, 1205 int_arm_neon_vpmaxu, 0>; 1206def VPMAXf : N3VDInt<1, 0, 0b00, 0b1111, 0, "vpmax.f32", v2f32, v2f32, 1207 int_arm_neon_vpmaxf, 0>; 1208 1209// VPMIN : Vector Pairwise Minimum 1210def VPMINs8 : N3VDInt<0, 0, 0b00, 0b1010, 1, "vpmin.s8", v8i8, v8i8, 1211 int_arm_neon_vpmins, 0>; 1212def VPMINs16 : N3VDInt<0, 0, 0b01, 0b1010, 1, "vpmin.s16", v4i16, v4i16, 1213 int_arm_neon_vpmins, 0>; 1214def VPMINs32 : N3VDInt<0, 0, 0b10, 0b1010, 1, "vpmin.s32", v2i32, v2i32, 1215 int_arm_neon_vpmins, 0>; 1216def VPMINu8 : N3VDInt<1, 0, 0b00, 0b1010, 1, "vpmin.u8", v8i8, v8i8, 1217 int_arm_neon_vpminu, 0>; 1218def VPMINu16 : N3VDInt<1, 0, 0b01, 0b1010, 1, "vpmin.u16", v4i16, v4i16, 1219 int_arm_neon_vpminu, 0>; 1220def VPMINu32 : N3VDInt<1, 0, 0b10, 0b1010, 1, "vpmin.u32", v2i32, v2i32, 1221 int_arm_neon_vpminu, 0>; 1222def VPMINf : N3VDInt<1, 0, 0b10, 0b1111, 0, "vpmin.f32", v2f32, v2f32, 1223 int_arm_neon_vpminf, 0>; 1224 1225// Vector Reciprocal and Reciprocal Square Root Estimate and Step. 1226 1227// VRECPE : Vector Reciprocal Estimate 1228def VRECPEd : N2VDInt<0b11, 0b11, 0b10, 0b11, 0b01000, 0, "vrecpe.u32", 1229 v2i32, v2i32, int_arm_neon_vrecpe>; 1230def VRECPEq : N2VQInt<0b11, 0b11, 0b10, 0b11, 0b01000, 0, "vrecpe.u32", 1231 v4i32, v4i32, int_arm_neon_vrecpe>; 1232def VRECPEfd : N2VDInt<0b11, 0b11, 0b10, 0b11, 0b01010, 0, "vrecpe.f32", 1233 v2f32, v2f32, int_arm_neon_vrecpef>; 1234def VRECPEfq : N2VQInt<0b11, 0b11, 0b10, 0b11, 0b01010, 0, "vrecpe.f32", 1235 v4f32, v4f32, int_arm_neon_vrecpef>; 1236 1237// VRECPS : Vector Reciprocal Step 1238def VRECPSfd : N3VDInt<0, 0, 0b00, 0b1111, 1, "vrecps.f32", v2f32, v2f32, 1239 int_arm_neon_vrecps, 1>; 1240def VRECPSfq : N3VQInt<0, 0, 0b00, 0b1111, 1, "vrecps.f32", v4f32, v4f32, 1241 int_arm_neon_vrecps, 1>; 1242 1243// VRSQRTE : Vector Reciprocal Square Root Estimate 1244def VRSQRTEd : N2VDInt<0b11, 0b11, 0b10, 0b11, 0b01001, 0, "vrsqrte.u32", 1245 v2i32, v2i32, int_arm_neon_vrsqrte>; 1246def VRSQRTEq : N2VQInt<0b11, 0b11, 0b10, 0b11, 0b01001, 0, "vrsqrte.u32", 1247 v4i32, v4i32, int_arm_neon_vrsqrte>; 1248def VRSQRTEfd : N2VDInt<0b11, 0b11, 0b10, 0b11, 0b01011, 0, "vrsqrte.f32", 1249 v2f32, v2f32, int_arm_neon_vrsqrtef>; 1250def VRSQRTEfq : N2VQInt<0b11, 0b11, 0b10, 0b11, 0b01011, 0, "vrsqrte.f32", 1251 v4f32, v4f32, int_arm_neon_vrsqrtef>; 1252 1253// VRSQRTS : Vector Reciprocal Square Root Step 1254def VRSQRTSfd : N3VDInt<0, 0, 0b10, 0b1111, 1, "vrsqrts.f32", v2f32, v2f32, 1255 int_arm_neon_vrsqrts, 1>; 1256def VRSQRTSfq : N3VQInt<0, 0, 0b10, 0b1111, 1, "vrsqrts.f32", v4f32, v4f32, 1257 int_arm_neon_vrsqrts, 1>; 1258 1259// Vector Shifts. 1260 1261// VSHL : Vector Shift 1262defm VSHLs : N3VInt_QHSD<0, 0, 0b0100, 0, "vshl.s", int_arm_neon_vshifts, 0>; 1263defm VSHLu : N3VInt_QHSD<1, 0, 0b0100, 0, "vshl.u", int_arm_neon_vshiftu, 0>; 1264// VSHL : Vector Shift Left (Immediate) 1265defm VSHLi : N2VSh_QHSD<0, 1, 0b0111, 1, "vshl.i", NEONvshl>; 1266// VSHR : Vector Shift Right (Immediate) 1267defm VSHRs : N2VSh_QHSD<0, 1, 0b0000, 1, "vshr.s", NEONvshrs>; 1268defm VSHRu : N2VSh_QHSD<1, 1, 0b0000, 1, "vshr.u", NEONvshru>; 1269 1270// VSHLL : Vector Shift Left Long 1271def VSHLLs8 : N2VLSh<0, 1, 0b001000, 0b1010, 0, 0, 1, "vshll.s8", 1272 v8i16, v8i8, NEONvshlls>; 1273def VSHLLs16 : N2VLSh<0, 1, 0b010000, 0b1010, 0, 0, 1, "vshll.s16", 1274 v4i32, v4i16, NEONvshlls>; 1275def VSHLLs32 : N2VLSh<0, 1, 0b100000, 0b1010, 0, 0, 1, "vshll.s32", 1276 v2i64, v2i32, NEONvshlls>; 1277def VSHLLu8 : N2VLSh<1, 1, 0b001000, 0b1010, 0, 0, 1, "vshll.u8", 1278 v8i16, v8i8, NEONvshllu>; 1279def VSHLLu16 : N2VLSh<1, 1, 0b010000, 0b1010, 0, 0, 1, "vshll.u16", 1280 v4i32, v4i16, NEONvshllu>; 1281def VSHLLu32 : N2VLSh<1, 1, 0b100000, 0b1010, 0, 0, 1, "vshll.u32", 1282 v2i64, v2i32, NEONvshllu>; 1283 1284// VSHLL : Vector Shift Left Long (with maximum shift count) 1285def VSHLLi8 : N2VLSh<1, 1, 0b110010, 0b0011, 0, 0, 0, "vshll.i8", 1286 v8i16, v8i8, NEONvshlli>; 1287def VSHLLi16 : N2VLSh<1, 1, 0b110110, 0b0011, 0, 0, 0, "vshll.i16", 1288 v4i32, v4i16, NEONvshlli>; 1289def VSHLLi32 : N2VLSh<1, 1, 0b111010, 0b0011, 0, 0, 0, "vshll.i32", 1290 v2i64, v2i32, NEONvshlli>; 1291 1292// VSHRN : Vector Shift Right and Narrow 1293def VSHRN16 : N2VNSh<0, 1, 0b001000, 0b1000, 0, 0, 1, "vshrn.i16", 1294 v8i8, v8i16, NEONvshrn>; 1295def VSHRN32 : N2VNSh<0, 1, 0b010000, 0b1000, 0, 0, 1, "vshrn.i32", 1296 v4i16, v4i32, NEONvshrn>; 1297def VSHRN64 : N2VNSh<0, 1, 0b100000, 0b1000, 0, 0, 1, "vshrn.i64", 1298 v2i32, v2i64, NEONvshrn>; 1299 1300// VRSHL : Vector Rounding Shift 1301defm VRSHLs : N3VInt_QHSD<0,0,0b0101,0, "vrshl.s", int_arm_neon_vrshifts, 0>; 1302defm VRSHLu : N3VInt_QHSD<1,0,0b0101,0, "vrshl.u", int_arm_neon_vrshiftu, 0>; 1303// VRSHR : Vector Rounding Shift Right 1304defm VRSHRs : N2VSh_QHSD<0, 1, 0b0010, 1, "vrshr.s", NEONvrshrs>; 1305defm VRSHRu : N2VSh_QHSD<1, 1, 0b0010, 1, "vrshr.u", NEONvrshru>; 1306 1307// VRSHRN : Vector Rounding Shift Right and Narrow 1308def VRSHRN16 : N2VNSh<0, 1, 0b001000, 0b1000, 0, 1, 1, "vrshrn.i16", 1309 v8i8, v8i16, NEONvrshrn>; 1310def VRSHRN32 : N2VNSh<0, 1, 0b010000, 0b1000, 0, 1, 1, "vrshrn.i32", 1311 v4i16, v4i32, NEONvrshrn>; 1312def VRSHRN64 : N2VNSh<0, 1, 0b100000, 0b1000, 0, 1, 1, "vrshrn.i64", 1313 v2i32, v2i64, NEONvrshrn>; 1314 1315// VQSHL : Vector Saturating Shift 1316defm VQSHLs : N3VInt_QHSD<0,0,0b0100,1, "vqshl.s", int_arm_neon_vqshifts, 0>; 1317defm VQSHLu : N3VInt_QHSD<1,0,0b0100,1, "vqshl.u", int_arm_neon_vqshiftu, 0>; 1318// VQSHL : Vector Saturating Shift Left (Immediate) 1319defm VQSHLsi : N2VSh_QHSD<0, 1, 0b0111, 1, "vqshl.s", NEONvqshls>; 1320defm VQSHLui : N2VSh_QHSD<1, 1, 0b0111, 1, "vqshl.u", NEONvqshlu>; 1321// VQSHLU : Vector Saturating Shift Left (Immediate, Unsigned) 1322defm VQSHLsu : N2VSh_QHSD<1, 1, 0b0110, 1, "vqshlu.s", NEONvqshlsu>; 1323 1324// VQSHRN : Vector Saturating Shift Right and Narrow 1325def VQSHRNs16 : N2VNSh<0, 1, 0b001000, 0b1001, 0, 0, 1, "vqshrn.s16", 1326 v8i8, v8i16, NEONvqshrns>; 1327def VQSHRNs32 : N2VNSh<0, 1, 0b010000, 0b1001, 0, 0, 1, "vqshrn.s32", 1328 v4i16, v4i32, NEONvqshrns>; 1329def VQSHRNs64 : N2VNSh<0, 1, 0b100000, 0b1001, 0, 0, 1, "vqshrn.s64", 1330 v2i32, v2i64, NEONvqshrns>; 1331def VQSHRNu16 : N2VNSh<1, 1, 0b001000, 0b1001, 0, 0, 1, "vqshrn.u16", 1332 v8i8, v8i16, NEONvqshrnu>; 1333def VQSHRNu32 : N2VNSh<1, 1, 0b010000, 0b1001, 0, 0, 1, "vqshrn.u32", 1334 v4i16, v4i32, NEONvqshrnu>; 1335def VQSHRNu64 : N2VNSh<1, 1, 0b100000, 0b1001, 0, 0, 1, "vqshrn.u64", 1336 v2i32, v2i64, NEONvqshrnu>; 1337 1338// VQSHRUN : Vector Saturating Shift Right and Narrow (Unsigned) 1339def VQSHRUN16 : N2VNSh<1, 1, 0b001000, 0b1000, 0, 0, 1, "vqshrun.s16", 1340 v8i8, v8i16, NEONvqshrnsu>; 1341def VQSHRUN32 : N2VNSh<1, 1, 0b010000, 0b1000, 0, 0, 1, "vqshrun.s32", 1342 v4i16, v4i32, NEONvqshrnsu>; 1343def VQSHRUN64 : N2VNSh<1, 1, 0b100000, 0b1000, 0, 0, 1, "vqshrun.s64", 1344 v2i32, v2i64, NEONvqshrnsu>; 1345 1346// VQRSHL : Vector Saturating Rounding Shift 1347defm VQRSHLs : N3VInt_QHSD<0, 0, 0b0101, 1, "vqrshl.s", 1348 int_arm_neon_vqrshifts, 0>; 1349defm VQRSHLu : N3VInt_QHSD<1, 0, 0b0101, 1, "vqrshl.u", 1350 int_arm_neon_vqrshiftu, 0>; 1351 1352// VQRSHRN : Vector Saturating Rounding Shift Right and Narrow 1353def VQRSHRNs16: N2VNSh<0, 1, 0b001000, 0b1001, 0, 1, 1, "vqrshrn.s16", 1354 v8i8, v8i16, NEONvqrshrns>; 1355def VQRSHRNs32: N2VNSh<0, 1, 0b010000, 0b1001, 0, 1, 1, "vqrshrn.s32", 1356 v4i16, v4i32, NEONvqrshrns>; 1357def VQRSHRNs64: N2VNSh<0, 1, 0b100000, 0b1001, 0, 1, 1, "vqrshrn.s64", 1358 v2i32, v2i64, NEONvqrshrns>; 1359def VQRSHRNu16: N2VNSh<1, 1, 0b001000, 0b1001, 0, 1, 1, "vqrshrn.u16", 1360 v8i8, v8i16, NEONvqrshrnu>; 1361def VQRSHRNu32: N2VNSh<1, 1, 0b010000, 0b1001, 0, 1, 1, "vqrshrn.u32", 1362 v4i16, v4i32, NEONvqrshrnu>; 1363def VQRSHRNu64: N2VNSh<1, 1, 0b100000, 0b1001, 0, 1, 1, "vqrshrn.u64", 1364 v2i32, v2i64, NEONvqrshrnu>; 1365 1366// VQRSHRUN : Vector Saturating Rounding Shift Right and Narrow (Unsigned) 1367def VQRSHRUN16: N2VNSh<1, 1, 0b001000, 0b1000, 0, 1, 1, "vqrshrun.s16", 1368 v8i8, v8i16, NEONvqrshrnsu>; 1369def VQRSHRUN32: N2VNSh<1, 1, 0b010000, 0b1000, 0, 1, 1, "vqrshrun.s32", 1370 v4i16, v4i32, NEONvqrshrnsu>; 1371def VQRSHRUN64: N2VNSh<1, 1, 0b100000, 0b1000, 0, 1, 1, "vqrshrun.s64", 1372 v2i32, v2i64, NEONvqrshrnsu>; 1373 1374// VSRA : Vector Shift Right and Accumulate 1375defm VSRAs : N2VShAdd_QHSD<0, 1, 0b0001, 1, "vsra.s", NEONvshrs>; 1376defm VSRAu : N2VShAdd_QHSD<1, 1, 0b0001, 1, "vsra.u", NEONvshru>; 1377// VRSRA : Vector Rounding Shift Right and Accumulate 1378defm VRSRAs : N2VShAdd_QHSD<0, 1, 0b0011, 1, "vrsra.s", NEONvrshrs>; 1379defm VRSRAu : N2VShAdd_QHSD<1, 1, 0b0011, 1, "vrsra.u", NEONvrshru>; 1380 1381// VSLI : Vector Shift Left and Insert 1382defm VSLI : N2VShIns_QHSD<1, 1, 0b0101, 1, "vsli.", NEONvsli>; 1383// VSRI : Vector Shift Right and Insert 1384defm VSRI : N2VShIns_QHSD<1, 1, 0b0100, 1, "vsri.", NEONvsri>; 1385 1386// Vector Absolute and Saturating Absolute. 1387 1388// VABS : Vector Absolute Value 1389defm VABS : N2VInt_QHS<0b11, 0b11, 0b01, 0b00110, 0, "vabs.s", 1390 int_arm_neon_vabs>; 1391def VABSfd : N2VDInt<0b11, 0b11, 0b10, 0b01, 0b01110, 0, "vabs.f32", 1392 v2f32, v2f32, int_arm_neon_vabsf>; 1393def VABSfq : N2VQInt<0b11, 0b11, 0b10, 0b01, 0b01110, 0, "vabs.f32", 1394 v4f32, v4f32, int_arm_neon_vabsf>; 1395def : N2VDInts<fabs, VABSfd>; 1396 1397// VQABS : Vector Saturating Absolute Value 1398defm VQABS : N2VInt_QHS<0b11, 0b11, 0b00, 0b01110, 0, "vqabs.s", 1399 int_arm_neon_vqabs>; 1400 1401// Vector Negate. 1402 1403def vneg : PatFrag<(ops node:$in), (sub immAllZerosV, node:$in)>; 1404def vneg_conv : PatFrag<(ops node:$in), (sub immAllZerosV_bc, node:$in)>; 1405 1406class VNEGD<bits<2> size, string OpcodeStr, ValueType Ty> 1407 : N2V<0b11, 0b11, size, 0b01, 0b00111, 0, 0, (outs DPR:$dst), (ins DPR:$src), 1408 !strconcat(OpcodeStr, "\t$dst, $src"), "", 1409 [(set DPR:$dst, (Ty (vneg DPR:$src)))]>; 1410class VNEGQ<bits<2> size, string OpcodeStr, ValueType Ty> 1411 : N2V<0b11, 0b11, size, 0b01, 0b00111, 1, 0, (outs QPR:$dst), (ins QPR:$src), 1412 !strconcat(OpcodeStr, "\t$dst, $src"), "", 1413 [(set QPR:$dst, (Ty (vneg QPR:$src)))]>; 1414 1415// VNEG : Vector Negate 1416def VNEGs8d : VNEGD<0b00, "vneg.s8", v8i8>; 1417def VNEGs16d : VNEGD<0b01, "vneg.s16", v4i16>; 1418def VNEGs32d : VNEGD<0b10, "vneg.s32", v2i32>; 1419def VNEGs8q : VNEGQ<0b00, "vneg.s8", v16i8>; 1420def VNEGs16q : VNEGQ<0b01, "vneg.s16", v8i16>; 1421def VNEGs32q : VNEGQ<0b10, "vneg.s32", v4i32>; 1422 1423// VNEG : Vector Negate (floating-point) 1424def VNEGf32d : N2V<0b11, 0b11, 0b10, 0b01, 0b01111, 0, 0, 1425 (outs DPR:$dst), (ins DPR:$src), "vneg.f32\t$dst, $src", "", 1426 [(set DPR:$dst, (v2f32 (fneg DPR:$src)))]>; 1427def VNEGf32q : N2V<0b11, 0b11, 0b10, 0b01, 0b01111, 1, 0, 1428 (outs QPR:$dst), (ins QPR:$src), "vneg.f32\t$dst, $src", "", 1429 [(set QPR:$dst, (v4f32 (fneg QPR:$src)))]>; 1430def : N2VDInts<fneg, VNEGf32d>; 1431 1432def : Pat<(v8i8 (vneg_conv DPR:$src)), (VNEGs8d DPR:$src)>; 1433def : Pat<(v4i16 (vneg_conv DPR:$src)), (VNEGs16d DPR:$src)>; 1434def : Pat<(v2i32 (vneg_conv DPR:$src)), (VNEGs32d DPR:$src)>; 1435def : Pat<(v16i8 (vneg_conv QPR:$src)), (VNEGs8q QPR:$src)>; 1436def : Pat<(v8i16 (vneg_conv QPR:$src)), (VNEGs16q QPR:$src)>; 1437def : Pat<(v4i32 (vneg_conv QPR:$src)), (VNEGs32q QPR:$src)>; 1438 1439// VQNEG : Vector Saturating Negate 1440defm VQNEG : N2VInt_QHS<0b11, 0b11, 0b00, 0b01111, 0, "vqneg.s", 1441 int_arm_neon_vqneg>; 1442 1443// Vector Bit Counting Operations. 1444 1445// VCLS : Vector Count Leading Sign Bits 1446defm VCLS : N2VInt_QHS<0b11, 0b11, 0b00, 0b01000, 0, "vcls.s", 1447 int_arm_neon_vcls>; 1448// VCLZ : Vector Count Leading Zeros 1449defm VCLZ : N2VInt_QHS<0b11, 0b11, 0b00, 0b01001, 0, "vclz.i", 1450 int_arm_neon_vclz>; 1451// VCNT : Vector Count One Bits 1452def VCNTd : N2VDInt<0b11, 0b11, 0b00, 0b00, 0b01010, 0, "vcnt.8", 1453 v8i8, v8i8, int_arm_neon_vcnt>; 1454def VCNTq : N2VQInt<0b11, 0b11, 0b00, 0b00, 0b01010, 0, "vcnt.8", 1455 v16i8, v16i8, int_arm_neon_vcnt>; 1456 1457// Vector Move Operations. 1458 1459// VMOV : Vector Move (Register) 1460 1461def VMOVD : N3V<0, 0, 0b10, 0b0001, 0, 1, (outs DPR:$dst), (ins DPR:$src), 1462 "vmov\t$dst, $src", "", []>; 1463def VMOVQ : N3V<0, 0, 0b10, 0b0001, 1, 1, (outs QPR:$dst), (ins QPR:$src), 1464 "vmov\t$dst, $src", "", []>; 1465 1466// VMOV : Vector Move (Immediate) 1467 1468// VMOV_get_imm8 xform function: convert build_vector to VMOV.i8 imm. 1469def VMOV_get_imm8 : SDNodeXForm<build_vector, [{ 1470 return ARM::getVMOVImm(N, 1, *CurDAG); 1471}]>; 1472def vmovImm8 : PatLeaf<(build_vector), [{ 1473 return ARM::getVMOVImm(N, 1, *CurDAG).getNode() != 0; 1474}], VMOV_get_imm8>; 1475 1476// VMOV_get_imm16 xform function: convert build_vector to VMOV.i16 imm. 1477def VMOV_get_imm16 : SDNodeXForm<build_vector, [{ 1478 return ARM::getVMOVImm(N, 2, *CurDAG); 1479}]>; 1480def vmovImm16 : PatLeaf<(build_vector), [{ 1481 return ARM::getVMOVImm(N, 2, *CurDAG).getNode() != 0; 1482}], VMOV_get_imm16>; 1483 1484// VMOV_get_imm32 xform function: convert build_vector to VMOV.i32 imm. 1485def VMOV_get_imm32 : SDNodeXForm<build_vector, [{ 1486 return ARM::getVMOVImm(N, 4, *CurDAG); 1487}]>; 1488def vmovImm32 : PatLeaf<(build_vector), [{ 1489 return ARM::getVMOVImm(N, 4, *CurDAG).getNode() != 0; 1490}], VMOV_get_imm32>; 1491 1492// VMOV_get_imm64 xform function: convert build_vector to VMOV.i64 imm. 1493def VMOV_get_imm64 : SDNodeXForm<build_vector, [{ 1494 return ARM::getVMOVImm(N, 8, *CurDAG); 1495}]>; 1496def vmovImm64 : PatLeaf<(build_vector), [{ 1497 return ARM::getVMOVImm(N, 8, *CurDAG).getNode() != 0; 1498}], VMOV_get_imm64>; 1499 1500// Note: Some of the cmode bits in the following VMOV instructions need to 1501// be encoded based on the immed values. 1502 1503def VMOVv8i8 : N1ModImm<1, 0b000, 0b1110, 0, 0, 0, 1, (outs DPR:$dst), 1504 (ins i8imm:$SIMM), "vmov.i8\t$dst, $SIMM", "", 1505 [(set DPR:$dst, (v8i8 vmovImm8:$SIMM))]>; 1506def VMOVv16i8 : N1ModImm<1, 0b000, 0b1110, 0, 1, 0, 1, (outs QPR:$dst), 1507 (ins i8imm:$SIMM), "vmov.i8\t$dst, $SIMM", "", 1508 [(set QPR:$dst, (v16i8 vmovImm8:$SIMM))]>; 1509 1510def VMOVv4i16 : N1ModImm<1, 0b000, 0b1000, 0, 0, 0, 1, (outs DPR:$dst), 1511 (ins i16imm:$SIMM), "vmov.i16\t$dst, $SIMM", "", 1512 [(set DPR:$dst, (v4i16 vmovImm16:$SIMM))]>; 1513def VMOVv8i16 : N1ModImm<1, 0b000, 0b1000, 0, 1, 0, 1, (outs QPR:$dst), 1514 (ins i16imm:$SIMM), "vmov.i16\t$dst, $SIMM", "", 1515 [(set QPR:$dst, (v8i16 vmovImm16:$SIMM))]>; 1516 1517def VMOVv2i32 : N1ModImm<1, 0b000, 0b0000, 0, 0, 0, 1, (outs DPR:$dst), 1518 (ins i32imm:$SIMM), "vmov.i32\t$dst, $SIMM", "", 1519 [(set DPR:$dst, (v2i32 vmovImm32:$SIMM))]>; 1520def VMOVv4i32 : N1ModImm<1, 0b000, 0b0000, 0, 1, 0, 1, (outs QPR:$dst), 1521 (ins i32imm:$SIMM), "vmov.i32\t$dst, $SIMM", "", 1522 [(set QPR:$dst, (v4i32 vmovImm32:$SIMM))]>; 1523 1524def VMOVv1i64 : N1ModImm<1, 0b000, 0b1110, 0, 0, 1, 1, (outs DPR:$dst), 1525 (ins i64imm:$SIMM), "vmov.i64\t$dst, $SIMM", "", 1526 [(set DPR:$dst, (v1i64 vmovImm64:$SIMM))]>; 1527def VMOVv2i64 : N1ModImm<1, 0b000, 0b1110, 0, 1, 1, 1, (outs QPR:$dst), 1528 (ins i64imm:$SIMM), "vmov.i64\t$dst, $SIMM", "", 1529 [(set QPR:$dst, (v2i64 vmovImm64:$SIMM))]>; 1530 1531// VMOV : Vector Get Lane (move scalar to ARM core register) 1532 1533def VGETLNs8 : NVGetLane<0b11100101, 0b1011, 0b00, 1534 (outs GPR:$dst), (ins DPR:$src, i32imm:$lane), 1535 "vmov", ".s8\t$dst, $src[$lane]", 1536 [(set GPR:$dst, (NEONvgetlanes (v8i8 DPR:$src), 1537 imm:$lane))]>; 1538def VGETLNs16 : NVGetLane<0b11100001, 0b1011, 0b01, 1539 (outs GPR:$dst), (ins DPR:$src, i32imm:$lane), 1540 "vmov", ".s16\t$dst, $src[$lane]", 1541 [(set GPR:$dst, (NEONvgetlanes (v4i16 DPR:$src), 1542 imm:$lane))]>; 1543def VGETLNu8 : NVGetLane<0b11101101, 0b1011, 0b00, 1544 (outs GPR:$dst), (ins DPR:$src, i32imm:$lane), 1545 "vmov", ".u8\t$dst, $src[$lane]", 1546 [(set GPR:$dst, (NEONvgetlaneu (v8i8 DPR:$src), 1547 imm:$lane))]>; 1548def VGETLNu16 : NVGetLane<0b11101001, 0b1011, 0b01, 1549 (outs GPR:$dst), (ins DPR:$src, i32imm:$lane), 1550 "vmov", ".u16\t$dst, $src[$lane]", 1551 [(set GPR:$dst, (NEONvgetlaneu (v4i16 DPR:$src), 1552 imm:$lane))]>; 1553def VGETLNi32 : NVGetLane<0b11100001, 0b1011, 0b00, 1554 (outs GPR:$dst), (ins DPR:$src, i32imm:$lane), 1555 "vmov", ".32\t$dst, $src[$lane]", 1556 [(set GPR:$dst, (extractelt (v2i32 DPR:$src), 1557 imm:$lane))]>; 1558// def VGETLNf32: see FMRDH and FMRDL in ARMInstrVFP.td 1559def : Pat<(NEONvgetlanes (v16i8 QPR:$src), imm:$lane), 1560 (VGETLNs8 (v8i8 (EXTRACT_SUBREG QPR:$src, 1561 (SubReg_i8_reg imm:$lane))), 1562 (SubReg_i8_lane imm:$lane))>; 1563def : Pat<(NEONvgetlanes (v8i16 QPR:$src), imm:$lane), 1564 (VGETLNs16 (v4i16 (EXTRACT_SUBREG QPR:$src, 1565 (SubReg_i16_reg imm:$lane))), 1566 (SubReg_i16_lane imm:$lane))>; 1567def : Pat<(NEONvgetlaneu (v16i8 QPR:$src), imm:$lane), 1568 (VGETLNu8 (v8i8 (EXTRACT_SUBREG QPR:$src, 1569 (SubReg_i8_reg imm:$lane))), 1570 (SubReg_i8_lane imm:$lane))>; 1571def : Pat<(NEONvgetlaneu (v8i16 QPR:$src), imm:$lane), 1572 (VGETLNu16 (v4i16 (EXTRACT_SUBREG QPR:$src, 1573 (SubReg_i16_reg imm:$lane))), 1574 (SubReg_i16_lane imm:$lane))>; 1575def : Pat<(extractelt (v4i32 QPR:$src), imm:$lane), 1576 (VGETLNi32 (v2i32 (EXTRACT_SUBREG QPR:$src, 1577 (SubReg_i32_reg imm:$lane))), 1578 (SubReg_i32_lane imm:$lane))>; 1579//def : Pat<(extractelt (v2i64 QPR:$src1), imm:$src2), 1580// (EXTRACT_SUBREG QPR:$src1, (SubReg_f64_reg imm:$src2))>; 1581def : Pat<(extractelt (v2f64 QPR:$src1), imm:$src2), 1582 (EXTRACT_SUBREG QPR:$src1, (SubReg_f64_reg imm:$src2))>; 1583 1584 1585// VMOV : Vector Set Lane (move ARM core register to scalar) 1586 1587let Constraints = "$src1 = $dst" in { 1588def VSETLNi8 : NVSetLane<0b11100100, 0b1011, 0b00, (outs DPR:$dst), 1589 (ins DPR:$src1, GPR:$src2, i32imm:$lane), 1590 "vmov", ".8\t$dst[$lane], $src2", 1591 [(set DPR:$dst, (vector_insert (v8i8 DPR:$src1), 1592 GPR:$src2, imm:$lane))]>; 1593def VSETLNi16 : NVSetLane<0b11100000, 0b1011, 0b01, (outs DPR:$dst), 1594 (ins DPR:$src1, GPR:$src2, i32imm:$lane), 1595 "vmov", ".16\t$dst[$lane], $src2", 1596 [(set DPR:$dst, (vector_insert (v4i16 DPR:$src1), 1597 GPR:$src2, imm:$lane))]>; 1598def VSETLNi32 : NVSetLane<0b11100000, 0b1011, 0b00, (outs DPR:$dst), 1599 (ins DPR:$src1, GPR:$src2, i32imm:$lane), 1600 "vmov", ".32\t$dst[$lane], $src2", 1601 [(set DPR:$dst, (insertelt (v2i32 DPR:$src1), 1602 GPR:$src2, imm:$lane))]>; 1603} 1604def : Pat<(vector_insert (v16i8 QPR:$src1), GPR:$src2, imm:$lane), 1605 (v16i8 (INSERT_SUBREG QPR:$src1, 1606 (VSETLNi8 (v8i8 (EXTRACT_SUBREG QPR:$src1, 1607 (SubReg_i8_reg imm:$lane))), 1608 GPR:$src2, (SubReg_i8_lane imm:$lane)), 1609 (SubReg_i8_reg imm:$lane)))>; 1610def : Pat<(vector_insert (v8i16 QPR:$src1), GPR:$src2, imm:$lane), 1611 (v8i16 (INSERT_SUBREG QPR:$src1, 1612 (VSETLNi16 (v4i16 (EXTRACT_SUBREG QPR:$src1, 1613 (SubReg_i16_reg imm:$lane))), 1614 GPR:$src2, (SubReg_i16_lane imm:$lane)), 1615 (SubReg_i16_reg imm:$lane)))>; 1616def : Pat<(insertelt (v4i32 QPR:$src1), GPR:$src2, imm:$lane), 1617 (v4i32 (INSERT_SUBREG QPR:$src1, 1618 (VSETLNi32 (v2i32 (EXTRACT_SUBREG QPR:$src1, 1619 (SubReg_i32_reg imm:$lane))), 1620 GPR:$src2, (SubReg_i32_lane imm:$lane)), 1621 (SubReg_i32_reg imm:$lane)))>; 1622 1623//def : Pat<(v2i64 (insertelt QPR:$src1, DPR:$src2, imm:$src3)), 1624// (INSERT_SUBREG QPR:$src1, DPR:$src2, (SubReg_f64_reg imm:$src3))>; 1625def : Pat<(v2f64 (insertelt QPR:$src1, DPR:$src2, imm:$src3)), 1626 (INSERT_SUBREG QPR:$src1, DPR:$src2, (SubReg_f64_reg imm:$src3))>; 1627 1628// VDUP : Vector Duplicate (from ARM core register to all elements) 1629 1630def splat_lo : PatFrag<(ops node:$lhs, node:$rhs), 1631 (vector_shuffle node:$lhs, node:$rhs), [{ 1632 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N); 1633 return SVOp->isSplat() && SVOp->getSplatIndex() == 0; 1634}]>; 1635 1636class VDUPD<bits<8> opcod1, bits<2> opcod3, string asmSize, ValueType Ty> 1637 : NVDup<opcod1, 0b1011, opcod3, (outs DPR:$dst), (ins GPR:$src), 1638 "vdup", !strconcat(asmSize, "\t$dst, $src"), 1639 [(set DPR:$dst, (Ty (splat_lo (scalar_to_vector GPR:$src), undef)))]>; 1640class VDUPQ<bits<8> opcod1, bits<2> opcod3, string asmSize, ValueType Ty> 1641 : NVDup<opcod1, 0b1011, opcod3, (outs QPR:$dst), (ins GPR:$src), 1642 "vdup", !strconcat(asmSize, "\t$dst, $src"), 1643 [(set QPR:$dst, (Ty (splat_lo (scalar_to_vector GPR:$src), undef)))]>; 1644 1645def VDUP8d : VDUPD<0b11101100, 0b00, ".8", v8i8>; 1646def VDUP16d : VDUPD<0b11101000, 0b01, ".16", v4i16>; 1647def VDUP32d : VDUPD<0b11101000, 0b00, ".32", v2i32>; 1648def VDUP8q : VDUPQ<0b11101110, 0b00, ".8", v16i8>; 1649def VDUP16q : VDUPQ<0b11101010, 0b01, ".16", v8i16>; 1650def VDUP32q : VDUPQ<0b11101010, 0b00, ".32", v4i32>; 1651 1652def VDUPfd : NVDup<0b11101000, 0b1011, 0b00, (outs DPR:$dst), (ins GPR:$src), 1653 "vdup", ".32\t$dst, $src", 1654 [(set DPR:$dst, (v2f32 (splat_lo 1655 (scalar_to_vector 1656 (f32 (bitconvert GPR:$src))), 1657 undef)))]>; 1658def VDUPfq : NVDup<0b11101010, 0b1011, 0b00, (outs QPR:$dst), (ins GPR:$src), 1659 "vdup", ".32\t$dst, $src", 1660 [(set QPR:$dst, (v4f32 (splat_lo 1661 (scalar_to_vector 1662 (f32 (bitconvert GPR:$src))), 1663 undef)))]>; 1664 1665// VDUP : Vector Duplicate Lane (from scalar to all elements) 1666 1667def SHUFFLE_get_splat_lane : SDNodeXForm<vector_shuffle, [{ 1668 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N); 1669 return CurDAG->getTargetConstant(SVOp->getSplatIndex(), MVT::i32); 1670}]>; 1671 1672def splat_lane : PatFrag<(ops node:$lhs, node:$rhs), 1673 (vector_shuffle node:$lhs, node:$rhs), [{ 1674 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N); 1675 return SVOp->isSplat(); 1676}], SHUFFLE_get_splat_lane>; 1677 1678class VDUPLND<bits<2> op19_18, bits<2> op17_16, string OpcodeStr, ValueType Ty> 1679 : N2V<0b11, 0b11, op19_18, op17_16, 0b11000, 0, 0, 1680 (outs DPR:$dst), (ins DPR:$src, i32imm:$lane), 1681 !strconcat(OpcodeStr, "\t$dst, $src[$lane]"), "", 1682 [(set DPR:$dst, (Ty (splat_lane:$lane DPR:$src, undef)))]>; 1683 1684// vector_shuffle requires that the source and destination types match, so 1685// VDUP to a 128-bit result uses a target-specific VDUPLANEQ node. 1686class VDUPLNQ<bits<2> op19_18, bits<2> op17_16, string OpcodeStr, 1687 ValueType ResTy, ValueType OpTy> 1688 : N2V<0b11, 0b11, op19_18, op17_16, 0b11000, 1, 0, 1689 (outs QPR:$dst), (ins DPR:$src, i32imm:$lane), 1690 !strconcat(OpcodeStr, "\t$dst, $src[$lane]"), "", 1691 [(set QPR:$dst, (ResTy (NEONvduplaneq (OpTy DPR:$src), imm:$lane)))]>; 1692 1693def VDUPLN8d : VDUPLND<0b00, 0b01, "vdup.8", v8i8>; 1694def VDUPLN16d : VDUPLND<0b00, 0b10, "vdup.16", v4i16>; 1695def VDUPLN32d : VDUPLND<0b01, 0b00, "vdup.32", v2i32>; 1696def VDUPLNfd : VDUPLND<0b01, 0b00, "vdup.32", v2f32>; 1697def VDUPLN8q : VDUPLNQ<0b00, 0b01, "vdup.8", v16i8, v8i8>; 1698def VDUPLN16q : VDUPLNQ<0b00, 0b10, "vdup.16", v8i16, v4i16>; 1699def VDUPLN32q : VDUPLNQ<0b01, 0b00, "vdup.32", v4i32, v2i32>; 1700def VDUPLNfq : VDUPLNQ<0b01, 0b00, "vdup.32", v4f32, v2f32>; 1701 1702// VMOVN : Vector Narrowing Move 1703defm VMOVN : N2VNInt_HSD<0b11,0b11,0b10,0b00100,0,0, "vmovn.i", 1704 int_arm_neon_vmovn>; 1705// VQMOVN : Vector Saturating Narrowing Move 1706defm VQMOVNs : N2VNInt_HSD<0b11,0b11,0b10,0b00101,0,0, "vqmovn.s", 1707 int_arm_neon_vqmovns>; 1708defm VQMOVNu : N2VNInt_HSD<0b11,0b11,0b10,0b00101,1,0, "vqmovn.u", 1709 int_arm_neon_vqmovnu>; 1710defm VQMOVNsu : N2VNInt_HSD<0b11,0b11,0b10,0b00100,1,0, "vqmovun.s", 1711 int_arm_neon_vqmovnsu>; 1712// VMOVL : Vector Lengthening Move 1713defm VMOVLs : N2VLInt_QHS<0,1,0b1010,0,0,1, "vmovl.s", int_arm_neon_vmovls>; 1714defm VMOVLu : N2VLInt_QHS<1,1,0b1010,0,0,1, "vmovl.u", int_arm_neon_vmovlu>; 1715 1716// Vector Conversions. 1717 1718// VCVT : Vector Convert Between Floating-Point and Integers 1719def VCVTf2sd : N2VD<0b11, 0b11, 0b10, 0b11, 0b01110, 0, "vcvt.s32.f32", 1720 v2i32, v2f32, fp_to_sint>; 1721def VCVTf2ud : N2VD<0b11, 0b11, 0b10, 0b11, 0b01111, 0, "vcvt.u32.f32", 1722 v2i32, v2f32, fp_to_uint>; 1723def VCVTs2fd : N2VD<0b11, 0b11, 0b10, 0b11, 0b01100, 0, "vcvt.f32.s32", 1724 v2f32, v2i32, sint_to_fp>; 1725def VCVTu2fd : N2VD<0b11, 0b11, 0b10, 0b11, 0b01101, 0, "vcvt.f32.u32", 1726 v2f32, v2i32, uint_to_fp>; 1727 1728def VCVTf2sq : N2VQ<0b11, 0b11, 0b10, 0b11, 0b01110, 0, "vcvt.s32.f32", 1729 v4i32, v4f32, fp_to_sint>; 1730def VCVTf2uq : N2VQ<0b11, 0b11, 0b10, 0b11, 0b01111, 0, "vcvt.u32.f32", 1731 v4i32, v4f32, fp_to_uint>; 1732def VCVTs2fq : N2VQ<0b11, 0b11, 0b10, 0b11, 0b01100, 0, "vcvt.f32.s32", 1733 v4f32, v4i32, sint_to_fp>; 1734def VCVTu2fq : N2VQ<0b11, 0b11, 0b10, 0b11, 0b01101, 0, "vcvt.f32.u32", 1735 v4f32, v4i32, uint_to_fp>; 1736 1737// VCVT : Vector Convert Between Floating-Point and Fixed-Point. 1738// Note: Some of the opcode bits in the following VCVT instructions need to 1739// be encoded based on the immed values. 1740def VCVTf2xsd : N2VCvtD<0, 1, 0b000000, 0b1111, 0, 1, "vcvt.s32.f32", 1741 v2i32, v2f32, int_arm_neon_vcvtfp2fxs>; 1742def VCVTf2xud : N2VCvtD<1, 1, 0b000000, 0b1111, 0, 1, "vcvt.u32.f32", 1743 v2i32, v2f32, int_arm_neon_vcvtfp2fxu>; 1744def VCVTxs2fd : N2VCvtD<0, 1, 0b000000, 0b1110, 0, 1, "vcvt.f32.s32", 1745 v2f32, v2i32, int_arm_neon_vcvtfxs2fp>; 1746def VCVTxu2fd : N2VCvtD<1, 1, 0b000000, 0b1110, 0, 1, "vcvt.f32.u32", 1747 v2f32, v2i32, int_arm_neon_vcvtfxu2fp>; 1748 1749def VCVTf2xsq : N2VCvtQ<0, 1, 0b000000, 0b1111, 0, 1, "vcvt.s32.f32", 1750 v4i32, v4f32, int_arm_neon_vcvtfp2fxs>; 1751def VCVTf2xuq : N2VCvtQ<1, 1, 0b000000, 0b1111, 0, 1, "vcvt.u32.f32", 1752 v4i32, v4f32, int_arm_neon_vcvtfp2fxu>; 1753def VCVTxs2fq : N2VCvtQ<0, 1, 0b000000, 0b1110, 0, 1, "vcvt.f32.s32", 1754 v4f32, v4i32, int_arm_neon_vcvtfxs2fp>; 1755def VCVTxu2fq : N2VCvtQ<1, 1, 0b000000, 0b1110, 0, 1, "vcvt.f32.u32", 1756 v4f32, v4i32, int_arm_neon_vcvtfxu2fp>; 1757 1758// VREV : Vector Reverse 1759 1760def vrev64_shuffle : PatFrag<(ops node:$in), 1761 (vector_shuffle node:$in, undef), [{ 1762 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N); 1763 return ARM::isVREVMask(SVOp, 64); 1764}]>; 1765 1766def vrev32_shuffle : PatFrag<(ops node:$in), 1767 (vector_shuffle node:$in, undef), [{ 1768 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N); 1769 return ARM::isVREVMask(SVOp, 32); 1770}]>; 1771 1772def vrev16_shuffle : PatFrag<(ops node:$in), 1773 (vector_shuffle node:$in, undef), [{ 1774 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N); 1775 return ARM::isVREVMask(SVOp, 16); 1776}]>; 1777 1778// VREV64 : Vector Reverse elements within 64-bit doublewords 1779 1780class VREV64D<bits<2> op19_18, string OpcodeStr, ValueType Ty> 1781 : N2V<0b11, 0b11, op19_18, 0b00, 0b00000, 0, 0, (outs DPR:$dst), 1782 (ins DPR:$src), !strconcat(OpcodeStr, "\t$dst, $src"), "", 1783 [(set DPR:$dst, (Ty (vrev64_shuffle (Ty DPR:$src))))]>; 1784class VREV64Q<bits<2> op19_18, string OpcodeStr, ValueType Ty> 1785 : N2V<0b11, 0b11, op19_18, 0b00, 0b00000, 1, 0, (outs QPR:$dst), 1786 (ins QPR:$src), !strconcat(OpcodeStr, "\t$dst, $src"), "", 1787 [(set QPR:$dst, (Ty (vrev64_shuffle (Ty QPR:$src))))]>; 1788 1789def VREV64d8 : VREV64D<0b00, "vrev64.8", v8i8>; 1790def VREV64d16 : VREV64D<0b01, "vrev64.16", v4i16>; 1791def VREV64d32 : VREV64D<0b10, "vrev64.32", v2i32>; 1792def VREV64df : VREV64D<0b10, "vrev64.32", v2f32>; 1793 1794def VREV64q8 : VREV64Q<0b00, "vrev64.8", v16i8>; 1795def VREV64q16 : VREV64Q<0b01, "vrev64.16", v8i16>; 1796def VREV64q32 : VREV64Q<0b10, "vrev64.32", v4i32>; 1797def VREV64qf : VREV64Q<0b10, "vrev64.32", v4f32>; 1798 1799// VREV32 : Vector Reverse elements within 32-bit words 1800 1801class VREV32D<bits<2> op19_18, string OpcodeStr, ValueType Ty> 1802 : N2V<0b11, 0b11, op19_18, 0b00, 0b00001, 0, 0, (outs DPR:$dst), 1803 (ins DPR:$src), !strconcat(OpcodeStr, "\t$dst, $src"), "", 1804 [(set DPR:$dst, (Ty (vrev32_shuffle (Ty DPR:$src))))]>; 1805class VREV32Q<bits<2> op19_18, string OpcodeStr, ValueType Ty> 1806 : N2V<0b11, 0b11, op19_18, 0b00, 0b00001, 1, 0, (outs QPR:$dst), 1807 (ins QPR:$src), !strconcat(OpcodeStr, "\t$dst, $src"), "", 1808 [(set QPR:$dst, (Ty (vrev32_shuffle (Ty QPR:$src))))]>; 1809 1810def VREV32d8 : VREV32D<0b00, "vrev32.8", v8i8>; 1811def VREV32d16 : VREV32D<0b01, "vrev32.16", v4i16>; 1812 1813def VREV32q8 : VREV32Q<0b00, "vrev32.8", v16i8>; 1814def VREV32q16 : VREV32Q<0b01, "vrev32.16", v8i16>; 1815 1816// VREV16 : Vector Reverse elements within 16-bit halfwords 1817 1818class VREV16D<bits<2> op19_18, string OpcodeStr, ValueType Ty> 1819 : N2V<0b11, 0b11, op19_18, 0b00, 0b00010, 0, 0, (outs DPR:$dst), 1820 (ins DPR:$src), !strconcat(OpcodeStr, "\t$dst, $src"), "", 1821 [(set DPR:$dst, (Ty (vrev16_shuffle (Ty DPR:$src))))]>; 1822class VREV16Q<bits<2> op19_18, string OpcodeStr, ValueType Ty> 1823 : N2V<0b11, 0b11, op19_18, 0b00, 0b00010, 1, 0, (outs QPR:$dst), 1824 (ins QPR:$src), !strconcat(OpcodeStr, "\t$dst, $src"), "", 1825 [(set QPR:$dst, (Ty (vrev16_shuffle (Ty QPR:$src))))]>; 1826 1827def VREV16d8 : VREV16D<0b00, "vrev16.8", v8i8>; 1828def VREV16q8 : VREV16Q<0b00, "vrev16.8", v16i8>; 1829 1830//===----------------------------------------------------------------------===// 1831// Non-Instruction Patterns 1832//===----------------------------------------------------------------------===// 1833 1834// bit_convert 1835def : Pat<(v1i64 (bitconvert (v2i32 DPR:$src))), (v1i64 DPR:$src)>; 1836def : Pat<(v1i64 (bitconvert (v4i16 DPR:$src))), (v1i64 DPR:$src)>; 1837def : Pat<(v1i64 (bitconvert (v8i8 DPR:$src))), (v1i64 DPR:$src)>; 1838def : Pat<(v1i64 (bitconvert (f64 DPR:$src))), (v1i64 DPR:$src)>; 1839def : Pat<(v1i64 (bitconvert (v2f32 DPR:$src))), (v1i64 DPR:$src)>; 1840def : Pat<(v2i32 (bitconvert (v1i64 DPR:$src))), (v2i32 DPR:$src)>; 1841def : Pat<(v2i32 (bitconvert (v4i16 DPR:$src))), (v2i32 DPR:$src)>; 1842def : Pat<(v2i32 (bitconvert (v8i8 DPR:$src))), (v2i32 DPR:$src)>; 1843def : Pat<(v2i32 (bitconvert (f64 DPR:$src))), (v2i32 DPR:$src)>; 1844def : Pat<(v2i32 (bitconvert (v2f32 DPR:$src))), (v2i32 DPR:$src)>; 1845def : Pat<(v4i16 (bitconvert (v1i64 DPR:$src))), (v4i16 DPR:$src)>; 1846def : Pat<(v4i16 (bitconvert (v2i32 DPR:$src))), (v4i16 DPR:$src)>; 1847def : Pat<(v4i16 (bitconvert (v8i8 DPR:$src))), (v4i16 DPR:$src)>; 1848def : Pat<(v4i16 (bitconvert (f64 DPR:$src))), (v4i16 DPR:$src)>; 1849def : Pat<(v4i16 (bitconvert (v2f32 DPR:$src))), (v4i16 DPR:$src)>; 1850def : Pat<(v8i8 (bitconvert (v1i64 DPR:$src))), (v8i8 DPR:$src)>; 1851def : Pat<(v8i8 (bitconvert (v2i32 DPR:$src))), (v8i8 DPR:$src)>; 1852def : Pat<(v8i8 (bitconvert (v4i16 DPR:$src))), (v8i8 DPR:$src)>; 1853def : Pat<(v8i8 (bitconvert (f64 DPR:$src))), (v8i8 DPR:$src)>; 1854def : Pat<(v8i8 (bitconvert (v2f32 DPR:$src))), (v8i8 DPR:$src)>; 1855def : Pat<(f64 (bitconvert (v1i64 DPR:$src))), (f64 DPR:$src)>; 1856def : Pat<(f64 (bitconvert (v2i32 DPR:$src))), (f64 DPR:$src)>; 1857def : Pat<(f64 (bitconvert (v4i16 DPR:$src))), (f64 DPR:$src)>; 1858def : Pat<(f64 (bitconvert (v8i8 DPR:$src))), (f64 DPR:$src)>; 1859def : Pat<(f64 (bitconvert (v2f32 DPR:$src))), (f64 DPR:$src)>; 1860def : Pat<(v2f32 (bitconvert (f64 DPR:$src))), (v2f32 DPR:$src)>; 1861def : Pat<(v2f32 (bitconvert (v1i64 DPR:$src))), (v2f32 DPR:$src)>; 1862def : Pat<(v2f32 (bitconvert (v2i32 DPR:$src))), (v2f32 DPR:$src)>; 1863def : Pat<(v2f32 (bitconvert (v4i16 DPR:$src))), (v2f32 DPR:$src)>; 1864def : Pat<(v2f32 (bitconvert (v8i8 DPR:$src))), (v2f32 DPR:$src)>; 1865 1866def : Pat<(v2i64 (bitconvert (v4i32 QPR:$src))), (v2i64 QPR:$src)>; 1867def : Pat<(v2i64 (bitconvert (v8i16 QPR:$src))), (v2i64 QPR:$src)>; 1868def : Pat<(v2i64 (bitconvert (v16i8 QPR:$src))), (v2i64 QPR:$src)>; 1869def : Pat<(v2i64 (bitconvert (v2f64 QPR:$src))), (v2i64 QPR:$src)>; 1870def : Pat<(v2i64 (bitconvert (v4f32 QPR:$src))), (v2i64 QPR:$src)>; 1871def : Pat<(v4i32 (bitconvert (v2i64 QPR:$src))), (v4i32 QPR:$src)>; 1872def : Pat<(v4i32 (bitconvert (v8i16 QPR:$src))), (v4i32 QPR:$src)>; 1873def : Pat<(v4i32 (bitconvert (v16i8 QPR:$src))), (v4i32 QPR:$src)>; 1874def : Pat<(v4i32 (bitconvert (v2f64 QPR:$src))), (v4i32 QPR:$src)>; 1875def : Pat<(v4i32 (bitconvert (v4f32 QPR:$src))), (v4i32 QPR:$src)>; 1876def : Pat<(v8i16 (bitconvert (v2i64 QPR:$src))), (v8i16 QPR:$src)>; 1877def : Pat<(v8i16 (bitconvert (v4i32 QPR:$src))), (v8i16 QPR:$src)>; 1878def : Pat<(v8i16 (bitconvert (v16i8 QPR:$src))), (v8i16 QPR:$src)>; 1879def : Pat<(v8i16 (bitconvert (v2f64 QPR:$src))), (v8i16 QPR:$src)>; 1880def : Pat<(v8i16 (bitconvert (v4f32 QPR:$src))), (v8i16 QPR:$src)>; 1881def : Pat<(v16i8 (bitconvert (v2i64 QPR:$src))), (v16i8 QPR:$src)>; 1882def : Pat<(v16i8 (bitconvert (v4i32 QPR:$src))), (v16i8 QPR:$src)>; 1883def : Pat<(v16i8 (bitconvert (v8i16 QPR:$src))), (v16i8 QPR:$src)>; 1884def : Pat<(v16i8 (bitconvert (v2f64 QPR:$src))), (v16i8 QPR:$src)>; 1885def : Pat<(v16i8 (bitconvert (v4f32 QPR:$src))), (v16i8 QPR:$src)>; 1886def : Pat<(v4f32 (bitconvert (v2i64 QPR:$src))), (v4f32 QPR:$src)>; 1887def : Pat<(v4f32 (bitconvert (v4i32 QPR:$src))), (v4f32 QPR:$src)>; 1888def : Pat<(v4f32 (bitconvert (v8i16 QPR:$src))), (v4f32 QPR:$src)>; 1889def : Pat<(v4f32 (bitconvert (v16i8 QPR:$src))), (v4f32 QPR:$src)>; 1890def : Pat<(v4f32 (bitconvert (v2f64 QPR:$src))), (v4f32 QPR:$src)>; 1891def : Pat<(v2f64 (bitconvert (v2i64 QPR:$src))), (v2f64 QPR:$src)>; 1892def : Pat<(v2f64 (bitconvert (v4i32 QPR:$src))), (v2f64 QPR:$src)>; 1893def : Pat<(v2f64 (bitconvert (v8i16 QPR:$src))), (v2f64 QPR:$src)>; 1894def : Pat<(v2f64 (bitconvert (v16i8 QPR:$src))), (v2f64 QPR:$src)>; 1895def : Pat<(v2f64 (bitconvert (v4f32 QPR:$src))), (v2f64 QPR:$src)>; 1896