ARMInstrNEON.td revision c94206e5521d06d196a290e0c4431150e6be031b
1//===-- ARMInstrNEON.td - NEON support for ARM -------------*- tablegen -*-===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file describes the ARM NEON instruction set. 11// 12//===----------------------------------------------------------------------===// 13 14 15//===----------------------------------------------------------------------===// 16// NEON-specific Operands. 17//===----------------------------------------------------------------------===// 18def nModImm : Operand<i32> { 19 let PrintMethod = "printNEONModImmOperand"; 20} 21 22def nImmSplatI8AsmOperand : AsmOperandClass { let Name = "NEONi8splat"; } 23def nImmSplatI8 : Operand<i32> { 24 let PrintMethod = "printNEONModImmOperand"; 25 let ParserMatchClass = nImmSplatI8AsmOperand; 26} 27def nImmSplatI16AsmOperand : AsmOperandClass { let Name = "NEONi16splat"; } 28def nImmSplatI16 : Operand<i32> { 29 let PrintMethod = "printNEONModImmOperand"; 30 let ParserMatchClass = nImmSplatI16AsmOperand; 31} 32def nImmSplatI32AsmOperand : AsmOperandClass { let Name = "NEONi32splat"; } 33def nImmSplatI32 : Operand<i32> { 34 let PrintMethod = "printNEONModImmOperand"; 35 let ParserMatchClass = nImmSplatI32AsmOperand; 36} 37def nImmVMOVI32AsmOperand : AsmOperandClass { let Name = "NEONi32vmov"; } 38def nImmVMOVI32 : Operand<i32> { 39 let PrintMethod = "printNEONModImmOperand"; 40 let ParserMatchClass = nImmVMOVI32AsmOperand; 41} 42def nImmVMOVI32NegAsmOperand : AsmOperandClass { let Name = "NEONi32vmovNeg"; } 43def nImmVMOVI32Neg : Operand<i32> { 44 let PrintMethod = "printNEONModImmOperand"; 45 let ParserMatchClass = nImmVMOVI32NegAsmOperand; 46} 47def nImmVMOVF32 : Operand<i32> { 48 let PrintMethod = "printFPImmOperand"; 49 let ParserMatchClass = FPImmOperand; 50} 51def nImmSplatI64AsmOperand : AsmOperandClass { let Name = "NEONi64splat"; } 52def nImmSplatI64 : Operand<i32> { 53 let PrintMethod = "printNEONModImmOperand"; 54 let ParserMatchClass = nImmSplatI64AsmOperand; 55} 56 57def VectorIndex8Operand : AsmOperandClass { let Name = "VectorIndex8"; } 58def VectorIndex16Operand : AsmOperandClass { let Name = "VectorIndex16"; } 59def VectorIndex32Operand : AsmOperandClass { let Name = "VectorIndex32"; } 60def VectorIndex8 : Operand<i32>, ImmLeaf<i32, [{ 61 return ((uint64_t)Imm) < 8; 62}]> { 63 let ParserMatchClass = VectorIndex8Operand; 64 let PrintMethod = "printVectorIndex"; 65 let MIOperandInfo = (ops i32imm); 66} 67def VectorIndex16 : Operand<i32>, ImmLeaf<i32, [{ 68 return ((uint64_t)Imm) < 4; 69}]> { 70 let ParserMatchClass = VectorIndex16Operand; 71 let PrintMethod = "printVectorIndex"; 72 let MIOperandInfo = (ops i32imm); 73} 74def VectorIndex32 : Operand<i32>, ImmLeaf<i32, [{ 75 return ((uint64_t)Imm) < 2; 76}]> { 77 let ParserMatchClass = VectorIndex32Operand; 78 let PrintMethod = "printVectorIndex"; 79 let MIOperandInfo = (ops i32imm); 80} 81 82// Register list of one D register. 83def VecListOneDAsmOperand : AsmOperandClass { 84 let Name = "VecListOneD"; 85 let ParserMethod = "parseVectorList"; 86 let RenderMethod = "addVecListOperands"; 87} 88def VecListOneD : RegisterOperand<DPR, "printVectorListOne"> { 89 let ParserMatchClass = VecListOneDAsmOperand; 90} 91// Register list of two sequential D registers. 92def VecListTwoDAsmOperand : AsmOperandClass { 93 let Name = "VecListTwoD"; 94 let ParserMethod = "parseVectorList"; 95 let RenderMethod = "addVecListOperands"; 96} 97def VecListTwoD : RegisterOperand<DPR, "printVectorListTwo"> { 98 let ParserMatchClass = VecListTwoDAsmOperand; 99} 100// Register list of three sequential D registers. 101def VecListThreeDAsmOperand : AsmOperandClass { 102 let Name = "VecListThreeD"; 103 let ParserMethod = "parseVectorList"; 104 let RenderMethod = "addVecListOperands"; 105} 106def VecListThreeD : RegisterOperand<DPR, "printVectorListThree"> { 107 let ParserMatchClass = VecListThreeDAsmOperand; 108} 109// Register list of four sequential D registers. 110def VecListFourDAsmOperand : AsmOperandClass { 111 let Name = "VecListFourD"; 112 let ParserMethod = "parseVectorList"; 113 let RenderMethod = "addVecListOperands"; 114} 115def VecListFourD : RegisterOperand<DPR, "printVectorListFour"> { 116 let ParserMatchClass = VecListFourDAsmOperand; 117} 118// Register list of two D registers spaced by 2 (two sequential Q registers). 119def VecListTwoQAsmOperand : AsmOperandClass { 120 let Name = "VecListTwoQ"; 121 let ParserMethod = "parseVectorList"; 122 let RenderMethod = "addVecListOperands"; 123} 124def VecListTwoQ : RegisterOperand<DPR, "printVectorListTwoSpaced"> { 125 let ParserMatchClass = VecListTwoQAsmOperand; 126} 127// Register list of three D registers spaced by 2 (three Q registers). 128def VecListThreeQAsmOperand : AsmOperandClass { 129 let Name = "VecListThreeQ"; 130 let ParserMethod = "parseVectorList"; 131 let RenderMethod = "addVecListOperands"; 132} 133def VecListThreeQ : RegisterOperand<DPR, "printVectorListThreeSpaced"> { 134 let ParserMatchClass = VecListThreeQAsmOperand; 135} 136// Register list of three D registers spaced by 2 (three Q registers). 137def VecListFourQAsmOperand : AsmOperandClass { 138 let Name = "VecListFourQ"; 139 let ParserMethod = "parseVectorList"; 140 let RenderMethod = "addVecListOperands"; 141} 142def VecListFourQ : RegisterOperand<DPR, "printVectorListFourSpaced"> { 143 let ParserMatchClass = VecListFourQAsmOperand; 144} 145 146// Register list of one D register, with "all lanes" subscripting. 147def VecListOneDAllLanesAsmOperand : AsmOperandClass { 148 let Name = "VecListOneDAllLanes"; 149 let ParserMethod = "parseVectorList"; 150 let RenderMethod = "addVecListOperands"; 151} 152def VecListOneDAllLanes : RegisterOperand<DPR, "printVectorListOneAllLanes"> { 153 let ParserMatchClass = VecListOneDAllLanesAsmOperand; 154} 155// Register list of two D registers, with "all lanes" subscripting. 156def VecListTwoDAllLanesAsmOperand : AsmOperandClass { 157 let Name = "VecListTwoDAllLanes"; 158 let ParserMethod = "parseVectorList"; 159 let RenderMethod = "addVecListOperands"; 160} 161def VecListTwoDAllLanes : RegisterOperand<DPR, "printVectorListTwoAllLanes"> { 162 let ParserMatchClass = VecListTwoDAllLanesAsmOperand; 163} 164// Register list of two D registers spaced by 2 (two sequential Q registers). 165def VecListTwoQAllLanesAsmOperand : AsmOperandClass { 166 let Name = "VecListTwoQAllLanes"; 167 let ParserMethod = "parseVectorList"; 168 let RenderMethod = "addVecListOperands"; 169} 170def VecListTwoQAllLanes : RegisterOperand<DPR, 171 "printVectorListTwoSpacedAllLanes"> { 172 let ParserMatchClass = VecListTwoQAllLanesAsmOperand; 173} 174// Register list of three D registers, with "all lanes" subscripting. 175def VecListThreeDAllLanesAsmOperand : AsmOperandClass { 176 let Name = "VecListThreeDAllLanes"; 177 let ParserMethod = "parseVectorList"; 178 let RenderMethod = "addVecListOperands"; 179} 180def VecListThreeDAllLanes : RegisterOperand<DPR, 181 "printVectorListThreeAllLanes"> { 182 let ParserMatchClass = VecListThreeDAllLanesAsmOperand; 183} 184// Register list of three D registers spaced by 2 (three sequential Q regs). 185def VecListThreeQAllLanesAsmOperand : AsmOperandClass { 186 let Name = "VecListThreeQAllLanes"; 187 let ParserMethod = "parseVectorList"; 188 let RenderMethod = "addVecListOperands"; 189} 190def VecListThreeQAllLanes : RegisterOperand<DPR, 191 "printVectorListThreeSpacedAllLanes"> { 192 let ParserMatchClass = VecListThreeQAllLanesAsmOperand; 193} 194// Register list of four D registers, with "all lanes" subscripting. 195def VecListFourDAllLanesAsmOperand : AsmOperandClass { 196 let Name = "VecListFourDAllLanes"; 197 let ParserMethod = "parseVectorList"; 198 let RenderMethod = "addVecListOperands"; 199} 200def VecListFourDAllLanes : RegisterOperand<DPR, "printVectorListFourAllLanes"> { 201 let ParserMatchClass = VecListFourDAllLanesAsmOperand; 202} 203// Register list of four D registers spaced by 2 (four sequential Q regs). 204def VecListFourQAllLanesAsmOperand : AsmOperandClass { 205 let Name = "VecListFourQAllLanes"; 206 let ParserMethod = "parseVectorList"; 207 let RenderMethod = "addVecListOperands"; 208} 209def VecListFourQAllLanes : RegisterOperand<DPR, 210 "printVectorListFourSpacedAllLanes"> { 211 let ParserMatchClass = VecListFourQAllLanesAsmOperand; 212} 213 214 215// Register list of one D register, with byte lane subscripting. 216def VecListOneDByteIndexAsmOperand : AsmOperandClass { 217 let Name = "VecListOneDByteIndexed"; 218 let ParserMethod = "parseVectorList"; 219 let RenderMethod = "addVecListIndexedOperands"; 220} 221def VecListOneDByteIndexed : Operand<i32> { 222 let ParserMatchClass = VecListOneDByteIndexAsmOperand; 223 let MIOperandInfo = (ops DPR:$Vd, i32imm:$idx); 224} 225// ...with half-word lane subscripting. 226def VecListOneDHWordIndexAsmOperand : AsmOperandClass { 227 let Name = "VecListOneDHWordIndexed"; 228 let ParserMethod = "parseVectorList"; 229 let RenderMethod = "addVecListIndexedOperands"; 230} 231def VecListOneDHWordIndexed : Operand<i32> { 232 let ParserMatchClass = VecListOneDHWordIndexAsmOperand; 233 let MIOperandInfo = (ops DPR:$Vd, i32imm:$idx); 234} 235// ...with word lane subscripting. 236def VecListOneDWordIndexAsmOperand : AsmOperandClass { 237 let Name = "VecListOneDWordIndexed"; 238 let ParserMethod = "parseVectorList"; 239 let RenderMethod = "addVecListIndexedOperands"; 240} 241def VecListOneDWordIndexed : Operand<i32> { 242 let ParserMatchClass = VecListOneDWordIndexAsmOperand; 243 let MIOperandInfo = (ops DPR:$Vd, i32imm:$idx); 244} 245 246// Register list of two D registers with byte lane subscripting. 247def VecListTwoDByteIndexAsmOperand : AsmOperandClass { 248 let Name = "VecListTwoDByteIndexed"; 249 let ParserMethod = "parseVectorList"; 250 let RenderMethod = "addVecListIndexedOperands"; 251} 252def VecListTwoDByteIndexed : Operand<i32> { 253 let ParserMatchClass = VecListTwoDByteIndexAsmOperand; 254 let MIOperandInfo = (ops DPR:$Vd, i32imm:$idx); 255} 256// ...with half-word lane subscripting. 257def VecListTwoDHWordIndexAsmOperand : AsmOperandClass { 258 let Name = "VecListTwoDHWordIndexed"; 259 let ParserMethod = "parseVectorList"; 260 let RenderMethod = "addVecListIndexedOperands"; 261} 262def VecListTwoDHWordIndexed : Operand<i32> { 263 let ParserMatchClass = VecListTwoDHWordIndexAsmOperand; 264 let MIOperandInfo = (ops DPR:$Vd, i32imm:$idx); 265} 266// ...with word lane subscripting. 267def VecListTwoDWordIndexAsmOperand : AsmOperandClass { 268 let Name = "VecListTwoDWordIndexed"; 269 let ParserMethod = "parseVectorList"; 270 let RenderMethod = "addVecListIndexedOperands"; 271} 272def VecListTwoDWordIndexed : Operand<i32> { 273 let ParserMatchClass = VecListTwoDWordIndexAsmOperand; 274 let MIOperandInfo = (ops DPR:$Vd, i32imm:$idx); 275} 276// Register list of two Q registers with half-word lane subscripting. 277def VecListTwoQHWordIndexAsmOperand : AsmOperandClass { 278 let Name = "VecListTwoQHWordIndexed"; 279 let ParserMethod = "parseVectorList"; 280 let RenderMethod = "addVecListIndexedOperands"; 281} 282def VecListTwoQHWordIndexed : Operand<i32> { 283 let ParserMatchClass = VecListTwoQHWordIndexAsmOperand; 284 let MIOperandInfo = (ops DPR:$Vd, i32imm:$idx); 285} 286// ...with word lane subscripting. 287def VecListTwoQWordIndexAsmOperand : AsmOperandClass { 288 let Name = "VecListTwoQWordIndexed"; 289 let ParserMethod = "parseVectorList"; 290 let RenderMethod = "addVecListIndexedOperands"; 291} 292def VecListTwoQWordIndexed : Operand<i32> { 293 let ParserMatchClass = VecListTwoQWordIndexAsmOperand; 294 let MIOperandInfo = (ops DPR:$Vd, i32imm:$idx); 295} 296 297 298// Register list of three D registers with byte lane subscripting. 299def VecListThreeDByteIndexAsmOperand : AsmOperandClass { 300 let Name = "VecListThreeDByteIndexed"; 301 let ParserMethod = "parseVectorList"; 302 let RenderMethod = "addVecListIndexedOperands"; 303} 304def VecListThreeDByteIndexed : Operand<i32> { 305 let ParserMatchClass = VecListThreeDByteIndexAsmOperand; 306 let MIOperandInfo = (ops DPR:$Vd, i32imm:$idx); 307} 308// ...with half-word lane subscripting. 309def VecListThreeDHWordIndexAsmOperand : AsmOperandClass { 310 let Name = "VecListThreeDHWordIndexed"; 311 let ParserMethod = "parseVectorList"; 312 let RenderMethod = "addVecListIndexedOperands"; 313} 314def VecListThreeDHWordIndexed : Operand<i32> { 315 let ParserMatchClass = VecListThreeDHWordIndexAsmOperand; 316 let MIOperandInfo = (ops DPR:$Vd, i32imm:$idx); 317} 318// ...with word lane subscripting. 319def VecListThreeDWordIndexAsmOperand : AsmOperandClass { 320 let Name = "VecListThreeDWordIndexed"; 321 let ParserMethod = "parseVectorList"; 322 let RenderMethod = "addVecListIndexedOperands"; 323} 324def VecListThreeDWordIndexed : Operand<i32> { 325 let ParserMatchClass = VecListThreeDWordIndexAsmOperand; 326 let MIOperandInfo = (ops DPR:$Vd, i32imm:$idx); 327} 328// Register list of three Q registers with half-word lane subscripting. 329def VecListThreeQHWordIndexAsmOperand : AsmOperandClass { 330 let Name = "VecListThreeQHWordIndexed"; 331 let ParserMethod = "parseVectorList"; 332 let RenderMethod = "addVecListIndexedOperands"; 333} 334def VecListThreeQHWordIndexed : Operand<i32> { 335 let ParserMatchClass = VecListThreeQHWordIndexAsmOperand; 336 let MIOperandInfo = (ops DPR:$Vd, i32imm:$idx); 337} 338// ...with word lane subscripting. 339def VecListThreeQWordIndexAsmOperand : AsmOperandClass { 340 let Name = "VecListThreeQWordIndexed"; 341 let ParserMethod = "parseVectorList"; 342 let RenderMethod = "addVecListIndexedOperands"; 343} 344def VecListThreeQWordIndexed : Operand<i32> { 345 let ParserMatchClass = VecListThreeQWordIndexAsmOperand; 346 let MIOperandInfo = (ops DPR:$Vd, i32imm:$idx); 347} 348 349// Register list of four D registers with byte lane subscripting. 350def VecListFourDByteIndexAsmOperand : AsmOperandClass { 351 let Name = "VecListFourDByteIndexed"; 352 let ParserMethod = "parseVectorList"; 353 let RenderMethod = "addVecListIndexedOperands"; 354} 355def VecListFourDByteIndexed : Operand<i32> { 356 let ParserMatchClass = VecListFourDByteIndexAsmOperand; 357 let MIOperandInfo = (ops DPR:$Vd, i32imm:$idx); 358} 359// ...with half-word lane subscripting. 360def VecListFourDHWordIndexAsmOperand : AsmOperandClass { 361 let Name = "VecListFourDHWordIndexed"; 362 let ParserMethod = "parseVectorList"; 363 let RenderMethod = "addVecListIndexedOperands"; 364} 365def VecListFourDHWordIndexed : Operand<i32> { 366 let ParserMatchClass = VecListFourDHWordIndexAsmOperand; 367 let MIOperandInfo = (ops DPR:$Vd, i32imm:$idx); 368} 369// ...with word lane subscripting. 370def VecListFourDWordIndexAsmOperand : AsmOperandClass { 371 let Name = "VecListFourDWordIndexed"; 372 let ParserMethod = "parseVectorList"; 373 let RenderMethod = "addVecListIndexedOperands"; 374} 375def VecListFourDWordIndexed : Operand<i32> { 376 let ParserMatchClass = VecListFourDWordIndexAsmOperand; 377 let MIOperandInfo = (ops DPR:$Vd, i32imm:$idx); 378} 379// Register list of four Q registers with half-word lane subscripting. 380def VecListFourQHWordIndexAsmOperand : AsmOperandClass { 381 let Name = "VecListFourQHWordIndexed"; 382 let ParserMethod = "parseVectorList"; 383 let RenderMethod = "addVecListIndexedOperands"; 384} 385def VecListFourQHWordIndexed : Operand<i32> { 386 let ParserMatchClass = VecListFourQHWordIndexAsmOperand; 387 let MIOperandInfo = (ops DPR:$Vd, i32imm:$idx); 388} 389// ...with word lane subscripting. 390def VecListFourQWordIndexAsmOperand : AsmOperandClass { 391 let Name = "VecListFourQWordIndexed"; 392 let ParserMethod = "parseVectorList"; 393 let RenderMethod = "addVecListIndexedOperands"; 394} 395def VecListFourQWordIndexed : Operand<i32> { 396 let ParserMatchClass = VecListFourQWordIndexAsmOperand; 397 let MIOperandInfo = (ops DPR:$Vd, i32imm:$idx); 398} 399 400 401//===----------------------------------------------------------------------===// 402// NEON-specific DAG Nodes. 403//===----------------------------------------------------------------------===// 404 405def SDTARMVCMP : SDTypeProfile<1, 2, [SDTCisInt<0>, SDTCisSameAs<1, 2>]>; 406def SDTARMVCMPZ : SDTypeProfile<1, 1, []>; 407 408def NEONvceq : SDNode<"ARMISD::VCEQ", SDTARMVCMP>; 409def NEONvceqz : SDNode<"ARMISD::VCEQZ", SDTARMVCMPZ>; 410def NEONvcge : SDNode<"ARMISD::VCGE", SDTARMVCMP>; 411def NEONvcgez : SDNode<"ARMISD::VCGEZ", SDTARMVCMPZ>; 412def NEONvclez : SDNode<"ARMISD::VCLEZ", SDTARMVCMPZ>; 413def NEONvcgeu : SDNode<"ARMISD::VCGEU", SDTARMVCMP>; 414def NEONvcgt : SDNode<"ARMISD::VCGT", SDTARMVCMP>; 415def NEONvcgtz : SDNode<"ARMISD::VCGTZ", SDTARMVCMPZ>; 416def NEONvcltz : SDNode<"ARMISD::VCLTZ", SDTARMVCMPZ>; 417def NEONvcgtu : SDNode<"ARMISD::VCGTU", SDTARMVCMP>; 418def NEONvtst : SDNode<"ARMISD::VTST", SDTARMVCMP>; 419 420// Types for vector shift by immediates. The "SHX" version is for long and 421// narrow operations where the source and destination vectors have different 422// types. The "SHINS" version is for shift and insert operations. 423def SDTARMVSH : SDTypeProfile<1, 2, [SDTCisInt<0>, SDTCisSameAs<0, 1>, 424 SDTCisVT<2, i32>]>; 425def SDTARMVSHX : SDTypeProfile<1, 2, [SDTCisInt<0>, SDTCisInt<1>, 426 SDTCisVT<2, i32>]>; 427def SDTARMVSHINS : SDTypeProfile<1, 3, [SDTCisInt<0>, SDTCisSameAs<0, 1>, 428 SDTCisSameAs<0, 2>, SDTCisVT<3, i32>]>; 429 430def NEONvshl : SDNode<"ARMISD::VSHL", SDTARMVSH>; 431def NEONvshrs : SDNode<"ARMISD::VSHRs", SDTARMVSH>; 432def NEONvshru : SDNode<"ARMISD::VSHRu", SDTARMVSH>; 433def NEONvshlls : SDNode<"ARMISD::VSHLLs", SDTARMVSHX>; 434def NEONvshllu : SDNode<"ARMISD::VSHLLu", SDTARMVSHX>; 435def NEONvshlli : SDNode<"ARMISD::VSHLLi", SDTARMVSHX>; 436def NEONvshrn : SDNode<"ARMISD::VSHRN", SDTARMVSHX>; 437 438def NEONvrshrs : SDNode<"ARMISD::VRSHRs", SDTARMVSH>; 439def NEONvrshru : SDNode<"ARMISD::VRSHRu", SDTARMVSH>; 440def NEONvrshrn : SDNode<"ARMISD::VRSHRN", SDTARMVSHX>; 441 442def NEONvqshls : SDNode<"ARMISD::VQSHLs", SDTARMVSH>; 443def NEONvqshlu : SDNode<"ARMISD::VQSHLu", SDTARMVSH>; 444def NEONvqshlsu : SDNode<"ARMISD::VQSHLsu", SDTARMVSH>; 445def NEONvqshrns : SDNode<"ARMISD::VQSHRNs", SDTARMVSHX>; 446def NEONvqshrnu : SDNode<"ARMISD::VQSHRNu", SDTARMVSHX>; 447def NEONvqshrnsu : SDNode<"ARMISD::VQSHRNsu", SDTARMVSHX>; 448 449def NEONvqrshrns : SDNode<"ARMISD::VQRSHRNs", SDTARMVSHX>; 450def NEONvqrshrnu : SDNode<"ARMISD::VQRSHRNu", SDTARMVSHX>; 451def NEONvqrshrnsu : SDNode<"ARMISD::VQRSHRNsu", SDTARMVSHX>; 452 453def NEONvsli : SDNode<"ARMISD::VSLI", SDTARMVSHINS>; 454def NEONvsri : SDNode<"ARMISD::VSRI", SDTARMVSHINS>; 455 456def SDTARMVGETLN : SDTypeProfile<1, 2, [SDTCisVT<0, i32>, SDTCisInt<1>, 457 SDTCisVT<2, i32>]>; 458def NEONvgetlaneu : SDNode<"ARMISD::VGETLANEu", SDTARMVGETLN>; 459def NEONvgetlanes : SDNode<"ARMISD::VGETLANEs", SDTARMVGETLN>; 460 461def SDTARMVMOVIMM : SDTypeProfile<1, 1, [SDTCisVec<0>, SDTCisVT<1, i32>]>; 462def NEONvmovImm : SDNode<"ARMISD::VMOVIMM", SDTARMVMOVIMM>; 463def NEONvmvnImm : SDNode<"ARMISD::VMVNIMM", SDTARMVMOVIMM>; 464def NEONvmovFPImm : SDNode<"ARMISD::VMOVFPIMM", SDTARMVMOVIMM>; 465 466def SDTARMVORRIMM : SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisSameAs<0, 1>, 467 SDTCisVT<2, i32>]>; 468def NEONvorrImm : SDNode<"ARMISD::VORRIMM", SDTARMVORRIMM>; 469def NEONvbicImm : SDNode<"ARMISD::VBICIMM", SDTARMVORRIMM>; 470 471def NEONvbsl : SDNode<"ARMISD::VBSL", 472 SDTypeProfile<1, 3, [SDTCisVec<0>, 473 SDTCisSameAs<0, 1>, 474 SDTCisSameAs<0, 2>, 475 SDTCisSameAs<0, 3>]>>; 476 477def NEONvdup : SDNode<"ARMISD::VDUP", SDTypeProfile<1, 1, [SDTCisVec<0>]>>; 478 479// VDUPLANE can produce a quad-register result from a double-register source, 480// so the result is not constrained to match the source. 481def NEONvduplane : SDNode<"ARMISD::VDUPLANE", 482 SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisVec<1>, 483 SDTCisVT<2, i32>]>>; 484 485def SDTARMVEXT : SDTypeProfile<1, 3, [SDTCisVec<0>, SDTCisSameAs<0, 1>, 486 SDTCisSameAs<0, 2>, SDTCisVT<3, i32>]>; 487def NEONvext : SDNode<"ARMISD::VEXT", SDTARMVEXT>; 488 489def SDTARMVSHUF : SDTypeProfile<1, 1, [SDTCisVec<0>, SDTCisSameAs<0, 1>]>; 490def NEONvrev64 : SDNode<"ARMISD::VREV64", SDTARMVSHUF>; 491def NEONvrev32 : SDNode<"ARMISD::VREV32", SDTARMVSHUF>; 492def NEONvrev16 : SDNode<"ARMISD::VREV16", SDTARMVSHUF>; 493 494def SDTARMVSHUF2 : SDTypeProfile<2, 2, [SDTCisVec<0>, SDTCisSameAs<0, 1>, 495 SDTCisSameAs<0, 2>, 496 SDTCisSameAs<0, 3>]>; 497def NEONzip : SDNode<"ARMISD::VZIP", SDTARMVSHUF2>; 498def NEONuzp : SDNode<"ARMISD::VUZP", SDTARMVSHUF2>; 499def NEONtrn : SDNode<"ARMISD::VTRN", SDTARMVSHUF2>; 500 501def SDTARMVMULL : SDTypeProfile<1, 2, [SDTCisInt<0>, SDTCisInt<1>, 502 SDTCisSameAs<1, 2>]>; 503def NEONvmulls : SDNode<"ARMISD::VMULLs", SDTARMVMULL>; 504def NEONvmullu : SDNode<"ARMISD::VMULLu", SDTARMVMULL>; 505 506def SDTARMFMAX : SDTypeProfile<1, 2, [SDTCisVT<0, f32>, SDTCisSameAs<0, 1>, 507 SDTCisSameAs<0, 2>]>; 508def NEONfmax : SDNode<"ARMISD::FMAX", SDTARMFMAX>; 509def NEONfmin : SDNode<"ARMISD::FMIN", SDTARMFMAX>; 510 511def NEONimmAllZerosV: PatLeaf<(NEONvmovImm (i32 timm)), [{ 512 ConstantSDNode *ConstVal = cast<ConstantSDNode>(N->getOperand(0)); 513 unsigned EltBits = 0; 514 uint64_t EltVal = ARM_AM::decodeNEONModImm(ConstVal->getZExtValue(), EltBits); 515 return (EltBits == 32 && EltVal == 0); 516}]>; 517 518def NEONimmAllOnesV: PatLeaf<(NEONvmovImm (i32 timm)), [{ 519 ConstantSDNode *ConstVal = cast<ConstantSDNode>(N->getOperand(0)); 520 unsigned EltBits = 0; 521 uint64_t EltVal = ARM_AM::decodeNEONModImm(ConstVal->getZExtValue(), EltBits); 522 return (EltBits == 8 && EltVal == 0xff); 523}]>; 524 525//===----------------------------------------------------------------------===// 526// NEON load / store instructions 527//===----------------------------------------------------------------------===// 528 529// Use VLDM to load a Q register as a D register pair. 530// This is a pseudo instruction that is expanded to VLDMD after reg alloc. 531def VLDMQIA 532 : PseudoVFPLdStM<(outs QPR:$dst), (ins GPR:$Rn), 533 IIC_fpLoad_m, "", 534 [(set QPR:$dst, (v2f64 (load GPR:$Rn)))]>; 535 536// Use VSTM to store a Q register as a D register pair. 537// This is a pseudo instruction that is expanded to VSTMD after reg alloc. 538def VSTMQIA 539 : PseudoVFPLdStM<(outs), (ins QPR:$src, GPR:$Rn), 540 IIC_fpStore_m, "", 541 [(store (v2f64 QPR:$src), GPR:$Rn)]>; 542 543// Classes for VLD* pseudo-instructions with multi-register operands. 544// These are expanded to real instructions after register allocation. 545class VLDQPseudo<InstrItinClass itin> 546 : PseudoNLdSt<(outs QPR:$dst), (ins addrmode6:$addr), itin, "">; 547class VLDQWBPseudo<InstrItinClass itin> 548 : PseudoNLdSt<(outs QPR:$dst, GPR:$wb), 549 (ins addrmode6:$addr, am6offset:$offset), itin, 550 "$addr.addr = $wb">; 551class VLDQWBfixedPseudo<InstrItinClass itin> 552 : PseudoNLdSt<(outs QPR:$dst, GPR:$wb), 553 (ins addrmode6:$addr), itin, 554 "$addr.addr = $wb">; 555class VLDQWBregisterPseudo<InstrItinClass itin> 556 : PseudoNLdSt<(outs QPR:$dst, GPR:$wb), 557 (ins addrmode6:$addr, rGPR:$offset), itin, 558 "$addr.addr = $wb">; 559 560class VLDQQPseudo<InstrItinClass itin> 561 : PseudoNLdSt<(outs QQPR:$dst), (ins addrmode6:$addr), itin, "">; 562class VLDQQWBPseudo<InstrItinClass itin> 563 : PseudoNLdSt<(outs QQPR:$dst, GPR:$wb), 564 (ins addrmode6:$addr, am6offset:$offset), itin, 565 "$addr.addr = $wb">; 566class VLDQQWBfixedPseudo<InstrItinClass itin> 567 : PseudoNLdSt<(outs QQPR:$dst, GPR:$wb), 568 (ins addrmode6:$addr), itin, 569 "$addr.addr = $wb">; 570class VLDQQWBregisterPseudo<InstrItinClass itin> 571 : PseudoNLdSt<(outs QQPR:$dst, GPR:$wb), 572 (ins addrmode6:$addr, rGPR:$offset), itin, 573 "$addr.addr = $wb">; 574 575 576class VLDQQQQPseudo<InstrItinClass itin> 577 : PseudoNLdSt<(outs QQQQPR:$dst), (ins addrmode6:$addr, QQQQPR:$src),itin, 578 "$src = $dst">; 579class VLDQQQQWBPseudo<InstrItinClass itin> 580 : PseudoNLdSt<(outs QQQQPR:$dst, GPR:$wb), 581 (ins addrmode6:$addr, am6offset:$offset, QQQQPR:$src), itin, 582 "$addr.addr = $wb, $src = $dst">; 583 584let mayLoad = 1, neverHasSideEffects = 1, hasExtraDefRegAllocReq = 1 in { 585 586// VLD1 : Vector Load (multiple single elements) 587class VLD1D<bits<4> op7_4, string Dt> 588 : NLdSt<0,0b10,0b0111,op7_4, (outs VecListOneD:$Vd), 589 (ins addrmode6:$Rn), IIC_VLD1, 590 "vld1", Dt, "$Vd, $Rn", "", []> { 591 let Rm = 0b1111; 592 let Inst{4} = Rn{4}; 593 let DecoderMethod = "DecodeVLDInstruction"; 594} 595class VLD1Q<bits<4> op7_4, string Dt> 596 : NLdSt<0,0b10,0b1010,op7_4, (outs VecListTwoD:$Vd), 597 (ins addrmode6:$Rn), IIC_VLD1x2, 598 "vld1", Dt, "$Vd, $Rn", "", []> { 599 let Rm = 0b1111; 600 let Inst{5-4} = Rn{5-4}; 601 let DecoderMethod = "DecodeVLDInstruction"; 602} 603 604def VLD1d8 : VLD1D<{0,0,0,?}, "8">; 605def VLD1d16 : VLD1D<{0,1,0,?}, "16">; 606def VLD1d32 : VLD1D<{1,0,0,?}, "32">; 607def VLD1d64 : VLD1D<{1,1,0,?}, "64">; 608 609def VLD1q8 : VLD1Q<{0,0,?,?}, "8">; 610def VLD1q16 : VLD1Q<{0,1,?,?}, "16">; 611def VLD1q32 : VLD1Q<{1,0,?,?}, "32">; 612def VLD1q64 : VLD1Q<{1,1,?,?}, "64">; 613 614def VLD1q8Pseudo : VLDQPseudo<IIC_VLD1x2>; 615def VLD1q16Pseudo : VLDQPseudo<IIC_VLD1x2>; 616def VLD1q32Pseudo : VLDQPseudo<IIC_VLD1x2>; 617def VLD1q64Pseudo : VLDQPseudo<IIC_VLD1x2>; 618 619// ...with address register writeback: 620multiclass VLD1DWB<bits<4> op7_4, string Dt> { 621 def _fixed : NLdSt<0,0b10, 0b0111,op7_4, (outs VecListOneD:$Vd, GPR:$wb), 622 (ins addrmode6:$Rn), IIC_VLD1u, 623 "vld1", Dt, "$Vd, $Rn!", 624 "$Rn.addr = $wb", []> { 625 let Rm = 0b1101; // NLdSt will assign to the right encoding bits. 626 let Inst{4} = Rn{4}; 627 let DecoderMethod = "DecodeVLDInstruction"; 628 let AsmMatchConverter = "cvtVLDwbFixed"; 629 } 630 def _register : NLdSt<0,0b10,0b0111,op7_4, (outs VecListOneD:$Vd, GPR:$wb), 631 (ins addrmode6:$Rn, rGPR:$Rm), IIC_VLD1u, 632 "vld1", Dt, "$Vd, $Rn, $Rm", 633 "$Rn.addr = $wb", []> { 634 let Inst{4} = Rn{4}; 635 let DecoderMethod = "DecodeVLDInstruction"; 636 let AsmMatchConverter = "cvtVLDwbRegister"; 637 } 638} 639multiclass VLD1QWB<bits<4> op7_4, string Dt> { 640 def _fixed : NLdSt<0,0b10,0b1010,op7_4, (outs VecListTwoD:$Vd, GPR:$wb), 641 (ins addrmode6:$Rn), IIC_VLD1x2u, 642 "vld1", Dt, "$Vd, $Rn!", 643 "$Rn.addr = $wb", []> { 644 let Rm = 0b1101; // NLdSt will assign to the right encoding bits. 645 let Inst{5-4} = Rn{5-4}; 646 let DecoderMethod = "DecodeVLDInstruction"; 647 let AsmMatchConverter = "cvtVLDwbFixed"; 648 } 649 def _register : NLdSt<0,0b10,0b1010,op7_4, (outs VecListTwoD:$Vd, GPR:$wb), 650 (ins addrmode6:$Rn, rGPR:$Rm), IIC_VLD1x2u, 651 "vld1", Dt, "$Vd, $Rn, $Rm", 652 "$Rn.addr = $wb", []> { 653 let Inst{5-4} = Rn{5-4}; 654 let DecoderMethod = "DecodeVLDInstruction"; 655 let AsmMatchConverter = "cvtVLDwbRegister"; 656 } 657} 658 659defm VLD1d8wb : VLD1DWB<{0,0,0,?}, "8">; 660defm VLD1d16wb : VLD1DWB<{0,1,0,?}, "16">; 661defm VLD1d32wb : VLD1DWB<{1,0,0,?}, "32">; 662defm VLD1d64wb : VLD1DWB<{1,1,0,?}, "64">; 663defm VLD1q8wb : VLD1QWB<{0,0,?,?}, "8">; 664defm VLD1q16wb : VLD1QWB<{0,1,?,?}, "16">; 665defm VLD1q32wb : VLD1QWB<{1,0,?,?}, "32">; 666defm VLD1q64wb : VLD1QWB<{1,1,?,?}, "64">; 667 668def VLD1q8PseudoWB_fixed : VLDQWBfixedPseudo<IIC_VLD1x2u>; 669def VLD1q16PseudoWB_fixed : VLDQWBfixedPseudo<IIC_VLD1x2u>; 670def VLD1q32PseudoWB_fixed : VLDQWBfixedPseudo<IIC_VLD1x2u>; 671def VLD1q64PseudoWB_fixed : VLDQWBfixedPseudo<IIC_VLD1x2u>; 672def VLD1q8PseudoWB_register : VLDQWBregisterPseudo<IIC_VLD1x2u>; 673def VLD1q16PseudoWB_register : VLDQWBregisterPseudo<IIC_VLD1x2u>; 674def VLD1q32PseudoWB_register : VLDQWBregisterPseudo<IIC_VLD1x2u>; 675def VLD1q64PseudoWB_register : VLDQWBregisterPseudo<IIC_VLD1x2u>; 676 677// ...with 3 registers 678class VLD1D3<bits<4> op7_4, string Dt> 679 : NLdSt<0,0b10,0b0110,op7_4, (outs VecListThreeD:$Vd), 680 (ins addrmode6:$Rn), IIC_VLD1x3, "vld1", Dt, 681 "$Vd, $Rn", "", []> { 682 let Rm = 0b1111; 683 let Inst{4} = Rn{4}; 684 let DecoderMethod = "DecodeVLDInstruction"; 685} 686multiclass VLD1D3WB<bits<4> op7_4, string Dt> { 687 def _fixed : NLdSt<0,0b10,0b0110, op7_4, (outs VecListThreeD:$Vd, GPR:$wb), 688 (ins addrmode6:$Rn), IIC_VLD1x2u, 689 "vld1", Dt, "$Vd, $Rn!", 690 "$Rn.addr = $wb", []> { 691 let Rm = 0b1101; // NLdSt will assign to the right encoding bits. 692 let Inst{4} = Rn{4}; 693 let DecoderMethod = "DecodeVLDInstruction"; 694 let AsmMatchConverter = "cvtVLDwbFixed"; 695 } 696 def _register : NLdSt<0,0b10,0b0110,op7_4, (outs VecListThreeD:$Vd, GPR:$wb), 697 (ins addrmode6:$Rn, rGPR:$Rm), IIC_VLD1x2u, 698 "vld1", Dt, "$Vd, $Rn, $Rm", 699 "$Rn.addr = $wb", []> { 700 let Inst{4} = Rn{4}; 701 let DecoderMethod = "DecodeVLDInstruction"; 702 let AsmMatchConverter = "cvtVLDwbRegister"; 703 } 704} 705 706def VLD1d8T : VLD1D3<{0,0,0,?}, "8">; 707def VLD1d16T : VLD1D3<{0,1,0,?}, "16">; 708def VLD1d32T : VLD1D3<{1,0,0,?}, "32">; 709def VLD1d64T : VLD1D3<{1,1,0,?}, "64">; 710 711defm VLD1d8Twb : VLD1D3WB<{0,0,0,?}, "8">; 712defm VLD1d16Twb : VLD1D3WB<{0,1,0,?}, "16">; 713defm VLD1d32Twb : VLD1D3WB<{1,0,0,?}, "32">; 714defm VLD1d64Twb : VLD1D3WB<{1,1,0,?}, "64">; 715 716def VLD1d64TPseudo : VLDQQPseudo<IIC_VLD1x3>; 717 718// ...with 4 registers 719class VLD1D4<bits<4> op7_4, string Dt> 720 : NLdSt<0, 0b10, 0b0010, op7_4, (outs VecListFourD:$Vd), 721 (ins addrmode6:$Rn), IIC_VLD1x4, "vld1", Dt, 722 "$Vd, $Rn", "", []> { 723 let Rm = 0b1111; 724 let Inst{5-4} = Rn{5-4}; 725 let DecoderMethod = "DecodeVLDInstruction"; 726} 727multiclass VLD1D4WB<bits<4> op7_4, string Dt> { 728 def _fixed : NLdSt<0,0b10,0b0010, op7_4, (outs VecListFourD:$Vd, GPR:$wb), 729 (ins addrmode6:$Rn), IIC_VLD1x2u, 730 "vld1", Dt, "$Vd, $Rn!", 731 "$Rn.addr = $wb", []> { 732 let Rm = 0b1101; // NLdSt will assign to the right encoding bits. 733 let Inst{5-4} = Rn{5-4}; 734 let DecoderMethod = "DecodeVLDInstruction"; 735 let AsmMatchConverter = "cvtVLDwbFixed"; 736 } 737 def _register : NLdSt<0,0b10,0b0010,op7_4, (outs VecListFourD:$Vd, GPR:$wb), 738 (ins addrmode6:$Rn, rGPR:$Rm), IIC_VLD1x2u, 739 "vld1", Dt, "$Vd, $Rn, $Rm", 740 "$Rn.addr = $wb", []> { 741 let Inst{5-4} = Rn{5-4}; 742 let DecoderMethod = "DecodeVLDInstruction"; 743 let AsmMatchConverter = "cvtVLDwbRegister"; 744 } 745} 746 747def VLD1d8Q : VLD1D4<{0,0,?,?}, "8">; 748def VLD1d16Q : VLD1D4<{0,1,?,?}, "16">; 749def VLD1d32Q : VLD1D4<{1,0,?,?}, "32">; 750def VLD1d64Q : VLD1D4<{1,1,?,?}, "64">; 751 752defm VLD1d8Qwb : VLD1D4WB<{0,0,?,?}, "8">; 753defm VLD1d16Qwb : VLD1D4WB<{0,1,?,?}, "16">; 754defm VLD1d32Qwb : VLD1D4WB<{1,0,?,?}, "32">; 755defm VLD1d64Qwb : VLD1D4WB<{1,1,?,?}, "64">; 756 757def VLD1d64QPseudo : VLDQQPseudo<IIC_VLD1x4>; 758 759// VLD2 : Vector Load (multiple 2-element structures) 760class VLD2<bits<4> op11_8, bits<4> op7_4, string Dt, RegisterOperand VdTy, 761 InstrItinClass itin> 762 : NLdSt<0, 0b10, op11_8, op7_4, (outs VdTy:$Vd), 763 (ins addrmode6:$Rn), itin, 764 "vld2", Dt, "$Vd, $Rn", "", []> { 765 let Rm = 0b1111; 766 let Inst{5-4} = Rn{5-4}; 767 let DecoderMethod = "DecodeVLDInstruction"; 768} 769 770def VLD2d8 : VLD2<0b1000, {0,0,?,?}, "8", VecListTwoD, IIC_VLD2>; 771def VLD2d16 : VLD2<0b1000, {0,1,?,?}, "16", VecListTwoD, IIC_VLD2>; 772def VLD2d32 : VLD2<0b1000, {1,0,?,?}, "32", VecListTwoD, IIC_VLD2>; 773 774def VLD2q8 : VLD2<0b0011, {0,0,?,?}, "8", VecListFourD, IIC_VLD2x2>; 775def VLD2q16 : VLD2<0b0011, {0,1,?,?}, "16", VecListFourD, IIC_VLD2x2>; 776def VLD2q32 : VLD2<0b0011, {1,0,?,?}, "32", VecListFourD, IIC_VLD2x2>; 777 778def VLD2d8Pseudo : VLDQPseudo<IIC_VLD2>; 779def VLD2d16Pseudo : VLDQPseudo<IIC_VLD2>; 780def VLD2d32Pseudo : VLDQPseudo<IIC_VLD2>; 781 782def VLD2q8Pseudo : VLDQQPseudo<IIC_VLD2x2>; 783def VLD2q16Pseudo : VLDQQPseudo<IIC_VLD2x2>; 784def VLD2q32Pseudo : VLDQQPseudo<IIC_VLD2x2>; 785 786// ...with address register writeback: 787multiclass VLD2WB<bits<4> op11_8, bits<4> op7_4, string Dt, 788 RegisterOperand VdTy, InstrItinClass itin> { 789 def _fixed : NLdSt<0, 0b10, op11_8, op7_4, (outs VdTy:$Vd, GPR:$wb), 790 (ins addrmode6:$Rn), itin, 791 "vld2", Dt, "$Vd, $Rn!", 792 "$Rn.addr = $wb", []> { 793 let Rm = 0b1101; // NLdSt will assign to the right encoding bits. 794 let Inst{5-4} = Rn{5-4}; 795 let DecoderMethod = "DecodeVLDInstruction"; 796 let AsmMatchConverter = "cvtVLDwbFixed"; 797 } 798 def _register : NLdSt<0, 0b10, op11_8, op7_4, (outs VdTy:$Vd, GPR:$wb), 799 (ins addrmode6:$Rn, rGPR:$Rm), itin, 800 "vld2", Dt, "$Vd, $Rn, $Rm", 801 "$Rn.addr = $wb", []> { 802 let Inst{5-4} = Rn{5-4}; 803 let DecoderMethod = "DecodeVLDInstruction"; 804 let AsmMatchConverter = "cvtVLDwbRegister"; 805 } 806} 807 808defm VLD2d8wb : VLD2WB<0b1000, {0,0,?,?}, "8", VecListTwoD, IIC_VLD2u>; 809defm VLD2d16wb : VLD2WB<0b1000, {0,1,?,?}, "16", VecListTwoD, IIC_VLD2u>; 810defm VLD2d32wb : VLD2WB<0b1000, {1,0,?,?}, "32", VecListTwoD, IIC_VLD2u>; 811 812defm VLD2q8wb : VLD2WB<0b0011, {0,0,?,?}, "8", VecListFourD, IIC_VLD2x2u>; 813defm VLD2q16wb : VLD2WB<0b0011, {0,1,?,?}, "16", VecListFourD, IIC_VLD2x2u>; 814defm VLD2q32wb : VLD2WB<0b0011, {1,0,?,?}, "32", VecListFourD, IIC_VLD2x2u>; 815 816def VLD2d8PseudoWB_fixed : VLDQWBfixedPseudo<IIC_VLD2u>; 817def VLD2d16PseudoWB_fixed : VLDQWBfixedPseudo<IIC_VLD2u>; 818def VLD2d32PseudoWB_fixed : VLDQWBfixedPseudo<IIC_VLD2u>; 819def VLD2d8PseudoWB_register : VLDQWBregisterPseudo<IIC_VLD2u>; 820def VLD2d16PseudoWB_register : VLDQWBregisterPseudo<IIC_VLD2u>; 821def VLD2d32PseudoWB_register : VLDQWBregisterPseudo<IIC_VLD2u>; 822 823def VLD2q8PseudoWB_fixed : VLDQQWBfixedPseudo<IIC_VLD2x2u>; 824def VLD2q16PseudoWB_fixed : VLDQQWBfixedPseudo<IIC_VLD2x2u>; 825def VLD2q32PseudoWB_fixed : VLDQQWBfixedPseudo<IIC_VLD2x2u>; 826def VLD2q8PseudoWB_register : VLDQQWBregisterPseudo<IIC_VLD2x2u>; 827def VLD2q16PseudoWB_register : VLDQQWBregisterPseudo<IIC_VLD2x2u>; 828def VLD2q32PseudoWB_register : VLDQQWBregisterPseudo<IIC_VLD2x2u>; 829 830// ...with double-spaced registers 831def VLD2b8 : VLD2<0b1001, {0,0,?,?}, "8", VecListTwoQ, IIC_VLD2>; 832def VLD2b16 : VLD2<0b1001, {0,1,?,?}, "16", VecListTwoQ, IIC_VLD2>; 833def VLD2b32 : VLD2<0b1001, {1,0,?,?}, "32", VecListTwoQ, IIC_VLD2>; 834defm VLD2b8wb : VLD2WB<0b1001, {0,0,?,?}, "8", VecListTwoQ, IIC_VLD2u>; 835defm VLD2b16wb : VLD2WB<0b1001, {0,1,?,?}, "16", VecListTwoQ, IIC_VLD2u>; 836defm VLD2b32wb : VLD2WB<0b1001, {1,0,?,?}, "32", VecListTwoQ, IIC_VLD2u>; 837 838// VLD3 : Vector Load (multiple 3-element structures) 839class VLD3D<bits<4> op11_8, bits<4> op7_4, string Dt> 840 : NLdSt<0, 0b10, op11_8, op7_4, (outs DPR:$Vd, DPR:$dst2, DPR:$dst3), 841 (ins addrmode6:$Rn), IIC_VLD3, 842 "vld3", Dt, "\\{$Vd, $dst2, $dst3\\}, $Rn", "", []> { 843 let Rm = 0b1111; 844 let Inst{4} = Rn{4}; 845 let DecoderMethod = "DecodeVLDInstruction"; 846} 847 848def VLD3d8 : VLD3D<0b0100, {0,0,0,?}, "8">; 849def VLD3d16 : VLD3D<0b0100, {0,1,0,?}, "16">; 850def VLD3d32 : VLD3D<0b0100, {1,0,0,?}, "32">; 851 852def VLD3d8Pseudo : VLDQQPseudo<IIC_VLD3>; 853def VLD3d16Pseudo : VLDQQPseudo<IIC_VLD3>; 854def VLD3d32Pseudo : VLDQQPseudo<IIC_VLD3>; 855 856// ...with address register writeback: 857class VLD3DWB<bits<4> op11_8, bits<4> op7_4, string Dt> 858 : NLdSt<0, 0b10, op11_8, op7_4, 859 (outs DPR:$Vd, DPR:$dst2, DPR:$dst3, GPR:$wb), 860 (ins addrmode6:$Rn, am6offset:$Rm), IIC_VLD3u, 861 "vld3", Dt, "\\{$Vd, $dst2, $dst3\\}, $Rn$Rm", 862 "$Rn.addr = $wb", []> { 863 let Inst{4} = Rn{4}; 864 let DecoderMethod = "DecodeVLDInstruction"; 865} 866 867def VLD3d8_UPD : VLD3DWB<0b0100, {0,0,0,?}, "8">; 868def VLD3d16_UPD : VLD3DWB<0b0100, {0,1,0,?}, "16">; 869def VLD3d32_UPD : VLD3DWB<0b0100, {1,0,0,?}, "32">; 870 871def VLD3d8Pseudo_UPD : VLDQQWBPseudo<IIC_VLD3u>; 872def VLD3d16Pseudo_UPD : VLDQQWBPseudo<IIC_VLD3u>; 873def VLD3d32Pseudo_UPD : VLDQQWBPseudo<IIC_VLD3u>; 874 875// ...with double-spaced registers: 876def VLD3q8 : VLD3D<0b0101, {0,0,0,?}, "8">; 877def VLD3q16 : VLD3D<0b0101, {0,1,0,?}, "16">; 878def VLD3q32 : VLD3D<0b0101, {1,0,0,?}, "32">; 879def VLD3q8_UPD : VLD3DWB<0b0101, {0,0,0,?}, "8">; 880def VLD3q16_UPD : VLD3DWB<0b0101, {0,1,0,?}, "16">; 881def VLD3q32_UPD : VLD3DWB<0b0101, {1,0,0,?}, "32">; 882 883def VLD3q8Pseudo_UPD : VLDQQQQWBPseudo<IIC_VLD3u>; 884def VLD3q16Pseudo_UPD : VLDQQQQWBPseudo<IIC_VLD3u>; 885def VLD3q32Pseudo_UPD : VLDQQQQWBPseudo<IIC_VLD3u>; 886 887// ...alternate versions to be allocated odd register numbers: 888def VLD3q8oddPseudo : VLDQQQQPseudo<IIC_VLD3>; 889def VLD3q16oddPseudo : VLDQQQQPseudo<IIC_VLD3>; 890def VLD3q32oddPseudo : VLDQQQQPseudo<IIC_VLD3>; 891 892def VLD3q8oddPseudo_UPD : VLDQQQQWBPseudo<IIC_VLD3u>; 893def VLD3q16oddPseudo_UPD : VLDQQQQWBPseudo<IIC_VLD3u>; 894def VLD3q32oddPseudo_UPD : VLDQQQQWBPseudo<IIC_VLD3u>; 895 896// VLD4 : Vector Load (multiple 4-element structures) 897class VLD4D<bits<4> op11_8, bits<4> op7_4, string Dt> 898 : NLdSt<0, 0b10, op11_8, op7_4, 899 (outs DPR:$Vd, DPR:$dst2, DPR:$dst3, DPR:$dst4), 900 (ins addrmode6:$Rn), IIC_VLD4, 901 "vld4", Dt, "\\{$Vd, $dst2, $dst3, $dst4\\}, $Rn", "", []> { 902 let Rm = 0b1111; 903 let Inst{5-4} = Rn{5-4}; 904 let DecoderMethod = "DecodeVLDInstruction"; 905} 906 907def VLD4d8 : VLD4D<0b0000, {0,0,?,?}, "8">; 908def VLD4d16 : VLD4D<0b0000, {0,1,?,?}, "16">; 909def VLD4d32 : VLD4D<0b0000, {1,0,?,?}, "32">; 910 911def VLD4d8Pseudo : VLDQQPseudo<IIC_VLD4>; 912def VLD4d16Pseudo : VLDQQPseudo<IIC_VLD4>; 913def VLD4d32Pseudo : VLDQQPseudo<IIC_VLD4>; 914 915// ...with address register writeback: 916class VLD4DWB<bits<4> op11_8, bits<4> op7_4, string Dt> 917 : NLdSt<0, 0b10, op11_8, op7_4, 918 (outs DPR:$Vd, DPR:$dst2, DPR:$dst3, DPR:$dst4, GPR:$wb), 919 (ins addrmode6:$Rn, am6offset:$Rm), IIC_VLD4u, 920 "vld4", Dt, "\\{$Vd, $dst2, $dst3, $dst4\\}, $Rn$Rm", 921 "$Rn.addr = $wb", []> { 922 let Inst{5-4} = Rn{5-4}; 923 let DecoderMethod = "DecodeVLDInstruction"; 924} 925 926def VLD4d8_UPD : VLD4DWB<0b0000, {0,0,?,?}, "8">; 927def VLD4d16_UPD : VLD4DWB<0b0000, {0,1,?,?}, "16">; 928def VLD4d32_UPD : VLD4DWB<0b0000, {1,0,?,?}, "32">; 929 930def VLD4d8Pseudo_UPD : VLDQQWBPseudo<IIC_VLD4u>; 931def VLD4d16Pseudo_UPD : VLDQQWBPseudo<IIC_VLD4u>; 932def VLD4d32Pseudo_UPD : VLDQQWBPseudo<IIC_VLD4u>; 933 934// ...with double-spaced registers: 935def VLD4q8 : VLD4D<0b0001, {0,0,?,?}, "8">; 936def VLD4q16 : VLD4D<0b0001, {0,1,?,?}, "16">; 937def VLD4q32 : VLD4D<0b0001, {1,0,?,?}, "32">; 938def VLD4q8_UPD : VLD4DWB<0b0001, {0,0,?,?}, "8">; 939def VLD4q16_UPD : VLD4DWB<0b0001, {0,1,?,?}, "16">; 940def VLD4q32_UPD : VLD4DWB<0b0001, {1,0,?,?}, "32">; 941 942def VLD4q8Pseudo_UPD : VLDQQQQWBPseudo<IIC_VLD4u>; 943def VLD4q16Pseudo_UPD : VLDQQQQWBPseudo<IIC_VLD4u>; 944def VLD4q32Pseudo_UPD : VLDQQQQWBPseudo<IIC_VLD4u>; 945 946// ...alternate versions to be allocated odd register numbers: 947def VLD4q8oddPseudo : VLDQQQQPseudo<IIC_VLD4>; 948def VLD4q16oddPseudo : VLDQQQQPseudo<IIC_VLD4>; 949def VLD4q32oddPseudo : VLDQQQQPseudo<IIC_VLD4>; 950 951def VLD4q8oddPseudo_UPD : VLDQQQQWBPseudo<IIC_VLD4u>; 952def VLD4q16oddPseudo_UPD : VLDQQQQWBPseudo<IIC_VLD4u>; 953def VLD4q32oddPseudo_UPD : VLDQQQQWBPseudo<IIC_VLD4u>; 954 955} // mayLoad = 1, neverHasSideEffects = 1, hasExtraDefRegAllocReq = 1 956 957// Classes for VLD*LN pseudo-instructions with multi-register operands. 958// These are expanded to real instructions after register allocation. 959class VLDQLNPseudo<InstrItinClass itin> 960 : PseudoNLdSt<(outs QPR:$dst), 961 (ins addrmode6:$addr, QPR:$src, nohash_imm:$lane), 962 itin, "$src = $dst">; 963class VLDQLNWBPseudo<InstrItinClass itin> 964 : PseudoNLdSt<(outs QPR:$dst, GPR:$wb), 965 (ins addrmode6:$addr, am6offset:$offset, QPR:$src, 966 nohash_imm:$lane), itin, "$addr.addr = $wb, $src = $dst">; 967class VLDQQLNPseudo<InstrItinClass itin> 968 : PseudoNLdSt<(outs QQPR:$dst), 969 (ins addrmode6:$addr, QQPR:$src, nohash_imm:$lane), 970 itin, "$src = $dst">; 971class VLDQQLNWBPseudo<InstrItinClass itin> 972 : PseudoNLdSt<(outs QQPR:$dst, GPR:$wb), 973 (ins addrmode6:$addr, am6offset:$offset, QQPR:$src, 974 nohash_imm:$lane), itin, "$addr.addr = $wb, $src = $dst">; 975class VLDQQQQLNPseudo<InstrItinClass itin> 976 : PseudoNLdSt<(outs QQQQPR:$dst), 977 (ins addrmode6:$addr, QQQQPR:$src, nohash_imm:$lane), 978 itin, "$src = $dst">; 979class VLDQQQQLNWBPseudo<InstrItinClass itin> 980 : PseudoNLdSt<(outs QQQQPR:$dst, GPR:$wb), 981 (ins addrmode6:$addr, am6offset:$offset, QQQQPR:$src, 982 nohash_imm:$lane), itin, "$addr.addr = $wb, $src = $dst">; 983 984// VLD1LN : Vector Load (single element to one lane) 985class VLD1LN<bits<4> op11_8, bits<4> op7_4, string Dt, ValueType Ty, 986 PatFrag LoadOp> 987 : NLdStLn<1, 0b10, op11_8, op7_4, (outs DPR:$Vd), 988 (ins addrmode6:$Rn, DPR:$src, nohash_imm:$lane), 989 IIC_VLD1ln, "vld1", Dt, "\\{$Vd[$lane]\\}, $Rn", 990 "$src = $Vd", 991 [(set DPR:$Vd, (vector_insert (Ty DPR:$src), 992 (i32 (LoadOp addrmode6:$Rn)), 993 imm:$lane))]> { 994 let Rm = 0b1111; 995 let DecoderMethod = "DecodeVLD1LN"; 996} 997class VLD1LN32<bits<4> op11_8, bits<4> op7_4, string Dt, ValueType Ty, 998 PatFrag LoadOp> 999 : NLdStLn<1, 0b10, op11_8, op7_4, (outs DPR:$Vd), 1000 (ins addrmode6oneL32:$Rn, DPR:$src, nohash_imm:$lane), 1001 IIC_VLD1ln, "vld1", Dt, "\\{$Vd[$lane]\\}, $Rn", 1002 "$src = $Vd", 1003 [(set DPR:$Vd, (vector_insert (Ty DPR:$src), 1004 (i32 (LoadOp addrmode6oneL32:$Rn)), 1005 imm:$lane))]> { 1006 let Rm = 0b1111; 1007 let DecoderMethod = "DecodeVLD1LN"; 1008} 1009class VLD1QLNPseudo<ValueType Ty, PatFrag LoadOp> : VLDQLNPseudo<IIC_VLD1ln> { 1010 let Pattern = [(set QPR:$dst, (vector_insert (Ty QPR:$src), 1011 (i32 (LoadOp addrmode6:$addr)), 1012 imm:$lane))]; 1013} 1014 1015def VLD1LNd8 : VLD1LN<0b0000, {?,?,?,0}, "8", v8i8, extloadi8> { 1016 let Inst{7-5} = lane{2-0}; 1017} 1018def VLD1LNd16 : VLD1LN<0b0100, {?,?,0,?}, "16", v4i16, extloadi16> { 1019 let Inst{7-6} = lane{1-0}; 1020 let Inst{5-4} = Rn{5-4}; 1021} 1022def VLD1LNd32 : VLD1LN32<0b1000, {?,0,?,?}, "32", v2i32, load> { 1023 let Inst{7} = lane{0}; 1024 let Inst{5-4} = Rn{5-4}; 1025} 1026 1027def VLD1LNq8Pseudo : VLD1QLNPseudo<v16i8, extloadi8>; 1028def VLD1LNq16Pseudo : VLD1QLNPseudo<v8i16, extloadi16>; 1029def VLD1LNq32Pseudo : VLD1QLNPseudo<v4i32, load>; 1030 1031def : Pat<(vector_insert (v2f32 DPR:$src), 1032 (f32 (load addrmode6:$addr)), imm:$lane), 1033 (VLD1LNd32 addrmode6:$addr, DPR:$src, imm:$lane)>; 1034def : Pat<(vector_insert (v4f32 QPR:$src), 1035 (f32 (load addrmode6:$addr)), imm:$lane), 1036 (VLD1LNq32Pseudo addrmode6:$addr, QPR:$src, imm:$lane)>; 1037 1038let mayLoad = 1, neverHasSideEffects = 1, hasExtraDefRegAllocReq = 1 in { 1039 1040// ...with address register writeback: 1041class VLD1LNWB<bits<4> op11_8, bits<4> op7_4, string Dt> 1042 : NLdStLn<1, 0b10, op11_8, op7_4, (outs DPR:$Vd, GPR:$wb), 1043 (ins addrmode6:$Rn, am6offset:$Rm, 1044 DPR:$src, nohash_imm:$lane), IIC_VLD1lnu, "vld1", Dt, 1045 "\\{$Vd[$lane]\\}, $Rn$Rm", 1046 "$src = $Vd, $Rn.addr = $wb", []> { 1047 let DecoderMethod = "DecodeVLD1LN"; 1048} 1049 1050def VLD1LNd8_UPD : VLD1LNWB<0b0000, {?,?,?,0}, "8"> { 1051 let Inst{7-5} = lane{2-0}; 1052} 1053def VLD1LNd16_UPD : VLD1LNWB<0b0100, {?,?,0,?}, "16"> { 1054 let Inst{7-6} = lane{1-0}; 1055 let Inst{4} = Rn{4}; 1056} 1057def VLD1LNd32_UPD : VLD1LNWB<0b1000, {?,0,?,?}, "32"> { 1058 let Inst{7} = lane{0}; 1059 let Inst{5} = Rn{4}; 1060 let Inst{4} = Rn{4}; 1061} 1062 1063def VLD1LNq8Pseudo_UPD : VLDQLNWBPseudo<IIC_VLD1lnu>; 1064def VLD1LNq16Pseudo_UPD : VLDQLNWBPseudo<IIC_VLD1lnu>; 1065def VLD1LNq32Pseudo_UPD : VLDQLNWBPseudo<IIC_VLD1lnu>; 1066 1067// VLD2LN : Vector Load (single 2-element structure to one lane) 1068class VLD2LN<bits<4> op11_8, bits<4> op7_4, string Dt> 1069 : NLdStLn<1, 0b10, op11_8, op7_4, (outs DPR:$Vd, DPR:$dst2), 1070 (ins addrmode6:$Rn, DPR:$src1, DPR:$src2, nohash_imm:$lane), 1071 IIC_VLD2ln, "vld2", Dt, "\\{$Vd[$lane], $dst2[$lane]\\}, $Rn", 1072 "$src1 = $Vd, $src2 = $dst2", []> { 1073 let Rm = 0b1111; 1074 let Inst{4} = Rn{4}; 1075 let DecoderMethod = "DecodeVLD2LN"; 1076} 1077 1078def VLD2LNd8 : VLD2LN<0b0001, {?,?,?,?}, "8"> { 1079 let Inst{7-5} = lane{2-0}; 1080} 1081def VLD2LNd16 : VLD2LN<0b0101, {?,?,0,?}, "16"> { 1082 let Inst{7-6} = lane{1-0}; 1083} 1084def VLD2LNd32 : VLD2LN<0b1001, {?,0,0,?}, "32"> { 1085 let Inst{7} = lane{0}; 1086} 1087 1088def VLD2LNd8Pseudo : VLDQLNPseudo<IIC_VLD2ln>; 1089def VLD2LNd16Pseudo : VLDQLNPseudo<IIC_VLD2ln>; 1090def VLD2LNd32Pseudo : VLDQLNPseudo<IIC_VLD2ln>; 1091 1092// ...with double-spaced registers: 1093def VLD2LNq16 : VLD2LN<0b0101, {?,?,1,?}, "16"> { 1094 let Inst{7-6} = lane{1-0}; 1095} 1096def VLD2LNq32 : VLD2LN<0b1001, {?,1,0,?}, "32"> { 1097 let Inst{7} = lane{0}; 1098} 1099 1100def VLD2LNq16Pseudo : VLDQQLNPseudo<IIC_VLD2ln>; 1101def VLD2LNq32Pseudo : VLDQQLNPseudo<IIC_VLD2ln>; 1102 1103// ...with address register writeback: 1104class VLD2LNWB<bits<4> op11_8, bits<4> op7_4, string Dt> 1105 : NLdStLn<1, 0b10, op11_8, op7_4, (outs DPR:$Vd, DPR:$dst2, GPR:$wb), 1106 (ins addrmode6:$Rn, am6offset:$Rm, 1107 DPR:$src1, DPR:$src2, nohash_imm:$lane), IIC_VLD2lnu, "vld2", Dt, 1108 "\\{$Vd[$lane], $dst2[$lane]\\}, $Rn$Rm", 1109 "$src1 = $Vd, $src2 = $dst2, $Rn.addr = $wb", []> { 1110 let Inst{4} = Rn{4}; 1111 let DecoderMethod = "DecodeVLD2LN"; 1112} 1113 1114def VLD2LNd8_UPD : VLD2LNWB<0b0001, {?,?,?,?}, "8"> { 1115 let Inst{7-5} = lane{2-0}; 1116} 1117def VLD2LNd16_UPD : VLD2LNWB<0b0101, {?,?,0,?}, "16"> { 1118 let Inst{7-6} = lane{1-0}; 1119} 1120def VLD2LNd32_UPD : VLD2LNWB<0b1001, {?,0,0,?}, "32"> { 1121 let Inst{7} = lane{0}; 1122} 1123 1124def VLD2LNd8Pseudo_UPD : VLDQLNWBPseudo<IIC_VLD2lnu>; 1125def VLD2LNd16Pseudo_UPD : VLDQLNWBPseudo<IIC_VLD2lnu>; 1126def VLD2LNd32Pseudo_UPD : VLDQLNWBPseudo<IIC_VLD2lnu>; 1127 1128def VLD2LNq16_UPD : VLD2LNWB<0b0101, {?,?,1,?}, "16"> { 1129 let Inst{7-6} = lane{1-0}; 1130} 1131def VLD2LNq32_UPD : VLD2LNWB<0b1001, {?,1,0,?}, "32"> { 1132 let Inst{7} = lane{0}; 1133} 1134 1135def VLD2LNq16Pseudo_UPD : VLDQQLNWBPseudo<IIC_VLD2lnu>; 1136def VLD2LNq32Pseudo_UPD : VLDQQLNWBPseudo<IIC_VLD2lnu>; 1137 1138// VLD3LN : Vector Load (single 3-element structure to one lane) 1139class VLD3LN<bits<4> op11_8, bits<4> op7_4, string Dt> 1140 : NLdStLn<1, 0b10, op11_8, op7_4, (outs DPR:$Vd, DPR:$dst2, DPR:$dst3), 1141 (ins addrmode6:$Rn, DPR:$src1, DPR:$src2, DPR:$src3, 1142 nohash_imm:$lane), IIC_VLD3ln, "vld3", Dt, 1143 "\\{$Vd[$lane], $dst2[$lane], $dst3[$lane]\\}, $Rn", 1144 "$src1 = $Vd, $src2 = $dst2, $src3 = $dst3", []> { 1145 let Rm = 0b1111; 1146 let DecoderMethod = "DecodeVLD3LN"; 1147} 1148 1149def VLD3LNd8 : VLD3LN<0b0010, {?,?,?,0}, "8"> { 1150 let Inst{7-5} = lane{2-0}; 1151} 1152def VLD3LNd16 : VLD3LN<0b0110, {?,?,0,0}, "16"> { 1153 let Inst{7-6} = lane{1-0}; 1154} 1155def VLD3LNd32 : VLD3LN<0b1010, {?,0,0,0}, "32"> { 1156 let Inst{7} = lane{0}; 1157} 1158 1159def VLD3LNd8Pseudo : VLDQQLNPseudo<IIC_VLD3ln>; 1160def VLD3LNd16Pseudo : VLDQQLNPseudo<IIC_VLD3ln>; 1161def VLD3LNd32Pseudo : VLDQQLNPseudo<IIC_VLD3ln>; 1162 1163// ...with double-spaced registers: 1164def VLD3LNq16 : VLD3LN<0b0110, {?,?,1,0}, "16"> { 1165 let Inst{7-6} = lane{1-0}; 1166} 1167def VLD3LNq32 : VLD3LN<0b1010, {?,1,0,0}, "32"> { 1168 let Inst{7} = lane{0}; 1169} 1170 1171def VLD3LNq16Pseudo : VLDQQQQLNPseudo<IIC_VLD3ln>; 1172def VLD3LNq32Pseudo : VLDQQQQLNPseudo<IIC_VLD3ln>; 1173 1174// ...with address register writeback: 1175class VLD3LNWB<bits<4> op11_8, bits<4> op7_4, string Dt> 1176 : NLdStLn<1, 0b10, op11_8, op7_4, 1177 (outs DPR:$Vd, DPR:$dst2, DPR:$dst3, GPR:$wb), 1178 (ins addrmode6:$Rn, am6offset:$Rm, 1179 DPR:$src1, DPR:$src2, DPR:$src3, nohash_imm:$lane), 1180 IIC_VLD3lnu, "vld3", Dt, 1181 "\\{$Vd[$lane], $dst2[$lane], $dst3[$lane]\\}, $Rn$Rm", 1182 "$src1 = $Vd, $src2 = $dst2, $src3 = $dst3, $Rn.addr = $wb", 1183 []> { 1184 let DecoderMethod = "DecodeVLD3LN"; 1185} 1186 1187def VLD3LNd8_UPD : VLD3LNWB<0b0010, {?,?,?,0}, "8"> { 1188 let Inst{7-5} = lane{2-0}; 1189} 1190def VLD3LNd16_UPD : VLD3LNWB<0b0110, {?,?,0,0}, "16"> { 1191 let Inst{7-6} = lane{1-0}; 1192} 1193def VLD3LNd32_UPD : VLD3LNWB<0b1010, {?,0,0,0}, "32"> { 1194 let Inst{7} = lane{0}; 1195} 1196 1197def VLD3LNd8Pseudo_UPD : VLDQQLNWBPseudo<IIC_VLD3lnu>; 1198def VLD3LNd16Pseudo_UPD : VLDQQLNWBPseudo<IIC_VLD3lnu>; 1199def VLD3LNd32Pseudo_UPD : VLDQQLNWBPseudo<IIC_VLD3lnu>; 1200 1201def VLD3LNq16_UPD : VLD3LNWB<0b0110, {?,?,1,0}, "16"> { 1202 let Inst{7-6} = lane{1-0}; 1203} 1204def VLD3LNq32_UPD : VLD3LNWB<0b1010, {?,1,0,0}, "32"> { 1205 let Inst{7} = lane{0}; 1206} 1207 1208def VLD3LNq16Pseudo_UPD : VLDQQQQLNWBPseudo<IIC_VLD3lnu>; 1209def VLD3LNq32Pseudo_UPD : VLDQQQQLNWBPseudo<IIC_VLD3lnu>; 1210 1211// VLD4LN : Vector Load (single 4-element structure to one lane) 1212class VLD4LN<bits<4> op11_8, bits<4> op7_4, string Dt> 1213 : NLdStLn<1, 0b10, op11_8, op7_4, 1214 (outs DPR:$Vd, DPR:$dst2, DPR:$dst3, DPR:$dst4), 1215 (ins addrmode6:$Rn, DPR:$src1, DPR:$src2, DPR:$src3, DPR:$src4, 1216 nohash_imm:$lane), IIC_VLD4ln, "vld4", Dt, 1217 "\\{$Vd[$lane], $dst2[$lane], $dst3[$lane], $dst4[$lane]\\}, $Rn", 1218 "$src1 = $Vd, $src2 = $dst2, $src3 = $dst3, $src4 = $dst4", []> { 1219 let Rm = 0b1111; 1220 let Inst{4} = Rn{4}; 1221 let DecoderMethod = "DecodeVLD4LN"; 1222} 1223 1224def VLD4LNd8 : VLD4LN<0b0011, {?,?,?,?}, "8"> { 1225 let Inst{7-5} = lane{2-0}; 1226} 1227def VLD4LNd16 : VLD4LN<0b0111, {?,?,0,?}, "16"> { 1228 let Inst{7-6} = lane{1-0}; 1229} 1230def VLD4LNd32 : VLD4LN<0b1011, {?,0,?,?}, "32"> { 1231 let Inst{7} = lane{0}; 1232 let Inst{5} = Rn{5}; 1233} 1234 1235def VLD4LNd8Pseudo : VLDQQLNPseudo<IIC_VLD4ln>; 1236def VLD4LNd16Pseudo : VLDQQLNPseudo<IIC_VLD4ln>; 1237def VLD4LNd32Pseudo : VLDQQLNPseudo<IIC_VLD4ln>; 1238 1239// ...with double-spaced registers: 1240def VLD4LNq16 : VLD4LN<0b0111, {?,?,1,?}, "16"> { 1241 let Inst{7-6} = lane{1-0}; 1242} 1243def VLD4LNq32 : VLD4LN<0b1011, {?,1,?,?}, "32"> { 1244 let Inst{7} = lane{0}; 1245 let Inst{5} = Rn{5}; 1246} 1247 1248def VLD4LNq16Pseudo : VLDQQQQLNPseudo<IIC_VLD4ln>; 1249def VLD4LNq32Pseudo : VLDQQQQLNPseudo<IIC_VLD4ln>; 1250 1251// ...with address register writeback: 1252class VLD4LNWB<bits<4> op11_8, bits<4> op7_4, string Dt> 1253 : NLdStLn<1, 0b10, op11_8, op7_4, 1254 (outs DPR:$Vd, DPR:$dst2, DPR:$dst3, DPR:$dst4, GPR:$wb), 1255 (ins addrmode6:$Rn, am6offset:$Rm, 1256 DPR:$src1, DPR:$src2, DPR:$src3, DPR:$src4, nohash_imm:$lane), 1257 IIC_VLD4lnu, "vld4", Dt, 1258"\\{$Vd[$lane], $dst2[$lane], $dst3[$lane], $dst4[$lane]\\}, $Rn$Rm", 1259"$src1 = $Vd, $src2 = $dst2, $src3 = $dst3, $src4 = $dst4, $Rn.addr = $wb", 1260 []> { 1261 let Inst{4} = Rn{4}; 1262 let DecoderMethod = "DecodeVLD4LN" ; 1263} 1264 1265def VLD4LNd8_UPD : VLD4LNWB<0b0011, {?,?,?,?}, "8"> { 1266 let Inst{7-5} = lane{2-0}; 1267} 1268def VLD4LNd16_UPD : VLD4LNWB<0b0111, {?,?,0,?}, "16"> { 1269 let Inst{7-6} = lane{1-0}; 1270} 1271def VLD4LNd32_UPD : VLD4LNWB<0b1011, {?,0,?,?}, "32"> { 1272 let Inst{7} = lane{0}; 1273 let Inst{5} = Rn{5}; 1274} 1275 1276def VLD4LNd8Pseudo_UPD : VLDQQLNWBPseudo<IIC_VLD4lnu>; 1277def VLD4LNd16Pseudo_UPD : VLDQQLNWBPseudo<IIC_VLD4lnu>; 1278def VLD4LNd32Pseudo_UPD : VLDQQLNWBPseudo<IIC_VLD4lnu>; 1279 1280def VLD4LNq16_UPD : VLD4LNWB<0b0111, {?,?,1,?}, "16"> { 1281 let Inst{7-6} = lane{1-0}; 1282} 1283def VLD4LNq32_UPD : VLD4LNWB<0b1011, {?,1,?,?}, "32"> { 1284 let Inst{7} = lane{0}; 1285 let Inst{5} = Rn{5}; 1286} 1287 1288def VLD4LNq16Pseudo_UPD : VLDQQQQLNWBPseudo<IIC_VLD4lnu>; 1289def VLD4LNq32Pseudo_UPD : VLDQQQQLNWBPseudo<IIC_VLD4lnu>; 1290 1291} // mayLoad = 1, neverHasSideEffects = 1, hasExtraDefRegAllocReq = 1 1292 1293// VLD1DUP : Vector Load (single element to all lanes) 1294class VLD1DUP<bits<4> op7_4, string Dt, ValueType Ty, PatFrag LoadOp> 1295 : NLdSt<1, 0b10, 0b1100, op7_4, (outs VecListOneDAllLanes:$Vd), 1296 (ins addrmode6dup:$Rn), 1297 IIC_VLD1dup, "vld1", Dt, "$Vd, $Rn", "", 1298 [(set VecListOneDAllLanes:$Vd, 1299 (Ty (NEONvdup (i32 (LoadOp addrmode6dup:$Rn)))))]> { 1300 let Rm = 0b1111; 1301 let Inst{4} = Rn{4}; 1302 let DecoderMethod = "DecodeVLD1DupInstruction"; 1303} 1304class VLD1QDUPPseudo<ValueType Ty, PatFrag LoadOp> : VLDQPseudo<IIC_VLD1dup> { 1305 let Pattern = [(set QPR:$dst, 1306 (Ty (NEONvdup (i32 (LoadOp addrmode6dup:$addr)))))]; 1307} 1308 1309def VLD1DUPd8 : VLD1DUP<{0,0,0,?}, "8", v8i8, extloadi8>; 1310def VLD1DUPd16 : VLD1DUP<{0,1,0,?}, "16", v4i16, extloadi16>; 1311def VLD1DUPd32 : VLD1DUP<{1,0,0,?}, "32", v2i32, load>; 1312 1313def VLD1DUPq8Pseudo : VLD1QDUPPseudo<v16i8, extloadi8>; 1314def VLD1DUPq16Pseudo : VLD1QDUPPseudo<v8i16, extloadi16>; 1315def VLD1DUPq32Pseudo : VLD1QDUPPseudo<v4i32, load>; 1316 1317def : Pat<(v2f32 (NEONvdup (f32 (load addrmode6dup:$addr)))), 1318 (VLD1DUPd32 addrmode6:$addr)>; 1319def : Pat<(v4f32 (NEONvdup (f32 (load addrmode6dup:$addr)))), 1320 (VLD1DUPq32Pseudo addrmode6:$addr)>; 1321 1322let mayLoad = 1, neverHasSideEffects = 1, hasExtraDefRegAllocReq = 1 in { 1323 1324class VLD1QDUP<bits<4> op7_4, string Dt> 1325 : NLdSt<1, 0b10, 0b1100, op7_4, (outs VecListTwoDAllLanes:$Vd), 1326 (ins addrmode6dup:$Rn), IIC_VLD1dup, 1327 "vld1", Dt, "$Vd, $Rn", "", []> { 1328 let Rm = 0b1111; 1329 let Inst{4} = Rn{4}; 1330 let DecoderMethod = "DecodeVLD1DupInstruction"; 1331} 1332 1333def VLD1DUPq8 : VLD1QDUP<{0,0,1,0}, "8">; 1334def VLD1DUPq16 : VLD1QDUP<{0,1,1,?}, "16">; 1335def VLD1DUPq32 : VLD1QDUP<{1,0,1,?}, "32">; 1336 1337// ...with address register writeback: 1338multiclass VLD1DUPWB<bits<4> op7_4, string Dt> { 1339 def _fixed : NLdSt<1, 0b10, 0b1100, op7_4, 1340 (outs VecListOneDAllLanes:$Vd, GPR:$wb), 1341 (ins addrmode6dup:$Rn), IIC_VLD1dupu, 1342 "vld1", Dt, "$Vd, $Rn!", 1343 "$Rn.addr = $wb", []> { 1344 let Rm = 0b1101; // NLdSt will assign to the right encoding bits. 1345 let Inst{4} = Rn{4}; 1346 let DecoderMethod = "DecodeVLD1DupInstruction"; 1347 let AsmMatchConverter = "cvtVLDwbFixed"; 1348 } 1349 def _register : NLdSt<1, 0b10, 0b1100, op7_4, 1350 (outs VecListOneDAllLanes:$Vd, GPR:$wb), 1351 (ins addrmode6dup:$Rn, rGPR:$Rm), IIC_VLD1dupu, 1352 "vld1", Dt, "$Vd, $Rn, $Rm", 1353 "$Rn.addr = $wb", []> { 1354 let Inst{4} = Rn{4}; 1355 let DecoderMethod = "DecodeVLD1DupInstruction"; 1356 let AsmMatchConverter = "cvtVLDwbRegister"; 1357 } 1358} 1359multiclass VLD1QDUPWB<bits<4> op7_4, string Dt> { 1360 def _fixed : NLdSt<1, 0b10, 0b1100, op7_4, 1361 (outs VecListTwoDAllLanes:$Vd, GPR:$wb), 1362 (ins addrmode6dup:$Rn), IIC_VLD1dupu, 1363 "vld1", Dt, "$Vd, $Rn!", 1364 "$Rn.addr = $wb", []> { 1365 let Rm = 0b1101; // NLdSt will assign to the right encoding bits. 1366 let Inst{4} = Rn{4}; 1367 let DecoderMethod = "DecodeVLD1DupInstruction"; 1368 let AsmMatchConverter = "cvtVLDwbFixed"; 1369 } 1370 def _register : NLdSt<1, 0b10, 0b1100, op7_4, 1371 (outs VecListTwoDAllLanes:$Vd, GPR:$wb), 1372 (ins addrmode6dup:$Rn, rGPR:$Rm), IIC_VLD1dupu, 1373 "vld1", Dt, "$Vd, $Rn, $Rm", 1374 "$Rn.addr = $wb", []> { 1375 let Inst{4} = Rn{4}; 1376 let DecoderMethod = "DecodeVLD1DupInstruction"; 1377 let AsmMatchConverter = "cvtVLDwbRegister"; 1378 } 1379} 1380 1381defm VLD1DUPd8wb : VLD1DUPWB<{0,0,0,0}, "8">; 1382defm VLD1DUPd16wb : VLD1DUPWB<{0,1,0,?}, "16">; 1383defm VLD1DUPd32wb : VLD1DUPWB<{1,0,0,?}, "32">; 1384 1385defm VLD1DUPq8wb : VLD1QDUPWB<{0,0,1,0}, "8">; 1386defm VLD1DUPq16wb : VLD1QDUPWB<{0,1,1,?}, "16">; 1387defm VLD1DUPq32wb : VLD1QDUPWB<{1,0,1,?}, "32">; 1388 1389def VLD1DUPq8PseudoWB_fixed : VLDQWBfixedPseudo<IIC_VLD1dupu>; 1390def VLD1DUPq16PseudoWB_fixed : VLDQWBfixedPseudo<IIC_VLD1dupu>; 1391def VLD1DUPq32PseudoWB_fixed : VLDQWBfixedPseudo<IIC_VLD1dupu>; 1392def VLD1DUPq8PseudoWB_register : VLDQWBregisterPseudo<IIC_VLD1dupu>; 1393def VLD1DUPq16PseudoWB_register : VLDQWBregisterPseudo<IIC_VLD1dupu>; 1394def VLD1DUPq32PseudoWB_register : VLDQWBregisterPseudo<IIC_VLD1dupu>; 1395 1396// VLD2DUP : Vector Load (single 2-element structure to all lanes) 1397class VLD2DUP<bits<4> op7_4, string Dt, RegisterOperand VdTy> 1398 : NLdSt<1, 0b10, 0b1101, op7_4, (outs VdTy:$Vd), 1399 (ins addrmode6dup:$Rn), IIC_VLD2dup, 1400 "vld2", Dt, "$Vd, $Rn", "", []> { 1401 let Rm = 0b1111; 1402 let Inst{4} = Rn{4}; 1403 let DecoderMethod = "DecodeVLD2DupInstruction"; 1404} 1405 1406def VLD2DUPd8 : VLD2DUP<{0,0,0,?}, "8", VecListTwoDAllLanes>; 1407def VLD2DUPd16 : VLD2DUP<{0,1,0,?}, "16", VecListTwoDAllLanes>; 1408def VLD2DUPd32 : VLD2DUP<{1,0,0,?}, "32", VecListTwoDAllLanes>; 1409 1410def VLD2DUPd8Pseudo : VLDQPseudo<IIC_VLD2dup>; 1411def VLD2DUPd16Pseudo : VLDQPseudo<IIC_VLD2dup>; 1412def VLD2DUPd32Pseudo : VLDQPseudo<IIC_VLD2dup>; 1413 1414// ...with double-spaced registers (not used for codegen): 1415def VLD2DUPd8x2 : VLD2DUP<{0,0,1,?}, "8", VecListTwoQAllLanes>; 1416def VLD2DUPd16x2 : VLD2DUP<{0,1,1,?}, "16", VecListTwoQAllLanes>; 1417def VLD2DUPd32x2 : VLD2DUP<{1,0,1,?}, "32", VecListTwoQAllLanes>; 1418 1419// ...with address register writeback: 1420multiclass VLD2DUPWB<bits<4> op7_4, string Dt, RegisterOperand VdTy> { 1421 def _fixed : NLdSt<1, 0b10, 0b1101, op7_4, 1422 (outs VdTy:$Vd, GPR:$wb), 1423 (ins addrmode6dup:$Rn), IIC_VLD2dupu, 1424 "vld2", Dt, "$Vd, $Rn!", 1425 "$Rn.addr = $wb", []> { 1426 let Rm = 0b1101; // NLdSt will assign to the right encoding bits. 1427 let Inst{4} = Rn{4}; 1428 let DecoderMethod = "DecodeVLD2DupInstruction"; 1429 let AsmMatchConverter = "cvtVLDwbFixed"; 1430 } 1431 def _register : NLdSt<1, 0b10, 0b1101, op7_4, 1432 (outs VdTy:$Vd, GPR:$wb), 1433 (ins addrmode6dup:$Rn, rGPR:$Rm), IIC_VLD2dupu, 1434 "vld2", Dt, "$Vd, $Rn, $Rm", 1435 "$Rn.addr = $wb", []> { 1436 let Inst{4} = Rn{4}; 1437 let DecoderMethod = "DecodeVLD2DupInstruction"; 1438 let AsmMatchConverter = "cvtVLDwbRegister"; 1439 } 1440} 1441 1442defm VLD2DUPd8wb : VLD2DUPWB<{0,0,0,0}, "8", VecListTwoDAllLanes>; 1443defm VLD2DUPd16wb : VLD2DUPWB<{0,1,0,?}, "16", VecListTwoDAllLanes>; 1444defm VLD2DUPd32wb : VLD2DUPWB<{1,0,0,?}, "32", VecListTwoDAllLanes>; 1445 1446defm VLD2DUPd8x2wb : VLD2DUPWB<{0,0,1,0}, "8", VecListTwoQAllLanes>; 1447defm VLD2DUPd16x2wb : VLD2DUPWB<{0,1,1,?}, "16", VecListTwoQAllLanes>; 1448defm VLD2DUPd32x2wb : VLD2DUPWB<{1,0,1,?}, "32", VecListTwoQAllLanes>; 1449 1450def VLD2DUPd8PseudoWB_fixed : VLDQWBfixedPseudo <IIC_VLD2dupu>; 1451def VLD2DUPd8PseudoWB_register : VLDQWBregisterPseudo<IIC_VLD2dupu>; 1452def VLD2DUPd16PseudoWB_fixed : VLDQWBfixedPseudo <IIC_VLD2dupu>; 1453def VLD2DUPd16PseudoWB_register : VLDQWBregisterPseudo<IIC_VLD2dupu>; 1454def VLD2DUPd32PseudoWB_fixed : VLDQWBfixedPseudo <IIC_VLD2dupu>; 1455def VLD2DUPd32PseudoWB_register : VLDQWBregisterPseudo<IIC_VLD2dupu>; 1456 1457// VLD3DUP : Vector Load (single 3-element structure to all lanes) 1458class VLD3DUP<bits<4> op7_4, string Dt> 1459 : NLdSt<1, 0b10, 0b1110, op7_4, (outs DPR:$Vd, DPR:$dst2, DPR:$dst3), 1460 (ins addrmode6dup:$Rn), IIC_VLD3dup, 1461 "vld3", Dt, "\\{$Vd[], $dst2[], $dst3[]\\}, $Rn", "", []> { 1462 let Rm = 0b1111; 1463 let Inst{4} = 0; 1464 let DecoderMethod = "DecodeVLD3DupInstruction"; 1465} 1466 1467def VLD3DUPd8 : VLD3DUP<{0,0,0,?}, "8">; 1468def VLD3DUPd16 : VLD3DUP<{0,1,0,?}, "16">; 1469def VLD3DUPd32 : VLD3DUP<{1,0,0,?}, "32">; 1470 1471def VLD3DUPd8Pseudo : VLDQQPseudo<IIC_VLD3dup>; 1472def VLD3DUPd16Pseudo : VLDQQPseudo<IIC_VLD3dup>; 1473def VLD3DUPd32Pseudo : VLDQQPseudo<IIC_VLD3dup>; 1474 1475// ...with double-spaced registers (not used for codegen): 1476def VLD3DUPq8 : VLD3DUP<{0,0,1,?}, "8">; 1477def VLD3DUPq16 : VLD3DUP<{0,1,1,?}, "16">; 1478def VLD3DUPq32 : VLD3DUP<{1,0,1,?}, "32">; 1479 1480// ...with address register writeback: 1481class VLD3DUPWB<bits<4> op7_4, string Dt> 1482 : NLdSt<1, 0b10, 0b1110, op7_4, (outs DPR:$Vd, DPR:$dst2, DPR:$dst3, GPR:$wb), 1483 (ins addrmode6dup:$Rn, am6offset:$Rm), IIC_VLD3dupu, 1484 "vld3", Dt, "\\{$Vd[], $dst2[], $dst3[]\\}, $Rn$Rm", 1485 "$Rn.addr = $wb", []> { 1486 let Inst{4} = 0; 1487 let DecoderMethod = "DecodeVLD3DupInstruction"; 1488} 1489 1490def VLD3DUPd8_UPD : VLD3DUPWB<{0,0,0,0}, "8">; 1491def VLD3DUPd16_UPD : VLD3DUPWB<{0,1,0,?}, "16">; 1492def VLD3DUPd32_UPD : VLD3DUPWB<{1,0,0,?}, "32">; 1493 1494def VLD3DUPq8_UPD : VLD3DUPWB<{0,0,1,0}, "8">; 1495def VLD3DUPq16_UPD : VLD3DUPWB<{0,1,1,?}, "16">; 1496def VLD3DUPq32_UPD : VLD3DUPWB<{1,0,1,?}, "32">; 1497 1498def VLD3DUPd8Pseudo_UPD : VLDQQWBPseudo<IIC_VLD3dupu>; 1499def VLD3DUPd16Pseudo_UPD : VLDQQWBPseudo<IIC_VLD3dupu>; 1500def VLD3DUPd32Pseudo_UPD : VLDQQWBPseudo<IIC_VLD3dupu>; 1501 1502// VLD4DUP : Vector Load (single 4-element structure to all lanes) 1503class VLD4DUP<bits<4> op7_4, string Dt> 1504 : NLdSt<1, 0b10, 0b1111, op7_4, 1505 (outs DPR:$Vd, DPR:$dst2, DPR:$dst3, DPR:$dst4), 1506 (ins addrmode6dup:$Rn), IIC_VLD4dup, 1507 "vld4", Dt, "\\{$Vd[], $dst2[], $dst3[], $dst4[]\\}, $Rn", "", []> { 1508 let Rm = 0b1111; 1509 let Inst{4} = Rn{4}; 1510 let DecoderMethod = "DecodeVLD4DupInstruction"; 1511} 1512 1513def VLD4DUPd8 : VLD4DUP<{0,0,0,?}, "8">; 1514def VLD4DUPd16 : VLD4DUP<{0,1,0,?}, "16">; 1515def VLD4DUPd32 : VLD4DUP<{1,?,0,?}, "32"> { let Inst{6} = Rn{5}; } 1516 1517def VLD4DUPd8Pseudo : VLDQQPseudo<IIC_VLD4dup>; 1518def VLD4DUPd16Pseudo : VLDQQPseudo<IIC_VLD4dup>; 1519def VLD4DUPd32Pseudo : VLDQQPseudo<IIC_VLD4dup>; 1520 1521// ...with double-spaced registers (not used for codegen): 1522def VLD4DUPq8 : VLD4DUP<{0,0,1,?}, "8">; 1523def VLD4DUPq16 : VLD4DUP<{0,1,1,?}, "16">; 1524def VLD4DUPq32 : VLD4DUP<{1,?,1,?}, "32"> { let Inst{6} = Rn{5}; } 1525 1526// ...with address register writeback: 1527class VLD4DUPWB<bits<4> op7_4, string Dt> 1528 : NLdSt<1, 0b10, 0b1111, op7_4, 1529 (outs DPR:$Vd, DPR:$dst2, DPR:$dst3, DPR:$dst4, GPR:$wb), 1530 (ins addrmode6dup:$Rn, am6offset:$Rm), IIC_VLD4dupu, 1531 "vld4", Dt, "\\{$Vd[], $dst2[], $dst3[], $dst4[]\\}, $Rn$Rm", 1532 "$Rn.addr = $wb", []> { 1533 let Inst{4} = Rn{4}; 1534 let DecoderMethod = "DecodeVLD4DupInstruction"; 1535} 1536 1537def VLD4DUPd8_UPD : VLD4DUPWB<{0,0,0,0}, "8">; 1538def VLD4DUPd16_UPD : VLD4DUPWB<{0,1,0,?}, "16">; 1539def VLD4DUPd32_UPD : VLD4DUPWB<{1,?,0,?}, "32"> { let Inst{6} = Rn{5}; } 1540 1541def VLD4DUPq8_UPD : VLD4DUPWB<{0,0,1,0}, "8">; 1542def VLD4DUPq16_UPD : VLD4DUPWB<{0,1,1,?}, "16">; 1543def VLD4DUPq32_UPD : VLD4DUPWB<{1,?,1,?}, "32"> { let Inst{6} = Rn{5}; } 1544 1545def VLD4DUPd8Pseudo_UPD : VLDQQWBPseudo<IIC_VLD4dupu>; 1546def VLD4DUPd16Pseudo_UPD : VLDQQWBPseudo<IIC_VLD4dupu>; 1547def VLD4DUPd32Pseudo_UPD : VLDQQWBPseudo<IIC_VLD4dupu>; 1548 1549} // mayLoad = 1, neverHasSideEffects = 1, hasExtraDefRegAllocReq = 1 1550 1551let mayStore = 1, neverHasSideEffects = 1, hasExtraSrcRegAllocReq = 1 in { 1552 1553// Classes for VST* pseudo-instructions with multi-register operands. 1554// These are expanded to real instructions after register allocation. 1555class VSTQPseudo<InstrItinClass itin> 1556 : PseudoNLdSt<(outs), (ins addrmode6:$addr, QPR:$src), itin, "">; 1557class VSTQWBPseudo<InstrItinClass itin> 1558 : PseudoNLdSt<(outs GPR:$wb), 1559 (ins addrmode6:$addr, am6offset:$offset, QPR:$src), itin, 1560 "$addr.addr = $wb">; 1561class VSTQWBfixedPseudo<InstrItinClass itin> 1562 : PseudoNLdSt<(outs GPR:$wb), 1563 (ins addrmode6:$addr, QPR:$src), itin, 1564 "$addr.addr = $wb">; 1565class VSTQWBregisterPseudo<InstrItinClass itin> 1566 : PseudoNLdSt<(outs GPR:$wb), 1567 (ins addrmode6:$addr, rGPR:$offset, QPR:$src), itin, 1568 "$addr.addr = $wb">; 1569class VSTQQPseudo<InstrItinClass itin> 1570 : PseudoNLdSt<(outs), (ins addrmode6:$addr, QQPR:$src), itin, "">; 1571class VSTQQWBPseudo<InstrItinClass itin> 1572 : PseudoNLdSt<(outs GPR:$wb), 1573 (ins addrmode6:$addr, am6offset:$offset, QQPR:$src), itin, 1574 "$addr.addr = $wb">; 1575class VSTQQWBfixedPseudo<InstrItinClass itin> 1576 : PseudoNLdSt<(outs GPR:$wb), 1577 (ins addrmode6:$addr, QQPR:$src), itin, 1578 "$addr.addr = $wb">; 1579class VSTQQWBregisterPseudo<InstrItinClass itin> 1580 : PseudoNLdSt<(outs GPR:$wb), 1581 (ins addrmode6:$addr, rGPR:$offset, QQPR:$src), itin, 1582 "$addr.addr = $wb">; 1583 1584class VSTQQQQPseudo<InstrItinClass itin> 1585 : PseudoNLdSt<(outs), (ins addrmode6:$addr, QQQQPR:$src), itin, "">; 1586class VSTQQQQWBPseudo<InstrItinClass itin> 1587 : PseudoNLdSt<(outs GPR:$wb), 1588 (ins addrmode6:$addr, am6offset:$offset, QQQQPR:$src), itin, 1589 "$addr.addr = $wb">; 1590 1591// VST1 : Vector Store (multiple single elements) 1592class VST1D<bits<4> op7_4, string Dt> 1593 : NLdSt<0,0b00,0b0111,op7_4, (outs), (ins addrmode6:$Rn, VecListOneD:$Vd), 1594 IIC_VST1, "vst1", Dt, "$Vd, $Rn", "", []> { 1595 let Rm = 0b1111; 1596 let Inst{4} = Rn{4}; 1597 let DecoderMethod = "DecodeVSTInstruction"; 1598} 1599class VST1Q<bits<4> op7_4, string Dt> 1600 : NLdSt<0,0b00,0b1010,op7_4, (outs), (ins addrmode6:$Rn, VecListTwoD:$Vd), 1601 IIC_VST1x2, "vst1", Dt, "$Vd, $Rn", "", []> { 1602 let Rm = 0b1111; 1603 let Inst{5-4} = Rn{5-4}; 1604 let DecoderMethod = "DecodeVSTInstruction"; 1605} 1606 1607def VST1d8 : VST1D<{0,0,0,?}, "8">; 1608def VST1d16 : VST1D<{0,1,0,?}, "16">; 1609def VST1d32 : VST1D<{1,0,0,?}, "32">; 1610def VST1d64 : VST1D<{1,1,0,?}, "64">; 1611 1612def VST1q8 : VST1Q<{0,0,?,?}, "8">; 1613def VST1q16 : VST1Q<{0,1,?,?}, "16">; 1614def VST1q32 : VST1Q<{1,0,?,?}, "32">; 1615def VST1q64 : VST1Q<{1,1,?,?}, "64">; 1616 1617def VST1q8Pseudo : VSTQPseudo<IIC_VST1x2>; 1618def VST1q16Pseudo : VSTQPseudo<IIC_VST1x2>; 1619def VST1q32Pseudo : VSTQPseudo<IIC_VST1x2>; 1620def VST1q64Pseudo : VSTQPseudo<IIC_VST1x2>; 1621 1622// ...with address register writeback: 1623multiclass VST1DWB<bits<4> op7_4, string Dt> { 1624 def _fixed : NLdSt<0,0b00, 0b0111,op7_4, (outs GPR:$wb), 1625 (ins addrmode6:$Rn, VecListOneD:$Vd), IIC_VLD1u, 1626 "vst1", Dt, "$Vd, $Rn!", 1627 "$Rn.addr = $wb", []> { 1628 let Rm = 0b1101; // NLdSt will assign to the right encoding bits. 1629 let Inst{4} = Rn{4}; 1630 let DecoderMethod = "DecodeVSTInstruction"; 1631 let AsmMatchConverter = "cvtVSTwbFixed"; 1632 } 1633 def _register : NLdSt<0,0b00,0b0111,op7_4, (outs GPR:$wb), 1634 (ins addrmode6:$Rn, rGPR:$Rm, VecListOneD:$Vd), 1635 IIC_VLD1u, 1636 "vst1", Dt, "$Vd, $Rn, $Rm", 1637 "$Rn.addr = $wb", []> { 1638 let Inst{4} = Rn{4}; 1639 let DecoderMethod = "DecodeVSTInstruction"; 1640 let AsmMatchConverter = "cvtVSTwbRegister"; 1641 } 1642} 1643multiclass VST1QWB<bits<4> op7_4, string Dt> { 1644 def _fixed : NLdSt<0,0b00,0b1010,op7_4, (outs GPR:$wb), 1645 (ins addrmode6:$Rn, VecListTwoD:$Vd), IIC_VLD1x2u, 1646 "vst1", Dt, "$Vd, $Rn!", 1647 "$Rn.addr = $wb", []> { 1648 let Rm = 0b1101; // NLdSt will assign to the right encoding bits. 1649 let Inst{5-4} = Rn{5-4}; 1650 let DecoderMethod = "DecodeVSTInstruction"; 1651 let AsmMatchConverter = "cvtVSTwbFixed"; 1652 } 1653 def _register : NLdSt<0,0b00,0b1010,op7_4, (outs GPR:$wb), 1654 (ins addrmode6:$Rn, rGPR:$Rm, VecListTwoD:$Vd), 1655 IIC_VLD1x2u, 1656 "vst1", Dt, "$Vd, $Rn, $Rm", 1657 "$Rn.addr = $wb", []> { 1658 let Inst{5-4} = Rn{5-4}; 1659 let DecoderMethod = "DecodeVSTInstruction"; 1660 let AsmMatchConverter = "cvtVSTwbRegister"; 1661 } 1662} 1663 1664defm VST1d8wb : VST1DWB<{0,0,0,?}, "8">; 1665defm VST1d16wb : VST1DWB<{0,1,0,?}, "16">; 1666defm VST1d32wb : VST1DWB<{1,0,0,?}, "32">; 1667defm VST1d64wb : VST1DWB<{1,1,0,?}, "64">; 1668 1669defm VST1q8wb : VST1QWB<{0,0,?,?}, "8">; 1670defm VST1q16wb : VST1QWB<{0,1,?,?}, "16">; 1671defm VST1q32wb : VST1QWB<{1,0,?,?}, "32">; 1672defm VST1q64wb : VST1QWB<{1,1,?,?}, "64">; 1673 1674def VST1q8PseudoWB_fixed : VSTQWBfixedPseudo<IIC_VST1x2u>; 1675def VST1q16PseudoWB_fixed : VSTQWBfixedPseudo<IIC_VST1x2u>; 1676def VST1q32PseudoWB_fixed : VSTQWBfixedPseudo<IIC_VST1x2u>; 1677def VST1q64PseudoWB_fixed : VSTQWBfixedPseudo<IIC_VST1x2u>; 1678def VST1q8PseudoWB_register : VSTQWBregisterPseudo<IIC_VST1x2u>; 1679def VST1q16PseudoWB_register : VSTQWBregisterPseudo<IIC_VST1x2u>; 1680def VST1q32PseudoWB_register : VSTQWBregisterPseudo<IIC_VST1x2u>; 1681def VST1q64PseudoWB_register : VSTQWBregisterPseudo<IIC_VST1x2u>; 1682 1683// ...with 3 registers 1684class VST1D3<bits<4> op7_4, string Dt> 1685 : NLdSt<0, 0b00, 0b0110, op7_4, (outs), 1686 (ins addrmode6:$Rn, VecListThreeD:$Vd), 1687 IIC_VST1x3, "vst1", Dt, "$Vd, $Rn", "", []> { 1688 let Rm = 0b1111; 1689 let Inst{4} = Rn{4}; 1690 let DecoderMethod = "DecodeVSTInstruction"; 1691} 1692multiclass VST1D3WB<bits<4> op7_4, string Dt> { 1693 def _fixed : NLdSt<0,0b00,0b0110,op7_4, (outs GPR:$wb), 1694 (ins addrmode6:$Rn, VecListThreeD:$Vd), IIC_VLD1x3u, 1695 "vst1", Dt, "$Vd, $Rn!", 1696 "$Rn.addr = $wb", []> { 1697 let Rm = 0b1101; // NLdSt will assign to the right encoding bits. 1698 let Inst{5-4} = Rn{5-4}; 1699 let DecoderMethod = "DecodeVSTInstruction"; 1700 let AsmMatchConverter = "cvtVSTwbFixed"; 1701 } 1702 def _register : NLdSt<0,0b00,0b0110,op7_4, (outs GPR:$wb), 1703 (ins addrmode6:$Rn, rGPR:$Rm, VecListThreeD:$Vd), 1704 IIC_VLD1x3u, 1705 "vst1", Dt, "$Vd, $Rn, $Rm", 1706 "$Rn.addr = $wb", []> { 1707 let Inst{5-4} = Rn{5-4}; 1708 let DecoderMethod = "DecodeVSTInstruction"; 1709 let AsmMatchConverter = "cvtVSTwbRegister"; 1710 } 1711} 1712 1713def VST1d8T : VST1D3<{0,0,0,?}, "8">; 1714def VST1d16T : VST1D3<{0,1,0,?}, "16">; 1715def VST1d32T : VST1D3<{1,0,0,?}, "32">; 1716def VST1d64T : VST1D3<{1,1,0,?}, "64">; 1717 1718defm VST1d8Twb : VST1D3WB<{0,0,0,?}, "8">; 1719defm VST1d16Twb : VST1D3WB<{0,1,0,?}, "16">; 1720defm VST1d32Twb : VST1D3WB<{1,0,0,?}, "32">; 1721defm VST1d64Twb : VST1D3WB<{1,1,0,?}, "64">; 1722 1723def VST1d64TPseudo : VSTQQPseudo<IIC_VST1x3>; 1724def VST1d64TPseudoWB_fixed : VSTQQWBPseudo<IIC_VST1x3u>; 1725def VST1d64TPseudoWB_register : VSTQQWBPseudo<IIC_VST1x3u>; 1726 1727// ...with 4 registers 1728class VST1D4<bits<4> op7_4, string Dt> 1729 : NLdSt<0, 0b00, 0b0010, op7_4, (outs), 1730 (ins addrmode6:$Rn, VecListFourD:$Vd), 1731 IIC_VST1x4, "vst1", Dt, "$Vd, $Rn", "", 1732 []> { 1733 let Rm = 0b1111; 1734 let Inst{5-4} = Rn{5-4}; 1735 let DecoderMethod = "DecodeVSTInstruction"; 1736} 1737multiclass VST1D4WB<bits<4> op7_4, string Dt> { 1738 def _fixed : NLdSt<0,0b00,0b0010,op7_4, (outs GPR:$wb), 1739 (ins addrmode6:$Rn, VecListFourD:$Vd), IIC_VLD1x4u, 1740 "vst1", Dt, "$Vd, $Rn!", 1741 "$Rn.addr = $wb", []> { 1742 let Rm = 0b1101; // NLdSt will assign to the right encoding bits. 1743 let Inst{5-4} = Rn{5-4}; 1744 let DecoderMethod = "DecodeVSTInstruction"; 1745 let AsmMatchConverter = "cvtVSTwbFixed"; 1746 } 1747 def _register : NLdSt<0,0b00,0b0010,op7_4, (outs GPR:$wb), 1748 (ins addrmode6:$Rn, rGPR:$Rm, VecListFourD:$Vd), 1749 IIC_VLD1x4u, 1750 "vst1", Dt, "$Vd, $Rn, $Rm", 1751 "$Rn.addr = $wb", []> { 1752 let Inst{5-4} = Rn{5-4}; 1753 let DecoderMethod = "DecodeVSTInstruction"; 1754 let AsmMatchConverter = "cvtVSTwbRegister"; 1755 } 1756} 1757 1758def VST1d8Q : VST1D4<{0,0,?,?}, "8">; 1759def VST1d16Q : VST1D4<{0,1,?,?}, "16">; 1760def VST1d32Q : VST1D4<{1,0,?,?}, "32">; 1761def VST1d64Q : VST1D4<{1,1,?,?}, "64">; 1762 1763defm VST1d8Qwb : VST1D4WB<{0,0,?,?}, "8">; 1764defm VST1d16Qwb : VST1D4WB<{0,1,?,?}, "16">; 1765defm VST1d32Qwb : VST1D4WB<{1,0,?,?}, "32">; 1766defm VST1d64Qwb : VST1D4WB<{1,1,?,?}, "64">; 1767 1768def VST1d64QPseudo : VSTQQPseudo<IIC_VST1x4>; 1769def VST1d64QPseudoWB_fixed : VSTQQWBPseudo<IIC_VST1x4u>; 1770def VST1d64QPseudoWB_register : VSTQQWBPseudo<IIC_VST1x4u>; 1771 1772// VST2 : Vector Store (multiple 2-element structures) 1773class VST2<bits<4> op11_8, bits<4> op7_4, string Dt, RegisterOperand VdTy, 1774 InstrItinClass itin> 1775 : NLdSt<0, 0b00, op11_8, op7_4, (outs), (ins addrmode6:$Rn, VdTy:$Vd), 1776 itin, "vst2", Dt, "$Vd, $Rn", "", []> { 1777 let Rm = 0b1111; 1778 let Inst{5-4} = Rn{5-4}; 1779 let DecoderMethod = "DecodeVSTInstruction"; 1780} 1781 1782def VST2d8 : VST2<0b1000, {0,0,?,?}, "8", VecListTwoD, IIC_VST2>; 1783def VST2d16 : VST2<0b1000, {0,1,?,?}, "16", VecListTwoD, IIC_VST2>; 1784def VST2d32 : VST2<0b1000, {1,0,?,?}, "32", VecListTwoD, IIC_VST2>; 1785 1786def VST2q8 : VST2<0b0011, {0,0,?,?}, "8", VecListFourD, IIC_VST2x2>; 1787def VST2q16 : VST2<0b0011, {0,1,?,?}, "16", VecListFourD, IIC_VST2x2>; 1788def VST2q32 : VST2<0b0011, {1,0,?,?}, "32", VecListFourD, IIC_VST2x2>; 1789 1790def VST2d8Pseudo : VSTQPseudo<IIC_VST2>; 1791def VST2d16Pseudo : VSTQPseudo<IIC_VST2>; 1792def VST2d32Pseudo : VSTQPseudo<IIC_VST2>; 1793 1794def VST2q8Pseudo : VSTQQPseudo<IIC_VST2x2>; 1795def VST2q16Pseudo : VSTQQPseudo<IIC_VST2x2>; 1796def VST2q32Pseudo : VSTQQPseudo<IIC_VST2x2>; 1797 1798// ...with address register writeback: 1799multiclass VST2DWB<bits<4> op11_8, bits<4> op7_4, string Dt, 1800 RegisterOperand VdTy> { 1801 def _fixed : NLdSt<0, 0b00, op11_8, op7_4, (outs GPR:$wb), 1802 (ins addrmode6:$Rn, VdTy:$Vd), IIC_VLD1u, 1803 "vst2", Dt, "$Vd, $Rn!", 1804 "$Rn.addr = $wb", []> { 1805 let Rm = 0b1101; // NLdSt will assign to the right encoding bits. 1806 let Inst{5-4} = Rn{5-4}; 1807 let DecoderMethod = "DecodeVSTInstruction"; 1808 let AsmMatchConverter = "cvtVSTwbFixed"; 1809 } 1810 def _register : NLdSt<0, 0b00, op11_8, op7_4, (outs GPR:$wb), 1811 (ins addrmode6:$Rn, rGPR:$Rm, VdTy:$Vd), IIC_VLD1u, 1812 "vst2", Dt, "$Vd, $Rn, $Rm", 1813 "$Rn.addr = $wb", []> { 1814 let Inst{5-4} = Rn{5-4}; 1815 let DecoderMethod = "DecodeVSTInstruction"; 1816 let AsmMatchConverter = "cvtVSTwbRegister"; 1817 } 1818} 1819multiclass VST2QWB<bits<4> op7_4, string Dt> { 1820 def _fixed : NLdSt<0, 0b00, 0b0011, op7_4, (outs GPR:$wb), 1821 (ins addrmode6:$Rn, VecListFourD:$Vd), IIC_VLD1u, 1822 "vst2", Dt, "$Vd, $Rn!", 1823 "$Rn.addr = $wb", []> { 1824 let Rm = 0b1101; // NLdSt will assign to the right encoding bits. 1825 let Inst{5-4} = Rn{5-4}; 1826 let DecoderMethod = "DecodeVSTInstruction"; 1827 let AsmMatchConverter = "cvtVSTwbFixed"; 1828 } 1829 def _register : NLdSt<0, 0b00, 0b0011, op7_4, (outs GPR:$wb), 1830 (ins addrmode6:$Rn, rGPR:$Rm, VecListFourD:$Vd), 1831 IIC_VLD1u, 1832 "vst2", Dt, "$Vd, $Rn, $Rm", 1833 "$Rn.addr = $wb", []> { 1834 let Inst{5-4} = Rn{5-4}; 1835 let DecoderMethod = "DecodeVSTInstruction"; 1836 let AsmMatchConverter = "cvtVSTwbRegister"; 1837 } 1838} 1839 1840defm VST2d8wb : VST2DWB<0b1000, {0,0,?,?}, "8", VecListTwoD>; 1841defm VST2d16wb : VST2DWB<0b1000, {0,1,?,?}, "16", VecListTwoD>; 1842defm VST2d32wb : VST2DWB<0b1000, {1,0,?,?}, "32", VecListTwoD>; 1843 1844defm VST2q8wb : VST2QWB<{0,0,?,?}, "8">; 1845defm VST2q16wb : VST2QWB<{0,1,?,?}, "16">; 1846defm VST2q32wb : VST2QWB<{1,0,?,?}, "32">; 1847 1848def VST2d8PseudoWB_fixed : VSTQWBfixedPseudo<IIC_VST2u>; 1849def VST2d16PseudoWB_fixed : VSTQWBfixedPseudo<IIC_VST2u>; 1850def VST2d32PseudoWB_fixed : VSTQWBfixedPseudo<IIC_VST2u>; 1851def VST2d8PseudoWB_register : VSTQWBregisterPseudo<IIC_VST2u>; 1852def VST2d16PseudoWB_register : VSTQWBregisterPseudo<IIC_VST2u>; 1853def VST2d32PseudoWB_register : VSTQWBregisterPseudo<IIC_VST2u>; 1854 1855def VST2q8PseudoWB_fixed : VSTQQWBfixedPseudo<IIC_VST2x2u>; 1856def VST2q16PseudoWB_fixed : VSTQQWBfixedPseudo<IIC_VST2x2u>; 1857def VST2q32PseudoWB_fixed : VSTQQWBfixedPseudo<IIC_VST2x2u>; 1858def VST2q8PseudoWB_register : VSTQQWBregisterPseudo<IIC_VST2x2u>; 1859def VST2q16PseudoWB_register : VSTQQWBregisterPseudo<IIC_VST2x2u>; 1860def VST2q32PseudoWB_register : VSTQQWBregisterPseudo<IIC_VST2x2u>; 1861 1862// ...with double-spaced registers 1863def VST2b8 : VST2<0b1001, {0,0,?,?}, "8", VecListTwoQ, IIC_VST2>; 1864def VST2b16 : VST2<0b1001, {0,1,?,?}, "16", VecListTwoQ, IIC_VST2>; 1865def VST2b32 : VST2<0b1001, {1,0,?,?}, "32", VecListTwoQ, IIC_VST2>; 1866defm VST2b8wb : VST2DWB<0b1001, {0,0,?,?}, "8", VecListTwoQ>; 1867defm VST2b16wb : VST2DWB<0b1001, {0,1,?,?}, "16", VecListTwoQ>; 1868defm VST2b32wb : VST2DWB<0b1001, {1,0,?,?}, "32", VecListTwoQ>; 1869 1870// VST3 : Vector Store (multiple 3-element structures) 1871class VST3D<bits<4> op11_8, bits<4> op7_4, string Dt> 1872 : NLdSt<0, 0b00, op11_8, op7_4, (outs), 1873 (ins addrmode6:$Rn, DPR:$Vd, DPR:$src2, DPR:$src3), IIC_VST3, 1874 "vst3", Dt, "\\{$Vd, $src2, $src3\\}, $Rn", "", []> { 1875 let Rm = 0b1111; 1876 let Inst{4} = Rn{4}; 1877 let DecoderMethod = "DecodeVSTInstruction"; 1878} 1879 1880def VST3d8 : VST3D<0b0100, {0,0,0,?}, "8">; 1881def VST3d16 : VST3D<0b0100, {0,1,0,?}, "16">; 1882def VST3d32 : VST3D<0b0100, {1,0,0,?}, "32">; 1883 1884def VST3d8Pseudo : VSTQQPseudo<IIC_VST3>; 1885def VST3d16Pseudo : VSTQQPseudo<IIC_VST3>; 1886def VST3d32Pseudo : VSTQQPseudo<IIC_VST3>; 1887 1888// ...with address register writeback: 1889class VST3DWB<bits<4> op11_8, bits<4> op7_4, string Dt> 1890 : NLdSt<0, 0b00, op11_8, op7_4, (outs GPR:$wb), 1891 (ins addrmode6:$Rn, am6offset:$Rm, 1892 DPR:$Vd, DPR:$src2, DPR:$src3), IIC_VST3u, 1893 "vst3", Dt, "\\{$Vd, $src2, $src3\\}, $Rn$Rm", 1894 "$Rn.addr = $wb", []> { 1895 let Inst{4} = Rn{4}; 1896 let DecoderMethod = "DecodeVSTInstruction"; 1897} 1898 1899def VST3d8_UPD : VST3DWB<0b0100, {0,0,0,?}, "8">; 1900def VST3d16_UPD : VST3DWB<0b0100, {0,1,0,?}, "16">; 1901def VST3d32_UPD : VST3DWB<0b0100, {1,0,0,?}, "32">; 1902 1903def VST3d8Pseudo_UPD : VSTQQWBPseudo<IIC_VST3u>; 1904def VST3d16Pseudo_UPD : VSTQQWBPseudo<IIC_VST3u>; 1905def VST3d32Pseudo_UPD : VSTQQWBPseudo<IIC_VST3u>; 1906 1907// ...with double-spaced registers: 1908def VST3q8 : VST3D<0b0101, {0,0,0,?}, "8">; 1909def VST3q16 : VST3D<0b0101, {0,1,0,?}, "16">; 1910def VST3q32 : VST3D<0b0101, {1,0,0,?}, "32">; 1911def VST3q8_UPD : VST3DWB<0b0101, {0,0,0,?}, "8">; 1912def VST3q16_UPD : VST3DWB<0b0101, {0,1,0,?}, "16">; 1913def VST3q32_UPD : VST3DWB<0b0101, {1,0,0,?}, "32">; 1914 1915def VST3q8Pseudo_UPD : VSTQQQQWBPseudo<IIC_VST3u>; 1916def VST3q16Pseudo_UPD : VSTQQQQWBPseudo<IIC_VST3u>; 1917def VST3q32Pseudo_UPD : VSTQQQQWBPseudo<IIC_VST3u>; 1918 1919// ...alternate versions to be allocated odd register numbers: 1920def VST3q8oddPseudo : VSTQQQQPseudo<IIC_VST3>; 1921def VST3q16oddPseudo : VSTQQQQPseudo<IIC_VST3>; 1922def VST3q32oddPseudo : VSTQQQQPseudo<IIC_VST3>; 1923 1924def VST3q8oddPseudo_UPD : VSTQQQQWBPseudo<IIC_VST3u>; 1925def VST3q16oddPseudo_UPD : VSTQQQQWBPseudo<IIC_VST3u>; 1926def VST3q32oddPseudo_UPD : VSTQQQQWBPseudo<IIC_VST3u>; 1927 1928// VST4 : Vector Store (multiple 4-element structures) 1929class VST4D<bits<4> op11_8, bits<4> op7_4, string Dt> 1930 : NLdSt<0, 0b00, op11_8, op7_4, (outs), 1931 (ins addrmode6:$Rn, DPR:$Vd, DPR:$src2, DPR:$src3, DPR:$src4), 1932 IIC_VST4, "vst4", Dt, "\\{$Vd, $src2, $src3, $src4\\}, $Rn", 1933 "", []> { 1934 let Rm = 0b1111; 1935 let Inst{5-4} = Rn{5-4}; 1936 let DecoderMethod = "DecodeVSTInstruction"; 1937} 1938 1939def VST4d8 : VST4D<0b0000, {0,0,?,?}, "8">; 1940def VST4d16 : VST4D<0b0000, {0,1,?,?}, "16">; 1941def VST4d32 : VST4D<0b0000, {1,0,?,?}, "32">; 1942 1943def VST4d8Pseudo : VSTQQPseudo<IIC_VST4>; 1944def VST4d16Pseudo : VSTQQPseudo<IIC_VST4>; 1945def VST4d32Pseudo : VSTQQPseudo<IIC_VST4>; 1946 1947// ...with address register writeback: 1948class VST4DWB<bits<4> op11_8, bits<4> op7_4, string Dt> 1949 : NLdSt<0, 0b00, op11_8, op7_4, (outs GPR:$wb), 1950 (ins addrmode6:$Rn, am6offset:$Rm, 1951 DPR:$Vd, DPR:$src2, DPR:$src3, DPR:$src4), IIC_VST4u, 1952 "vst4", Dt, "\\{$Vd, $src2, $src3, $src4\\}, $Rn$Rm", 1953 "$Rn.addr = $wb", []> { 1954 let Inst{5-4} = Rn{5-4}; 1955 let DecoderMethod = "DecodeVSTInstruction"; 1956} 1957 1958def VST4d8_UPD : VST4DWB<0b0000, {0,0,?,?}, "8">; 1959def VST4d16_UPD : VST4DWB<0b0000, {0,1,?,?}, "16">; 1960def VST4d32_UPD : VST4DWB<0b0000, {1,0,?,?}, "32">; 1961 1962def VST4d8Pseudo_UPD : VSTQQWBPseudo<IIC_VST4u>; 1963def VST4d16Pseudo_UPD : VSTQQWBPseudo<IIC_VST4u>; 1964def VST4d32Pseudo_UPD : VSTQQWBPseudo<IIC_VST4u>; 1965 1966// ...with double-spaced registers: 1967def VST4q8 : VST4D<0b0001, {0,0,?,?}, "8">; 1968def VST4q16 : VST4D<0b0001, {0,1,?,?}, "16">; 1969def VST4q32 : VST4D<0b0001, {1,0,?,?}, "32">; 1970def VST4q8_UPD : VST4DWB<0b0001, {0,0,?,?}, "8">; 1971def VST4q16_UPD : VST4DWB<0b0001, {0,1,?,?}, "16">; 1972def VST4q32_UPD : VST4DWB<0b0001, {1,0,?,?}, "32">; 1973 1974def VST4q8Pseudo_UPD : VSTQQQQWBPseudo<IIC_VST4u>; 1975def VST4q16Pseudo_UPD : VSTQQQQWBPseudo<IIC_VST4u>; 1976def VST4q32Pseudo_UPD : VSTQQQQWBPseudo<IIC_VST4u>; 1977 1978// ...alternate versions to be allocated odd register numbers: 1979def VST4q8oddPseudo : VSTQQQQPseudo<IIC_VST4>; 1980def VST4q16oddPseudo : VSTQQQQPseudo<IIC_VST4>; 1981def VST4q32oddPseudo : VSTQQQQPseudo<IIC_VST4>; 1982 1983def VST4q8oddPseudo_UPD : VSTQQQQWBPseudo<IIC_VST4u>; 1984def VST4q16oddPseudo_UPD : VSTQQQQWBPseudo<IIC_VST4u>; 1985def VST4q32oddPseudo_UPD : VSTQQQQWBPseudo<IIC_VST4u>; 1986 1987} // mayStore = 1, neverHasSideEffects = 1, hasExtraSrcRegAllocReq = 1 1988 1989// Classes for VST*LN pseudo-instructions with multi-register operands. 1990// These are expanded to real instructions after register allocation. 1991class VSTQLNPseudo<InstrItinClass itin> 1992 : PseudoNLdSt<(outs), (ins addrmode6:$addr, QPR:$src, nohash_imm:$lane), 1993 itin, "">; 1994class VSTQLNWBPseudo<InstrItinClass itin> 1995 : PseudoNLdSt<(outs GPR:$wb), 1996 (ins addrmode6:$addr, am6offset:$offset, QPR:$src, 1997 nohash_imm:$lane), itin, "$addr.addr = $wb">; 1998class VSTQQLNPseudo<InstrItinClass itin> 1999 : PseudoNLdSt<(outs), (ins addrmode6:$addr, QQPR:$src, nohash_imm:$lane), 2000 itin, "">; 2001class VSTQQLNWBPseudo<InstrItinClass itin> 2002 : PseudoNLdSt<(outs GPR:$wb), 2003 (ins addrmode6:$addr, am6offset:$offset, QQPR:$src, 2004 nohash_imm:$lane), itin, "$addr.addr = $wb">; 2005class VSTQQQQLNPseudo<InstrItinClass itin> 2006 : PseudoNLdSt<(outs), (ins addrmode6:$addr, QQQQPR:$src, nohash_imm:$lane), 2007 itin, "">; 2008class VSTQQQQLNWBPseudo<InstrItinClass itin> 2009 : PseudoNLdSt<(outs GPR:$wb), 2010 (ins addrmode6:$addr, am6offset:$offset, QQQQPR:$src, 2011 nohash_imm:$lane), itin, "$addr.addr = $wb">; 2012 2013// VST1LN : Vector Store (single element from one lane) 2014class VST1LN<bits<4> op11_8, bits<4> op7_4, string Dt, ValueType Ty, 2015 PatFrag StoreOp, SDNode ExtractOp> 2016 : NLdStLn<1, 0b00, op11_8, op7_4, (outs), 2017 (ins addrmode6:$Rn, DPR:$Vd, nohash_imm:$lane), 2018 IIC_VST1ln, "vst1", Dt, "\\{$Vd[$lane]\\}, $Rn", "", 2019 [(StoreOp (ExtractOp (Ty DPR:$Vd), imm:$lane), addrmode6:$Rn)]> { 2020 let Rm = 0b1111; 2021 let DecoderMethod = "DecodeVST1LN"; 2022} 2023class VST1LN32<bits<4> op11_8, bits<4> op7_4, string Dt, ValueType Ty, 2024 PatFrag StoreOp, SDNode ExtractOp> 2025 : NLdStLn<1, 0b00, op11_8, op7_4, (outs), 2026 (ins addrmode6oneL32:$Rn, DPR:$Vd, nohash_imm:$lane), 2027 IIC_VST1ln, "vst1", Dt, "\\{$Vd[$lane]\\}, $Rn", "", 2028 [(StoreOp (ExtractOp (Ty DPR:$Vd), imm:$lane), addrmode6oneL32:$Rn)]>{ 2029 let Rm = 0b1111; 2030 let DecoderMethod = "DecodeVST1LN"; 2031} 2032class VST1QLNPseudo<ValueType Ty, PatFrag StoreOp, SDNode ExtractOp> 2033 : VSTQLNPseudo<IIC_VST1ln> { 2034 let Pattern = [(StoreOp (ExtractOp (Ty QPR:$src), imm:$lane), 2035 addrmode6:$addr)]; 2036} 2037 2038def VST1LNd8 : VST1LN<0b0000, {?,?,?,0}, "8", v8i8, truncstorei8, 2039 NEONvgetlaneu> { 2040 let Inst{7-5} = lane{2-0}; 2041} 2042def VST1LNd16 : VST1LN<0b0100, {?,?,0,?}, "16", v4i16, truncstorei16, 2043 NEONvgetlaneu> { 2044 let Inst{7-6} = lane{1-0}; 2045 let Inst{4} = Rn{5}; 2046} 2047 2048def VST1LNd32 : VST1LN32<0b1000, {?,0,?,?}, "32", v2i32, store, extractelt> { 2049 let Inst{7} = lane{0}; 2050 let Inst{5-4} = Rn{5-4}; 2051} 2052 2053def VST1LNq8Pseudo : VST1QLNPseudo<v16i8, truncstorei8, NEONvgetlaneu>; 2054def VST1LNq16Pseudo : VST1QLNPseudo<v8i16, truncstorei16, NEONvgetlaneu>; 2055def VST1LNq32Pseudo : VST1QLNPseudo<v4i32, store, extractelt>; 2056 2057def : Pat<(store (extractelt (v2f32 DPR:$src), imm:$lane), addrmode6:$addr), 2058 (VST1LNd32 addrmode6:$addr, DPR:$src, imm:$lane)>; 2059def : Pat<(store (extractelt (v4f32 QPR:$src), imm:$lane), addrmode6:$addr), 2060 (VST1LNq32Pseudo addrmode6:$addr, QPR:$src, imm:$lane)>; 2061 2062// ...with address register writeback: 2063class VST1LNWB<bits<4> op11_8, bits<4> op7_4, string Dt, ValueType Ty, 2064 PatFrag StoreOp, SDNode ExtractOp> 2065 : NLdStLn<1, 0b00, op11_8, op7_4, (outs GPR:$wb), 2066 (ins addrmode6:$Rn, am6offset:$Rm, 2067 DPR:$Vd, nohash_imm:$lane), IIC_VST1lnu, "vst1", Dt, 2068 "\\{$Vd[$lane]\\}, $Rn$Rm", 2069 "$Rn.addr = $wb", 2070 [(set GPR:$wb, (StoreOp (ExtractOp (Ty DPR:$Vd), imm:$lane), 2071 addrmode6:$Rn, am6offset:$Rm))]> { 2072 let DecoderMethod = "DecodeVST1LN"; 2073} 2074class VST1QLNWBPseudo<ValueType Ty, PatFrag StoreOp, SDNode ExtractOp> 2075 : VSTQLNWBPseudo<IIC_VST1lnu> { 2076 let Pattern = [(set GPR:$wb, (StoreOp (ExtractOp (Ty QPR:$src), imm:$lane), 2077 addrmode6:$addr, am6offset:$offset))]; 2078} 2079 2080def VST1LNd8_UPD : VST1LNWB<0b0000, {?,?,?,0}, "8", v8i8, post_truncsti8, 2081 NEONvgetlaneu> { 2082 let Inst{7-5} = lane{2-0}; 2083} 2084def VST1LNd16_UPD : VST1LNWB<0b0100, {?,?,0,?}, "16", v4i16, post_truncsti16, 2085 NEONvgetlaneu> { 2086 let Inst{7-6} = lane{1-0}; 2087 let Inst{4} = Rn{5}; 2088} 2089def VST1LNd32_UPD : VST1LNWB<0b1000, {?,0,?,?}, "32", v2i32, post_store, 2090 extractelt> { 2091 let Inst{7} = lane{0}; 2092 let Inst{5-4} = Rn{5-4}; 2093} 2094 2095def VST1LNq8Pseudo_UPD : VST1QLNWBPseudo<v16i8, post_truncsti8, NEONvgetlaneu>; 2096def VST1LNq16Pseudo_UPD : VST1QLNWBPseudo<v8i16, post_truncsti16,NEONvgetlaneu>; 2097def VST1LNq32Pseudo_UPD : VST1QLNWBPseudo<v4i32, post_store, extractelt>; 2098 2099let mayStore = 1, neverHasSideEffects = 1, hasExtraSrcRegAllocReq = 1 in { 2100 2101// VST2LN : Vector Store (single 2-element structure from one lane) 2102class VST2LN<bits<4> op11_8, bits<4> op7_4, string Dt> 2103 : NLdStLn<1, 0b00, op11_8, op7_4, (outs), 2104 (ins addrmode6:$Rn, DPR:$Vd, DPR:$src2, nohash_imm:$lane), 2105 IIC_VST2ln, "vst2", Dt, "\\{$Vd[$lane], $src2[$lane]\\}, $Rn", 2106 "", []> { 2107 let Rm = 0b1111; 2108 let Inst{4} = Rn{4}; 2109 let DecoderMethod = "DecodeVST2LN"; 2110} 2111 2112def VST2LNd8 : VST2LN<0b0001, {?,?,?,?}, "8"> { 2113 let Inst{7-5} = lane{2-0}; 2114} 2115def VST2LNd16 : VST2LN<0b0101, {?,?,0,?}, "16"> { 2116 let Inst{7-6} = lane{1-0}; 2117} 2118def VST2LNd32 : VST2LN<0b1001, {?,0,0,?}, "32"> { 2119 let Inst{7} = lane{0}; 2120} 2121 2122def VST2LNd8Pseudo : VSTQLNPseudo<IIC_VST2ln>; 2123def VST2LNd16Pseudo : VSTQLNPseudo<IIC_VST2ln>; 2124def VST2LNd32Pseudo : VSTQLNPseudo<IIC_VST2ln>; 2125 2126// ...with double-spaced registers: 2127def VST2LNq16 : VST2LN<0b0101, {?,?,1,?}, "16"> { 2128 let Inst{7-6} = lane{1-0}; 2129 let Inst{4} = Rn{4}; 2130} 2131def VST2LNq32 : VST2LN<0b1001, {?,1,0,?}, "32"> { 2132 let Inst{7} = lane{0}; 2133 let Inst{4} = Rn{4}; 2134} 2135 2136def VST2LNq16Pseudo : VSTQQLNPseudo<IIC_VST2ln>; 2137def VST2LNq32Pseudo : VSTQQLNPseudo<IIC_VST2ln>; 2138 2139// ...with address register writeback: 2140class VST2LNWB<bits<4> op11_8, bits<4> op7_4, string Dt> 2141 : NLdStLn<1, 0b00, op11_8, op7_4, (outs GPR:$wb), 2142 (ins addrmode6:$Rn, am6offset:$Rm, 2143 DPR:$Vd, DPR:$src2, nohash_imm:$lane), IIC_VST2lnu, "vst2", Dt, 2144 "\\{$Vd[$lane], $src2[$lane]\\}, $Rn$Rm", 2145 "$Rn.addr = $wb", []> { 2146 let Inst{4} = Rn{4}; 2147 let DecoderMethod = "DecodeVST2LN"; 2148} 2149 2150def VST2LNd8_UPD : VST2LNWB<0b0001, {?,?,?,?}, "8"> { 2151 let Inst{7-5} = lane{2-0}; 2152} 2153def VST2LNd16_UPD : VST2LNWB<0b0101, {?,?,0,?}, "16"> { 2154 let Inst{7-6} = lane{1-0}; 2155} 2156def VST2LNd32_UPD : VST2LNWB<0b1001, {?,0,0,?}, "32"> { 2157 let Inst{7} = lane{0}; 2158} 2159 2160def VST2LNd8Pseudo_UPD : VSTQLNWBPseudo<IIC_VST2lnu>; 2161def VST2LNd16Pseudo_UPD : VSTQLNWBPseudo<IIC_VST2lnu>; 2162def VST2LNd32Pseudo_UPD : VSTQLNWBPseudo<IIC_VST2lnu>; 2163 2164def VST2LNq16_UPD : VST2LNWB<0b0101, {?,?,1,?}, "16"> { 2165 let Inst{7-6} = lane{1-0}; 2166} 2167def VST2LNq32_UPD : VST2LNWB<0b1001, {?,1,0,?}, "32"> { 2168 let Inst{7} = lane{0}; 2169} 2170 2171def VST2LNq16Pseudo_UPD : VSTQQLNWBPseudo<IIC_VST2lnu>; 2172def VST2LNq32Pseudo_UPD : VSTQQLNWBPseudo<IIC_VST2lnu>; 2173 2174// VST3LN : Vector Store (single 3-element structure from one lane) 2175class VST3LN<bits<4> op11_8, bits<4> op7_4, string Dt> 2176 : NLdStLn<1, 0b00, op11_8, op7_4, (outs), 2177 (ins addrmode6:$Rn, DPR:$Vd, DPR:$src2, DPR:$src3, 2178 nohash_imm:$lane), IIC_VST3ln, "vst3", Dt, 2179 "\\{$Vd[$lane], $src2[$lane], $src3[$lane]\\}, $Rn", "", []> { 2180 let Rm = 0b1111; 2181 let DecoderMethod = "DecodeVST3LN"; 2182} 2183 2184def VST3LNd8 : VST3LN<0b0010, {?,?,?,0}, "8"> { 2185 let Inst{7-5} = lane{2-0}; 2186} 2187def VST3LNd16 : VST3LN<0b0110, {?,?,0,0}, "16"> { 2188 let Inst{7-6} = lane{1-0}; 2189} 2190def VST3LNd32 : VST3LN<0b1010, {?,0,0,0}, "32"> { 2191 let Inst{7} = lane{0}; 2192} 2193 2194def VST3LNd8Pseudo : VSTQQLNPseudo<IIC_VST3ln>; 2195def VST3LNd16Pseudo : VSTQQLNPseudo<IIC_VST3ln>; 2196def VST3LNd32Pseudo : VSTQQLNPseudo<IIC_VST3ln>; 2197 2198// ...with double-spaced registers: 2199def VST3LNq16 : VST3LN<0b0110, {?,?,1,0}, "16"> { 2200 let Inst{7-6} = lane{1-0}; 2201} 2202def VST3LNq32 : VST3LN<0b1010, {?,1,0,0}, "32"> { 2203 let Inst{7} = lane{0}; 2204} 2205 2206def VST3LNq16Pseudo : VSTQQQQLNPseudo<IIC_VST3ln>; 2207def VST3LNq32Pseudo : VSTQQQQLNPseudo<IIC_VST3ln>; 2208 2209// ...with address register writeback: 2210class VST3LNWB<bits<4> op11_8, bits<4> op7_4, string Dt> 2211 : NLdStLn<1, 0b00, op11_8, op7_4, (outs GPR:$wb), 2212 (ins addrmode6:$Rn, am6offset:$Rm, 2213 DPR:$Vd, DPR:$src2, DPR:$src3, nohash_imm:$lane), 2214 IIC_VST3lnu, "vst3", Dt, 2215 "\\{$Vd[$lane], $src2[$lane], $src3[$lane]\\}, $Rn$Rm", 2216 "$Rn.addr = $wb", []> { 2217 let DecoderMethod = "DecodeVST3LN"; 2218} 2219 2220def VST3LNd8_UPD : VST3LNWB<0b0010, {?,?,?,0}, "8"> { 2221 let Inst{7-5} = lane{2-0}; 2222} 2223def VST3LNd16_UPD : VST3LNWB<0b0110, {?,?,0,0}, "16"> { 2224 let Inst{7-6} = lane{1-0}; 2225} 2226def VST3LNd32_UPD : VST3LNWB<0b1010, {?,0,0,0}, "32"> { 2227 let Inst{7} = lane{0}; 2228} 2229 2230def VST3LNd8Pseudo_UPD : VSTQQLNWBPseudo<IIC_VST3lnu>; 2231def VST3LNd16Pseudo_UPD : VSTQQLNWBPseudo<IIC_VST3lnu>; 2232def VST3LNd32Pseudo_UPD : VSTQQLNWBPseudo<IIC_VST3lnu>; 2233 2234def VST3LNq16_UPD : VST3LNWB<0b0110, {?,?,1,0}, "16"> { 2235 let Inst{7-6} = lane{1-0}; 2236} 2237def VST3LNq32_UPD : VST3LNWB<0b1010, {?,1,0,0}, "32"> { 2238 let Inst{7} = lane{0}; 2239} 2240 2241def VST3LNq16Pseudo_UPD : VSTQQQQLNWBPseudo<IIC_VST3lnu>; 2242def VST3LNq32Pseudo_UPD : VSTQQQQLNWBPseudo<IIC_VST3lnu>; 2243 2244// VST4LN : Vector Store (single 4-element structure from one lane) 2245class VST4LN<bits<4> op11_8, bits<4> op7_4, string Dt> 2246 : NLdStLn<1, 0b00, op11_8, op7_4, (outs), 2247 (ins addrmode6:$Rn, DPR:$Vd, DPR:$src2, DPR:$src3, DPR:$src4, 2248 nohash_imm:$lane), IIC_VST4ln, "vst4", Dt, 2249 "\\{$Vd[$lane], $src2[$lane], $src3[$lane], $src4[$lane]\\}, $Rn", 2250 "", []> { 2251 let Rm = 0b1111; 2252 let Inst{4} = Rn{4}; 2253 let DecoderMethod = "DecodeVST4LN"; 2254} 2255 2256def VST4LNd8 : VST4LN<0b0011, {?,?,?,?}, "8"> { 2257 let Inst{7-5} = lane{2-0}; 2258} 2259def VST4LNd16 : VST4LN<0b0111, {?,?,0,?}, "16"> { 2260 let Inst{7-6} = lane{1-0}; 2261} 2262def VST4LNd32 : VST4LN<0b1011, {?,0,?,?}, "32"> { 2263 let Inst{7} = lane{0}; 2264 let Inst{5} = Rn{5}; 2265} 2266 2267def VST4LNd8Pseudo : VSTQQLNPseudo<IIC_VST4ln>; 2268def VST4LNd16Pseudo : VSTQQLNPseudo<IIC_VST4ln>; 2269def VST4LNd32Pseudo : VSTQQLNPseudo<IIC_VST4ln>; 2270 2271// ...with double-spaced registers: 2272def VST4LNq16 : VST4LN<0b0111, {?,?,1,?}, "16"> { 2273 let Inst{7-6} = lane{1-0}; 2274} 2275def VST4LNq32 : VST4LN<0b1011, {?,1,?,?}, "32"> { 2276 let Inst{7} = lane{0}; 2277 let Inst{5} = Rn{5}; 2278} 2279 2280def VST4LNq16Pseudo : VSTQQQQLNPseudo<IIC_VST4ln>; 2281def VST4LNq32Pseudo : VSTQQQQLNPseudo<IIC_VST4ln>; 2282 2283// ...with address register writeback: 2284class VST4LNWB<bits<4> op11_8, bits<4> op7_4, string Dt> 2285 : NLdStLn<1, 0b00, op11_8, op7_4, (outs GPR:$wb), 2286 (ins addrmode6:$Rn, am6offset:$Rm, 2287 DPR:$Vd, DPR:$src2, DPR:$src3, DPR:$src4, nohash_imm:$lane), 2288 IIC_VST4lnu, "vst4", Dt, 2289 "\\{$Vd[$lane], $src2[$lane], $src3[$lane], $src4[$lane]\\}, $Rn$Rm", 2290 "$Rn.addr = $wb", []> { 2291 let Inst{4} = Rn{4}; 2292 let DecoderMethod = "DecodeVST4LN"; 2293} 2294 2295def VST4LNd8_UPD : VST4LNWB<0b0011, {?,?,?,?}, "8"> { 2296 let Inst{7-5} = lane{2-0}; 2297} 2298def VST4LNd16_UPD : VST4LNWB<0b0111, {?,?,0,?}, "16"> { 2299 let Inst{7-6} = lane{1-0}; 2300} 2301def VST4LNd32_UPD : VST4LNWB<0b1011, {?,0,?,?}, "32"> { 2302 let Inst{7} = lane{0}; 2303 let Inst{5} = Rn{5}; 2304} 2305 2306def VST4LNd8Pseudo_UPD : VSTQQLNWBPseudo<IIC_VST4lnu>; 2307def VST4LNd16Pseudo_UPD : VSTQQLNWBPseudo<IIC_VST4lnu>; 2308def VST4LNd32Pseudo_UPD : VSTQQLNWBPseudo<IIC_VST4lnu>; 2309 2310def VST4LNq16_UPD : VST4LNWB<0b0111, {?,?,1,?}, "16"> { 2311 let Inst{7-6} = lane{1-0}; 2312} 2313def VST4LNq32_UPD : VST4LNWB<0b1011, {?,1,?,?}, "32"> { 2314 let Inst{7} = lane{0}; 2315 let Inst{5} = Rn{5}; 2316} 2317 2318def VST4LNq16Pseudo_UPD : VSTQQQQLNWBPseudo<IIC_VST4lnu>; 2319def VST4LNq32Pseudo_UPD : VSTQQQQLNWBPseudo<IIC_VST4lnu>; 2320 2321} // mayStore = 1, neverHasSideEffects = 1, hasExtraSrcRegAllocReq = 1 2322 2323 2324//===----------------------------------------------------------------------===// 2325// NEON pattern fragments 2326//===----------------------------------------------------------------------===// 2327 2328// Extract D sub-registers of Q registers. 2329def DSubReg_i8_reg : SDNodeXForm<imm, [{ 2330 assert(ARM::dsub_7 == ARM::dsub_0+7 && "Unexpected subreg numbering"); 2331 return CurDAG->getTargetConstant(ARM::dsub_0 + N->getZExtValue()/8, MVT::i32); 2332}]>; 2333def DSubReg_i16_reg : SDNodeXForm<imm, [{ 2334 assert(ARM::dsub_7 == ARM::dsub_0+7 && "Unexpected subreg numbering"); 2335 return CurDAG->getTargetConstant(ARM::dsub_0 + N->getZExtValue()/4, MVT::i32); 2336}]>; 2337def DSubReg_i32_reg : SDNodeXForm<imm, [{ 2338 assert(ARM::dsub_7 == ARM::dsub_0+7 && "Unexpected subreg numbering"); 2339 return CurDAG->getTargetConstant(ARM::dsub_0 + N->getZExtValue()/2, MVT::i32); 2340}]>; 2341def DSubReg_f64_reg : SDNodeXForm<imm, [{ 2342 assert(ARM::dsub_7 == ARM::dsub_0+7 && "Unexpected subreg numbering"); 2343 return CurDAG->getTargetConstant(ARM::dsub_0 + N->getZExtValue(), MVT::i32); 2344}]>; 2345 2346// Extract S sub-registers of Q/D registers. 2347def SSubReg_f32_reg : SDNodeXForm<imm, [{ 2348 assert(ARM::ssub_3 == ARM::ssub_0+3 && "Unexpected subreg numbering"); 2349 return CurDAG->getTargetConstant(ARM::ssub_0 + N->getZExtValue(), MVT::i32); 2350}]>; 2351 2352// Translate lane numbers from Q registers to D subregs. 2353def SubReg_i8_lane : SDNodeXForm<imm, [{ 2354 return CurDAG->getTargetConstant(N->getZExtValue() & 7, MVT::i32); 2355}]>; 2356def SubReg_i16_lane : SDNodeXForm<imm, [{ 2357 return CurDAG->getTargetConstant(N->getZExtValue() & 3, MVT::i32); 2358}]>; 2359def SubReg_i32_lane : SDNodeXForm<imm, [{ 2360 return CurDAG->getTargetConstant(N->getZExtValue() & 1, MVT::i32); 2361}]>; 2362 2363//===----------------------------------------------------------------------===// 2364// Instruction Classes 2365//===----------------------------------------------------------------------===// 2366 2367// Basic 2-register operations: double- and quad-register. 2368class N2VD<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18, 2369 bits<2> op17_16, bits<5> op11_7, bit op4, string OpcodeStr, 2370 string Dt, ValueType ResTy, ValueType OpTy, SDNode OpNode> 2371 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, 0, op4, (outs DPR:$Vd), 2372 (ins DPR:$Vm), IIC_VUNAD, OpcodeStr, Dt,"$Vd, $Vm", "", 2373 [(set DPR:$Vd, (ResTy (OpNode (OpTy DPR:$Vm))))]>; 2374class N2VQ<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18, 2375 bits<2> op17_16, bits<5> op11_7, bit op4, string OpcodeStr, 2376 string Dt, ValueType ResTy, ValueType OpTy, SDNode OpNode> 2377 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, 1, op4, (outs QPR:$Vd), 2378 (ins QPR:$Vm), IIC_VUNAQ, OpcodeStr, Dt,"$Vd, $Vm", "", 2379 [(set QPR:$Vd, (ResTy (OpNode (OpTy QPR:$Vm))))]>; 2380 2381// Basic 2-register intrinsics, both double- and quad-register. 2382class N2VDInt<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18, 2383 bits<2> op17_16, bits<5> op11_7, bit op4, 2384 InstrItinClass itin, string OpcodeStr, string Dt, 2385 ValueType ResTy, ValueType OpTy, Intrinsic IntOp> 2386 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, 0, op4, (outs DPR:$Vd), 2387 (ins DPR:$Vm), itin, OpcodeStr, Dt, "$Vd, $Vm", "", 2388 [(set DPR:$Vd, (ResTy (IntOp (OpTy DPR:$Vm))))]>; 2389class N2VQInt<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18, 2390 bits<2> op17_16, bits<5> op11_7, bit op4, 2391 InstrItinClass itin, string OpcodeStr, string Dt, 2392 ValueType ResTy, ValueType OpTy, Intrinsic IntOp> 2393 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, 1, op4, (outs QPR:$Vd), 2394 (ins QPR:$Vm), itin, OpcodeStr, Dt, "$Vd, $Vm", "", 2395 [(set QPR:$Vd, (ResTy (IntOp (OpTy QPR:$Vm))))]>; 2396 2397// Narrow 2-register operations. 2398class N2VN<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18, 2399 bits<2> op17_16, bits<5> op11_7, bit op6, bit op4, 2400 InstrItinClass itin, string OpcodeStr, string Dt, 2401 ValueType TyD, ValueType TyQ, SDNode OpNode> 2402 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, op6, op4, (outs DPR:$Vd), 2403 (ins QPR:$Vm), itin, OpcodeStr, Dt, "$Vd, $Vm", "", 2404 [(set DPR:$Vd, (TyD (OpNode (TyQ QPR:$Vm))))]>; 2405 2406// Narrow 2-register intrinsics. 2407class N2VNInt<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18, 2408 bits<2> op17_16, bits<5> op11_7, bit op6, bit op4, 2409 InstrItinClass itin, string OpcodeStr, string Dt, 2410 ValueType TyD, ValueType TyQ, Intrinsic IntOp> 2411 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, op6, op4, (outs DPR:$Vd), 2412 (ins QPR:$Vm), itin, OpcodeStr, Dt, "$Vd, $Vm", "", 2413 [(set DPR:$Vd, (TyD (IntOp (TyQ QPR:$Vm))))]>; 2414 2415// Long 2-register operations (currently only used for VMOVL). 2416class N2VL<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18, 2417 bits<2> op17_16, bits<5> op11_7, bit op6, bit op4, 2418 InstrItinClass itin, string OpcodeStr, string Dt, 2419 ValueType TyQ, ValueType TyD, SDNode OpNode> 2420 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, op6, op4, (outs QPR:$Vd), 2421 (ins DPR:$Vm), itin, OpcodeStr, Dt, "$Vd, $Vm", "", 2422 [(set QPR:$Vd, (TyQ (OpNode (TyD DPR:$Vm))))]>; 2423 2424// Long 2-register intrinsics. 2425class N2VLInt<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18, 2426 bits<2> op17_16, bits<5> op11_7, bit op6, bit op4, 2427 InstrItinClass itin, string OpcodeStr, string Dt, 2428 ValueType TyQ, ValueType TyD, Intrinsic IntOp> 2429 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, op6, op4, (outs QPR:$Vd), 2430 (ins DPR:$Vm), itin, OpcodeStr, Dt, "$Vd, $Vm", "", 2431 [(set QPR:$Vd, (TyQ (IntOp (TyD DPR:$Vm))))]>; 2432 2433// 2-register shuffles (VTRN/VZIP/VUZP), both double- and quad-register. 2434class N2VDShuffle<bits<2> op19_18, bits<5> op11_7, string OpcodeStr, string Dt> 2435 : N2V<0b11, 0b11, op19_18, 0b10, op11_7, 0, 0, (outs DPR:$Vd, DPR:$Vm), 2436 (ins DPR:$src1, DPR:$src2), IIC_VPERMD, 2437 OpcodeStr, Dt, "$Vd, $Vm", 2438 "$src1 = $Vd, $src2 = $Vm", []>; 2439class N2VQShuffle<bits<2> op19_18, bits<5> op11_7, 2440 InstrItinClass itin, string OpcodeStr, string Dt> 2441 : N2V<0b11, 0b11, op19_18, 0b10, op11_7, 1, 0, (outs QPR:$Vd, QPR:$Vm), 2442 (ins QPR:$src1, QPR:$src2), itin, OpcodeStr, Dt, "$Vd, $Vm", 2443 "$src1 = $Vd, $src2 = $Vm", []>; 2444 2445// Basic 3-register operations: double- and quad-register. 2446class N3VD<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4, 2447 InstrItinClass itin, string OpcodeStr, string Dt, 2448 ValueType ResTy, ValueType OpTy, SDNode OpNode, bit Commutable> 2449 : N3V<op24, op23, op21_20, op11_8, 0, op4, 2450 (outs DPR:$Vd), (ins DPR:$Vn, DPR:$Vm), N3RegFrm, itin, 2451 OpcodeStr, Dt, "$Vd, $Vn, $Vm", "", 2452 [(set DPR:$Vd, (ResTy (OpNode (OpTy DPR:$Vn), (OpTy DPR:$Vm))))]> { 2453 let isCommutable = Commutable; 2454} 2455// Same as N3VD but no data type. 2456class N3VDX<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4, 2457 InstrItinClass itin, string OpcodeStr, 2458 ValueType ResTy, ValueType OpTy, 2459 SDNode OpNode, bit Commutable> 2460 : N3VX<op24, op23, op21_20, op11_8, 0, op4, 2461 (outs DPR:$Vd), (ins DPR:$Vn, DPR:$Vm), N3RegFrm, itin, 2462 OpcodeStr, "$Vd, $Vn, $Vm", "", 2463 [(set DPR:$Vd, (ResTy (OpNode (OpTy DPR:$Vn), (OpTy DPR:$Vm))))]>{ 2464 let isCommutable = Commutable; 2465} 2466 2467class N3VDSL<bits<2> op21_20, bits<4> op11_8, 2468 InstrItinClass itin, string OpcodeStr, string Dt, 2469 ValueType Ty, SDNode ShOp> 2470 : N3VLane32<0, 1, op21_20, op11_8, 1, 0, 2471 (outs DPR:$Vd), (ins DPR:$Vn, DPR_VFP2:$Vm, VectorIndex32:$lane), 2472 NVMulSLFrm, itin, OpcodeStr, Dt, "$Vd, $Vn, $Vm$lane", "", 2473 [(set (Ty DPR:$Vd), 2474 (Ty (ShOp (Ty DPR:$Vn), 2475 (Ty (NEONvduplane (Ty DPR_VFP2:$Vm),imm:$lane)))))]> { 2476 let isCommutable = 0; 2477} 2478class N3VDSL16<bits<2> op21_20, bits<4> op11_8, 2479 string OpcodeStr, string Dt, ValueType Ty, SDNode ShOp> 2480 : N3VLane16<0, 1, op21_20, op11_8, 1, 0, 2481 (outs DPR:$Vd), (ins DPR:$Vn, DPR_8:$Vm, VectorIndex16:$lane), 2482 NVMulSLFrm, IIC_VMULi16D, OpcodeStr, Dt,"$Vd, $Vn, $Vm$lane","", 2483 [(set (Ty DPR:$Vd), 2484 (Ty (ShOp (Ty DPR:$Vn), 2485 (Ty (NEONvduplane (Ty DPR_8:$Vm), imm:$lane)))))]> { 2486 let isCommutable = 0; 2487} 2488 2489class N3VQ<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4, 2490 InstrItinClass itin, string OpcodeStr, string Dt, 2491 ValueType ResTy, ValueType OpTy, SDNode OpNode, bit Commutable> 2492 : N3V<op24, op23, op21_20, op11_8, 1, op4, 2493 (outs QPR:$Vd), (ins QPR:$Vn, QPR:$Vm), N3RegFrm, itin, 2494 OpcodeStr, Dt, "$Vd, $Vn, $Vm", "", 2495 [(set QPR:$Vd, (ResTy (OpNode (OpTy QPR:$Vn), (OpTy QPR:$Vm))))]> { 2496 let isCommutable = Commutable; 2497} 2498class N3VQX<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4, 2499 InstrItinClass itin, string OpcodeStr, 2500 ValueType ResTy, ValueType OpTy, SDNode OpNode, bit Commutable> 2501 : N3VX<op24, op23, op21_20, op11_8, 1, op4, 2502 (outs QPR:$Vd), (ins QPR:$Vn, QPR:$Vm), N3RegFrm, itin, 2503 OpcodeStr, "$Vd, $Vn, $Vm", "", 2504 [(set QPR:$Vd, (ResTy (OpNode (OpTy QPR:$Vn), (OpTy QPR:$Vm))))]>{ 2505 let isCommutable = Commutable; 2506} 2507class N3VQSL<bits<2> op21_20, bits<4> op11_8, 2508 InstrItinClass itin, string OpcodeStr, string Dt, 2509 ValueType ResTy, ValueType OpTy, SDNode ShOp> 2510 : N3VLane32<1, 1, op21_20, op11_8, 1, 0, 2511 (outs QPR:$Vd), (ins QPR:$Vn, DPR_VFP2:$Vm, VectorIndex32:$lane), 2512 NVMulSLFrm, itin, OpcodeStr, Dt, "$Vd, $Vn, $Vm$lane", "", 2513 [(set (ResTy QPR:$Vd), 2514 (ResTy (ShOp (ResTy QPR:$Vn), 2515 (ResTy (NEONvduplane (OpTy DPR_VFP2:$Vm), 2516 imm:$lane)))))]> { 2517 let isCommutable = 0; 2518} 2519class N3VQSL16<bits<2> op21_20, bits<4> op11_8, string OpcodeStr, string Dt, 2520 ValueType ResTy, ValueType OpTy, SDNode ShOp> 2521 : N3VLane16<1, 1, op21_20, op11_8, 1, 0, 2522 (outs QPR:$Vd), (ins QPR:$Vn, DPR_8:$Vm, VectorIndex16:$lane), 2523 NVMulSLFrm, IIC_VMULi16Q, OpcodeStr, Dt,"$Vd, $Vn, $Vm$lane", "", 2524 [(set (ResTy QPR:$Vd), 2525 (ResTy (ShOp (ResTy QPR:$Vn), 2526 (ResTy (NEONvduplane (OpTy DPR_8:$Vm), 2527 imm:$lane)))))]> { 2528 let isCommutable = 0; 2529} 2530 2531// Basic 3-register intrinsics, both double- and quad-register. 2532class N3VDInt<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4, 2533 Format f, InstrItinClass itin, string OpcodeStr, string Dt, 2534 ValueType ResTy, ValueType OpTy, Intrinsic IntOp, bit Commutable> 2535 : N3V<op24, op23, op21_20, op11_8, 0, op4, 2536 (outs DPR:$Vd), (ins DPR:$Vn, DPR:$Vm), f, itin, 2537 OpcodeStr, Dt, "$Vd, $Vn, $Vm", "", 2538 [(set DPR:$Vd, (ResTy (IntOp (OpTy DPR:$Vn), (OpTy DPR:$Vm))))]> { 2539 let isCommutable = Commutable; 2540} 2541class N3VDIntSL<bits<2> op21_20, bits<4> op11_8, InstrItinClass itin, 2542 string OpcodeStr, string Dt, ValueType Ty, Intrinsic IntOp> 2543 : N3VLane32<0, 1, op21_20, op11_8, 1, 0, 2544 (outs DPR:$Vd), (ins DPR:$Vn, DPR_VFP2:$Vm, VectorIndex32:$lane), 2545 NVMulSLFrm, itin, OpcodeStr, Dt, "$Vd, $Vn, $Vm$lane", "", 2546 [(set (Ty DPR:$Vd), 2547 (Ty (IntOp (Ty DPR:$Vn), 2548 (Ty (NEONvduplane (Ty DPR_VFP2:$Vm), 2549 imm:$lane)))))]> { 2550 let isCommutable = 0; 2551} 2552class N3VDIntSL16<bits<2> op21_20, bits<4> op11_8, InstrItinClass itin, 2553 string OpcodeStr, string Dt, ValueType Ty, Intrinsic IntOp> 2554 : N3VLane16<0, 1, op21_20, op11_8, 1, 0, 2555 (outs DPR:$Vd), (ins DPR:$Vn, DPR_8:$Vm, VectorIndex16:$lane), 2556 NVMulSLFrm, itin, OpcodeStr, Dt, "$Vd, $Vn, $Vm$lane", "", 2557 [(set (Ty DPR:$Vd), 2558 (Ty (IntOp (Ty DPR:$Vn), 2559 (Ty (NEONvduplane (Ty DPR_8:$Vm), imm:$lane)))))]> { 2560 let isCommutable = 0; 2561} 2562class N3VDIntSh<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4, 2563 Format f, InstrItinClass itin, string OpcodeStr, string Dt, 2564 ValueType ResTy, ValueType OpTy, Intrinsic IntOp> 2565 : N3V<op24, op23, op21_20, op11_8, 0, op4, 2566 (outs DPR:$Vd), (ins DPR:$Vm, DPR:$Vn), f, itin, 2567 OpcodeStr, Dt, "$Vd, $Vm, $Vn", "", 2568 [(set DPR:$Vd, (ResTy (IntOp (OpTy DPR:$Vm), (OpTy DPR:$Vn))))]> { 2569 let isCommutable = 0; 2570} 2571 2572class N3VQInt<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4, 2573 Format f, InstrItinClass itin, string OpcodeStr, string Dt, 2574 ValueType ResTy, ValueType OpTy, Intrinsic IntOp, bit Commutable> 2575 : N3V<op24, op23, op21_20, op11_8, 1, op4, 2576 (outs QPR:$Vd), (ins QPR:$Vn, QPR:$Vm), f, itin, 2577 OpcodeStr, Dt, "$Vd, $Vn, $Vm", "", 2578 [(set QPR:$Vd, (ResTy (IntOp (OpTy QPR:$Vn), (OpTy QPR:$Vm))))]> { 2579 let isCommutable = Commutable; 2580} 2581class N3VQIntSL<bits<2> op21_20, bits<4> op11_8, InstrItinClass itin, 2582 string OpcodeStr, string Dt, 2583 ValueType ResTy, ValueType OpTy, Intrinsic IntOp> 2584 : N3VLane32<1, 1, op21_20, op11_8, 1, 0, 2585 (outs QPR:$Vd), (ins QPR:$Vn, DPR_VFP2:$Vm, VectorIndex32:$lane), 2586 NVMulSLFrm, itin, OpcodeStr, Dt, "$Vd, $Vn, $Vm$lane", "", 2587 [(set (ResTy QPR:$Vd), 2588 (ResTy (IntOp (ResTy QPR:$Vn), 2589 (ResTy (NEONvduplane (OpTy DPR_VFP2:$Vm), 2590 imm:$lane)))))]> { 2591 let isCommutable = 0; 2592} 2593class N3VQIntSL16<bits<2> op21_20, bits<4> op11_8, InstrItinClass itin, 2594 string OpcodeStr, string Dt, 2595 ValueType ResTy, ValueType OpTy, Intrinsic IntOp> 2596 : N3VLane16<1, 1, op21_20, op11_8, 1, 0, 2597 (outs QPR:$Vd), (ins QPR:$Vn, DPR_8:$Vm, VectorIndex16:$lane), 2598 NVMulSLFrm, itin, OpcodeStr, Dt, "$Vd, $Vn, $Vm$lane", "", 2599 [(set (ResTy QPR:$Vd), 2600 (ResTy (IntOp (ResTy QPR:$Vn), 2601 (ResTy (NEONvduplane (OpTy DPR_8:$Vm), 2602 imm:$lane)))))]> { 2603 let isCommutable = 0; 2604} 2605class N3VQIntSh<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4, 2606 Format f, InstrItinClass itin, string OpcodeStr, string Dt, 2607 ValueType ResTy, ValueType OpTy, Intrinsic IntOp> 2608 : N3V<op24, op23, op21_20, op11_8, 1, op4, 2609 (outs QPR:$Vd), (ins QPR:$Vm, QPR:$Vn), f, itin, 2610 OpcodeStr, Dt, "$Vd, $Vm, $Vn", "", 2611 [(set QPR:$Vd, (ResTy (IntOp (OpTy QPR:$Vm), (OpTy QPR:$Vn))))]> { 2612 let isCommutable = 0; 2613} 2614 2615// Multiply-Add/Sub operations: double- and quad-register. 2616class N3VDMulOp<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4, 2617 InstrItinClass itin, string OpcodeStr, string Dt, 2618 ValueType Ty, SDPatternOperator MulOp, SDPatternOperator OpNode> 2619 : N3V<op24, op23, op21_20, op11_8, 0, op4, 2620 (outs DPR:$Vd), (ins DPR:$src1, DPR:$Vn, DPR:$Vm), N3RegFrm, itin, 2621 OpcodeStr, Dt, "$Vd, $Vn, $Vm", "$src1 = $Vd", 2622 [(set DPR:$Vd, (Ty (OpNode DPR:$src1, 2623 (Ty (MulOp DPR:$Vn, DPR:$Vm)))))]>; 2624 2625class N3VDMulOpSL<bits<2> op21_20, bits<4> op11_8, InstrItinClass itin, 2626 string OpcodeStr, string Dt, 2627 ValueType Ty, SDPatternOperator MulOp, SDPatternOperator ShOp> 2628 : N3VLane32<0, 1, op21_20, op11_8, 1, 0, 2629 (outs DPR:$Vd), 2630 (ins DPR:$src1, DPR:$Vn, DPR_VFP2:$Vm, VectorIndex32:$lane), 2631 NVMulSLFrm, itin, 2632 OpcodeStr, Dt, "$Vd, $Vn, $Vm$lane", "$src1 = $Vd", 2633 [(set (Ty DPR:$Vd), 2634 (Ty (ShOp (Ty DPR:$src1), 2635 (Ty (MulOp DPR:$Vn, 2636 (Ty (NEONvduplane (Ty DPR_VFP2:$Vm), 2637 imm:$lane)))))))]>; 2638class N3VDMulOpSL16<bits<2> op21_20, bits<4> op11_8, InstrItinClass itin, 2639 string OpcodeStr, string Dt, 2640 ValueType Ty, SDNode MulOp, SDNode ShOp> 2641 : N3VLane16<0, 1, op21_20, op11_8, 1, 0, 2642 (outs DPR:$Vd), 2643 (ins DPR:$src1, DPR:$Vn, DPR_8:$Vm, VectorIndex16:$lane), 2644 NVMulSLFrm, itin, 2645 OpcodeStr, Dt, "$Vd, $Vn, $Vm$lane", "$src1 = $Vd", 2646 [(set (Ty DPR:$Vd), 2647 (Ty (ShOp (Ty DPR:$src1), 2648 (Ty (MulOp DPR:$Vn, 2649 (Ty (NEONvduplane (Ty DPR_8:$Vm), 2650 imm:$lane)))))))]>; 2651 2652class N3VQMulOp<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4, 2653 InstrItinClass itin, string OpcodeStr, string Dt, ValueType Ty, 2654 SDPatternOperator MulOp, SDPatternOperator OpNode> 2655 : N3V<op24, op23, op21_20, op11_8, 1, op4, 2656 (outs QPR:$Vd), (ins QPR:$src1, QPR:$Vn, QPR:$Vm), N3RegFrm, itin, 2657 OpcodeStr, Dt, "$Vd, $Vn, $Vm", "$src1 = $Vd", 2658 [(set QPR:$Vd, (Ty (OpNode QPR:$src1, 2659 (Ty (MulOp QPR:$Vn, QPR:$Vm)))))]>; 2660class N3VQMulOpSL<bits<2> op21_20, bits<4> op11_8, InstrItinClass itin, 2661 string OpcodeStr, string Dt, ValueType ResTy, ValueType OpTy, 2662 SDPatternOperator MulOp, SDPatternOperator ShOp> 2663 : N3VLane32<1, 1, op21_20, op11_8, 1, 0, 2664 (outs QPR:$Vd), 2665 (ins QPR:$src1, QPR:$Vn, DPR_VFP2:$Vm, VectorIndex32:$lane), 2666 NVMulSLFrm, itin, 2667 OpcodeStr, Dt, "$Vd, $Vn, $Vm$lane", "$src1 = $Vd", 2668 [(set (ResTy QPR:$Vd), 2669 (ResTy (ShOp (ResTy QPR:$src1), 2670 (ResTy (MulOp QPR:$Vn, 2671 (ResTy (NEONvduplane (OpTy DPR_VFP2:$Vm), 2672 imm:$lane)))))))]>; 2673class N3VQMulOpSL16<bits<2> op21_20, bits<4> op11_8, InstrItinClass itin, 2674 string OpcodeStr, string Dt, 2675 ValueType ResTy, ValueType OpTy, 2676 SDNode MulOp, SDNode ShOp> 2677 : N3VLane16<1, 1, op21_20, op11_8, 1, 0, 2678 (outs QPR:$Vd), 2679 (ins QPR:$src1, QPR:$Vn, DPR_8:$Vm, VectorIndex16:$lane), 2680 NVMulSLFrm, itin, 2681 OpcodeStr, Dt, "$Vd, $Vn, $Vm$lane", "$src1 = $Vd", 2682 [(set (ResTy QPR:$Vd), 2683 (ResTy (ShOp (ResTy QPR:$src1), 2684 (ResTy (MulOp QPR:$Vn, 2685 (ResTy (NEONvduplane (OpTy DPR_8:$Vm), 2686 imm:$lane)))))))]>; 2687 2688// Neon Intrinsic-Op instructions (VABA): double- and quad-register. 2689class N3VDIntOp<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4, 2690 InstrItinClass itin, string OpcodeStr, string Dt, 2691 ValueType Ty, Intrinsic IntOp, SDNode OpNode> 2692 : N3V<op24, op23, op21_20, op11_8, 0, op4, 2693 (outs DPR:$Vd), (ins DPR:$src1, DPR:$Vn, DPR:$Vm), N3RegFrm, itin, 2694 OpcodeStr, Dt, "$Vd, $Vn, $Vm", "$src1 = $Vd", 2695 [(set DPR:$Vd, (Ty (OpNode DPR:$src1, 2696 (Ty (IntOp (Ty DPR:$Vn), (Ty DPR:$Vm))))))]>; 2697class N3VQIntOp<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4, 2698 InstrItinClass itin, string OpcodeStr, string Dt, 2699 ValueType Ty, Intrinsic IntOp, SDNode OpNode> 2700 : N3V<op24, op23, op21_20, op11_8, 1, op4, 2701 (outs QPR:$Vd), (ins QPR:$src1, QPR:$Vn, QPR:$Vm), N3RegFrm, itin, 2702 OpcodeStr, Dt, "$Vd, $Vn, $Vm", "$src1 = $Vd", 2703 [(set QPR:$Vd, (Ty (OpNode QPR:$src1, 2704 (Ty (IntOp (Ty QPR:$Vn), (Ty QPR:$Vm))))))]>; 2705 2706// Neon 3-argument intrinsics, both double- and quad-register. 2707// The destination register is also used as the first source operand register. 2708class N3VDInt3<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4, 2709 InstrItinClass itin, string OpcodeStr, string Dt, 2710 ValueType ResTy, ValueType OpTy, Intrinsic IntOp> 2711 : N3V<op24, op23, op21_20, op11_8, 0, op4, 2712 (outs DPR:$Vd), (ins DPR:$src1, DPR:$Vn, DPR:$Vm), N3RegFrm, itin, 2713 OpcodeStr, Dt, "$Vd, $Vn, $Vm", "$src1 = $Vd", 2714 [(set DPR:$Vd, (ResTy (IntOp (OpTy DPR:$src1), 2715 (OpTy DPR:$Vn), (OpTy DPR:$Vm))))]>; 2716class N3VQInt3<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4, 2717 InstrItinClass itin, string OpcodeStr, string Dt, 2718 ValueType ResTy, ValueType OpTy, Intrinsic IntOp> 2719 : N3V<op24, op23, op21_20, op11_8, 1, op4, 2720 (outs QPR:$Vd), (ins QPR:$src1, QPR:$Vn, QPR:$Vm), N3RegFrm, itin, 2721 OpcodeStr, Dt, "$Vd, $Vn, $Vm", "$src1 = $Vd", 2722 [(set QPR:$Vd, (ResTy (IntOp (OpTy QPR:$src1), 2723 (OpTy QPR:$Vn), (OpTy QPR:$Vm))))]>; 2724 2725// Long Multiply-Add/Sub operations. 2726class N3VLMulOp<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4, 2727 InstrItinClass itin, string OpcodeStr, string Dt, 2728 ValueType TyQ, ValueType TyD, SDNode MulOp, SDNode OpNode> 2729 : N3V<op24, op23, op21_20, op11_8, 0, op4, 2730 (outs QPR:$Vd), (ins QPR:$src1, DPR:$Vn, DPR:$Vm), N3RegFrm, itin, 2731 OpcodeStr, Dt, "$Vd, $Vn, $Vm", "$src1 = $Vd", 2732 [(set QPR:$Vd, (OpNode (TyQ QPR:$src1), 2733 (TyQ (MulOp (TyD DPR:$Vn), 2734 (TyD DPR:$Vm)))))]>; 2735class N3VLMulOpSL<bit op24, bits<2> op21_20, bits<4> op11_8, 2736 InstrItinClass itin, string OpcodeStr, string Dt, 2737 ValueType TyQ, ValueType TyD, SDNode MulOp, SDNode OpNode> 2738 : N3VLane32<op24, 1, op21_20, op11_8, 1, 0, (outs QPR:$Vd), 2739 (ins QPR:$src1, DPR:$Vn, DPR_VFP2:$Vm, VectorIndex32:$lane), 2740 NVMulSLFrm, itin, 2741 OpcodeStr, Dt, "$Vd, $Vn, $Vm$lane", "$src1 = $Vd", 2742 [(set QPR:$Vd, 2743 (OpNode (TyQ QPR:$src1), 2744 (TyQ (MulOp (TyD DPR:$Vn), 2745 (TyD (NEONvduplane (TyD DPR_VFP2:$Vm), 2746 imm:$lane))))))]>; 2747class N3VLMulOpSL16<bit op24, bits<2> op21_20, bits<4> op11_8, 2748 InstrItinClass itin, string OpcodeStr, string Dt, 2749 ValueType TyQ, ValueType TyD, SDNode MulOp, SDNode OpNode> 2750 : N3VLane16<op24, 1, op21_20, op11_8, 1, 0, (outs QPR:$Vd), 2751 (ins QPR:$src1, DPR:$Vn, DPR_8:$Vm, VectorIndex16:$lane), 2752 NVMulSLFrm, itin, 2753 OpcodeStr, Dt, "$Vd, $Vn, $Vm$lane", "$src1 = $Vd", 2754 [(set QPR:$Vd, 2755 (OpNode (TyQ QPR:$src1), 2756 (TyQ (MulOp (TyD DPR:$Vn), 2757 (TyD (NEONvduplane (TyD DPR_8:$Vm), 2758 imm:$lane))))))]>; 2759 2760// Long Intrinsic-Op vector operations with explicit extend (VABAL). 2761class N3VLIntExtOp<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4, 2762 InstrItinClass itin, string OpcodeStr, string Dt, 2763 ValueType TyQ, ValueType TyD, Intrinsic IntOp, SDNode ExtOp, 2764 SDNode OpNode> 2765 : N3V<op24, op23, op21_20, op11_8, 0, op4, 2766 (outs QPR:$Vd), (ins QPR:$src1, DPR:$Vn, DPR:$Vm), N3RegFrm, itin, 2767 OpcodeStr, Dt, "$Vd, $Vn, $Vm", "$src1 = $Vd", 2768 [(set QPR:$Vd, (OpNode (TyQ QPR:$src1), 2769 (TyQ (ExtOp (TyD (IntOp (TyD DPR:$Vn), 2770 (TyD DPR:$Vm)))))))]>; 2771 2772// Neon Long 3-argument intrinsic. The destination register is 2773// a quad-register and is also used as the first source operand register. 2774class N3VLInt3<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4, 2775 InstrItinClass itin, string OpcodeStr, string Dt, 2776 ValueType TyQ, ValueType TyD, Intrinsic IntOp> 2777 : N3V<op24, op23, op21_20, op11_8, 0, op4, 2778 (outs QPR:$Vd), (ins QPR:$src1, DPR:$Vn, DPR:$Vm), N3RegFrm, itin, 2779 OpcodeStr, Dt, "$Vd, $Vn, $Vm", "$src1 = $Vd", 2780 [(set QPR:$Vd, 2781 (TyQ (IntOp (TyQ QPR:$src1), (TyD DPR:$Vn), (TyD DPR:$Vm))))]>; 2782class N3VLInt3SL<bit op24, bits<2> op21_20, bits<4> op11_8, InstrItinClass itin, 2783 string OpcodeStr, string Dt, 2784 ValueType ResTy, ValueType OpTy, Intrinsic IntOp> 2785 : N3VLane32<op24, 1, op21_20, op11_8, 1, 0, 2786 (outs QPR:$Vd), 2787 (ins QPR:$src1, DPR:$Vn, DPR_VFP2:$Vm, VectorIndex32:$lane), 2788 NVMulSLFrm, itin, 2789 OpcodeStr, Dt, "$Vd, $Vn, $Vm$lane", "$src1 = $Vd", 2790 [(set (ResTy QPR:$Vd), 2791 (ResTy (IntOp (ResTy QPR:$src1), 2792 (OpTy DPR:$Vn), 2793 (OpTy (NEONvduplane (OpTy DPR_VFP2:$Vm), 2794 imm:$lane)))))]>; 2795class N3VLInt3SL16<bit op24, bits<2> op21_20, bits<4> op11_8, 2796 InstrItinClass itin, string OpcodeStr, string Dt, 2797 ValueType ResTy, ValueType OpTy, Intrinsic IntOp> 2798 : N3VLane16<op24, 1, op21_20, op11_8, 1, 0, 2799 (outs QPR:$Vd), 2800 (ins QPR:$src1, DPR:$Vn, DPR_8:$Vm, VectorIndex16:$lane), 2801 NVMulSLFrm, itin, 2802 OpcodeStr, Dt, "$Vd, $Vn, $Vm$lane", "$src1 = $Vd", 2803 [(set (ResTy QPR:$Vd), 2804 (ResTy (IntOp (ResTy QPR:$src1), 2805 (OpTy DPR:$Vn), 2806 (OpTy (NEONvduplane (OpTy DPR_8:$Vm), 2807 imm:$lane)))))]>; 2808 2809// Narrowing 3-register intrinsics. 2810class N3VNInt<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4, 2811 string OpcodeStr, string Dt, ValueType TyD, ValueType TyQ, 2812 Intrinsic IntOp, bit Commutable> 2813 : N3V<op24, op23, op21_20, op11_8, 0, op4, 2814 (outs DPR:$Vd), (ins QPR:$Vn, QPR:$Vm), N3RegFrm, IIC_VBINi4D, 2815 OpcodeStr, Dt, "$Vd, $Vn, $Vm", "", 2816 [(set DPR:$Vd, (TyD (IntOp (TyQ QPR:$Vn), (TyQ QPR:$Vm))))]> { 2817 let isCommutable = Commutable; 2818} 2819 2820// Long 3-register operations. 2821class N3VL<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4, 2822 InstrItinClass itin, string OpcodeStr, string Dt, 2823 ValueType TyQ, ValueType TyD, SDNode OpNode, bit Commutable> 2824 : N3V<op24, op23, op21_20, op11_8, 0, op4, 2825 (outs QPR:$Vd), (ins DPR:$Vn, DPR:$Vm), N3RegFrm, itin, 2826 OpcodeStr, Dt, "$Vd, $Vn, $Vm", "", 2827 [(set QPR:$Vd, (TyQ (OpNode (TyD DPR:$Vn), (TyD DPR:$Vm))))]> { 2828 let isCommutable = Commutable; 2829} 2830class N3VLSL<bit op24, bits<2> op21_20, bits<4> op11_8, 2831 InstrItinClass itin, string OpcodeStr, string Dt, 2832 ValueType TyQ, ValueType TyD, SDNode OpNode> 2833 : N3VLane32<op24, 1, op21_20, op11_8, 1, 0, 2834 (outs QPR:$Vd), (ins DPR:$Vn, DPR_VFP2:$Vm, VectorIndex32:$lane), 2835 NVMulSLFrm, itin, OpcodeStr, Dt, "$Vd, $Vn, $Vm$lane", "", 2836 [(set QPR:$Vd, 2837 (TyQ (OpNode (TyD DPR:$Vn), 2838 (TyD (NEONvduplane (TyD DPR_VFP2:$Vm),imm:$lane)))))]>; 2839class N3VLSL16<bit op24, bits<2> op21_20, bits<4> op11_8, 2840 InstrItinClass itin, string OpcodeStr, string Dt, 2841 ValueType TyQ, ValueType TyD, SDNode OpNode> 2842 : N3VLane16<op24, 1, op21_20, op11_8, 1, 0, 2843 (outs QPR:$Vd), (ins DPR:$Vn, DPR_8:$Vm, VectorIndex16:$lane), 2844 NVMulSLFrm, itin, OpcodeStr, Dt, "$Vd, $Vn, $Vm$lane", "", 2845 [(set QPR:$Vd, 2846 (TyQ (OpNode (TyD DPR:$Vn), 2847 (TyD (NEONvduplane (TyD DPR_8:$Vm), imm:$lane)))))]>; 2848 2849// Long 3-register operations with explicitly extended operands. 2850class N3VLExt<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4, 2851 InstrItinClass itin, string OpcodeStr, string Dt, 2852 ValueType TyQ, ValueType TyD, SDNode OpNode, SDNode ExtOp, 2853 bit Commutable> 2854 : N3V<op24, op23, op21_20, op11_8, 0, op4, 2855 (outs QPR:$Vd), (ins DPR:$Vn, DPR:$Vm), N3RegFrm, itin, 2856 OpcodeStr, Dt, "$Vd, $Vn, $Vm", "", 2857 [(set QPR:$Vd, (OpNode (TyQ (ExtOp (TyD DPR:$Vn))), 2858 (TyQ (ExtOp (TyD DPR:$Vm)))))]> { 2859 let isCommutable = Commutable; 2860} 2861 2862// Long 3-register intrinsics with explicit extend (VABDL). 2863class N3VLIntExt<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4, 2864 InstrItinClass itin, string OpcodeStr, string Dt, 2865 ValueType TyQ, ValueType TyD, Intrinsic IntOp, SDNode ExtOp, 2866 bit Commutable> 2867 : N3V<op24, op23, op21_20, op11_8, 0, op4, 2868 (outs QPR:$Vd), (ins DPR:$Vn, DPR:$Vm), N3RegFrm, itin, 2869 OpcodeStr, Dt, "$Vd, $Vn, $Vm", "", 2870 [(set QPR:$Vd, (TyQ (ExtOp (TyD (IntOp (TyD DPR:$Vn), 2871 (TyD DPR:$Vm))))))]> { 2872 let isCommutable = Commutable; 2873} 2874 2875// Long 3-register intrinsics. 2876class N3VLInt<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4, 2877 InstrItinClass itin, string OpcodeStr, string Dt, 2878 ValueType TyQ, ValueType TyD, Intrinsic IntOp, bit Commutable> 2879 : N3V<op24, op23, op21_20, op11_8, 0, op4, 2880 (outs QPR:$Vd), (ins DPR:$Vn, DPR:$Vm), N3RegFrm, itin, 2881 OpcodeStr, Dt, "$Vd, $Vn, $Vm", "", 2882 [(set QPR:$Vd, (TyQ (IntOp (TyD DPR:$Vn), (TyD DPR:$Vm))))]> { 2883 let isCommutable = Commutable; 2884} 2885class N3VLIntSL<bit op24, bits<2> op21_20, bits<4> op11_8, InstrItinClass itin, 2886 string OpcodeStr, string Dt, 2887 ValueType ResTy, ValueType OpTy, Intrinsic IntOp> 2888 : N3VLane32<op24, 1, op21_20, op11_8, 1, 0, 2889 (outs QPR:$Vd), (ins DPR:$Vn, DPR_VFP2:$Vm, VectorIndex32:$lane), 2890 NVMulSLFrm, itin, OpcodeStr, Dt, "$Vd, $Vn, $Vm$lane", "", 2891 [(set (ResTy QPR:$Vd), 2892 (ResTy (IntOp (OpTy DPR:$Vn), 2893 (OpTy (NEONvduplane (OpTy DPR_VFP2:$Vm), 2894 imm:$lane)))))]>; 2895class N3VLIntSL16<bit op24, bits<2> op21_20, bits<4> op11_8, 2896 InstrItinClass itin, string OpcodeStr, string Dt, 2897 ValueType ResTy, ValueType OpTy, Intrinsic IntOp> 2898 : N3VLane16<op24, 1, op21_20, op11_8, 1, 0, 2899 (outs QPR:$Vd), (ins DPR:$Vn, DPR_8:$Vm, VectorIndex16:$lane), 2900 NVMulSLFrm, itin, OpcodeStr, Dt, "$Vd, $Vn, $Vm$lane", "", 2901 [(set (ResTy QPR:$Vd), 2902 (ResTy (IntOp (OpTy DPR:$Vn), 2903 (OpTy (NEONvduplane (OpTy DPR_8:$Vm), 2904 imm:$lane)))))]>; 2905 2906// Wide 3-register operations. 2907class N3VW<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4, 2908 string OpcodeStr, string Dt, ValueType TyQ, ValueType TyD, 2909 SDNode OpNode, SDNode ExtOp, bit Commutable> 2910 : N3V<op24, op23, op21_20, op11_8, 0, op4, 2911 (outs QPR:$Vd), (ins QPR:$Vn, DPR:$Vm), N3RegFrm, IIC_VSUBiD, 2912 OpcodeStr, Dt, "$Vd, $Vn, $Vm", "", 2913 [(set QPR:$Vd, (OpNode (TyQ QPR:$Vn), 2914 (TyQ (ExtOp (TyD DPR:$Vm)))))]> { 2915 let isCommutable = Commutable; 2916} 2917 2918// Pairwise long 2-register intrinsics, both double- and quad-register. 2919class N2VDPLInt<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18, 2920 bits<2> op17_16, bits<5> op11_7, bit op4, 2921 string OpcodeStr, string Dt, 2922 ValueType ResTy, ValueType OpTy, Intrinsic IntOp> 2923 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, 0, op4, (outs DPR:$Vd), 2924 (ins DPR:$Vm), IIC_VSHLiD, OpcodeStr, Dt, "$Vd, $Vm", "", 2925 [(set DPR:$Vd, (ResTy (IntOp (OpTy DPR:$Vm))))]>; 2926class N2VQPLInt<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18, 2927 bits<2> op17_16, bits<5> op11_7, bit op4, 2928 string OpcodeStr, string Dt, 2929 ValueType ResTy, ValueType OpTy, Intrinsic IntOp> 2930 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, 1, op4, (outs QPR:$Vd), 2931 (ins QPR:$Vm), IIC_VSHLiD, OpcodeStr, Dt, "$Vd, $Vm", "", 2932 [(set QPR:$Vd, (ResTy (IntOp (OpTy QPR:$Vm))))]>; 2933 2934// Pairwise long 2-register accumulate intrinsics, 2935// both double- and quad-register. 2936// The destination register is also used as the first source operand register. 2937class N2VDPLInt2<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18, 2938 bits<2> op17_16, bits<5> op11_7, bit op4, 2939 string OpcodeStr, string Dt, 2940 ValueType ResTy, ValueType OpTy, Intrinsic IntOp> 2941 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, 0, op4, 2942 (outs DPR:$Vd), (ins DPR:$src1, DPR:$Vm), IIC_VPALiD, 2943 OpcodeStr, Dt, "$Vd, $Vm", "$src1 = $Vd", 2944 [(set DPR:$Vd, (ResTy (IntOp (ResTy DPR:$src1), (OpTy DPR:$Vm))))]>; 2945class N2VQPLInt2<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18, 2946 bits<2> op17_16, bits<5> op11_7, bit op4, 2947 string OpcodeStr, string Dt, 2948 ValueType ResTy, ValueType OpTy, Intrinsic IntOp> 2949 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, 1, op4, 2950 (outs QPR:$Vd), (ins QPR:$src1, QPR:$Vm), IIC_VPALiQ, 2951 OpcodeStr, Dt, "$Vd, $Vm", "$src1 = $Vd", 2952 [(set QPR:$Vd, (ResTy (IntOp (ResTy QPR:$src1), (OpTy QPR:$Vm))))]>; 2953 2954// Shift by immediate, 2955// both double- and quad-register. 2956class N2VDSh<bit op24, bit op23, bits<4> op11_8, bit op7, bit op4, 2957 Format f, InstrItinClass itin, Operand ImmTy, 2958 string OpcodeStr, string Dt, ValueType Ty, SDNode OpNode> 2959 : N2VImm<op24, op23, op11_8, op7, 0, op4, 2960 (outs DPR:$Vd), (ins DPR:$Vm, ImmTy:$SIMM), f, itin, 2961 OpcodeStr, Dt, "$Vd, $Vm, $SIMM", "", 2962 [(set DPR:$Vd, (Ty (OpNode (Ty DPR:$Vm), (i32 imm:$SIMM))))]>; 2963class N2VQSh<bit op24, bit op23, bits<4> op11_8, bit op7, bit op4, 2964 Format f, InstrItinClass itin, Operand ImmTy, 2965 string OpcodeStr, string Dt, ValueType Ty, SDNode OpNode> 2966 : N2VImm<op24, op23, op11_8, op7, 1, op4, 2967 (outs QPR:$Vd), (ins QPR:$Vm, ImmTy:$SIMM), f, itin, 2968 OpcodeStr, Dt, "$Vd, $Vm, $SIMM", "", 2969 [(set QPR:$Vd, (Ty (OpNode (Ty QPR:$Vm), (i32 imm:$SIMM))))]>; 2970 2971// Long shift by immediate. 2972class N2VLSh<bit op24, bit op23, bits<4> op11_8, bit op7, bit op6, bit op4, 2973 string OpcodeStr, string Dt, 2974 ValueType ResTy, ValueType OpTy, Operand ImmTy, SDNode OpNode> 2975 : N2VImm<op24, op23, op11_8, op7, op6, op4, 2976 (outs QPR:$Vd), (ins DPR:$Vm, ImmTy:$SIMM), N2RegVShLFrm, 2977 IIC_VSHLiD, OpcodeStr, Dt, "$Vd, $Vm, $SIMM", "", 2978 [(set QPR:$Vd, (ResTy (OpNode (OpTy DPR:$Vm), 2979 (i32 imm:$SIMM))))]>; 2980 2981// Narrow shift by immediate. 2982class N2VNSh<bit op24, bit op23, bits<4> op11_8, bit op7, bit op6, bit op4, 2983 InstrItinClass itin, string OpcodeStr, string Dt, 2984 ValueType ResTy, ValueType OpTy, Operand ImmTy, SDNode OpNode> 2985 : N2VImm<op24, op23, op11_8, op7, op6, op4, 2986 (outs DPR:$Vd), (ins QPR:$Vm, ImmTy:$SIMM), N2RegVShRFrm, itin, 2987 OpcodeStr, Dt, "$Vd, $Vm, $SIMM", "", 2988 [(set DPR:$Vd, (ResTy (OpNode (OpTy QPR:$Vm), 2989 (i32 imm:$SIMM))))]>; 2990 2991// Shift right by immediate and accumulate, 2992// both double- and quad-register. 2993class N2VDShAdd<bit op24, bit op23, bits<4> op11_8, bit op7, bit op4, 2994 Operand ImmTy, string OpcodeStr, string Dt, 2995 ValueType Ty, SDNode ShOp> 2996 : N2VImm<op24, op23, op11_8, op7, 0, op4, (outs DPR:$Vd), 2997 (ins DPR:$src1, DPR:$Vm, ImmTy:$SIMM), N2RegVShRFrm, IIC_VPALiD, 2998 OpcodeStr, Dt, "$Vd, $Vm, $SIMM", "$src1 = $Vd", 2999 [(set DPR:$Vd, (Ty (add DPR:$src1, 3000 (Ty (ShOp DPR:$Vm, (i32 imm:$SIMM))))))]>; 3001class N2VQShAdd<bit op24, bit op23, bits<4> op11_8, bit op7, bit op4, 3002 Operand ImmTy, string OpcodeStr, string Dt, 3003 ValueType Ty, SDNode ShOp> 3004 : N2VImm<op24, op23, op11_8, op7, 1, op4, (outs QPR:$Vd), 3005 (ins QPR:$src1, QPR:$Vm, ImmTy:$SIMM), N2RegVShRFrm, IIC_VPALiD, 3006 OpcodeStr, Dt, "$Vd, $Vm, $SIMM", "$src1 = $Vd", 3007 [(set QPR:$Vd, (Ty (add QPR:$src1, 3008 (Ty (ShOp QPR:$Vm, (i32 imm:$SIMM))))))]>; 3009 3010// Shift by immediate and insert, 3011// both double- and quad-register. 3012class N2VDShIns<bit op24, bit op23, bits<4> op11_8, bit op7, bit op4, 3013 Operand ImmTy, Format f, string OpcodeStr, string Dt, 3014 ValueType Ty,SDNode ShOp> 3015 : N2VImm<op24, op23, op11_8, op7, 0, op4, (outs DPR:$Vd), 3016 (ins DPR:$src1, DPR:$Vm, ImmTy:$SIMM), f, IIC_VSHLiD, 3017 OpcodeStr, Dt, "$Vd, $Vm, $SIMM", "$src1 = $Vd", 3018 [(set DPR:$Vd, (Ty (ShOp DPR:$src1, DPR:$Vm, (i32 imm:$SIMM))))]>; 3019class N2VQShIns<bit op24, bit op23, bits<4> op11_8, bit op7, bit op4, 3020 Operand ImmTy, Format f, string OpcodeStr, string Dt, 3021 ValueType Ty,SDNode ShOp> 3022 : N2VImm<op24, op23, op11_8, op7, 1, op4, (outs QPR:$Vd), 3023 (ins QPR:$src1, QPR:$Vm, ImmTy:$SIMM), f, IIC_VSHLiQ, 3024 OpcodeStr, Dt, "$Vd, $Vm, $SIMM", "$src1 = $Vd", 3025 [(set QPR:$Vd, (Ty (ShOp QPR:$src1, QPR:$Vm, (i32 imm:$SIMM))))]>; 3026 3027// Convert, with fractional bits immediate, 3028// both double- and quad-register. 3029class N2VCvtD<bit op24, bit op23, bits<4> op11_8, bit op7, bit op4, 3030 string OpcodeStr, string Dt, ValueType ResTy, ValueType OpTy, 3031 Intrinsic IntOp> 3032 : N2VImm<op24, op23, op11_8, op7, 0, op4, 3033 (outs DPR:$Vd), (ins DPR:$Vm, neon_vcvt_imm32:$SIMM), NVCVTFrm, 3034 IIC_VUNAD, OpcodeStr, Dt, "$Vd, $Vm, $SIMM", "", 3035 [(set DPR:$Vd, (ResTy (IntOp (OpTy DPR:$Vm), (i32 imm:$SIMM))))]>; 3036class N2VCvtQ<bit op24, bit op23, bits<4> op11_8, bit op7, bit op4, 3037 string OpcodeStr, string Dt, ValueType ResTy, ValueType OpTy, 3038 Intrinsic IntOp> 3039 : N2VImm<op24, op23, op11_8, op7, 1, op4, 3040 (outs QPR:$Vd), (ins QPR:$Vm, neon_vcvt_imm32:$SIMM), NVCVTFrm, 3041 IIC_VUNAQ, OpcodeStr, Dt, "$Vd, $Vm, $SIMM", "", 3042 [(set QPR:$Vd, (ResTy (IntOp (OpTy QPR:$Vm), (i32 imm:$SIMM))))]>; 3043 3044//===----------------------------------------------------------------------===// 3045// Multiclasses 3046//===----------------------------------------------------------------------===// 3047 3048// Abbreviations used in multiclass suffixes: 3049// Q = quarter int (8 bit) elements 3050// H = half int (16 bit) elements 3051// S = single int (32 bit) elements 3052// D = double int (64 bit) elements 3053 3054// Neon 2-register vector operations and intrinsics. 3055 3056// Neon 2-register comparisons. 3057// source operand element sizes of 8, 16 and 32 bits: 3058multiclass N2V_QHS_cmp<bits<2> op24_23, bits<2> op21_20, bits<2> op17_16, 3059 bits<5> op11_7, bit op4, string opc, string Dt, 3060 string asm, SDNode OpNode> { 3061 // 64-bit vector types. 3062 def v8i8 : N2V<op24_23, op21_20, 0b00, op17_16, op11_7, 0, op4, 3063 (outs DPR:$Vd), (ins DPR:$Vm), NoItinerary, 3064 opc, !strconcat(Dt, "8"), asm, "", 3065 [(set DPR:$Vd, (v8i8 (OpNode (v8i8 DPR:$Vm))))]>; 3066 def v4i16 : N2V<op24_23, op21_20, 0b01, op17_16, op11_7, 0, op4, 3067 (outs DPR:$Vd), (ins DPR:$Vm), NoItinerary, 3068 opc, !strconcat(Dt, "16"), asm, "", 3069 [(set DPR:$Vd, (v4i16 (OpNode (v4i16 DPR:$Vm))))]>; 3070 def v2i32 : N2V<op24_23, op21_20, 0b10, op17_16, op11_7, 0, op4, 3071 (outs DPR:$Vd), (ins DPR:$Vm), NoItinerary, 3072 opc, !strconcat(Dt, "32"), asm, "", 3073 [(set DPR:$Vd, (v2i32 (OpNode (v2i32 DPR:$Vm))))]>; 3074 def v2f32 : N2V<op24_23, op21_20, 0b10, op17_16, op11_7, 0, op4, 3075 (outs DPR:$Vd), (ins DPR:$Vm), NoItinerary, 3076 opc, "f32", asm, "", 3077 [(set DPR:$Vd, (v2i32 (OpNode (v2f32 DPR:$Vm))))]> { 3078 let Inst{10} = 1; // overwrite F = 1 3079 } 3080 3081 // 128-bit vector types. 3082 def v16i8 : N2V<op24_23, op21_20, 0b00, op17_16, op11_7, 1, op4, 3083 (outs QPR:$Vd), (ins QPR:$Vm), NoItinerary, 3084 opc, !strconcat(Dt, "8"), asm, "", 3085 [(set QPR:$Vd, (v16i8 (OpNode (v16i8 QPR:$Vm))))]>; 3086 def v8i16 : N2V<op24_23, op21_20, 0b01, op17_16, op11_7, 1, op4, 3087 (outs QPR:$Vd), (ins QPR:$Vm), NoItinerary, 3088 opc, !strconcat(Dt, "16"), asm, "", 3089 [(set QPR:$Vd, (v8i16 (OpNode (v8i16 QPR:$Vm))))]>; 3090 def v4i32 : N2V<op24_23, op21_20, 0b10, op17_16, op11_7, 1, op4, 3091 (outs QPR:$Vd), (ins QPR:$Vm), NoItinerary, 3092 opc, !strconcat(Dt, "32"), asm, "", 3093 [(set QPR:$Vd, (v4i32 (OpNode (v4i32 QPR:$Vm))))]>; 3094 def v4f32 : N2V<op24_23, op21_20, 0b10, op17_16, op11_7, 1, op4, 3095 (outs QPR:$Vd), (ins QPR:$Vm), NoItinerary, 3096 opc, "f32", asm, "", 3097 [(set QPR:$Vd, (v4i32 (OpNode (v4f32 QPR:$Vm))))]> { 3098 let Inst{10} = 1; // overwrite F = 1 3099 } 3100} 3101 3102 3103// Neon 2-register vector intrinsics, 3104// element sizes of 8, 16 and 32 bits: 3105multiclass N2VInt_QHS<bits<2> op24_23, bits<2> op21_20, bits<2> op17_16, 3106 bits<5> op11_7, bit op4, 3107 InstrItinClass itinD, InstrItinClass itinQ, 3108 string OpcodeStr, string Dt, Intrinsic IntOp> { 3109 // 64-bit vector types. 3110 def v8i8 : N2VDInt<op24_23, op21_20, 0b00, op17_16, op11_7, op4, 3111 itinD, OpcodeStr, !strconcat(Dt, "8"), v8i8, v8i8, IntOp>; 3112 def v4i16 : N2VDInt<op24_23, op21_20, 0b01, op17_16, op11_7, op4, 3113 itinD, OpcodeStr, !strconcat(Dt, "16"),v4i16,v4i16,IntOp>; 3114 def v2i32 : N2VDInt<op24_23, op21_20, 0b10, op17_16, op11_7, op4, 3115 itinD, OpcodeStr, !strconcat(Dt, "32"),v2i32,v2i32,IntOp>; 3116 3117 // 128-bit vector types. 3118 def v16i8 : N2VQInt<op24_23, op21_20, 0b00, op17_16, op11_7, op4, 3119 itinQ, OpcodeStr, !strconcat(Dt, "8"), v16i8,v16i8,IntOp>; 3120 def v8i16 : N2VQInt<op24_23, op21_20, 0b01, op17_16, op11_7, op4, 3121 itinQ, OpcodeStr, !strconcat(Dt, "16"),v8i16,v8i16,IntOp>; 3122 def v4i32 : N2VQInt<op24_23, op21_20, 0b10, op17_16, op11_7, op4, 3123 itinQ, OpcodeStr, !strconcat(Dt, "32"),v4i32,v4i32,IntOp>; 3124} 3125 3126 3127// Neon Narrowing 2-register vector operations, 3128// source operand element sizes of 16, 32 and 64 bits: 3129multiclass N2VN_HSD<bits<2> op24_23, bits<2> op21_20, bits<2> op17_16, 3130 bits<5> op11_7, bit op6, bit op4, 3131 InstrItinClass itin, string OpcodeStr, string Dt, 3132 SDNode OpNode> { 3133 def v8i8 : N2VN<op24_23, op21_20, 0b00, op17_16, op11_7, op6, op4, 3134 itin, OpcodeStr, !strconcat(Dt, "16"), 3135 v8i8, v8i16, OpNode>; 3136 def v4i16 : N2VN<op24_23, op21_20, 0b01, op17_16, op11_7, op6, op4, 3137 itin, OpcodeStr, !strconcat(Dt, "32"), 3138 v4i16, v4i32, OpNode>; 3139 def v2i32 : N2VN<op24_23, op21_20, 0b10, op17_16, op11_7, op6, op4, 3140 itin, OpcodeStr, !strconcat(Dt, "64"), 3141 v2i32, v2i64, OpNode>; 3142} 3143 3144// Neon Narrowing 2-register vector intrinsics, 3145// source operand element sizes of 16, 32 and 64 bits: 3146multiclass N2VNInt_HSD<bits<2> op24_23, bits<2> op21_20, bits<2> op17_16, 3147 bits<5> op11_7, bit op6, bit op4, 3148 InstrItinClass itin, string OpcodeStr, string Dt, 3149 Intrinsic IntOp> { 3150 def v8i8 : N2VNInt<op24_23, op21_20, 0b00, op17_16, op11_7, op6, op4, 3151 itin, OpcodeStr, !strconcat(Dt, "16"), 3152 v8i8, v8i16, IntOp>; 3153 def v4i16 : N2VNInt<op24_23, op21_20, 0b01, op17_16, op11_7, op6, op4, 3154 itin, OpcodeStr, !strconcat(Dt, "32"), 3155 v4i16, v4i32, IntOp>; 3156 def v2i32 : N2VNInt<op24_23, op21_20, 0b10, op17_16, op11_7, op6, op4, 3157 itin, OpcodeStr, !strconcat(Dt, "64"), 3158 v2i32, v2i64, IntOp>; 3159} 3160 3161 3162// Neon Lengthening 2-register vector intrinsic (currently specific to VMOVL). 3163// source operand element sizes of 16, 32 and 64 bits: 3164multiclass N2VL_QHS<bits<2> op24_23, bits<5> op11_7, bit op6, bit op4, 3165 string OpcodeStr, string Dt, SDNode OpNode> { 3166 def v8i16 : N2VL<op24_23, 0b00, 0b10, 0b00, op11_7, op6, op4, IIC_VQUNAiD, 3167 OpcodeStr, !strconcat(Dt, "8"), v8i16, v8i8, OpNode>; 3168 def v4i32 : N2VL<op24_23, 0b01, 0b00, 0b00, op11_7, op6, op4, IIC_VQUNAiD, 3169 OpcodeStr, !strconcat(Dt, "16"), v4i32, v4i16, OpNode>; 3170 def v2i64 : N2VL<op24_23, 0b10, 0b00, 0b00, op11_7, op6, op4, IIC_VQUNAiD, 3171 OpcodeStr, !strconcat(Dt, "32"), v2i64, v2i32, OpNode>; 3172} 3173 3174 3175// Neon 3-register vector operations. 3176 3177// First with only element sizes of 8, 16 and 32 bits: 3178multiclass N3V_QHS<bit op24, bit op23, bits<4> op11_8, bit op4, 3179 InstrItinClass itinD16, InstrItinClass itinD32, 3180 InstrItinClass itinQ16, InstrItinClass itinQ32, 3181 string OpcodeStr, string Dt, 3182 SDNode OpNode, bit Commutable = 0> { 3183 // 64-bit vector types. 3184 def v8i8 : N3VD<op24, op23, 0b00, op11_8, op4, itinD16, 3185 OpcodeStr, !strconcat(Dt, "8"), 3186 v8i8, v8i8, OpNode, Commutable>; 3187 def v4i16 : N3VD<op24, op23, 0b01, op11_8, op4, itinD16, 3188 OpcodeStr, !strconcat(Dt, "16"), 3189 v4i16, v4i16, OpNode, Commutable>; 3190 def v2i32 : N3VD<op24, op23, 0b10, op11_8, op4, itinD32, 3191 OpcodeStr, !strconcat(Dt, "32"), 3192 v2i32, v2i32, OpNode, Commutable>; 3193 3194 // 128-bit vector types. 3195 def v16i8 : N3VQ<op24, op23, 0b00, op11_8, op4, itinQ16, 3196 OpcodeStr, !strconcat(Dt, "8"), 3197 v16i8, v16i8, OpNode, Commutable>; 3198 def v8i16 : N3VQ<op24, op23, 0b01, op11_8, op4, itinQ16, 3199 OpcodeStr, !strconcat(Dt, "16"), 3200 v8i16, v8i16, OpNode, Commutable>; 3201 def v4i32 : N3VQ<op24, op23, 0b10, op11_8, op4, itinQ32, 3202 OpcodeStr, !strconcat(Dt, "32"), 3203 v4i32, v4i32, OpNode, Commutable>; 3204} 3205 3206multiclass N3VSL_HS<bits<4> op11_8, string OpcodeStr, SDNode ShOp> { 3207 def v4i16 : N3VDSL16<0b01, op11_8, OpcodeStr, "i16", v4i16, ShOp>; 3208 def v2i32 : N3VDSL<0b10, op11_8, IIC_VMULi32D, OpcodeStr, "i32", v2i32, ShOp>; 3209 def v8i16 : N3VQSL16<0b01, op11_8, OpcodeStr, "i16", v8i16, v4i16, ShOp>; 3210 def v4i32 : N3VQSL<0b10, op11_8, IIC_VMULi32Q, OpcodeStr, "i32", 3211 v4i32, v2i32, ShOp>; 3212} 3213 3214// ....then also with element size 64 bits: 3215multiclass N3V_QHSD<bit op24, bit op23, bits<4> op11_8, bit op4, 3216 InstrItinClass itinD, InstrItinClass itinQ, 3217 string OpcodeStr, string Dt, 3218 SDNode OpNode, bit Commutable = 0> 3219 : N3V_QHS<op24, op23, op11_8, op4, itinD, itinD, itinQ, itinQ, 3220 OpcodeStr, Dt, OpNode, Commutable> { 3221 def v1i64 : N3VD<op24, op23, 0b11, op11_8, op4, itinD, 3222 OpcodeStr, !strconcat(Dt, "64"), 3223 v1i64, v1i64, OpNode, Commutable>; 3224 def v2i64 : N3VQ<op24, op23, 0b11, op11_8, op4, itinQ, 3225 OpcodeStr, !strconcat(Dt, "64"), 3226 v2i64, v2i64, OpNode, Commutable>; 3227} 3228 3229 3230// Neon 3-register vector intrinsics. 3231 3232// First with only element sizes of 16 and 32 bits: 3233multiclass N3VInt_HS<bit op24, bit op23, bits<4> op11_8, bit op4, Format f, 3234 InstrItinClass itinD16, InstrItinClass itinD32, 3235 InstrItinClass itinQ16, InstrItinClass itinQ32, 3236 string OpcodeStr, string Dt, 3237 Intrinsic IntOp, bit Commutable = 0> { 3238 // 64-bit vector types. 3239 def v4i16 : N3VDInt<op24, op23, 0b01, op11_8, op4, f, itinD16, 3240 OpcodeStr, !strconcat(Dt, "16"), 3241 v4i16, v4i16, IntOp, Commutable>; 3242 def v2i32 : N3VDInt<op24, op23, 0b10, op11_8, op4, f, itinD32, 3243 OpcodeStr, !strconcat(Dt, "32"), 3244 v2i32, v2i32, IntOp, Commutable>; 3245 3246 // 128-bit vector types. 3247 def v8i16 : N3VQInt<op24, op23, 0b01, op11_8, op4, f, itinQ16, 3248 OpcodeStr, !strconcat(Dt, "16"), 3249 v8i16, v8i16, IntOp, Commutable>; 3250 def v4i32 : N3VQInt<op24, op23, 0b10, op11_8, op4, f, itinQ32, 3251 OpcodeStr, !strconcat(Dt, "32"), 3252 v4i32, v4i32, IntOp, Commutable>; 3253} 3254multiclass N3VInt_HSSh<bit op24, bit op23, bits<4> op11_8, bit op4, Format f, 3255 InstrItinClass itinD16, InstrItinClass itinD32, 3256 InstrItinClass itinQ16, InstrItinClass itinQ32, 3257 string OpcodeStr, string Dt, 3258 Intrinsic IntOp> { 3259 // 64-bit vector types. 3260 def v4i16 : N3VDIntSh<op24, op23, 0b01, op11_8, op4, f, itinD16, 3261 OpcodeStr, !strconcat(Dt, "16"), 3262 v4i16, v4i16, IntOp>; 3263 def v2i32 : N3VDIntSh<op24, op23, 0b10, op11_8, op4, f, itinD32, 3264 OpcodeStr, !strconcat(Dt, "32"), 3265 v2i32, v2i32, IntOp>; 3266 3267 // 128-bit vector types. 3268 def v8i16 : N3VQIntSh<op24, op23, 0b01, op11_8, op4, f, itinQ16, 3269 OpcodeStr, !strconcat(Dt, "16"), 3270 v8i16, v8i16, IntOp>; 3271 def v4i32 : N3VQIntSh<op24, op23, 0b10, op11_8, op4, f, itinQ32, 3272 OpcodeStr, !strconcat(Dt, "32"), 3273 v4i32, v4i32, IntOp>; 3274} 3275 3276multiclass N3VIntSL_HS<bits<4> op11_8, 3277 InstrItinClass itinD16, InstrItinClass itinD32, 3278 InstrItinClass itinQ16, InstrItinClass itinQ32, 3279 string OpcodeStr, string Dt, Intrinsic IntOp> { 3280 def v4i16 : N3VDIntSL16<0b01, op11_8, itinD16, 3281 OpcodeStr, !strconcat(Dt, "16"), v4i16, IntOp>; 3282 def v2i32 : N3VDIntSL<0b10, op11_8, itinD32, 3283 OpcodeStr, !strconcat(Dt, "32"), v2i32, IntOp>; 3284 def v8i16 : N3VQIntSL16<0b01, op11_8, itinQ16, 3285 OpcodeStr, !strconcat(Dt, "16"), v8i16, v4i16, IntOp>; 3286 def v4i32 : N3VQIntSL<0b10, op11_8, itinQ32, 3287 OpcodeStr, !strconcat(Dt, "32"), v4i32, v2i32, IntOp>; 3288} 3289 3290// ....then also with element size of 8 bits: 3291multiclass N3VInt_QHS<bit op24, bit op23, bits<4> op11_8, bit op4, Format f, 3292 InstrItinClass itinD16, InstrItinClass itinD32, 3293 InstrItinClass itinQ16, InstrItinClass itinQ32, 3294 string OpcodeStr, string Dt, 3295 Intrinsic IntOp, bit Commutable = 0> 3296 : N3VInt_HS<op24, op23, op11_8, op4, f, itinD16, itinD32, itinQ16, itinQ32, 3297 OpcodeStr, Dt, IntOp, Commutable> { 3298 def v8i8 : N3VDInt<op24, op23, 0b00, op11_8, op4, f, itinD16, 3299 OpcodeStr, !strconcat(Dt, "8"), 3300 v8i8, v8i8, IntOp, Commutable>; 3301 def v16i8 : N3VQInt<op24, op23, 0b00, op11_8, op4, f, itinQ16, 3302 OpcodeStr, !strconcat(Dt, "8"), 3303 v16i8, v16i8, IntOp, Commutable>; 3304} 3305multiclass N3VInt_QHSSh<bit op24, bit op23, bits<4> op11_8, bit op4, Format f, 3306 InstrItinClass itinD16, InstrItinClass itinD32, 3307 InstrItinClass itinQ16, InstrItinClass itinQ32, 3308 string OpcodeStr, string Dt, 3309 Intrinsic IntOp> 3310 : N3VInt_HSSh<op24, op23, op11_8, op4, f, itinD16, itinD32, itinQ16, itinQ32, 3311 OpcodeStr, Dt, IntOp> { 3312 def v8i8 : N3VDIntSh<op24, op23, 0b00, op11_8, op4, f, itinD16, 3313 OpcodeStr, !strconcat(Dt, "8"), 3314 v8i8, v8i8, IntOp>; 3315 def v16i8 : N3VQIntSh<op24, op23, 0b00, op11_8, op4, f, itinQ16, 3316 OpcodeStr, !strconcat(Dt, "8"), 3317 v16i8, v16i8, IntOp>; 3318} 3319 3320 3321// ....then also with element size of 64 bits: 3322multiclass N3VInt_QHSD<bit op24, bit op23, bits<4> op11_8, bit op4, Format f, 3323 InstrItinClass itinD16, InstrItinClass itinD32, 3324 InstrItinClass itinQ16, InstrItinClass itinQ32, 3325 string OpcodeStr, string Dt, 3326 Intrinsic IntOp, bit Commutable = 0> 3327 : N3VInt_QHS<op24, op23, op11_8, op4, f, itinD16, itinD32, itinQ16, itinQ32, 3328 OpcodeStr, Dt, IntOp, Commutable> { 3329 def v1i64 : N3VDInt<op24, op23, 0b11, op11_8, op4, f, itinD32, 3330 OpcodeStr, !strconcat(Dt, "64"), 3331 v1i64, v1i64, IntOp, Commutable>; 3332 def v2i64 : N3VQInt<op24, op23, 0b11, op11_8, op4, f, itinQ32, 3333 OpcodeStr, !strconcat(Dt, "64"), 3334 v2i64, v2i64, IntOp, Commutable>; 3335} 3336multiclass N3VInt_QHSDSh<bit op24, bit op23, bits<4> op11_8, bit op4, Format f, 3337 InstrItinClass itinD16, InstrItinClass itinD32, 3338 InstrItinClass itinQ16, InstrItinClass itinQ32, 3339 string OpcodeStr, string Dt, 3340 Intrinsic IntOp> 3341 : N3VInt_QHSSh<op24, op23, op11_8, op4, f, itinD16, itinD32, itinQ16, itinQ32, 3342 OpcodeStr, Dt, IntOp> { 3343 def v1i64 : N3VDIntSh<op24, op23, 0b11, op11_8, op4, f, itinD32, 3344 OpcodeStr, !strconcat(Dt, "64"), 3345 v1i64, v1i64, IntOp>; 3346 def v2i64 : N3VQIntSh<op24, op23, 0b11, op11_8, op4, f, itinQ32, 3347 OpcodeStr, !strconcat(Dt, "64"), 3348 v2i64, v2i64, IntOp>; 3349} 3350 3351// Neon Narrowing 3-register vector intrinsics, 3352// source operand element sizes of 16, 32 and 64 bits: 3353multiclass N3VNInt_HSD<bit op24, bit op23, bits<4> op11_8, bit op4, 3354 string OpcodeStr, string Dt, 3355 Intrinsic IntOp, bit Commutable = 0> { 3356 def v8i8 : N3VNInt<op24, op23, 0b00, op11_8, op4, 3357 OpcodeStr, !strconcat(Dt, "16"), 3358 v8i8, v8i16, IntOp, Commutable>; 3359 def v4i16 : N3VNInt<op24, op23, 0b01, op11_8, op4, 3360 OpcodeStr, !strconcat(Dt, "32"), 3361 v4i16, v4i32, IntOp, Commutable>; 3362 def v2i32 : N3VNInt<op24, op23, 0b10, op11_8, op4, 3363 OpcodeStr, !strconcat(Dt, "64"), 3364 v2i32, v2i64, IntOp, Commutable>; 3365} 3366 3367 3368// Neon Long 3-register vector operations. 3369 3370multiclass N3VL_QHS<bit op24, bit op23, bits<4> op11_8, bit op4, 3371 InstrItinClass itin16, InstrItinClass itin32, 3372 string OpcodeStr, string Dt, 3373 SDNode OpNode, bit Commutable = 0> { 3374 def v8i16 : N3VL<op24, op23, 0b00, op11_8, op4, itin16, 3375 OpcodeStr, !strconcat(Dt, "8"), 3376 v8i16, v8i8, OpNode, Commutable>; 3377 def v4i32 : N3VL<op24, op23, 0b01, op11_8, op4, itin16, 3378 OpcodeStr, !strconcat(Dt, "16"), 3379 v4i32, v4i16, OpNode, Commutable>; 3380 def v2i64 : N3VL<op24, op23, 0b10, op11_8, op4, itin32, 3381 OpcodeStr, !strconcat(Dt, "32"), 3382 v2i64, v2i32, OpNode, Commutable>; 3383} 3384 3385multiclass N3VLSL_HS<bit op24, bits<4> op11_8, 3386 InstrItinClass itin, string OpcodeStr, string Dt, 3387 SDNode OpNode> { 3388 def v4i16 : N3VLSL16<op24, 0b01, op11_8, itin, OpcodeStr, 3389 !strconcat(Dt, "16"), v4i32, v4i16, OpNode>; 3390 def v2i32 : N3VLSL<op24, 0b10, op11_8, itin, OpcodeStr, 3391 !strconcat(Dt, "32"), v2i64, v2i32, OpNode>; 3392} 3393 3394multiclass N3VLExt_QHS<bit op24, bit op23, bits<4> op11_8, bit op4, 3395 InstrItinClass itin16, InstrItinClass itin32, 3396 string OpcodeStr, string Dt, 3397 SDNode OpNode, SDNode ExtOp, bit Commutable = 0> { 3398 def v8i16 : N3VLExt<op24, op23, 0b00, op11_8, op4, itin16, 3399 OpcodeStr, !strconcat(Dt, "8"), 3400 v8i16, v8i8, OpNode, ExtOp, Commutable>; 3401 def v4i32 : N3VLExt<op24, op23, 0b01, op11_8, op4, itin16, 3402 OpcodeStr, !strconcat(Dt, "16"), 3403 v4i32, v4i16, OpNode, ExtOp, Commutable>; 3404 def v2i64 : N3VLExt<op24, op23, 0b10, op11_8, op4, itin32, 3405 OpcodeStr, !strconcat(Dt, "32"), 3406 v2i64, v2i32, OpNode, ExtOp, Commutable>; 3407} 3408 3409// Neon Long 3-register vector intrinsics. 3410 3411// First with only element sizes of 16 and 32 bits: 3412multiclass N3VLInt_HS<bit op24, bit op23, bits<4> op11_8, bit op4, 3413 InstrItinClass itin16, InstrItinClass itin32, 3414 string OpcodeStr, string Dt, 3415 Intrinsic IntOp, bit Commutable = 0> { 3416 def v4i32 : N3VLInt<op24, op23, 0b01, op11_8, op4, itin16, 3417 OpcodeStr, !strconcat(Dt, "16"), 3418 v4i32, v4i16, IntOp, Commutable>; 3419 def v2i64 : N3VLInt<op24, op23, 0b10, op11_8, op4, itin32, 3420 OpcodeStr, !strconcat(Dt, "32"), 3421 v2i64, v2i32, IntOp, Commutable>; 3422} 3423 3424multiclass N3VLIntSL_HS<bit op24, bits<4> op11_8, 3425 InstrItinClass itin, string OpcodeStr, string Dt, 3426 Intrinsic IntOp> { 3427 def v4i16 : N3VLIntSL16<op24, 0b01, op11_8, itin, 3428 OpcodeStr, !strconcat(Dt, "16"), v4i32, v4i16, IntOp>; 3429 def v2i32 : N3VLIntSL<op24, 0b10, op11_8, itin, 3430 OpcodeStr, !strconcat(Dt, "32"), v2i64, v2i32, IntOp>; 3431} 3432 3433// ....then also with element size of 8 bits: 3434multiclass N3VLInt_QHS<bit op24, bit op23, bits<4> op11_8, bit op4, 3435 InstrItinClass itin16, InstrItinClass itin32, 3436 string OpcodeStr, string Dt, 3437 Intrinsic IntOp, bit Commutable = 0> 3438 : N3VLInt_HS<op24, op23, op11_8, op4, itin16, itin32, OpcodeStr, Dt, 3439 IntOp, Commutable> { 3440 def v8i16 : N3VLInt<op24, op23, 0b00, op11_8, op4, itin16, 3441 OpcodeStr, !strconcat(Dt, "8"), 3442 v8i16, v8i8, IntOp, Commutable>; 3443} 3444 3445// ....with explicit extend (VABDL). 3446multiclass N3VLIntExt_QHS<bit op24, bit op23, bits<4> op11_8, bit op4, 3447 InstrItinClass itin, string OpcodeStr, string Dt, 3448 Intrinsic IntOp, SDNode ExtOp, bit Commutable = 0> { 3449 def v8i16 : N3VLIntExt<op24, op23, 0b00, op11_8, op4, itin, 3450 OpcodeStr, !strconcat(Dt, "8"), 3451 v8i16, v8i8, IntOp, ExtOp, Commutable>; 3452 def v4i32 : N3VLIntExt<op24, op23, 0b01, op11_8, op4, itin, 3453 OpcodeStr, !strconcat(Dt, "16"), 3454 v4i32, v4i16, IntOp, ExtOp, Commutable>; 3455 def v2i64 : N3VLIntExt<op24, op23, 0b10, op11_8, op4, itin, 3456 OpcodeStr, !strconcat(Dt, "32"), 3457 v2i64, v2i32, IntOp, ExtOp, Commutable>; 3458} 3459 3460 3461// Neon Wide 3-register vector intrinsics, 3462// source operand element sizes of 8, 16 and 32 bits: 3463multiclass N3VW_QHS<bit op24, bit op23, bits<4> op11_8, bit op4, 3464 string OpcodeStr, string Dt, 3465 SDNode OpNode, SDNode ExtOp, bit Commutable = 0> { 3466 def v8i16 : N3VW<op24, op23, 0b00, op11_8, op4, 3467 OpcodeStr, !strconcat(Dt, "8"), 3468 v8i16, v8i8, OpNode, ExtOp, Commutable>; 3469 def v4i32 : N3VW<op24, op23, 0b01, op11_8, op4, 3470 OpcodeStr, !strconcat(Dt, "16"), 3471 v4i32, v4i16, OpNode, ExtOp, Commutable>; 3472 def v2i64 : N3VW<op24, op23, 0b10, op11_8, op4, 3473 OpcodeStr, !strconcat(Dt, "32"), 3474 v2i64, v2i32, OpNode, ExtOp, Commutable>; 3475} 3476 3477 3478// Neon Multiply-Op vector operations, 3479// element sizes of 8, 16 and 32 bits: 3480multiclass N3VMulOp_QHS<bit op24, bit op23, bits<4> op11_8, bit op4, 3481 InstrItinClass itinD16, InstrItinClass itinD32, 3482 InstrItinClass itinQ16, InstrItinClass itinQ32, 3483 string OpcodeStr, string Dt, SDNode OpNode> { 3484 // 64-bit vector types. 3485 def v8i8 : N3VDMulOp<op24, op23, 0b00, op11_8, op4, itinD16, 3486 OpcodeStr, !strconcat(Dt, "8"), v8i8, mul, OpNode>; 3487 def v4i16 : N3VDMulOp<op24, op23, 0b01, op11_8, op4, itinD16, 3488 OpcodeStr, !strconcat(Dt, "16"), v4i16, mul, OpNode>; 3489 def v2i32 : N3VDMulOp<op24, op23, 0b10, op11_8, op4, itinD32, 3490 OpcodeStr, !strconcat(Dt, "32"), v2i32, mul, OpNode>; 3491 3492 // 128-bit vector types. 3493 def v16i8 : N3VQMulOp<op24, op23, 0b00, op11_8, op4, itinQ16, 3494 OpcodeStr, !strconcat(Dt, "8"), v16i8, mul, OpNode>; 3495 def v8i16 : N3VQMulOp<op24, op23, 0b01, op11_8, op4, itinQ16, 3496 OpcodeStr, !strconcat(Dt, "16"), v8i16, mul, OpNode>; 3497 def v4i32 : N3VQMulOp<op24, op23, 0b10, op11_8, op4, itinQ32, 3498 OpcodeStr, !strconcat(Dt, "32"), v4i32, mul, OpNode>; 3499} 3500 3501multiclass N3VMulOpSL_HS<bits<4> op11_8, 3502 InstrItinClass itinD16, InstrItinClass itinD32, 3503 InstrItinClass itinQ16, InstrItinClass itinQ32, 3504 string OpcodeStr, string Dt, SDNode ShOp> { 3505 def v4i16 : N3VDMulOpSL16<0b01, op11_8, itinD16, 3506 OpcodeStr, !strconcat(Dt, "16"), v4i16, mul, ShOp>; 3507 def v2i32 : N3VDMulOpSL<0b10, op11_8, itinD32, 3508 OpcodeStr, !strconcat(Dt, "32"), v2i32, mul, ShOp>; 3509 def v8i16 : N3VQMulOpSL16<0b01, op11_8, itinQ16, 3510 OpcodeStr, !strconcat(Dt, "16"), v8i16, v4i16, 3511 mul, ShOp>; 3512 def v4i32 : N3VQMulOpSL<0b10, op11_8, itinQ32, 3513 OpcodeStr, !strconcat(Dt, "32"), v4i32, v2i32, 3514 mul, ShOp>; 3515} 3516 3517// Neon Intrinsic-Op vector operations, 3518// element sizes of 8, 16 and 32 bits: 3519multiclass N3VIntOp_QHS<bit op24, bit op23, bits<4> op11_8, bit op4, 3520 InstrItinClass itinD, InstrItinClass itinQ, 3521 string OpcodeStr, string Dt, Intrinsic IntOp, 3522 SDNode OpNode> { 3523 // 64-bit vector types. 3524 def v8i8 : N3VDIntOp<op24, op23, 0b00, op11_8, op4, itinD, 3525 OpcodeStr, !strconcat(Dt, "8"), v8i8, IntOp, OpNode>; 3526 def v4i16 : N3VDIntOp<op24, op23, 0b01, op11_8, op4, itinD, 3527 OpcodeStr, !strconcat(Dt, "16"), v4i16, IntOp, OpNode>; 3528 def v2i32 : N3VDIntOp<op24, op23, 0b10, op11_8, op4, itinD, 3529 OpcodeStr, !strconcat(Dt, "32"), v2i32, IntOp, OpNode>; 3530 3531 // 128-bit vector types. 3532 def v16i8 : N3VQIntOp<op24, op23, 0b00, op11_8, op4, itinQ, 3533 OpcodeStr, !strconcat(Dt, "8"), v16i8, IntOp, OpNode>; 3534 def v8i16 : N3VQIntOp<op24, op23, 0b01, op11_8, op4, itinQ, 3535 OpcodeStr, !strconcat(Dt, "16"), v8i16, IntOp, OpNode>; 3536 def v4i32 : N3VQIntOp<op24, op23, 0b10, op11_8, op4, itinQ, 3537 OpcodeStr, !strconcat(Dt, "32"), v4i32, IntOp, OpNode>; 3538} 3539 3540// Neon 3-argument intrinsics, 3541// element sizes of 8, 16 and 32 bits: 3542multiclass N3VInt3_QHS<bit op24, bit op23, bits<4> op11_8, bit op4, 3543 InstrItinClass itinD, InstrItinClass itinQ, 3544 string OpcodeStr, string Dt, Intrinsic IntOp> { 3545 // 64-bit vector types. 3546 def v8i8 : N3VDInt3<op24, op23, 0b00, op11_8, op4, itinD, 3547 OpcodeStr, !strconcat(Dt, "8"), v8i8, v8i8, IntOp>; 3548 def v4i16 : N3VDInt3<op24, op23, 0b01, op11_8, op4, itinD, 3549 OpcodeStr, !strconcat(Dt, "16"), v4i16, v4i16, IntOp>; 3550 def v2i32 : N3VDInt3<op24, op23, 0b10, op11_8, op4, itinD, 3551 OpcodeStr, !strconcat(Dt, "32"), v2i32, v2i32, IntOp>; 3552 3553 // 128-bit vector types. 3554 def v16i8 : N3VQInt3<op24, op23, 0b00, op11_8, op4, itinQ, 3555 OpcodeStr, !strconcat(Dt, "8"), v16i8, v16i8, IntOp>; 3556 def v8i16 : N3VQInt3<op24, op23, 0b01, op11_8, op4, itinQ, 3557 OpcodeStr, !strconcat(Dt, "16"), v8i16, v8i16, IntOp>; 3558 def v4i32 : N3VQInt3<op24, op23, 0b10, op11_8, op4, itinQ, 3559 OpcodeStr, !strconcat(Dt, "32"), v4i32, v4i32, IntOp>; 3560} 3561 3562 3563// Neon Long Multiply-Op vector operations, 3564// element sizes of 8, 16 and 32 bits: 3565multiclass N3VLMulOp_QHS<bit op24, bit op23, bits<4> op11_8, bit op4, 3566 InstrItinClass itin16, InstrItinClass itin32, 3567 string OpcodeStr, string Dt, SDNode MulOp, 3568 SDNode OpNode> { 3569 def v8i16 : N3VLMulOp<op24, op23, 0b00, op11_8, op4, itin16, OpcodeStr, 3570 !strconcat(Dt, "8"), v8i16, v8i8, MulOp, OpNode>; 3571 def v4i32 : N3VLMulOp<op24, op23, 0b01, op11_8, op4, itin16, OpcodeStr, 3572 !strconcat(Dt, "16"), v4i32, v4i16, MulOp, OpNode>; 3573 def v2i64 : N3VLMulOp<op24, op23, 0b10, op11_8, op4, itin32, OpcodeStr, 3574 !strconcat(Dt, "32"), v2i64, v2i32, MulOp, OpNode>; 3575} 3576 3577multiclass N3VLMulOpSL_HS<bit op24, bits<4> op11_8, string OpcodeStr, 3578 string Dt, SDNode MulOp, SDNode OpNode> { 3579 def v4i16 : N3VLMulOpSL16<op24, 0b01, op11_8, IIC_VMACi16D, OpcodeStr, 3580 !strconcat(Dt,"16"), v4i32, v4i16, MulOp, OpNode>; 3581 def v2i32 : N3VLMulOpSL<op24, 0b10, op11_8, IIC_VMACi32D, OpcodeStr, 3582 !strconcat(Dt, "32"), v2i64, v2i32, MulOp, OpNode>; 3583} 3584 3585 3586// Neon Long 3-argument intrinsics. 3587 3588// First with only element sizes of 16 and 32 bits: 3589multiclass N3VLInt3_HS<bit op24, bit op23, bits<4> op11_8, bit op4, 3590 InstrItinClass itin16, InstrItinClass itin32, 3591 string OpcodeStr, string Dt, Intrinsic IntOp> { 3592 def v4i32 : N3VLInt3<op24, op23, 0b01, op11_8, op4, itin16, 3593 OpcodeStr, !strconcat(Dt, "16"), v4i32, v4i16, IntOp>; 3594 def v2i64 : N3VLInt3<op24, op23, 0b10, op11_8, op4, itin32, 3595 OpcodeStr, !strconcat(Dt, "32"), v2i64, v2i32, IntOp>; 3596} 3597 3598multiclass N3VLInt3SL_HS<bit op24, bits<4> op11_8, 3599 string OpcodeStr, string Dt, Intrinsic IntOp> { 3600 def v4i16 : N3VLInt3SL16<op24, 0b01, op11_8, IIC_VMACi16D, 3601 OpcodeStr, !strconcat(Dt,"16"), v4i32, v4i16, IntOp>; 3602 def v2i32 : N3VLInt3SL<op24, 0b10, op11_8, IIC_VMACi32D, 3603 OpcodeStr, !strconcat(Dt, "32"), v2i64, v2i32, IntOp>; 3604} 3605 3606// ....then also with element size of 8 bits: 3607multiclass N3VLInt3_QHS<bit op24, bit op23, bits<4> op11_8, bit op4, 3608 InstrItinClass itin16, InstrItinClass itin32, 3609 string OpcodeStr, string Dt, Intrinsic IntOp> 3610 : N3VLInt3_HS<op24, op23, op11_8, op4, itin16, itin32, OpcodeStr, Dt, IntOp> { 3611 def v8i16 : N3VLInt3<op24, op23, 0b00, op11_8, op4, itin16, 3612 OpcodeStr, !strconcat(Dt, "8"), v8i16, v8i8, IntOp>; 3613} 3614 3615// ....with explicit extend (VABAL). 3616multiclass N3VLIntExtOp_QHS<bit op24, bit op23, bits<4> op11_8, bit op4, 3617 InstrItinClass itin, string OpcodeStr, string Dt, 3618 Intrinsic IntOp, SDNode ExtOp, SDNode OpNode> { 3619 def v8i16 : N3VLIntExtOp<op24, op23, 0b00, op11_8, op4, itin, 3620 OpcodeStr, !strconcat(Dt, "8"), v8i16, v8i8, 3621 IntOp, ExtOp, OpNode>; 3622 def v4i32 : N3VLIntExtOp<op24, op23, 0b01, op11_8, op4, itin, 3623 OpcodeStr, !strconcat(Dt, "16"), v4i32, v4i16, 3624 IntOp, ExtOp, OpNode>; 3625 def v2i64 : N3VLIntExtOp<op24, op23, 0b10, op11_8, op4, itin, 3626 OpcodeStr, !strconcat(Dt, "32"), v2i64, v2i32, 3627 IntOp, ExtOp, OpNode>; 3628} 3629 3630 3631// Neon Pairwise long 2-register intrinsics, 3632// element sizes of 8, 16 and 32 bits: 3633multiclass N2VPLInt_QHS<bits<2> op24_23, bits<2> op21_20, bits<2> op17_16, 3634 bits<5> op11_7, bit op4, 3635 string OpcodeStr, string Dt, Intrinsic IntOp> { 3636 // 64-bit vector types. 3637 def v8i8 : N2VDPLInt<op24_23, op21_20, 0b00, op17_16, op11_7, op4, 3638 OpcodeStr, !strconcat(Dt, "8"), v4i16, v8i8, IntOp>; 3639 def v4i16 : N2VDPLInt<op24_23, op21_20, 0b01, op17_16, op11_7, op4, 3640 OpcodeStr, !strconcat(Dt, "16"), v2i32, v4i16, IntOp>; 3641 def v2i32 : N2VDPLInt<op24_23, op21_20, 0b10, op17_16, op11_7, op4, 3642 OpcodeStr, !strconcat(Dt, "32"), v1i64, v2i32, IntOp>; 3643 3644 // 128-bit vector types. 3645 def v16i8 : N2VQPLInt<op24_23, op21_20, 0b00, op17_16, op11_7, op4, 3646 OpcodeStr, !strconcat(Dt, "8"), v8i16, v16i8, IntOp>; 3647 def v8i16 : N2VQPLInt<op24_23, op21_20, 0b01, op17_16, op11_7, op4, 3648 OpcodeStr, !strconcat(Dt, "16"), v4i32, v8i16, IntOp>; 3649 def v4i32 : N2VQPLInt<op24_23, op21_20, 0b10, op17_16, op11_7, op4, 3650 OpcodeStr, !strconcat(Dt, "32"), v2i64, v4i32, IntOp>; 3651} 3652 3653 3654// Neon Pairwise long 2-register accumulate intrinsics, 3655// element sizes of 8, 16 and 32 bits: 3656multiclass N2VPLInt2_QHS<bits<2> op24_23, bits<2> op21_20, bits<2> op17_16, 3657 bits<5> op11_7, bit op4, 3658 string OpcodeStr, string Dt, Intrinsic IntOp> { 3659 // 64-bit vector types. 3660 def v8i8 : N2VDPLInt2<op24_23, op21_20, 0b00, op17_16, op11_7, op4, 3661 OpcodeStr, !strconcat(Dt, "8"), v4i16, v8i8, IntOp>; 3662 def v4i16 : N2VDPLInt2<op24_23, op21_20, 0b01, op17_16, op11_7, op4, 3663 OpcodeStr, !strconcat(Dt, "16"), v2i32, v4i16, IntOp>; 3664 def v2i32 : N2VDPLInt2<op24_23, op21_20, 0b10, op17_16, op11_7, op4, 3665 OpcodeStr, !strconcat(Dt, "32"), v1i64, v2i32, IntOp>; 3666 3667 // 128-bit vector types. 3668 def v16i8 : N2VQPLInt2<op24_23, op21_20, 0b00, op17_16, op11_7, op4, 3669 OpcodeStr, !strconcat(Dt, "8"), v8i16, v16i8, IntOp>; 3670 def v8i16 : N2VQPLInt2<op24_23, op21_20, 0b01, op17_16, op11_7, op4, 3671 OpcodeStr, !strconcat(Dt, "16"), v4i32, v8i16, IntOp>; 3672 def v4i32 : N2VQPLInt2<op24_23, op21_20, 0b10, op17_16, op11_7, op4, 3673 OpcodeStr, !strconcat(Dt, "32"), v2i64, v4i32, IntOp>; 3674} 3675 3676 3677// Neon 2-register vector shift by immediate, 3678// with f of either N2RegVShLFrm or N2RegVShRFrm 3679// element sizes of 8, 16, 32 and 64 bits: 3680multiclass N2VShL_QHSD<bit op24, bit op23, bits<4> op11_8, bit op4, 3681 InstrItinClass itin, string OpcodeStr, string Dt, 3682 SDNode OpNode> { 3683 // 64-bit vector types. 3684 def v8i8 : N2VDSh<op24, op23, op11_8, 0, op4, N2RegVShLFrm, itin, i32imm, 3685 OpcodeStr, !strconcat(Dt, "8"), v8i8, OpNode> { 3686 let Inst{21-19} = 0b001; // imm6 = 001xxx 3687 } 3688 def v4i16 : N2VDSh<op24, op23, op11_8, 0, op4, N2RegVShLFrm, itin, i32imm, 3689 OpcodeStr, !strconcat(Dt, "16"), v4i16, OpNode> { 3690 let Inst{21-20} = 0b01; // imm6 = 01xxxx 3691 } 3692 def v2i32 : N2VDSh<op24, op23, op11_8, 0, op4, N2RegVShLFrm, itin, i32imm, 3693 OpcodeStr, !strconcat(Dt, "32"), v2i32, OpNode> { 3694 let Inst{21} = 0b1; // imm6 = 1xxxxx 3695 } 3696 def v1i64 : N2VDSh<op24, op23, op11_8, 1, op4, N2RegVShLFrm, itin, i32imm, 3697 OpcodeStr, !strconcat(Dt, "64"), v1i64, OpNode>; 3698 // imm6 = xxxxxx 3699 3700 // 128-bit vector types. 3701 def v16i8 : N2VQSh<op24, op23, op11_8, 0, op4, N2RegVShLFrm, itin, i32imm, 3702 OpcodeStr, !strconcat(Dt, "8"), v16i8, OpNode> { 3703 let Inst{21-19} = 0b001; // imm6 = 001xxx 3704 } 3705 def v8i16 : N2VQSh<op24, op23, op11_8, 0, op4, N2RegVShLFrm, itin, i32imm, 3706 OpcodeStr, !strconcat(Dt, "16"), v8i16, OpNode> { 3707 let Inst{21-20} = 0b01; // imm6 = 01xxxx 3708 } 3709 def v4i32 : N2VQSh<op24, op23, op11_8, 0, op4, N2RegVShLFrm, itin, i32imm, 3710 OpcodeStr, !strconcat(Dt, "32"), v4i32, OpNode> { 3711 let Inst{21} = 0b1; // imm6 = 1xxxxx 3712 } 3713 def v2i64 : N2VQSh<op24, op23, op11_8, 1, op4, N2RegVShLFrm, itin, i32imm, 3714 OpcodeStr, !strconcat(Dt, "64"), v2i64, OpNode>; 3715 // imm6 = xxxxxx 3716} 3717multiclass N2VShR_QHSD<bit op24, bit op23, bits<4> op11_8, bit op4, 3718 InstrItinClass itin, string OpcodeStr, string Dt, 3719 SDNode OpNode> { 3720 // 64-bit vector types. 3721 def v8i8 : N2VDSh<op24, op23, op11_8, 0, op4, N2RegVShRFrm, itin, shr_imm8, 3722 OpcodeStr, !strconcat(Dt, "8"), v8i8, OpNode> { 3723 let Inst{21-19} = 0b001; // imm6 = 001xxx 3724 } 3725 def v4i16 : N2VDSh<op24, op23, op11_8, 0, op4, N2RegVShRFrm, itin, shr_imm16, 3726 OpcodeStr, !strconcat(Dt, "16"), v4i16, OpNode> { 3727 let Inst{21-20} = 0b01; // imm6 = 01xxxx 3728 } 3729 def v2i32 : N2VDSh<op24, op23, op11_8, 0, op4, N2RegVShRFrm, itin, shr_imm32, 3730 OpcodeStr, !strconcat(Dt, "32"), v2i32, OpNode> { 3731 let Inst{21} = 0b1; // imm6 = 1xxxxx 3732 } 3733 def v1i64 : N2VDSh<op24, op23, op11_8, 1, op4, N2RegVShRFrm, itin, shr_imm64, 3734 OpcodeStr, !strconcat(Dt, "64"), v1i64, OpNode>; 3735 // imm6 = xxxxxx 3736 3737 // 128-bit vector types. 3738 def v16i8 : N2VQSh<op24, op23, op11_8, 0, op4, N2RegVShRFrm, itin, shr_imm8, 3739 OpcodeStr, !strconcat(Dt, "8"), v16i8, OpNode> { 3740 let Inst{21-19} = 0b001; // imm6 = 001xxx 3741 } 3742 def v8i16 : N2VQSh<op24, op23, op11_8, 0, op4, N2RegVShRFrm, itin, shr_imm16, 3743 OpcodeStr, !strconcat(Dt, "16"), v8i16, OpNode> { 3744 let Inst{21-20} = 0b01; // imm6 = 01xxxx 3745 } 3746 def v4i32 : N2VQSh<op24, op23, op11_8, 0, op4, N2RegVShRFrm, itin, shr_imm32, 3747 OpcodeStr, !strconcat(Dt, "32"), v4i32, OpNode> { 3748 let Inst{21} = 0b1; // imm6 = 1xxxxx 3749 } 3750 def v2i64 : N2VQSh<op24, op23, op11_8, 1, op4, N2RegVShRFrm, itin, shr_imm64, 3751 OpcodeStr, !strconcat(Dt, "64"), v2i64, OpNode>; 3752 // imm6 = xxxxxx 3753} 3754 3755// Neon Shift-Accumulate vector operations, 3756// element sizes of 8, 16, 32 and 64 bits: 3757multiclass N2VShAdd_QHSD<bit op24, bit op23, bits<4> op11_8, bit op4, 3758 string OpcodeStr, string Dt, SDNode ShOp> { 3759 // 64-bit vector types. 3760 def v8i8 : N2VDShAdd<op24, op23, op11_8, 0, op4, shr_imm8, 3761 OpcodeStr, !strconcat(Dt, "8"), v8i8, ShOp> { 3762 let Inst{21-19} = 0b001; // imm6 = 001xxx 3763 } 3764 def v4i16 : N2VDShAdd<op24, op23, op11_8, 0, op4, shr_imm16, 3765 OpcodeStr, !strconcat(Dt, "16"), v4i16, ShOp> { 3766 let Inst{21-20} = 0b01; // imm6 = 01xxxx 3767 } 3768 def v2i32 : N2VDShAdd<op24, op23, op11_8, 0, op4, shr_imm32, 3769 OpcodeStr, !strconcat(Dt, "32"), v2i32, ShOp> { 3770 let Inst{21} = 0b1; // imm6 = 1xxxxx 3771 } 3772 def v1i64 : N2VDShAdd<op24, op23, op11_8, 1, op4, shr_imm64, 3773 OpcodeStr, !strconcat(Dt, "64"), v1i64, ShOp>; 3774 // imm6 = xxxxxx 3775 3776 // 128-bit vector types. 3777 def v16i8 : N2VQShAdd<op24, op23, op11_8, 0, op4, shr_imm8, 3778 OpcodeStr, !strconcat(Dt, "8"), v16i8, ShOp> { 3779 let Inst{21-19} = 0b001; // imm6 = 001xxx 3780 } 3781 def v8i16 : N2VQShAdd<op24, op23, op11_8, 0, op4, shr_imm16, 3782 OpcodeStr, !strconcat(Dt, "16"), v8i16, ShOp> { 3783 let Inst{21-20} = 0b01; // imm6 = 01xxxx 3784 } 3785 def v4i32 : N2VQShAdd<op24, op23, op11_8, 0, op4, shr_imm32, 3786 OpcodeStr, !strconcat(Dt, "32"), v4i32, ShOp> { 3787 let Inst{21} = 0b1; // imm6 = 1xxxxx 3788 } 3789 def v2i64 : N2VQShAdd<op24, op23, op11_8, 1, op4, shr_imm64, 3790 OpcodeStr, !strconcat(Dt, "64"), v2i64, ShOp>; 3791 // imm6 = xxxxxx 3792} 3793 3794// Neon Shift-Insert vector operations, 3795// with f of either N2RegVShLFrm or N2RegVShRFrm 3796// element sizes of 8, 16, 32 and 64 bits: 3797multiclass N2VShInsL_QHSD<bit op24, bit op23, bits<4> op11_8, bit op4, 3798 string OpcodeStr> { 3799 // 64-bit vector types. 3800 def v8i8 : N2VDShIns<op24, op23, op11_8, 0, op4, i32imm, 3801 N2RegVShLFrm, OpcodeStr, "8", v8i8, NEONvsli> { 3802 let Inst{21-19} = 0b001; // imm6 = 001xxx 3803 } 3804 def v4i16 : N2VDShIns<op24, op23, op11_8, 0, op4, i32imm, 3805 N2RegVShLFrm, OpcodeStr, "16", v4i16, NEONvsli> { 3806 let Inst{21-20} = 0b01; // imm6 = 01xxxx 3807 } 3808 def v2i32 : N2VDShIns<op24, op23, op11_8, 0, op4, i32imm, 3809 N2RegVShLFrm, OpcodeStr, "32", v2i32, NEONvsli> { 3810 let Inst{21} = 0b1; // imm6 = 1xxxxx 3811 } 3812 def v1i64 : N2VDShIns<op24, op23, op11_8, 1, op4, i32imm, 3813 N2RegVShLFrm, OpcodeStr, "64", v1i64, NEONvsli>; 3814 // imm6 = xxxxxx 3815 3816 // 128-bit vector types. 3817 def v16i8 : N2VQShIns<op24, op23, op11_8, 0, op4, i32imm, 3818 N2RegVShLFrm, OpcodeStr, "8", v16i8, NEONvsli> { 3819 let Inst{21-19} = 0b001; // imm6 = 001xxx 3820 } 3821 def v8i16 : N2VQShIns<op24, op23, op11_8, 0, op4, i32imm, 3822 N2RegVShLFrm, OpcodeStr, "16", v8i16, NEONvsli> { 3823 let Inst{21-20} = 0b01; // imm6 = 01xxxx 3824 } 3825 def v4i32 : N2VQShIns<op24, op23, op11_8, 0, op4, i32imm, 3826 N2RegVShLFrm, OpcodeStr, "32", v4i32, NEONvsli> { 3827 let Inst{21} = 0b1; // imm6 = 1xxxxx 3828 } 3829 def v2i64 : N2VQShIns<op24, op23, op11_8, 1, op4, i32imm, 3830 N2RegVShLFrm, OpcodeStr, "64", v2i64, NEONvsli>; 3831 // imm6 = xxxxxx 3832} 3833multiclass N2VShInsR_QHSD<bit op24, bit op23, bits<4> op11_8, bit op4, 3834 string OpcodeStr> { 3835 // 64-bit vector types. 3836 def v8i8 : N2VDShIns<op24, op23, op11_8, 0, op4, shr_imm8, 3837 N2RegVShRFrm, OpcodeStr, "8", v8i8, NEONvsri> { 3838 let Inst{21-19} = 0b001; // imm6 = 001xxx 3839 } 3840 def v4i16 : N2VDShIns<op24, op23, op11_8, 0, op4, shr_imm16, 3841 N2RegVShRFrm, OpcodeStr, "16", v4i16, NEONvsri> { 3842 let Inst{21-20} = 0b01; // imm6 = 01xxxx 3843 } 3844 def v2i32 : N2VDShIns<op24, op23, op11_8, 0, op4, shr_imm32, 3845 N2RegVShRFrm, OpcodeStr, "32", v2i32, NEONvsri> { 3846 let Inst{21} = 0b1; // imm6 = 1xxxxx 3847 } 3848 def v1i64 : N2VDShIns<op24, op23, op11_8, 1, op4, shr_imm64, 3849 N2RegVShRFrm, OpcodeStr, "64", v1i64, NEONvsri>; 3850 // imm6 = xxxxxx 3851 3852 // 128-bit vector types. 3853 def v16i8 : N2VQShIns<op24, op23, op11_8, 0, op4, shr_imm8, 3854 N2RegVShRFrm, OpcodeStr, "8", v16i8, NEONvsri> { 3855 let Inst{21-19} = 0b001; // imm6 = 001xxx 3856 } 3857 def v8i16 : N2VQShIns<op24, op23, op11_8, 0, op4, shr_imm16, 3858 N2RegVShRFrm, OpcodeStr, "16", v8i16, NEONvsri> { 3859 let Inst{21-20} = 0b01; // imm6 = 01xxxx 3860 } 3861 def v4i32 : N2VQShIns<op24, op23, op11_8, 0, op4, shr_imm32, 3862 N2RegVShRFrm, OpcodeStr, "32", v4i32, NEONvsri> { 3863 let Inst{21} = 0b1; // imm6 = 1xxxxx 3864 } 3865 def v2i64 : N2VQShIns<op24, op23, op11_8, 1, op4, shr_imm64, 3866 N2RegVShRFrm, OpcodeStr, "64", v2i64, NEONvsri>; 3867 // imm6 = xxxxxx 3868} 3869 3870// Neon Shift Long operations, 3871// element sizes of 8, 16, 32 bits: 3872multiclass N2VLSh_QHS<bit op24, bit op23, bits<4> op11_8, bit op7, bit op6, 3873 bit op4, string OpcodeStr, string Dt, SDNode OpNode> { 3874 def v8i16 : N2VLSh<op24, op23, op11_8, op7, op6, op4, 3875 OpcodeStr, !strconcat(Dt, "8"), v8i16, v8i8, imm1_7, OpNode> { 3876 let Inst{21-19} = 0b001; // imm6 = 001xxx 3877 } 3878 def v4i32 : N2VLSh<op24, op23, op11_8, op7, op6, op4, 3879 OpcodeStr, !strconcat(Dt, "16"), v4i32, v4i16, imm1_15, OpNode> { 3880 let Inst{21-20} = 0b01; // imm6 = 01xxxx 3881 } 3882 def v2i64 : N2VLSh<op24, op23, op11_8, op7, op6, op4, 3883 OpcodeStr, !strconcat(Dt, "32"), v2i64, v2i32, imm1_31, OpNode> { 3884 let Inst{21} = 0b1; // imm6 = 1xxxxx 3885 } 3886} 3887 3888// Neon Shift Narrow operations, 3889// element sizes of 16, 32, 64 bits: 3890multiclass N2VNSh_HSD<bit op24, bit op23, bits<4> op11_8, bit op7, bit op6, 3891 bit op4, InstrItinClass itin, string OpcodeStr, string Dt, 3892 SDNode OpNode> { 3893 def v8i8 : N2VNSh<op24, op23, op11_8, op7, op6, op4, itin, 3894 OpcodeStr, !strconcat(Dt, "16"), 3895 v8i8, v8i16, shr_imm8, OpNode> { 3896 let Inst{21-19} = 0b001; // imm6 = 001xxx 3897 } 3898 def v4i16 : N2VNSh<op24, op23, op11_8, op7, op6, op4, itin, 3899 OpcodeStr, !strconcat(Dt, "32"), 3900 v4i16, v4i32, shr_imm16, OpNode> { 3901 let Inst{21-20} = 0b01; // imm6 = 01xxxx 3902 } 3903 def v2i32 : N2VNSh<op24, op23, op11_8, op7, op6, op4, itin, 3904 OpcodeStr, !strconcat(Dt, "64"), 3905 v2i32, v2i64, shr_imm32, OpNode> { 3906 let Inst{21} = 0b1; // imm6 = 1xxxxx 3907 } 3908} 3909 3910//===----------------------------------------------------------------------===// 3911// Instruction Definitions. 3912//===----------------------------------------------------------------------===// 3913 3914// Vector Add Operations. 3915 3916// VADD : Vector Add (integer and floating-point) 3917defm VADD : N3V_QHSD<0, 0, 0b1000, 0, IIC_VBINiD, IIC_VBINiQ, "vadd", "i", 3918 add, 1>; 3919def VADDfd : N3VD<0, 0, 0b00, 0b1101, 0, IIC_VBIND, "vadd", "f32", 3920 v2f32, v2f32, fadd, 1>; 3921def VADDfq : N3VQ<0, 0, 0b00, 0b1101, 0, IIC_VBINQ, "vadd", "f32", 3922 v4f32, v4f32, fadd, 1>; 3923// VADDL : Vector Add Long (Q = D + D) 3924defm VADDLs : N3VLExt_QHS<0,1,0b0000,0, IIC_VSHLiD, IIC_VSHLiD, 3925 "vaddl", "s", add, sext, 1>; 3926defm VADDLu : N3VLExt_QHS<1,1,0b0000,0, IIC_VSHLiD, IIC_VSHLiD, 3927 "vaddl", "u", add, zext, 1>; 3928// VADDW : Vector Add Wide (Q = Q + D) 3929defm VADDWs : N3VW_QHS<0,1,0b0001,0, "vaddw", "s", add, sext, 0>; 3930defm VADDWu : N3VW_QHS<1,1,0b0001,0, "vaddw", "u", add, zext, 0>; 3931// VHADD : Vector Halving Add 3932defm VHADDs : N3VInt_QHS<0, 0, 0b0000, 0, N3RegFrm, 3933 IIC_VBINi4D, IIC_VBINi4D, IIC_VBINi4Q, IIC_VBINi4Q, 3934 "vhadd", "s", int_arm_neon_vhadds, 1>; 3935defm VHADDu : N3VInt_QHS<1, 0, 0b0000, 0, N3RegFrm, 3936 IIC_VBINi4D, IIC_VBINi4D, IIC_VBINi4Q, IIC_VBINi4Q, 3937 "vhadd", "u", int_arm_neon_vhaddu, 1>; 3938// VRHADD : Vector Rounding Halving Add 3939defm VRHADDs : N3VInt_QHS<0, 0, 0b0001, 0, N3RegFrm, 3940 IIC_VBINi4D, IIC_VBINi4D, IIC_VBINi4Q, IIC_VBINi4Q, 3941 "vrhadd", "s", int_arm_neon_vrhadds, 1>; 3942defm VRHADDu : N3VInt_QHS<1, 0, 0b0001, 0, N3RegFrm, 3943 IIC_VBINi4D, IIC_VBINi4D, IIC_VBINi4Q, IIC_VBINi4Q, 3944 "vrhadd", "u", int_arm_neon_vrhaddu, 1>; 3945// VQADD : Vector Saturating Add 3946defm VQADDs : N3VInt_QHSD<0, 0, 0b0000, 1, N3RegFrm, 3947 IIC_VBINi4D, IIC_VBINi4D, IIC_VBINi4Q, IIC_VBINi4Q, 3948 "vqadd", "s", int_arm_neon_vqadds, 1>; 3949defm VQADDu : N3VInt_QHSD<1, 0, 0b0000, 1, N3RegFrm, 3950 IIC_VBINi4D, IIC_VBINi4D, IIC_VBINi4Q, IIC_VBINi4Q, 3951 "vqadd", "u", int_arm_neon_vqaddu, 1>; 3952// VADDHN : Vector Add and Narrow Returning High Half (D = Q + Q) 3953defm VADDHN : N3VNInt_HSD<0,1,0b0100,0, "vaddhn", "i", 3954 int_arm_neon_vaddhn, 1>; 3955// VRADDHN : Vector Rounding Add and Narrow Returning High Half (D = Q + Q) 3956defm VRADDHN : N3VNInt_HSD<1,1,0b0100,0, "vraddhn", "i", 3957 int_arm_neon_vraddhn, 1>; 3958 3959// Vector Multiply Operations. 3960 3961// VMUL : Vector Multiply (integer, polynomial and floating-point) 3962defm VMUL : N3V_QHS<0, 0, 0b1001, 1, IIC_VMULi16D, IIC_VMULi32D, 3963 IIC_VMULi16Q, IIC_VMULi32Q, "vmul", "i", mul, 1>; 3964def VMULpd : N3VDInt<1, 0, 0b00, 0b1001, 1, N3RegFrm, IIC_VMULi16D, "vmul", 3965 "p8", v8i8, v8i8, int_arm_neon_vmulp, 1>; 3966def VMULpq : N3VQInt<1, 0, 0b00, 0b1001, 1, N3RegFrm, IIC_VMULi16Q, "vmul", 3967 "p8", v16i8, v16i8, int_arm_neon_vmulp, 1>; 3968def VMULfd : N3VD<1, 0, 0b00, 0b1101, 1, IIC_VFMULD, "vmul", "f32", 3969 v2f32, v2f32, fmul, 1>; 3970def VMULfq : N3VQ<1, 0, 0b00, 0b1101, 1, IIC_VFMULQ, "vmul", "f32", 3971 v4f32, v4f32, fmul, 1>; 3972defm VMULsl : N3VSL_HS<0b1000, "vmul", mul>; 3973def VMULslfd : N3VDSL<0b10, 0b1001, IIC_VBIND, "vmul", "f32", v2f32, fmul>; 3974def VMULslfq : N3VQSL<0b10, 0b1001, IIC_VBINQ, "vmul", "f32", v4f32, 3975 v2f32, fmul>; 3976 3977def : Pat<(v8i16 (mul (v8i16 QPR:$src1), 3978 (v8i16 (NEONvduplane (v8i16 QPR:$src2), imm:$lane)))), 3979 (v8i16 (VMULslv8i16 (v8i16 QPR:$src1), 3980 (v4i16 (EXTRACT_SUBREG QPR:$src2, 3981 (DSubReg_i16_reg imm:$lane))), 3982 (SubReg_i16_lane imm:$lane)))>; 3983def : Pat<(v4i32 (mul (v4i32 QPR:$src1), 3984 (v4i32 (NEONvduplane (v4i32 QPR:$src2), imm:$lane)))), 3985 (v4i32 (VMULslv4i32 (v4i32 QPR:$src1), 3986 (v2i32 (EXTRACT_SUBREG QPR:$src2, 3987 (DSubReg_i32_reg imm:$lane))), 3988 (SubReg_i32_lane imm:$lane)))>; 3989def : Pat<(v4f32 (fmul (v4f32 QPR:$src1), 3990 (v4f32 (NEONvduplane (v4f32 QPR:$src2), imm:$lane)))), 3991 (v4f32 (VMULslfq (v4f32 QPR:$src1), 3992 (v2f32 (EXTRACT_SUBREG QPR:$src2, 3993 (DSubReg_i32_reg imm:$lane))), 3994 (SubReg_i32_lane imm:$lane)))>; 3995 3996// VQDMULH : Vector Saturating Doubling Multiply Returning High Half 3997defm VQDMULH : N3VInt_HS<0, 0, 0b1011, 0, N3RegFrm, IIC_VMULi16D, IIC_VMULi32D, 3998 IIC_VMULi16Q, IIC_VMULi32Q, 3999 "vqdmulh", "s", int_arm_neon_vqdmulh, 1>; 4000defm VQDMULHsl: N3VIntSL_HS<0b1100, IIC_VMULi16D, IIC_VMULi32D, 4001 IIC_VMULi16Q, IIC_VMULi32Q, 4002 "vqdmulh", "s", int_arm_neon_vqdmulh>; 4003def : Pat<(v8i16 (int_arm_neon_vqdmulh (v8i16 QPR:$src1), 4004 (v8i16 (NEONvduplane (v8i16 QPR:$src2), 4005 imm:$lane)))), 4006 (v8i16 (VQDMULHslv8i16 (v8i16 QPR:$src1), 4007 (v4i16 (EXTRACT_SUBREG QPR:$src2, 4008 (DSubReg_i16_reg imm:$lane))), 4009 (SubReg_i16_lane imm:$lane)))>; 4010def : Pat<(v4i32 (int_arm_neon_vqdmulh (v4i32 QPR:$src1), 4011 (v4i32 (NEONvduplane (v4i32 QPR:$src2), 4012 imm:$lane)))), 4013 (v4i32 (VQDMULHslv4i32 (v4i32 QPR:$src1), 4014 (v2i32 (EXTRACT_SUBREG QPR:$src2, 4015 (DSubReg_i32_reg imm:$lane))), 4016 (SubReg_i32_lane imm:$lane)))>; 4017 4018// VQRDMULH : Vector Rounding Saturating Doubling Multiply Returning High Half 4019defm VQRDMULH : N3VInt_HS<1, 0, 0b1011, 0, N3RegFrm, 4020 IIC_VMULi16D,IIC_VMULi32D,IIC_VMULi16Q,IIC_VMULi32Q, 4021 "vqrdmulh", "s", int_arm_neon_vqrdmulh, 1>; 4022defm VQRDMULHsl : N3VIntSL_HS<0b1101, IIC_VMULi16D, IIC_VMULi32D, 4023 IIC_VMULi16Q, IIC_VMULi32Q, 4024 "vqrdmulh", "s", int_arm_neon_vqrdmulh>; 4025def : Pat<(v8i16 (int_arm_neon_vqrdmulh (v8i16 QPR:$src1), 4026 (v8i16 (NEONvduplane (v8i16 QPR:$src2), 4027 imm:$lane)))), 4028 (v8i16 (VQRDMULHslv8i16 (v8i16 QPR:$src1), 4029 (v4i16 (EXTRACT_SUBREG QPR:$src2, 4030 (DSubReg_i16_reg imm:$lane))), 4031 (SubReg_i16_lane imm:$lane)))>; 4032def : Pat<(v4i32 (int_arm_neon_vqrdmulh (v4i32 QPR:$src1), 4033 (v4i32 (NEONvduplane (v4i32 QPR:$src2), 4034 imm:$lane)))), 4035 (v4i32 (VQRDMULHslv4i32 (v4i32 QPR:$src1), 4036 (v2i32 (EXTRACT_SUBREG QPR:$src2, 4037 (DSubReg_i32_reg imm:$lane))), 4038 (SubReg_i32_lane imm:$lane)))>; 4039 4040// VMULL : Vector Multiply Long (integer and polynomial) (Q = D * D) 4041defm VMULLs : N3VL_QHS<0,1,0b1100,0, IIC_VMULi16D, IIC_VMULi32D, 4042 "vmull", "s", NEONvmulls, 1>; 4043defm VMULLu : N3VL_QHS<1,1,0b1100,0, IIC_VMULi16D, IIC_VMULi32D, 4044 "vmull", "u", NEONvmullu, 1>; 4045def VMULLp : N3VLInt<0, 1, 0b00, 0b1110, 0, IIC_VMULi16D, "vmull", "p8", 4046 v8i16, v8i8, int_arm_neon_vmullp, 1>; 4047defm VMULLsls : N3VLSL_HS<0, 0b1010, IIC_VMULi16D, "vmull", "s", NEONvmulls>; 4048defm VMULLslu : N3VLSL_HS<1, 0b1010, IIC_VMULi16D, "vmull", "u", NEONvmullu>; 4049 4050// VQDMULL : Vector Saturating Doubling Multiply Long (Q = D * D) 4051defm VQDMULL : N3VLInt_HS<0,1,0b1101,0, IIC_VMULi16D, IIC_VMULi32D, 4052 "vqdmull", "s", int_arm_neon_vqdmull, 1>; 4053defm VQDMULLsl: N3VLIntSL_HS<0, 0b1011, IIC_VMULi16D, 4054 "vqdmull", "s", int_arm_neon_vqdmull>; 4055 4056// Vector Multiply-Accumulate and Multiply-Subtract Operations. 4057 4058// VMLA : Vector Multiply Accumulate (integer and floating-point) 4059defm VMLA : N3VMulOp_QHS<0, 0, 0b1001, 0, IIC_VMACi16D, IIC_VMACi32D, 4060 IIC_VMACi16Q, IIC_VMACi32Q, "vmla", "i", add>; 4061def VMLAfd : N3VDMulOp<0, 0, 0b00, 0b1101, 1, IIC_VMACD, "vmla", "f32", 4062 v2f32, fmul_su, fadd_mlx>, 4063 Requires<[HasNEON, UseFPVMLx, NoNEONVFP4]>; 4064def VMLAfq : N3VQMulOp<0, 0, 0b00, 0b1101, 1, IIC_VMACQ, "vmla", "f32", 4065 v4f32, fmul_su, fadd_mlx>, 4066 Requires<[HasNEON, UseFPVMLx, NoNEONVFP4]>; 4067defm VMLAsl : N3VMulOpSL_HS<0b0000, IIC_VMACi16D, IIC_VMACi32D, 4068 IIC_VMACi16Q, IIC_VMACi32Q, "vmla", "i", add>; 4069def VMLAslfd : N3VDMulOpSL<0b10, 0b0001, IIC_VMACD, "vmla", "f32", 4070 v2f32, fmul_su, fadd_mlx>, 4071 Requires<[HasNEON, UseFPVMLx]>; 4072def VMLAslfq : N3VQMulOpSL<0b10, 0b0001, IIC_VMACQ, "vmla", "f32", 4073 v4f32, v2f32, fmul_su, fadd_mlx>, 4074 Requires<[HasNEON, UseFPVMLx]>; 4075 4076def : Pat<(v8i16 (add (v8i16 QPR:$src1), 4077 (mul (v8i16 QPR:$src2), 4078 (v8i16 (NEONvduplane (v8i16 QPR:$src3), imm:$lane))))), 4079 (v8i16 (VMLAslv8i16 (v8i16 QPR:$src1), (v8i16 QPR:$src2), 4080 (v4i16 (EXTRACT_SUBREG QPR:$src3, 4081 (DSubReg_i16_reg imm:$lane))), 4082 (SubReg_i16_lane imm:$lane)))>; 4083 4084def : Pat<(v4i32 (add (v4i32 QPR:$src1), 4085 (mul (v4i32 QPR:$src2), 4086 (v4i32 (NEONvduplane (v4i32 QPR:$src3), imm:$lane))))), 4087 (v4i32 (VMLAslv4i32 (v4i32 QPR:$src1), (v4i32 QPR:$src2), 4088 (v2i32 (EXTRACT_SUBREG QPR:$src3, 4089 (DSubReg_i32_reg imm:$lane))), 4090 (SubReg_i32_lane imm:$lane)))>; 4091 4092def : Pat<(v4f32 (fadd_mlx (v4f32 QPR:$src1), 4093 (fmul_su (v4f32 QPR:$src2), 4094 (v4f32 (NEONvduplane (v4f32 QPR:$src3), imm:$lane))))), 4095 (v4f32 (VMLAslfq (v4f32 QPR:$src1), 4096 (v4f32 QPR:$src2), 4097 (v2f32 (EXTRACT_SUBREG QPR:$src3, 4098 (DSubReg_i32_reg imm:$lane))), 4099 (SubReg_i32_lane imm:$lane)))>, 4100 Requires<[HasNEON, UseFPVMLx]>; 4101 4102// VMLAL : Vector Multiply Accumulate Long (Q += D * D) 4103defm VMLALs : N3VLMulOp_QHS<0,1,0b1000,0, IIC_VMACi16D, IIC_VMACi32D, 4104 "vmlal", "s", NEONvmulls, add>; 4105defm VMLALu : N3VLMulOp_QHS<1,1,0b1000,0, IIC_VMACi16D, IIC_VMACi32D, 4106 "vmlal", "u", NEONvmullu, add>; 4107 4108defm VMLALsls : N3VLMulOpSL_HS<0, 0b0010, "vmlal", "s", NEONvmulls, add>; 4109defm VMLALslu : N3VLMulOpSL_HS<1, 0b0010, "vmlal", "u", NEONvmullu, add>; 4110 4111// VQDMLAL : Vector Saturating Doubling Multiply Accumulate Long (Q += D * D) 4112defm VQDMLAL : N3VLInt3_HS<0, 1, 0b1001, 0, IIC_VMACi16D, IIC_VMACi32D, 4113 "vqdmlal", "s", int_arm_neon_vqdmlal>; 4114defm VQDMLALsl: N3VLInt3SL_HS<0, 0b0011, "vqdmlal", "s", int_arm_neon_vqdmlal>; 4115 4116// VMLS : Vector Multiply Subtract (integer and floating-point) 4117defm VMLS : N3VMulOp_QHS<1, 0, 0b1001, 0, IIC_VMACi16D, IIC_VMACi32D, 4118 IIC_VMACi16Q, IIC_VMACi32Q, "vmls", "i", sub>; 4119def VMLSfd : N3VDMulOp<0, 0, 0b10, 0b1101, 1, IIC_VMACD, "vmls", "f32", 4120 v2f32, fmul_su, fsub_mlx>, 4121 Requires<[HasNEON, UseFPVMLx, NoNEONVFP4]>; 4122def VMLSfq : N3VQMulOp<0, 0, 0b10, 0b1101, 1, IIC_VMACQ, "vmls", "f32", 4123 v4f32, fmul_su, fsub_mlx>, 4124 Requires<[HasNEON, UseFPVMLx, NoNEONVFP4]>; 4125defm VMLSsl : N3VMulOpSL_HS<0b0100, IIC_VMACi16D, IIC_VMACi32D, 4126 IIC_VMACi16Q, IIC_VMACi32Q, "vmls", "i", sub>; 4127def VMLSslfd : N3VDMulOpSL<0b10, 0b0101, IIC_VMACD, "vmls", "f32", 4128 v2f32, fmul_su, fsub_mlx>, 4129 Requires<[HasNEON, UseFPVMLx]>; 4130def VMLSslfq : N3VQMulOpSL<0b10, 0b0101, IIC_VMACQ, "vmls", "f32", 4131 v4f32, v2f32, fmul_su, fsub_mlx>, 4132 Requires<[HasNEON, UseFPVMLx]>; 4133 4134def : Pat<(v8i16 (sub (v8i16 QPR:$src1), 4135 (mul (v8i16 QPR:$src2), 4136 (v8i16 (NEONvduplane (v8i16 QPR:$src3), imm:$lane))))), 4137 (v8i16 (VMLSslv8i16 (v8i16 QPR:$src1), (v8i16 QPR:$src2), 4138 (v4i16 (EXTRACT_SUBREG QPR:$src3, 4139 (DSubReg_i16_reg imm:$lane))), 4140 (SubReg_i16_lane imm:$lane)))>; 4141 4142def : Pat<(v4i32 (sub (v4i32 QPR:$src1), 4143 (mul (v4i32 QPR:$src2), 4144 (v4i32 (NEONvduplane (v4i32 QPR:$src3), imm:$lane))))), 4145 (v4i32 (VMLSslv4i32 (v4i32 QPR:$src1), (v4i32 QPR:$src2), 4146 (v2i32 (EXTRACT_SUBREG QPR:$src3, 4147 (DSubReg_i32_reg imm:$lane))), 4148 (SubReg_i32_lane imm:$lane)))>; 4149 4150def : Pat<(v4f32 (fsub_mlx (v4f32 QPR:$src1), 4151 (fmul_su (v4f32 QPR:$src2), 4152 (v4f32 (NEONvduplane (v4f32 QPR:$src3), imm:$lane))))), 4153 (v4f32 (VMLSslfq (v4f32 QPR:$src1), (v4f32 QPR:$src2), 4154 (v2f32 (EXTRACT_SUBREG QPR:$src3, 4155 (DSubReg_i32_reg imm:$lane))), 4156 (SubReg_i32_lane imm:$lane)))>, 4157 Requires<[HasNEON, UseFPVMLx]>; 4158 4159// VMLSL : Vector Multiply Subtract Long (Q -= D * D) 4160defm VMLSLs : N3VLMulOp_QHS<0,1,0b1010,0, IIC_VMACi16D, IIC_VMACi32D, 4161 "vmlsl", "s", NEONvmulls, sub>; 4162defm VMLSLu : N3VLMulOp_QHS<1,1,0b1010,0, IIC_VMACi16D, IIC_VMACi32D, 4163 "vmlsl", "u", NEONvmullu, sub>; 4164 4165defm VMLSLsls : N3VLMulOpSL_HS<0, 0b0110, "vmlsl", "s", NEONvmulls, sub>; 4166defm VMLSLslu : N3VLMulOpSL_HS<1, 0b0110, "vmlsl", "u", NEONvmullu, sub>; 4167 4168// VQDMLSL : Vector Saturating Doubling Multiply Subtract Long (Q -= D * D) 4169defm VQDMLSL : N3VLInt3_HS<0, 1, 0b1011, 0, IIC_VMACi16D, IIC_VMACi32D, 4170 "vqdmlsl", "s", int_arm_neon_vqdmlsl>; 4171defm VQDMLSLsl: N3VLInt3SL_HS<0, 0b111, "vqdmlsl", "s", int_arm_neon_vqdmlsl>; 4172 4173 4174// Fused Vector Multiply-Accumulate and Fused Multiply-Subtract Operations. 4175def VFMAfd : N3VDMulOp<0, 0, 0b00, 0b1100, 1, IIC_VFMACD, "vfma", "f32", 4176 v2f32, fmul_su, fadd_mlx>, 4177 Requires<[HasNEONVFP4]>; 4178 4179def VFMAfq : N3VQMulOp<0, 0, 0b00, 0b1100, 1, IIC_VFMACQ, "vfma", "f32", 4180 v4f32, fmul_su, fadd_mlx>, 4181 Requires<[HasNEONVFP4]>; 4182 4183// Fused Vector Multiply Subtract (floating-point) 4184def VFMSfd : N3VDMulOp<0, 0, 0b10, 0b1100, 1, IIC_VFMACD, "vfms", "f32", 4185 v2f32, fmul_su, fsub_mlx>, 4186 Requires<[HasNEONVFP4]>; 4187def VFMSfq : N3VQMulOp<0, 0, 0b10, 0b1100, 1, IIC_VFMACQ, "vfms", "f32", 4188 v4f32, fmul_su, fsub_mlx>, 4189 Requires<[HasNEONVFP4]>; 4190 4191// Vector Subtract Operations. 4192 4193// VSUB : Vector Subtract (integer and floating-point) 4194defm VSUB : N3V_QHSD<1, 0, 0b1000, 0, IIC_VSUBiD, IIC_VSUBiQ, 4195 "vsub", "i", sub, 0>; 4196def VSUBfd : N3VD<0, 0, 0b10, 0b1101, 0, IIC_VBIND, "vsub", "f32", 4197 v2f32, v2f32, fsub, 0>; 4198def VSUBfq : N3VQ<0, 0, 0b10, 0b1101, 0, IIC_VBINQ, "vsub", "f32", 4199 v4f32, v4f32, fsub, 0>; 4200// VSUBL : Vector Subtract Long (Q = D - D) 4201defm VSUBLs : N3VLExt_QHS<0,1,0b0010,0, IIC_VSHLiD, IIC_VSHLiD, 4202 "vsubl", "s", sub, sext, 0>; 4203defm VSUBLu : N3VLExt_QHS<1,1,0b0010,0, IIC_VSHLiD, IIC_VSHLiD, 4204 "vsubl", "u", sub, zext, 0>; 4205// VSUBW : Vector Subtract Wide (Q = Q - D) 4206defm VSUBWs : N3VW_QHS<0,1,0b0011,0, "vsubw", "s", sub, sext, 0>; 4207defm VSUBWu : N3VW_QHS<1,1,0b0011,0, "vsubw", "u", sub, zext, 0>; 4208// VHSUB : Vector Halving Subtract 4209defm VHSUBs : N3VInt_QHS<0, 0, 0b0010, 0, N3RegFrm, 4210 IIC_VSUBi4D, IIC_VSUBi4D, IIC_VSUBi4Q, IIC_VSUBi4Q, 4211 "vhsub", "s", int_arm_neon_vhsubs, 0>; 4212defm VHSUBu : N3VInt_QHS<1, 0, 0b0010, 0, N3RegFrm, 4213 IIC_VSUBi4D, IIC_VSUBi4D, IIC_VSUBi4Q, IIC_VSUBi4Q, 4214 "vhsub", "u", int_arm_neon_vhsubu, 0>; 4215// VQSUB : Vector Saturing Subtract 4216defm VQSUBs : N3VInt_QHSD<0, 0, 0b0010, 1, N3RegFrm, 4217 IIC_VSUBi4D, IIC_VSUBi4D, IIC_VSUBi4Q, IIC_VSUBi4Q, 4218 "vqsub", "s", int_arm_neon_vqsubs, 0>; 4219defm VQSUBu : N3VInt_QHSD<1, 0, 0b0010, 1, N3RegFrm, 4220 IIC_VSUBi4D, IIC_VSUBi4D, IIC_VSUBi4Q, IIC_VSUBi4Q, 4221 "vqsub", "u", int_arm_neon_vqsubu, 0>; 4222// VSUBHN : Vector Subtract and Narrow Returning High Half (D = Q - Q) 4223defm VSUBHN : N3VNInt_HSD<0,1,0b0110,0, "vsubhn", "i", 4224 int_arm_neon_vsubhn, 0>; 4225// VRSUBHN : Vector Rounding Subtract and Narrow Returning High Half (D=Q-Q) 4226defm VRSUBHN : N3VNInt_HSD<1,1,0b0110,0, "vrsubhn", "i", 4227 int_arm_neon_vrsubhn, 0>; 4228 4229// Vector Comparisons. 4230 4231// VCEQ : Vector Compare Equal 4232defm VCEQ : N3V_QHS<1, 0, 0b1000, 1, IIC_VSUBi4D, IIC_VSUBi4D, IIC_VSUBi4Q, 4233 IIC_VSUBi4Q, "vceq", "i", NEONvceq, 1>; 4234def VCEQfd : N3VD<0,0,0b00,0b1110,0, IIC_VBIND, "vceq", "f32", v2i32, v2f32, 4235 NEONvceq, 1>; 4236def VCEQfq : N3VQ<0,0,0b00,0b1110,0, IIC_VBINQ, "vceq", "f32", v4i32, v4f32, 4237 NEONvceq, 1>; 4238 4239defm VCEQz : N2V_QHS_cmp<0b11, 0b11, 0b01, 0b00010, 0, "vceq", "i", 4240 "$Vd, $Vm, #0", NEONvceqz>; 4241 4242// VCGE : Vector Compare Greater Than or Equal 4243defm VCGEs : N3V_QHS<0, 0, 0b0011, 1, IIC_VSUBi4D, IIC_VSUBi4D, IIC_VSUBi4Q, 4244 IIC_VSUBi4Q, "vcge", "s", NEONvcge, 0>; 4245defm VCGEu : N3V_QHS<1, 0, 0b0011, 1, IIC_VSUBi4D, IIC_VSUBi4D, IIC_VSUBi4Q, 4246 IIC_VSUBi4Q, "vcge", "u", NEONvcgeu, 0>; 4247def VCGEfd : N3VD<1,0,0b00,0b1110,0, IIC_VBIND, "vcge", "f32", v2i32, v2f32, 4248 NEONvcge, 0>; 4249def VCGEfq : N3VQ<1,0,0b00,0b1110,0, IIC_VBINQ, "vcge", "f32", v4i32, v4f32, 4250 NEONvcge, 0>; 4251 4252defm VCGEz : N2V_QHS_cmp<0b11, 0b11, 0b01, 0b00001, 0, "vcge", "s", 4253 "$Vd, $Vm, #0", NEONvcgez>; 4254defm VCLEz : N2V_QHS_cmp<0b11, 0b11, 0b01, 0b00011, 0, "vcle", "s", 4255 "$Vd, $Vm, #0", NEONvclez>; 4256 4257// VCGT : Vector Compare Greater Than 4258defm VCGTs : N3V_QHS<0, 0, 0b0011, 0, IIC_VSUBi4D, IIC_VSUBi4D, IIC_VSUBi4Q, 4259 IIC_VSUBi4Q, "vcgt", "s", NEONvcgt, 0>; 4260defm VCGTu : N3V_QHS<1, 0, 0b0011, 0, IIC_VSUBi4D, IIC_VSUBi4D, IIC_VSUBi4Q, 4261 IIC_VSUBi4Q, "vcgt", "u", NEONvcgtu, 0>; 4262def VCGTfd : N3VD<1,0,0b10,0b1110,0, IIC_VBIND, "vcgt", "f32", v2i32, v2f32, 4263 NEONvcgt, 0>; 4264def VCGTfq : N3VQ<1,0,0b10,0b1110,0, IIC_VBINQ, "vcgt", "f32", v4i32, v4f32, 4265 NEONvcgt, 0>; 4266 4267defm VCGTz : N2V_QHS_cmp<0b11, 0b11, 0b01, 0b00000, 0, "vcgt", "s", 4268 "$Vd, $Vm, #0", NEONvcgtz>; 4269defm VCLTz : N2V_QHS_cmp<0b11, 0b11, 0b01, 0b00100, 0, "vclt", "s", 4270 "$Vd, $Vm, #0", NEONvcltz>; 4271 4272// VACGE : Vector Absolute Compare Greater Than or Equal (aka VCAGE) 4273def VACGEd : N3VDInt<1, 0, 0b00, 0b1110, 1, N3RegFrm, IIC_VBIND, "vacge", 4274 "f32", v2i32, v2f32, int_arm_neon_vacged, 0>; 4275def VACGEq : N3VQInt<1, 0, 0b00, 0b1110, 1, N3RegFrm, IIC_VBINQ, "vacge", 4276 "f32", v4i32, v4f32, int_arm_neon_vacgeq, 0>; 4277// VACGT : Vector Absolute Compare Greater Than (aka VCAGT) 4278def VACGTd : N3VDInt<1, 0, 0b10, 0b1110, 1, N3RegFrm, IIC_VBIND, "vacgt", 4279 "f32", v2i32, v2f32, int_arm_neon_vacgtd, 0>; 4280def VACGTq : N3VQInt<1, 0, 0b10, 0b1110, 1, N3RegFrm, IIC_VBINQ, "vacgt", 4281 "f32", v4i32, v4f32, int_arm_neon_vacgtq, 0>; 4282// VTST : Vector Test Bits 4283defm VTST : N3V_QHS<0, 0, 0b1000, 1, IIC_VBINi4D, IIC_VBINi4D, IIC_VBINi4Q, 4284 IIC_VBINi4Q, "vtst", "", NEONvtst, 1>; 4285 4286// Vector Bitwise Operations. 4287 4288def vnotd : PatFrag<(ops node:$in), 4289 (xor node:$in, (bitconvert (v8i8 NEONimmAllOnesV)))>; 4290def vnotq : PatFrag<(ops node:$in), 4291 (xor node:$in, (bitconvert (v16i8 NEONimmAllOnesV)))>; 4292 4293 4294// VAND : Vector Bitwise AND 4295def VANDd : N3VDX<0, 0, 0b00, 0b0001, 1, IIC_VBINiD, "vand", 4296 v2i32, v2i32, and, 1>; 4297def VANDq : N3VQX<0, 0, 0b00, 0b0001, 1, IIC_VBINiQ, "vand", 4298 v4i32, v4i32, and, 1>; 4299 4300// VEOR : Vector Bitwise Exclusive OR 4301def VEORd : N3VDX<1, 0, 0b00, 0b0001, 1, IIC_VBINiD, "veor", 4302 v2i32, v2i32, xor, 1>; 4303def VEORq : N3VQX<1, 0, 0b00, 0b0001, 1, IIC_VBINiQ, "veor", 4304 v4i32, v4i32, xor, 1>; 4305 4306// VORR : Vector Bitwise OR 4307def VORRd : N3VDX<0, 0, 0b10, 0b0001, 1, IIC_VBINiD, "vorr", 4308 v2i32, v2i32, or, 1>; 4309def VORRq : N3VQX<0, 0, 0b10, 0b0001, 1, IIC_VBINiQ, "vorr", 4310 v4i32, v4i32, or, 1>; 4311 4312def VORRiv4i16 : N1ModImm<1, 0b000, {1,0,?,1}, 0, 0, 0, 1, 4313 (outs DPR:$Vd), (ins nImmSplatI16:$SIMM, DPR:$src), 4314 IIC_VMOVImm, 4315 "vorr", "i16", "$Vd, $SIMM", "$src = $Vd", 4316 [(set DPR:$Vd, 4317 (v4i16 (NEONvorrImm DPR:$src, timm:$SIMM)))]> { 4318 let Inst{9} = SIMM{9}; 4319} 4320 4321def VORRiv2i32 : N1ModImm<1, 0b000, {0,?,?,1}, 0, 0, 0, 1, 4322 (outs DPR:$Vd), (ins nImmSplatI32:$SIMM, DPR:$src), 4323 IIC_VMOVImm, 4324 "vorr", "i32", "$Vd, $SIMM", "$src = $Vd", 4325 [(set DPR:$Vd, 4326 (v2i32 (NEONvorrImm DPR:$src, timm:$SIMM)))]> { 4327 let Inst{10-9} = SIMM{10-9}; 4328} 4329 4330def VORRiv8i16 : N1ModImm<1, 0b000, {1,0,?,1}, 0, 1, 0, 1, 4331 (outs QPR:$Vd), (ins nImmSplatI16:$SIMM, QPR:$src), 4332 IIC_VMOVImm, 4333 "vorr", "i16", "$Vd, $SIMM", "$src = $Vd", 4334 [(set QPR:$Vd, 4335 (v8i16 (NEONvorrImm QPR:$src, timm:$SIMM)))]> { 4336 let Inst{9} = SIMM{9}; 4337} 4338 4339def VORRiv4i32 : N1ModImm<1, 0b000, {0,?,?,1}, 0, 1, 0, 1, 4340 (outs QPR:$Vd), (ins nImmSplatI32:$SIMM, QPR:$src), 4341 IIC_VMOVImm, 4342 "vorr", "i32", "$Vd, $SIMM", "$src = $Vd", 4343 [(set QPR:$Vd, 4344 (v4i32 (NEONvorrImm QPR:$src, timm:$SIMM)))]> { 4345 let Inst{10-9} = SIMM{10-9}; 4346} 4347 4348 4349// VBIC : Vector Bitwise Bit Clear (AND NOT) 4350def VBICd : N3VX<0, 0, 0b01, 0b0001, 0, 1, (outs DPR:$Vd), 4351 (ins DPR:$Vn, DPR:$Vm), N3RegFrm, IIC_VBINiD, 4352 "vbic", "$Vd, $Vn, $Vm", "", 4353 [(set DPR:$Vd, (v2i32 (and DPR:$Vn, 4354 (vnotd DPR:$Vm))))]>; 4355def VBICq : N3VX<0, 0, 0b01, 0b0001, 1, 1, (outs QPR:$Vd), 4356 (ins QPR:$Vn, QPR:$Vm), N3RegFrm, IIC_VBINiQ, 4357 "vbic", "$Vd, $Vn, $Vm", "", 4358 [(set QPR:$Vd, (v4i32 (and QPR:$Vn, 4359 (vnotq QPR:$Vm))))]>; 4360 4361def VBICiv4i16 : N1ModImm<1, 0b000, {1,0,?,1}, 0, 0, 1, 1, 4362 (outs DPR:$Vd), (ins nImmSplatI16:$SIMM, DPR:$src), 4363 IIC_VMOVImm, 4364 "vbic", "i16", "$Vd, $SIMM", "$src = $Vd", 4365 [(set DPR:$Vd, 4366 (v4i16 (NEONvbicImm DPR:$src, timm:$SIMM)))]> { 4367 let Inst{9} = SIMM{9}; 4368} 4369 4370def VBICiv2i32 : N1ModImm<1, 0b000, {0,?,?,1}, 0, 0, 1, 1, 4371 (outs DPR:$Vd), (ins nImmSplatI32:$SIMM, DPR:$src), 4372 IIC_VMOVImm, 4373 "vbic", "i32", "$Vd, $SIMM", "$src = $Vd", 4374 [(set DPR:$Vd, 4375 (v2i32 (NEONvbicImm DPR:$src, timm:$SIMM)))]> { 4376 let Inst{10-9} = SIMM{10-9}; 4377} 4378 4379def VBICiv8i16 : N1ModImm<1, 0b000, {1,0,?,1}, 0, 1, 1, 1, 4380 (outs QPR:$Vd), (ins nImmSplatI16:$SIMM, QPR:$src), 4381 IIC_VMOVImm, 4382 "vbic", "i16", "$Vd, $SIMM", "$src = $Vd", 4383 [(set QPR:$Vd, 4384 (v8i16 (NEONvbicImm QPR:$src, timm:$SIMM)))]> { 4385 let Inst{9} = SIMM{9}; 4386} 4387 4388def VBICiv4i32 : N1ModImm<1, 0b000, {0,?,?,1}, 0, 1, 1, 1, 4389 (outs QPR:$Vd), (ins nImmSplatI32:$SIMM, QPR:$src), 4390 IIC_VMOVImm, 4391 "vbic", "i32", "$Vd, $SIMM", "$src = $Vd", 4392 [(set QPR:$Vd, 4393 (v4i32 (NEONvbicImm QPR:$src, timm:$SIMM)))]> { 4394 let Inst{10-9} = SIMM{10-9}; 4395} 4396 4397// VORN : Vector Bitwise OR NOT 4398def VORNd : N3VX<0, 0, 0b11, 0b0001, 0, 1, (outs DPR:$Vd), 4399 (ins DPR:$Vn, DPR:$Vm), N3RegFrm, IIC_VBINiD, 4400 "vorn", "$Vd, $Vn, $Vm", "", 4401 [(set DPR:$Vd, (v2i32 (or DPR:$Vn, 4402 (vnotd DPR:$Vm))))]>; 4403def VORNq : N3VX<0, 0, 0b11, 0b0001, 1, 1, (outs QPR:$Vd), 4404 (ins QPR:$Vn, QPR:$Vm), N3RegFrm, IIC_VBINiQ, 4405 "vorn", "$Vd, $Vn, $Vm", "", 4406 [(set QPR:$Vd, (v4i32 (or QPR:$Vn, 4407 (vnotq QPR:$Vm))))]>; 4408 4409// VMVN : Vector Bitwise NOT (Immediate) 4410 4411let isReMaterializable = 1 in { 4412 4413def VMVNv4i16 : N1ModImm<1, 0b000, {1,0,?,0}, 0, 0, 1, 1, (outs DPR:$Vd), 4414 (ins nImmSplatI16:$SIMM), IIC_VMOVImm, 4415 "vmvn", "i16", "$Vd, $SIMM", "", 4416 [(set DPR:$Vd, (v4i16 (NEONvmvnImm timm:$SIMM)))]> { 4417 let Inst{9} = SIMM{9}; 4418} 4419 4420def VMVNv8i16 : N1ModImm<1, 0b000, {1,0,?,0}, 0, 1, 1, 1, (outs QPR:$Vd), 4421 (ins nImmSplatI16:$SIMM), IIC_VMOVImm, 4422 "vmvn", "i16", "$Vd, $SIMM", "", 4423 [(set QPR:$Vd, (v8i16 (NEONvmvnImm timm:$SIMM)))]> { 4424 let Inst{9} = SIMM{9}; 4425} 4426 4427def VMVNv2i32 : N1ModImm<1, 0b000, {?,?,?,?}, 0, 0, 1, 1, (outs DPR:$Vd), 4428 (ins nImmVMOVI32:$SIMM), IIC_VMOVImm, 4429 "vmvn", "i32", "$Vd, $SIMM", "", 4430 [(set DPR:$Vd, (v2i32 (NEONvmvnImm timm:$SIMM)))]> { 4431 let Inst{11-8} = SIMM{11-8}; 4432} 4433 4434def VMVNv4i32 : N1ModImm<1, 0b000, {?,?,?,?}, 0, 1, 1, 1, (outs QPR:$Vd), 4435 (ins nImmVMOVI32:$SIMM), IIC_VMOVImm, 4436 "vmvn", "i32", "$Vd, $SIMM", "", 4437 [(set QPR:$Vd, (v4i32 (NEONvmvnImm timm:$SIMM)))]> { 4438 let Inst{11-8} = SIMM{11-8}; 4439} 4440} 4441 4442// VMVN : Vector Bitwise NOT 4443def VMVNd : N2VX<0b11, 0b11, 0b00, 0b00, 0b01011, 0, 0, 4444 (outs DPR:$Vd), (ins DPR:$Vm), IIC_VSUBiD, 4445 "vmvn", "$Vd, $Vm", "", 4446 [(set DPR:$Vd, (v2i32 (vnotd DPR:$Vm)))]>; 4447def VMVNq : N2VX<0b11, 0b11, 0b00, 0b00, 0b01011, 1, 0, 4448 (outs QPR:$Vd), (ins QPR:$Vm), IIC_VSUBiD, 4449 "vmvn", "$Vd, $Vm", "", 4450 [(set QPR:$Vd, (v4i32 (vnotq QPR:$Vm)))]>; 4451def : Pat<(v2i32 (vnotd DPR:$src)), (VMVNd DPR:$src)>; 4452def : Pat<(v4i32 (vnotq QPR:$src)), (VMVNq QPR:$src)>; 4453 4454// VBSL : Vector Bitwise Select 4455def VBSLd : N3VX<1, 0, 0b01, 0b0001, 0, 1, (outs DPR:$Vd), 4456 (ins DPR:$src1, DPR:$Vn, DPR:$Vm), 4457 N3RegFrm, IIC_VCNTiD, 4458 "vbsl", "$Vd, $Vn, $Vm", "$src1 = $Vd", 4459 [(set DPR:$Vd, 4460 (v2i32 (NEONvbsl DPR:$src1, DPR:$Vn, DPR:$Vm)))]>; 4461 4462def : Pat<(v2i32 (or (and DPR:$Vn, DPR:$Vd), 4463 (and DPR:$Vm, (vnotd DPR:$Vd)))), 4464 (VBSLd DPR:$Vd, DPR:$Vn, DPR:$Vm)>; 4465 4466def VBSLq : N3VX<1, 0, 0b01, 0b0001, 1, 1, (outs QPR:$Vd), 4467 (ins QPR:$src1, QPR:$Vn, QPR:$Vm), 4468 N3RegFrm, IIC_VCNTiQ, 4469 "vbsl", "$Vd, $Vn, $Vm", "$src1 = $Vd", 4470 [(set QPR:$Vd, 4471 (v4i32 (NEONvbsl QPR:$src1, QPR:$Vn, QPR:$Vm)))]>; 4472 4473def : Pat<(v4i32 (or (and QPR:$Vn, QPR:$Vd), 4474 (and QPR:$Vm, (vnotq QPR:$Vd)))), 4475 (VBSLq QPR:$Vd, QPR:$Vn, QPR:$Vm)>; 4476 4477// VBIF : Vector Bitwise Insert if False 4478// like VBSL but with: "vbif $dst, $src3, $src1", "$src2 = $dst", 4479// FIXME: This instruction's encoding MAY NOT BE correct. 4480def VBIFd : N3VX<1, 0, 0b11, 0b0001, 0, 1, 4481 (outs DPR:$Vd), (ins DPR:$src1, DPR:$Vn, DPR:$Vm), 4482 N3RegFrm, IIC_VBINiD, 4483 "vbif", "$Vd, $Vn, $Vm", "$src1 = $Vd", 4484 []>; 4485def VBIFq : N3VX<1, 0, 0b11, 0b0001, 1, 1, 4486 (outs QPR:$Vd), (ins QPR:$src1, QPR:$Vn, QPR:$Vm), 4487 N3RegFrm, IIC_VBINiQ, 4488 "vbif", "$Vd, $Vn, $Vm", "$src1 = $Vd", 4489 []>; 4490 4491// VBIT : Vector Bitwise Insert if True 4492// like VBSL but with: "vbit $dst, $src2, $src1", "$src3 = $dst", 4493// FIXME: This instruction's encoding MAY NOT BE correct. 4494def VBITd : N3VX<1, 0, 0b10, 0b0001, 0, 1, 4495 (outs DPR:$Vd), (ins DPR:$src1, DPR:$Vn, DPR:$Vm), 4496 N3RegFrm, IIC_VBINiD, 4497 "vbit", "$Vd, $Vn, $Vm", "$src1 = $Vd", 4498 []>; 4499def VBITq : N3VX<1, 0, 0b10, 0b0001, 1, 1, 4500 (outs QPR:$Vd), (ins QPR:$src1, QPR:$Vn, QPR:$Vm), 4501 N3RegFrm, IIC_VBINiQ, 4502 "vbit", "$Vd, $Vn, $Vm", "$src1 = $Vd", 4503 []>; 4504 4505// VBIT/VBIF are not yet implemented. The TwoAddress pass will not go looking 4506// for equivalent operations with different register constraints; it just 4507// inserts copies. 4508 4509// Vector Absolute Differences. 4510 4511// VABD : Vector Absolute Difference 4512defm VABDs : N3VInt_QHS<0, 0, 0b0111, 0, N3RegFrm, 4513 IIC_VSUBi4D, IIC_VSUBi4D, IIC_VSUBi4Q, IIC_VSUBi4Q, 4514 "vabd", "s", int_arm_neon_vabds, 1>; 4515defm VABDu : N3VInt_QHS<1, 0, 0b0111, 0, N3RegFrm, 4516 IIC_VSUBi4D, IIC_VSUBi4D, IIC_VSUBi4Q, IIC_VSUBi4Q, 4517 "vabd", "u", int_arm_neon_vabdu, 1>; 4518def VABDfd : N3VDInt<1, 0, 0b10, 0b1101, 0, N3RegFrm, IIC_VBIND, 4519 "vabd", "f32", v2f32, v2f32, int_arm_neon_vabds, 1>; 4520def VABDfq : N3VQInt<1, 0, 0b10, 0b1101, 0, N3RegFrm, IIC_VBINQ, 4521 "vabd", "f32", v4f32, v4f32, int_arm_neon_vabds, 1>; 4522 4523// VABDL : Vector Absolute Difference Long (Q = | D - D |) 4524defm VABDLs : N3VLIntExt_QHS<0,1,0b0111,0, IIC_VSUBi4Q, 4525 "vabdl", "s", int_arm_neon_vabds, zext, 1>; 4526defm VABDLu : N3VLIntExt_QHS<1,1,0b0111,0, IIC_VSUBi4Q, 4527 "vabdl", "u", int_arm_neon_vabdu, zext, 1>; 4528 4529// VABA : Vector Absolute Difference and Accumulate 4530defm VABAs : N3VIntOp_QHS<0,0,0b0111,1, IIC_VABAD, IIC_VABAQ, 4531 "vaba", "s", int_arm_neon_vabds, add>; 4532defm VABAu : N3VIntOp_QHS<1,0,0b0111,1, IIC_VABAD, IIC_VABAQ, 4533 "vaba", "u", int_arm_neon_vabdu, add>; 4534 4535// VABAL : Vector Absolute Difference and Accumulate Long (Q += | D - D |) 4536defm VABALs : N3VLIntExtOp_QHS<0,1,0b0101,0, IIC_VABAD, 4537 "vabal", "s", int_arm_neon_vabds, zext, add>; 4538defm VABALu : N3VLIntExtOp_QHS<1,1,0b0101,0, IIC_VABAD, 4539 "vabal", "u", int_arm_neon_vabdu, zext, add>; 4540 4541// Vector Maximum and Minimum. 4542 4543// VMAX : Vector Maximum 4544defm VMAXs : N3VInt_QHS<0, 0, 0b0110, 0, N3RegFrm, 4545 IIC_VSUBi4D, IIC_VSUBi4D, IIC_VSUBi4Q, IIC_VSUBi4Q, 4546 "vmax", "s", int_arm_neon_vmaxs, 1>; 4547defm VMAXu : N3VInt_QHS<1, 0, 0b0110, 0, N3RegFrm, 4548 IIC_VSUBi4D, IIC_VSUBi4D, IIC_VSUBi4Q, IIC_VSUBi4Q, 4549 "vmax", "u", int_arm_neon_vmaxu, 1>; 4550def VMAXfd : N3VDInt<0, 0, 0b00, 0b1111, 0, N3RegFrm, IIC_VBIND, 4551 "vmax", "f32", 4552 v2f32, v2f32, int_arm_neon_vmaxs, 1>; 4553def VMAXfq : N3VQInt<0, 0, 0b00, 0b1111, 0, N3RegFrm, IIC_VBINQ, 4554 "vmax", "f32", 4555 v4f32, v4f32, int_arm_neon_vmaxs, 1>; 4556 4557// VMIN : Vector Minimum 4558defm VMINs : N3VInt_QHS<0, 0, 0b0110, 1, N3RegFrm, 4559 IIC_VSUBi4D, IIC_VSUBi4D, IIC_VSUBi4Q, IIC_VSUBi4Q, 4560 "vmin", "s", int_arm_neon_vmins, 1>; 4561defm VMINu : N3VInt_QHS<1, 0, 0b0110, 1, N3RegFrm, 4562 IIC_VSUBi4D, IIC_VSUBi4D, IIC_VSUBi4Q, IIC_VSUBi4Q, 4563 "vmin", "u", int_arm_neon_vminu, 1>; 4564def VMINfd : N3VDInt<0, 0, 0b10, 0b1111, 0, N3RegFrm, IIC_VBIND, 4565 "vmin", "f32", 4566 v2f32, v2f32, int_arm_neon_vmins, 1>; 4567def VMINfq : N3VQInt<0, 0, 0b10, 0b1111, 0, N3RegFrm, IIC_VBINQ, 4568 "vmin", "f32", 4569 v4f32, v4f32, int_arm_neon_vmins, 1>; 4570 4571// Vector Pairwise Operations. 4572 4573// VPADD : Vector Pairwise Add 4574def VPADDi8 : N3VDInt<0, 0, 0b00, 0b1011, 1, N3RegFrm, IIC_VSHLiD, 4575 "vpadd", "i8", 4576 v8i8, v8i8, int_arm_neon_vpadd, 0>; 4577def VPADDi16 : N3VDInt<0, 0, 0b01, 0b1011, 1, N3RegFrm, IIC_VSHLiD, 4578 "vpadd", "i16", 4579 v4i16, v4i16, int_arm_neon_vpadd, 0>; 4580def VPADDi32 : N3VDInt<0, 0, 0b10, 0b1011, 1, N3RegFrm, IIC_VSHLiD, 4581 "vpadd", "i32", 4582 v2i32, v2i32, int_arm_neon_vpadd, 0>; 4583def VPADDf : N3VDInt<1, 0, 0b00, 0b1101, 0, N3RegFrm, 4584 IIC_VPBIND, "vpadd", "f32", 4585 v2f32, v2f32, int_arm_neon_vpadd, 0>; 4586 4587// VPADDL : Vector Pairwise Add Long 4588defm VPADDLs : N2VPLInt_QHS<0b11, 0b11, 0b00, 0b00100, 0, "vpaddl", "s", 4589 int_arm_neon_vpaddls>; 4590defm VPADDLu : N2VPLInt_QHS<0b11, 0b11, 0b00, 0b00101, 0, "vpaddl", "u", 4591 int_arm_neon_vpaddlu>; 4592 4593// VPADAL : Vector Pairwise Add and Accumulate Long 4594defm VPADALs : N2VPLInt2_QHS<0b11, 0b11, 0b00, 0b01100, 0, "vpadal", "s", 4595 int_arm_neon_vpadals>; 4596defm VPADALu : N2VPLInt2_QHS<0b11, 0b11, 0b00, 0b01101, 0, "vpadal", "u", 4597 int_arm_neon_vpadalu>; 4598 4599// VPMAX : Vector Pairwise Maximum 4600def VPMAXs8 : N3VDInt<0, 0, 0b00, 0b1010, 0, N3RegFrm, IIC_VSUBi4D, "vpmax", 4601 "s8", v8i8, v8i8, int_arm_neon_vpmaxs, 0>; 4602def VPMAXs16 : N3VDInt<0, 0, 0b01, 0b1010, 0, N3RegFrm, IIC_VSUBi4D, "vpmax", 4603 "s16", v4i16, v4i16, int_arm_neon_vpmaxs, 0>; 4604def VPMAXs32 : N3VDInt<0, 0, 0b10, 0b1010, 0, N3RegFrm, IIC_VSUBi4D, "vpmax", 4605 "s32", v2i32, v2i32, int_arm_neon_vpmaxs, 0>; 4606def VPMAXu8 : N3VDInt<1, 0, 0b00, 0b1010, 0, N3RegFrm, IIC_VSUBi4D, "vpmax", 4607 "u8", v8i8, v8i8, int_arm_neon_vpmaxu, 0>; 4608def VPMAXu16 : N3VDInt<1, 0, 0b01, 0b1010, 0, N3RegFrm, IIC_VSUBi4D, "vpmax", 4609 "u16", v4i16, v4i16, int_arm_neon_vpmaxu, 0>; 4610def VPMAXu32 : N3VDInt<1, 0, 0b10, 0b1010, 0, N3RegFrm, IIC_VSUBi4D, "vpmax", 4611 "u32", v2i32, v2i32, int_arm_neon_vpmaxu, 0>; 4612def VPMAXf : N3VDInt<1, 0, 0b00, 0b1111, 0, N3RegFrm, IIC_VPBIND, "vpmax", 4613 "f32", v2f32, v2f32, int_arm_neon_vpmaxs, 0>; 4614 4615// VPMIN : Vector Pairwise Minimum 4616def VPMINs8 : N3VDInt<0, 0, 0b00, 0b1010, 1, N3RegFrm, IIC_VSUBi4D, "vpmin", 4617 "s8", v8i8, v8i8, int_arm_neon_vpmins, 0>; 4618def VPMINs16 : N3VDInt<0, 0, 0b01, 0b1010, 1, N3RegFrm, IIC_VSUBi4D, "vpmin", 4619 "s16", v4i16, v4i16, int_arm_neon_vpmins, 0>; 4620def VPMINs32 : N3VDInt<0, 0, 0b10, 0b1010, 1, N3RegFrm, IIC_VSUBi4D, "vpmin", 4621 "s32", v2i32, v2i32, int_arm_neon_vpmins, 0>; 4622def VPMINu8 : N3VDInt<1, 0, 0b00, 0b1010, 1, N3RegFrm, IIC_VSUBi4D, "vpmin", 4623 "u8", v8i8, v8i8, int_arm_neon_vpminu, 0>; 4624def VPMINu16 : N3VDInt<1, 0, 0b01, 0b1010, 1, N3RegFrm, IIC_VSUBi4D, "vpmin", 4625 "u16", v4i16, v4i16, int_arm_neon_vpminu, 0>; 4626def VPMINu32 : N3VDInt<1, 0, 0b10, 0b1010, 1, N3RegFrm, IIC_VSUBi4D, "vpmin", 4627 "u32", v2i32, v2i32, int_arm_neon_vpminu, 0>; 4628def VPMINf : N3VDInt<1, 0, 0b10, 0b1111, 0, N3RegFrm, IIC_VPBIND, "vpmin", 4629 "f32", v2f32, v2f32, int_arm_neon_vpmins, 0>; 4630 4631// Vector Reciprocal and Reciprocal Square Root Estimate and Step. 4632 4633// VRECPE : Vector Reciprocal Estimate 4634def VRECPEd : N2VDInt<0b11, 0b11, 0b10, 0b11, 0b01000, 0, 4635 IIC_VUNAD, "vrecpe", "u32", 4636 v2i32, v2i32, int_arm_neon_vrecpe>; 4637def VRECPEq : N2VQInt<0b11, 0b11, 0b10, 0b11, 0b01000, 0, 4638 IIC_VUNAQ, "vrecpe", "u32", 4639 v4i32, v4i32, int_arm_neon_vrecpe>; 4640def VRECPEfd : N2VDInt<0b11, 0b11, 0b10, 0b11, 0b01010, 0, 4641 IIC_VUNAD, "vrecpe", "f32", 4642 v2f32, v2f32, int_arm_neon_vrecpe>; 4643def VRECPEfq : N2VQInt<0b11, 0b11, 0b10, 0b11, 0b01010, 0, 4644 IIC_VUNAQ, "vrecpe", "f32", 4645 v4f32, v4f32, int_arm_neon_vrecpe>; 4646 4647// VRECPS : Vector Reciprocal Step 4648def VRECPSfd : N3VDInt<0, 0, 0b00, 0b1111, 1, N3RegFrm, 4649 IIC_VRECSD, "vrecps", "f32", 4650 v2f32, v2f32, int_arm_neon_vrecps, 1>; 4651def VRECPSfq : N3VQInt<0, 0, 0b00, 0b1111, 1, N3RegFrm, 4652 IIC_VRECSQ, "vrecps", "f32", 4653 v4f32, v4f32, int_arm_neon_vrecps, 1>; 4654 4655// VRSQRTE : Vector Reciprocal Square Root Estimate 4656def VRSQRTEd : N2VDInt<0b11, 0b11, 0b10, 0b11, 0b01001, 0, 4657 IIC_VUNAD, "vrsqrte", "u32", 4658 v2i32, v2i32, int_arm_neon_vrsqrte>; 4659def VRSQRTEq : N2VQInt<0b11, 0b11, 0b10, 0b11, 0b01001, 0, 4660 IIC_VUNAQ, "vrsqrte", "u32", 4661 v4i32, v4i32, int_arm_neon_vrsqrte>; 4662def VRSQRTEfd : N2VDInt<0b11, 0b11, 0b10, 0b11, 0b01011, 0, 4663 IIC_VUNAD, "vrsqrte", "f32", 4664 v2f32, v2f32, int_arm_neon_vrsqrte>; 4665def VRSQRTEfq : N2VQInt<0b11, 0b11, 0b10, 0b11, 0b01011, 0, 4666 IIC_VUNAQ, "vrsqrte", "f32", 4667 v4f32, v4f32, int_arm_neon_vrsqrte>; 4668 4669// VRSQRTS : Vector Reciprocal Square Root Step 4670def VRSQRTSfd : N3VDInt<0, 0, 0b10, 0b1111, 1, N3RegFrm, 4671 IIC_VRECSD, "vrsqrts", "f32", 4672 v2f32, v2f32, int_arm_neon_vrsqrts, 1>; 4673def VRSQRTSfq : N3VQInt<0, 0, 0b10, 0b1111, 1, N3RegFrm, 4674 IIC_VRECSQ, "vrsqrts", "f32", 4675 v4f32, v4f32, int_arm_neon_vrsqrts, 1>; 4676 4677// Vector Shifts. 4678 4679// VSHL : Vector Shift 4680defm VSHLs : N3VInt_QHSDSh<0, 0, 0b0100, 0, N3RegVShFrm, 4681 IIC_VSHLiD, IIC_VSHLiD, IIC_VSHLiQ, IIC_VSHLiQ, 4682 "vshl", "s", int_arm_neon_vshifts>; 4683defm VSHLu : N3VInt_QHSDSh<1, 0, 0b0100, 0, N3RegVShFrm, 4684 IIC_VSHLiD, IIC_VSHLiD, IIC_VSHLiQ, IIC_VSHLiQ, 4685 "vshl", "u", int_arm_neon_vshiftu>; 4686 4687// VSHL : Vector Shift Left (Immediate) 4688defm VSHLi : N2VShL_QHSD<0, 1, 0b0101, 1, IIC_VSHLiD, "vshl", "i", NEONvshl>; 4689 4690// VSHR : Vector Shift Right (Immediate) 4691defm VSHRs : N2VShR_QHSD<0, 1, 0b0000, 1, IIC_VSHLiD, "vshr", "s",NEONvshrs>; 4692defm VSHRu : N2VShR_QHSD<1, 1, 0b0000, 1, IIC_VSHLiD, "vshr", "u",NEONvshru>; 4693 4694// VSHLL : Vector Shift Left Long 4695defm VSHLLs : N2VLSh_QHS<0, 1, 0b1010, 0, 0, 1, "vshll", "s", NEONvshlls>; 4696defm VSHLLu : N2VLSh_QHS<1, 1, 0b1010, 0, 0, 1, "vshll", "u", NEONvshllu>; 4697 4698// VSHLL : Vector Shift Left Long (with maximum shift count) 4699class N2VLShMax<bit op24, bit op23, bits<6> op21_16, bits<4> op11_8, bit op7, 4700 bit op6, bit op4, string OpcodeStr, string Dt, ValueType ResTy, 4701 ValueType OpTy, Operand ImmTy, SDNode OpNode> 4702 : N2VLSh<op24, op23, op11_8, op7, op6, op4, OpcodeStr, Dt, 4703 ResTy, OpTy, ImmTy, OpNode> { 4704 let Inst{21-16} = op21_16; 4705 let DecoderMethod = "DecodeVSHLMaxInstruction"; 4706} 4707def VSHLLi8 : N2VLShMax<1, 1, 0b110010, 0b0011, 0, 0, 0, "vshll", "i8", 4708 v8i16, v8i8, imm8, NEONvshlli>; 4709def VSHLLi16 : N2VLShMax<1, 1, 0b110110, 0b0011, 0, 0, 0, "vshll", "i16", 4710 v4i32, v4i16, imm16, NEONvshlli>; 4711def VSHLLi32 : N2VLShMax<1, 1, 0b111010, 0b0011, 0, 0, 0, "vshll", "i32", 4712 v2i64, v2i32, imm32, NEONvshlli>; 4713 4714// VSHRN : Vector Shift Right and Narrow 4715defm VSHRN : N2VNSh_HSD<0,1,0b1000,0,0,1, IIC_VSHLiD, "vshrn", "i", 4716 NEONvshrn>; 4717 4718// VRSHL : Vector Rounding Shift 4719defm VRSHLs : N3VInt_QHSDSh<0, 0, 0b0101, 0, N3RegVShFrm, 4720 IIC_VSHLi4D, IIC_VSHLi4D, IIC_VSHLi4Q, IIC_VSHLi4Q, 4721 "vrshl", "s", int_arm_neon_vrshifts>; 4722defm VRSHLu : N3VInt_QHSDSh<1, 0, 0b0101, 0, N3RegVShFrm, 4723 IIC_VSHLi4D, IIC_VSHLi4D, IIC_VSHLi4Q, IIC_VSHLi4Q, 4724 "vrshl", "u", int_arm_neon_vrshiftu>; 4725// VRSHR : Vector Rounding Shift Right 4726defm VRSHRs : N2VShR_QHSD<0,1,0b0010,1, IIC_VSHLi4D, "vrshr", "s",NEONvrshrs>; 4727defm VRSHRu : N2VShR_QHSD<1,1,0b0010,1, IIC_VSHLi4D, "vrshr", "u",NEONvrshru>; 4728 4729// VRSHRN : Vector Rounding Shift Right and Narrow 4730defm VRSHRN : N2VNSh_HSD<0, 1, 0b1000, 0, 1, 1, IIC_VSHLi4D, "vrshrn", "i", 4731 NEONvrshrn>; 4732 4733// VQSHL : Vector Saturating Shift 4734defm VQSHLs : N3VInt_QHSDSh<0, 0, 0b0100, 1, N3RegVShFrm, 4735 IIC_VSHLi4D, IIC_VSHLi4D, IIC_VSHLi4Q, IIC_VSHLi4Q, 4736 "vqshl", "s", int_arm_neon_vqshifts>; 4737defm VQSHLu : N3VInt_QHSDSh<1, 0, 0b0100, 1, N3RegVShFrm, 4738 IIC_VSHLi4D, IIC_VSHLi4D, IIC_VSHLi4Q, IIC_VSHLi4Q, 4739 "vqshl", "u", int_arm_neon_vqshiftu>; 4740// VQSHL : Vector Saturating Shift Left (Immediate) 4741defm VQSHLsi : N2VShL_QHSD<0,1,0b0111,1, IIC_VSHLi4D, "vqshl", "s",NEONvqshls>; 4742defm VQSHLui : N2VShL_QHSD<1,1,0b0111,1, IIC_VSHLi4D, "vqshl", "u",NEONvqshlu>; 4743 4744// VQSHLU : Vector Saturating Shift Left (Immediate, Unsigned) 4745defm VQSHLsu : N2VShL_QHSD<1,1,0b0110,1, IIC_VSHLi4D,"vqshlu","s",NEONvqshlsu>; 4746 4747// VQSHRN : Vector Saturating Shift Right and Narrow 4748defm VQSHRNs : N2VNSh_HSD<0, 1, 0b1001, 0, 0, 1, IIC_VSHLi4D, "vqshrn", "s", 4749 NEONvqshrns>; 4750defm VQSHRNu : N2VNSh_HSD<1, 1, 0b1001, 0, 0, 1, IIC_VSHLi4D, "vqshrn", "u", 4751 NEONvqshrnu>; 4752 4753// VQSHRUN : Vector Saturating Shift Right and Narrow (Unsigned) 4754defm VQSHRUN : N2VNSh_HSD<1, 1, 0b1000, 0, 0, 1, IIC_VSHLi4D, "vqshrun", "s", 4755 NEONvqshrnsu>; 4756 4757// VQRSHL : Vector Saturating Rounding Shift 4758defm VQRSHLs : N3VInt_QHSDSh<0, 0, 0b0101, 1, N3RegVShFrm, 4759 IIC_VSHLi4D, IIC_VSHLi4D, IIC_VSHLi4Q, IIC_VSHLi4Q, 4760 "vqrshl", "s", int_arm_neon_vqrshifts>; 4761defm VQRSHLu : N3VInt_QHSDSh<1, 0, 0b0101, 1, N3RegVShFrm, 4762 IIC_VSHLi4D, IIC_VSHLi4D, IIC_VSHLi4Q, IIC_VSHLi4Q, 4763 "vqrshl", "u", int_arm_neon_vqrshiftu>; 4764 4765// VQRSHRN : Vector Saturating Rounding Shift Right and Narrow 4766defm VQRSHRNs : N2VNSh_HSD<0, 1, 0b1001, 0, 1, 1, IIC_VSHLi4D, "vqrshrn", "s", 4767 NEONvqrshrns>; 4768defm VQRSHRNu : N2VNSh_HSD<1, 1, 0b1001, 0, 1, 1, IIC_VSHLi4D, "vqrshrn", "u", 4769 NEONvqrshrnu>; 4770 4771// VQRSHRUN : Vector Saturating Rounding Shift Right and Narrow (Unsigned) 4772defm VQRSHRUN : N2VNSh_HSD<1, 1, 0b1000, 0, 1, 1, IIC_VSHLi4D, "vqrshrun", "s", 4773 NEONvqrshrnsu>; 4774 4775// VSRA : Vector Shift Right and Accumulate 4776defm VSRAs : N2VShAdd_QHSD<0, 1, 0b0001, 1, "vsra", "s", NEONvshrs>; 4777defm VSRAu : N2VShAdd_QHSD<1, 1, 0b0001, 1, "vsra", "u", NEONvshru>; 4778// VRSRA : Vector Rounding Shift Right and Accumulate 4779defm VRSRAs : N2VShAdd_QHSD<0, 1, 0b0011, 1, "vrsra", "s", NEONvrshrs>; 4780defm VRSRAu : N2VShAdd_QHSD<1, 1, 0b0011, 1, "vrsra", "u", NEONvrshru>; 4781 4782// VSLI : Vector Shift Left and Insert 4783defm VSLI : N2VShInsL_QHSD<1, 1, 0b0101, 1, "vsli">; 4784 4785// VSRI : Vector Shift Right and Insert 4786defm VSRI : N2VShInsR_QHSD<1, 1, 0b0100, 1, "vsri">; 4787 4788// Vector Absolute and Saturating Absolute. 4789 4790// VABS : Vector Absolute Value 4791defm VABS : N2VInt_QHS<0b11, 0b11, 0b01, 0b00110, 0, 4792 IIC_VUNAiD, IIC_VUNAiQ, "vabs", "s", 4793 int_arm_neon_vabs>; 4794def VABSfd : N2VDInt<0b11, 0b11, 0b10, 0b01, 0b01110, 0, 4795 IIC_VUNAD, "vabs", "f32", 4796 v2f32, v2f32, int_arm_neon_vabs>; 4797def VABSfq : N2VQInt<0b11, 0b11, 0b10, 0b01, 0b01110, 0, 4798 IIC_VUNAQ, "vabs", "f32", 4799 v4f32, v4f32, int_arm_neon_vabs>; 4800 4801// VQABS : Vector Saturating Absolute Value 4802defm VQABS : N2VInt_QHS<0b11, 0b11, 0b00, 0b01110, 0, 4803 IIC_VQUNAiD, IIC_VQUNAiQ, "vqabs", "s", 4804 int_arm_neon_vqabs>; 4805 4806// Vector Negate. 4807 4808def vnegd : PatFrag<(ops node:$in), 4809 (sub (bitconvert (v2i32 NEONimmAllZerosV)), node:$in)>; 4810def vnegq : PatFrag<(ops node:$in), 4811 (sub (bitconvert (v4i32 NEONimmAllZerosV)), node:$in)>; 4812 4813class VNEGD<bits<2> size, string OpcodeStr, string Dt, ValueType Ty> 4814 : N2V<0b11, 0b11, size, 0b01, 0b00111, 0, 0, (outs DPR:$Vd), (ins DPR:$Vm), 4815 IIC_VSHLiD, OpcodeStr, Dt, "$Vd, $Vm", "", 4816 [(set DPR:$Vd, (Ty (vnegd DPR:$Vm)))]>; 4817class VNEGQ<bits<2> size, string OpcodeStr, string Dt, ValueType Ty> 4818 : N2V<0b11, 0b11, size, 0b01, 0b00111, 1, 0, (outs QPR:$Vd), (ins QPR:$Vm), 4819 IIC_VSHLiQ, OpcodeStr, Dt, "$Vd, $Vm", "", 4820 [(set QPR:$Vd, (Ty (vnegq QPR:$Vm)))]>; 4821 4822// VNEG : Vector Negate (integer) 4823def VNEGs8d : VNEGD<0b00, "vneg", "s8", v8i8>; 4824def VNEGs16d : VNEGD<0b01, "vneg", "s16", v4i16>; 4825def VNEGs32d : VNEGD<0b10, "vneg", "s32", v2i32>; 4826def VNEGs8q : VNEGQ<0b00, "vneg", "s8", v16i8>; 4827def VNEGs16q : VNEGQ<0b01, "vneg", "s16", v8i16>; 4828def VNEGs32q : VNEGQ<0b10, "vneg", "s32", v4i32>; 4829 4830// VNEG : Vector Negate (floating-point) 4831def VNEGfd : N2V<0b11, 0b11, 0b10, 0b01, 0b01111, 0, 0, 4832 (outs DPR:$Vd), (ins DPR:$Vm), IIC_VUNAD, 4833 "vneg", "f32", "$Vd, $Vm", "", 4834 [(set DPR:$Vd, (v2f32 (fneg DPR:$Vm)))]>; 4835def VNEGf32q : N2V<0b11, 0b11, 0b10, 0b01, 0b01111, 1, 0, 4836 (outs QPR:$Vd), (ins QPR:$Vm), IIC_VUNAQ, 4837 "vneg", "f32", "$Vd, $Vm", "", 4838 [(set QPR:$Vd, (v4f32 (fneg QPR:$Vm)))]>; 4839 4840def : Pat<(v8i8 (vnegd DPR:$src)), (VNEGs8d DPR:$src)>; 4841def : Pat<(v4i16 (vnegd DPR:$src)), (VNEGs16d DPR:$src)>; 4842def : Pat<(v2i32 (vnegd DPR:$src)), (VNEGs32d DPR:$src)>; 4843def : Pat<(v16i8 (vnegq QPR:$src)), (VNEGs8q QPR:$src)>; 4844def : Pat<(v8i16 (vnegq QPR:$src)), (VNEGs16q QPR:$src)>; 4845def : Pat<(v4i32 (vnegq QPR:$src)), (VNEGs32q QPR:$src)>; 4846 4847// VQNEG : Vector Saturating Negate 4848defm VQNEG : N2VInt_QHS<0b11, 0b11, 0b00, 0b01111, 0, 4849 IIC_VQUNAiD, IIC_VQUNAiQ, "vqneg", "s", 4850 int_arm_neon_vqneg>; 4851 4852// Vector Bit Counting Operations. 4853 4854// VCLS : Vector Count Leading Sign Bits 4855defm VCLS : N2VInt_QHS<0b11, 0b11, 0b00, 0b01000, 0, 4856 IIC_VCNTiD, IIC_VCNTiQ, "vcls", "s", 4857 int_arm_neon_vcls>; 4858// VCLZ : Vector Count Leading Zeros 4859defm VCLZ : N2VInt_QHS<0b11, 0b11, 0b00, 0b01001, 0, 4860 IIC_VCNTiD, IIC_VCNTiQ, "vclz", "i", 4861 int_arm_neon_vclz>; 4862// VCNT : Vector Count One Bits 4863def VCNTd : N2VDInt<0b11, 0b11, 0b00, 0b00, 0b01010, 0, 4864 IIC_VCNTiD, "vcnt", "8", 4865 v8i8, v8i8, int_arm_neon_vcnt>; 4866def VCNTq : N2VQInt<0b11, 0b11, 0b00, 0b00, 0b01010, 0, 4867 IIC_VCNTiQ, "vcnt", "8", 4868 v16i8, v16i8, int_arm_neon_vcnt>; 4869 4870// Vector Swap 4871def VSWPd : N2VX<0b11, 0b11, 0b00, 0b10, 0b00000, 0, 0, 4872 (outs DPR:$Vd, DPR:$Vd1), (ins DPR:$Vm, DPR:$Vm1), 4873 NoItinerary, "vswp", "$Vd, $Vd1", "$Vm = $Vd, $Vm1 = $Vd1", 4874 []>; 4875def VSWPq : N2VX<0b11, 0b11, 0b00, 0b10, 0b00000, 1, 0, 4876 (outs QPR:$Vd, QPR:$Vd1), (ins QPR:$Vm, QPR:$Vm1), 4877 NoItinerary, "vswp", "$Vd, $Vd1", "$Vm = $Vd, $Vm1 = $Vd1", 4878 []>; 4879 4880// Vector Move Operations. 4881 4882// VMOV : Vector Move (Register) 4883def : InstAlias<"vmov${p} $Vd, $Vm", 4884 (VORRd DPR:$Vd, DPR:$Vm, DPR:$Vm, pred:$p)>; 4885def : InstAlias<"vmov${p} $Vd, $Vm", 4886 (VORRq QPR:$Vd, QPR:$Vm, QPR:$Vm, pred:$p)>; 4887 4888// VMOV : Vector Move (Immediate) 4889 4890let isReMaterializable = 1 in { 4891def VMOVv8i8 : N1ModImm<1, 0b000, 0b1110, 0, 0, 0, 1, (outs DPR:$Vd), 4892 (ins nImmSplatI8:$SIMM), IIC_VMOVImm, 4893 "vmov", "i8", "$Vd, $SIMM", "", 4894 [(set DPR:$Vd, (v8i8 (NEONvmovImm timm:$SIMM)))]>; 4895def VMOVv16i8 : N1ModImm<1, 0b000, 0b1110, 0, 1, 0, 1, (outs QPR:$Vd), 4896 (ins nImmSplatI8:$SIMM), IIC_VMOVImm, 4897 "vmov", "i8", "$Vd, $SIMM", "", 4898 [(set QPR:$Vd, (v16i8 (NEONvmovImm timm:$SIMM)))]>; 4899 4900def VMOVv4i16 : N1ModImm<1, 0b000, {1,0,?,0}, 0, 0, 0, 1, (outs DPR:$Vd), 4901 (ins nImmSplatI16:$SIMM), IIC_VMOVImm, 4902 "vmov", "i16", "$Vd, $SIMM", "", 4903 [(set DPR:$Vd, (v4i16 (NEONvmovImm timm:$SIMM)))]> { 4904 let Inst{9} = SIMM{9}; 4905} 4906 4907def VMOVv8i16 : N1ModImm<1, 0b000, {1,0,?,0}, 0, 1, 0, 1, (outs QPR:$Vd), 4908 (ins nImmSplatI16:$SIMM), IIC_VMOVImm, 4909 "vmov", "i16", "$Vd, $SIMM", "", 4910 [(set QPR:$Vd, (v8i16 (NEONvmovImm timm:$SIMM)))]> { 4911 let Inst{9} = SIMM{9}; 4912} 4913 4914def VMOVv2i32 : N1ModImm<1, 0b000, {?,?,?,?}, 0, 0, 0, 1, (outs DPR:$Vd), 4915 (ins nImmVMOVI32:$SIMM), IIC_VMOVImm, 4916 "vmov", "i32", "$Vd, $SIMM", "", 4917 [(set DPR:$Vd, (v2i32 (NEONvmovImm timm:$SIMM)))]> { 4918 let Inst{11-8} = SIMM{11-8}; 4919} 4920 4921def VMOVv4i32 : N1ModImm<1, 0b000, {?,?,?,?}, 0, 1, 0, 1, (outs QPR:$Vd), 4922 (ins nImmVMOVI32:$SIMM), IIC_VMOVImm, 4923 "vmov", "i32", "$Vd, $SIMM", "", 4924 [(set QPR:$Vd, (v4i32 (NEONvmovImm timm:$SIMM)))]> { 4925 let Inst{11-8} = SIMM{11-8}; 4926} 4927 4928def VMOVv1i64 : N1ModImm<1, 0b000, 0b1110, 0, 0, 1, 1, (outs DPR:$Vd), 4929 (ins nImmSplatI64:$SIMM), IIC_VMOVImm, 4930 "vmov", "i64", "$Vd, $SIMM", "", 4931 [(set DPR:$Vd, (v1i64 (NEONvmovImm timm:$SIMM)))]>; 4932def VMOVv2i64 : N1ModImm<1, 0b000, 0b1110, 0, 1, 1, 1, (outs QPR:$Vd), 4933 (ins nImmSplatI64:$SIMM), IIC_VMOVImm, 4934 "vmov", "i64", "$Vd, $SIMM", "", 4935 [(set QPR:$Vd, (v2i64 (NEONvmovImm timm:$SIMM)))]>; 4936 4937def VMOVv2f32 : N1ModImm<1, 0b000, 0b1111, 0, 0, 0, 1, (outs DPR:$Vd), 4938 (ins nImmVMOVF32:$SIMM), IIC_VMOVImm, 4939 "vmov", "f32", "$Vd, $SIMM", "", 4940 [(set DPR:$Vd, (v2f32 (NEONvmovFPImm timm:$SIMM)))]>; 4941def VMOVv4f32 : N1ModImm<1, 0b000, 0b1111, 0, 1, 0, 1, (outs QPR:$Vd), 4942 (ins nImmVMOVF32:$SIMM), IIC_VMOVImm, 4943 "vmov", "f32", "$Vd, $SIMM", "", 4944 [(set QPR:$Vd, (v4f32 (NEONvmovFPImm timm:$SIMM)))]>; 4945} // isReMaterializable 4946 4947// VMOV : Vector Get Lane (move scalar to ARM core register) 4948 4949def VGETLNs8 : NVGetLane<{1,1,1,0,0,1,?,1}, 0b1011, {?,?}, 4950 (outs GPR:$R), (ins DPR:$V, VectorIndex8:$lane), 4951 IIC_VMOVSI, "vmov", "s8", "$R, $V$lane", 4952 [(set GPR:$R, (NEONvgetlanes (v8i8 DPR:$V), 4953 imm:$lane))]> { 4954 let Inst{21} = lane{2}; 4955 let Inst{6-5} = lane{1-0}; 4956} 4957def VGETLNs16 : NVGetLane<{1,1,1,0,0,0,?,1}, 0b1011, {?,1}, 4958 (outs GPR:$R), (ins DPR:$V, VectorIndex16:$lane), 4959 IIC_VMOVSI, "vmov", "s16", "$R, $V$lane", 4960 [(set GPR:$R, (NEONvgetlanes (v4i16 DPR:$V), 4961 imm:$lane))]> { 4962 let Inst{21} = lane{1}; 4963 let Inst{6} = lane{0}; 4964} 4965def VGETLNu8 : NVGetLane<{1,1,1,0,1,1,?,1}, 0b1011, {?,?}, 4966 (outs GPR:$R), (ins DPR:$V, VectorIndex8:$lane), 4967 IIC_VMOVSI, "vmov", "u8", "$R, $V$lane", 4968 [(set GPR:$R, (NEONvgetlaneu (v8i8 DPR:$V), 4969 imm:$lane))]> { 4970 let Inst{21} = lane{2}; 4971 let Inst{6-5} = lane{1-0}; 4972} 4973def VGETLNu16 : NVGetLane<{1,1,1,0,1,0,?,1}, 0b1011, {?,1}, 4974 (outs GPR:$R), (ins DPR:$V, VectorIndex16:$lane), 4975 IIC_VMOVSI, "vmov", "u16", "$R, $V$lane", 4976 [(set GPR:$R, (NEONvgetlaneu (v4i16 DPR:$V), 4977 imm:$lane))]> { 4978 let Inst{21} = lane{1}; 4979 let Inst{6} = lane{0}; 4980} 4981def VGETLNi32 : NVGetLane<{1,1,1,0,0,0,?,1}, 0b1011, 0b00, 4982 (outs GPR:$R), (ins DPR:$V, VectorIndex32:$lane), 4983 IIC_VMOVSI, "vmov", "32", "$R, $V$lane", 4984 [(set GPR:$R, (extractelt (v2i32 DPR:$V), 4985 imm:$lane))]> { 4986 let Inst{21} = lane{0}; 4987} 4988// def VGETLNf32: see FMRDH and FMRDL in ARMInstrVFP.td 4989def : Pat<(NEONvgetlanes (v16i8 QPR:$src), imm:$lane), 4990 (VGETLNs8 (v8i8 (EXTRACT_SUBREG QPR:$src, 4991 (DSubReg_i8_reg imm:$lane))), 4992 (SubReg_i8_lane imm:$lane))>; 4993def : Pat<(NEONvgetlanes (v8i16 QPR:$src), imm:$lane), 4994 (VGETLNs16 (v4i16 (EXTRACT_SUBREG QPR:$src, 4995 (DSubReg_i16_reg imm:$lane))), 4996 (SubReg_i16_lane imm:$lane))>; 4997def : Pat<(NEONvgetlaneu (v16i8 QPR:$src), imm:$lane), 4998 (VGETLNu8 (v8i8 (EXTRACT_SUBREG QPR:$src, 4999 (DSubReg_i8_reg imm:$lane))), 5000 (SubReg_i8_lane imm:$lane))>; 5001def : Pat<(NEONvgetlaneu (v8i16 QPR:$src), imm:$lane), 5002 (VGETLNu16 (v4i16 (EXTRACT_SUBREG QPR:$src, 5003 (DSubReg_i16_reg imm:$lane))), 5004 (SubReg_i16_lane imm:$lane))>; 5005def : Pat<(extractelt (v4i32 QPR:$src), imm:$lane), 5006 (VGETLNi32 (v2i32 (EXTRACT_SUBREG QPR:$src, 5007 (DSubReg_i32_reg imm:$lane))), 5008 (SubReg_i32_lane imm:$lane))>; 5009def : Pat<(extractelt (v2f32 DPR:$src1), imm:$src2), 5010 (EXTRACT_SUBREG (v2f32 (COPY_TO_REGCLASS (v2f32 DPR:$src1),DPR_VFP2)), 5011 (SSubReg_f32_reg imm:$src2))>; 5012def : Pat<(extractelt (v4f32 QPR:$src1), imm:$src2), 5013 (EXTRACT_SUBREG (v4f32 (COPY_TO_REGCLASS (v4f32 QPR:$src1),QPR_VFP2)), 5014 (SSubReg_f32_reg imm:$src2))>; 5015//def : Pat<(extractelt (v2i64 QPR:$src1), imm:$src2), 5016// (EXTRACT_SUBREG QPR:$src1, (DSubReg_f64_reg imm:$src2))>; 5017def : Pat<(extractelt (v2f64 QPR:$src1), imm:$src2), 5018 (EXTRACT_SUBREG QPR:$src1, (DSubReg_f64_reg imm:$src2))>; 5019 5020 5021// VMOV : Vector Set Lane (move ARM core register to scalar) 5022 5023let Constraints = "$src1 = $V" in { 5024def VSETLNi8 : NVSetLane<{1,1,1,0,0,1,?,0}, 0b1011, {?,?}, (outs DPR:$V), 5025 (ins DPR:$src1, GPR:$R, VectorIndex8:$lane), 5026 IIC_VMOVISL, "vmov", "8", "$V$lane, $R", 5027 [(set DPR:$V, (vector_insert (v8i8 DPR:$src1), 5028 GPR:$R, imm:$lane))]> { 5029 let Inst{21} = lane{2}; 5030 let Inst{6-5} = lane{1-0}; 5031} 5032def VSETLNi16 : NVSetLane<{1,1,1,0,0,0,?,0}, 0b1011, {?,1}, (outs DPR:$V), 5033 (ins DPR:$src1, GPR:$R, VectorIndex16:$lane), 5034 IIC_VMOVISL, "vmov", "16", "$V$lane, $R", 5035 [(set DPR:$V, (vector_insert (v4i16 DPR:$src1), 5036 GPR:$R, imm:$lane))]> { 5037 let Inst{21} = lane{1}; 5038 let Inst{6} = lane{0}; 5039} 5040def VSETLNi32 : NVSetLane<{1,1,1,0,0,0,?,0}, 0b1011, 0b00, (outs DPR:$V), 5041 (ins DPR:$src1, GPR:$R, VectorIndex32:$lane), 5042 IIC_VMOVISL, "vmov", "32", "$V$lane, $R", 5043 [(set DPR:$V, (insertelt (v2i32 DPR:$src1), 5044 GPR:$R, imm:$lane))]> { 5045 let Inst{21} = lane{0}; 5046} 5047} 5048def : Pat<(vector_insert (v16i8 QPR:$src1), GPR:$src2, imm:$lane), 5049 (v16i8 (INSERT_SUBREG QPR:$src1, 5050 (v8i8 (VSETLNi8 (v8i8 (EXTRACT_SUBREG QPR:$src1, 5051 (DSubReg_i8_reg imm:$lane))), 5052 GPR:$src2, (SubReg_i8_lane imm:$lane))), 5053 (DSubReg_i8_reg imm:$lane)))>; 5054def : Pat<(vector_insert (v8i16 QPR:$src1), GPR:$src2, imm:$lane), 5055 (v8i16 (INSERT_SUBREG QPR:$src1, 5056 (v4i16 (VSETLNi16 (v4i16 (EXTRACT_SUBREG QPR:$src1, 5057 (DSubReg_i16_reg imm:$lane))), 5058 GPR:$src2, (SubReg_i16_lane imm:$lane))), 5059 (DSubReg_i16_reg imm:$lane)))>; 5060def : Pat<(insertelt (v4i32 QPR:$src1), GPR:$src2, imm:$lane), 5061 (v4i32 (INSERT_SUBREG QPR:$src1, 5062 (v2i32 (VSETLNi32 (v2i32 (EXTRACT_SUBREG QPR:$src1, 5063 (DSubReg_i32_reg imm:$lane))), 5064 GPR:$src2, (SubReg_i32_lane imm:$lane))), 5065 (DSubReg_i32_reg imm:$lane)))>; 5066 5067def : Pat<(v2f32 (insertelt DPR:$src1, SPR:$src2, imm:$src3)), 5068 (INSERT_SUBREG (v2f32 (COPY_TO_REGCLASS DPR:$src1, DPR_VFP2)), 5069 SPR:$src2, (SSubReg_f32_reg imm:$src3))>; 5070def : Pat<(v4f32 (insertelt QPR:$src1, SPR:$src2, imm:$src3)), 5071 (INSERT_SUBREG (v4f32 (COPY_TO_REGCLASS QPR:$src1, QPR_VFP2)), 5072 SPR:$src2, (SSubReg_f32_reg imm:$src3))>; 5073 5074//def : Pat<(v2i64 (insertelt QPR:$src1, DPR:$src2, imm:$src3)), 5075// (INSERT_SUBREG QPR:$src1, DPR:$src2, (DSubReg_f64_reg imm:$src3))>; 5076def : Pat<(v2f64 (insertelt QPR:$src1, DPR:$src2, imm:$src3)), 5077 (INSERT_SUBREG QPR:$src1, DPR:$src2, (DSubReg_f64_reg imm:$src3))>; 5078 5079def : Pat<(v2f32 (scalar_to_vector SPR:$src)), 5080 (INSERT_SUBREG (v2f32 (IMPLICIT_DEF)), SPR:$src, ssub_0)>; 5081def : Pat<(v2f64 (scalar_to_vector (f64 DPR:$src))), 5082 (INSERT_SUBREG (v2f64 (IMPLICIT_DEF)), DPR:$src, dsub_0)>; 5083def : Pat<(v4f32 (scalar_to_vector SPR:$src)), 5084 (INSERT_SUBREG (v4f32 (IMPLICIT_DEF)), SPR:$src, ssub_0)>; 5085 5086def : Pat<(v8i8 (scalar_to_vector GPR:$src)), 5087 (VSETLNi8 (v8i8 (IMPLICIT_DEF)), GPR:$src, (i32 0))>; 5088def : Pat<(v4i16 (scalar_to_vector GPR:$src)), 5089 (VSETLNi16 (v4i16 (IMPLICIT_DEF)), GPR:$src, (i32 0))>; 5090def : Pat<(v2i32 (scalar_to_vector GPR:$src)), 5091 (VSETLNi32 (v2i32 (IMPLICIT_DEF)), GPR:$src, (i32 0))>; 5092 5093def : Pat<(v16i8 (scalar_to_vector GPR:$src)), 5094 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)), 5095 (VSETLNi8 (v8i8 (IMPLICIT_DEF)), GPR:$src, (i32 0)), 5096 dsub_0)>; 5097def : Pat<(v8i16 (scalar_to_vector GPR:$src)), 5098 (INSERT_SUBREG (v8i16 (IMPLICIT_DEF)), 5099 (VSETLNi16 (v4i16 (IMPLICIT_DEF)), GPR:$src, (i32 0)), 5100 dsub_0)>; 5101def : Pat<(v4i32 (scalar_to_vector GPR:$src)), 5102 (INSERT_SUBREG (v4i32 (IMPLICIT_DEF)), 5103 (VSETLNi32 (v2i32 (IMPLICIT_DEF)), GPR:$src, (i32 0)), 5104 dsub_0)>; 5105 5106// VDUP : Vector Duplicate (from ARM core register to all elements) 5107 5108class VDUPD<bits<8> opcod1, bits<2> opcod3, string Dt, ValueType Ty> 5109 : NVDup<opcod1, 0b1011, opcod3, (outs DPR:$V), (ins GPR:$R), 5110 IIC_VMOVIS, "vdup", Dt, "$V, $R", 5111 [(set DPR:$V, (Ty (NEONvdup (i32 GPR:$R))))]>; 5112class VDUPQ<bits<8> opcod1, bits<2> opcod3, string Dt, ValueType Ty> 5113 : NVDup<opcod1, 0b1011, opcod3, (outs QPR:$V), (ins GPR:$R), 5114 IIC_VMOVIS, "vdup", Dt, "$V, $R", 5115 [(set QPR:$V, (Ty (NEONvdup (i32 GPR:$R))))]>; 5116 5117def VDUP8d : VDUPD<0b11101100, 0b00, "8", v8i8>; 5118def VDUP16d : VDUPD<0b11101000, 0b01, "16", v4i16>; 5119def VDUP32d : VDUPD<0b11101000, 0b00, "32", v2i32>; 5120def VDUP8q : VDUPQ<0b11101110, 0b00, "8", v16i8>; 5121def VDUP16q : VDUPQ<0b11101010, 0b01, "16", v8i16>; 5122def VDUP32q : VDUPQ<0b11101010, 0b00, "32", v4i32>; 5123 5124def : Pat<(v2f32 (NEONvdup (f32 (bitconvert GPR:$R)))), (VDUP32d GPR:$R)>; 5125def : Pat<(v4f32 (NEONvdup (f32 (bitconvert GPR:$R)))), (VDUP32q GPR:$R)>; 5126 5127// VDUP : Vector Duplicate Lane (from scalar to all elements) 5128 5129class VDUPLND<bits<4> op19_16, string OpcodeStr, string Dt, 5130 ValueType Ty, Operand IdxTy> 5131 : NVDupLane<op19_16, 0, (outs DPR:$Vd), (ins DPR:$Vm, IdxTy:$lane), 5132 IIC_VMOVD, OpcodeStr, Dt, "$Vd, $Vm$lane", 5133 [(set DPR:$Vd, (Ty (NEONvduplane (Ty DPR:$Vm), imm:$lane)))]>; 5134 5135class VDUPLNQ<bits<4> op19_16, string OpcodeStr, string Dt, 5136 ValueType ResTy, ValueType OpTy, Operand IdxTy> 5137 : NVDupLane<op19_16, 1, (outs QPR:$Vd), (ins DPR:$Vm, IdxTy:$lane), 5138 IIC_VMOVQ, OpcodeStr, Dt, "$Vd, $Vm$lane", 5139 [(set QPR:$Vd, (ResTy (NEONvduplane (OpTy DPR:$Vm), 5140 VectorIndex32:$lane)))]>; 5141 5142// Inst{19-16} is partially specified depending on the element size. 5143 5144def VDUPLN8d : VDUPLND<{?,?,?,1}, "vdup", "8", v8i8, VectorIndex8> { 5145 bits<3> lane; 5146 let Inst{19-17} = lane{2-0}; 5147} 5148def VDUPLN16d : VDUPLND<{?,?,1,0}, "vdup", "16", v4i16, VectorIndex16> { 5149 bits<2> lane; 5150 let Inst{19-18} = lane{1-0}; 5151} 5152def VDUPLN32d : VDUPLND<{?,1,0,0}, "vdup", "32", v2i32, VectorIndex32> { 5153 bits<1> lane; 5154 let Inst{19} = lane{0}; 5155} 5156def VDUPLN8q : VDUPLNQ<{?,?,?,1}, "vdup", "8", v16i8, v8i8, VectorIndex8> { 5157 bits<3> lane; 5158 let Inst{19-17} = lane{2-0}; 5159} 5160def VDUPLN16q : VDUPLNQ<{?,?,1,0}, "vdup", "16", v8i16, v4i16, VectorIndex16> { 5161 bits<2> lane; 5162 let Inst{19-18} = lane{1-0}; 5163} 5164def VDUPLN32q : VDUPLNQ<{?,1,0,0}, "vdup", "32", v4i32, v2i32, VectorIndex32> { 5165 bits<1> lane; 5166 let Inst{19} = lane{0}; 5167} 5168 5169def : Pat<(v2f32 (NEONvduplane (v2f32 DPR:$Vm), imm:$lane)), 5170 (VDUPLN32d DPR:$Vm, imm:$lane)>; 5171 5172def : Pat<(v4f32 (NEONvduplane (v2f32 DPR:$Vm), imm:$lane)), 5173 (VDUPLN32q DPR:$Vm, imm:$lane)>; 5174 5175def : Pat<(v16i8 (NEONvduplane (v16i8 QPR:$src), imm:$lane)), 5176 (v16i8 (VDUPLN8q (v8i8 (EXTRACT_SUBREG QPR:$src, 5177 (DSubReg_i8_reg imm:$lane))), 5178 (SubReg_i8_lane imm:$lane)))>; 5179def : Pat<(v8i16 (NEONvduplane (v8i16 QPR:$src), imm:$lane)), 5180 (v8i16 (VDUPLN16q (v4i16 (EXTRACT_SUBREG QPR:$src, 5181 (DSubReg_i16_reg imm:$lane))), 5182 (SubReg_i16_lane imm:$lane)))>; 5183def : Pat<(v4i32 (NEONvduplane (v4i32 QPR:$src), imm:$lane)), 5184 (v4i32 (VDUPLN32q (v2i32 (EXTRACT_SUBREG QPR:$src, 5185 (DSubReg_i32_reg imm:$lane))), 5186 (SubReg_i32_lane imm:$lane)))>; 5187def : Pat<(v4f32 (NEONvduplane (v4f32 QPR:$src), imm:$lane)), 5188 (v4f32 (VDUPLN32q (v2f32 (EXTRACT_SUBREG QPR:$src, 5189 (DSubReg_i32_reg imm:$lane))), 5190 (SubReg_i32_lane imm:$lane)))>; 5191 5192def VDUPfdf : PseudoNeonI<(outs DPR:$dst), (ins SPR:$src), IIC_VMOVD, "", 5193 [(set DPR:$dst, (v2f32 (NEONvdup (f32 SPR:$src))))]>; 5194def VDUPfqf : PseudoNeonI<(outs QPR:$dst), (ins SPR:$src), IIC_VMOVD, "", 5195 [(set QPR:$dst, (v4f32 (NEONvdup (f32 SPR:$src))))]>; 5196 5197// VMOVN : Vector Narrowing Move 5198defm VMOVN : N2VN_HSD<0b11,0b11,0b10,0b00100,0,0, IIC_VMOVN, 5199 "vmovn", "i", trunc>; 5200// VQMOVN : Vector Saturating Narrowing Move 5201defm VQMOVNs : N2VNInt_HSD<0b11,0b11,0b10,0b00101,0,0, IIC_VQUNAiD, 5202 "vqmovn", "s", int_arm_neon_vqmovns>; 5203defm VQMOVNu : N2VNInt_HSD<0b11,0b11,0b10,0b00101,1,0, IIC_VQUNAiD, 5204 "vqmovn", "u", int_arm_neon_vqmovnu>; 5205defm VQMOVNsu : N2VNInt_HSD<0b11,0b11,0b10,0b00100,1,0, IIC_VQUNAiD, 5206 "vqmovun", "s", int_arm_neon_vqmovnsu>; 5207// VMOVL : Vector Lengthening Move 5208defm VMOVLs : N2VL_QHS<0b01,0b10100,0,1, "vmovl", "s", sext>; 5209defm VMOVLu : N2VL_QHS<0b11,0b10100,0,1, "vmovl", "u", zext>; 5210def : Pat<(v8i16 (anyext (v8i8 DPR:$Vm))), (VMOVLuv8i16 DPR:$Vm)>; 5211def : Pat<(v4i32 (anyext (v4i16 DPR:$Vm))), (VMOVLuv4i32 DPR:$Vm)>; 5212def : Pat<(v2i64 (anyext (v2i32 DPR:$Vm))), (VMOVLuv2i64 DPR:$Vm)>; 5213 5214// Vector Conversions. 5215 5216// VCVT : Vector Convert Between Floating-Point and Integers 5217def VCVTf2sd : N2VD<0b11, 0b11, 0b10, 0b11, 0b01110, 0, "vcvt", "s32.f32", 5218 v2i32, v2f32, fp_to_sint>; 5219def VCVTf2ud : N2VD<0b11, 0b11, 0b10, 0b11, 0b01111, 0, "vcvt", "u32.f32", 5220 v2i32, v2f32, fp_to_uint>; 5221def VCVTs2fd : N2VD<0b11, 0b11, 0b10, 0b11, 0b01100, 0, "vcvt", "f32.s32", 5222 v2f32, v2i32, sint_to_fp>; 5223def VCVTu2fd : N2VD<0b11, 0b11, 0b10, 0b11, 0b01101, 0, "vcvt", "f32.u32", 5224 v2f32, v2i32, uint_to_fp>; 5225 5226def VCVTf2sq : N2VQ<0b11, 0b11, 0b10, 0b11, 0b01110, 0, "vcvt", "s32.f32", 5227 v4i32, v4f32, fp_to_sint>; 5228def VCVTf2uq : N2VQ<0b11, 0b11, 0b10, 0b11, 0b01111, 0, "vcvt", "u32.f32", 5229 v4i32, v4f32, fp_to_uint>; 5230def VCVTs2fq : N2VQ<0b11, 0b11, 0b10, 0b11, 0b01100, 0, "vcvt", "f32.s32", 5231 v4f32, v4i32, sint_to_fp>; 5232def VCVTu2fq : N2VQ<0b11, 0b11, 0b10, 0b11, 0b01101, 0, "vcvt", "f32.u32", 5233 v4f32, v4i32, uint_to_fp>; 5234 5235// VCVT : Vector Convert Between Floating-Point and Fixed-Point. 5236let DecoderMethod = "DecodeVCVTD" in { 5237def VCVTf2xsd : N2VCvtD<0, 1, 0b1111, 0, 1, "vcvt", "s32.f32", 5238 v2i32, v2f32, int_arm_neon_vcvtfp2fxs>; 5239def VCVTf2xud : N2VCvtD<1, 1, 0b1111, 0, 1, "vcvt", "u32.f32", 5240 v2i32, v2f32, int_arm_neon_vcvtfp2fxu>; 5241def VCVTxs2fd : N2VCvtD<0, 1, 0b1110, 0, 1, "vcvt", "f32.s32", 5242 v2f32, v2i32, int_arm_neon_vcvtfxs2fp>; 5243def VCVTxu2fd : N2VCvtD<1, 1, 0b1110, 0, 1, "vcvt", "f32.u32", 5244 v2f32, v2i32, int_arm_neon_vcvtfxu2fp>; 5245} 5246 5247let DecoderMethod = "DecodeVCVTQ" in { 5248def VCVTf2xsq : N2VCvtQ<0, 1, 0b1111, 0, 1, "vcvt", "s32.f32", 5249 v4i32, v4f32, int_arm_neon_vcvtfp2fxs>; 5250def VCVTf2xuq : N2VCvtQ<1, 1, 0b1111, 0, 1, "vcvt", "u32.f32", 5251 v4i32, v4f32, int_arm_neon_vcvtfp2fxu>; 5252def VCVTxs2fq : N2VCvtQ<0, 1, 0b1110, 0, 1, "vcvt", "f32.s32", 5253 v4f32, v4i32, int_arm_neon_vcvtfxs2fp>; 5254def VCVTxu2fq : N2VCvtQ<1, 1, 0b1110, 0, 1, "vcvt", "f32.u32", 5255 v4f32, v4i32, int_arm_neon_vcvtfxu2fp>; 5256} 5257 5258// VCVT : Vector Convert Between Half-Precision and Single-Precision. 5259def VCVTf2h : N2VNInt<0b11, 0b11, 0b01, 0b10, 0b01100, 0, 0, 5260 IIC_VUNAQ, "vcvt", "f16.f32", 5261 v4i16, v4f32, int_arm_neon_vcvtfp2hf>, 5262 Requires<[HasNEON, HasFP16]>; 5263def VCVTh2f : N2VLInt<0b11, 0b11, 0b01, 0b10, 0b01110, 0, 0, 5264 IIC_VUNAQ, "vcvt", "f32.f16", 5265 v4f32, v4i16, int_arm_neon_vcvthf2fp>, 5266 Requires<[HasNEON, HasFP16]>; 5267 5268// Vector Reverse. 5269 5270// VREV64 : Vector Reverse elements within 64-bit doublewords 5271 5272class VREV64D<bits<2> op19_18, string OpcodeStr, string Dt, ValueType Ty> 5273 : N2V<0b11, 0b11, op19_18, 0b00, 0b00000, 0, 0, (outs DPR:$Vd), 5274 (ins DPR:$Vm), IIC_VMOVD, 5275 OpcodeStr, Dt, "$Vd, $Vm", "", 5276 [(set DPR:$Vd, (Ty (NEONvrev64 (Ty DPR:$Vm))))]>; 5277class VREV64Q<bits<2> op19_18, string OpcodeStr, string Dt, ValueType Ty> 5278 : N2V<0b11, 0b11, op19_18, 0b00, 0b00000, 1, 0, (outs QPR:$Vd), 5279 (ins QPR:$Vm), IIC_VMOVQ, 5280 OpcodeStr, Dt, "$Vd, $Vm", "", 5281 [(set QPR:$Vd, (Ty (NEONvrev64 (Ty QPR:$Vm))))]>; 5282 5283def VREV64d8 : VREV64D<0b00, "vrev64", "8", v8i8>; 5284def VREV64d16 : VREV64D<0b01, "vrev64", "16", v4i16>; 5285def VREV64d32 : VREV64D<0b10, "vrev64", "32", v2i32>; 5286def : Pat<(v2f32 (NEONvrev64 (v2f32 DPR:$Vm))), (VREV64d32 DPR:$Vm)>; 5287 5288def VREV64q8 : VREV64Q<0b00, "vrev64", "8", v16i8>; 5289def VREV64q16 : VREV64Q<0b01, "vrev64", "16", v8i16>; 5290def VREV64q32 : VREV64Q<0b10, "vrev64", "32", v4i32>; 5291def : Pat<(v4f32 (NEONvrev64 (v4f32 QPR:$Vm))), (VREV64q32 QPR:$Vm)>; 5292 5293// VREV32 : Vector Reverse elements within 32-bit words 5294 5295class VREV32D<bits<2> op19_18, string OpcodeStr, string Dt, ValueType Ty> 5296 : N2V<0b11, 0b11, op19_18, 0b00, 0b00001, 0, 0, (outs DPR:$Vd), 5297 (ins DPR:$Vm), IIC_VMOVD, 5298 OpcodeStr, Dt, "$Vd, $Vm", "", 5299 [(set DPR:$Vd, (Ty (NEONvrev32 (Ty DPR:$Vm))))]>; 5300class VREV32Q<bits<2> op19_18, string OpcodeStr, string Dt, ValueType Ty> 5301 : N2V<0b11, 0b11, op19_18, 0b00, 0b00001, 1, 0, (outs QPR:$Vd), 5302 (ins QPR:$Vm), IIC_VMOVQ, 5303 OpcodeStr, Dt, "$Vd, $Vm", "", 5304 [(set QPR:$Vd, (Ty (NEONvrev32 (Ty QPR:$Vm))))]>; 5305 5306def VREV32d8 : VREV32D<0b00, "vrev32", "8", v8i8>; 5307def VREV32d16 : VREV32D<0b01, "vrev32", "16", v4i16>; 5308 5309def VREV32q8 : VREV32Q<0b00, "vrev32", "8", v16i8>; 5310def VREV32q16 : VREV32Q<0b01, "vrev32", "16", v8i16>; 5311 5312// VREV16 : Vector Reverse elements within 16-bit halfwords 5313 5314class VREV16D<bits<2> op19_18, string OpcodeStr, string Dt, ValueType Ty> 5315 : N2V<0b11, 0b11, op19_18, 0b00, 0b00010, 0, 0, (outs DPR:$Vd), 5316 (ins DPR:$Vm), IIC_VMOVD, 5317 OpcodeStr, Dt, "$Vd, $Vm", "", 5318 [(set DPR:$Vd, (Ty (NEONvrev16 (Ty DPR:$Vm))))]>; 5319class VREV16Q<bits<2> op19_18, string OpcodeStr, string Dt, ValueType Ty> 5320 : N2V<0b11, 0b11, op19_18, 0b00, 0b00010, 1, 0, (outs QPR:$Vd), 5321 (ins QPR:$Vm), IIC_VMOVQ, 5322 OpcodeStr, Dt, "$Vd, $Vm", "", 5323 [(set QPR:$Vd, (Ty (NEONvrev16 (Ty QPR:$Vm))))]>; 5324 5325def VREV16d8 : VREV16D<0b00, "vrev16", "8", v8i8>; 5326def VREV16q8 : VREV16Q<0b00, "vrev16", "8", v16i8>; 5327 5328// Other Vector Shuffles. 5329 5330// Aligned extractions: really just dropping registers 5331 5332class AlignedVEXTq<ValueType DestTy, ValueType SrcTy, SDNodeXForm LaneCVT> 5333 : Pat<(DestTy (vector_extract_subvec (SrcTy QPR:$src), (i32 imm:$start))), 5334 (EXTRACT_SUBREG (SrcTy QPR:$src), (LaneCVT imm:$start))>; 5335 5336def : AlignedVEXTq<v8i8, v16i8, DSubReg_i8_reg>; 5337 5338def : AlignedVEXTq<v4i16, v8i16, DSubReg_i16_reg>; 5339 5340def : AlignedVEXTq<v2i32, v4i32, DSubReg_i32_reg>; 5341 5342def : AlignedVEXTq<v1i64, v2i64, DSubReg_f64_reg>; 5343 5344def : AlignedVEXTq<v2f32, v4f32, DSubReg_i32_reg>; 5345 5346 5347// VEXT : Vector Extract 5348 5349class VEXTd<string OpcodeStr, string Dt, ValueType Ty, Operand immTy> 5350 : N3V<0,1,0b11,{?,?,?,?},0,0, (outs DPR:$Vd), 5351 (ins DPR:$Vn, DPR:$Vm, immTy:$index), NVExtFrm, 5352 IIC_VEXTD, OpcodeStr, Dt, "$Vd, $Vn, $Vm, $index", "", 5353 [(set DPR:$Vd, (Ty (NEONvext (Ty DPR:$Vn), 5354 (Ty DPR:$Vm), imm:$index)))]> { 5355 bits<4> index; 5356 let Inst{11-8} = index{3-0}; 5357} 5358 5359class VEXTq<string OpcodeStr, string Dt, ValueType Ty, Operand immTy> 5360 : N3V<0,1,0b11,{?,?,?,?},1,0, (outs QPR:$Vd), 5361 (ins QPR:$Vn, QPR:$Vm, imm0_15:$index), NVExtFrm, 5362 IIC_VEXTQ, OpcodeStr, Dt, "$Vd, $Vn, $Vm, $index", "", 5363 [(set QPR:$Vd, (Ty (NEONvext (Ty QPR:$Vn), 5364 (Ty QPR:$Vm), imm:$index)))]> { 5365 bits<4> index; 5366 let Inst{11-8} = index{3-0}; 5367} 5368 5369def VEXTd8 : VEXTd<"vext", "8", v8i8, imm0_7> { 5370 let Inst{11-8} = index{3-0}; 5371} 5372def VEXTd16 : VEXTd<"vext", "16", v4i16, imm0_3> { 5373 let Inst{11-9} = index{2-0}; 5374 let Inst{8} = 0b0; 5375} 5376def VEXTd32 : VEXTd<"vext", "32", v2i32, imm0_1> { 5377 let Inst{11-10} = index{1-0}; 5378 let Inst{9-8} = 0b00; 5379} 5380def : Pat<(v2f32 (NEONvext (v2f32 DPR:$Vn), 5381 (v2f32 DPR:$Vm), 5382 (i32 imm:$index))), 5383 (VEXTd32 DPR:$Vn, DPR:$Vm, imm:$index)>; 5384 5385def VEXTq8 : VEXTq<"vext", "8", v16i8, imm0_15> { 5386 let Inst{11-8} = index{3-0}; 5387} 5388def VEXTq16 : VEXTq<"vext", "16", v8i16, imm0_7> { 5389 let Inst{11-9} = index{2-0}; 5390 let Inst{8} = 0b0; 5391} 5392def VEXTq32 : VEXTq<"vext", "32", v4i32, imm0_3> { 5393 let Inst{11-10} = index{1-0}; 5394 let Inst{9-8} = 0b00; 5395} 5396def VEXTq64 : VEXTq<"vext", "64", v2i64, imm0_1> { 5397 let Inst{11} = index{0}; 5398 let Inst{10-8} = 0b000; 5399} 5400def : Pat<(v4f32 (NEONvext (v4f32 QPR:$Vn), 5401 (v4f32 QPR:$Vm), 5402 (i32 imm:$index))), 5403 (VEXTq32 QPR:$Vn, QPR:$Vm, imm:$index)>; 5404 5405// VTRN : Vector Transpose 5406 5407def VTRNd8 : N2VDShuffle<0b00, 0b00001, "vtrn", "8">; 5408def VTRNd16 : N2VDShuffle<0b01, 0b00001, "vtrn", "16">; 5409def VTRNd32 : N2VDShuffle<0b10, 0b00001, "vtrn", "32">; 5410 5411def VTRNq8 : N2VQShuffle<0b00, 0b00001, IIC_VPERMQ, "vtrn", "8">; 5412def VTRNq16 : N2VQShuffle<0b01, 0b00001, IIC_VPERMQ, "vtrn", "16">; 5413def VTRNq32 : N2VQShuffle<0b10, 0b00001, IIC_VPERMQ, "vtrn", "32">; 5414 5415// VUZP : Vector Unzip (Deinterleave) 5416 5417def VUZPd8 : N2VDShuffle<0b00, 0b00010, "vuzp", "8">; 5418def VUZPd16 : N2VDShuffle<0b01, 0b00010, "vuzp", "16">; 5419def VUZPd32 : N2VDShuffle<0b10, 0b00010, "vuzp", "32">; 5420 5421def VUZPq8 : N2VQShuffle<0b00, 0b00010, IIC_VPERMQ3, "vuzp", "8">; 5422def VUZPq16 : N2VQShuffle<0b01, 0b00010, IIC_VPERMQ3, "vuzp", "16">; 5423def VUZPq32 : N2VQShuffle<0b10, 0b00010, IIC_VPERMQ3, "vuzp", "32">; 5424 5425// VZIP : Vector Zip (Interleave) 5426 5427def VZIPd8 : N2VDShuffle<0b00, 0b00011, "vzip", "8">; 5428def VZIPd16 : N2VDShuffle<0b01, 0b00011, "vzip", "16">; 5429def VZIPd32 : N2VDShuffle<0b10, 0b00011, "vzip", "32">; 5430 5431def VZIPq8 : N2VQShuffle<0b00, 0b00011, IIC_VPERMQ3, "vzip", "8">; 5432def VZIPq16 : N2VQShuffle<0b01, 0b00011, IIC_VPERMQ3, "vzip", "16">; 5433def VZIPq32 : N2VQShuffle<0b10, 0b00011, IIC_VPERMQ3, "vzip", "32">; 5434 5435// Vector Table Lookup and Table Extension. 5436 5437// VTBL : Vector Table Lookup 5438let DecoderMethod = "DecodeTBLInstruction" in { 5439def VTBL1 5440 : N3V<1,1,0b11,0b1000,0,0, (outs DPR:$Vd), 5441 (ins VecListOneD:$Vn, DPR:$Vm), NVTBLFrm, IIC_VTB1, 5442 "vtbl", "8", "$Vd, $Vn, $Vm", "", 5443 [(set DPR:$Vd, (v8i8 (int_arm_neon_vtbl1 VecListOneD:$Vn, DPR:$Vm)))]>; 5444let hasExtraSrcRegAllocReq = 1 in { 5445def VTBL2 5446 : N3V<1,1,0b11,0b1001,0,0, (outs DPR:$Vd), 5447 (ins VecListTwoD:$Vn, DPR:$Vm), NVTBLFrm, IIC_VTB2, 5448 "vtbl", "8", "$Vd, $Vn, $Vm", "", []>; 5449def VTBL3 5450 : N3V<1,1,0b11,0b1010,0,0, (outs DPR:$Vd), 5451 (ins VecListThreeD:$Vn, DPR:$Vm), NVTBLFrm, IIC_VTB3, 5452 "vtbl", "8", "$Vd, $Vn, $Vm", "", []>; 5453def VTBL4 5454 : N3V<1,1,0b11,0b1011,0,0, (outs DPR:$Vd), 5455 (ins VecListFourD:$Vn, DPR:$Vm), 5456 NVTBLFrm, IIC_VTB4, 5457 "vtbl", "8", "$Vd, $Vn, $Vm", "", []>; 5458} // hasExtraSrcRegAllocReq = 1 5459 5460def VTBL2Pseudo 5461 : PseudoNeonI<(outs DPR:$dst), (ins QPR:$tbl, DPR:$src), IIC_VTB2, "", []>; 5462def VTBL3Pseudo 5463 : PseudoNeonI<(outs DPR:$dst), (ins QQPR:$tbl, DPR:$src), IIC_VTB3, "", []>; 5464def VTBL4Pseudo 5465 : PseudoNeonI<(outs DPR:$dst), (ins QQPR:$tbl, DPR:$src), IIC_VTB4, "", []>; 5466 5467// VTBX : Vector Table Extension 5468def VTBX1 5469 : N3V<1,1,0b11,0b1000,1,0, (outs DPR:$Vd), 5470 (ins DPR:$orig, VecListOneD:$Vn, DPR:$Vm), NVTBLFrm, IIC_VTBX1, 5471 "vtbx", "8", "$Vd, $Vn, $Vm", "$orig = $Vd", 5472 [(set DPR:$Vd, (v8i8 (int_arm_neon_vtbx1 5473 DPR:$orig, VecListOneD:$Vn, DPR:$Vm)))]>; 5474let hasExtraSrcRegAllocReq = 1 in { 5475def VTBX2 5476 : N3V<1,1,0b11,0b1001,1,0, (outs DPR:$Vd), 5477 (ins DPR:$orig, VecListTwoD:$Vn, DPR:$Vm), NVTBLFrm, IIC_VTBX2, 5478 "vtbx", "8", "$Vd, $Vn, $Vm", "$orig = $Vd", []>; 5479def VTBX3 5480 : N3V<1,1,0b11,0b1010,1,0, (outs DPR:$Vd), 5481 (ins DPR:$orig, VecListThreeD:$Vn, DPR:$Vm), 5482 NVTBLFrm, IIC_VTBX3, 5483 "vtbx", "8", "$Vd, $Vn, $Vm", 5484 "$orig = $Vd", []>; 5485def VTBX4 5486 : N3V<1,1,0b11,0b1011,1,0, (outs DPR:$Vd), 5487 (ins DPR:$orig, VecListFourD:$Vn, DPR:$Vm), NVTBLFrm, IIC_VTBX4, 5488 "vtbx", "8", "$Vd, $Vn, $Vm", 5489 "$orig = $Vd", []>; 5490} // hasExtraSrcRegAllocReq = 1 5491 5492def VTBX2Pseudo 5493 : PseudoNeonI<(outs DPR:$dst), (ins DPR:$orig, QPR:$tbl, DPR:$src), 5494 IIC_VTBX2, "$orig = $dst", []>; 5495def VTBX3Pseudo 5496 : PseudoNeonI<(outs DPR:$dst), (ins DPR:$orig, QQPR:$tbl, DPR:$src), 5497 IIC_VTBX3, "$orig = $dst", []>; 5498def VTBX4Pseudo 5499 : PseudoNeonI<(outs DPR:$dst), (ins DPR:$orig, QQPR:$tbl, DPR:$src), 5500 IIC_VTBX4, "$orig = $dst", []>; 5501} // DecoderMethod = "DecodeTBLInstruction" 5502 5503//===----------------------------------------------------------------------===// 5504// NEON instructions for single-precision FP math 5505//===----------------------------------------------------------------------===// 5506 5507class N2VSPat<SDNode OpNode, NeonI Inst> 5508 : NEONFPPat<(f32 (OpNode SPR:$a)), 5509 (EXTRACT_SUBREG 5510 (v2f32 (COPY_TO_REGCLASS (Inst 5511 (INSERT_SUBREG 5512 (v2f32 (COPY_TO_REGCLASS (v2f32 (IMPLICIT_DEF)), DPR_VFP2)), 5513 SPR:$a, ssub_0)), DPR_VFP2)), ssub_0)>; 5514 5515class N3VSPat<SDNode OpNode, NeonI Inst> 5516 : NEONFPPat<(f32 (OpNode SPR:$a, SPR:$b)), 5517 (EXTRACT_SUBREG 5518 (v2f32 (COPY_TO_REGCLASS (Inst 5519 (INSERT_SUBREG 5520 (v2f32 (COPY_TO_REGCLASS (v2f32 (IMPLICIT_DEF)), DPR_VFP2)), 5521 SPR:$a, ssub_0), 5522 (INSERT_SUBREG 5523 (v2f32 (COPY_TO_REGCLASS (v2f32 (IMPLICIT_DEF)), DPR_VFP2)), 5524 SPR:$b, ssub_0)), DPR_VFP2)), ssub_0)>; 5525 5526class N3VSMulOpPat<SDNode MulNode, SDNode OpNode, NeonI Inst> 5527 : NEONFPPat<(f32 (OpNode SPR:$acc, (f32 (MulNode SPR:$a, SPR:$b)))), 5528 (EXTRACT_SUBREG 5529 (v2f32 (COPY_TO_REGCLASS (Inst 5530 (INSERT_SUBREG 5531 (v2f32 (COPY_TO_REGCLASS (v2f32 (IMPLICIT_DEF)), DPR_VFP2)), 5532 SPR:$acc, ssub_0), 5533 (INSERT_SUBREG 5534 (v2f32 (COPY_TO_REGCLASS (v2f32 (IMPLICIT_DEF)), DPR_VFP2)), 5535 SPR:$a, ssub_0), 5536 (INSERT_SUBREG 5537 (v2f32 (COPY_TO_REGCLASS (v2f32 (IMPLICIT_DEF)), DPR_VFP2)), 5538 SPR:$b, ssub_0)), DPR_VFP2)), ssub_0)>; 5539 5540def : N3VSPat<fadd, VADDfd>; 5541def : N3VSPat<fsub, VSUBfd>; 5542def : N3VSPat<fmul, VMULfd>; 5543def : N3VSMulOpPat<fmul, fadd, VMLAfd>, 5544 Requires<[HasNEON, UseNEONForFP, UseFPVMLx, NoNEONVFP4]>; 5545def : N3VSMulOpPat<fmul, fsub, VMLSfd>, 5546 Requires<[HasNEON, UseNEONForFP, UseFPVMLx, NoNEONVFP4]>; 5547def : N3VSMulOpPat<fmul, fadd, VFMAfd>, 5548 Requires<[HasNEONVFP4, UseNEONForFP]>; 5549def : N3VSMulOpPat<fmul, fsub, VFMSfd>, 5550 Requires<[HasNEONVFP4, UseNEONForFP]>; 5551def : N2VSPat<fabs, VABSfd>; 5552def : N2VSPat<fneg, VNEGfd>; 5553def : N3VSPat<NEONfmax, VMAXfd>; 5554def : N3VSPat<NEONfmin, VMINfd>; 5555def : N2VSPat<arm_ftosi, VCVTf2sd>; 5556def : N2VSPat<arm_ftoui, VCVTf2ud>; 5557def : N2VSPat<arm_sitof, VCVTs2fd>; 5558def : N2VSPat<arm_uitof, VCVTu2fd>; 5559 5560//===----------------------------------------------------------------------===// 5561// Non-Instruction Patterns 5562//===----------------------------------------------------------------------===// 5563 5564// bit_convert 5565def : Pat<(v1i64 (bitconvert (v2i32 DPR:$src))), (v1i64 DPR:$src)>; 5566def : Pat<(v1i64 (bitconvert (v4i16 DPR:$src))), (v1i64 DPR:$src)>; 5567def : Pat<(v1i64 (bitconvert (v8i8 DPR:$src))), (v1i64 DPR:$src)>; 5568def : Pat<(v1i64 (bitconvert (f64 DPR:$src))), (v1i64 DPR:$src)>; 5569def : Pat<(v1i64 (bitconvert (v2f32 DPR:$src))), (v1i64 DPR:$src)>; 5570def : Pat<(v2i32 (bitconvert (v1i64 DPR:$src))), (v2i32 DPR:$src)>; 5571def : Pat<(v2i32 (bitconvert (v4i16 DPR:$src))), (v2i32 DPR:$src)>; 5572def : Pat<(v2i32 (bitconvert (v8i8 DPR:$src))), (v2i32 DPR:$src)>; 5573def : Pat<(v2i32 (bitconvert (f64 DPR:$src))), (v2i32 DPR:$src)>; 5574def : Pat<(v2i32 (bitconvert (v2f32 DPR:$src))), (v2i32 DPR:$src)>; 5575def : Pat<(v4i16 (bitconvert (v1i64 DPR:$src))), (v4i16 DPR:$src)>; 5576def : Pat<(v4i16 (bitconvert (v2i32 DPR:$src))), (v4i16 DPR:$src)>; 5577def : Pat<(v4i16 (bitconvert (v8i8 DPR:$src))), (v4i16 DPR:$src)>; 5578def : Pat<(v4i16 (bitconvert (f64 DPR:$src))), (v4i16 DPR:$src)>; 5579def : Pat<(v4i16 (bitconvert (v2f32 DPR:$src))), (v4i16 DPR:$src)>; 5580def : Pat<(v8i8 (bitconvert (v1i64 DPR:$src))), (v8i8 DPR:$src)>; 5581def : Pat<(v8i8 (bitconvert (v2i32 DPR:$src))), (v8i8 DPR:$src)>; 5582def : Pat<(v8i8 (bitconvert (v4i16 DPR:$src))), (v8i8 DPR:$src)>; 5583def : Pat<(v8i8 (bitconvert (f64 DPR:$src))), (v8i8 DPR:$src)>; 5584def : Pat<(v8i8 (bitconvert (v2f32 DPR:$src))), (v8i8 DPR:$src)>; 5585def : Pat<(f64 (bitconvert (v1i64 DPR:$src))), (f64 DPR:$src)>; 5586def : Pat<(f64 (bitconvert (v2i32 DPR:$src))), (f64 DPR:$src)>; 5587def : Pat<(f64 (bitconvert (v4i16 DPR:$src))), (f64 DPR:$src)>; 5588def : Pat<(f64 (bitconvert (v8i8 DPR:$src))), (f64 DPR:$src)>; 5589def : Pat<(f64 (bitconvert (v2f32 DPR:$src))), (f64 DPR:$src)>; 5590def : Pat<(v2f32 (bitconvert (f64 DPR:$src))), (v2f32 DPR:$src)>; 5591def : Pat<(v2f32 (bitconvert (v1i64 DPR:$src))), (v2f32 DPR:$src)>; 5592def : Pat<(v2f32 (bitconvert (v2i32 DPR:$src))), (v2f32 DPR:$src)>; 5593def : Pat<(v2f32 (bitconvert (v4i16 DPR:$src))), (v2f32 DPR:$src)>; 5594def : Pat<(v2f32 (bitconvert (v8i8 DPR:$src))), (v2f32 DPR:$src)>; 5595 5596def : Pat<(v2i64 (bitconvert (v4i32 QPR:$src))), (v2i64 QPR:$src)>; 5597def : Pat<(v2i64 (bitconvert (v8i16 QPR:$src))), (v2i64 QPR:$src)>; 5598def : Pat<(v2i64 (bitconvert (v16i8 QPR:$src))), (v2i64 QPR:$src)>; 5599def : Pat<(v2i64 (bitconvert (v2f64 QPR:$src))), (v2i64 QPR:$src)>; 5600def : Pat<(v2i64 (bitconvert (v4f32 QPR:$src))), (v2i64 QPR:$src)>; 5601def : Pat<(v4i32 (bitconvert (v2i64 QPR:$src))), (v4i32 QPR:$src)>; 5602def : Pat<(v4i32 (bitconvert (v8i16 QPR:$src))), (v4i32 QPR:$src)>; 5603def : Pat<(v4i32 (bitconvert (v16i8 QPR:$src))), (v4i32 QPR:$src)>; 5604def : Pat<(v4i32 (bitconvert (v2f64 QPR:$src))), (v4i32 QPR:$src)>; 5605def : Pat<(v4i32 (bitconvert (v4f32 QPR:$src))), (v4i32 QPR:$src)>; 5606def : Pat<(v8i16 (bitconvert (v2i64 QPR:$src))), (v8i16 QPR:$src)>; 5607def : Pat<(v8i16 (bitconvert (v4i32 QPR:$src))), (v8i16 QPR:$src)>; 5608def : Pat<(v8i16 (bitconvert (v16i8 QPR:$src))), (v8i16 QPR:$src)>; 5609def : Pat<(v8i16 (bitconvert (v2f64 QPR:$src))), (v8i16 QPR:$src)>; 5610def : Pat<(v8i16 (bitconvert (v4f32 QPR:$src))), (v8i16 QPR:$src)>; 5611def : Pat<(v16i8 (bitconvert (v2i64 QPR:$src))), (v16i8 QPR:$src)>; 5612def : Pat<(v16i8 (bitconvert (v4i32 QPR:$src))), (v16i8 QPR:$src)>; 5613def : Pat<(v16i8 (bitconvert (v8i16 QPR:$src))), (v16i8 QPR:$src)>; 5614def : Pat<(v16i8 (bitconvert (v2f64 QPR:$src))), (v16i8 QPR:$src)>; 5615def : Pat<(v16i8 (bitconvert (v4f32 QPR:$src))), (v16i8 QPR:$src)>; 5616def : Pat<(v4f32 (bitconvert (v2i64 QPR:$src))), (v4f32 QPR:$src)>; 5617def : Pat<(v4f32 (bitconvert (v4i32 QPR:$src))), (v4f32 QPR:$src)>; 5618def : Pat<(v4f32 (bitconvert (v8i16 QPR:$src))), (v4f32 QPR:$src)>; 5619def : Pat<(v4f32 (bitconvert (v16i8 QPR:$src))), (v4f32 QPR:$src)>; 5620def : Pat<(v4f32 (bitconvert (v2f64 QPR:$src))), (v4f32 QPR:$src)>; 5621def : Pat<(v2f64 (bitconvert (v2i64 QPR:$src))), (v2f64 QPR:$src)>; 5622def : Pat<(v2f64 (bitconvert (v4i32 QPR:$src))), (v2f64 QPR:$src)>; 5623def : Pat<(v2f64 (bitconvert (v8i16 QPR:$src))), (v2f64 QPR:$src)>; 5624def : Pat<(v2f64 (bitconvert (v16i8 QPR:$src))), (v2f64 QPR:$src)>; 5625def : Pat<(v2f64 (bitconvert (v4f32 QPR:$src))), (v2f64 QPR:$src)>; 5626 5627// Vector lengthening move with load, matching extending loads. 5628 5629// extload, zextload and sextload for a standard lengthening load. Example: 5630// Lengthen_Single<"8", "i16", "i8"> = Pat<(v8i16 (extloadvi8 addrmode5:$addr)) 5631// (VMOVLuv8i16 (VLDRD addrmode5:$addr))>; 5632multiclass Lengthen_Single<string DestLanes, string DestTy, string SrcTy> { 5633 def _Any : Pat<(!cast<ValueType>("v" # DestLanes # DestTy) 5634 (!cast<PatFrag>("extloadv" # SrcTy) addrmode5:$addr)), 5635 (!cast<Instruction>("VMOVLuv" # DestLanes # DestTy) 5636 (VLDRD addrmode5:$addr))>; 5637 def _Z : Pat<(!cast<ValueType>("v" # DestLanes # DestTy) 5638 (!cast<PatFrag>("zextloadv" # SrcTy) addrmode5:$addr)), 5639 (!cast<Instruction>("VMOVLuv" # DestLanes # DestTy) 5640 (VLDRD addrmode5:$addr))>; 5641 def _S : Pat<(!cast<ValueType>("v" # DestLanes # DestTy) 5642 (!cast<PatFrag>("sextloadv" # SrcTy) addrmode5:$addr)), 5643 (!cast<Instruction>("VMOVLsv" # DestLanes # DestTy) 5644 (VLDRD addrmode5:$addr))>; 5645} 5646 5647// extload, zextload and sextload for a lengthening load which only uses 5648// half the lanes available. Example: 5649// Lengthen_HalfSingle<"4", "i16", "8", "i16", "i8"> = 5650// Pat<(v4i16 (extloadvi8 addrmode5:$addr)) 5651// (EXTRACT_SUBREG (VMOVLuv8i16 (INSERT_SUBREG (f64 (IMPLICIT_DEF)), 5652// (VLDRS addrmode5:$addr), 5653// ssub_0)), 5654// dsub_0)>; 5655multiclass Lengthen_HalfSingle<string DestLanes, string DestTy, string SrcTy, 5656 string InsnLanes, string InsnTy> { 5657 def _Any : Pat<(!cast<ValueType>("v" # DestLanes # DestTy) 5658 (!cast<PatFrag>("extloadv" # SrcTy) addrmode5:$addr)), 5659 (EXTRACT_SUBREG (!cast<Instruction>("VMOVLuv" # InsnLanes # InsnTy) 5660 (INSERT_SUBREG (f64 (IMPLICIT_DEF)), (VLDRS addrmode5:$addr), ssub_0)), 5661 dsub_0)>; 5662 def _Z : Pat<(!cast<ValueType>("v" # DestLanes # DestTy) 5663 (!cast<PatFrag>("zextloadv" # SrcTy) addrmode5:$addr)), 5664 (EXTRACT_SUBREG (!cast<Instruction>("VMOVLuv" # InsnLanes # InsnTy) 5665 (INSERT_SUBREG (f64 (IMPLICIT_DEF)), (VLDRS addrmode5:$addr), ssub_0)), 5666 dsub_0)>; 5667 def _S : Pat<(!cast<ValueType>("v" # DestLanes # DestTy) 5668 (!cast<PatFrag>("sextloadv" # SrcTy) addrmode5:$addr)), 5669 (EXTRACT_SUBREG (!cast<Instruction>("VMOVLsv" # InsnLanes # InsnTy) 5670 (INSERT_SUBREG (f64 (IMPLICIT_DEF)), (VLDRS addrmode5:$addr), ssub_0)), 5671 dsub_0)>; 5672} 5673 5674// extload, zextload and sextload for a lengthening load followed by another 5675// lengthening load, to quadruple the initial length. 5676// Lengthen_Double<"4", "i32", "i8", "8", "i16", "4", "i32", qsub_0> = 5677// Pat<(v4i32 (extloadvi8 addrmode5:$addr)) 5678// (EXTRACT_SUBREG (VMOVLuv4i32 5679// (EXTRACT_SUBREG (VMOVLuv8i16 (INSERT_SUBREG (f64 (IMPLICIT_DEF)), 5680// (VLDRS addrmode5:$addr), 5681// ssub_0)), 5682// dsub_0)), 5683// qsub_0)>; 5684multiclass Lengthen_Double<string DestLanes, string DestTy, string SrcTy, 5685 string Insn1Lanes, string Insn1Ty, string Insn2Lanes, 5686 string Insn2Ty, SubRegIndex RegType> { 5687 def _Any : Pat<(!cast<ValueType>("v" # DestLanes # DestTy) 5688 (!cast<PatFrag>("extloadv" # SrcTy) addrmode5:$addr)), 5689 (EXTRACT_SUBREG (!cast<Instruction>("VMOVLuv" # Insn2Lanes # Insn2Ty) 5690 (EXTRACT_SUBREG (!cast<Instruction>("VMOVLuv" # Insn1Lanes # Insn1Ty) 5691 (INSERT_SUBREG (f64 (IMPLICIT_DEF)), (VLDRS addrmode5:$addr), 5692 ssub_0)), dsub_0)), 5693 RegType)>; 5694 def _Z : Pat<(!cast<ValueType>("v" # DestLanes # DestTy) 5695 (!cast<PatFrag>("zextloadv" # SrcTy) addrmode5:$addr)), 5696 (EXTRACT_SUBREG (!cast<Instruction>("VMOVLuv" # Insn2Lanes # Insn2Ty) 5697 (EXTRACT_SUBREG (!cast<Instruction>("VMOVLuv" # Insn1Lanes # Insn1Ty) 5698 (INSERT_SUBREG (f64 (IMPLICIT_DEF)), (VLDRS addrmode5:$addr), 5699 ssub_0)), dsub_0)), 5700 RegType)>; 5701 def _S : Pat<(!cast<ValueType>("v" # DestLanes # DestTy) 5702 (!cast<PatFrag>("sextloadv" # SrcTy) addrmode5:$addr)), 5703 (EXTRACT_SUBREG (!cast<Instruction>("VMOVLsv" # Insn2Lanes # Insn2Ty) 5704 (EXTRACT_SUBREG (!cast<Instruction>("VMOVLsv" # Insn1Lanes # Insn1Ty) 5705 (INSERT_SUBREG (f64 (IMPLICIT_DEF)), (VLDRS addrmode5:$addr), 5706 ssub_0)), dsub_0)), 5707 RegType)>; 5708} 5709 5710defm : Lengthen_Single<"8", "i16", "i8">; // v8i8 -> v8i16 5711defm : Lengthen_Single<"4", "i32", "i16">; // v4i16 -> v4i32 5712defm : Lengthen_Single<"2", "i64", "i32">; // v2i32 -> v2i64 5713 5714defm : Lengthen_HalfSingle<"4", "i16", "i8", "8", "i16">; // v4i8 -> v4i16 5715defm : Lengthen_HalfSingle<"2", "i16", "i8", "8", "i16">; // v2i8 -> v2i16 5716defm : Lengthen_HalfSingle<"2", "i32", "i16", "4", "i32">; // v2i16 -> v2i32 5717 5718// Double lengthening - v4i8 -> v4i16 -> v4i32 5719defm : Lengthen_Double<"4", "i32", "i8", "8", "i16", "4", "i32", qsub_0>; 5720// v2i8 -> v2i16 -> v2i32 5721defm : Lengthen_Double<"2", "i32", "i8", "8", "i16", "4", "i32", dsub_0>; 5722// v2i16 -> v2i32 -> v2i64 5723defm : Lengthen_Double<"2", "i64", "i16", "4", "i32", "2", "i64", qsub_0>; 5724 5725// Triple lengthening - v2i8 -> v2i16 -> v2i32 -> v2i64 5726def : Pat<(v2i64 (extloadvi8 addrmode5:$addr)), 5727 (VMOVLuv2i64 (EXTRACT_SUBREG (VMOVLuv4i32 (EXTRACT_SUBREG (VMOVLuv8i16 5728 (INSERT_SUBREG (f64 (IMPLICIT_DEF)), (VLDRS addrmode5:$addr), ssub_0)), 5729 dsub_0)), dsub_0))>; 5730def : Pat<(v2i64 (zextloadvi8 addrmode5:$addr)), 5731 (VMOVLuv2i64 (EXTRACT_SUBREG (VMOVLuv4i32 (EXTRACT_SUBREG (VMOVLuv8i16 5732 (INSERT_SUBREG (f64 (IMPLICIT_DEF)), (VLDRS addrmode5:$addr), ssub_0)), 5733 dsub_0)), dsub_0))>; 5734def : Pat<(v2i64 (sextloadvi8 addrmode5:$addr)), 5735 (VMOVLsv2i64 (EXTRACT_SUBREG (VMOVLsv4i32 (EXTRACT_SUBREG (VMOVLsv8i16 5736 (INSERT_SUBREG (f64 (IMPLICIT_DEF)), (VLDRS addrmode5:$addr), ssub_0)), 5737 dsub_0)), dsub_0))>; 5738 5739//===----------------------------------------------------------------------===// 5740// Assembler aliases 5741// 5742 5743def : VFP2InstAlias<"fmdhr${p} $Dd, $Rn", 5744 (VSETLNi32 DPR:$Dd, GPR:$Rn, 1, pred:$p)>; 5745def : VFP2InstAlias<"fmdlr${p} $Dd, $Rn", 5746 (VSETLNi32 DPR:$Dd, GPR:$Rn, 0, pred:$p)>; 5747 5748 5749// VADD two-operand aliases. 5750def : NEONInstAlias<"vadd${p}.i8 $Vdn, $Vm", 5751 (VADDv16i8 QPR:$Vdn, QPR:$Vdn, QPR:$Vm, pred:$p)>; 5752def : NEONInstAlias<"vadd${p}.i16 $Vdn, $Vm", 5753 (VADDv8i16 QPR:$Vdn, QPR:$Vdn, QPR:$Vm, pred:$p)>; 5754def : NEONInstAlias<"vadd${p}.i32 $Vdn, $Vm", 5755 (VADDv4i32 QPR:$Vdn, QPR:$Vdn, QPR:$Vm, pred:$p)>; 5756def : NEONInstAlias<"vadd${p}.i64 $Vdn, $Vm", 5757 (VADDv2i64 QPR:$Vdn, QPR:$Vdn, QPR:$Vm, pred:$p)>; 5758 5759def : NEONInstAlias<"vadd${p}.i8 $Vdn, $Vm", 5760 (VADDv8i8 DPR:$Vdn, DPR:$Vdn, DPR:$Vm, pred:$p)>; 5761def : NEONInstAlias<"vadd${p}.i16 $Vdn, $Vm", 5762 (VADDv4i16 DPR:$Vdn, DPR:$Vdn, DPR:$Vm, pred:$p)>; 5763def : NEONInstAlias<"vadd${p}.i32 $Vdn, $Vm", 5764 (VADDv2i32 DPR:$Vdn, DPR:$Vdn, DPR:$Vm, pred:$p)>; 5765def : NEONInstAlias<"vadd${p}.i64 $Vdn, $Vm", 5766 (VADDv1i64 DPR:$Vdn, DPR:$Vdn, DPR:$Vm, pred:$p)>; 5767 5768def : NEONInstAlias<"vadd${p}.f32 $Vdn, $Vm", 5769 (VADDfd DPR:$Vdn, DPR:$Vdn, DPR:$Vm, pred:$p)>; 5770def : NEONInstAlias<"vadd${p}.f32 $Vdn, $Vm", 5771 (VADDfq QPR:$Vdn, QPR:$Vdn, QPR:$Vm, pred:$p)>; 5772 5773// VSUB two-operand aliases. 5774def : NEONInstAlias<"vsub${p}.i8 $Vdn, $Vm", 5775 (VSUBv16i8 QPR:$Vdn, QPR:$Vdn, QPR:$Vm, pred:$p)>; 5776def : NEONInstAlias<"vsub${p}.i16 $Vdn, $Vm", 5777 (VSUBv8i16 QPR:$Vdn, QPR:$Vdn, QPR:$Vm, pred:$p)>; 5778def : NEONInstAlias<"vsub${p}.i32 $Vdn, $Vm", 5779 (VSUBv4i32 QPR:$Vdn, QPR:$Vdn, QPR:$Vm, pred:$p)>; 5780def : NEONInstAlias<"vsub${p}.i64 $Vdn, $Vm", 5781 (VSUBv2i64 QPR:$Vdn, QPR:$Vdn, QPR:$Vm, pred:$p)>; 5782 5783def : NEONInstAlias<"vsub${p}.i8 $Vdn, $Vm", 5784 (VSUBv8i8 DPR:$Vdn, DPR:$Vdn, DPR:$Vm, pred:$p)>; 5785def : NEONInstAlias<"vsub${p}.i16 $Vdn, $Vm", 5786 (VSUBv4i16 DPR:$Vdn, DPR:$Vdn, DPR:$Vm, pred:$p)>; 5787def : NEONInstAlias<"vsub${p}.i32 $Vdn, $Vm", 5788 (VSUBv2i32 DPR:$Vdn, DPR:$Vdn, DPR:$Vm, pred:$p)>; 5789def : NEONInstAlias<"vsub${p}.i64 $Vdn, $Vm", 5790 (VSUBv1i64 DPR:$Vdn, DPR:$Vdn, DPR:$Vm, pred:$p)>; 5791 5792def : NEONInstAlias<"vsub${p}.f32 $Vdn, $Vm", 5793 (VSUBfd DPR:$Vdn, DPR:$Vdn, DPR:$Vm, pred:$p)>; 5794def : NEONInstAlias<"vsub${p}.f32 $Vdn, $Vm", 5795 (VSUBfq QPR:$Vdn, QPR:$Vdn, QPR:$Vm, pred:$p)>; 5796 5797// VADDW two-operand aliases. 5798def : NEONInstAlias<"vaddw${p}.s8 $Vdn, $Vm", 5799 (VADDWsv8i16 QPR:$Vdn, QPR:$Vdn, DPR:$Vm, pred:$p)>; 5800def : NEONInstAlias<"vaddw${p}.s16 $Vdn, $Vm", 5801 (VADDWsv4i32 QPR:$Vdn, QPR:$Vdn, DPR:$Vm, pred:$p)>; 5802def : NEONInstAlias<"vaddw${p}.s32 $Vdn, $Vm", 5803 (VADDWsv2i64 QPR:$Vdn, QPR:$Vdn, DPR:$Vm, pred:$p)>; 5804def : NEONInstAlias<"vaddw${p}.u8 $Vdn, $Vm", 5805 (VADDWuv8i16 QPR:$Vdn, QPR:$Vdn, DPR:$Vm, pred:$p)>; 5806def : NEONInstAlias<"vaddw${p}.u16 $Vdn, $Vm", 5807 (VADDWuv4i32 QPR:$Vdn, QPR:$Vdn, DPR:$Vm, pred:$p)>; 5808def : NEONInstAlias<"vaddw${p}.u32 $Vdn, $Vm", 5809 (VADDWuv2i64 QPR:$Vdn, QPR:$Vdn, DPR:$Vm, pred:$p)>; 5810 5811// VAND/VBIC/VEOR/VORR accept but do not require a type suffix. 5812defm : NEONDTAnyInstAlias<"vand${p}", "$Vd, $Vn, $Vm", 5813 (VANDd DPR:$Vd, DPR:$Vn, DPR:$Vm, pred:$p)>; 5814defm : NEONDTAnyInstAlias<"vand${p}", "$Vd, $Vn, $Vm", 5815 (VANDq QPR:$Vd, QPR:$Vn, QPR:$Vm, pred:$p)>; 5816defm : NEONDTAnyInstAlias<"vbic${p}", "$Vd, $Vn, $Vm", 5817 (VBICd DPR:$Vd, DPR:$Vn, DPR:$Vm, pred:$p)>; 5818defm : NEONDTAnyInstAlias<"vbic${p}", "$Vd, $Vn, $Vm", 5819 (VBICq QPR:$Vd, QPR:$Vn, QPR:$Vm, pred:$p)>; 5820defm : NEONDTAnyInstAlias<"veor${p}", "$Vd, $Vn, $Vm", 5821 (VEORd DPR:$Vd, DPR:$Vn, DPR:$Vm, pred:$p)>; 5822defm : NEONDTAnyInstAlias<"veor${p}", "$Vd, $Vn, $Vm", 5823 (VEORq QPR:$Vd, QPR:$Vn, QPR:$Vm, pred:$p)>; 5824defm : NEONDTAnyInstAlias<"vorr${p}", "$Vd, $Vn, $Vm", 5825 (VORRd DPR:$Vd, DPR:$Vn, DPR:$Vm, pred:$p)>; 5826defm : NEONDTAnyInstAlias<"vorr${p}", "$Vd, $Vn, $Vm", 5827 (VORRq QPR:$Vd, QPR:$Vn, QPR:$Vm, pred:$p)>; 5828// ... two-operand aliases 5829def : NEONInstAlias<"vand${p} $Vdn, $Vm", 5830 (VANDd DPR:$Vdn, DPR:$Vdn, DPR:$Vm, pred:$p)>; 5831def : NEONInstAlias<"vand${p} $Vdn, $Vm", 5832 (VANDq QPR:$Vdn, QPR:$Vdn, QPR:$Vm, pred:$p)>; 5833def : NEONInstAlias<"vbic${p} $Vdn, $Vm", 5834 (VBICd DPR:$Vdn, DPR:$Vdn, DPR:$Vm, pred:$p)>; 5835def : NEONInstAlias<"vbic${p} $Vdn, $Vm", 5836 (VBICq QPR:$Vdn, QPR:$Vdn, QPR:$Vm, pred:$p)>; 5837def : NEONInstAlias<"veor${p} $Vdn, $Vm", 5838 (VEORd DPR:$Vdn, DPR:$Vdn, DPR:$Vm, pred:$p)>; 5839def : NEONInstAlias<"veor${p} $Vdn, $Vm", 5840 (VEORq QPR:$Vdn, QPR:$Vdn, QPR:$Vm, pred:$p)>; 5841def : NEONInstAlias<"vorr${p} $Vdn, $Vm", 5842 (VORRd DPR:$Vdn, DPR:$Vdn, DPR:$Vm, pred:$p)>; 5843def : NEONInstAlias<"vorr${p} $Vdn, $Vm", 5844 (VORRq QPR:$Vdn, QPR:$Vdn, QPR:$Vm, pred:$p)>; 5845 5846defm : NEONDTAnyInstAlias<"vand${p}", "$Vdn, $Vm", 5847 (VANDd DPR:$Vdn, DPR:$Vdn, DPR:$Vm, pred:$p)>; 5848defm : NEONDTAnyInstAlias<"vand${p}", "$Vdn, $Vm", 5849 (VANDq QPR:$Vdn, QPR:$Vdn, QPR:$Vm, pred:$p)>; 5850defm : NEONDTAnyInstAlias<"veor${p}", "$Vdn, $Vm", 5851 (VEORd DPR:$Vdn, DPR:$Vdn, DPR:$Vm, pred:$p)>; 5852defm : NEONDTAnyInstAlias<"veor${p}", "$Vdn, $Vm", 5853 (VEORq QPR:$Vdn, QPR:$Vdn, QPR:$Vm, pred:$p)>; 5854defm : NEONDTAnyInstAlias<"vorr${p}", "$Vdn, $Vm", 5855 (VORRd DPR:$Vdn, DPR:$Vdn, DPR:$Vm, pred:$p)>; 5856defm : NEONDTAnyInstAlias<"vorr${p}", "$Vdn, $Vm", 5857 (VORRq QPR:$Vdn, QPR:$Vdn, QPR:$Vm, pred:$p)>; 5858 5859// VMUL two-operand aliases. 5860def : NEONInstAlias<"vmul${p}.p8 $Qdn, $Qm", 5861 (VMULpq QPR:$Qdn, QPR:$Qdn, QPR:$Qm, pred:$p)>; 5862def : NEONInstAlias<"vmul${p}.i8 $Qdn, $Qm", 5863 (VMULv16i8 QPR:$Qdn, QPR:$Qdn, QPR:$Qm, pred:$p)>; 5864def : NEONInstAlias<"vmul${p}.i16 $Qdn, $Qm", 5865 (VMULv8i16 QPR:$Qdn, QPR:$Qdn, QPR:$Qm, pred:$p)>; 5866def : NEONInstAlias<"vmul${p}.i32 $Qdn, $Qm", 5867 (VMULv4i32 QPR:$Qdn, QPR:$Qdn, QPR:$Qm, pred:$p)>; 5868 5869def : NEONInstAlias<"vmul${p}.p8 $Ddn, $Dm", 5870 (VMULpd DPR:$Ddn, DPR:$Ddn, DPR:$Dm, pred:$p)>; 5871def : NEONInstAlias<"vmul${p}.i8 $Ddn, $Dm", 5872 (VMULv8i8 DPR:$Ddn, DPR:$Ddn, DPR:$Dm, pred:$p)>; 5873def : NEONInstAlias<"vmul${p}.i16 $Ddn, $Dm", 5874 (VMULv4i16 DPR:$Ddn, DPR:$Ddn, DPR:$Dm, pred:$p)>; 5875def : NEONInstAlias<"vmul${p}.i32 $Ddn, $Dm", 5876 (VMULv2i32 DPR:$Ddn, DPR:$Ddn, DPR:$Dm, pred:$p)>; 5877 5878def : NEONInstAlias<"vmul${p}.f32 $Qdn, $Qm", 5879 (VMULfq QPR:$Qdn, QPR:$Qdn, QPR:$Qm, pred:$p)>; 5880def : NEONInstAlias<"vmul${p}.f32 $Ddn, $Dm", 5881 (VMULfd DPR:$Ddn, DPR:$Ddn, DPR:$Dm, pred:$p)>; 5882 5883def : NEONInstAlias<"vmul${p}.i16 $Ddn, $Dm$lane", 5884 (VMULslv4i16 DPR:$Ddn, DPR:$Ddn, DPR_8:$Dm, 5885 VectorIndex16:$lane, pred:$p)>; 5886def : NEONInstAlias<"vmul${p}.i16 $Qdn, $Dm$lane", 5887 (VMULslv8i16 QPR:$Qdn, QPR:$Qdn, DPR_8:$Dm, 5888 VectorIndex16:$lane, pred:$p)>; 5889 5890def : NEONInstAlias<"vmul${p}.i32 $Ddn, $Dm$lane", 5891 (VMULslv2i32 DPR:$Ddn, DPR:$Ddn, DPR_VFP2:$Dm, 5892 VectorIndex32:$lane, pred:$p)>; 5893def : NEONInstAlias<"vmul${p}.i32 $Qdn, $Dm$lane", 5894 (VMULslv4i32 QPR:$Qdn, QPR:$Qdn, DPR_VFP2:$Dm, 5895 VectorIndex32:$lane, pred:$p)>; 5896 5897def : NEONInstAlias<"vmul${p}.f32 $Ddn, $Dm$lane", 5898 (VMULslfd DPR:$Ddn, DPR:$Ddn, DPR_VFP2:$Dm, 5899 VectorIndex32:$lane, pred:$p)>; 5900def : NEONInstAlias<"vmul${p}.f32 $Qdn, $Dm$lane", 5901 (VMULslfq QPR:$Qdn, QPR:$Qdn, DPR_VFP2:$Dm, 5902 VectorIndex32:$lane, pred:$p)>; 5903 5904// VQADD (register) two-operand aliases. 5905def : NEONInstAlias<"vqadd${p}.s8 $Vdn, $Vm", 5906 (VQADDsv8i8 DPR:$Vdn, DPR:$Vdn, DPR:$Vm, pred:$p)>; 5907def : NEONInstAlias<"vqadd${p}.s16 $Vdn, $Vm", 5908 (VQADDsv4i16 DPR:$Vdn, DPR:$Vdn, DPR:$Vm, pred:$p)>; 5909def : NEONInstAlias<"vqadd${p}.s32 $Vdn, $Vm", 5910 (VQADDsv2i32 DPR:$Vdn, DPR:$Vdn, DPR:$Vm, pred:$p)>; 5911def : NEONInstAlias<"vqadd${p}.s64 $Vdn, $Vm", 5912 (VQADDsv1i64 DPR:$Vdn, DPR:$Vdn, DPR:$Vm, pred:$p)>; 5913def : NEONInstAlias<"vqadd${p}.u8 $Vdn, $Vm", 5914 (VQADDuv8i8 DPR:$Vdn, DPR:$Vdn, DPR:$Vm, pred:$p)>; 5915def : NEONInstAlias<"vqadd${p}.u16 $Vdn, $Vm", 5916 (VQADDuv4i16 DPR:$Vdn, DPR:$Vdn, DPR:$Vm, pred:$p)>; 5917def : NEONInstAlias<"vqadd${p}.u32 $Vdn, $Vm", 5918 (VQADDuv2i32 DPR:$Vdn, DPR:$Vdn, DPR:$Vm, pred:$p)>; 5919def : NEONInstAlias<"vqadd${p}.u64 $Vdn, $Vm", 5920 (VQADDuv1i64 DPR:$Vdn, DPR:$Vdn, DPR:$Vm, pred:$p)>; 5921 5922def : NEONInstAlias<"vqadd${p}.s8 $Vdn, $Vm", 5923 (VQADDsv16i8 QPR:$Vdn, QPR:$Vdn, QPR:$Vm, pred:$p)>; 5924def : NEONInstAlias<"vqadd${p}.s16 $Vdn, $Vm", 5925 (VQADDsv8i16 QPR:$Vdn, QPR:$Vdn, QPR:$Vm, pred:$p)>; 5926def : NEONInstAlias<"vqadd${p}.s32 $Vdn, $Vm", 5927 (VQADDsv4i32 QPR:$Vdn, QPR:$Vdn, QPR:$Vm, pred:$p)>; 5928def : NEONInstAlias<"vqadd${p}.s64 $Vdn, $Vm", 5929 (VQADDsv2i64 QPR:$Vdn, QPR:$Vdn, QPR:$Vm, pred:$p)>; 5930def : NEONInstAlias<"vqadd${p}.u8 $Vdn, $Vm", 5931 (VQADDuv16i8 QPR:$Vdn, QPR:$Vdn, QPR:$Vm, pred:$p)>; 5932def : NEONInstAlias<"vqadd${p}.u16 $Vdn, $Vm", 5933 (VQADDuv8i16 QPR:$Vdn, QPR:$Vdn, QPR:$Vm, pred:$p)>; 5934def : NEONInstAlias<"vqadd${p}.u32 $Vdn, $Vm", 5935 (VQADDuv4i32 QPR:$Vdn, QPR:$Vdn, QPR:$Vm, pred:$p)>; 5936def : NEONInstAlias<"vqadd${p}.u64 $Vdn, $Vm", 5937 (VQADDuv2i64 QPR:$Vdn, QPR:$Vdn, QPR:$Vm, pred:$p)>; 5938 5939// VSHL (immediate) two-operand aliases. 5940def : NEONInstAlias<"vshl${p}.i8 $Vdn, $imm", 5941 (VSHLiv8i8 DPR:$Vdn, DPR:$Vdn, imm0_7:$imm, pred:$p)>; 5942def : NEONInstAlias<"vshl${p}.i16 $Vdn, $imm", 5943 (VSHLiv4i16 DPR:$Vdn, DPR:$Vdn, imm0_15:$imm, pred:$p)>; 5944def : NEONInstAlias<"vshl${p}.i32 $Vdn, $imm", 5945 (VSHLiv2i32 DPR:$Vdn, DPR:$Vdn, imm0_31:$imm, pred:$p)>; 5946def : NEONInstAlias<"vshl${p}.i64 $Vdn, $imm", 5947 (VSHLiv1i64 DPR:$Vdn, DPR:$Vdn, imm0_63:$imm, pred:$p)>; 5948 5949def : NEONInstAlias<"vshl${p}.i8 $Vdn, $imm", 5950 (VSHLiv16i8 QPR:$Vdn, QPR:$Vdn, imm0_7:$imm, pred:$p)>; 5951def : NEONInstAlias<"vshl${p}.i16 $Vdn, $imm", 5952 (VSHLiv8i16 QPR:$Vdn, QPR:$Vdn, imm0_15:$imm, pred:$p)>; 5953def : NEONInstAlias<"vshl${p}.i32 $Vdn, $imm", 5954 (VSHLiv4i32 QPR:$Vdn, QPR:$Vdn, imm0_31:$imm, pred:$p)>; 5955def : NEONInstAlias<"vshl${p}.i64 $Vdn, $imm", 5956 (VSHLiv2i64 QPR:$Vdn, QPR:$Vdn, imm0_63:$imm, pred:$p)>; 5957 5958// VSHL (register) two-operand aliases. 5959def : NEONInstAlias<"vshl${p}.s8 $Vdn, $Vm", 5960 (VSHLsv8i8 DPR:$Vdn, DPR:$Vdn, DPR:$Vm, pred:$p)>; 5961def : NEONInstAlias<"vshl${p}.s16 $Vdn, $Vm", 5962 (VSHLsv4i16 DPR:$Vdn, DPR:$Vdn, DPR:$Vm, pred:$p)>; 5963def : NEONInstAlias<"vshl${p}.s32 $Vdn, $Vm", 5964 (VSHLsv2i32 DPR:$Vdn, DPR:$Vdn, DPR:$Vm, pred:$p)>; 5965def : NEONInstAlias<"vshl${p}.s64 $Vdn, $Vm", 5966 (VSHLsv1i64 DPR:$Vdn, DPR:$Vdn, DPR:$Vm, pred:$p)>; 5967def : NEONInstAlias<"vshl${p}.u8 $Vdn, $Vm", 5968 (VSHLuv8i8 DPR:$Vdn, DPR:$Vdn, DPR:$Vm, pred:$p)>; 5969def : NEONInstAlias<"vshl${p}.u16 $Vdn, $Vm", 5970 (VSHLuv4i16 DPR:$Vdn, DPR:$Vdn, DPR:$Vm, pred:$p)>; 5971def : NEONInstAlias<"vshl${p}.u32 $Vdn, $Vm", 5972 (VSHLuv2i32 DPR:$Vdn, DPR:$Vdn, DPR:$Vm, pred:$p)>; 5973def : NEONInstAlias<"vshl${p}.u64 $Vdn, $Vm", 5974 (VSHLuv1i64 DPR:$Vdn, DPR:$Vdn, DPR:$Vm, pred:$p)>; 5975 5976def : NEONInstAlias<"vshl${p}.s8 $Vdn, $Vm", 5977 (VSHLsv16i8 QPR:$Vdn, QPR:$Vdn, QPR:$Vm, pred:$p)>; 5978def : NEONInstAlias<"vshl${p}.s16 $Vdn, $Vm", 5979 (VSHLsv8i16 QPR:$Vdn, QPR:$Vdn, QPR:$Vm, pred:$p)>; 5980def : NEONInstAlias<"vshl${p}.s32 $Vdn, $Vm", 5981 (VSHLsv4i32 QPR:$Vdn, QPR:$Vdn, QPR:$Vm, pred:$p)>; 5982def : NEONInstAlias<"vshl${p}.s64 $Vdn, $Vm", 5983 (VSHLsv2i64 QPR:$Vdn, QPR:$Vdn, QPR:$Vm, pred:$p)>; 5984def : NEONInstAlias<"vshl${p}.u8 $Vdn, $Vm", 5985 (VSHLuv16i8 QPR:$Vdn, QPR:$Vdn, QPR:$Vm, pred:$p)>; 5986def : NEONInstAlias<"vshl${p}.u16 $Vdn, $Vm", 5987 (VSHLuv8i16 QPR:$Vdn, QPR:$Vdn, QPR:$Vm, pred:$p)>; 5988def : NEONInstAlias<"vshl${p}.u32 $Vdn, $Vm", 5989 (VSHLuv4i32 QPR:$Vdn, QPR:$Vdn, QPR:$Vm, pred:$p)>; 5990def : NEONInstAlias<"vshl${p}.u64 $Vdn, $Vm", 5991 (VSHLuv2i64 QPR:$Vdn, QPR:$Vdn, QPR:$Vm, pred:$p)>; 5992 5993// VSHL (immediate) two-operand aliases. 5994def : NEONInstAlias<"vshr${p}.s8 $Vdn, $imm", 5995 (VSHRsv8i8 DPR:$Vdn, DPR:$Vdn, shr_imm8:$imm, pred:$p)>; 5996def : NEONInstAlias<"vshr${p}.s16 $Vdn, $imm", 5997 (VSHRsv4i16 DPR:$Vdn, DPR:$Vdn, shr_imm16:$imm, pred:$p)>; 5998def : NEONInstAlias<"vshr${p}.s32 $Vdn, $imm", 5999 (VSHRsv2i32 DPR:$Vdn, DPR:$Vdn, shr_imm32:$imm, pred:$p)>; 6000def : NEONInstAlias<"vshr${p}.s64 $Vdn, $imm", 6001 (VSHRsv1i64 DPR:$Vdn, DPR:$Vdn, shr_imm64:$imm, pred:$p)>; 6002 6003def : NEONInstAlias<"vshr${p}.s8 $Vdn, $imm", 6004 (VSHRsv16i8 QPR:$Vdn, QPR:$Vdn, shr_imm8:$imm, pred:$p)>; 6005def : NEONInstAlias<"vshr${p}.s16 $Vdn, $imm", 6006 (VSHRsv8i16 QPR:$Vdn, QPR:$Vdn, shr_imm16:$imm, pred:$p)>; 6007def : NEONInstAlias<"vshr${p}.s32 $Vdn, $imm", 6008 (VSHRsv4i32 QPR:$Vdn, QPR:$Vdn, shr_imm32:$imm, pred:$p)>; 6009def : NEONInstAlias<"vshr${p}.s64 $Vdn, $imm", 6010 (VSHRsv2i64 QPR:$Vdn, QPR:$Vdn, shr_imm64:$imm, pred:$p)>; 6011 6012def : NEONInstAlias<"vshr${p}.u8 $Vdn, $imm", 6013 (VSHRuv8i8 DPR:$Vdn, DPR:$Vdn, shr_imm8:$imm, pred:$p)>; 6014def : NEONInstAlias<"vshr${p}.u16 $Vdn, $imm", 6015 (VSHRuv4i16 DPR:$Vdn, DPR:$Vdn, shr_imm16:$imm, pred:$p)>; 6016def : NEONInstAlias<"vshr${p}.u32 $Vdn, $imm", 6017 (VSHRuv2i32 DPR:$Vdn, DPR:$Vdn, shr_imm32:$imm, pred:$p)>; 6018def : NEONInstAlias<"vshr${p}.u64 $Vdn, $imm", 6019 (VSHRuv1i64 DPR:$Vdn, DPR:$Vdn, shr_imm64:$imm, pred:$p)>; 6020 6021def : NEONInstAlias<"vshr${p}.u8 $Vdn, $imm", 6022 (VSHRuv16i8 QPR:$Vdn, QPR:$Vdn, shr_imm8:$imm, pred:$p)>; 6023def : NEONInstAlias<"vshr${p}.u16 $Vdn, $imm", 6024 (VSHRuv8i16 QPR:$Vdn, QPR:$Vdn, shr_imm16:$imm, pred:$p)>; 6025def : NEONInstAlias<"vshr${p}.u32 $Vdn, $imm", 6026 (VSHRuv4i32 QPR:$Vdn, QPR:$Vdn, shr_imm32:$imm, pred:$p)>; 6027def : NEONInstAlias<"vshr${p}.u64 $Vdn, $imm", 6028 (VSHRuv2i64 QPR:$Vdn, QPR:$Vdn, shr_imm64:$imm, pred:$p)>; 6029 6030// VLD1 single-lane pseudo-instructions. These need special handling for 6031// the lane index that an InstAlias can't handle, so we use these instead. 6032def VLD1LNdAsm_8 : NEONDataTypeAsmPseudoInst<"vld1${p}", ".8", "$list, $addr", 6033 (ins VecListOneDByteIndexed:$list, addrmode6:$addr, pred:$p)>; 6034def VLD1LNdAsm_16 : NEONDataTypeAsmPseudoInst<"vld1${p}", ".16", "$list, $addr", 6035 (ins VecListOneDHWordIndexed:$list, addrmode6:$addr, pred:$p)>; 6036def VLD1LNdAsm_32 : NEONDataTypeAsmPseudoInst<"vld1${p}", ".32", "$list, $addr", 6037 (ins VecListOneDWordIndexed:$list, addrmode6:$addr, pred:$p)>; 6038 6039def VLD1LNdWB_fixed_Asm_8 : 6040 NEONDataTypeAsmPseudoInst<"vld1${p}", ".8", "$list, $addr!", 6041 (ins VecListOneDByteIndexed:$list, addrmode6:$addr, pred:$p)>; 6042def VLD1LNdWB_fixed_Asm_16 : 6043 NEONDataTypeAsmPseudoInst<"vld1${p}", ".16", "$list, $addr!", 6044 (ins VecListOneDHWordIndexed:$list, addrmode6:$addr, pred:$p)>; 6045def VLD1LNdWB_fixed_Asm_32 : 6046 NEONDataTypeAsmPseudoInst<"vld1${p}", ".32", "$list, $addr!", 6047 (ins VecListOneDWordIndexed:$list, addrmode6:$addr, pred:$p)>; 6048def VLD1LNdWB_register_Asm_8 : 6049 NEONDataTypeAsmPseudoInst<"vld1${p}", ".8", "$list, $addr, $Rm", 6050 (ins VecListOneDByteIndexed:$list, addrmode6:$addr, 6051 rGPR:$Rm, pred:$p)>; 6052def VLD1LNdWB_register_Asm_16 : 6053 NEONDataTypeAsmPseudoInst<"vld1${p}", ".16", "$list, $addr, $Rm", 6054 (ins VecListOneDHWordIndexed:$list, addrmode6:$addr, 6055 rGPR:$Rm, pred:$p)>; 6056def VLD1LNdWB_register_Asm_32 : 6057 NEONDataTypeAsmPseudoInst<"vld1${p}", ".32", "$list, $addr, $Rm", 6058 (ins VecListOneDWordIndexed:$list, addrmode6:$addr, 6059 rGPR:$Rm, pred:$p)>; 6060 6061 6062// VST1 single-lane pseudo-instructions. These need special handling for 6063// the lane index that an InstAlias can't handle, so we use these instead. 6064def VST1LNdAsm_8 : NEONDataTypeAsmPseudoInst<"vst1${p}", ".8", "$list, $addr", 6065 (ins VecListOneDByteIndexed:$list, addrmode6:$addr, pred:$p)>; 6066def VST1LNdAsm_16 : NEONDataTypeAsmPseudoInst<"vst1${p}", ".16", "$list, $addr", 6067 (ins VecListOneDHWordIndexed:$list, addrmode6:$addr, pred:$p)>; 6068def VST1LNdAsm_32 : NEONDataTypeAsmPseudoInst<"vst1${p}", ".32", "$list, $addr", 6069 (ins VecListOneDWordIndexed:$list, addrmode6:$addr, pred:$p)>; 6070 6071def VST1LNdWB_fixed_Asm_8 : 6072 NEONDataTypeAsmPseudoInst<"vst1${p}", ".8", "$list, $addr!", 6073 (ins VecListOneDByteIndexed:$list, addrmode6:$addr, pred:$p)>; 6074def VST1LNdWB_fixed_Asm_16 : 6075 NEONDataTypeAsmPseudoInst<"vst1${p}", ".16", "$list, $addr!", 6076 (ins VecListOneDHWordIndexed:$list, addrmode6:$addr, pred:$p)>; 6077def VST1LNdWB_fixed_Asm_32 : 6078 NEONDataTypeAsmPseudoInst<"vst1${p}", ".32", "$list, $addr!", 6079 (ins VecListOneDWordIndexed:$list, addrmode6:$addr, pred:$p)>; 6080def VST1LNdWB_register_Asm_8 : 6081 NEONDataTypeAsmPseudoInst<"vst1${p}", ".8", "$list, $addr, $Rm", 6082 (ins VecListOneDByteIndexed:$list, addrmode6:$addr, 6083 rGPR:$Rm, pred:$p)>; 6084def VST1LNdWB_register_Asm_16 : 6085 NEONDataTypeAsmPseudoInst<"vst1${p}", ".16", "$list, $addr, $Rm", 6086 (ins VecListOneDHWordIndexed:$list, addrmode6:$addr, 6087 rGPR:$Rm, pred:$p)>; 6088def VST1LNdWB_register_Asm_32 : 6089 NEONDataTypeAsmPseudoInst<"vst1${p}", ".32", "$list, $addr, $Rm", 6090 (ins VecListOneDWordIndexed:$list, addrmode6:$addr, 6091 rGPR:$Rm, pred:$p)>; 6092 6093// VLD2 single-lane pseudo-instructions. These need special handling for 6094// the lane index that an InstAlias can't handle, so we use these instead. 6095def VLD2LNdAsm_8 : NEONDataTypeAsmPseudoInst<"vld2${p}", ".8", "$list, $addr", 6096 (ins VecListTwoDByteIndexed:$list, addrmode6:$addr, pred:$p)>; 6097def VLD2LNdAsm_16 : NEONDataTypeAsmPseudoInst<"vld2${p}", ".16", "$list, $addr", 6098 (ins VecListTwoDHWordIndexed:$list, addrmode6:$addr, pred:$p)>; 6099def VLD2LNdAsm_32 : NEONDataTypeAsmPseudoInst<"vld2${p}", ".32", "$list, $addr", 6100 (ins VecListTwoDWordIndexed:$list, addrmode6:$addr, pred:$p)>; 6101def VLD2LNqAsm_16 : NEONDataTypeAsmPseudoInst<"vld2${p}", ".16", "$list, $addr", 6102 (ins VecListTwoQHWordIndexed:$list, addrmode6:$addr, pred:$p)>; 6103def VLD2LNqAsm_32 : NEONDataTypeAsmPseudoInst<"vld2${p}", ".32", "$list, $addr", 6104 (ins VecListTwoQWordIndexed:$list, addrmode6:$addr, pred:$p)>; 6105 6106def VLD2LNdWB_fixed_Asm_8 : 6107 NEONDataTypeAsmPseudoInst<"vld2${p}", ".8", "$list, $addr!", 6108 (ins VecListTwoDByteIndexed:$list, addrmode6:$addr, pred:$p)>; 6109def VLD2LNdWB_fixed_Asm_16 : 6110 NEONDataTypeAsmPseudoInst<"vld2${p}", ".16", "$list, $addr!", 6111 (ins VecListTwoDHWordIndexed:$list, addrmode6:$addr, pred:$p)>; 6112def VLD2LNdWB_fixed_Asm_32 : 6113 NEONDataTypeAsmPseudoInst<"vld2${p}", ".32", "$list, $addr!", 6114 (ins VecListTwoDWordIndexed:$list, addrmode6:$addr, pred:$p)>; 6115def VLD2LNqWB_fixed_Asm_16 : 6116 NEONDataTypeAsmPseudoInst<"vld2${p}", ".16", "$list, $addr!", 6117 (ins VecListTwoQHWordIndexed:$list, addrmode6:$addr, pred:$p)>; 6118def VLD2LNqWB_fixed_Asm_32 : 6119 NEONDataTypeAsmPseudoInst<"vld2${p}", ".32", "$list, $addr!", 6120 (ins VecListTwoQWordIndexed:$list, addrmode6:$addr, pred:$p)>; 6121def VLD2LNdWB_register_Asm_8 : 6122 NEONDataTypeAsmPseudoInst<"vld2${p}", ".8", "$list, $addr, $Rm", 6123 (ins VecListTwoDByteIndexed:$list, addrmode6:$addr, 6124 rGPR:$Rm, pred:$p)>; 6125def VLD2LNdWB_register_Asm_16 : 6126 NEONDataTypeAsmPseudoInst<"vld2${p}", ".16", "$list, $addr, $Rm", 6127 (ins VecListTwoDHWordIndexed:$list, addrmode6:$addr, 6128 rGPR:$Rm, pred:$p)>; 6129def VLD2LNdWB_register_Asm_32 : 6130 NEONDataTypeAsmPseudoInst<"vld2${p}", ".32", "$list, $addr, $Rm", 6131 (ins VecListTwoDWordIndexed:$list, addrmode6:$addr, 6132 rGPR:$Rm, pred:$p)>; 6133def VLD2LNqWB_register_Asm_16 : 6134 NEONDataTypeAsmPseudoInst<"vld2${p}", ".16", "$list, $addr, $Rm", 6135 (ins VecListTwoQHWordIndexed:$list, addrmode6:$addr, 6136 rGPR:$Rm, pred:$p)>; 6137def VLD2LNqWB_register_Asm_32 : 6138 NEONDataTypeAsmPseudoInst<"vld2${p}", ".32", "$list, $addr, $Rm", 6139 (ins VecListTwoQWordIndexed:$list, addrmode6:$addr, 6140 rGPR:$Rm, pred:$p)>; 6141 6142 6143// VST2 single-lane pseudo-instructions. These need special handling for 6144// the lane index that an InstAlias can't handle, so we use these instead. 6145def VST2LNdAsm_8 : NEONDataTypeAsmPseudoInst<"vst2${p}", ".8", "$list, $addr", 6146 (ins VecListTwoDByteIndexed:$list, addrmode6:$addr, pred:$p)>; 6147def VST2LNdAsm_16 : NEONDataTypeAsmPseudoInst<"vst2${p}", ".16", "$list, $addr", 6148 (ins VecListTwoDHWordIndexed:$list, addrmode6:$addr, pred:$p)>; 6149def VST2LNdAsm_32 : NEONDataTypeAsmPseudoInst<"vst2${p}", ".32", "$list, $addr", 6150 (ins VecListTwoDWordIndexed:$list, addrmode6:$addr, pred:$p)>; 6151def VST2LNqAsm_16 : NEONDataTypeAsmPseudoInst<"vst2${p}", ".16", "$list, $addr", 6152 (ins VecListTwoQHWordIndexed:$list, addrmode6:$addr, pred:$p)>; 6153def VST2LNqAsm_32 : NEONDataTypeAsmPseudoInst<"vst2${p}", ".32", "$list, $addr", 6154 (ins VecListTwoQWordIndexed:$list, addrmode6:$addr, pred:$p)>; 6155 6156def VST2LNdWB_fixed_Asm_8 : 6157 NEONDataTypeAsmPseudoInst<"vst2${p}", ".8", "$list, $addr!", 6158 (ins VecListTwoDByteIndexed:$list, addrmode6:$addr, pred:$p)>; 6159def VST2LNdWB_fixed_Asm_16 : 6160 NEONDataTypeAsmPseudoInst<"vst2${p}", ".16", "$list, $addr!", 6161 (ins VecListTwoDHWordIndexed:$list, addrmode6:$addr, pred:$p)>; 6162def VST2LNdWB_fixed_Asm_32 : 6163 NEONDataTypeAsmPseudoInst<"vst2${p}", ".32", "$list, $addr!", 6164 (ins VecListTwoDWordIndexed:$list, addrmode6:$addr, pred:$p)>; 6165def VST2LNqWB_fixed_Asm_16 : 6166 NEONDataTypeAsmPseudoInst<"vst2${p}", ".16", "$list, $addr!", 6167 (ins VecListTwoQHWordIndexed:$list, addrmode6:$addr, pred:$p)>; 6168def VST2LNqWB_fixed_Asm_32 : 6169 NEONDataTypeAsmPseudoInst<"vst2${p}", ".32", "$list, $addr!", 6170 (ins VecListTwoQWordIndexed:$list, addrmode6:$addr, pred:$p)>; 6171def VST2LNdWB_register_Asm_8 : 6172 NEONDataTypeAsmPseudoInst<"vst2${p}", ".8", "$list, $addr, $Rm", 6173 (ins VecListTwoDByteIndexed:$list, addrmode6:$addr, 6174 rGPR:$Rm, pred:$p)>; 6175def VST2LNdWB_register_Asm_16 : 6176 NEONDataTypeAsmPseudoInst<"vst2${p}", ".16","$list, $addr, $Rm", 6177 (ins VecListTwoDHWordIndexed:$list, addrmode6:$addr, 6178 rGPR:$Rm, pred:$p)>; 6179def VST2LNdWB_register_Asm_32 : 6180 NEONDataTypeAsmPseudoInst<"vst2${p}", ".32", "$list, $addr, $Rm", 6181 (ins VecListTwoDWordIndexed:$list, addrmode6:$addr, 6182 rGPR:$Rm, pred:$p)>; 6183def VST2LNqWB_register_Asm_16 : 6184 NEONDataTypeAsmPseudoInst<"vst2${p}", ".16","$list, $addr, $Rm", 6185 (ins VecListTwoQHWordIndexed:$list, addrmode6:$addr, 6186 rGPR:$Rm, pred:$p)>; 6187def VST2LNqWB_register_Asm_32 : 6188 NEONDataTypeAsmPseudoInst<"vst2${p}", ".32", "$list, $addr, $Rm", 6189 (ins VecListTwoQWordIndexed:$list, addrmode6:$addr, 6190 rGPR:$Rm, pred:$p)>; 6191 6192// VLD3 all-lanes pseudo-instructions. These need special handling for 6193// the lane index that an InstAlias can't handle, so we use these instead. 6194def VLD3DUPdAsm_8 : NEONDataTypeAsmPseudoInst<"vld3${p}", ".8", "$list, $addr", 6195 (ins VecListThreeDAllLanes:$list, addrmode6:$addr, pred:$p)>; 6196def VLD3DUPdAsm_16 : NEONDataTypeAsmPseudoInst<"vld3${p}", ".16", "$list, $addr", 6197 (ins VecListThreeDAllLanes:$list, addrmode6:$addr, pred:$p)>; 6198def VLD3DUPdAsm_32 : NEONDataTypeAsmPseudoInst<"vld3${p}", ".32", "$list, $addr", 6199 (ins VecListThreeDAllLanes:$list, addrmode6:$addr, pred:$p)>; 6200def VLD3DUPqAsm_8 : NEONDataTypeAsmPseudoInst<"vld3${p}", ".8", "$list, $addr", 6201 (ins VecListThreeQAllLanes:$list, addrmode6:$addr, pred:$p)>; 6202def VLD3DUPqAsm_16 : NEONDataTypeAsmPseudoInst<"vld3${p}", ".16", "$list, $addr", 6203 (ins VecListThreeQAllLanes:$list, addrmode6:$addr, pred:$p)>; 6204def VLD3DUPqAsm_32 : NEONDataTypeAsmPseudoInst<"vld3${p}", ".32", "$list, $addr", 6205 (ins VecListThreeQAllLanes:$list, addrmode6:$addr, pred:$p)>; 6206 6207def VLD3DUPdWB_fixed_Asm_8 : 6208 NEONDataTypeAsmPseudoInst<"vld3${p}", ".8", "$list, $addr!", 6209 (ins VecListThreeDAllLanes:$list, addrmode6:$addr, pred:$p)>; 6210def VLD3DUPdWB_fixed_Asm_16 : 6211 NEONDataTypeAsmPseudoInst<"vld3${p}", ".16", "$list, $addr!", 6212 (ins VecListThreeDAllLanes:$list, addrmode6:$addr, pred:$p)>; 6213def VLD3DUPdWB_fixed_Asm_32 : 6214 NEONDataTypeAsmPseudoInst<"vld3${p}", ".32", "$list, $addr!", 6215 (ins VecListThreeDAllLanes:$list, addrmode6:$addr, pred:$p)>; 6216def VLD3DUPqWB_fixed_Asm_8 : 6217 NEONDataTypeAsmPseudoInst<"vld3${p}", ".8", "$list, $addr!", 6218 (ins VecListThreeQAllLanes:$list, addrmode6:$addr, pred:$p)>; 6219def VLD3DUPqWB_fixed_Asm_16 : 6220 NEONDataTypeAsmPseudoInst<"vld3${p}", ".16", "$list, $addr!", 6221 (ins VecListThreeQAllLanes:$list, addrmode6:$addr, pred:$p)>; 6222def VLD3DUPqWB_fixed_Asm_32 : 6223 NEONDataTypeAsmPseudoInst<"vld3${p}", ".32", "$list, $addr!", 6224 (ins VecListThreeQAllLanes:$list, addrmode6:$addr, pred:$p)>; 6225def VLD3DUPdWB_register_Asm_8 : 6226 NEONDataTypeAsmPseudoInst<"vld3${p}", ".8", "$list, $addr, $Rm", 6227 (ins VecListThreeDAllLanes:$list, addrmode6:$addr, 6228 rGPR:$Rm, pred:$p)>; 6229def VLD3DUPdWB_register_Asm_16 : 6230 NEONDataTypeAsmPseudoInst<"vld3${p}", ".16", "$list, $addr, $Rm", 6231 (ins VecListThreeDAllLanes:$list, addrmode6:$addr, 6232 rGPR:$Rm, pred:$p)>; 6233def VLD3DUPdWB_register_Asm_32 : 6234 NEONDataTypeAsmPseudoInst<"vld3${p}", ".32", "$list, $addr, $Rm", 6235 (ins VecListThreeDAllLanes:$list, addrmode6:$addr, 6236 rGPR:$Rm, pred:$p)>; 6237def VLD3DUPqWB_register_Asm_8 : 6238 NEONDataTypeAsmPseudoInst<"vld3${p}", ".8", "$list, $addr, $Rm", 6239 (ins VecListThreeQAllLanes:$list, addrmode6:$addr, 6240 rGPR:$Rm, pred:$p)>; 6241def VLD3DUPqWB_register_Asm_16 : 6242 NEONDataTypeAsmPseudoInst<"vld3${p}", ".16", "$list, $addr, $Rm", 6243 (ins VecListThreeQAllLanes:$list, addrmode6:$addr, 6244 rGPR:$Rm, pred:$p)>; 6245def VLD3DUPqWB_register_Asm_32 : 6246 NEONDataTypeAsmPseudoInst<"vld3${p}", ".32", "$list, $addr, $Rm", 6247 (ins VecListThreeQAllLanes:$list, addrmode6:$addr, 6248 rGPR:$Rm, pred:$p)>; 6249 6250 6251// VLD3 single-lane pseudo-instructions. These need special handling for 6252// the lane index that an InstAlias can't handle, so we use these instead. 6253def VLD3LNdAsm_8 : NEONDataTypeAsmPseudoInst<"vld3${p}", ".8", "$list, $addr", 6254 (ins VecListThreeDByteIndexed:$list, addrmode6:$addr, pred:$p)>; 6255def VLD3LNdAsm_16 : NEONDataTypeAsmPseudoInst<"vld3${p}", ".16", "$list, $addr", 6256 (ins VecListThreeDHWordIndexed:$list, addrmode6:$addr, pred:$p)>; 6257def VLD3LNdAsm_32 : NEONDataTypeAsmPseudoInst<"vld3${p}", ".32", "$list, $addr", 6258 (ins VecListThreeDWordIndexed:$list, addrmode6:$addr, pred:$p)>; 6259def VLD3LNqAsm_16 : NEONDataTypeAsmPseudoInst<"vld3${p}", ".16", "$list, $addr", 6260 (ins VecListThreeQHWordIndexed:$list, addrmode6:$addr, pred:$p)>; 6261def VLD3LNqAsm_32 : NEONDataTypeAsmPseudoInst<"vld3${p}", ".32", "$list, $addr", 6262 (ins VecListThreeQWordIndexed:$list, addrmode6:$addr, pred:$p)>; 6263 6264def VLD3LNdWB_fixed_Asm_8 : 6265 NEONDataTypeAsmPseudoInst<"vld3${p}", ".8", "$list, $addr!", 6266 (ins VecListThreeDByteIndexed:$list, addrmode6:$addr, pred:$p)>; 6267def VLD3LNdWB_fixed_Asm_16 : 6268 NEONDataTypeAsmPseudoInst<"vld3${p}", ".16", "$list, $addr!", 6269 (ins VecListThreeDHWordIndexed:$list, addrmode6:$addr, pred:$p)>; 6270def VLD3LNdWB_fixed_Asm_32 : 6271 NEONDataTypeAsmPseudoInst<"vld3${p}", ".32", "$list, $addr!", 6272 (ins VecListThreeDWordIndexed:$list, addrmode6:$addr, pred:$p)>; 6273def VLD3LNqWB_fixed_Asm_16 : 6274 NEONDataTypeAsmPseudoInst<"vld3${p}", ".16", "$list, $addr!", 6275 (ins VecListThreeQHWordIndexed:$list, addrmode6:$addr, pred:$p)>; 6276def VLD3LNqWB_fixed_Asm_32 : 6277 NEONDataTypeAsmPseudoInst<"vld3${p}", ".32", "$list, $addr!", 6278 (ins VecListThreeQWordIndexed:$list, addrmode6:$addr, pred:$p)>; 6279def VLD3LNdWB_register_Asm_8 : 6280 NEONDataTypeAsmPseudoInst<"vld3${p}", ".8", "$list, $addr, $Rm", 6281 (ins VecListThreeDByteIndexed:$list, addrmode6:$addr, 6282 rGPR:$Rm, pred:$p)>; 6283def VLD3LNdWB_register_Asm_16 : 6284 NEONDataTypeAsmPseudoInst<"vld3${p}", ".16", "$list, $addr, $Rm", 6285 (ins VecListThreeDHWordIndexed:$list, addrmode6:$addr, 6286 rGPR:$Rm, pred:$p)>; 6287def VLD3LNdWB_register_Asm_32 : 6288 NEONDataTypeAsmPseudoInst<"vld3${p}", ".32", "$list, $addr, $Rm", 6289 (ins VecListThreeDWordIndexed:$list, addrmode6:$addr, 6290 rGPR:$Rm, pred:$p)>; 6291def VLD3LNqWB_register_Asm_16 : 6292 NEONDataTypeAsmPseudoInst<"vld3${p}", ".16", "$list, $addr, $Rm", 6293 (ins VecListThreeQHWordIndexed:$list, addrmode6:$addr, 6294 rGPR:$Rm, pred:$p)>; 6295def VLD3LNqWB_register_Asm_32 : 6296 NEONDataTypeAsmPseudoInst<"vld3${p}", ".32", "$list, $addr, $Rm", 6297 (ins VecListThreeQWordIndexed:$list, addrmode6:$addr, 6298 rGPR:$Rm, pred:$p)>; 6299 6300// VLD3 multiple structure pseudo-instructions. These need special handling for 6301// the vector operands that the normal instructions don't yet model. 6302// FIXME: Remove these when the register classes and instructions are updated. 6303def VLD3dAsm_8 : NEONDataTypeAsmPseudoInst<"vld3${p}", ".8", "$list, $addr", 6304 (ins VecListThreeD:$list, addrmode6:$addr, pred:$p)>; 6305def VLD3dAsm_16 : NEONDataTypeAsmPseudoInst<"vld3${p}", ".16", "$list, $addr", 6306 (ins VecListThreeD:$list, addrmode6:$addr, pred:$p)>; 6307def VLD3dAsm_32 : NEONDataTypeAsmPseudoInst<"vld3${p}", ".32", "$list, $addr", 6308 (ins VecListThreeD:$list, addrmode6:$addr, pred:$p)>; 6309def VLD3qAsm_8 : NEONDataTypeAsmPseudoInst<"vld3${p}", ".8", "$list, $addr", 6310 (ins VecListThreeQ:$list, addrmode6:$addr, pred:$p)>; 6311def VLD3qAsm_16 : NEONDataTypeAsmPseudoInst<"vld3${p}", ".16", "$list, $addr", 6312 (ins VecListThreeQ:$list, addrmode6:$addr, pred:$p)>; 6313def VLD3qAsm_32 : NEONDataTypeAsmPseudoInst<"vld3${p}", ".32", "$list, $addr", 6314 (ins VecListThreeQ:$list, addrmode6:$addr, pred:$p)>; 6315 6316def VLD3dWB_fixed_Asm_8 : 6317 NEONDataTypeAsmPseudoInst<"vld3${p}", ".8", "$list, $addr!", 6318 (ins VecListThreeD:$list, addrmode6:$addr, pred:$p)>; 6319def VLD3dWB_fixed_Asm_16 : 6320 NEONDataTypeAsmPseudoInst<"vld3${p}", ".16", "$list, $addr!", 6321 (ins VecListThreeD:$list, addrmode6:$addr, pred:$p)>; 6322def VLD3dWB_fixed_Asm_32 : 6323 NEONDataTypeAsmPseudoInst<"vld3${p}", ".32", "$list, $addr!", 6324 (ins VecListThreeD:$list, addrmode6:$addr, pred:$p)>; 6325def VLD3qWB_fixed_Asm_8 : 6326 NEONDataTypeAsmPseudoInst<"vld3${p}", ".8", "$list, $addr!", 6327 (ins VecListThreeQ:$list, addrmode6:$addr, pred:$p)>; 6328def VLD3qWB_fixed_Asm_16 : 6329 NEONDataTypeAsmPseudoInst<"vld3${p}", ".16", "$list, $addr!", 6330 (ins VecListThreeQ:$list, addrmode6:$addr, pred:$p)>; 6331def VLD3qWB_fixed_Asm_32 : 6332 NEONDataTypeAsmPseudoInst<"vld3${p}", ".32", "$list, $addr!", 6333 (ins VecListThreeQ:$list, addrmode6:$addr, pred:$p)>; 6334def VLD3dWB_register_Asm_8 : 6335 NEONDataTypeAsmPseudoInst<"vld3${p}", ".8", "$list, $addr, $Rm", 6336 (ins VecListThreeD:$list, addrmode6:$addr, 6337 rGPR:$Rm, pred:$p)>; 6338def VLD3dWB_register_Asm_16 : 6339 NEONDataTypeAsmPseudoInst<"vld3${p}", ".16", "$list, $addr, $Rm", 6340 (ins VecListThreeD:$list, addrmode6:$addr, 6341 rGPR:$Rm, pred:$p)>; 6342def VLD3dWB_register_Asm_32 : 6343 NEONDataTypeAsmPseudoInst<"vld3${p}", ".32", "$list, $addr, $Rm", 6344 (ins VecListThreeD:$list, addrmode6:$addr, 6345 rGPR:$Rm, pred:$p)>; 6346def VLD3qWB_register_Asm_8 : 6347 NEONDataTypeAsmPseudoInst<"vld3${p}", ".8", "$list, $addr, $Rm", 6348 (ins VecListThreeQ:$list, addrmode6:$addr, 6349 rGPR:$Rm, pred:$p)>; 6350def VLD3qWB_register_Asm_16 : 6351 NEONDataTypeAsmPseudoInst<"vld3${p}", ".16", "$list, $addr, $Rm", 6352 (ins VecListThreeQ:$list, addrmode6:$addr, 6353 rGPR:$Rm, pred:$p)>; 6354def VLD3qWB_register_Asm_32 : 6355 NEONDataTypeAsmPseudoInst<"vld3${p}", ".32", "$list, $addr, $Rm", 6356 (ins VecListThreeQ:$list, addrmode6:$addr, 6357 rGPR:$Rm, pred:$p)>; 6358 6359// VST3 single-lane pseudo-instructions. These need special handling for 6360// the lane index that an InstAlias can't handle, so we use these instead. 6361def VST3LNdAsm_8 : NEONDataTypeAsmPseudoInst<"vst3${p}", ".8", "$list, $addr", 6362 (ins VecListThreeDByteIndexed:$list, addrmode6:$addr, pred:$p)>; 6363def VST3LNdAsm_16 : NEONDataTypeAsmPseudoInst<"vst3${p}", ".16", "$list, $addr", 6364 (ins VecListThreeDHWordIndexed:$list, addrmode6:$addr, pred:$p)>; 6365def VST3LNdAsm_32 : NEONDataTypeAsmPseudoInst<"vst3${p}", ".32", "$list, $addr", 6366 (ins VecListThreeDWordIndexed:$list, addrmode6:$addr, pred:$p)>; 6367def VST3LNqAsm_16 : NEONDataTypeAsmPseudoInst<"vst3${p}", ".16", "$list, $addr", 6368 (ins VecListThreeQHWordIndexed:$list, addrmode6:$addr, pred:$p)>; 6369def VST3LNqAsm_32 : NEONDataTypeAsmPseudoInst<"vst3${p}", ".32", "$list, $addr", 6370 (ins VecListThreeQWordIndexed:$list, addrmode6:$addr, pred:$p)>; 6371 6372def VST3LNdWB_fixed_Asm_8 : 6373 NEONDataTypeAsmPseudoInst<"vst3${p}", ".8", "$list, $addr!", 6374 (ins VecListThreeDByteIndexed:$list, addrmode6:$addr, pred:$p)>; 6375def VST3LNdWB_fixed_Asm_16 : 6376 NEONDataTypeAsmPseudoInst<"vst3${p}", ".16", "$list, $addr!", 6377 (ins VecListThreeDHWordIndexed:$list, addrmode6:$addr, pred:$p)>; 6378def VST3LNdWB_fixed_Asm_32 : 6379 NEONDataTypeAsmPseudoInst<"vst3${p}", ".32", "$list, $addr!", 6380 (ins VecListThreeDWordIndexed:$list, addrmode6:$addr, pred:$p)>; 6381def VST3LNqWB_fixed_Asm_16 : 6382 NEONDataTypeAsmPseudoInst<"vst3${p}", ".16", "$list, $addr!", 6383 (ins VecListThreeQHWordIndexed:$list, addrmode6:$addr, pred:$p)>; 6384def VST3LNqWB_fixed_Asm_32 : 6385 NEONDataTypeAsmPseudoInst<"vst3${p}", ".32", "$list, $addr!", 6386 (ins VecListThreeQWordIndexed:$list, addrmode6:$addr, pred:$p)>; 6387def VST3LNdWB_register_Asm_8 : 6388 NEONDataTypeAsmPseudoInst<"vst3${p}", ".8", "$list, $addr, $Rm", 6389 (ins VecListThreeDByteIndexed:$list, addrmode6:$addr, 6390 rGPR:$Rm, pred:$p)>; 6391def VST3LNdWB_register_Asm_16 : 6392 NEONDataTypeAsmPseudoInst<"vst3${p}", ".16", "$list, $addr, $Rm", 6393 (ins VecListThreeDHWordIndexed:$list, addrmode6:$addr, 6394 rGPR:$Rm, pred:$p)>; 6395def VST3LNdWB_register_Asm_32 : 6396 NEONDataTypeAsmPseudoInst<"vst3${p}", ".32", "$list, $addr, $Rm", 6397 (ins VecListThreeDWordIndexed:$list, addrmode6:$addr, 6398 rGPR:$Rm, pred:$p)>; 6399def VST3LNqWB_register_Asm_16 : 6400 NEONDataTypeAsmPseudoInst<"vst3${p}", ".16", "$list, $addr, $Rm", 6401 (ins VecListThreeQHWordIndexed:$list, addrmode6:$addr, 6402 rGPR:$Rm, pred:$p)>; 6403def VST3LNqWB_register_Asm_32 : 6404 NEONDataTypeAsmPseudoInst<"vst3${p}", ".32", "$list, $addr, $Rm", 6405 (ins VecListThreeQWordIndexed:$list, addrmode6:$addr, 6406 rGPR:$Rm, pred:$p)>; 6407 6408 6409// VST3 multiple structure pseudo-instructions. These need special handling for 6410// the vector operands that the normal instructions don't yet model. 6411// FIXME: Remove these when the register classes and instructions are updated. 6412def VST3dAsm_8 : NEONDataTypeAsmPseudoInst<"vst3${p}", ".8", "$list, $addr", 6413 (ins VecListThreeD:$list, addrmode6:$addr, pred:$p)>; 6414def VST3dAsm_16 : NEONDataTypeAsmPseudoInst<"vst3${p}", ".16", "$list, $addr", 6415 (ins VecListThreeD:$list, addrmode6:$addr, pred:$p)>; 6416def VST3dAsm_32 : NEONDataTypeAsmPseudoInst<"vst3${p}", ".32", "$list, $addr", 6417 (ins VecListThreeD:$list, addrmode6:$addr, pred:$p)>; 6418def VST3qAsm_8 : NEONDataTypeAsmPseudoInst<"vst3${p}", ".8", "$list, $addr", 6419 (ins VecListThreeQ:$list, addrmode6:$addr, pred:$p)>; 6420def VST3qAsm_16 : NEONDataTypeAsmPseudoInst<"vst3${p}", ".16", "$list, $addr", 6421 (ins VecListThreeQ:$list, addrmode6:$addr, pred:$p)>; 6422def VST3qAsm_32 : NEONDataTypeAsmPseudoInst<"vst3${p}", ".32", "$list, $addr", 6423 (ins VecListThreeQ:$list, addrmode6:$addr, pred:$p)>; 6424 6425def VST3dWB_fixed_Asm_8 : 6426 NEONDataTypeAsmPseudoInst<"vst3${p}", ".8", "$list, $addr!", 6427 (ins VecListThreeD:$list, addrmode6:$addr, pred:$p)>; 6428def VST3dWB_fixed_Asm_16 : 6429 NEONDataTypeAsmPseudoInst<"vst3${p}", ".16", "$list, $addr!", 6430 (ins VecListThreeD:$list, addrmode6:$addr, pred:$p)>; 6431def VST3dWB_fixed_Asm_32 : 6432 NEONDataTypeAsmPseudoInst<"vst3${p}", ".32", "$list, $addr!", 6433 (ins VecListThreeD:$list, addrmode6:$addr, pred:$p)>; 6434def VST3qWB_fixed_Asm_8 : 6435 NEONDataTypeAsmPseudoInst<"vst3${p}", ".8", "$list, $addr!", 6436 (ins VecListThreeQ:$list, addrmode6:$addr, pred:$p)>; 6437def VST3qWB_fixed_Asm_16 : 6438 NEONDataTypeAsmPseudoInst<"vst3${p}", ".16", "$list, $addr!", 6439 (ins VecListThreeQ:$list, addrmode6:$addr, pred:$p)>; 6440def VST3qWB_fixed_Asm_32 : 6441 NEONDataTypeAsmPseudoInst<"vst3${p}", ".32", "$list, $addr!", 6442 (ins VecListThreeQ:$list, addrmode6:$addr, pred:$p)>; 6443def VST3dWB_register_Asm_8 : 6444 NEONDataTypeAsmPseudoInst<"vst3${p}", ".8", "$list, $addr, $Rm", 6445 (ins VecListThreeD:$list, addrmode6:$addr, 6446 rGPR:$Rm, pred:$p)>; 6447def VST3dWB_register_Asm_16 : 6448 NEONDataTypeAsmPseudoInst<"vst3${p}", ".16", "$list, $addr, $Rm", 6449 (ins VecListThreeD:$list, addrmode6:$addr, 6450 rGPR:$Rm, pred:$p)>; 6451def VST3dWB_register_Asm_32 : 6452 NEONDataTypeAsmPseudoInst<"vst3${p}", ".32", "$list, $addr, $Rm", 6453 (ins VecListThreeD:$list, addrmode6:$addr, 6454 rGPR:$Rm, pred:$p)>; 6455def VST3qWB_register_Asm_8 : 6456 NEONDataTypeAsmPseudoInst<"vst3${p}", ".8", "$list, $addr, $Rm", 6457 (ins VecListThreeQ:$list, addrmode6:$addr, 6458 rGPR:$Rm, pred:$p)>; 6459def VST3qWB_register_Asm_16 : 6460 NEONDataTypeAsmPseudoInst<"vst3${p}", ".16", "$list, $addr, $Rm", 6461 (ins VecListThreeQ:$list, addrmode6:$addr, 6462 rGPR:$Rm, pred:$p)>; 6463def VST3qWB_register_Asm_32 : 6464 NEONDataTypeAsmPseudoInst<"vst3${p}", ".32", "$list, $addr, $Rm", 6465 (ins VecListThreeQ:$list, addrmode6:$addr, 6466 rGPR:$Rm, pred:$p)>; 6467 6468// VLD4 all-lanes pseudo-instructions. These need special handling for 6469// the lane index that an InstAlias can't handle, so we use these instead. 6470def VLD4DUPdAsm_8 : NEONDataTypeAsmPseudoInst<"vld4${p}", ".8", "$list, $addr", 6471 (ins VecListFourDAllLanes:$list, addrmode6:$addr, pred:$p)>; 6472def VLD4DUPdAsm_16 : NEONDataTypeAsmPseudoInst<"vld4${p}", ".16", "$list, $addr", 6473 (ins VecListFourDAllLanes:$list, addrmode6:$addr, pred:$p)>; 6474def VLD4DUPdAsm_32 : NEONDataTypeAsmPseudoInst<"vld4${p}", ".32", "$list, $addr", 6475 (ins VecListFourDAllLanes:$list, addrmode6:$addr, pred:$p)>; 6476def VLD4DUPqAsm_8 : NEONDataTypeAsmPseudoInst<"vld4${p}", ".8", "$list, $addr", 6477 (ins VecListFourQAllLanes:$list, addrmode6:$addr, pred:$p)>; 6478def VLD4DUPqAsm_16 : NEONDataTypeAsmPseudoInst<"vld4${p}", ".16", "$list, $addr", 6479 (ins VecListFourQAllLanes:$list, addrmode6:$addr, pred:$p)>; 6480def VLD4DUPqAsm_32 : NEONDataTypeAsmPseudoInst<"vld4${p}", ".32", "$list, $addr", 6481 (ins VecListFourQAllLanes:$list, addrmode6:$addr, pred:$p)>; 6482 6483def VLD4DUPdWB_fixed_Asm_8 : 6484 NEONDataTypeAsmPseudoInst<"vld4${p}", ".8", "$list, $addr!", 6485 (ins VecListFourDAllLanes:$list, addrmode6:$addr, pred:$p)>; 6486def VLD4DUPdWB_fixed_Asm_16 : 6487 NEONDataTypeAsmPseudoInst<"vld4${p}", ".16", "$list, $addr!", 6488 (ins VecListFourDAllLanes:$list, addrmode6:$addr, pred:$p)>; 6489def VLD4DUPdWB_fixed_Asm_32 : 6490 NEONDataTypeAsmPseudoInst<"vld4${p}", ".32", "$list, $addr!", 6491 (ins VecListFourDAllLanes:$list, addrmode6:$addr, pred:$p)>; 6492def VLD4DUPqWB_fixed_Asm_8 : 6493 NEONDataTypeAsmPseudoInst<"vld4${p}", ".8", "$list, $addr!", 6494 (ins VecListFourQAllLanes:$list, addrmode6:$addr, pred:$p)>; 6495def VLD4DUPqWB_fixed_Asm_16 : 6496 NEONDataTypeAsmPseudoInst<"vld4${p}", ".16", "$list, $addr!", 6497 (ins VecListFourQAllLanes:$list, addrmode6:$addr, pred:$p)>; 6498def VLD4DUPqWB_fixed_Asm_32 : 6499 NEONDataTypeAsmPseudoInst<"vld4${p}", ".32", "$list, $addr!", 6500 (ins VecListFourQAllLanes:$list, addrmode6:$addr, pred:$p)>; 6501def VLD4DUPdWB_register_Asm_8 : 6502 NEONDataTypeAsmPseudoInst<"vld4${p}", ".8", "$list, $addr, $Rm", 6503 (ins VecListFourDAllLanes:$list, addrmode6:$addr, 6504 rGPR:$Rm, pred:$p)>; 6505def VLD4DUPdWB_register_Asm_16 : 6506 NEONDataTypeAsmPseudoInst<"vld4${p}", ".16", "$list, $addr, $Rm", 6507 (ins VecListFourDAllLanes:$list, addrmode6:$addr, 6508 rGPR:$Rm, pred:$p)>; 6509def VLD4DUPdWB_register_Asm_32 : 6510 NEONDataTypeAsmPseudoInst<"vld4${p}", ".32", "$list, $addr, $Rm", 6511 (ins VecListFourDAllLanes:$list, addrmode6:$addr, 6512 rGPR:$Rm, pred:$p)>; 6513def VLD4DUPqWB_register_Asm_8 : 6514 NEONDataTypeAsmPseudoInst<"vld4${p}", ".8", "$list, $addr, $Rm", 6515 (ins VecListFourQAllLanes:$list, addrmode6:$addr, 6516 rGPR:$Rm, pred:$p)>; 6517def VLD4DUPqWB_register_Asm_16 : 6518 NEONDataTypeAsmPseudoInst<"vld4${p}", ".16", "$list, $addr, $Rm", 6519 (ins VecListFourQAllLanes:$list, addrmode6:$addr, 6520 rGPR:$Rm, pred:$p)>; 6521def VLD4DUPqWB_register_Asm_32 : 6522 NEONDataTypeAsmPseudoInst<"vld4${p}", ".32", "$list, $addr, $Rm", 6523 (ins VecListFourQAllLanes:$list, addrmode6:$addr, 6524 rGPR:$Rm, pred:$p)>; 6525 6526 6527// VLD4 single-lane pseudo-instructions. These need special handling for 6528// the lane index that an InstAlias can't handle, so we use these instead. 6529def VLD4LNdAsm_8 : NEONDataTypeAsmPseudoInst<"vld4${p}", ".8", "$list, $addr", 6530 (ins VecListFourDByteIndexed:$list, addrmode6:$addr, pred:$p)>; 6531def VLD4LNdAsm_16 : NEONDataTypeAsmPseudoInst<"vld4${p}", ".16", "$list, $addr", 6532 (ins VecListFourDHWordIndexed:$list, addrmode6:$addr, pred:$p)>; 6533def VLD4LNdAsm_32 : NEONDataTypeAsmPseudoInst<"vld4${p}", ".32", "$list, $addr", 6534 (ins VecListFourDWordIndexed:$list, addrmode6:$addr, pred:$p)>; 6535def VLD4LNqAsm_16 : NEONDataTypeAsmPseudoInst<"vld4${p}", ".16", "$list, $addr", 6536 (ins VecListFourQHWordIndexed:$list, addrmode6:$addr, pred:$p)>; 6537def VLD4LNqAsm_32 : NEONDataTypeAsmPseudoInst<"vld4${p}", ".32", "$list, $addr", 6538 (ins VecListFourQWordIndexed:$list, addrmode6:$addr, pred:$p)>; 6539 6540def VLD4LNdWB_fixed_Asm_8 : 6541 NEONDataTypeAsmPseudoInst<"vld4${p}", ".8", "$list, $addr!", 6542 (ins VecListFourDByteIndexed:$list, addrmode6:$addr, pred:$p)>; 6543def VLD4LNdWB_fixed_Asm_16 : 6544 NEONDataTypeAsmPseudoInst<"vld4${p}", ".16", "$list, $addr!", 6545 (ins VecListFourDHWordIndexed:$list, addrmode6:$addr, pred:$p)>; 6546def VLD4LNdWB_fixed_Asm_32 : 6547 NEONDataTypeAsmPseudoInst<"vld4${p}", ".32", "$list, $addr!", 6548 (ins VecListFourDWordIndexed:$list, addrmode6:$addr, pred:$p)>; 6549def VLD4LNqWB_fixed_Asm_16 : 6550 NEONDataTypeAsmPseudoInst<"vld4${p}", ".16", "$list, $addr!", 6551 (ins VecListFourQHWordIndexed:$list, addrmode6:$addr, pred:$p)>; 6552def VLD4LNqWB_fixed_Asm_32 : 6553 NEONDataTypeAsmPseudoInst<"vld4${p}", ".32", "$list, $addr!", 6554 (ins VecListFourQWordIndexed:$list, addrmode6:$addr, pred:$p)>; 6555def VLD4LNdWB_register_Asm_8 : 6556 NEONDataTypeAsmPseudoInst<"vld4${p}", ".8", "$list, $addr, $Rm", 6557 (ins VecListFourDByteIndexed:$list, addrmode6:$addr, 6558 rGPR:$Rm, pred:$p)>; 6559def VLD4LNdWB_register_Asm_16 : 6560 NEONDataTypeAsmPseudoInst<"vld4${p}", ".16", "$list, $addr, $Rm", 6561 (ins VecListFourDHWordIndexed:$list, addrmode6:$addr, 6562 rGPR:$Rm, pred:$p)>; 6563def VLD4LNdWB_register_Asm_32 : 6564 NEONDataTypeAsmPseudoInst<"vld4${p}", ".32", "$list, $addr, $Rm", 6565 (ins VecListFourDWordIndexed:$list, addrmode6:$addr, 6566 rGPR:$Rm, pred:$p)>; 6567def VLD4LNqWB_register_Asm_16 : 6568 NEONDataTypeAsmPseudoInst<"vld4${p}", ".16", "$list, $addr, $Rm", 6569 (ins VecListFourQHWordIndexed:$list, addrmode6:$addr, 6570 rGPR:$Rm, pred:$p)>; 6571def VLD4LNqWB_register_Asm_32 : 6572 NEONDataTypeAsmPseudoInst<"vld4${p}", ".32", "$list, $addr, $Rm", 6573 (ins VecListFourQWordIndexed:$list, addrmode6:$addr, 6574 rGPR:$Rm, pred:$p)>; 6575 6576 6577 6578// VLD4 multiple structure pseudo-instructions. These need special handling for 6579// the vector operands that the normal instructions don't yet model. 6580// FIXME: Remove these when the register classes and instructions are updated. 6581def VLD4dAsm_8 : NEONDataTypeAsmPseudoInst<"vld4${p}", ".8", "$list, $addr", 6582 (ins VecListFourD:$list, addrmode6:$addr, pred:$p)>; 6583def VLD4dAsm_16 : NEONDataTypeAsmPseudoInst<"vld4${p}", ".16", "$list, $addr", 6584 (ins VecListFourD:$list, addrmode6:$addr, pred:$p)>; 6585def VLD4dAsm_32 : NEONDataTypeAsmPseudoInst<"vld4${p}", ".32", "$list, $addr", 6586 (ins VecListFourD:$list, addrmode6:$addr, pred:$p)>; 6587def VLD4qAsm_8 : NEONDataTypeAsmPseudoInst<"vld4${p}", ".8", "$list, $addr", 6588 (ins VecListFourQ:$list, addrmode6:$addr, pred:$p)>; 6589def VLD4qAsm_16 : NEONDataTypeAsmPseudoInst<"vld4${p}", ".16", "$list, $addr", 6590 (ins VecListFourQ:$list, addrmode6:$addr, pred:$p)>; 6591def VLD4qAsm_32 : NEONDataTypeAsmPseudoInst<"vld4${p}", ".32", "$list, $addr", 6592 (ins VecListFourQ:$list, addrmode6:$addr, pred:$p)>; 6593 6594def VLD4dWB_fixed_Asm_8 : 6595 NEONDataTypeAsmPseudoInst<"vld4${p}", ".8", "$list, $addr!", 6596 (ins VecListFourD:$list, addrmode6:$addr, pred:$p)>; 6597def VLD4dWB_fixed_Asm_16 : 6598 NEONDataTypeAsmPseudoInst<"vld4${p}", ".16", "$list, $addr!", 6599 (ins VecListFourD:$list, addrmode6:$addr, pred:$p)>; 6600def VLD4dWB_fixed_Asm_32 : 6601 NEONDataTypeAsmPseudoInst<"vld4${p}", ".32", "$list, $addr!", 6602 (ins VecListFourD:$list, addrmode6:$addr, pred:$p)>; 6603def VLD4qWB_fixed_Asm_8 : 6604 NEONDataTypeAsmPseudoInst<"vld4${p}", ".8", "$list, $addr!", 6605 (ins VecListFourQ:$list, addrmode6:$addr, pred:$p)>; 6606def VLD4qWB_fixed_Asm_16 : 6607 NEONDataTypeAsmPseudoInst<"vld4${p}", ".16", "$list, $addr!", 6608 (ins VecListFourQ:$list, addrmode6:$addr, pred:$p)>; 6609def VLD4qWB_fixed_Asm_32 : 6610 NEONDataTypeAsmPseudoInst<"vld4${p}", ".32", "$list, $addr!", 6611 (ins VecListFourQ:$list, addrmode6:$addr, pred:$p)>; 6612def VLD4dWB_register_Asm_8 : 6613 NEONDataTypeAsmPseudoInst<"vld4${p}", ".8", "$list, $addr, $Rm", 6614 (ins VecListFourD:$list, addrmode6:$addr, 6615 rGPR:$Rm, pred:$p)>; 6616def VLD4dWB_register_Asm_16 : 6617 NEONDataTypeAsmPseudoInst<"vld4${p}", ".16", "$list, $addr, $Rm", 6618 (ins VecListFourD:$list, addrmode6:$addr, 6619 rGPR:$Rm, pred:$p)>; 6620def VLD4dWB_register_Asm_32 : 6621 NEONDataTypeAsmPseudoInst<"vld4${p}", ".32", "$list, $addr, $Rm", 6622 (ins VecListFourD:$list, addrmode6:$addr, 6623 rGPR:$Rm, pred:$p)>; 6624def VLD4qWB_register_Asm_8 : 6625 NEONDataTypeAsmPseudoInst<"vld4${p}", ".8", "$list, $addr, $Rm", 6626 (ins VecListFourQ:$list, addrmode6:$addr, 6627 rGPR:$Rm, pred:$p)>; 6628def VLD4qWB_register_Asm_16 : 6629 NEONDataTypeAsmPseudoInst<"vld4${p}", ".16", "$list, $addr, $Rm", 6630 (ins VecListFourQ:$list, addrmode6:$addr, 6631 rGPR:$Rm, pred:$p)>; 6632def VLD4qWB_register_Asm_32 : 6633 NEONDataTypeAsmPseudoInst<"vld4${p}", ".32", "$list, $addr, $Rm", 6634 (ins VecListFourQ:$list, addrmode6:$addr, 6635 rGPR:$Rm, pred:$p)>; 6636 6637// VST4 single-lane pseudo-instructions. These need special handling for 6638// the lane index that an InstAlias can't handle, so we use these instead. 6639def VST4LNdAsm_8 : NEONDataTypeAsmPseudoInst<"vst4${p}", ".8", "$list, $addr", 6640 (ins VecListFourDByteIndexed:$list, addrmode6:$addr, pred:$p)>; 6641def VST4LNdAsm_16 : NEONDataTypeAsmPseudoInst<"vst4${p}", ".16", "$list, $addr", 6642 (ins VecListFourDHWordIndexed:$list, addrmode6:$addr, pred:$p)>; 6643def VST4LNdAsm_32 : NEONDataTypeAsmPseudoInst<"vst4${p}", ".32", "$list, $addr", 6644 (ins VecListFourDWordIndexed:$list, addrmode6:$addr, pred:$p)>; 6645def VST4LNqAsm_16 : NEONDataTypeAsmPseudoInst<"vst4${p}", ".16", "$list, $addr", 6646 (ins VecListFourQHWordIndexed:$list, addrmode6:$addr, pred:$p)>; 6647def VST4LNqAsm_32 : NEONDataTypeAsmPseudoInst<"vst4${p}", ".32", "$list, $addr", 6648 (ins VecListFourQWordIndexed:$list, addrmode6:$addr, pred:$p)>; 6649 6650def VST4LNdWB_fixed_Asm_8 : 6651 NEONDataTypeAsmPseudoInst<"vst4${p}", ".8", "$list, $addr!", 6652 (ins VecListFourDByteIndexed:$list, addrmode6:$addr, pred:$p)>; 6653def VST4LNdWB_fixed_Asm_16 : 6654 NEONDataTypeAsmPseudoInst<"vst4${p}", ".16", "$list, $addr!", 6655 (ins VecListFourDHWordIndexed:$list, addrmode6:$addr, pred:$p)>; 6656def VST4LNdWB_fixed_Asm_32 : 6657 NEONDataTypeAsmPseudoInst<"vst4${p}", ".32", "$list, $addr!", 6658 (ins VecListFourDWordIndexed:$list, addrmode6:$addr, pred:$p)>; 6659def VST4LNqWB_fixed_Asm_16 : 6660 NEONDataTypeAsmPseudoInst<"vst4${p}", ".16", "$list, $addr!", 6661 (ins VecListFourQHWordIndexed:$list, addrmode6:$addr, pred:$p)>; 6662def VST4LNqWB_fixed_Asm_32 : 6663 NEONDataTypeAsmPseudoInst<"vst4${p}", ".32", "$list, $addr!", 6664 (ins VecListFourQWordIndexed:$list, addrmode6:$addr, pred:$p)>; 6665def VST4LNdWB_register_Asm_8 : 6666 NEONDataTypeAsmPseudoInst<"vst4${p}", ".8", "$list, $addr, $Rm", 6667 (ins VecListFourDByteIndexed:$list, addrmode6:$addr, 6668 rGPR:$Rm, pred:$p)>; 6669def VST4LNdWB_register_Asm_16 : 6670 NEONDataTypeAsmPseudoInst<"vst4${p}", ".16", "$list, $addr, $Rm", 6671 (ins VecListFourDHWordIndexed:$list, addrmode6:$addr, 6672 rGPR:$Rm, pred:$p)>; 6673def VST4LNdWB_register_Asm_32 : 6674 NEONDataTypeAsmPseudoInst<"vst4${p}", ".32", "$list, $addr, $Rm", 6675 (ins VecListFourDWordIndexed:$list, addrmode6:$addr, 6676 rGPR:$Rm, pred:$p)>; 6677def VST4LNqWB_register_Asm_16 : 6678 NEONDataTypeAsmPseudoInst<"vst4${p}", ".16", "$list, $addr, $Rm", 6679 (ins VecListFourQHWordIndexed:$list, addrmode6:$addr, 6680 rGPR:$Rm, pred:$p)>; 6681def VST4LNqWB_register_Asm_32 : 6682 NEONDataTypeAsmPseudoInst<"vst4${p}", ".32", "$list, $addr, $Rm", 6683 (ins VecListFourQWordIndexed:$list, addrmode6:$addr, 6684 rGPR:$Rm, pred:$p)>; 6685 6686 6687// VST4 multiple structure pseudo-instructions. These need special handling for 6688// the vector operands that the normal instructions don't yet model. 6689// FIXME: Remove these when the register classes and instructions are updated. 6690def VST4dAsm_8 : NEONDataTypeAsmPseudoInst<"vst4${p}", ".8", "$list, $addr", 6691 (ins VecListFourD:$list, addrmode6:$addr, pred:$p)>; 6692def VST4dAsm_16 : NEONDataTypeAsmPseudoInst<"vst4${p}", ".16", "$list, $addr", 6693 (ins VecListFourD:$list, addrmode6:$addr, pred:$p)>; 6694def VST4dAsm_32 : NEONDataTypeAsmPseudoInst<"vst4${p}", ".32", "$list, $addr", 6695 (ins VecListFourD:$list, addrmode6:$addr, pred:$p)>; 6696def VST4qAsm_8 : NEONDataTypeAsmPseudoInst<"vst4${p}", ".8", "$list, $addr", 6697 (ins VecListFourQ:$list, addrmode6:$addr, pred:$p)>; 6698def VST4qAsm_16 : NEONDataTypeAsmPseudoInst<"vst4${p}", ".16", "$list, $addr", 6699 (ins VecListFourQ:$list, addrmode6:$addr, pred:$p)>; 6700def VST4qAsm_32 : NEONDataTypeAsmPseudoInst<"vst4${p}", ".32", "$list, $addr", 6701 (ins VecListFourQ:$list, addrmode6:$addr, pred:$p)>; 6702 6703def VST4dWB_fixed_Asm_8 : 6704 NEONDataTypeAsmPseudoInst<"vst4${p}", ".8", "$list, $addr!", 6705 (ins VecListFourD:$list, addrmode6:$addr, pred:$p)>; 6706def VST4dWB_fixed_Asm_16 : 6707 NEONDataTypeAsmPseudoInst<"vst4${p}", ".16", "$list, $addr!", 6708 (ins VecListFourD:$list, addrmode6:$addr, pred:$p)>; 6709def VST4dWB_fixed_Asm_32 : 6710 NEONDataTypeAsmPseudoInst<"vst4${p}", ".32", "$list, $addr!", 6711 (ins VecListFourD:$list, addrmode6:$addr, pred:$p)>; 6712def VST4qWB_fixed_Asm_8 : 6713 NEONDataTypeAsmPseudoInst<"vst4${p}", ".8", "$list, $addr!", 6714 (ins VecListFourQ:$list, addrmode6:$addr, pred:$p)>; 6715def VST4qWB_fixed_Asm_16 : 6716 NEONDataTypeAsmPseudoInst<"vst4${p}", ".16", "$list, $addr!", 6717 (ins VecListFourQ:$list, addrmode6:$addr, pred:$p)>; 6718def VST4qWB_fixed_Asm_32 : 6719 NEONDataTypeAsmPseudoInst<"vst4${p}", ".32", "$list, $addr!", 6720 (ins VecListFourQ:$list, addrmode6:$addr, pred:$p)>; 6721def VST4dWB_register_Asm_8 : 6722 NEONDataTypeAsmPseudoInst<"vst4${p}", ".8", "$list, $addr, $Rm", 6723 (ins VecListFourD:$list, addrmode6:$addr, 6724 rGPR:$Rm, pred:$p)>; 6725def VST4dWB_register_Asm_16 : 6726 NEONDataTypeAsmPseudoInst<"vst4${p}", ".16", "$list, $addr, $Rm", 6727 (ins VecListFourD:$list, addrmode6:$addr, 6728 rGPR:$Rm, pred:$p)>; 6729def VST4dWB_register_Asm_32 : 6730 NEONDataTypeAsmPseudoInst<"vst4${p}", ".32", "$list, $addr, $Rm", 6731 (ins VecListFourD:$list, addrmode6:$addr, 6732 rGPR:$Rm, pred:$p)>; 6733def VST4qWB_register_Asm_8 : 6734 NEONDataTypeAsmPseudoInst<"vst4${p}", ".8", "$list, $addr, $Rm", 6735 (ins VecListFourQ:$list, addrmode6:$addr, 6736 rGPR:$Rm, pred:$p)>; 6737def VST4qWB_register_Asm_16 : 6738 NEONDataTypeAsmPseudoInst<"vst4${p}", ".16", "$list, $addr, $Rm", 6739 (ins VecListFourQ:$list, addrmode6:$addr, 6740 rGPR:$Rm, pred:$p)>; 6741def VST4qWB_register_Asm_32 : 6742 NEONDataTypeAsmPseudoInst<"vst4${p}", ".32", "$list, $addr, $Rm", 6743 (ins VecListFourQ:$list, addrmode6:$addr, 6744 rGPR:$Rm, pred:$p)>; 6745 6746// VMOV takes an optional datatype suffix 6747defm : NEONDTAnyInstAlias<"vmov${p}", "$Vd, $Vm", 6748 (VORRd DPR:$Vd, DPR:$Vm, DPR:$Vm, pred:$p)>; 6749defm : NEONDTAnyInstAlias<"vmov${p}", "$Vd, $Vm", 6750 (VORRq QPR:$Vd, QPR:$Vm, QPR:$Vm, pred:$p)>; 6751 6752// VCLT (register) is an assembler alias for VCGT w/ the operands reversed. 6753// D-register versions. 6754def : NEONInstAlias<"vcle${p}.s8 $Dd, $Dn, $Dm", 6755 (VCGEsv8i8 DPR:$Dd, DPR:$Dm, DPR:$Dn, pred:$p)>; 6756def : NEONInstAlias<"vcle${p}.s16 $Dd, $Dn, $Dm", 6757 (VCGEsv4i16 DPR:$Dd, DPR:$Dm, DPR:$Dn, pred:$p)>; 6758def : NEONInstAlias<"vcle${p}.s32 $Dd, $Dn, $Dm", 6759 (VCGEsv2i32 DPR:$Dd, DPR:$Dm, DPR:$Dn, pred:$p)>; 6760def : NEONInstAlias<"vcle${p}.u8 $Dd, $Dn, $Dm", 6761 (VCGEuv8i8 DPR:$Dd, DPR:$Dm, DPR:$Dn, pred:$p)>; 6762def : NEONInstAlias<"vcle${p}.u16 $Dd, $Dn, $Dm", 6763 (VCGEuv4i16 DPR:$Dd, DPR:$Dm, DPR:$Dn, pred:$p)>; 6764def : NEONInstAlias<"vcle${p}.u32 $Dd, $Dn, $Dm", 6765 (VCGEuv2i32 DPR:$Dd, DPR:$Dm, DPR:$Dn, pred:$p)>; 6766def : NEONInstAlias<"vcle${p}.f32 $Dd, $Dn, $Dm", 6767 (VCGEfd DPR:$Dd, DPR:$Dm, DPR:$Dn, pred:$p)>; 6768// Q-register versions. 6769def : NEONInstAlias<"vcle${p}.s8 $Qd, $Qn, $Qm", 6770 (VCGEsv16i8 QPR:$Qd, QPR:$Qm, QPR:$Qn, pred:$p)>; 6771def : NEONInstAlias<"vcle${p}.s16 $Qd, $Qn, $Qm", 6772 (VCGEsv8i16 QPR:$Qd, QPR:$Qm, QPR:$Qn, pred:$p)>; 6773def : NEONInstAlias<"vcle${p}.s32 $Qd, $Qn, $Qm", 6774 (VCGEsv4i32 QPR:$Qd, QPR:$Qm, QPR:$Qn, pred:$p)>; 6775def : NEONInstAlias<"vcle${p}.u8 $Qd, $Qn, $Qm", 6776 (VCGEuv16i8 QPR:$Qd, QPR:$Qm, QPR:$Qn, pred:$p)>; 6777def : NEONInstAlias<"vcle${p}.u16 $Qd, $Qn, $Qm", 6778 (VCGEuv8i16 QPR:$Qd, QPR:$Qm, QPR:$Qn, pred:$p)>; 6779def : NEONInstAlias<"vcle${p}.u32 $Qd, $Qn, $Qm", 6780 (VCGEuv4i32 QPR:$Qd, QPR:$Qm, QPR:$Qn, pred:$p)>; 6781def : NEONInstAlias<"vcle${p}.f32 $Qd, $Qn, $Qm", 6782 (VCGEfq QPR:$Qd, QPR:$Qm, QPR:$Qn, pred:$p)>; 6783 6784// VCLT (register) is an assembler alias for VCGT w/ the operands reversed. 6785// D-register versions. 6786def : NEONInstAlias<"vclt${p}.s8 $Dd, $Dn, $Dm", 6787 (VCGTsv8i8 DPR:$Dd, DPR:$Dm, DPR:$Dn, pred:$p)>; 6788def : NEONInstAlias<"vclt${p}.s16 $Dd, $Dn, $Dm", 6789 (VCGTsv4i16 DPR:$Dd, DPR:$Dm, DPR:$Dn, pred:$p)>; 6790def : NEONInstAlias<"vclt${p}.s32 $Dd, $Dn, $Dm", 6791 (VCGTsv2i32 DPR:$Dd, DPR:$Dm, DPR:$Dn, pred:$p)>; 6792def : NEONInstAlias<"vclt${p}.u8 $Dd, $Dn, $Dm", 6793 (VCGTuv8i8 DPR:$Dd, DPR:$Dm, DPR:$Dn, pred:$p)>; 6794def : NEONInstAlias<"vclt${p}.u16 $Dd, $Dn, $Dm", 6795 (VCGTuv4i16 DPR:$Dd, DPR:$Dm, DPR:$Dn, pred:$p)>; 6796def : NEONInstAlias<"vclt${p}.u32 $Dd, $Dn, $Dm", 6797 (VCGTuv2i32 DPR:$Dd, DPR:$Dm, DPR:$Dn, pred:$p)>; 6798def : NEONInstAlias<"vclt${p}.f32 $Dd, $Dn, $Dm", 6799 (VCGTfd DPR:$Dd, DPR:$Dm, DPR:$Dn, pred:$p)>; 6800// Q-register versions. 6801def : NEONInstAlias<"vclt${p}.s8 $Qd, $Qn, $Qm", 6802 (VCGTsv16i8 QPR:$Qd, QPR:$Qm, QPR:$Qn, pred:$p)>; 6803def : NEONInstAlias<"vclt${p}.s16 $Qd, $Qn, $Qm", 6804 (VCGTsv8i16 QPR:$Qd, QPR:$Qm, QPR:$Qn, pred:$p)>; 6805def : NEONInstAlias<"vclt${p}.s32 $Qd, $Qn, $Qm", 6806 (VCGTsv4i32 QPR:$Qd, QPR:$Qm, QPR:$Qn, pred:$p)>; 6807def : NEONInstAlias<"vclt${p}.u8 $Qd, $Qn, $Qm", 6808 (VCGTuv16i8 QPR:$Qd, QPR:$Qm, QPR:$Qn, pred:$p)>; 6809def : NEONInstAlias<"vclt${p}.u16 $Qd, $Qn, $Qm", 6810 (VCGTuv8i16 QPR:$Qd, QPR:$Qm, QPR:$Qn, pred:$p)>; 6811def : NEONInstAlias<"vclt${p}.u32 $Qd, $Qn, $Qm", 6812 (VCGTuv4i32 QPR:$Qd, QPR:$Qm, QPR:$Qn, pred:$p)>; 6813def : NEONInstAlias<"vclt${p}.f32 $Qd, $Qn, $Qm", 6814 (VCGTfq QPR:$Qd, QPR:$Qm, QPR:$Qn, pred:$p)>; 6815 6816// Two-operand variants for VEXT 6817def : NEONInstAlias<"vext${p}.8 $Vdn, $Vm, $imm", 6818 (VEXTd8 DPR:$Vdn, DPR:$Vdn, DPR:$Vm, imm0_7:$imm, pred:$p)>; 6819def : NEONInstAlias<"vext${p}.16 $Vdn, $Vm, $imm", 6820 (VEXTd16 DPR:$Vdn, DPR:$Vdn, DPR:$Vm, imm0_3:$imm, pred:$p)>; 6821def : NEONInstAlias<"vext${p}.32 $Vdn, $Vm, $imm", 6822 (VEXTd32 DPR:$Vdn, DPR:$Vdn, DPR:$Vm, imm0_1:$imm, pred:$p)>; 6823 6824def : NEONInstAlias<"vext${p}.8 $Vdn, $Vm, $imm", 6825 (VEXTq8 QPR:$Vdn, QPR:$Vdn, QPR:$Vm, imm0_15:$imm, pred:$p)>; 6826def : NEONInstAlias<"vext${p}.16 $Vdn, $Vm, $imm", 6827 (VEXTq16 QPR:$Vdn, QPR:$Vdn, QPR:$Vm, imm0_7:$imm, pred:$p)>; 6828def : NEONInstAlias<"vext${p}.32 $Vdn, $Vm, $imm", 6829 (VEXTq32 QPR:$Vdn, QPR:$Vdn, QPR:$Vm, imm0_3:$imm, pred:$p)>; 6830def : NEONInstAlias<"vext${p}.64 $Vdn, $Vm, $imm", 6831 (VEXTq64 QPR:$Vdn, QPR:$Vdn, QPR:$Vm, imm0_1:$imm, pred:$p)>; 6832 6833// Two-operand variants for VQDMULH 6834def : NEONInstAlias<"vqdmulh${p}.s16 $Vdn, $Vm", 6835 (VQDMULHv4i16 DPR:$Vdn, DPR:$Vdn, DPR:$Vm, pred:$p)>; 6836def : NEONInstAlias<"vqdmulh${p}.s32 $Vdn, $Vm", 6837 (VQDMULHv2i32 DPR:$Vdn, DPR:$Vdn, DPR:$Vm, pred:$p)>; 6838 6839def : NEONInstAlias<"vqdmulh${p}.s16 $Vdn, $Vm", 6840 (VQDMULHv8i16 QPR:$Vdn, QPR:$Vdn, QPR:$Vm, pred:$p)>; 6841def : NEONInstAlias<"vqdmulh${p}.s32 $Vdn, $Vm", 6842 (VQDMULHv4i32 QPR:$Vdn, QPR:$Vdn, QPR:$Vm, pred:$p)>; 6843 6844// Two-operand variants for VMAX. 6845def : NEONInstAlias<"vmax${p}.s8 $Vdn, $Vm", 6846 (VMAXsv8i8 DPR:$Vdn, DPR:$Vdn, DPR:$Vm, pred:$p)>; 6847def : NEONInstAlias<"vmax${p}.s16 $Vdn, $Vm", 6848 (VMAXsv4i16 DPR:$Vdn, DPR:$Vdn, DPR:$Vm, pred:$p)>; 6849def : NEONInstAlias<"vmax${p}.s32 $Vdn, $Vm", 6850 (VMAXsv2i32 DPR:$Vdn, DPR:$Vdn, DPR:$Vm, pred:$p)>; 6851def : NEONInstAlias<"vmax${p}.u8 $Vdn, $Vm", 6852 (VMAXuv8i8 DPR:$Vdn, DPR:$Vdn, DPR:$Vm, pred:$p)>; 6853def : NEONInstAlias<"vmax${p}.u16 $Vdn, $Vm", 6854 (VMAXuv4i16 DPR:$Vdn, DPR:$Vdn, DPR:$Vm, pred:$p)>; 6855def : NEONInstAlias<"vmax${p}.u32 $Vdn, $Vm", 6856 (VMAXuv2i32 DPR:$Vdn, DPR:$Vdn, DPR:$Vm, pred:$p)>; 6857def : NEONInstAlias<"vmax${p}.f32 $Vdn, $Vm", 6858 (VMAXfd DPR:$Vdn, DPR:$Vdn, DPR:$Vm, pred:$p)>; 6859 6860def : NEONInstAlias<"vmax${p}.s8 $Vdn, $Vm", 6861 (VMAXsv16i8 QPR:$Vdn, QPR:$Vdn, QPR:$Vm, pred:$p)>; 6862def : NEONInstAlias<"vmax${p}.s16 $Vdn, $Vm", 6863 (VMAXsv8i16 QPR:$Vdn, QPR:$Vdn, QPR:$Vm, pred:$p)>; 6864def : NEONInstAlias<"vmax${p}.s32 $Vdn, $Vm", 6865 (VMAXsv4i32 QPR:$Vdn, QPR:$Vdn, QPR:$Vm, pred:$p)>; 6866def : NEONInstAlias<"vmax${p}.u8 $Vdn, $Vm", 6867 (VMAXuv16i8 QPR:$Vdn, QPR:$Vdn, QPR:$Vm, pred:$p)>; 6868def : NEONInstAlias<"vmax${p}.u16 $Vdn, $Vm", 6869 (VMAXuv8i16 QPR:$Vdn, QPR:$Vdn, QPR:$Vm, pred:$p)>; 6870def : NEONInstAlias<"vmax${p}.u32 $Vdn, $Vm", 6871 (VMAXuv4i32 QPR:$Vdn, QPR:$Vdn, QPR:$Vm, pred:$p)>; 6872def : NEONInstAlias<"vmax${p}.f32 $Vdn, $Vm", 6873 (VMAXfq QPR:$Vdn, QPR:$Vdn, QPR:$Vm, pred:$p)>; 6874 6875// Two-operand variants for VMIN. 6876def : NEONInstAlias<"vmin${p}.s8 $Vdn, $Vm", 6877 (VMINsv8i8 DPR:$Vdn, DPR:$Vdn, DPR:$Vm, pred:$p)>; 6878def : NEONInstAlias<"vmin${p}.s16 $Vdn, $Vm", 6879 (VMINsv4i16 DPR:$Vdn, DPR:$Vdn, DPR:$Vm, pred:$p)>; 6880def : NEONInstAlias<"vmin${p}.s32 $Vdn, $Vm", 6881 (VMINsv2i32 DPR:$Vdn, DPR:$Vdn, DPR:$Vm, pred:$p)>; 6882def : NEONInstAlias<"vmin${p}.u8 $Vdn, $Vm", 6883 (VMINuv8i8 DPR:$Vdn, DPR:$Vdn, DPR:$Vm, pred:$p)>; 6884def : NEONInstAlias<"vmin${p}.u16 $Vdn, $Vm", 6885 (VMINuv4i16 DPR:$Vdn, DPR:$Vdn, DPR:$Vm, pred:$p)>; 6886def : NEONInstAlias<"vmin${p}.u32 $Vdn, $Vm", 6887 (VMINuv2i32 DPR:$Vdn, DPR:$Vdn, DPR:$Vm, pred:$p)>; 6888def : NEONInstAlias<"vmin${p}.f32 $Vdn, $Vm", 6889 (VMINfd DPR:$Vdn, DPR:$Vdn, DPR:$Vm, pred:$p)>; 6890 6891def : NEONInstAlias<"vmin${p}.s8 $Vdn, $Vm", 6892 (VMINsv16i8 QPR:$Vdn, QPR:$Vdn, QPR:$Vm, pred:$p)>; 6893def : NEONInstAlias<"vmin${p}.s16 $Vdn, $Vm", 6894 (VMINsv8i16 QPR:$Vdn, QPR:$Vdn, QPR:$Vm, pred:$p)>; 6895def : NEONInstAlias<"vmin${p}.s32 $Vdn, $Vm", 6896 (VMINsv4i32 QPR:$Vdn, QPR:$Vdn, QPR:$Vm, pred:$p)>; 6897def : NEONInstAlias<"vmin${p}.u8 $Vdn, $Vm", 6898 (VMINuv16i8 QPR:$Vdn, QPR:$Vdn, QPR:$Vm, pred:$p)>; 6899def : NEONInstAlias<"vmin${p}.u16 $Vdn, $Vm", 6900 (VMINuv8i16 QPR:$Vdn, QPR:$Vdn, QPR:$Vm, pred:$p)>; 6901def : NEONInstAlias<"vmin${p}.u32 $Vdn, $Vm", 6902 (VMINuv4i32 QPR:$Vdn, QPR:$Vdn, QPR:$Vm, pred:$p)>; 6903def : NEONInstAlias<"vmin${p}.f32 $Vdn, $Vm", 6904 (VMINfq QPR:$Vdn, QPR:$Vdn, QPR:$Vm, pred:$p)>; 6905 6906// Two-operand variants for VPADD. 6907def : NEONInstAlias<"vpadd${p}.i8 $Vdn, $Vm", 6908 (VPADDi8 DPR:$Vdn, DPR:$Vdn, DPR:$Vm, pred:$p)>; 6909def : NEONInstAlias<"vpadd${p}.i16 $Vdn, $Vm", 6910 (VPADDi16 DPR:$Vdn, DPR:$Vdn, DPR:$Vm, pred:$p)>; 6911def : NEONInstAlias<"vpadd${p}.i32 $Vdn, $Vm", 6912 (VPADDi32 DPR:$Vdn, DPR:$Vdn, DPR:$Vm, pred:$p)>; 6913def : NEONInstAlias<"vpadd${p}.f32 $Vdn, $Vm", 6914 (VPADDf DPR:$Vdn, DPR:$Vdn, DPR:$Vm, pred:$p)>; 6915 6916// Two-operand variants for VSRA. 6917 // Signed. 6918def : NEONInstAlias<"vsra${p}.s8 $Vdm, $imm", 6919 (VSRAsv8i8 DPR:$Vdm, DPR:$Vdm, shr_imm8:$imm, pred:$p)>; 6920def : NEONInstAlias<"vsra${p}.s16 $Vdm, $imm", 6921 (VSRAsv4i16 DPR:$Vdm, DPR:$Vdm, shr_imm16:$imm, pred:$p)>; 6922def : NEONInstAlias<"vsra${p}.s32 $Vdm, $imm", 6923 (VSRAsv2i32 DPR:$Vdm, DPR:$Vdm, shr_imm32:$imm, pred:$p)>; 6924def : NEONInstAlias<"vsra${p}.s64 $Vdm, $imm", 6925 (VSRAsv1i64 DPR:$Vdm, DPR:$Vdm, shr_imm64:$imm, pred:$p)>; 6926 6927def : NEONInstAlias<"vsra${p}.s8 $Vdm, $imm", 6928 (VSRAsv16i8 QPR:$Vdm, QPR:$Vdm, shr_imm8:$imm, pred:$p)>; 6929def : NEONInstAlias<"vsra${p}.s16 $Vdm, $imm", 6930 (VSRAsv8i16 QPR:$Vdm, QPR:$Vdm, shr_imm16:$imm, pred:$p)>; 6931def : NEONInstAlias<"vsra${p}.s32 $Vdm, $imm", 6932 (VSRAsv4i32 QPR:$Vdm, QPR:$Vdm, shr_imm32:$imm, pred:$p)>; 6933def : NEONInstAlias<"vsra${p}.s64 $Vdm, $imm", 6934 (VSRAsv2i64 QPR:$Vdm, QPR:$Vdm, shr_imm64:$imm, pred:$p)>; 6935 6936 // Unsigned. 6937def : NEONInstAlias<"vsra${p}.u8 $Vdm, $imm", 6938 (VSRAuv8i8 DPR:$Vdm, DPR:$Vdm, shr_imm8:$imm, pred:$p)>; 6939def : NEONInstAlias<"vsra${p}.u16 $Vdm, $imm", 6940 (VSRAuv4i16 DPR:$Vdm, DPR:$Vdm, shr_imm16:$imm, pred:$p)>; 6941def : NEONInstAlias<"vsra${p}.u32 $Vdm, $imm", 6942 (VSRAuv2i32 DPR:$Vdm, DPR:$Vdm, shr_imm32:$imm, pred:$p)>; 6943def : NEONInstAlias<"vsra${p}.u64 $Vdm, $imm", 6944 (VSRAuv1i64 DPR:$Vdm, DPR:$Vdm, shr_imm64:$imm, pred:$p)>; 6945 6946def : NEONInstAlias<"vsra${p}.u8 $Vdm, $imm", 6947 (VSRAuv16i8 QPR:$Vdm, QPR:$Vdm, shr_imm8:$imm, pred:$p)>; 6948def : NEONInstAlias<"vsra${p}.u16 $Vdm, $imm", 6949 (VSRAuv8i16 QPR:$Vdm, QPR:$Vdm, shr_imm16:$imm, pred:$p)>; 6950def : NEONInstAlias<"vsra${p}.u32 $Vdm, $imm", 6951 (VSRAuv4i32 QPR:$Vdm, QPR:$Vdm, shr_imm32:$imm, pred:$p)>; 6952def : NEONInstAlias<"vsra${p}.u64 $Vdm, $imm", 6953 (VSRAuv2i64 QPR:$Vdm, QPR:$Vdm, shr_imm64:$imm, pred:$p)>; 6954 6955// Two-operand variants for VSRI. 6956def : NEONInstAlias<"vsri${p}.8 $Vdm, $imm", 6957 (VSRIv8i8 DPR:$Vdm, DPR:$Vdm, shr_imm8:$imm, pred:$p)>; 6958def : NEONInstAlias<"vsri${p}.16 $Vdm, $imm", 6959 (VSRIv4i16 DPR:$Vdm, DPR:$Vdm, shr_imm16:$imm, pred:$p)>; 6960def : NEONInstAlias<"vsri${p}.32 $Vdm, $imm", 6961 (VSRIv2i32 DPR:$Vdm, DPR:$Vdm, shr_imm32:$imm, pred:$p)>; 6962def : NEONInstAlias<"vsri${p}.64 $Vdm, $imm", 6963 (VSRIv1i64 DPR:$Vdm, DPR:$Vdm, shr_imm64:$imm, pred:$p)>; 6964 6965def : NEONInstAlias<"vsri${p}.8 $Vdm, $imm", 6966 (VSRIv16i8 QPR:$Vdm, QPR:$Vdm, shr_imm8:$imm, pred:$p)>; 6967def : NEONInstAlias<"vsri${p}.16 $Vdm, $imm", 6968 (VSRIv8i16 QPR:$Vdm, QPR:$Vdm, shr_imm16:$imm, pred:$p)>; 6969def : NEONInstAlias<"vsri${p}.32 $Vdm, $imm", 6970 (VSRIv4i32 QPR:$Vdm, QPR:$Vdm, shr_imm32:$imm, pred:$p)>; 6971def : NEONInstAlias<"vsri${p}.64 $Vdm, $imm", 6972 (VSRIv2i64 QPR:$Vdm, QPR:$Vdm, shr_imm64:$imm, pred:$p)>; 6973 6974// Two-operand variants for VSLI. 6975def : NEONInstAlias<"vsli${p}.8 $Vdm, $imm", 6976 (VSLIv8i8 DPR:$Vdm, DPR:$Vdm, shr_imm8:$imm, pred:$p)>; 6977def : NEONInstAlias<"vsli${p}.16 $Vdm, $imm", 6978 (VSLIv4i16 DPR:$Vdm, DPR:$Vdm, shr_imm16:$imm, pred:$p)>; 6979def : NEONInstAlias<"vsli${p}.32 $Vdm, $imm", 6980 (VSLIv2i32 DPR:$Vdm, DPR:$Vdm, shr_imm32:$imm, pred:$p)>; 6981def : NEONInstAlias<"vsli${p}.64 $Vdm, $imm", 6982 (VSLIv1i64 DPR:$Vdm, DPR:$Vdm, shr_imm64:$imm, pred:$p)>; 6983 6984def : NEONInstAlias<"vsli${p}.8 $Vdm, $imm", 6985 (VSLIv16i8 QPR:$Vdm, QPR:$Vdm, shr_imm8:$imm, pred:$p)>; 6986def : NEONInstAlias<"vsli${p}.16 $Vdm, $imm", 6987 (VSLIv8i16 QPR:$Vdm, QPR:$Vdm, shr_imm16:$imm, pred:$p)>; 6988def : NEONInstAlias<"vsli${p}.32 $Vdm, $imm", 6989 (VSLIv4i32 QPR:$Vdm, QPR:$Vdm, shr_imm32:$imm, pred:$p)>; 6990def : NEONInstAlias<"vsli${p}.64 $Vdm, $imm", 6991 (VSLIv2i64 QPR:$Vdm, QPR:$Vdm, shr_imm64:$imm, pred:$p)>; 6992 6993// VSWP allows, but does not require, a type suffix. 6994defm : NEONDTAnyInstAlias<"vswp${p}", "$Vd, $Vm", 6995 (VSWPd DPR:$Vd, DPR:$Vm, pred:$p)>; 6996defm : NEONDTAnyInstAlias<"vswp${p}", "$Vd, $Vm", 6997 (VSWPq QPR:$Vd, QPR:$Vm, pred:$p)>; 6998 6999// VBIF, VBIT, and VBSL allow, but do not require, a type suffix. 7000defm : NEONDTAnyInstAlias<"vbif${p}", "$Vd, $Vn, $Vm", 7001 (VBIFd DPR:$Vd, DPR:$Vn, DPR:$Vm, pred:$p)>; 7002defm : NEONDTAnyInstAlias<"vbit${p}", "$Vd, $Vn, $Vm", 7003 (VBITd DPR:$Vd, DPR:$Vn, DPR:$Vm, pred:$p)>; 7004defm : NEONDTAnyInstAlias<"vbsl${p}", "$Vd, $Vn, $Vm", 7005 (VBSLd DPR:$Vd, DPR:$Vn, DPR:$Vm, pred:$p)>; 7006defm : NEONDTAnyInstAlias<"vbif${p}", "$Vd, $Vn, $Vm", 7007 (VBIFq QPR:$Vd, QPR:$Vn, QPR:$Vm, pred:$p)>; 7008defm : NEONDTAnyInstAlias<"vbit${p}", "$Vd, $Vn, $Vm", 7009 (VBITq QPR:$Vd, QPR:$Vn, QPR:$Vm, pred:$p)>; 7010defm : NEONDTAnyInstAlias<"vbsl${p}", "$Vd, $Vn, $Vm", 7011 (VBSLq QPR:$Vd, QPR:$Vn, QPR:$Vm, pred:$p)>; 7012 7013// "vmov Rd, #-imm" can be handled via "vmvn". 7014def : NEONInstAlias<"vmov${p}.i32 $Vd, $imm", 7015 (VMVNv2i32 DPR:$Vd, nImmVMOVI32Neg:$imm, pred:$p)>; 7016def : NEONInstAlias<"vmov${p}.i32 $Vd, $imm", 7017 (VMVNv4i32 QPR:$Vd, nImmVMOVI32Neg:$imm, pred:$p)>; 7018def : NEONInstAlias<"vmvn${p}.i32 $Vd, $imm", 7019 (VMOVv2i32 DPR:$Vd, nImmVMOVI32Neg:$imm, pred:$p)>; 7020def : NEONInstAlias<"vmvn${p}.i32 $Vd, $imm", 7021 (VMOVv4i32 QPR:$Vd, nImmVMOVI32Neg:$imm, pred:$p)>; 7022 7023// 'gas' compatibility aliases for quad-word instructions. Strictly speaking, 7024// these should restrict to just the Q register variants, but the register 7025// classes are enough to match correctly regardless, so we keep it simple 7026// and just use MnemonicAlias. 7027def : NEONMnemonicAlias<"vbicq", "vbic">; 7028def : NEONMnemonicAlias<"vandq", "vand">; 7029def : NEONMnemonicAlias<"veorq", "veor">; 7030def : NEONMnemonicAlias<"vorrq", "vorr">; 7031 7032def : NEONMnemonicAlias<"vmovq", "vmov">; 7033def : NEONMnemonicAlias<"vmvnq", "vmvn">; 7034// Explicit versions for floating point so that the FPImm variants get 7035// handled early. The parser gets confused otherwise. 7036def : NEONMnemonicAlias<"vmovq.f32", "vmov.f32">; 7037def : NEONMnemonicAlias<"vmovq.f64", "vmov.f64">; 7038 7039def : NEONMnemonicAlias<"vaddq", "vadd">; 7040def : NEONMnemonicAlias<"vsubq", "vsub">; 7041 7042def : NEONMnemonicAlias<"vminq", "vmin">; 7043def : NEONMnemonicAlias<"vmaxq", "vmax">; 7044 7045def : NEONMnemonicAlias<"vmulq", "vmul">; 7046 7047def : NEONMnemonicAlias<"vabsq", "vabs">; 7048 7049def : NEONMnemonicAlias<"vshlq", "vshl">; 7050def : NEONMnemonicAlias<"vshrq", "vshr">; 7051 7052def : NEONMnemonicAlias<"vcvtq", "vcvt">; 7053 7054def : NEONMnemonicAlias<"vcleq", "vcle">; 7055def : NEONMnemonicAlias<"vceqq", "vceq">; 7056 7057def : NEONMnemonicAlias<"vzipq", "vzip">; 7058def : NEONMnemonicAlias<"vswpq", "vswp">; 7059 7060def : NEONMnemonicAlias<"vrecpeq.f32", "vrecpe.f32">; 7061def : NEONMnemonicAlias<"vrecpeq.u32", "vrecpe.u32">; 7062 7063 7064// Alias for loading floating point immediates that aren't representable 7065// using the vmov.f32 encoding but the bitpattern is representable using 7066// the .i32 encoding. 7067def : NEONInstAlias<"vmov${p}.f32 $Vd, $imm", 7068 (VMOVv4i32 QPR:$Vd, nImmVMOVI32:$imm, pred:$p)>; 7069def : NEONInstAlias<"vmov${p}.f32 $Vd, $imm", 7070 (VMOVv2i32 DPR:$Vd, nImmVMOVI32:$imm, pred:$p)>; 7071